MSI MS-7702 Schematics rev1.0

1

Cover Sheet
BLOCK DIAGRAM

Clock Distribution
PWRGD&RESET Map
GPIO/MSIC TABLE
VRM Intersil 6328 3+1 PHASE
AMD FM1

DDR3 DIMM CH-A

DDR3 DIMM CH-B
DDR REF POWER AND CAPS
EMI Reserved

AMD HUDSON D2/3

A A

SWITCH/HDMI CONN.

TRAVIS & VGA CONN.
SATA//eSATA/PS2/ FAN
LAN RTL8111E/81105E
SUPER I/O NCT66776F
ACPI UPI & SYS POWER
FCH CORE & DDR POWER
Azalia CODEC ALC892/662
USB 2.0/3.0CONN.
USB POWER/DISCHARGE

1
2
3 Power Deliver Chart
4
5
6
7
8 ~ 11
12
13
14
15
16~20
21
22
23
24
25
26
27
28
29
30

(MS-7702L2 Ver:1.0)

CPU:

AMD FM1(Llano uPGA FAMILIES)

System Chipset:

AMD - Hudson D3/D2

On Board Chipset:

CLOCK GEN --FCH internal clock gen
LPC Super I/O --NCT6776F
LAN-Realtek 8111E/8105E

Azalia CODEC - Realtek ALC892/662/888/

Main Memory:

DDR III * 4 (max 32G)

Expansion Slots:

PCI Express X16 Slot * 1
PCI Express X1 Slot * 3
PCI Express X1 Slot *1 for front USB3.0

VRM

Controller - Intersil 6328 3+1 Phase

mATX: 244mm * 244mm

FUSION

PCI EXPRESS X16 SLOT
PCIE X1 SLOTs
ATX & Front Panel
Auto BOM Manual
MINI PCIE CONN,

31
32
33
34
35

MICRO-START INT'L CO.,LTD.

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Title

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COVER SHEET

COVER SHEET

COVER SHEET

Size Document Number Rev

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Custom

Custom

Custom

Date: Sheet

Date: Sheet

1

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

FUSION 1.0

FUSION 1.0

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135Friday, April 29, 2011

135Friday, April 29, 2011

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FUSION BLOCK DIAGRAM

D D

VGA CONNECTOR

22

VGA

HUDSON D3

18

VGA MAIN LINK

HDMI CON

PCIE GFX x16

C C

PCIE INTERFACE

10/100/Giga bit
ETHERNET
8105EL/8111EL

B B

24

PCIE INTERFACE

DP 1

DP0

21

PCIE x16

30

USB
REAR

/HDR

USB
REAR

29

Only D3 support USB3.0

USB 2.0

USB 3.0

FM1

8~11

UMI

HUDSON D3/D2

DDRIII 1333~1866

DDRIII 1333~1866

AZALIA

SERIAL ATA 3.0

CHA

CHB

UNBUFFERED
DDRIII DIMM1 2

UNBUFFERED
DDRIII DIMM3 4

ALC662/888/892

i-SATA [4:1]

23

e-SATA 5

23

12

13

28

CPU CORE POWER
NB CORE POWERACPI CONTROLLER
Intersil ISL6323
Intersil ISL6612A

PCIE x1 SLOT1,2,3

7

31

16~20

SPI Bus

SPI ROM 16M

18

26

CPU VDDP Power
CPU VDDR Power
CPU VDDA Power
DUAL POWER

A A

DDR3 DRAM POWER
FCH CORE POWER

ATX CON

5

26

27

32

4

SUPER I/O NCT66776F

KBD
MOUSE

3

SERIAL
PORT

23 25

25

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Title

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BLOCK Diagram

BLOCK Diagram

BLOCK Diagram

Size Document Number Rev

Size Document Number Rev

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Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

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FUSION 1.0

FUSION 1.0

FUSION 1.0

235Wednesday, August 17, 2011

235Wednesday, August 17, 2011

235Wednesday, August 17, 2011

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Power Deliver Chart

2.5V Shunt
Regulator

VRM SW

D D

ATX P/S WITH 1A STBY CURRENT

5V

5VSB

+/-5%

+/-5%

C C

3.3V
+/-5%

12V
+/-5%

-12V
+/-5%

CPU
PW
12V
+/-5%

5VDIMM Linear
REGULATOR

VCC5_SB FET
REGULATOR

VCC3_WAKE Linear
REGULATOR

1.5V VDD SW
REGULATOR

1.1V VCCP SW
REGULATOR

VCC3_SB SW
REGULATOR

VCC5_SB

REGUALTOR

VDDA25 (S0, S1)

VCCP (S0, S1) / VCC_NB (S0, S1)

1.2V VDDR
REGULATOR

1.2V VDDP
REGULATOR

0.75V VTT_DDR
REGULATOR

CPU_VDDR (S0, S1)

CPU_VDDP (S0, S1)

VCC_DDR (S0, S1, S3)

DDRIII DIMM X4

VDD MEM
VTT_DDR

NB_VCC1P1 (S0, S1)

VCC3 (S0, S1)

VCC3_SB (S0, S1, S3, S5)

1.1V_SB Linear
REGULATOR

+1.1VDUAL(S0,S1,S3,S5)

15A
2 A

OPTION

0R

AMD FM1 CPU

VDDA

2.5V(1.8~2.7V)
VDDCORE

0.8-2V
VDDNBCORE

1.2V
CPU_VDDR

1.2V

CPU_VDDP

1.2V

DDR3 MEM I/F 1.5V
VCC_DDR

0.8~2.3V TBD A

HUDSON 2/3

VDDPL_11_DAC

VDDAN_11_ML

VDDCR_11

VDDAN_11_SATA

VDDAN_11_CLK

VDDAN_11_PCIE

VDDIO_33_PCIGP 3.3V
(S0, S1)
VDDPL_33_*_RUN

VDDPL_33_*_ALW

VDDIO_33_GBE_S

VDDAN_33_USB_S

VDDXL_33_S

VDDIO_33_S

VDDCR/AN_11_SUSB_S

VDDCR/AN_11_USB_S

VDDCR_11_GBE_S

VDDCR_11_S

100 mA
500 mA
700 mA
400 mA
900 mA

300 mA
320 mA

34 mA
1 mA
130 mA
6 mA
30 mA

500 mA
52 mA
100 mA

100 mA

0.5A
120A

20A

5A

5A

20 mA

B B

VCC3 (S0, S1)

+5VA Linear
REGULATOR

SVCC Linear
REGULATOR

SVCC(S0,S3)

+5VA (S0, S1)

AUDIO CODEC

3.3V CORE

5V ANALOG

0.1A

0.1A

SUPER I/O

+3.3V (S0, S1)

VCC3_WAKE (S0, S1, S3, S5)

+3.3VDUAL (S3)

0.01A

0.01A

VCC3_WAKE (S0, S1, S3, S5)

A A

5

COM Port

-12V

0.1A

X1 PCIE per

3.3V
12V

3.3Vaux

3.0A

0.5A

0.1A

4

X16 PCIE per

3.3V
12V

3.3VDual

3.0A

5.5A

0.3A

USB X6 FR

VDD
5VDual

3.8A

USB X4 RL 2XPS/2

5VDual

VDD

0.5A

5VDual

2.0A

3

ENTHENET

3.3V 1.05V

70mA

300mA

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Power Deliver Chart

Power Deliver Chart

Power Deliver Chart

FUSION 1.0

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FUSION 1.0

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335Friday, April 29, 2011

335Friday, April 29, 2011

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INTERNAL CLOCK MODE

D D

CH A CH B

DIMM1

DIMM2

DIMM3

DIMM4

AMD
HUDSON-D3/D2

MEM_MA_CLK_H0/L0

MEM_MA_CLK_H3/L3

MEM_MA_CLK_H2/L2

C C

MEM_MA_CLK_H1/L1

AMD

FM1 APU

B B

MEM_MB_CLK_H0/L0

MEM_MB_CLK_H3/L3

MEM_MB_CLK_H1/L1

MEM_MB_CLK_H2/L2

APU_CLKP/N

DISP_CLKP/N

FCH_APU_CLKP

FCH_DISP_CLKP
100MHZ (NO SPREAD)

USBCLK

14M_25M_48M_OSC

25M_X2

SATA_X1

25M_X1

25MHZ RTC CLOCK

FOR SATA DNI

25M Hz

32K_X1

SATA_X2

32.768K Hz

PCICLK0

PCICLK2

PCICLK2

PCICLK3

PCICLK4

LPCCLK0
LPCCLK1

RTCCLK

AZ_BITCLK

SPI_CLK

FCH_GFX_CLKP/N

FCH_GPP_CLK0P/N

FCH_GPP_CLK1P/N

FCH_GPP_CLK2P/N

FCH_GPP_CLK3P/N

FCH_GPP_CLK4P/N

32K_X2

PCICLK1

33MHZ

PCI_CLK4

PCI_CLK3PCI_CLK2

33MHZ

LPC_CLK0

LPCCLK1

33MHZ

AZ_BIT_CLK

24MHZ

SPI_CLK

xxHZ

PE16_GXF_CLK/PE16_GXF_CLK#

100MHZ

PE1_GPP_CLK0/PE1_GPP_CLK0#

100MHZ

PE1_GPP_CLK1/PE1_GPP_CLK1#

100MHZ

PE1_GPP_CLK2/PE1_GPP_CLK2#

100MHZ

PE_LAN_CLK/PE_LAN_CLK#

100MHZ

SIO NCT6776F

STRAPS SETTING,

UNUSED CLOCKS

STRAPS SETTING,

RESERVE TP

HD AUDIO

SPI ROM & HEADER

PCIE GFX SLOT (FM1, 16 LANES)

PCIE GPP SLOT1 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT2 (HUDSON-D3, 1 LANE)

PCIE GPP SLOT3(HUDSON-D3, 1 LANE)

PCIE LAN (FM1, 1 LANE)

reserve LAN_CLKREQ#

PCIEX16 SLOT

PCIE X1 SLOT

PCIE X1 SLOT

PCIE X1 SLOT

PCIE LAN

PCIE LAN RTL8111E

25M Hz

A A

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Clock Distribution

Clock Distribution

Clock Distribution

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C

C

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FUSION 1.0

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FM1

PWROK(Pin AG11)

4

PWRGD MAP

3

2

1

POWER ON SEQUENCE

HUDSON D3/D2

APU_PG(Pin E26)

D D

PWR_BTN#(Pin J4)

SLP_S3#(Pin T3)

SLP_S5#(Pin W2)

APU_PWRGD

FCH_PWRGDPWR_GD(Pin N7)

NCT 6776F

SLP_S5#

SLP_S5#(Pin 84)

SUSB#(Pin 64)SLP_S3#

PSOUT# (Pin 60)PSOUT#

ATX_POWER

U16

NCP1587

VRM U5

ISL6328CR

VDDPWRGD(Pin 34)

U32

NCP1587

U41

*

PS_ON#

FCH_PWRGD

CPU_VDD

VRM_PWRGD

U30

NCP102

Pin16

ATX_PWROK U23 (UP7501) 5VDIMM

Pin8

F_PANEL1PSIN#

VCC_DDR

CPU_VDDP
CPU_VDDR

NB_VCC1P1

*

U54 (UP7704) VDDA_25

MEANS OPTION

PSON# (Pin 63)

PSIN# (Pin 61)

C C

ATX_PWROK

SLP_S5#

ATX_PWROK
APU_FM1R1
VCC_DDR

VRM_PWRGD

B B

ATX_PWROK
NB_VCC1P1
FP_RST#
SLP_S3#

D41

CPU_VDDP_VDDR_EN

NBCORE_EN

D40

DDR_EN

VCORE_EN

APU_PWRGD

FCH_PWRGD_R

EN(Pin 25)

PWROK(Pin 35)

RESET MAP

FM1

RESET_L(Pin AJ13)

HUDSON D3/D2

CLK GEN

Reserve TP
Reserve TP

PCIE_RST#(Pin AE2)

A_RST#(Pin AD5)Super IO

PCIE_RST2#(Pin AB6)
PCIRST#(Pin AB5)

5

PCIE 16X slot
PCIE 1X slot 1
PCIE 1X slot 2
PCIE LAN

A A

LPC debug

ICS-9VRS4818

APU_RST#(Pin F26)

SYS_RESET#(Pin U4)

FP_RST#

APU_RST#

RESET#(Pin 12)RESET_IN#(Pin 70)

F_PANEL

MICRO-START INT'L CO.,LTD.

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MICRO-START INT'L CO.,LTD.

PWRGD/RESET MAP

PWRGD/RESET MAP

PWRGD/RESET MAP

FUSION 1.0

FUSION 1.0

FUSION 1.0

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DDR DIMM Config.

SIO NCT6776F GPIO Config

D D

50 GP60 VSB

78 GP36 VSB SIO_VDUAL_EN

GPIO Power Rail Function descriptionPin

GP4638 VSB SIO_WAKE

YLW_LED/GP4539 VSB

GRN_LED/GP4440 VSB PWR_LED

GP6742 VSB

GP6544

GP6445 VSB

GP6347 VSB

GP6248 VSB

GP6149 VSB

VSB

SUS_LED

USB_EN

MB_ID0

MB_ID1

MB_ID2

COM_GPIO2

CHASSIS_ID1

CHASSIS_ID2

Comment

OD

GPI

GPI

GPI

GPI

GPI

GPI

reserved

reserved

reserved

reserved

reserved

reserved

DEVICE

DIMM 1

10100000B

CH-A

10100010B A4H

CH-A MEM_MA_CLK_H3/L3

DIMM 3

10100001B

CH-B

DIMM 4

10100011B A6H

CH-B

CLOCKADDRESS

MEM_MA_CLK_H1/L1

A0H

MEM_MA_CLK_H2/L2

MEM_MA_CLK_H0/L0DIMM 2

MEM_MB_CLK_H1/L1

A2H

MEM_MB_CLK_H2/L2

MEM_MB_CLK_H0/L0
MEM_MB_CLK_H3/L3

SMBus TABLE

FCH HUDSON D3/D2GPIO Config

Pin

AJ3

C C

B B

AD22 SATA_ACT#/GPIO67 SATA_LED#:SATA Channel Active

M6

V3 SPI_CLK/GPIO162 SPI Clock

V6 SPI_DI/GPIO164 SPI Data In

V5 SPI_DO/GPIO163 SPI Data Output

T6 SPI_CS1#/GPIO165 SPI Chip Select1#

Y6 SPI_HOLD#/GEVENT9# SPI HOLD#. Assert low to hold the SPI transaction.

J7 USB_OC1#/TDI/GEVENT13# OC#1:USB2.0 port 4,5

P5 USB_OC2#/TCK/GEVENT14#

P5 USB_OC3#/

P6 USB_OC4#/IR_RX0/

T1 OC#5:USB2.0 port 2,3

R8 OC#6:USB2.0 port 0,1

M7 OC#7:USB 3.0 port 2,USB 2.0 port12BLINK/USB_OC7#/

pin Name Function description

AD0/GPIO0 CLEAR_CMOS

IR_LED#/LLB#/GPIO184 MINI_PWRONJ2

TEMPIN3/TALERT#/
GPIO174

ROM_RST#/SPI_WP#/GPIO161V1 SPI write protect (active low)

USB_OC0#/SPI_TPM_CS#/
TRST#/GEVENT12#

AC_PRES/TDO/GEVENT15#

GEVENT16#
USB_OC5#/IR_TX0/
GEVENT17#
USB_OC6#/IR_TX1/
GEVENT6#

GEVENT18#

GPIO[171::173];GPIO[175::182];
GPIO[193::194]

FCH_TALERT#:Thermal Alert.
The FCH can be programmed to generate an
SMI, SCI, or IRQ13 through GPE, or generate an SMI
without GPE in response to the signal’s assertion.

OC#0:USB 3.0 port 3,USB 2.0 port 13T8

OC#2:USB2.0 port 8,9

OC#3:USB 3.0 port 0,USB 2.0 port 10

OC#4:USB 3.0 port 1,USB 2.0 port 11

Configure as one of the following:
10-kΩ 5% pull-up resistor to +3.3V_S5.
10-kΩ 5% pull-down resistor.

SOURCE

DP0_AUXP_C
/DP0_AUXN_C

APU

DP1_AUXP_C
/DP1_AUXN_C

SCLK0/SDATA0

FCH

SCLK1/SDATA1 LAN,PCIE SLOTs,MINI_PCIE

SCLK3/SDATA3 TP

RESET TABLE

SOURCE

PCIE_RST# PCIe 16X,1X,LAN,MINI_PCIE

FCH

FRONT
PANEL

A_RST# SIO,LPC debug
PCIE_RST2# RESERVE TP
LDT_RST# APU
AZ_RST# AZALIA CODEC
DDR3_RST# NC
FC_RST# DEBUG BUS
ROM_RST# NC
FP_RST# FCH,CLOCK GEN

LINKED DEVICESINGLE NAME

HDMI

Hudson D2/3
DP to VGA translator

DIMMs,CLOCK GEN
,SIO

LINKED DEVICESINGLE NAME

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

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GPIO/MSIC TABLE

GPIO/MSIC TABLE

GPIO/MSIC TABLE

FUSION 1.0

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ISL6328/6612A 3+1 Phase

D D

VRM_PWRGD27

COREFB+_R

VCCP

COREFB+10

COREFB-10

C C

CPU_VDDNB

NBCOREFB+10

B B

VRM_PWRGD_R

ATX_PWROK25,26,27,33

APU_FM1R110

VCORE_EN_R25,27

A A

Soft-Start Ramp Rate: TBD mV/us

OCP ~ 160A
Work F=230Khz

VCC5

R5
10KR0402R510KR0402

C16

C16

C1500p50X0402

C1500p50X0402

R22

R22

47.5R1%0402

47.5R1%0402

R13 100R0402R13 100R0402
R14 0R0402R14 0R0402

R23 0R0402R23 0R0402
R24 100R0402R24 100R0402

C110

C110

20.5KR1%0402

20.5KR1%0402

R95

R95
X_47.5R1%0402

X_47.5R1%0402

R96 1.37KR1%0402-HFR96 1.37KR1%0402-HF
R88 100R0402R88 100R0402
R89 0R0402R89 0R0402

VCC5_ISL6328

VCC5_ISL6328
VCC5_ISL6328
VCC5_ISL6328

VCCP

R75

R75
X_1KR0402

X_1KR0402

R76 X_10KR0402R76 X_10KR0402

D11 S-RB751V-40_SOD323-RHD11 S-RB751V-40_SOD323-RH

D10 S-RB751V-40_SOD323-RHD10 S-RB751V-40_SOD323-RH

VCORE_EN_R

VRM_PWRGD_R

C100 X_C0.1u16Y0402C100 X_C0.1u16Y0402

VRM_PWROK

C102 X_C0.1u16Y0402C102 X_C0.1u16Y0402

VCORE_EN

C45 C2.2u6.3X50402C45 C2.2u6.3X50402

0.98V Threshold

VCORE_EN

0.95V Threshold

VRM_PWROK

APU_SVD10
APU_SVC10

R10

R10

X_2.15KR1%0402

X_2.15KR1%0402

R12

R12

2.37KR1%0402

2.37KR1%0402

C17

C17
C2200p50X0402

C2200p50X0402

R21

R21
301R1%0402

301R1%0402

R41R41
R2 0R0402R2 0R0402

C46 C150P50N0402C46 C150P50N0402

R11

R11

4.99KR1%0402

4.99KR1%0402

C47 C0.01U16X0402C47 C0.01U16X0402

VRM_PWRGD_R

C31

C31

C6800P50X0402

C6800P50X0402

APU_PWRGD10,16

C18 X_C0.1u16Y0402C18 X_C0.1u16Y0402

C32

C32
X_C0.1u16Y0402

X_C0.1u16Y0402

R127

R127

34KR1%0402

34KR1%0402

C99 X_C680p50XC99 X_C680p50X

R107

R107

6.04KR1%0402

6.04KR1%0402

C93

C93

C220p50N0402

C220p50N0402

C85 X_C0.1u16Y0402C85 X_C0.1u16Y0402 R140

R60 0R0402R60 0R0402

R20 X_100R0402R20 X_100R0402
R73 X_100R0402R73 X_100R0402
R77 X_100R0402R77 X_100R0402 U25

C73

C73

C0.015u16X0402

C0.015u16X0402

R53

R53

107KR1%0402-RH

107KR1%0402-RH

C108

C108

C0.022u50X

C0.022u50X

Disable APD

R72

R72

10KR1%0402

10KR1%0402

R70

R70

25.5KR1%0402-RH

25.5KR1%0402-RH

C48

C48
X_C0.1u16Y0402

X_C0.1u16Y0402

NBCOREFB+_R

C44

C44

X_C1500p50X0402

X_C1500p50X0402

R78

R78

20KR1%0402

20KR1%0402

VCC5_ISL6328

U5

25

EN

35

PWROK

OD

34

VDDPWRGD

6

SVD

5

SVC

VCORE_COMP

VCORE_COMP

17

R19

R19

X_35.7KR1%0402

X_35.7KR1%0402

C66

C66

C0.1U25X

C0.1U25X

16

15

14

13

19

18

10

1
2

3
8

9
4

COMP
FB

FB_PSI

VSEN

RGND

COMP_NB
FB_NB

VSEN_NB
APD
APA

FS
OFS
DRPCTRL

OCP

VCORE_FB

VRM_PSI

COREFB+_R

COREFB-_R

VDDNB_COMP

VDDNB_COMP
VDDNB_FBNBCOREFB+_R

VRM_APD
VRM_APA

VRM_FS ISEN_NB_R
VRM_OFS
VRM_DRPCTRL

VRM_OCP

VCC5

VRM_PWRGD

DS

C68

C68

Q8

G

X_C0.1u16Y0402

X_C0.1u16Y0402

X_N-2N7002_SOT23Q8X_N-2N7002_SOT23

+12VINVCC5

R74

G

+12VIN

R74
10KR0402

10KR0402

DS

Q13

Q13
N-2N7002_SOT23

N-2N7002_SOT23

DS

G

CHOKE7

CHOKE7

CH-1.1u35A1.7m-RH

CH-1.1u35A1.7m-RH

R81

R81

10.7KR1%0402

10.7KR1%0402

Q14

Q14
N-2N7002_SOT23

N-2N7002_SOT23

1 2

+

+

C334

C334

C10u16Y1206

C10u16Y1206

C340

C340

X_C0.01u25X0402

X_C0.01u25X0402

12

2

1

5

B

ATX_12V

ATX_12V

12V

12V

12V

12V

GND GND

GND GND

PWR-2X2M_natural-RH

PWR-2X2M_natural-RH

5

CE

Q7

4

3

R69

R69
X_10KR0402

X_10KR0402

X_N-SST3904_SOT23Q7X_N-SST3904_SOT23

VCC5

BOTTOM PAD
CONNECT TO GND
Through 8 VIAs

Make sure +12VIN
connector plug in

+

+

12

EC25

EC25

CD270u16SO-RH-2

CD270u16SO-RH-2

4

7

VCC

GND

ISL6328CRU5ISL6328CR

49

EC17

EC17

CD270u16SO-RH-2

CD270u16SO-RH-2

4

R80

R80

2.2R0805

2.2R0805

BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB

ISEN_NB+

ISEN_NB-

+

+

12

C106

C106
C0.1u10X0402

C0.1u10X0402

PVCC

GVOT

BOOT1
UGATE1
PHASE1
LGATE1

BOOT2
UGATE2
PHASE2
LGATE2

PWM3
PWM4

ISEN1+

ISEN1-

ISEN2+

ISEN2-

ISEN3+

ISEN3-

ISEN4+

ISEN4-

TCOMP1
TCOMP2

R92

R92
1KR0402

1KR0402

EC5

EC5

CD270u16SO-RH-2

CD270u16SO-RH-2

42
29

31
32
33
30

27
26
24
28

37
36

20
21

22
23

44
43

46
45

40
39
38
41

48
47

11
12

C92

C92
C2.2U6.3X0603

C2.2U6.3X0603

+

+

12

+12VIN VCC5

C70 C2.2u25X1206-HF-1C70 C2.2u25X1206-HF-1

BOOT1 BOOT1_R

R82

R82

2.2R1%0805

2.2R1%0805

BOOT2 BOOT2_R

R68

R68

2.2R1%0805

2.2R1%0805

PWM3

R52 249R1%0402R52 249R1%0402

PHASE11_R

PHASE11

R28

R28

4.02KR1%0402

4.02KR1%0402

ISEN2_R ISEN2

R50 249R1%0402R50 249R1%0402

PHASE22_R

PHASE22

R27

R27

4.02KR1%0402

4.02KR1%0402

ISEN3_R

R111 237R1%0402R111 237R1%0402

PHASE33_R

PHASE33

R140

4.02KR1%0402

4.02KR1%0402

Disable PWM4

VCC5

NB_BOOT NB_BOOT_R

R110

R110

2.2R1%0805

2.2R1%0805

R113 180R1%0402R113 180R1%0402

PHASE_NB_R

PHASE_NBA

R116

R116

12.1KR1%0402

12.1KR1%0402

R55 2.8KR1%0402R55 2.8KR1%0402

R66 1.5KR1%0402R66 1.5KR1%0402

R54

R54

C59

C59

C22p50N0402

C22p50N0402

19.6KR1%0402

19.6KR1%0402

VCORE_EN

VIN

C315

C315

EC11

EC11

C0.1u16Y0402

C0.1u16Y0402

CD270u16SO-RH-2

CD270u16SO-RH-2

R131

R131

2.2R0805

2.2R0805

C87

C87
C0.1U25X

C0.1U25X

C62

C62
C0.1U25X

C0.1U25X

R51 X_0R0402R51 X_0R0402
C21 C0.22U16XC21 C0.22U16X

R49 X_0R0402R49 X_0R0402
C33 C0.22U16XC33 C0.22U16X

R137 X_0R0402R137 X_0R0402
C118 C0.22U16XC118 C0.22U16X

C104

C104
C0.1U25X

C0.1U25X

R112 X_0R0402R112 X_0R0402
C107 C0.1U25XC107 C0.1U25X

R120

R120

X_2.2R0805

X_2.2R0805

C105

C105
C1U16X5

C1U16X5

UGATE1

PHASE1
LGATE1

UGATE2

PHASE2
LGATE2

ISEN1ISEN1_R

C35 C0.1U25XC35 C0.1U25X

ISEN3

UGATE_NB

PHASE_NB
LGATE_NB

ISEN_NB

Close PHASE1

RT1

RT1

Output Choke

10KRT1%

10KRT1%

Vcore side

R56

R56

16.2KR1%0402

16.2KR1%0402

C34

C34

C119

C119

C0.1U25X

C0.1U25X

C0.1U25X

C0.1U25X

C109

C109
C0.1U25X

C0.1U25X

3

2

1

VIN

C148

C148

C288

C288

C1U16X5

C1U16X5

C10u16Y1206

C10u16Y1206

CHOKE2 CH-0.36u55A0.46m-HFCHOKE2 CH-0.36u55A0.46m-HF

1 2

12

CP9CP9

PHASE11
ISEN1

C168

C168

C163

C163

C1U16X5

C1U16X5

C10u16Y1206

C10u16Y1206

CHOKE4 CH-0.36u55A0.46m-HFCHOKE4 CH-0.36u55A0.46m-HF

1 2

12

CP11CP11

PHASE22
ISEN2

C232

C232

C225

C225

C1U16X5

C1U16X5

C10u16Y1206

C10u16Y1206

CHOKE6 CH-0.36u55A0.46m-HFCHOKE6 CH-0.36u55A0.46m-HF

1 2

12

CP13CP13

PHASE33
ISEN3

VCORE output 80A
OCP:160A

12

C144

C144

CP10CP10

C10u6.3X50805

C10u6.3X50805

Place close
to CHOKE

12

C184

C184

CP12CP12

C10u6.3X50805

C10u6.3X50805

Place close
to CHOKE

12

C253

C253

CP14CP14

C10u6.3X50805

C10u6.3X50805

Place close
to CHOKE

VCCP

+

+

12

+

+

12

EC10

EC10

EC23

EC23

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

VCCP

+

+

+

+

12

12

EC22

EC22

EC16

EC16

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

VCCP

+

+

12

+

+

12

EC15

EC15

EC9

EC9

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

CPU_VDDNB

+12VIN

R326

R326

2.2R0805

2.2R0805

R1 0R0805R1 0R0805
C338

C338
C1U25X0805

C1U25X0805

VCCP

+

+

12

+

+

12

EC26

EC26

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

EC74

EC74

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

C1

C1
X_C1U25X0805

X_C1U25X0805

+

+

12

+

+

12

EC73

EC73

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

+

+

12

+

+

12

EC78

EC78

C470u2.5pSO-RH

C470u2.5pSO-RH

U25

6

VCC

UGATE

7

BOOT

PVCC

PHASE

4

GND

3

PWM

LGATE

ISL6612ACBZT_SOIC8-RH

ISL6612ACBZT_SOIC8-RH

UGATE1

PHASE1

LGATE1

bottom side

EC77

EC77

C470u2.5pSO-RH

C470u2.5pSO-RH

UGATE2 UGATE2_R

PHASE2

Top side

EC79

EC79

LGATE2

C470u2.5pSO-RH

C470u2.5pSO-RH

UGATE3 UGATE3_R

1

BOOT3

2

R297

R297

2.2R1%0805

2.2R1%0805

8

PHASE3

LGATE3PWM3

5

R198 1R0805R198 1R0805
R212 10KR0402R212 10KR0402

R199 0R0805R199 0R0805

R261 1R0805R261 1R0805
R265 10KR0402R265 10KR0402

R259 0R0805R259 0R0805

R296 1R0805R296 1R0805
C328

C328

R272 10KR0402R272 10KR0402

C0.1U25X

C0.1U25X

R320 0R0805R320 0R0805

UGATE1_R

LGATE1_R

LGATE2_R

LGATE3_R

Q21

Q21

Q25

Q25

D

D

D

D

G

G

G

G

S

S

S

S

N-P0903BD

N-P0903BD

X_N-P0903BD

X_N-P0903BD

Q26

Q26

Q20

Q20

R152

D

D

G

G

S

S

N-P0603BD

N-P0603BD

R152

D

D

G

G

2.2R1206

2.2R1206

S

S

C126

C126
C1000P50X0402

C1000P50X0402

N-P0603BD

N-P0603BD

VIN

Q37

Q37

Q32

Q32

D

D

D

D

G

G

G

G

S

S

S

S

N-P0903BD

N-P0903BD

X_N-P0903BD

X_N-P0903BD

Q31

Q31

Q38

Q38

D

D

G

G

S

S

N-P0603BD

N-P0603BD

R226

R226

D

D

G

G

2.2R1206

2.2R1206

S

S

C174

C174
C1000P50X0402

C1000P50X0402

N-P0603BD

N-P0603BD

VIN

Q41

Q41

Q44

Q44

D

D

D

D

G

G

G

G

S

S

S

S

N-P0903BD

N-P0903BD

X_N-P0903BD

X_N-P0903BD

R270

R270

Q42

Q42

Q45

Q45

D

D

D

D

G

G

S

S

N-P0603BD

N-P0603BD

2.2R1206

2.2R1206

G

G

S

S

C246

C246
C1000P50X0402

C1000P50X0402

N-P0603BD

N-P0603BD

VIN

C95

C95

C125

C125

C10u16Y1206

C10u16Y1206

C1U16X5

C1U16X5

Q17

Q17

D

LGATE_NB_R

G

G

G

G

D

S

S

N-P0903BD

N-P0903BD

Q15

Q15

D

D

S

S

N-P0603BD

N-P0603BD

CHOKE1 CH-0.36u55A0.46m-HFCHOKE1 CH-0.36u55A0.46m-HF

1 2

R58

R58

Q16

Q16

D

D

2.2R1206

2.2R1206

G

G

S

S

C53

C53
C1000P50X0402

C1000P50X0402

N-P0603BD

N-P0603BD

PHASE_NBA
ISEN_NB

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

12

CP7CP7

ISL6328/6612A 3+1 Phase

ISL6328/6612A 3+1 Phase

ISL6328/6612A 3+1 Phase

C

C

C

FUSION 1.0

FUSION 1.0

FUSION 1.0

UGATE_NB

PHASE_NB

LGATE_NB

TP1TP1

TP2TP2

3

VCC5_ISL6328
VIN

R136 1R0805R136 1R0805
R126 10KR0402R126 10KR0402

R91 0R0805R91 0R0805

UGATE_NB_R

2

NB_CORE output 20A
OCP:32A

CPU_VDDNB

+

+

+

+

12

12

C123

C123

CP8CP8

C10u6.3X50805

C10u6.3X50805

Place close
to CHOKE

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

1

12

EC7

EC7

EC6

EC6

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

735Saturday, August 13, 2011

735Saturday, August 13, 2011

735Saturday, August 13, 2011

of

of

of

CD820u2.5SO-RH-3

CD820u2.5SO-RH-3

5

4

3

2

1

FM1 PCIE I/F

mach@CRB PCIE AC Capacitors:75nF to 200nF

D D

P_GFX_RXP0

GFX_RX0P31
GFX_RX0N31
GFX_RX1P31
GFX_RX1N31
GFX_RX2P31
GFX_RX2N31
GFX_RX3P31
GFX_RX3N31
GFX_RX4P31
GFX_RX4N31
GFX_RX5P31
GFX_RX5N31
GFX_RX6P31
GFX_RX6N31
GFX_RX7P31
GFX_RX7N31
GFX_RX8P31
GFX_RX8N31

C C

B B

VCC_VDDP_B

GFX_RX9P31
GFX_RX9N31
GFX_RX10P31
GFX_RX10N31
GFX_RX11P31
GFX_RX11N31
GFX_RX12P31
GFX_RX12N31
GFX_RX13P31
GFX_RX13N31
GFX_RX14P31
GFX_RX14N31
GFX_RX15P31
GFX_RX15N31

LAN_RXC_P24
LAN_RXC_N24

UMI_RX0P16
UMI_RX0N16
UMI_RX1P16
UMI_RX1N16
UMI_RX2P16
UMI_RX2N16
UMI_RX3P16
UMI_RX3N16

R252 196R1%R252 196R1%

Layout:
Place within 1.5'' of APU

LAN_RXC_P
LAN_RXC_N

APU_P_ZVDDP

AF8

AF9
AE7
AE8
AD5
AD6
AD8
AD9
AC7
AC8
AB5
AB6
AB8
AB9
AA7
AA8

AH5
AH6
AH8
AH9
AG7
AG8

AF5

AF6

AL5

AL4

AK3

AK2

AJ2

AJ1

AJ4

AJ5

Y5
Y6
Y8

Y9
W7
W8

V5

V6

V8

V9

U7

U8

T5

T6

T8

T9

J7

P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15

P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3

P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3

P_ZVDDP

PCI EXPRESS

PCI EXPRESS

U100H

U100H

GPP GRAPHICS

GPP GRAPHICS

UMI_LINK

UMI_LINK

P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9

P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15

P_GPP_TXP0

P_GPP_TXN0

P_GPP_TXP1

P_GPP_TXN1

P_GPP_TXP2

P_GPP_TXN2

P_GPP_TXP3

P_GPP_TXN3

P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3

P_ZVSS

<APU>

<APU>

Layout: PLACE CAPS WITH APU < 1 INCH
ROUTE ALL PCIE AS 85OHM +/-10%

AE2
AE1
AE4
AE5
AD2
AD3
AC2
AC1
AC4
AC5
AB2
AB3
AA2
AA1
AA4
AA5
Y2
Y3
W2
W1
W4
W5
V2
V3
U2
U1
U4
U5
T2
T3
R2
R1

AH2
AH3
AG2
AG1
AG4
AG5
AF2
AF3

UMI_TX0P_APU

AK8

UMI_TX0N_APU

AK9

UMI_TX1P_APU

AL7

UMI_TX1N_APU

AL8

UMI_TX2P_APU

AK5

UMI_TX2N_APU

AK6

UMI_TX3P_APU

AJ7

UMI_TX3N_APU

AJ8

APU_P_ZVSS

J6

GFX_TXP0
GFX_TXN0
GFX_TXP1
GFX_TXN1
GFX_TXP2
GFX_TXN2
GFX_TXP3
GFX_TXN3
GFX_TXP4
GFX_TXN4
GFX_TXP5
GFX_TXN5
GFX_TXP6
GFX_TXN6
GFX_TXP7
GFX_TXN7
GFX_TXP8
GFX_TXN8
GFX_TXP9
GFX_TXN9
GFX_TXP10
GFX_TXN10
GFX_TXP11
GFX_TXN11
GFX_TXP12
GFX_TXN12
GFX_TXP13
GFX_TXN13
GFX_TXP14
GFX_TXN14
GFX_TXP15
GFX_TXN15

LAN_TXP
LAN_TXN

C423 C0.1u10X0402C423 C0.1u10X0402
C422 C0.1u10X0402C422 C0.1u10X0402
C420 C0.1u10X0402C420 C0.1u10X0402
C421 C0.1u10X0402C421 C0.1u10X0402
C418 C0.1u10X0402C418 C0.1u10X0402
C419 C0.1u10X0402C419 C0.1u10X0402
C417 C0.1u10X0402C417 C0.1u10X0402
C416 C0.1u10X0402C416 C0.1u10X0402
C414 C0.1u10X0402C414 C0.1u10X0402
C415 C0.1u10X0402C415 C0.1u10X0402
C412 C0.1u10X0402C412 C0.1u10X0402
C413 C0.1u10X0402C413 C0.1u10X0402
C411 C0.1u10X0402C411 C0.1u10X0402
C410 C0.1u10X0402C410 C0.1u10X0402
C409 C0.1u10X0402C409 C0.1u10X0402
C408 C0.1u10X0402C408 C0.1u10X0402
C406 C0.1u10X0402C406 C0.1u10X0402
C407 C0.1u10X0402C407 C0.1u10X0402
C405 C0.1u10X0402C405 C0.1u10X0402
C404 C0.1u10X0402C404 C0.1u10X0402
C402 C0.1u10X0402C402 C0.1u10X0402
C403 C0.1u10X0402C403 C0.1u10X0402
C400 C0.1u10X0402C400 C0.1u10X0402
C401 C0.1u10X0402C401 C0.1u10X0402
C399 C0.1u10X0402C399 C0.1u10X0402
C398 C0.1u10X0402C398 C0.1u10X0402
C396 C0.1u10X0402C396 C0.1u10X0402
C397 C0.1u10X0402C397 C0.1u10X0402
C394 C0.1u10X0402C394 C0.1u10X0402
C395 C0.1u10X0402C395 C0.1u10X0402
C393 C0.1u10X0402C393 C0.1u10X0402
C392 C0.1u10X0402C392 C0.1u10X0402

C799 C0.1u10X0402C799 C0.1u10X0402
C800 C0.1u10X0402C800 C0.1u10X0402

C318 C0.1u10X0402C318 C0.1u10X0402
C319 C0.1u10X0402C319 C0.1u10X0402
C304 C0.1u10X0402C304 C0.1u10X0402
C305 C0.1u10X0402C305 C0.1u10X0402
C302 C0.1u10X0402C302 C0.1u10X0402
C303 C0.1u10X0402C303 C0.1u10X0402
C316 C0.1u10X0402C316 C0.1u10X0402
C317 C0.1u10X0402C317 C0.1u10X0402

R253 196R1%R253 196R1%

Layout:
Place within 1.5'' of APU

GFX_TXC_0P 31
GFX_TXC_0N 31
GFX_TXC_1P 31
GFX_TXC_1N 31
GFX_TXC_2P 31
GFX_TXC_2N 31
GFX_TXC_3P 31
GFX_TXC_3N 31
GFX_TXC_4P 31
GFX_TXC_4N 31
GFX_TXC_5P 31
GFX_TXC_5N 31
GFX_TXC_6P 31
GFX_TXC_6N 31
GFX_TXC_7P 31
GFX_TXC_7N 31
GFX_TXC_8P 31
GFX_TXC_8N 31
GFX_TXC_9P 31
GFX_TXC_9N 31
GFX_TXC_10P 31
GFX_TXC_10N 31
GFX_TXC_11P 31
GFX_TXC_11N 31
GFX_TXC_12P 31
GFX_TXC_12N 31
GFX_TXC_13P 31
GFX_TXC_13N 31
GFX_TXC_14P 31
GFX_TXC_14N 31
GFX_TXC_15P 31
GFX_TXC_15N 31

LAN_TXC_P 24
LAN_TXC_N 24

UMI_TX0P 16
UMI_TX0N 16
UMI_TX1P 16
UMI_TX1N 16
UMI_TX2P 16
UMI_TX2N 16
UMI_TX3P 16
UMI_TX3N 16

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

FM1 PCIE I/F

FM1 PCIE I/F

FM1 PCIE I/F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

B

B

B

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FUSION 1.0

FUSION 1.0

FUSION 1.0

835Wednesday, August 17, 2011

835Wednesday, August 17, 2011

835Wednesday, August 17, 2011

of

of

1

of

5

4

3

2

1

FM1DDR3 I/F

MEM_MA_DQS_L[7..0]12
MEM_MA_DQS_H[7..0]12

MEM_MA_DM[7..0]12

D D

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13

MEM_MA_ADD[15..0]12

MEM_MA_BANK012
MEM_MA_BANK112
MEM_MA_BANK212

C C

mach@CLOCK assignment can be changed

MEM_MA_CLK_H012
MEM_MA_CLK_L012
MEM_MA_CLK_H112
MEM_MA_CLK_L112
MEM_MA_CLK_H212
MEM_MA_CLK_L212
MEM_MA_CLK_H312
MEM_MA_CLK_L312

MEM_MA_CKE012
MEM_MA_CKE112

MEM_MA0_ODT012
MEM_MA0_ODT112
MEM_MA1_ODT012
MEM_MA1_ODT112

MEM_MA0_CS_L012
MEM_MA0_CS_L112
MEM_MA1_CS_L012

B B

MEM_MA1_CS_L112
MEM_MA_RAS_L12

MEM_MA_CAS_L12
MEM_MA_WE_L12

MEM_MA_RESET#12
MEM_MA_HOT#12

APU_M_VREF

VCC_DDR

MEM_MA_ADD14
MEM_MA_ADD15

MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7

MEM_MA_CLK_H0
MEM_MA_CLK_L0
MEM_MA_CLK_H1
MEM_MA_CLK_L1
MEM_MA_CLK_H2
MEM_MA_CLK_L2
MEM_MA_CLK_H3
MEM_MA_CLK_L3

MEM_MA_CKE0
MEM_MA_CKE1

MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA1_ODT0
MEM_MA1_ODT1

MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA1_CS_L0
MEM_MA1_CS_L1

MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA_WE_L

MEM_MA_RESET#
MEM_MA_HOT#

R254 39.2R1%0402R254 39.2R1%0402

Layout:
Place within 1.5'' of APU

APU_M_ZVDDIO

AE25
AG21

AE28
AE29
AG24
AG25

AE16
AD16

AA24
AC27
AA25
AC26

AB26
AB25

W26

AF29

AF17

AF20
AF21

W23

W25

MA_ADD0

V27

MA_ADD1

P27

MA_ADD2

R25

MA_ADD3

P26

MA_ADD4

R24

MA_ADD5

P24

MA_ADD6

P23

MA_ADD7

N26

MA_ADD8

N23

MA_ADD9

M25

MA_ADD10

V24

MA_ADD11

N25

MA_ADD12

M24

MA_ADD13

Y23

MA_ADD14

L27

MA_ADD15

L24

MA_BANK0
MA_BANK1

V25

MA_BANK2

L26

MA_DM0

H12

MA_DM1

E17

MA_DM2

H21

MA_DM3

F25

MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DM8

G29

MA_DQS_H0

G13

MA_DQS_L0

F13

MA_DQS_H1

H17

MA_DQS_L1

G17

MA_DQS_H2

F21

MA_DQS_L2

E21

MA_DQS_H3

G26

MA_DQS_L3

G25

MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MA_DQS_H8

F30

MA_DQS_L8

E30

MA_CLK_H0

U27

MA_CLK_L0

U26

MA_CLK_H1

T23

MA_CLK_L1

U23

MA_CLK_H2

T25

MA_CLK_L2

T26

MA_CLK_H3

R27

MA_CLK_L3

R28

MA_CKE0

L23

MA_CKE1

K26

MA0_ODT0
MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0

Y27

MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

MA_RAS_L
MA_CAS_L

Y24

MA_WE_L

Y26

MA_RESET_L

J25

MA_EVENT_L

U24

M_VREF

K22

M_ZVDDIO

J24

MEMORY CHANNEL A

MEMORY CHANNEL A

U100A

U100A

E12
F12
H14
E15
G11
H11
E14
G14

F16
G16
H18
F19
F15
H15
E18
F18

G20
H20
E23
G23
G19
E20
F22
G22

F24
H24
E27
F27
H23
E24
E26
H26

AD30
AF30
AG27
AF27
AD31
AE31
AG28
AD28

AF26
AD25
AF23
AE23
AD27
AE26
AF24
AD24

AG22
AD21
AE19
AG19
AD22
AE22
AE20
AD19

AG18
AE17
AF15
AG15
AD18
AF18
AG16
AD15

F28
E29
G31
H30
H27
G28
F31
H29

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7

MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15

MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23

MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31

MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39

MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47

MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55

MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7

MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15

MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23

MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31

MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39

MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47

MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55

MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_CHECK0
MA_CHECK1
MA_CHECK2
MA_CHECK3
MA_CHECK4
MA_CHECK5
MA_CHECK6
MA_CHECK7

<APU>

<APU>

MEM_MA_DATA[63..0] 12

MEM_MB_ADD[15..0]13

MEM_MB_BANK013
MEM_MB_BANK113
MEM_MB_BANK213

MEM_MB_CLK_H013
MEM_MB_CLK_L013
MEM_MB_CLK_H113
MEM_MB_CLK_L113
MEM_MB_CLK_H213
MEM_MB_CLK_L213
MEM_MB_CLK_H313
MEM_MB_CLK_L313

MEM_MB_CKE013
MEM_MB_CKE113

MEM_MB0_ODT013
MEM_MB0_ODT113
MEM_MB1_ODT013
MEM_MB1_ODT113

MEM_MB0_CS_L013
MEM_MB0_CS_L113
MEM_MB1_CS_L013
MEM_MB1_CS_L113

MEM_MB_RAS_L13
MEM_MB_CAS_L13
MEM_MB_WE_L13

MEM_MB_RESET#13
MEM_MB_HOT#13

MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2

MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7

MEM_MB_CLK_H0
MEM_MB_CLK_L0
MEM_MB_CLK_H1
MEM_MB_CLK_L1
MEM_MB_CLK_H2
MEM_MB_CLK_L2
MEM_MB_CLK_H3
MEM_MB_CLK_L3

MEM_MB_CKE0
MEM_MB_CKE1

MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB1_ODT0
MEM_MB1_ODT1

MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB1_CS_L0
MEM_MB1_CS_L1

MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB_WE_L

MEM_MB_RESET#
MEM_MB_HOT#

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

MEM_MB_DQS_L[7..0]13
MEM_MB_DQS_H[7..0]13

MEM_MB_DM[7..0]13

U100B

AB28

AL29
AH25
AK21
AJ17

AJ29
AH29
AK25
AL25
AJ20
AJ21
AL16
AL17

AA30
AC30
AA31
AC29

AB29
AB31

AA27
AA28

U100B

MEMORY CHANNEL B

MEMORY CHANNEL B

MB_ADD0

V31

MB_ADD1

N28

MB_ADD2

P29

MB_ADD3

N29

MB_ADD4

N31

MB_ADD5

M30

MB_ADD6

M31

MB_ADD7

M28

MB_ADD8

M27

MB_ADD9

L30

MB_ADD10

W31

MB_ADD11

L29

MB_ADD12

K28

MB_ADD13
MB_ADD14

K31

MB_ADD15

J31

MB_BANK0

W29

MB_BANK1

V30

MB_BANK2

K29

MB_DM0

B12

MB_DM1

D16

MB_DM2

B20

MB_DM3

A25

MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DM8

D29

MB_DQS_H0

D13

MB_DQS_L0

C13

MB_DQS_H1

A17

MB_DQS_L1

B17

MB_DQS_H2

B21

MB_DQS_L2

C21

MB_DQS_H3

D25

MB_DQS_L3

C25

MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_DQS_H8

B29

MB_DQS_L8

A29

MB_CLK_H0

U30

MB_CLK_L0

U29

MB_CLK_H1

T29

MB_CLK_L1

T28

MB_CLK_H2

R31

MB_CLK_L2

T31

MB_CLK_H3

P30

MB_CLK_L3

R30

MB_CKE0

J30

MB_CKE1

J28

MB0_ODT0
MB0_ODT1
MB1_ODT0
MB1_ODT1

MB0_CS_L0

Y29

MB0_CS_L1
MB1_CS_L0

Y30

MB1_CS_L1

MB_RAS_L

W28

MB_CAS_L
MB_WE_L

MB_RESET_L

J27

MB_EVENT_L

V28

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7

MB_DATA8

MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15

MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23

MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31

MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39

MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47

MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55

MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_CHECK0
MB_CHECK1
MB_CHECK2
MB_CHECK3
MB_CHECK4
MB_CHECK5
MB_CHECK6
MB_CHECK7

MEM_MB_DATA0

D11

MEM_MB_DATA1

C12

MEM_MB_DATA2

A14

MEM_MB_DATA3

B14

MEM_MB_DATA4

B11

MEM_MB_DATA5

A11

MEM_MB_DATA6

A13

MEM_MB_DATA7

D14

MEM_MB_DATA8

A16

MEM_MB_DATA9

C16

MEM_MB_DATA10

B18

MEM_MB_DATA11

A19

MEM_MB_DATA12

C15

MEM_MB_DATA13

B15

MEM_MB_DATA14

D17

MEM_MB_DATA15

C18

MEM_MB_DATA16

D20

MEM_MB_DATA17

A20

MEM_MB_DATA18

D22

MEM_MB_DATA19

D23

MEM_MB_DATA20

C19

MEM_MB_DATA21

D19

MEM_MB_DATA22

A22

MEM_MB_DATA23

C22

MEM_MB_DATA24

C24

MEM_MB_DATA25

B24

MEM_MB_DATA26

B26

MEM_MB_DATA27

C27

MEM_MB_DATA28

A23

MEM_MB_DATA29

B23

MEM_MB_DATA30

D26

MEM_MB_DATA31

A26

MEM_MB_DATA32

AJ30

MEM_MB_DATA33

AK30

MEM_MB_DATA34

AH28

MEM_MB_DATA35

AJ27

MEM_MB_DATA36

AG30

MEM_MB_DATA37

AH31

MEM_MB_DATA38

AK28

MEM_MB_DATA39

AL28

MEM_MB_DATA40

AJ26

MEM_MB_DATA41

AH26

MEM_MB_DATA42

AH23

MEM_MB_DATA43

AJ23

MEM_MB_DATA44

AK27

MEM_MB_DATA45

AL26

MEM_MB_DATA46

AJ24

MEM_MB_DATA47

AK24

MEM_MB_DATA48

AK22

MEM_MB_DATA49

AH22

MEM_MB_DATA50

AL19

MEM_MB_DATA51

AK19

MEM_MB_DATA52

AL23

MEM_MB_DATA53

AL22

MEM_MB_DATA54

AH20

MEM_MB_DATA55

AL20

MEM_MB_DATA56

AJ18

MEM_MB_DATA57

AH17

MEM_MB_DATA58

AJ15

MEM_MB_DATA59

AK15

MEM_MB_DATA60

AH19

MEM_MB_DATA61

AK18

MEM_MB_DATA62

AK16

MEM_MB_DATA63

AH16
A28

D28
C30
D31
B27
C28
B30
C31

<APU>

<APU>

MEM_MB_DATA[63..0] 13

VCC_DDR

R196

R196

1KR1%

1KR1%

A A

5

R201

R201

1KR1%

1KR1%

C170

C170

C1000P50X0402

C1000P50X0402

APU_M_VREF

C679

C679

C0.1u10X0402

C0.1u10X0402

C156

C156

Layout:
Place within 1.0'' of APU

C1000P50X0402

C1000P50X0402

4

VCC_DDR

R275 1KR0402R275 1KR0402
R274 1KR0402R274 1KR0402

3

MEM_MA_HOT#
MEM_MB_HOT#

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DDR3 I/F

FM1 DDR3 I/F

FM1 DDR3 I/F

FUSION 1.0

FUSION 1.0

FUSION 1.0

1

935Wednesday, August 17, 2011

935Wednesday, August 17, 2011

935Wednesday, August 17, 2011

of

of

of

5

FM1 DISPLAY I/F

Note: Several vias on the DP0 interface violate the minimum distance rules
for via to via spacing between diff pairs. These violations have been reviewed and approved
on an individual basis, and pose no significant singal integrity issues for this implementation since
the route lengths are under the maximum allowed spec, and the via distance violations are not severe.

DP0_TX0P21
DP0_TX0N21

mach@DP0 for HDMI

D D

mach@DP1 for CRT

APU_SIC

C337

C337

X_C10p50N0402

X_C10p50N0402

Layout: Place within 1.5'' of APU

APU_RST#
APU_PWRGD

C C

C335

C335

C299

C299

C180p50N0402

C180p50N0402

C180p50N0402

C180p50N0402

DP0_TX1P21
DP0_TX1N21

DP0_TX2P21
DP0_TX2N21

DP0_TX3P21
DP0_TX3N21

DP1_TX0P18
DP1_TX0N18

DP1_TX1P18
DP1_TX1N18

DP1_TX2P18
DP1_TX2N18

DP1_TX3P18
DP1_TX3N18

APU_PROCHOT#16

APU_RST#16

APU_PWRGD7,16

APU_CLK16
APU_CLK#16

DISP_CLK16
DISP_CLK#16

APU_SIC25
APU_SID25

C230 C0.1u10X0402C230 C0.1u10X0402
C235 C0.1u10X0402C235 C0.1u10X0402

C226 C0.1u10X0402C226 C0.1u10X0402
C220 C0.1u10X0402C220 C0.1u10X0402

C213 C0.1u10X0402C213 C0.1u10X0402
C209 C0.1u10X0402C209 C0.1u10X0402

C210 C0.1u10X0402C210 C0.1u10X0402
C214 C0.1u10X0402C214 C0.1u10X0402

C255 C0.1u10X0402C255 C0.1u10X0402
C259 C0.1u10X0402C259 C0.1u10X0402

C248 C0.1u10X0402C248 C0.1u10X0402
C252 C0.1u10X0402C252 C0.1u10X0402

C244 C0.1u10X0402C244 C0.1u10X0402
C238 C0.1u10X0402C238 C0.1u10X0402

C240 C0.1u10X0402C240 C0.1u10X0402
C236 C0.1u10X0402C236 C0.1u10X0402

APU_SIC

R316 10R0402R316 10R0402

APU_SID

APU_RST#
APU_PWRGD

APU_PROCHOT#
APU_THERMTRIP#
APU_ALERT#

VCC_DDR VCC3_SB

R304

R304

R305

R305

TP9TP9

NBCOREFB+7

VDDIOFB+27

COREFB+

COREFB+7

TP10TP10

COREFB-7

APU_THERMTRIP#

2

10KR0402

10KR0402

61

Q49A

Q49A

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

10KR0402

10KR0402

FCH_THERMTRIP# 17

VCC3_SBVCC_DDR

R302

R302

R303

R303

APU_ALERT#

B B

Q49B

Q49B

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

5

10KR0402

10KR0402

10KR0402

10KR0402

34

FCH_TALERT# 18

PULL UP

VCC_DDR

R307 1KR0402R307 1KR0402
R317 1KR0402R317 1KR0402

R288 300R0402R288 300R0402
R310 300R0402R310 300R0402

R289 300R0402R289 300R0402
R287 1KR0402R287 1KR0402
R290 1KR0402R290 1KR0402

R318 1KR0402R318 1KR0402

VCC5_SB

R301 10KR0402R301 10KR0402

A A

APU_SIC_R
APU_SID

APU_RST#
APU_PWRGD

APU_PROCHOT#
APU_ALERT#
APU_THERMTRIP#

FCH_DMA_ACTIVE#

APU_FM1R1

To overide VID:remove R520,R521
Stuff R82 to enter FIX mode

4

ROUTE PCIE AS 85OHM +/-10%
PLACE CAPS WITH APU < 1 INCH

Trace length within 10"

ANALOG/DISPLAY/MISC

AL12

AK12
AH12

AG12

AF10
AG10

AJ13

AG11

AL14
AK14
AD10

AF13

ANALOG/DISPLAY/MISC

DP0_TXP0

M2

DP0_TXN0

M3

DP0_TXP1

L2

DP0_TXN1

L1

DP0_TXP2

L4

DP0_TXN2

L5

DP0_TXP3

K2

DP0_TXN3

K3

DP1_TXP0

R4

DP1_TXN0

R5

DP1_TXP1

P2

DP1_TXN1

P3

DP1_TXP2

N2

DP1_TXN2

N1

DP1_TXP3

N4

DP1_TXN3

N5

CLKIN_H
CLKIN_L

DISP_CLKIN_H
DISP_CLKIN_L

SVC

A8

SVD

B8

SIC
SID

RESET_L
PWROK

PROCHOT_L
THERMTRIP_L
ALERT_L

TDI

E9

TDO

G10

TCK

E8

TMS

D8

TRST_L

F10

DBRDY

D7

DBREQ_L

F8

RSVD_1

E11

RSVD_2

H9

RSVD_3

K23

RSVD_4

K25

RSVD_5

VDDP_SENSE

B5

VDDNB_SENSE

A6

VDDIO_SENSE

B6

VDD_SENSE

C7

VDDR_SENSE

A5

VSS_SENSE

C6

DP0_TX0P_APU
DP0_TX0N_APU

DP0_TX1P_APU
DP0_TX1N_APU

DP0_TX2P_APU
DP0_TX2N_APU

DP0_TX3P_APU
DP0_TX3N_APU

DP1_TX0P_APU
DP1_TX0N_APU

DP1_TX1P_APU
DP1_TX1N_APU

DP1_TX2P_APU
DP1_TX2N_APU

DP1_TX3P_APU
DP1_TX3N_APU

APU_SVC_R
APU_SVD_R

APU_SIC_R

CPU_TDI
CPU_TDO
CPU_TCK
CPU_TMS
CPU_TRST_L
CPU_DBRDY
CPU_DBREQ_L

VDDP_SENSE

VDDR_SENSE

VID OVERRIDE CIRCUIT

APU_SVC_R
APU_SVD_R
APU_PWRGD

SVC SVD
0

0
001
1
11

BOOT Voltage

Pre-PWROK metel VID V_FIX MODE

1.1

1.0

0.9

0.8

1.4

1.2

1.0

0.8

3

U100C

U100C

DISPLAY PORT 0

DISPLAY PORT 0

DISPLAY PORT MISC.

DISPLAY PORT MISC.

DISPLAY PORT 1

DISPLAY PORT 1

CLK

CLK

CTRL SER.

CTRL SER.

TEST

TEST

JTAG

JTAG

SENSE RSVD

SENSE RSVD

TEST2, TEST3, TEST6, TEST10, TEST23, TEST28_H TEST28_L, and any RSVD pins have no connections.
TEST4, TEST5, TEST[17:14], TEST25_H/L,TEST30_H/L, and TEST32_H/L have onboard test points.

DP_AUX_ZVSS

DP_AUX_ZVSS

J9

APU_BLON

DP_BLON

G9

APU_DIGON

DP_DIGON

G7

APU_BLPWM

DP_VARY_BL

H8

DP0_AUXP

K6

DP0_AUXN

K8

DP1_AUXP

L7

DP1_AUXN

L8

DP2_AUXP

R7

DP2_AUXN

R8

DP3_AUXP

P8

DP3_AUXN

P9

DP4_AUXP

N7

DP4_AUXN

N8

DP5_AUXP

M8

DP5_AUXN

M9

DP0_HPD

K9

DP1_HPD

K5

DP2_HPD

P5

DP3_HPD

P6

DP4_HPD

M5

DP5_HPD

M6

THERMDA

AH14

THERMDC

AG14

TEST2

AB23

TEST3

AC24

TEST6

AG13

TEST9

D10

TEST10

C10

TEST12

F6

TEST14

D9

TEST15

C9

TEST16

B9

TEST17

A9

TEST18

E4

TEST19

F5

TEST20

D4

TEST21

D5

TEST22

E5

TEST23

F7

TEST24

E6

TEST25_H

AE11

TEST25_L

AD11

TEST28_H

G5

TEST28_L

G6

TEST30_H

AD14

TEST30_L

AE14

TEST31

AG31

TEST32_H

AE13

TEST32_L

AD13

TEST35

A7

FM1R1

AC12

DMAACTIVE_L

AF11

<APU>

<APU>

mach@FM1R1 used to control VRM_EN(D66)???
FM1R1 = OPEN ON PKG. IF LOW, KEEP PWR OFF!

R207 150R1%0402R207 150R1%0402

DP0

DP1

DP2_HPD
DP3_HPD
DP4_HPD
DP5_HPD

APU_TEST4
APU_TEST5
APU_TEST2
APU_TEST3
APU_TEST6
APU_TEST9
APU_TEST10
APU_TEST12
APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST21
APU_TEST22
APU_TEST23
APU_TEST24
APU_TEST25_H
APU_TEST25_L
APU_TEST28_H
APU_TEST28_L
APU_TEST30_H
APU_TEST30_L
APU_TEST31
APU_TEST32_H
APU_TEST32L
APU_TEST35

APU_FM1R1
FCH_DMA_ACTIVE#

Layout: Place within 1.5'' of APU

DP0_AUXP_C 21
DP0_AUXN_C 21

DP1_AUXP_C 18
DP1_AUXN_C 18

DP0_TX0,TX1,TX2 and TX3
DP0_AUX0 and DP0_HPD

DP1_TX0,TX1,TX2 and TX3
DP1_AUX0 and DP1_HPD

R266 100KR0402R266 100KR0402
R267 100KR0402R267 100KR0402
R262 100KR0402R262 100KR0402
R260 100KR0402R260 100KR0402

TP39TP39
TP45TP45
TP40TP40
TP41TP41
TP44TP44

R210 0R0402R210 0R0402

TP33TP33

R192 1KR0402R192 1KR0402

R203 1KR0402R203 1KR0402
R189 1KR0402R189 1KR0402
R191 1KR0402R191 1KR0402
R205 1KR0402R205 1KR0402
R190 1KR0402R190 1KR0402

TP36TP36

R204 1KR0402R204 1KR0402
R319 511R1%0402R319 511R1%0402

R311 511R1%0402R311 511R1%0402
TP38TP38
TP37TP37

R308 X_39.2R1%0402R308 X_39.2R1%0402

R300 X_39.2R1%0402R300 X_39.2R1%0402

R280 39.2R1%0402R280 39.2R1%0402
TP42TP42
TP43TP43

R206 X_300R0402R206 X_300R0402

R193 300R0402R193 300R0402

APU_FM1R1 7

FCH_DMA_ACTIVE# 16

MACH@??? DP2 to PCIE16X conn?

DP0_HPD_HDMI_C 21
DP1_HPD_VGA_C 18

CPU_VDDP

VCC_DDR

Sabine HDMI Design Guidance
HDMI enable strapping:
TEST35 PU TO VCC_DDR thru 300R

VCC_DDR

R185

R185

R186

R186

1KR0402

1KR0402

1KR0402

1KR0402

R209 0R0402R209 0R0402
R208 0R0402R208 0R0402

R309

R309

R195

R195

X_220R0402

X_220R0402

X_220R0402

X_220R0402

R194

R194

X_220R0402

X_220R0402

APU_SVC 7
APU_SVD 7

2

CPU_TRST_L

HDT+ Connector

VCC_DDR

J2

J2

1

CPU_VDDIO

3

GND

5

GND

7

R658 X_0R0402R658 X_0R0402
R659 X_10KR0402R659 X_10KR0402
R660 X_10KR0402R660 X_10KR0402
R661 X_10KR0402R661 X_10KR0402

GND
CPU_TRST_L9CPU_PWROK_BUF
CPU_DBRDY311CPU_RST_L_BUF
CPU_DBRDY213CPU_DBRDY0
CPU_DBRDY115CPU_DBREQ_L

17

GND
CPU_VDDIO19CPU_PLLTEST1

X_H2X10SM-1.27PITCH_BLUE-RH

X_H2X10SM-1.27PITCH_BLUE-RH

VCC3 VCC3

R9

2

X_10KR0402R9X_10KR0402

APU_PWROK_BUFAPU_PWRGD APU_LDT_RST_BUF

61

Q83A

Q83A

X_NN-CMKT3904_SOT363-6-RH

X_NN-CMKT3904_SOT363-6-RH

VCC_DDRVCC_DDR

Layout: Place close to HDT header

R653 1KR0402R653 1KR0402
R651 1KR0402R651 1KR0402
R652 1KR0402R652 1KR0402
R657 1KR0402R657 1KR0402
R654 300R0402R654 300R0402

SCAN Conn,

APU_TEST18
APU_TEST19
APU_TEST21
APU_TEST22
APU_TEST12
APU_TEST24
APU_TEST20

WARM RESET

APU_RST#

GPU DEBUG

APU_TEST14
APU_TEST15
APU_TEST16
APU_TEST17
APU_BLON
APU_DIGON
APU_BLPWM
DP1_HPD_VGA_C

CPU_TCK

CPU_TMS

CPU_TDI

CPU_TDO

CPU_PLLTEST0

APU_RST#

TP8TP8
TP7TP7
TP32TP32

2
4
6
8

APU_PWROK_BUF

10

APU_LDT_RST_BUF

12
14
16
18
20

5

R83

R83

Q83B

Q83B

X_0R0402

X_0R0402

X_NN-CMKT3904_SOT363-6-RH

X_NN-CMKT3904_SOT363-6-RH

CPU_TDI
CPU_TCK
CPU_TMS
CPU_TRST_L
CPU_DBREQ_L

TP46TP46
TP64TP64
TP65TP65
TP67TP67
TP68TP68
TP69TP69
TP70TP70

TP71TP71

TP72TP72
TP73TP73
TP74TP74
TP75TP75
TP76TP76
TP77TP77
TP78TP78
TP79TP79

1

CPU_TCK
CPU_TMS
CPU_TDI
CPU_TDO

CPU_DBRDY

CPU_DBREQ_L

APU_TEST19
APU_TEST18

R42

R42

X_10KR0402

X_10KR0402

34

NBCOREFB+
VDDIOFB+
COREFB+

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

FM1 DISPLAY/MSIC

FM1 DISPLAY/MSIC

FM1 DISPLAY/MSIC

FUSION 1.0

FUSION 1.0

FUSION 1.0

1

10 35Wednesday, August 17, 2011

10 35Wednesday, August 17, 2011

10 35Wednesday, August 17, 2011

of

of

of

5

BOTTOM SIDE DECOUPLING

VCCP

C697,C700,C705,C710 change to ASM-5010

D D

C700

C700

C22u6.3X1206

C22u6.3X1206

C697

C697

C22u6.3X1206

C22u6.3X1206

C705

C705

C22u6.3X1206

C22u6.3X1206

C710

C710

C22u6.3X1206

C22u6.3X1206

C682

C682

C47u6.3X1206

C47u6.3X1206

C704

C704

VCCP VCCP

C694

C694

C712

C712

VCCP

C715

C C

C715

C702

C702

C689

C689

C47u4X50805-RH

C47u4X50805-RH

C47u4X50805-RH

C22u6.3X50805-RH

C22u6.3X50805-RH

C47u4X50805-RH

C709

C709

C708

C708

C47u4X50805-RH

C47u4X50805-RH

C22u6.3X50805-RH

C22u6.3X50805-RH

C22u6.3X50805-RH

C22u6.3X50805-RH

VCCP VCCP

C716

C716

C0.22U16X

C0.22U16X

C0.22U16X

C0.22U16X

C693

C693

C0.01u25X

C0.01u25X

C711

C711

C0.01u25X

C0.01u25X

C714

C714

CPU_VDDNB

C789

C796

C796

C47u6.3X1206

C47u6.3X1206

C790

C790

C795

C795

C47u6.3X1206

C47u6.3X1206

C789

C47u6.3X1206

C47u6.3X1206

C794

C794

C47u6.3X1206

C47u6.3X1206

C792

C792

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

VCC_DDR

B B

C695

C695

CPU_VDDR

C298

C298

A A

VCCP

C260

C260

C180p50N0402

C180p50N0402

C681

C681

C685

C22u6.3X1206

C22u6.3X1206

C314

C314

C4.7u6.3X5

C4.7u6.3X5

C273

C273

C180p50N0402

C180p50N0402

C685

C22u6.3X1206

C22u6.3X1206

C332

C332

C4.7u6.3X5

C4.7u6.3X5

C268

C268

X_C180p50N0402

X_C180p50N0402

5

C22u6.3X1206

C22u6.3X1206

C0.22U16X

C0.22U16X

C690

C690

C22u6.3X1206

C22u6.3X1206

Layout: Place close to Pins
AH11,AJ11,AK11,AL11

C324

C324

C22u6.3X1206

C22u6.3X1206

C180p50N0402

C180p50N0402

C223

C223

C10u6.3X50805

C10u6.3X50805

C330

C330

C0.22U16X

C0.22U16X

C216

C216

X_C180p50N0402

X_C180p50N0402

C698

C698

C4.7u6.3X5

C4.7u6.3X5

CPU_VDDP

C263

C263

X_C180p50N0402

X_C180p50N0402

C696

C696

C699

C699

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C684

C684

C713

C713

C22u6.3X50805-RH

C22u6.3X50805-RH

C680

C680

C0.01u25X

C0.01u25X

C0.01u25X

C0.01u25X

C797

C797

C816

C816

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C47u6.3X1206

C272

C272

C706

C706

C703

C703

C4.7u6.3X5

C4.7u6.3X5

C4.7u6.3X5

C4.7u6.3X5

Layout: Place close to Pins
AH10,AJ10,AK10,AL10

C296

C296

C310

C310

C10u6.3X50805

C10u6.3X50805

C323

C323

C10u6.3X50805

C10u6.3X50805

C687

C687

C47u4X50805-RH

C47u4X50805-RH

C718

C718

C180p50N0402

C180p50N0402

C814

C814

C47u6.3X1206

C47u6.3X1206

C4.7u6.3X5

C4.7u6.3X5

C4.7u6.3X5

C4.7u6.3X5

C47u6.3X1206

C47u6.3X1206

C707

C707

C47u4X50805-RH

C47u4X50805-RH

C719

C719

C791

C791

C270

C270

C0.22U16X

C0.22U16X

C329

C329

C0.22U16X

C0.22U16X

C692

C692

C47u6.3X1206

C47u6.3X1206

C701

C701

C688

C688

C180p50N0402

C180p50N0402

C815

C815

C47u6.3X1206

C47u6.3X1206

C221

C221

C0.22U16X

C0.22U16X

C326

C326

C1000P50X0402

C1000P50X0402

C683

C683

C47u6.3X1206

C47u6.3X1206

C22u6.3X50805-RH

C22u6.3X50805-RH

C180p50N0402

C180p50N0402

C47u6.3X1206

C47u6.3X1206

EMC Caps On Bottom side

C162

C162

C202

C202

X_C180p50N0402

X_C180p50N0402

X_C180p50N0402

X_C180p50N0402

C191

C191

X_C180p50N0402

X_C180p50N0402

C166

C166

X_C180p50N0402

X_C180p50N0402

C798

C798

C47u6.3X1206

C47u6.3X1206

C784

C784

C180p50N0402

C180p50N0402

C331

C331

C1000P50X0402

C1000P50X0402

C211

C211

X_C180p50N0402

X_C180p50N0402

4

VCCP VCCP

C785

C785

C180p50N0402

C180p50N0402

C154

C154

C150

C150

X_C180p50N0402

X_C180p50N0402

X_C180p50N0402

X_C180p50N0402

4

U100D

U100D

VDD

M12

VDD

P12

VDD

H10

VDD

H6

VDD

U19

VDD

J11

VDD

J13

VDD

J15

VDD

J17

VDD

J19

VDD

J21

VDD

J5

VDD

K10

VDD

K12

VDD

K14

VDD

K16

VDD

K18

VDD

K20

VDD

K4

VDD

L11

VDD

W19

VDD

L15

VDD

L17

VDD

N19

VDD

L21

VDD

L3

VDD

L6

VDD

M1

VDD

M10

VDD

W13

VDD

M16

VDD

M18

VDD

M20

VDD

U21

VDD

M4

VDD

M7

VDD

N11

VDD

N21

VDD

P1

VDD

P10

VDD

P20

VDD

R11

VDD

R21

VDD

R3

VDD

R6

VDD

T1

VDD

T10

VDD

T12

VDD

T20

VDD

T4

VDD

T7

U100E

U100E

VDDIO

J26

VDDIO

J29

VDDIO

K24

VDDIO

K27

VDDIO

K30

VDDIO

L25

VDDIO

L28

VDDIO

L31

VDDIO

M23

VDDIO

M26

VDDIO

M29

VDDIO

N24

VDDIO

N27

VDDIO

N30

VDDIO

P22

VDDIO

P25

VDDIO

P28

VDDIO

P31

VDDIO

R23

VDDIO

R26

VDDIO

R29

VDDIO

T22

VDDIO

T24

VDDIO

T27

VDDIO

T30

VDDIO

U25

VDDIO

U28

VDDIO

U31

VDDIO

V22

VDDIO

V23

VDDIO

V26

VDDIO

V29

VDDIO

W24

VDDIO

W27

VDDIO

W30

VDDIO

Y22

VDDIO

Y25

VDDIO

Y28

VDDIO

Y31

VDDIO

AA23

VDDIO

AA26

VDDIO

AA29

VDDIO

AB22

VDDIO

AB24

VDDIO

AB27

VDDIO

AB30

VDDIO

AC23

VDDIO

AC25

VDDIO

AC28

VDDIO

AC31

VDDIO

M22

C197

C197

X_C180p50N0402

X_C180p50N0402

C149

C149

X_C180p50N0402

X_C180p50N0402

POWER

POWER

3

VDD

VDD

VDD

U11

VDD

U13

VDD

V1

VDD

V10

VDD

V12

VDD

V20

VDD

W11

VDD

W21

VDD

W3

VDD

W6

VDD

Y1

VDD

Y10

VDD

Y12

VDD

Y14

VDD

Y16

VDD

Y18

VDD

Y20

VDD

Y4

VDD

Y7

VDD

AA11

VDD

AA13

VDD

AA15

VDD

AA17

VDD

AA19

VDD

AA21

VDD

AB1

VDD

AB10

VDD

R13

VDD

AB14

VDD

AB16

VDD

AB18

VDD

R19

VDD

AC11

VDD

AC13

VDD

AC15

VDD

AC17

VDD

AC19

VDD

AC21

VDD

AC3

VDD

AC6

VDD

AD1

VDD

AD4

VDD

AD7

VDD

AF1

VDD

AG3

VDD

AG6

VDD

AH1

VDD

AH4

VDD

AH7

VDD

AK4

VDD

AK7

<APU>

<APU>

TOTLE
POWER
PINS

416 2

VALUE/SIZE/
MATERIAL

22U/1206/X5R
10U/0805/X5R

4.7U/0805/X5R

0.22U/0603/X5R

0.1U/0603/X5R

0.01U/0603/X5R

3.3 nF/0603/X5R
1 nF/0603/X5R
1 nF/0603/X5R
180 pF/0603/X5R

VDDA25VCC_DDR

VDDA

C277

C277

VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB
VDDNB

VDDNB
VDDNB_CAP_1
VDDNB_CAP_2

VDDP_A_1
VDDP_A_2
VDDP_A_3
VDDP_A_4

VDDP_B_1
VDDP_B_2
VDDP_B_3
VDDP_B_4

<APU>

<APU>

AD12

VDDA

AE12
A3

A4
B3
B4
C1
C2
C3
C4
C5
D1
D2
D3
E1
E2
E3
F1
F2
F3
F4
M14
N13

AH10
AJ10
AK10
AL10

VDDR

AH11

VDDR

AJ11

VDDR

AK11

VDDR

AL11
J1

J2
J3
J4

VDDR

H1

VDDR

H2

VDDR

H3

VDDR

H4

CPU_VDDNB

C180p50N0402

C180p50N0402

C181

C181

TP18TP18

CPU_VDDNB

VDDNB = 0.8V
(Variable)

Layout: Place close to Pins M14,M13
inside the backplate cavity openning

VDDNB_CAP

C686 C22u6.3X1206C686 C22u6.3X1206
C691 C22u6.3X1206C691 C22u6.3X1206

CPU_VDDP

CPU_VDDR

VCC_VDDP_B

CPU_VDDR_B

VDDR = 1.2V
VDDPCIE = 1.2V
ONLY ONE SIDE OF VDDPCIE & VDDR MUST
CONNECTED ON THE PCB.CONNECTING BOTH SIDES
IS ACCEPTABLE BUT NOT REQUIRED. BOTH SIDES
MUST BE DECOUPLED.

VCC_VDDP_B CPU_VDDR_B

C204

C204

C180p50N0402

C180p50N0402

C180p50N0402

C180p50N0402

3

FM1 DECOUPLING CAPS

VSS

VDD

VDDNB

VDDIO

19

102

226

11

/

7

/

3

/

2

/

/

/
/

4

/

/

/

/
/

/
/

31

Place across each VDDIO-GND plane seam

VCC_DDR

C357

C357

C0.22U16X

C0.22U16X

Layout: Place caps within 0.6'' of APU

Layout: Place close to Pins
H1,H2,H3,H4

C189

C189

CPU_VDDP CPU_VDDR

C281

C281

C203

C203

C180p50N0402

C180p50N0402

C180p50N0402

C180p50N0402

51

2

4
1

2
1

4

2

2+2

/

/

/

/

/

/

/

/

/

/
2+2

C371

C371

C758

C758

C0.22U16X

C0.22U16X

C180p50N0402

C180p50N0402

C306

C306

C312

C312

C0.22U16X

C0.22U16X

C4.7u6.3X5

C4.7u6.3X5

Layout: Place close to Pins
J1,J2,J3,J4

C200

C200

C198

C198

C4.7u6.3X5

C4.7u6.3X5

C10u6.3X50805

C10u6.3X50805

C185

C185

C186

C186

C4.7u6.3X5

C4.7u6.3X5

C10u6.3X50805

C10u6.3X50805

C308

C308

C194

C194

C180p50N0402

C180p50N0402

VDDP

COMB

8

/

2+1(B)

2
2
/
/
/
//
4
2+2

C757

C757

C180p50N0402

C180p50N0402

FB5

FB5

30L3A-40_0805-RH

30L3A-40_0805-RH

C717

C717

C3300p50X0402

C3300p50X0402

VCC_VDDP_B

C196

C196

C199

C199

C0.22U16X

C0.22U16X

C1000P50X0402

C1000P50X0402

CPU_VDDR_B

C187

C187

C4.7u6.3X5

C4.7u6.3X5

C0.22U16X

C0.22U16X

VDDP and VDDR support two separate
power planes with single regulator

2

4

NEAR

//1

2
2
/
/
/
/
/
/

SPLIT

4

FAR

/
/
2
2
/
/
/
/
/
/

VDDA

Mvref

1

/

/

/

/
/

1

/

1
/

1
/

/

/

1

1
/
/

/

VDDR

COMB

SPLIT

8

1
2+2
2+2
/
/

/
//
2

CPU_VDDNB

C169

C180

C180

C169

C164

C164

C0.22U16X

C0.22U16X

C0.22U16X

C0.22U16X

C180p50N0402

C180p50N0402

VDDA_25VDDA25

C195

C195

C1000P50X0402

C1000P50X0402

C188

C188

C0.22U16X

C0.22U16X

C321

C321

C180p50N0402

C180p50N0402

2

1

U100F

U100F

VSS

VSS

VSS_1

A10

VSS_2

A12

VSS_3

A15

VSS_4

A18

VSS_5

A21

VSS_6

A24

VSS_7

A27

VSS_8

AL9

VSS_9

B10

VSS_10

B13

VSS_11

B16

VSS_12

B19

VSS_13

B22

VSS_14

B25

VSS_15

B28

VSS_16

B7

VSS_17

C11

VSS_18

C14

VSS_19

C17

VSS_20

C20

VSS_21

C23

VSS_22

C26

VSS_23

C29

VSS_24

C8

VSS_25

D12

VSS_26

D15

VSS_27

D18

VSS_28

D21

VSS_29

D24

VSS_30

D27

VSS_31

D30

VSS_32

D6

VSS_33

E10

VSS_34

E13

VSS_35

E16

VSS_36

E19

VSS_37

E22

VSS_38

E25

VSS_39

E28

VSS_40

E31

VSS_41

E7

VSS_42

F11

VSS_43

F14

VSS_44

F17

VSS_45

F20

VSS_46

F23

VSS_47

F26

VSS_48

F29

VSS_49

F9

VSS_50

G1

VSS_51

G12

VSS_52

G15

VSS_53

G18

VSS_54

G2

VSS_55

G21

VSS_56

G24

VSS_57

G27

VSS_58

G3

U100G

U100G

VSS

T11

VSS

T21

VSS

U10

VSS

U12

VSS

U20

VSS

U22

VSS

U3

VSS

U6

VSS

U9

VSS

V11

VSS

V21

VSS

V4

VSS

V7

VSS

W10

VSS

W12

VSS

W20

VSS

W22

VSS

W9

VSS

Y11

VSS

Y13

VSS

Y15

VSS

Y17

VSS

Y19

VSS

Y21

VSS

AA10

VSS

AA14

VSS

AA16

VSS

AA18

VSS

AA22

VSS

AA3

VSS

AA6

VSS

AA9

VSS

AB11

VSS

AB13

VSS

AB15

VSS

AB17

VSS

AB19

VSS

AB21

VSS

AB4

VSS

AB7

VSS

AC10

VSS

AC14

VSS

AC16

VSS

AC18

VSS

AC20

VSS

AC22

VSS

AC9

VSS

AD17

VSS

AD20

VSS

AD23

VSS

AD26

VSS

AD29

VSS

AE10

VSS

AE15

VSS

AE18

VSS

AE21

VSS

AE24

VSS

AE27

Title

Title

Title

FM1 POWER&DECOUPLING

FM1 POWER&DECOUPLING

FM1 POWER&DECOUPLING

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

C

C

C

Date: Sheet

Date: Sheet

Date: Sheet

VSS_59

G30

VSS_60

G4

VSS_61

G8

VSS_62

H13

VSS_63

H16

VSS_64

H19

VSS_65

H22

VSS_66

H25

VSS_67

H28

VSS_68

H31

VSS_69

H5

VSS_70

H7

VSS_71

J10

VSS_72

J12

VSS_73

J14

VSS_74

J16

VSS_75

J18

VSS_76

J20

VSS_77

J22

VSS_78

J23

VSS_79

J8

VSS_80

K1

VSS_81

K11

VSS_82

V13

VSS_83

K15

VSS_84

K17

VSS_85

V19

VSS_86

K21

VSS_87

K7

VSS_88

L10

VSS_89

L12

VSS_90

L14

VSS_91

L16

VSS_92

L18

VSS_93

L20

VSS_94

L22

VSS_95

L9

VSS_96

M11

VSS_97

M13

VSS_98

M15

VSS_99

M17

VSS_100

M21

VSS_101

N10

VSS_102

N12

VSS_103

N20

VSS_104

N22

VSS_105

N3

VSS_106

N6

VSS_107

N9

VSS_108

P11

VSS_109

P21

VSS_110

P4

VSS_111

P7

VSS_112

R10

VSS_113

R12

VSS_114

R20

VSS_115

R22

VSS_116

R9

<APU>

<APU>

VSS

VSS

VSS

AE3

VSS

AE30

VSS

AE6

VSS

AE9

VSS

AF12

VSS

AF14

VSS

AF16

VSS

AF19

VSS

AF22

VSS

AF25

VSS

AF28

VSS

AF31

VSS

AF4

VSS

AF7

VSS

AG17

VSS

AG20

VSS

AG23

VSS

AG26

VSS

AG29

VSS

AG9

VSS

AH13

VSS

AH15

VSS

AH18

VSS

AH21

VSS

AH24

VSS

AH27

VSS

AH30

VSS

AJ12

VSS

AJ14

VSS

AJ16

VSS

AJ19

VSS

AJ22

VSS

AJ25

VSS

AJ28

VSS

AJ3

VSS

AJ31

VSS

AJ6

VSS

AJ9

VSS

AK13

VSS

AK17

VSS

AK20

VSS

AK23

VSS

AK26

VSS

AK29

VSS

AL13

VSS

AL15

VSS

AL18

VSS

AL21

VSS

AL24

VSS

AL27

VSS

AL3

VSS

AL6

VSS

M19

VSS

P13

VSS

P19

VSS

T13

VSS

T19

<APU>

<APU>

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

FUSION 1.0

FUSION 1.0

FUSION 1.0

1

11 35Wednesday, August 17, 2011

11 35Wednesday, August 17, 2011

11 35Wednesday, August 17, 2011

of

of

of