MSI MS-7699 Schematics rev0A

5

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Title Page

MSI

MS_7699 Ver

D D

C C

CPU:

10

AMD AM3 AM3+

System Chipset:

AMD/ATI 760G/785G/880G
AMD/ATI RS710

On Board Chipset:

FINTEK Super I/O -- F71868AD
LAN -- RLT8111E COLAY 8105
HD Codec --ALC887/892

UPD720200F1-USB 3.0

ASM1061 SATA 6G

BIOS -- SPI ROM 8M

Cover Sheet 1
Block Diagram

AMD AM3 941

First Logical DDRIII DIMM

Second Logical DDRIII DIMM
AMD/ATI 760G/785G/880G

AMD/ATI SB710

Clock-Gen 9LPRS477DKLFT

PCI EXPRESS X16 & X 1 SLOT
PCI Slot 1&2&3
LPC-F71868AD / FDD / COM / LPT

FAN

LAN -- RLT8111E & RLT8105

Azalia Codec-ALC892

ASM1061 SATA 6G

UPD720200F1-USB 3.0

2
3,4,5
6
7

8,9,10,11,12

13,14,15,16,17

18
19

20
21

22

23

24
25

26

USB 3.0 Power & Connector

Main Memory:

USB connectors

DDR III X 4 (Max 32GB)

VGA & HDMI & DVI CONN

Expansion Slots:

B B

PCI-E X16 X1
PCI-E X1 X2

PCI 2.2 Slot X2

ACPI by UPI

PWM- UPI1601

VRM dirve

VCC_DDR&VCC1_1 NB

Clock Generator:

Controller--9LPRS477DKLFT

ATX/Front Panel/KB/EMI

EMI CAP

Mannual parts for BOM

PWM:

A A

UPI1601

5

4

Power OK MAP

POS MAP

Clock Distribution

Power Deliver Chart
Modify History

3

27
28

29
30

31

32
33
34
35
36

37

38

39,40
41

42

2

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

01 Cover Sheet

01 Cover Sheet

01 Cover Sheet

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

Date: Sheet of

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

of

142Friday, June 01, 2012

142Friday, June 01, 2012

142Friday, June 01, 2012

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Project RS-740/760 BLOCK DIAGRAM

DDRIII 800, 1066, 1333

D D

AMD
AM3

AM3 SOCKET

3,4,5

OUT

16x16 2.6GHZ(HT3)HyperTransport LINK

IN

128bit

DDRIII 800, 1066, 1333

128bit

UNBUFFERED
DDRIII DIMM1 DIMM2

UNBUFFERED
DDRIII DIMM3 DIMM4

DDRIII LOGICAL DIMM

6

7

ATI NB - RS760/740/880

HyperTransport LINK0 CPU I/F
1 16X PCIE VIDEO I/F

USB 2.0

1 4X PCIE I/F WITH SB
6 1X PCIE I/F

8,9,10,11,12

A-LINK

4X PCIE

ATI SB - SB710

USB2.0 (12)
SATA2 (4 PORTS)
AC97 2.3
HD AUDIO 1.0
ACPI 1.1
SPI I/F
PCI/PCI BRIDGE

13,14,15,16,17

Fintek SIO 71868AD

2X1 PCIE INTERFACE

AZALIA

SERIAL ATA 2.0

SPI Bus

LPC BUS

21

NEC7202A 4PORT
USB3.0

TPM Pin Header

26

29

ASM 1061
SATA6G

VIA RTL892/887

SATA#0~5

14

SPI ROM 8M

10

SATA#7~8

25

25

24

PCIE GFX x16

C C

REALTEK
RLT8111E&RLT8105EL

USB-11
REAR

23

USB-10
REAR

28

PCIE x1 SLOT119PCIE x1 SLOT119PCIE x1 SLOT1

USB-4USB-5

28

28

USB-7
FRONT FRONT

USB-6 USB-1

4X1 PCIE INTERFACE

28 28 28

19

USB-2USB-3
REARREARREARREAR

USB-0
FRONTFRONT

PCIE x16

19

28 282828

B B

PCI BUS

CLOCK GEN
9LPRS477

18

ACPI CONTROLLER

uPI

32

A A

CPU CORE POWER
NB CORE POWER
UPI1601
UPI 6282 UPI6281

CPU VLDT Power

RS760 CORE POWER

PCIE & SB POWER

DDR3 DRAM POWER

31

33

33

PCI SLOT 1

20

PCI SLOT 2

20

ATX CON & DUAL POWER

5

34

4

Parallel Port

21

3

KBD
MOUSE

21 21

SERIAL
PORT

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

02 BLOCK DIAGRAM

02 BLOCK DIAGRAM

02 BLOCK DIAGRAM

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

242Friday, June 01, 2012

242Friday, June 01, 2012

242Friday, June 01, 2012

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C4.7u16Y1206

C4.7u16Y1206

R137

R137

169R1%

169R1%

LDT_PWRGD13

R211

R211

39.2R1%

39.2R1%

CPU_STRAP_HI_E11
CPU_STRAP_LO_F11

R212

R212

39.2R1%

39.2R1%

RN5

RN5

THERM_SIC_R
THERM_SID_R

C97

C97

C0.22u16X

C0.22u16X

CPUCLKIN
CPUCLKIN#

LDT_STOP#10,13

LDT_RST#10,13

C89

C89

X_C1000p50X

X_C1000p50X

THERM_SIC
THERM_SID

R188 X_1KR0402R188 X_1KR0402

VCC_DDR

CORE_FB31
CORE_FB#31

TP14TP14

TP18TP18

R132 300R0402R132 300R0402
R133 300R0402R133 300R0402

AM3R2 need change to 1K

TP12TP12
TP15TP15
TP17TP17
TP11TP11
TP19TP19

TP16TP16

VCC_DDR

135

7

R123

R123
300R0402

300R0402

246

8

THERM_SIC_R 21
THERM_SID_R 21

C82

C82

LDT_PWRGD
LDT_STOP#

LDT_RST#

TP22TP22

CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS

CPU_DBREQ_L
CORE_FB

CORE_FB#
M_VDDIO_PWRGD
CPU_VDDR_SENSE

CPU_TEST25_H

CPU_TEST25_L

CPU_TEST19
CPU_TEST18

CPU_TEST17
CPU_TEST16
CPU_TEST15
CPU_TEST14
CPU_TEST12

CPU_RSVD3

X_C3300p50X0402

X_C3300p50X0402

CPU_PRESENT_L

CPU_M_VREF

THERM_SIC

HT_CADIN_H[15..0]8

D D

HT_CLKIN_H18

HT_CLKIN_L18

HT_CLKIN_H08

HT_CLKIN_L08

HT_CTLIN_H18

HT_CTLIN_L18

HT_CTLIN_H08

HT_CTLIN_L08

HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14

C C

B B

A A

HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8

HT_CADIN_H7
HT_CADIN_H6

HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0

IMC_TDI

IMC_TDI15

IMC_DBRDY15

IMC_DBRDY

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

IMC_TDO15

IMC_TCK

IMC_TCK15

HT_CADIN_L[15..0]8

HT_CADOUT_H[15..0]8

HT_CADOUT_L[15..0]8

N6

P6
N3
N2

V4

V5
U1

V1

U6

V6

T4

T5
R6

T6

P4

P5
M4
M5

L6
M6

K4

K5

J6

K6
U3

U2
R1

T1
R3
R2
N1

P1

L1
M1

L3

L2

J1

K1

J3

J2

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

CPU output pin:TDO,DBRDY ;OTHERS :INPUT

6

Q36

Q36

2

5

Q38

Q38

4

1

3

HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]

CPU1A

CPU1A

L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0

L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0

L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8

L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0

4

1

3

5

1
3
5
7

2

6

L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8

L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4

HT LINK

HT LINK

L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0

112233445566778

8

CPU_TDO
CPU_DBRDY

+1.8V_S0 +1.8V_S0

RN6

RN6

2
4
6
8

8P4R-10KR0402

8P4R-10KR0402

CPU_TDIIMC_TDO

CPU_TCK IMC_TMS

AD5
AD4
AD1
AC1

Y6
W6
W2
W3

Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4

Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1

IMC_DBREQ_L15

IMC_TMS15

L1

80/2A/B8L180/2A/B8

HT_CLKOUT_H1 8
HT_CLKOUT_L1 8
HT_CLKOUT_H0 8
HT_CLKOUT_L0 8

HT_CTLOUT_H1 8
HT_CTLOUT_L1 8
HT_CTLOUT_H0 8
HT_CTLOUT_L0 8

HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8

HT_CADOUT_H7
HT_CADOUT_L7HT_CADIN_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0

LDT_RST#

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

Q32

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

Q32

IMC_DBREQ_L

VDDA25VDDA_25

CPU_CLK18

CPU_CLK#18

IMC_CRST_L
IMC_TRST_LCPU_TRST_L

RN7

RN7

1
3
5
7

8P4R-10KR0402

8P4R-10KR0402

CPU_DBREQ_L

CPU_TMS

R187 X_1KR0402R187 X_1KR0402

2
4
6
8

VCC_DDR

4

6

1

3

Q37

Q37

5

2

5

2

4

6

1

3

THERM_SID

C99

C99

C3900p50X

C3900p50X

C98

C98

C3900p50X

C3900p50X

VCC_DDR

R182R182

VCC_DDR

AM3R2 remove

IMC_CRST_L 15
IMC_TRST_L 15

R198R198
R193R193

R183 1KR0402R183 1KR0402
R184 1KR0402R184 1KR0402

X_8P4R-1KR0402

X_8P4R-1KR0402

FOR AM3R2 need stuff 1K

CPU_TMS
CPU_TRST_L
CPU_TDI
CPU_TCK
CPU_DBREQ_L

C87

C87

VDDA25

ALERT_L

R134R134

CPUVID331
CPUVID231
CPUVID131

CPU_HOT

CPU_HOT 13

CPU1D

CPU1D

C10

VDDA_1

D10

VDDA_2

MISC.

A8
B8

C9
D8
C7

AL3

AL6
AK6
AK4
AL4

AL10
AJ10
AH10

AL9

A5
G2

G1

F3
E12
F12

AH11
AJ11

A10
B10
F10

E9
AJ7

F6

D6

E7

F8

C5
AH9

E5
AJ5
AH7
AJ6

C18
C20

F2
G24
G25
H25
L25
L26

LDT_PWRGD13

MISC.

CLKIN_H
CLKIN_L

PWROK
LDTSTOP_L
RESET_L

CPU_PRESENT_L

SIC
SID
SA0
ALERT_L

TDI
TRST_L
TCK
TMS

DBREQ_L
VDD_FB_H

VDD_FB_L
M_VDDIO_PWRGD
VDDR_SENSE
M_VREF

M_ZN
M_ZP

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9

TEST17
TEST16
TEST15
TEST14
TEST12

TEST7
TEST6
TEST3
TEST2

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

INT. MISC.

INT. MISC.

RSVD6
RSVD7
RSVD8

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

R74

R74

4.7KR0402

4.7KR0402

VCC_DDR

B

Q7

Q7
N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

CE

CORE_TYPE

SVC/VID3
SVD/VID2

PVIEN/VID1

THERMDC
THERMDA

THERMTRIP_L

PROCHOT_L

DBRDY

VDDIO_FB_H

VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L

PSI_L

HTREF1
HTREF0

TEST29_H
TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST28_H
TEST28_L

TEST27
TEST26
TEST10

TEST8

RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
RSVD15
RSVD16

G5
D2

VID5

D1

VID4

C1
E3
E2
E1

VID0

AG9
AG8
AK7
AL7

AK10

TDO

B6
AK11

AL11
G4
G3

F1
V8

V7

C11
D11

AK8
AH8
AJ9
AL8
AJ8

J10
H9
AK9
AK5
G7
D4

L30
L31
AD25
AE24
AE25
AJ18
AJ20
AK3

1KR0402

1KR0402

CPU_CORE_TYPE

CPUVID3
CPUVID2
CPUVID1

THERMDC_CPU
THERMDA_CPU

CPU_HOT

CPU_TDO

CPU_DBRDY

CPU_PSI_L
HTREF1

HTREF0

CPU_TEST29_H
CPU_TEST29_L

CPU_TEST24

CPU_TEST23

CPU_TEST22

CPU_TEST21
CPU_TEST20

CPU_TEST27
CPU_TEST26

VCC3

R85

R85

4.7KR0402

4.7KR0402

VCC_DDR

R78

R78

DDRPWRFB

R214 X_0R0402R214 X_0R0402

VCCP_NBFB 31
VCCP_NBFB# 31

TP21TP21

R199 X_1KR4R199 X_1KR4

TP20TP20

VCC_DDR

R201 X_300R4R201 X_300R4

R189 300R0402R189 300R0402

1K ohm FOR AM3R2

CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L

C51

C51

X_C100p50N0402

X_C100p50N0402

THERMDC_CPU 21
THERMDA_CPU 21

R138

R138

80.6R1%

80.6R1%

R185

R185

300R0402

300R0402

CPU_DBREQ_L

CPU_TEST25_H
CPU_TEST25_L

M_VDDIO_PWRGD

PWROK_PWM 31

1K ohm FOR AM3R2

CPU_THRIP_L#

TP13TP13

C172

C172

C1000p50X0402

C1000p50X0402

R194

R194

300R0402

300R0402

C94

C94
X_C0.1u25Y

X_C0.1u25Y

1K ohm FOR AM3R2

R186 10KR0402R186 10KR0402
R129 510R0402R129 510R0402
R131 X_510R0402R131 X_510R0402

R136 X_510R0402R136 X_510R0402
R135 510R0402R135 510R0402

R128 1KR0402R128 1KR0402

R191

R191

300R0402

300R0402

R190

R190
1KR0402

1KR0402

N-MMBT3904SOT23

N-MMBT3904SOT23

R195 44.2R1%R195 44.2R1%
R196 44.2R1%R196 44.2R1%

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

REF15

REF15

OPT

OPT

X_1KR

X_1KR

VCC_DDR

B

VCC_DDR

R205

R205

4.7KR0402

4.7KR0402

B

Q29

Q29

C E

C173

C173

C1000p50X0402

C1000p50X0402

46.4 ohm FOR AM3R2

R121

R121
15R1%

15R1%

R124

R124
15R1%

15R1%

C0.1u25Y0402-RH

C0.1u25Y0402-RH

RN4

RN4

1
3
5
7

8P4R-300R-RH

8P4R-300R-RH

1K ohm FOR AM3R2

REF16

REF16

OPT

OPT

X_848R 1K

X_848R 1K

R213

R213

4.7KR0402

4.7KR0402

Q33

Q33
N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

CE

CPU_THRIP# 15

TALERT# 14,21

VCCA_1V2

CPU_M_VREF

C92

C92

2

LDT_RST#

4

LDT_STOP#

6

LDT_PWRGD

8

REF17

REF17

OPT

OPT

X_46.4R

X_46.4R

TP10TP10

C86

C86
C1000p50X

C1000p50X

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet of

5

4

3

2

Date: Sheet of

MICRO-START INT'L CO.,LTD.

03 AM3 HT I/F,CTRL&DEBUG

03 AM3 HT I/F,CTRL&DEBUG

03 AM3 HT I/F,CTRL&DEBUG

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

342Friday, June 01, 2012

342Friday, June 01, 2012

342Friday, June 01, 2012

of

5

4

3

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1

MEM_MA_DQS_L[7..0]6,7 MEM_MB_DQS_L[7..0]6,7
MEM_MA_DQS_H[7..0]6,7

MEM_MA_DM[7..0]6,7

MEM_MA_ADD[15..0]6,7

5

MEM_MA_DATA[63..0]6,7

MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1

MEM_MA0_CS_L1
MEM_MA0_CS_L0

MEM_MA0_ODT1
MEM_MA0_ODT0

MEM_MA1_CS_L1
MEM_MA1_CS_L0

MEM_MA1_ODT1
MEM_MA1_ODT0

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_CKE1
MEM_MA_CKE0

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0

D D

MEM_MA1_CLK_H17
MEM_MA1_CLK_L17
MEM_MA0_CLK_H06
MEM_MA0_CLK_L06
MEM_MA1_CLK_H07
MEM_MA1_CLK_L07
MEM_MA0_CLK_H16
MEM_MA0_CLK_L16

MEM_MA0_CS_L16
MEM_MA0_CS_L06

MEM_MA0_ODT16

C C

B B

A A

MEM_MA0_ODT06
MEM_MA1_CS_L17

MEM_MA1_CS_L07
MEM_MA1_ODT17

MEM_MA1_ODT07

MEM_MA_CAS_L6,7
MEM_MA_WE_L6,7
MEM_MA_RAS_L6,7

MEM_MA_BANK26,7
MEM_MA_BANK16,7
MEM_MA_BANK06,7

MEM_MA_CKE16,7
MEM_MA_CKE06,7

MEM_MA_DQS_L[7..0] MEM_MB_DQS_L[7..0]
MEM_MA_DQS_H[7..0]
MEM_MA_DM[7..0]
MEM_MA_ADD[15..0]
MEM_MA_DATA[63..0]

CPU1B

CPU1B

AG21

MA_CLK_H7

AG20

MA_CLK_L7

AE20

MA_CLK_H6

AE19

MA_CLK_L6

U27

MA_CLK_H5

U26

MA_CLK_L5

V27

MA_CLK_H4

W27

MA_CLK_L4

W26

MA_CLK_H3

W25

MA_CLK_L3

U24

MA_CLK_H2

V24

MA_CLK_L2

G19

MA_CLK_H1

H19

MA_CLK_L1

G20

MA_CLK_H0

G21

MA_CLK_L0

AC25

MA0_CS_L1

AA24

MA0_CS_L0

AE28

MA0_ODT1

AC28

MA0_ODT0

AD27

MA1_CS_L1

AA25

MA1_CS_L0

AE27

MA1_ODT1

AC27

MA1_ODT0

E20

MA_RESET_L

AB25

MA_CAS_L

AB27

MA_WE_L

AA26

MA_RAS_L

N25

MA_BANK2

Y27

MA_BANK1

AA27

MA_BANK0

L27

MA_CKE1

M25

MA_CKE0

M27

MA_ADD15

N24

MA_ADD14

AC26

MA_ADD13

N26

MA_ADD12

P25

MA_ADD11

Y25

MA_ADD10

N27

MA_ADD9

R24

MA_ADD8

P27

MA_ADD7

R25

MA_ADD6

R26

MA_ADD5

R27

MA_ADD4

T25

MA_ADD3

U25

MA_ADD2

T27

MA_ADD1

W24

MA_ADD0

AD15

MA_DQS_H7

AE15

MA_DQS_L7

AG18

MA_DQS_H6

AG19

MA_DQS_L6

AG24

MA_DQS_H5

AG25

MA_DQS_L5

AG27

MA_DQS_H4

AG28

MA_DQS_L4

D29

MA_DQS_H3

C29

MA_DQS_L3

C25

MA_DQS_H2

D25

MA_DQS_L2

E19

MA_DQS_H1

F19

MA_DQS_L1

F15

MA_DQS_H0

G15

MA_DQS_L0

AF15

MA_DM7

AF19

MA_DM6

AJ25

MA_DM5

AH29

MA_DM4

B29

MA_DM3

E24

MA_DM2

E18

MA_DM1

H15

MA_DM0

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12

MEM CHA

MEM CHA

MA_DATA11
MA_DATA10

MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0

MA_DQS_H8

MA_DQS_L8

MA_DM8

MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0

MA_EVENT_L

4

AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14

J28
J27

J25
K25

J26
G28
G27
L24
K27
H29
H27

W30

MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20

MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10

MEM_MA_DATA9

MEM_MA_DATA8

MEM_MA_DATA7

MEM_MA_DATA6

MEM_MA_DATA5

MEM_MA_DATA4

MEM_MA_DATA3

MEM_MA_DATA2

MEM_MA_DATA1

MEM_MA_DATA0

1KR0402

1KR0402

MEM_MA_EVENT_L

R179

R179

MEM_MA_EVENT_L 6,7

MEM_MB_DQS_H[7..0]6,7

MEM_MB_DM[7..0]6,7
MEM_MB_ADD[15..0]6,7
MEM_MB_DATA[63..0]6,7

MEM_MB1_CLK_H17
MEM_MB1_CLK_L17
MEM_MB0_CLK_H06
MEM_MB0_CLK_L06
MEM_MB1_CLK_H07
MEM_MB1_CLK_L07
MEM_MB0_CLK_H16
MEM_MB0_CLK_L16

MEM_MB0_CS_L16
MEM_MB0_CS_L06

MEM_MB0_ODT16
MEM_MB0_ODT06

MEM_MB1_CS_L17
MEM_MB1_CS_L07

MEM_MB1_ODT17
MEM_MB1_ODT07

MEM_MB_RESET#6,7MEM_MA_RESET#6,7
MEM_MB_CAS_L6,7

MEM_MB_WE_L6,7
MEM_MB_RAS_L6,7

MEM_MB_BANK26,7
MEM_MB_BANK16,7
MEM_MB_BANK06,7

MEM_MB_CKE16,7
MEM_MB_CKE06,7

3

MEM_MB_DQS_H[7..0]
MEM_MB_DM[7..0]
MEM_MB_ADD[15..0]
MEM_MB_DATA[63..0]

MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1

MEM_MB0_CS_L1
MEM_MB0_CS_L0

MEM_MB0_ODT1
MEM_MB0_ODT0

MEM_MB1_CS_L1
MEM_MB1_CS_L0

MEM_MB1_ODT1
MEM_MB1_ODT0

MEM_MB_RESET#MEM_MA_RESET#
MEM_MB_CAS_L

MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_CKE1
MEM_MB_CKE0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0

AJ19

AK19

AL19
AL18

W29
W28

W31

AE30
AC31

AF31

AD29
AE29

AB31
AG31

AD31

AC29
AC30
AB29

AA31
AA28

AE31

AA29

AA30
AK13

AJ13

AK17

AJ17

AK23

AL23
AL28
AL29

AJ14

AH17

AJ23

AK29

U31
U30

Y31
Y30

C19
D19

B19

N31

M31
M29

N28
N29

N30
P29

P31
R29
R28
R31
R30
T31
T29
U29
U28

D31
C31
C24
C23
D17
C17
C14
C13

C30
A23
B17
B13

V31
A18

A19

CPU1C

CPU1C

MB_CLK_H7
MB_CLK_L7
MB_CLK_H6
MB_CLK_L6
MB_CLK_H5
MB_CLK_L5
MB_CLK_H4
MB_CLK_L4
MB_CLK_H3
MB_CLK_L3
MB_CLK_H2
MB_CLK_L2
MB_CLK_H1
MB_CLK_L1
MB_CLK_H0
MB_CLK_L0

MB0_CS_L1
MB0_CS_L0

MB0_ODT1
MB0_ODT0

MB1_CS_L1
MB1_CS_L0

MB1_ODT1
MB1_ODT0

MB_RESET_L
MB_CAS_L

MB_WE_L
MB_RAS_L

MB_BANK2
MB_BANK1
MB_BANK0

MB_CKE1
MB_CKE0

MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0

MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0

MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

MEM CHB

MEM CHB

2

MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10

MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0

MB_DQS_H8

MB_DQS_L8

MB_DM8

MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0

MB_EVENT_L

AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13

J31
J30

J29
K29

K31
G30
G29
L29
L28
H31
G31

V29

MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0

VCC_DDRVCC_DDR

R176

R176
1KR0402

MEM_MB_EVENT_L

Title

Title

Title

04 AM3 DDR MEMORY I/F

04 AM3 DDR MEMORY I/F

04 AM3 DDR MEMORY I/F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

1KR0402

MEM_MB_EVENT_L 6,7

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

442Friday, June 01, 2012

442Friday, June 01, 2012

442Friday, June 01, 2012

of

of

of

VCCP

D D

C C

B B

B3
C2
C4
D3
D5
E4
E6
F5

F7
G6
G8

H7

H11
H23

J8
J12
J14
J16
J18
J20
J22
J24

K7

K9

K11
K13
K15
K17
K19
K21
K23

L4

L5

L8

L10
L12
L14
L16
L18
L20
L22

M2
M3
M7
M9

M11
M13
M15
M17
M19
M21
M23

N8

N10
N12
N14
N16
N18
N20
N22

P7

P9

P11
P13
P15
P17
P19
P21
P23

R4

R5

R8

R10
R12
R14
R16
R18
R20
R22

T2

T3

T7

T9

T11
T13

CPU1E

CPU1E

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
VDD_63
VDD_64
VDD_65
VDD_66
VDD_67
VDD_68
VDD_69
VDD_70
VDD_71
VDD_72
VDD_73
VDD_74
VDD_75
VDD_76
VDD_77
VDD_78
VDD_79
VDD_80
VDD_81
VDD_82
VDD_83
VDD_84
VDD_85

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

5

A3

VSS_1

A7

VSS_2

A9

VSS_3

A11

VSS_4

B4

VSS_5

B9

VSS_6

B11

VSS_7

B14

VSS_8

B16

VSS_9

B18

VSS_10

B20

VSS_11

B22

VSS_12

B24

VSS_13

B26

VSS_14

B28

VSS_15

B30

VSS_16

C3

VSS_17

D14

VSS_18

D16

VSS_19

D18

VSS_20

D20

VSS_21

D22

VSS_22

D24

VSS_23

D26

VSS_24

D28

VSS_25

D30

VSS_26

E11

VSS_27

F4

VSS_28

F14

VSS_29

F16

VSS_30

F18

VSS_31

F20

VSS_32

F22

VSS_33

F24

VSS_34

F26

VSS_35

F28

VSS_36

F30

VSS_37

G9

VSS_38

G11

VSS_39

H8

VSS_40

H10

VSS_41

H12

VSS_42

H14

VSS_43

H16

VSS_44

H18

VSS_45

H24

VSS_46

H26

VSS_47

H28

VSS_48

H30

VSS_49

J4

VSS_50

J5

VSS_51

POWER/GND1

POWER/GND1

J7

VSS_52

J9

VSS_53

J11

VSS_54

J13

VSS_55

J15

VSS_56

J17

VSS_57

J19

VSS_58

J21

VSS_59

J23

VSS_60

K2

VSS_61

K3

VSS_62

K8

VSS_63

K10

VSS_64

K12

VSS_65

K14

VSS_66

K16

VSS_67

K18

VSS_68

K20

VSS_69

K22

VSS_70

K24

VSS_71

K26

VSS_72

K28

VSS_73

K30

VSS_74

L7

VSS_75

L9

VSS_76

L11

VSS_77

L13

VSS_78

L15

VSS_79

L17

VSS_80

L19

VSS_81

L21

VSS_82

L23

VSS_83

M8

VSS_84

M10

VSS_85

VCCP

T15
T17
T19
T21
T23

U8
U10
U12
U14
U16
U18
U20
U22

V9

V11
V13
V15
V17
V19
V21
V23
W4
W5

W8
W10
W12
W14
W16
W18
W20
W22

Y2
Y3
Y7

Y9
Y11
Y13
Y15
Y17
Y19
Y21
Y23

AA8
AA10
AA12
AA14
AA16
AA18
AA20
AA22

AB7

AB9
AB11
AB13
AB15
AB17
AB19
AB21
AB23

AC4

AC5

AC8
AC10
AC12
AC14
AC16
AC18
AC20
AC22

AD2

AD3

AD7

AD9
AD11
AD23
AE10
AE12

AF7

AF9
AF11

AG4

AG5

AG7

AH2

AH3

CPU1F

CPU1F

VDD_86
VDD_87
VDD_88
VDD_89
VDD_90
VDD_91
VDD_92
VDD_93
VDD_94
VDD_95
VDD_96
VDD_97
VDD_98
VDD_99
VDD_100
VDD_101
VDD_102
VDD_103
VDD_104
VDD_105
VDD_106
VDD_107
VDD_108
VDD_109
VDD_110
VDD_111
VDD_112
VDD_113
VDD_114
VDD_115
VDD_116
VDD_117
VDD_118
VDD_119
VDD_120
VDD_121
VDD_122
VDD_123
VDD_124
VDD_125
VDD_126
VDD_127
VDD_128
VDD_129
VDD_130
VDD_131
VDD_132
VDD_133
VDD_134
VDD_135
VDD_136
VDD_137
VDD_138
VDD_139
VDD_140
VDD_141
VDD_142
VDD_143
VDD_144
VDD_145
VDD_146
VDD_147
VDD_148
VDD_149
VDD_150
VDD_151
VDD_152
VDD_153
VDD_154
VDD_155
VDD_156
VDD_157
VDD_158
VDD_159
VDD_160
VDD_161
VDD_162
VDD_163
VDD_164
VDD_165
VDD_166
VDD_167
VDD_168
VDD_169
VDD_170

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

4

M12

VSS_86

M14

VSS_87

M16

VSS_88

M18

VSS_89

M20

VSS_90

M22

VSS_91

N4

VSS_92

N5

VSS_93

N7

VSS_94

N9

VSS_95

N11

VSS_96

N13

VSS_97

N15

VSS_98

N17

VSS_99

N19

VSS_100

N21

VSS_101

N23

VSS_102

P2

VSS_103

P3

VSS_104

P8

VSS_105

P10

VSS_106

P12

VSS_107

P14

VSS_108

P16

VSS_109

P18

VSS_110

P20

VSS_111

P22

VSS_112

R7

VSS_113

R9

VSS_114

R11

VSS_115

R13

VSS_116

R15

VSS_117

R17

VSS_118

R19

VSS_119

R21

VSS_120

R23

VSS_121

T8

VSS_122

T10

VSS_123

T12

VSS_124

T14

VSS_125

T16

VSS_126

T18

VSS_127

T20

VSS_128

T22

VSS_129

U4

VSS_130

U5

VSS_131

U7

VSS_132

U9

VSS_133

U11

VSS_134

U13

VSS_135

POWER/GND2

POWER/GND2

U15

VSS_136

U17

VSS_137

U19

VSS_138

U21

VSS_139

U23

VSS_140

V2

VSS_141

V3

VSS_142

V10

VSS_143

V12

VSS_144

V14

VSS_145

V16

VSS_146

V18

VSS_147

V20

VSS_148

V22

VSS_149

W7

VSS_150

W9

VSS_151

W11

VSS_152

W13

VSS_153

W15

VSS_154

W17

VSS_155

W19

VSS_156

W21

VSS_157

W23

VSS_158

Y8

VSS_159

Y10

VSS_160

Y12

VSS_161

Y14

VSS_162

Y16

VSS_163

Y18

VSS_164

Y20

VSS_165

Y22

VSS_166

AA4

VSS_167

AA5

VSS_168

AA7

VSS_169

AA9

VSS_170

VCCP_NB

CPU1G

CPU1G

A4

VDDNB_1

A6

VDDNB_2

B5

VDDNB_3

B7

VDDNB_4

C6

VDDNB_5

C8

VDDNB_6

D7

VDDNB_7

D9

VDDNB_8

E8

VDDNB_9

E10

VDDNB_10

F9

VDDNB_11

F11

VDDNB_12

G10

VDDNB_13

G12

VDDNB_14

B2

NP/RSVD

H20

NP/VSS1

AE7

NP/VSS2

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

VCC_DDR VCCPVCCP VCCP_NB

X_C2.2u6.3X5

X_C2.2u6.3X5

VCC_DDR

C140

C140

C0.1u25Y0402-RH

C0.1u25Y0402-RH

VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202

POWER/GND3

POWER/GND3

VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214

BOTTOM

C695

C695

X_C2.2u6.3X5

X_C2.2u6.3X5

C137

C137

C133

C133

C171

C171

C0.1u25Y0402-RH

C0.1u25Y0402-RH

C0.1u25Y0402-RH

C0.1u25Y0402-RH

C1000p50X0402

C1000p50X0402

3

CPU1H

AJ1
AJ2
AJ3
AJ4

A12
B12
C12
D12

M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28

Y29
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30

VCCP_NB CAPFOR EMI

VCCP_NB

C78 C0.22u16XC78 C0.22u16X

C79 C0.22u16XC79 C0.22u16X

VCCP_NB

C76 C4.7u10Y0805C76 C4.7u10Y0805

VCCP_NB

C109 C10u6.3X50805C109 C10u6.3X50805

C70 X_C10u6.3X50805C70 X_C10u6.3X50805

VCCP_NB

C665 C22u6.3X1206C665 C22u6.3X1206

C108 X_C22u6.3X1206C108 X_C22u6.3X1206

CPU1H

VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4

VDDR_1
VDDR_2
VDDR_3
VDDR_4

VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29

ZIF-SOCKET941-RH

ZIF-SOCKET941-RH

VCC_DDR

C174

C174

X_C2200p10X0402

X_C2200p10X0402

C180

C180

C2200p10X0402

C2200p10X0402

C666

C666
X_C0.01u50X

X_C0.01u50X

VCCA_1V2

CPU_VDDR_B

VCC_DDR

AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16

C148

C148

C183

C183

X_C2200p10X0402

X_C2200p10X0402

X_C2200p10X0402

C116

C693

C693

C116

X_C2.2u6.3X5

X_C2.2u6.3X5

C131

C131

C300

C300

C167

C167

C470p50X0402

C470p50X0402

X_C180p50N0402

X_C180p50N0402

C470p50X0402

C470p50X0402

X_C2200p10X0402

VCC_DDR

C132

C132

C134

C134

C168

C168

C470p50X0402

C470p50X0402

C1000p50X0402

C1000p50X0402

C470p50X0402

C470p50X0402

bottom

2

VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4

VDDR_5
VDDR_6
VDDR_7
VDDR_8
VDDR_9

VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230

POWER/GND4

POWER/GND4

VSS_231
VSS_232
VSS_233
VSS_234
VSS_235
VSS_236
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242

VCCP_NB

C88 C180p50N0402C88 C180p50N0402

VCCP_NB

C664 C0.01u50XC664 C0.01u50X

C77 C0.01u50XC77 C0.01u50X

C117 X_C0.01u50XC117 X_C0.01u50X

1

VLDT_RUN_B

H1
H2
H5
H6

CPU_VDDR

AG12
AH12
AJ12
AK12
AL12

AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
AK20
AK22
AK24
AK26
AK28
AK30
AL5

bottom

C126

C126

C10u6.3X50805

C10u6.3X50805

far VDDR 4pin

CPU_VDDR_B

C129

C129

C0.01u50X

C0.01u50X

C105 C0.01u50XC105 C0.01u50X

C96 X_C0.01u50XC96 X_C0.01u50X

C102 C0.22u16XC102 C0.22u16X

C90 C4.7u10Y0805C90 C4.7u10Y0805

C84 C4.7u10Y0805C84 C4.7u10Y0805

C80 X_C4.7u10Y0805C80 X_C4.7u10Y0805

C85 X_C4.7u10Y0805C85 X_C4.7u10Y0805

CPU_VDDR CAP

C130

C130

X_C0.01u50X

X_C0.01u50X

C128

C128

X_C0.01u50X

X_C0.01u50X

near VDDR 5pin

CPU_VDDR

bottom

C196 C0.01u50XC196 C0.01u50X

C190 C0.22u16XC190 C0.22u16X

C199 X_C0.22u16XC199 X_C0.22u16X

C188 C0.22u16XC188 C0.22u16X

C218 X_C0.22u16XC218 X_C0.22u16X

C181 C4.7u10Y0805C181 C4.7u10Y0805

C216 X_C4.7u10Y0805C216 X_C4.7u10Y0805

C215 X_C4.7u10Y0805C215 X_C4.7u10Y0805

C178 C4.7u10Y0805C178 C4.7u10Y0805

C214 X_C10u6.3X50805C214 X_C10u6.3X50805

C219 C22u6.3X1206C219 C22u6.3X1206

VCCA_1V2

VCCA_1V2

A A

5

VCCA_1V2 CAP

C169 C4.7u10Y0805C169 C4.7u10Y0805

C182 X_C4.7u10Y0805C182 X_C4.7u10Y0805

C176 C10u6.3X50805C176 C10u6.3X50805

C179 C10u6.3X50805C179 C10u6.3X50805

C227 X_C10u6.3X50805C227 X_C10u6.3X50805

VCCA_1V2

4

C189 X_C180p50N0402C189 X_C180p50N0402

C186 C180p50N0402C186 C180p50N0402

VCC_DDR

C667 X_C10u6.3X50805C667 X_C10u6.3X50805

VCC_DDR

C676 X_C22u6.3X1206C676 X_C22u6.3X1206

C671 C22u6.3X1206C671 C22u6.3X1206

C685 C22u6.3X1206C685 C22u6.3X1206

C681 X_C22u6.3X1206C681 X_C22u6.3X1206

bottom

VCC_DDR

C294 C0.22u16XC294 C0.22u16X

C678 C0.22u16XC678 C0.22u16X

VCC_DDR

C185 X_C4.7u10Y0805C185 X_C4.7u10Y0805

C694 X_C4.7u10Y0805C694 X_C4.7u10Y0805

C154 X_C4.7u10Y0805C154 X_C4.7u10Y0805

C689 C4.7u10Y0805C689 C4.7u10Y0805

3

VCC_DDR CAP

VCC_DDR

C177 C180p50N0402C177 C180p50N0402

C175 C180p50N0402C175 C180p50N0402

VCC_DDR

C690 C0.01u50XC690 C0.01u50X

C679 C0.01u50XC679 C0.01u50X

bottom

VCCP

C692 C22u6.3X50805-RHC692 C22u6.3X50805-RH
C682 C22u6.3X50805-RHC682 C22u6.3X50805-RH
C669 C22u6.3X50805-RHC669 C22u6.3X50805-RH
C673 C22u6.3X50805-RHC673 C22u6.3X50805-RH
C680 C22u6.3X50805-RHC680 C22u6.3X50805-RH
C677 C22u6.3X50805-RHC677 C22u6.3X50805-RH
C674 C22u6.3X50805-RHC674 C22u6.3X50805-RH
C684 C22u6.3X50805-RHC684 C22u6.3X50805-RH
C670 C22u6.3X50805-RHC670 C22u6.3X50805-RH
C686 C22u6.3X50805-RHC686 C22u6.3X50805-RH
C688 C22u6.3X50805-RHC688 C22u6.3X50805-RH

C713 C22u6.3X50805-RHC713 C22u6.3X50805-RH
C714 C22u6.3X50805-RHC714 C22u6.3X50805-RH

2

VCCP

C707 C22u6.3X50805-RHC707 C22u6.3X50805-RH
C708 C22u6.3X50805-RHC708 C22u6.3X50805-RH
C709 C22u6.3X50805-RHC709 C22u6.3X50805-RH
C710 C22u6.3X50805-RHC710 C22u6.3X50805-RH
C711 C22u6.3X50805-RHC711 C22u6.3X50805-RH
C712 C22u6.3X50805-RHC712 C22u6.3X50805-RH

VCCP

C123 X_C22u6.3X50805C123 X_C22u6.3X50805
C121 X_C22u6.3X50805C121 X_C22u6.3X50805
C210 C22u6.3X50805C210 C22u6.3X50805
C125 C10u6.3X50805C125 C10u6.3X50805
C193 X_C22u6.3X50805C193 X_C22u6.3X50805
C145 X_C22u6.3X50805C145 X_C22u6.3X50805
C687 C22u6.3X50805C687 C22u6.3X50805

VCCP

C675 C180p50N0402C675 C180p50N0402

VCCP

C668 C0.01u50XC668 C0.01u50X

C691 C0.01u50XC691 C0.01u50X

VCCP

C672 C0.22u16XC672 C0.22u16X

C683 C0.22u16XC683 C0.22u16X

VCCP

C141 X_C22u10Y0805C141 X_C22u10Y0805

C136 X_C22u10Y0805C136 X_C22u10Y0805

C696 C4.7u10Y0805C696 C4.7u10Y0805

bottom

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

MICRO-START INT'L CO.,LTD.

05 AM3 PWR & GND

05 AM3 PWR & GND

05 AM3 PWR & GND

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

542Friday, June 01, 2012

542Friday, June 01, 2012

542Friday, June 01, 2012

VCCP CAP

5

10

12
13
18
19

21
22
27
28

30
31
36
37

81
82
87
88

90
91
96
97

99

11
14
17
20
23
26
29
32
35
38
41
44
47
80
83
86
89
92
95
98

3
4
9

2
5
8

DIMM1

DIMM1

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

MEM_MA_DQS_H[7..0]
MEM_MA_DQS_L[7..0]
MEM_MA_DM[7..0]
MEM_MA_ADD[15..0]
MEM_MA_DATA[63..0]

54

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

VSS

VSS

VSS

VSS

107

110

113

116

119

VCC3

C228

C228

X_C0.1u16Y0402

X_C0.1u16Y0402

VTT_DDRVCC_DDR

MEM_MA_EVENT_L

48

187

170

173

176

VDD

VDD

DDR3

DDR3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

121

VSS

124

127

130

133

136

139

142

145

148

236

179

182

183

186

189

191

194

197

120

VDD

VDD

VDD

VSS

VSS

VSS

151

154

157

VTT

VDD

VDD

VDD

VDD

VDD

VDDSPD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

160

163

166

199

202

205

208

211

214

198

167

53

79

240

68

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

A10/AP

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

DM0/DQS9

NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

ODT0
ODT1
CKE0
CKE1
CS0#
CS1#

RAS#
CAS#

RESET#

CK0#

CK1(NU)

CK1#(NU)

VREFDQ

VREFCA

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

MEC1

217

220

223

226

229

232

235

239

MEC1

MEC2

MEM_MA_DQS_H[7..0]4,7
MEM_MA_DQS_L[7..0]4,7

MEM_MA_DM[7..0]4,7
MEM_MA_ADD[15..0]4,7
MEM_MA_DATA[63..0]4,7

D D

MEM_MA_DATA0 MEM_MA_ADD0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31

C C

B B

MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

122
123
128
129

131
132
137
138

140
141
146
147

149
150
155
156

200
201
206
207

209
210
215
216

100
105
106
218
219
224
225
108
109
114
115
227
228
233
234

101
104

188

A0

181

FREE4

A1

61

A2

180

A3

59

A4

58

A5

178

A6

56

A7

177

A8

175

A9

70
55

A11

174

A12

196

A13

172

A14

171

A15

39

CB0

40

CB1

45

CB2

46

CB3

158

CB4

159

CB5

164

CB6

165

CB7

7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42

125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162

195
77
50
169
193
76
71

BA0

190

BA1

52

BA2

73

WE#

192
74
168

184

CK0

185
63
64

1
67
118

SCL

238

SDA

237

SA1

117

SA0

MEC2

MEC3

DDRIII-240P_BLUE-RH

DDRIII-240P_BLUE-RH

MEC3

4

MEM_MA_EVENT_L 4,7

MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2

MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA_RESET#

MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1

VDDR_VREF_DQ

VDDR_VREF_CA
SCL0
SDA0

MEM_MA0_ODT0 4
MEM_MA0_ODT1 4
MEM_MA_CKE0 4,7
MEM_MA_CKE1 4,7
MEM_MA0_CS_L0 4
MEM_MA0_CS_L1 4
MEM_MA_BANK0 4,7
MEM_MA_BANK1 4,7
MEM_MA_BANK2 4,7

MEM_MA_WE_L 4,7
MEM_MA_RAS_L 4,7
MEM_MA_CAS_L 4,7
MEM_MA_RESET# 4,7

MEM_MA0_CLK_H0 4
MEM_MA0_CLK_L0 4
MEM_MA0_CLK_H1 4
MEM_MA0_CLK_L1 4

VDDR_VREF_DQ

VDDR_VREF_CA

SCL0 7,15,18,30,31
SDA0 7,15,18,30,31

3

VCC3

Y

D17

D17
X_1PS226_SOT23

SCL0

SDA0

VCC_DDR

R79

R79
15R1%

15R1%

R83

R83
15R1%

15R1%

VCC_DDR

R159

R159
15R1%

15R1%

R163

R163
15R1%

15R1%

VDDR_VREF_DQ

VDDR_VREF_DQ VDDR_VREF_CA

C44

C44

C52

C52

X_C0.1u16Y0402

X_C0.1u16Y0402

X_C1u10X

X_C1u10X

Z

VCC3

Z

C43

C43

X_C0.1u25Y0402-RH

X_C0.1u25Y0402-RH

VDDR_VREF_DQ

C49

C49
C0.1u25Y0402-RH

C0.1u25Y0402-RH

C155

C155

X_C0.1u25Y0402-RH

X_C0.1u25Y0402-RH

VDDR_VREF_CA

C162

C162
C0.1u25Y0402-RH

C0.1u25Y0402-RH

VDDR_VREF_CA

X_1PS226_SOT23

X

Y

D18

D18
X_1PS226_SOT23

X_1PS226_SOT23

X

VDDR_VREF_DQ

C45

C45
C1000p16X0402

C1000p16X0402

VDDR_VREF_CA

C166

C166

C0.1u16Y0402

C0.1u16Y0402

C159

C159
C1000p16X0402

C1000p16X0402

C152

C152
X_C1u10X

X_C1u10X

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

2

3
4
9

2
5
8

DIMM3

DIMM3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC_DDR

MEM_MB_DQS_H[7..0]
MEM_MB_DQS_L[7..0]
MEM_MB_DM[7..0]
MEM_MB_ADD[15..0]
MEM_MB_DATA[63..0]

54

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

VSS

VSS

VSS

VSS

107

110

113

116

119

121

VCC3

C265

C265

C0.1u16Y0402

C0.1u16Y0402

VTT_DDR

170

173

176

VDD

VDD

DDR3

DDR3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

124

127

130

133

136

139

142

145

148

236

179

182

183

186

189

191

194

197

120

VDD

VDD

VSS

VSS

151

154

157

VTT

VDD

VDD

VDD

VDD

VDD

VDD

VDDSPD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

160

163

166

199

202

205

208

211

214

MEM_MB_EVENT_L

48

187

198

167

53

79

240

68

VTT

VSS

217

220

A0

RSVD

FREE1

FREE249FREE3

FREE4

A1
A2

NC/TEST4

NC/PAR_IN

A3

NC/ERR_OUT

A4
A5
A6
A7
A8
A9

A10/AP

A11
A12
A13
A14
A15

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

DM0/DQS9

NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

ODT0
ODT1
CKE0
CKE1

CS0#
CS1#

BA0
BA1
BA2

WE#
RAS#
CAS#

RESET#

CK0

CK0#

CK1(NU)

CK1#(NU)

VREFDQ
VREFCA

SCL
SDA
SA1
SA0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

MEC1

MEC2

MEC3

DDRIII-240P_BLUE-RH

DDRIII-240P_BLUE-RH

223

226

229

232

235

239

MEC1

MEC2

MEC3

188
181
61
180
59
58
178
56
177
175
70
55
174
196
172
171

39
40
45
46
158
159
164
165

7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42

125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162

MEM_MB0_ODT0

195

MEM_MB0_ODT1

77

MEM_MB_CKE0

50

MEM_MB_CKE1

169

MEM_MB0_CS_L0

193

MEM_MB0_CS_L1

76

MEM_MB_BANK0

71

MEM_MB_BANK1

190

MEM_MB_BANK2

52

MEM_MB_WE_L

73

MEM_MB_RAS_L

192

MEM_MB_CAS_L

74

MEM_MB_RESET#

168

MEM_MB0_CLK_H0

184

MEM_MB0_CLK_L0

185

MEM_MB0_CLK_H1

63

MEM_MB0_CLK_L1

64
1

67
118
238
237
117

MEM_MB_EVENT_L 4,7

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

VDDR_VREF_DQ
VDDR_VREF_CA
SCL0
SDA0

VCC3

MEM_MB_DQS_H[7..0]4,7
MEM_MB_DQS_L[7..0]4,7

MEM_MB_DM[7..0]4,7

MEM_MB_ADD[15..0]4,7

MEM_MB_DATA[63..0]4,7

10
122
123
128
129

12

13

18

19
131
132
137
138

21

22

27

28
140
141
146
147

30

31

36

37
149
150
155
156

81

82

87

88
200
201
206
207

90

91

96

97
209
210
215
216

99
100
105
106
218
219
224
225
108
109
114
115
227
228
233
234

11

14

17

20

23

26

29

32

35

38

41

44

47

80

83

86

89

92

95

98
101
104

1

MEM_MB0_ODT0 4

MEM_MB0_ODT1 4
MEM_MB_CKE0 4,7
MEM_MB_CKE1 4,7
MEM_MB0_CS_L0 4
MEM_MB0_CS_L1 4
MEM_MB_BANK0 4,7
MEM_MB_BANK1 4,7
MEM_MB_BANK2 4,7

MEM_MB_WE_L 4,7
MEM_MB_RAS_L 4,7
MEM_MB_CAS_L 4,7
MEM_MB_RESET# 4,7

MEM_MB0_CLK_H0 4
MEM_MB0_CLK_L0 4
MEM_MB0_CLK_H1 4
MEM_MB0_CLK_L1 4

SCL0 7,15,18,30,31
SDA0 7,15,18,30,31

ADDRESS A0

A A

5

VTT_DDR

C318 X_C4.7u6.3X5C318 X_C4.7u6.3X5
C324 X_C4.7u6.3X5C324 X_C4.7u6.3X5

VTT_DDR

C316 C0.1u16Y0402C316 C0.1u16Y0402
C239 X_C0.1u16Y0402C239 X_C0.1u16Y0402

C238 C0.1u16Y0402C238 C0.1u16Y0402

4

3

ADDRESS A2

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet of

MICRO-START INT'L CO.,LTD.

06 First Logical DDR DIMM

06 First Logical DDR DIMM

06 First Logical DDR DIMM

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

642Friday, June 01, 2012

of

642Friday, June 01, 2012

of

642Friday, June 01, 2012

5

MEM_MA_DQS_H[7..0]4,6
MEM_MA_DQS_L[7..0]4,6

MEM_MA_DM[7..0]4,6
MEM_MA_ADD[15..0]4,6

MEM_MA_DATA[63..0]4,6

MEM_MA_DQS_H[7..0]
MEM_MA_DQS_L[7..0]
MEM_MA_DM[7..0]
MEM_MA_ADD[15..0]
MEM_MA_DATA[63..0]

VCC3

4

3

MEM_MB_DQS_L[7..0]4,6
MEM_MB_DQS_H[7..0]4,6

MEM_MB_DM[7..0]4,6

MEM_MB_ADD[15..0]4,6

MEM_MB_DATA[63..0]4,6

MEM_MB_DQS_L[7..0]
MEM_MB_DQS_H[7..0]
MEM_MB_DM[7..0]
MEM_MB_ADD[15..0]
MEM_MB_DATA[63..0]

2

VCC3

1

D D

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26

C C

B B

A A

MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

VCC_DDR

54

DIMM2

DIMM2

3

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

DQ0

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

VSS

VSS

VSS

VSS

VSS

107

110

113

116

119

170

173

176

179

182

VDD

VDD

VDD

VDD

DDR3

DDR3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

121

124

127

130

133

136

139

142

145

148

151

154

VTT_DDR

236

183

186

189

191

194

197

VDD

VDD

VDD

VDD

VDD

VDD

VDDSPD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

157

160

163

166

199

202

205

208

211

C226

C226

C0.1u16Y0402

C0.1u16Y0402

MEM_MA_EVENT_L

53

120

240

167

48

187

198

68

79

VTT

VTT

RSVD

FREE1

FREE249FREE3

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

A10/AP

DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#

DM0/DQS9

NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ

VREFCA

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

MEC1

214

217

220

223

226

229

232

235

239

MEC1

188

A0

181

FREE4

A1

61

A2

180

A3

59

A4

58

A5

178

A6

56

A7

177

A8

175

A9

70
55

A11

174

A12

196

A13

172

A14

171

A15

39

CB0

40

CB1

45

CB2

46

CB3

158

CB4

159

CB5

164

CB6

165

CB7

7

DQS0

6
16

DQS1

15
25

DQS2

24
34

DQS3

33
85

DQS4

84
94

DQS5

93
103

DQS6

102
112

DQS7

111
43

DQS8

42
125

126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162

195

ODT0

77

ODT1

50

CKE0

169

CKE1

193

CS0#

76

CS1#

71

BA0

190

BA1

52

BA2

73

WE#

192

RAS#

74

CAS#

168
184

CK0

185

CK0#

63
64

1
67
118

SCL

238

SDA

237

SA1

117

SA0

MEC2

MEC3

ZIF-DDRIII240P-RH

ZIF-DDRIII240P-RH

MEC2

MEC3

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA1_ODT0
MEM_MA1_ODT1
MEM_MA_CKE0
MEM_MA_CKE1
MEM_MA1_CS_L0
MEM_MA1_CS_L1
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2

MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA_RESET#

MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1

VDDR_VREF_DQ

VDDR_VREF_CA
SCL0
SDA0

MEM_MA1_ODT0 4

MEM_MA1_ODT1 4
MEM_MA_CKE0 4,6
MEM_MA_CKE1 4,6
MEM_MA1_CS_L0 4
MEM_MA1_CS_L1 4
MEM_MA_BANK0 4,6
MEM_MA_BANK1 4,6
MEM_MA_BANK2 4,6

MEM_MA_WE_L 4,6
MEM_MA_RAS_L 4,6
MEM_MA_CAS_L 4,6
MEM_MA_RESET# 4,6

MEM_MA1_CLK_H0 4
MEM_MA1_CLK_L0 4
MEM_MA1_CLK_H1 4
MEM_MA1_CLK_L1 4

SCL0 6,15,18,30,31
SDA0 6,15,18,30,31

VCC3 VCC3

C62

C62

X_C0.1u16Y0402

X_C0.1u16Y0402

VDDR_VREF_CAVDDR_VREF_DQ

C153

C153

X_C0.1u16Y0402

X_C0.1u16Y0402

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

VCC_DDR

54

DIMM4

DIMM4

3

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

DQ0

4

DQ1

9

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

18

DQ10

19

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

21

DQ16

22

DQ17

27

DQ18

28

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

30

DQ24

31

DQ25

36

DQ26

37

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

81

DQ32

82

DQ33

87

DQ34

88

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

90

DQ40

91

DQ41

96

DQ42

97

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

99

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

80

VSS

83

VSS

86

VSS

89

VSS

92

VSS

95

VSS

98

VSS

101

VSS

104

VSS

VSS

VSS

VSS

VSS

VSS

107

110

113

116

119

170

173

176

179

182

183

186

189

191

194

197

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

DDR3

DDR3

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

121

124

127

130

133

136

139

142

145

148

151

154

157

160

163

166

199

202

205

236

VSS

208

VTT_DDR

120

VDDSPD

VSS

VSS

211

214

C279

C279

C0.1u16Y0402

C0.1u16Y0402

MEM_MB_EVENT_L

53

240

167

48

187

198

68

79

VTT

VTT

NC/PAR_IN

VSS

VSS

VSS

VSS

217

220

223

NC/ERR_OUT

VSS

226

229

NC/TEST4

VSS

232

RSVD

FREE1

DM0/DQS9

NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

VSS

VSS

235

239

FREE249FREE3

FREE4

A10/AP

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

ODT0
ODT1
CKE0
CKE1
CS0#
CS1#

RAS#
CAS#

RESET#

CK0#

CK1(NU)

CK1#(NU)

VREFDQ

VREFCA

VSS

MEC1

MEC2

MEC1

MEC2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

WE#

CK0

SCL
SDA

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
A13
A14
A15

BA0
BA1
BA2

SA1
SA0

MEC3

ZIF-DDRIII240P-RH

ZIF-DDRIII240P-RH

MEC3

188
181
61
180
59
58
178
56
177
175
70
55
174
196
172
171

39
40
45
46
158
159
164
165

7
6
16
15
25
24
34
33
85
84
94
93
103
102
112
111
43
42

125
126
134
135
143
144
152
153
203
204
212
213
221
222
230
231
161
162

195
77
50
169
193
76
71
190
52

73
192
74
168

184
185
63
64

1
67
118
238
237
117

MEM_MB_EVENT_L 4,6MEM_MA_EVENT_L 4,6

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

MEM_MB1_ODT0
MEM_MB1_ODT1
MEM_MB_CKE0
MEM_MB_CKE1
MEM_MB1_CS_L0
MEM_MB1_CS_L1
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2

MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB_RESET#

MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1

VDDR_VREF_DQ
VDDR_VREF_CA

SCL0
SDA0

MEM_MB1_ODT0 4

MEM_MB1_ODT1 4
MEM_MB_CKE0 4,6
MEM_MB_CKE1 4,6
MEM_MB1_CS_L0 4
MEM_MB1_CS_L1 4
MEM_MB_BANK0 4,6
MEM_MB_BANK1 4,6
MEM_MB_BANK2 4,6

MEM_MB_WE_L 4,6
MEM_MB_RAS_L 4,6
MEM_MB_CAS_L 4,6
MEM_MB_RESET# 4,6

MEM_MB1_CLK_H0 4
MEM_MB1_CLK_L0 4
MEM_MB1_CLK_H1 4
MEM_MB1_CLK_L1 4

ADDRESS A4 ADDRESS A6

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom
Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

07 Second Logical DDR DIMM

07 Second Logical DDR DIMM

07 Second Logical DDR DIMM

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

742Friday, June 01, 2012

742Friday, June 01, 2012

742Friday, June 01, 2012

of

of

of

5

D D

4

3

2

1

HT_TXCALP
HT_TXCALN

5 / 10

HT_CADIN_H[15..0]
HT_CADIN_L[15..0]

HT_CADIN_H0
HT_CADIN_L0
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H7
HT_CADIN_L7

HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H15
HT_CADIN_L15

R225301R1%0402 R225301R1%0402

HT_CLKIN_H0 3
HT_CLKIN_L0 3
HT_CLKIN_H1 3
HT_CLKIN_L1 3

HT_CTLIN_H0 3
HT_CTLIN_L0 3
HT_CTLIN_H1 3
HT_CTLIN_L1 3

REF2

REF2

NB

NB

X_760G

X_760G

REF3

REF3

NB

NB

X_785G

X_785G

HT_CADOUT_H[15..0]3
HT_CADOUT_L[15..0]3

C C

HT_CLKOUT_H03
HT_CLKOUT_L03
HT_CLKOUT_H13
HT_CLKOUT_L13

HT_CTLOUT_H03
HT_CTLOUT_L03
HT_CTLOUT_H13
HT_CTLOUT_L13

B B

HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]

20 / 5 / 5 / 5 / 20 20 / 5 / 5 / 5 / 20

HT_CADOUT_H0
HT_CADOUT_L0
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H7
HT_CADOUT_L7

HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H15
HT_CADOUT_L15

HT_RXCALP

R227301R1%0402 R227301R1%0402

HT_RXCALNHT_RXCALN

NB1A

NB1A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

AMD-215-0674007-00-A01-RH

AMD-215-0674007-00-A01-RH

PART 1 OF 6

PART 1 OF 6

HYPER TRANSPORT CPU

HYPER TRANSPORT CPU

Check U10 New Version : Port Number

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

I/F

I/F

HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_CADIN_H[15..0]3

HT_CADIN_L[15..0]3

HT_TXCALP
HT_TXCALN

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H24
H25
L21
L20

M24
M25
P19
R18

B24
B25

RX780/RS740/RS780 difference table (HT LINK)

X_C0.01u16X0402

X_C0.01u16X0402

C135

C135

VCCP

C120

C120
X_C0.01u16X0402

X_C0.01u16X0402

SIGNALS
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN

RS740 RX780

49.9R (GND)

49.9R (VDDHT)

1.21K

1.21K100R

RS780

301R

301R

Adding some 0.01uF stitching capacitors
for crossing a split when these signals
change different reference layer.

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

08 760G&785G&880G-HT

08 760G&785G&880G-HT

08 760G&785G&880G-HT

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

842Friday, June 01, 2012

842Friday, June 01, 2012

842Friday, June 01, 2012

of

of

of

5

4

3

2

1

20 / 5.5 / 4.5 / 5.5 / 20 20 / 5.5 / 4.5 / 5.5 / 20

GFX_RX0P19
GFX_RX0N19
GFX_RX1P19
GFX_RX1N19
GFX_RX2P19
GFX_RX2N19

D D

C C

GFX_RX3P19
GFX_RX3N19
GFX_RX4P19
GFX_RX4N19
GFX_RX5P19
GFX_RX5N19
GFX_RX6P19
GFX_RX6N19
GFX_RX7P19
GFX_RX7N19
GFX_RX8P19
GFX_RX8N19
GFX_RX9P19
GFX_RX9N19
GFX_RX10P19
GFX_RX10N19
GFX_RX11P19
GFX_RX11N19
GFX_RX12P19
GFX_RX12N19
GFX_RX13P19
GFX_RX13N19
GFX_RX14P19
GFX_RX14N19
GFX_RX15P19
GFX_RX15N19

PE0_RX19
PE0_RX#19
RX_LANP123
RX_LANN123

NEC_USB_RX26
NEC_USB_RX#26

MAR_SATA_RX25
MAR_SATA_RX#25

PE1_RX19
PE1_RX#19
PE2_RX19
PE2_RX#19

A_RX0P13
A_RX0N13
A_RX1P13
A_RX1N13
A_RX2P13
A_RX2N13
A_RX3P13
A_RX3N13

A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N

NB1B

NB1B

D4

GFX_RX0P

C4

GFX_RX0N

A3

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

AMD-215-0674007-00-A01-RH

AMD-215-0674007-00-A01-RH

PART 2 OF 6

PART 2 OF 6

GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N

PCIE I/F GFX

PCIE I/F GFX

GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP
PCE_CALRN

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N

GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

PE0_TX

AC1

PE0_TX#

AC2

TX_LANP1

AB4

TX_LANN1

AB3

NEC_USB_TX

AA2

NEC_USB_TX#

AA1

MAR_SATA_TX

Y1

MAR_SATA_TX#

Y2

PE1_TX

Y4

PE1_TX#

Y3

PE2_TX

V1

PE2_TX#

V2

A_TX0P_C

AD7

A_TX0N_C

AE7

A_TX1P_C

AE6

A_TX1N_C

AD6

A_TX2P_C

AB6

A_TX2N_C

AC6

A_TX3P_C

AD5

A_TX3N_C

AE5

R274 1.27KR1%0402R274 1.27KR1%0402

AC8

R270 2KR1%0402R270 2KR1%0402

AB8

GFX_TX0P 19
GFX_TX0N 19
GFX_TX1P 19
GFX_TX1N 19
GFX_TX2P 19
GFX_TX2N 19
GFX_TX3P 19
GFX_TX3N 19
GFX_TX4P 19
GFX_TX4N 19
GFX_TX5P 19
GFX_TX5N 19
GFX_TX6P 19
GFX_TX6N 19
GFX_TX7P 19
GFX_TX7N 19
GFX_TX8P 19
GFX_TX8N 19
GFX_TX9P 19
GFX_TX9N 19
GFX_TX10P 19
GFX_TX10N 19
GFX_TX11P 19
GFX_TX11N 19
GFX_TX12P 19
GFX_TX12N 19
GFX_TX13P 19
GFX_TX13N 19
GFX_TX14P 19
GFX_TX14N 19
GFX_TX15P 19
GFX_TX15N 19

C322 C0.1u10X0402C322 C0.1u10X0402
C326 C0.1u10X0402C326 C0.1u10X0402

X7R

C295 C0.1u10X0402C295 C0.1u10X0402
C296 C0.1u10X0402C296 C0.1u10X0402
C298 C0.1u10X0402C298 C0.1u10X0402
C301 C0.1u10X0402C301 C0.1u10X0402
C292 C0.1u10X0402C292 C0.1u10X0402
C293 C0.1u10X0402C293 C0.1u10X0402
C312 C0.1u10X0402C312 C0.1u10X0402
C309 C0.1u10X0402C309 C0.1u10X0402

VCC1_1

PE0_TX 19
PE0_TX# 19
TXLANP1 23
TXLANN1 23
NEC_USB_TX 26
NEC_USB_TX# 26
MAR_SATA_TX 25
MAR_SATA_TX# 25
PE1_TX 19
PE1_TX# 19
PE2_TX 19
PE2_TX# 19

A_TX0P 13
A_TX0N 13
A_TX1P 13
A_TX1N 13
A_TX2P 13
A_TX2N 13
A_TX3P 13
A_TX3N 13

1.2V (RS740)

1.1V(RS780)

RX780/RS740/RS780 GPP difference table

RS740 RX780/RS780

B B

PCE_CALRP
GPP4
GPP5

562R (GND) 1.27K (GND)
NC
NC

GPP4
GPP5

RX780/RS740/RS780 GPP Routing table

GPP X4 CONNECTOR
GPP X1 CONNECTOR
GIGABIT ETHERNET GPP3

RS740 RX780/RS780
GPP[2:0] GPP[3:0]

GPP4
GPP5

RS780 Display Port Support (muxed on GFX)

DP0

DP1

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

09 760G&785G&880G-PCIE I/F

09 760G&785G&880G-PCIE I/F

09 760G&785G&880G-PCIE I/F

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

942Friday, June 01, 2012

942Friday, June 01, 2012

942Friday, June 01, 2012

of

of

of

5

SPEC. HI:0.7VCC LOW:0.3VCC

D D

SYS_PWRGD30

WD_PWRGD15

C C

NBGFX_SRCCLK18

NBGFX_SRCCLK#18

R363 X_R/2R363 X_R/2

R422 X_R/2R422 X_R/2

RX740/RS740/RS780 difference table

NB_PWRGD IN

ALLOW_LDTSTOP
OUT(default)/IN

LDT_STOP#
IN(default)/IN

*, CLMC mode: NB send LDT_STOP#, ALLOW_LDTSTOP will become input

+1.8V_S0

B B

ALLOW_LDTSTOP13

+1.8V_S0

RN8

RN8

7

8

5

6

VCC3

A A

4
2

LDT_RST#3,13

LDT_STOP#3,13

3
1

8P4R-4.7KR0402

8P4R-4.7KR0402

SB_PWRGD

NB_PWRGD_IN

C254 X_C10p50N0402C254 X_C10p50N0402

R29

C248 X_C10p50N0402C248 X_C10p50N0402

G29

C243 X_C10p50N0402C243 X_C10p50N0402

B29

1.1V

VCC1_1

+1.8V_S0

Stuff : RX780
Nc : RS780

RS740 RX780

3.3V IN

1.8V IN

OC OC OC/3.3V IN

1.8V IN 1.8V IN/OC

3.3V IN

R259

R259
1KR0402

1KR0402

R248 X_R/2R248 X_R/2

5

2

4

6

1

3

FB8 220L2A-50FB8 220L2A-50

FB5

FB5
FB3 220L2A-50FB3 220L2A-50

FB10 220L2A-50FB10 220L2A-50

FB11

FB11

X_220L2A-50

X_220L2A-50

Stuff : RS740

RS780

1.8V IN

*

*

ALLOW_LDTSTOP_NB

Q45

Q45

NN-CMKT3904_SOT363-6-RH

NN-CMKT3904_SOT363-6-RH

LDT_STOP#_NB

220L2A-50

220L2A-50

+1.8V_S0

+1.8V_S0

R285

R285

330R0402

NB_PWRGD_IN

NB_PWRGD_IN must have a pull-up
resister to +1.8V_S0 due to
NC7W207 output pin is op-drain

3VDUAL

R365

R365
X_4.7KR0402

X_4.7KR0402

330R0402

For meet power
sequence

SB_PWRGD 15

PLL X5R

C281

C281
C2.2u6.3X5

C2.2u6.3X5

C252

C252

C698

C698

C0.1u16Y0402

C2.2u6.3X5

C2.2u6.3X5

RS780 & DDR3 based CPU:
use an open-drain buffer and pulled up to 1.8V_S0
through a 1-kR 5% resistor on the Northbridge side

C0.1u16Y0402

HTREFCLK18
HTREFCLK#18

NBLINKCLK18
NBLINKCLK#18

NB CLOCK INPUT TABLE

NB CLOCKS
HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N

R281

R281

GFX_REFCLK

1KR0402

1KR0402

GPP_REFCLK
GPPSB_REFCLK 100M DIFF 100M DIFF

* RS780 can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.

4

CP7

CP7

X_Copper

VCC3

+1.8V_S0

+1.8V_S0

HSYNC#11,29
VSYNC#11,29

DDC_CLK29

DDC_DATA29

C308

C308
C2.2u6.3X5

C2.2u6.3X5

NB_OSC_14M18

VCC1_1

VCC3

RS740 RX780 RS780

66M SE(SE)

NC

14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
NC NC vref

100M DIFF
NC
100M DIFF

X_Copper

ANALOG POWER X5R

FB6

FB6

X_220L2A-50

X_220L2A-50

R243R243

CP6 X_CopperCP6 X_Copper

FB4

FB4

X_220L2A-50

X_220L2A-50

C264

C264

C2.2u6.3X5

C2.2u6.3X5

NB_OSC_14M

VCC3

RN9

RN9
8P4R-4.7KR0402

8P4R-4.7KR0402

1
3
5
7

R283 X_4.7KR0402R283 X_4.7KR0402

R279 X_4.7KR0402R279 X_4.7KR0402

100M DIFF
100M DIFF

100M DIFF
100M DIFF

C2.2u6.3X5

C2.2u6.3X5

HSYNC#
VSYNC#

C310

C310
C0.1u16Y0402

C0.1u16Y0402

R269 150R1%0402R269 150R1%0402

2
4
6
8

AVDD

C268

C268

C2.2u6.3X5

C2.2u6.3X5

AVDDI

C259

C259
C2.2u6.3X5

C2.2u6.3X5

15 MILS WIDTH

AVDDQ

C255

C255

C256

C256

C0.1u16Y0402

C0.1u16Y0402

10 MILS WIDTH

R237 140R1%0402R237 140R1%0402

10 MILS WIDTH

R236 150R1%0402R236 150R1%0402

10 MILS WIDTH

R230 150R1%0402R230 150R1%0402

R280R280
R288R288

15 MILS WIDTH

X_10KR0402R276 X_10KR0402R276

TP23TP23

I2C_DATA

I2C_CLK
DDC_DATA_B8
DDC_CLK_A8

100M DIFF
100M DIFF

100M DIFF(IN/OUT)*
100M DIFF(OUT)

15 MILS WIDTH

C267

C267
C0.1u16Y0402

C0.1u16Y0402

15 MILS WIDTH
15 MILS WIDTH

B9,A9 pulling up resistors are stuffed for not
working and hardware reseting issue.B8,A8
pulling up resistors are reserved.

DDC_DATA_B819
DDC_CLK_A819

RS740_DFT_GPIO011

RS740_DFT_GPIO111

STRP_DATA
If not implemented:
RS740: Pulled up to 3.3 V with a 10-k? 5% resistor.
RS780: Not Connected.
RX780: Pulled up to 1.8 V with a 10-k? 5% resistor.

15 MILS WIDTH

C272

C272
C0.1u16Y0402

C0.1u16Y0402

15 MILS WIDTH

R268 150R1%0402R268 150R1%0402

DAC_RSET

R245715R1%0402 R245715R1%0402

RS780

PLLVDD

PLLVDD18

VDDA18HTPLL
VDDA18PCIEPLL

SYSRESET#
NB_PWRGD_IN
LDT_STOP#_NB
ALLOW_LDTSTOP_NB

HTREFCLK
HTREFCLK#

I2C_CLK
I2C_DATA
DDC_DATA_B8
DDC_CLK_A8

STRP_DATA

RS740_DFT_GPIO1

100M DIFF
100M DIFF

3

2

RS780

NB1C

NB1C

F12
E12
F14

G15

H15
H14

E17
F17
F15

G18
G17

E18
F18
E19
F19

A11
B11

F8
E8

G14

A12
D14
B12

H17

D7

E7

D8
A10
C10
C12

C25
C24

E11
F11

T2
T1

U1

U2

V4
V3

B9
A9
B8
A8
B7
A7

B10

G11

C8

AVDD
AVDD
AVDDDI
AVSSDI
AVDDQ
AVSSQ

C
Y
COMP

RED
RED#
GREEN
GREEN#
BLUE
BLUE#

DAC_HSYNC
DAC_VSYNC
DAC_SCL
DAC_SDA

DAC_RSET
PLLVDD

PLLVDD18
PLLVSS

VDDA18HTPLL
VDDA18PCIEPLL

VDDA18PCIEPLL
SYSRESET#

POWERGOOD
LDTSTOP#
ALLOW_LDTSTOP

HT_REFCLKP
HT_REFCLKN

REFCLK_P
REFCLK_N

GFX_REFCLKP
GFX_REFCLKN

GPP_REFCLKP
GPP_REFCLKN

GPPSB_REFCLKP
GPPSB_REFCLKN

I2C_CLK
I2C_DATA
DDC_DATA
DDC_CLK
AUX1P
AUX1N

STRP_DATA
VSS
AUX_CAL

PART 3 OF 6

PART 3 OF 6

CRT/TVOUT

CRT/TVOUT

LVTM

LVTM

PM

PM

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

AMD-215-0674007-00-A01-RH

AMD-215-0674007-00-A01-RH

THERMALDIODE_P

THERMALDIODE_N

TXOUT_L0P

TXOUT_L0N

TXOUT_L1P

TXOUT_L1N

TXOUT_L2P

TXOUT_L2N

TXOUT_L3P

TXOUT_L3N
TXOUT_U0P

TXOUT_U0N
TXOUT_U1P
TXOUT_U1N
TXOUT_U2P
TXOUT_U2N
TXOUT_U3P
TXOUT_U3N

TXCLK_LP
TXCLK_LN
TXCLK_UP
TXCLK_UN

VDDLTP18

VSSLTP18

VDDLT18
VDDLT18
VDDLT33
VDDLT33

VSSLT
VSSLT
VSSLT
VSSLT
VSSLT
VSSLT
VSSLT

GPIO3
GPIO2
GPIO4

TMDS_HPD

TVCLKIN

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21

if not support DVI can remove C684 C683 C685 C686

D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

HPD

D12
AE8

AD8
D13

X_0.1u/16v/Y5/4

X_0.1u/16v/Y5/4

TEST_EN

R253

R253

1.8KR0402

1.8KR0402

C291

C291

VDDLT33

TMDS_HPD0

RS740/RX780/RS780: STRAP_DEBUG_BUS_GPIO_ENABLE

Enables the Test Debug Bus using GPIO and/or memory IO
1 : Disable (RS740); Enable (RX780/RS780)
0 : Enable (RS740); Disable(RX780/RS780)

RX780: pin DFT_GPIO5
RS780: pin VSYNC

DFT_GPIO[4:2]: STRAP_PCIE_GPP_CFG[2:0]

These pin straps are used to configure PCI-E GPP mode.
111: register defined (register default to Config E) default
110: 4-0-0-0-0 Config A
101: 4-4-0-0-0 Config B
100: 4-2-2-0-0 Config C
011: 4-2-1-1-0 Config D
010: 4-1-1-1-1 Config E
others: register defined (default to Config E)

RS740/RX780/RS780: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected

RX780: pin DFT_GPIO1
RS780: pin SUS_STAT#

1

CP8

CP8

FB9

C241

C241
X_1u/6.3v/Y5/4

X_1u/6.3v/Y5/4

VCC3

FB9

X_220L2A-50

X_220L2A-50
CP5

CP5

FB2

FB2

X_220L2A-50

X_220L2A-50

15 MILS WIDTH

C289

C289

X_C2.2u6.3X5

X_C2.2u6.3X5

15 MILS WIDTH

R246 X_0R0402R246 X_0R0402

RS740

R263 X_0R0402R263 X_0R0402

R277 4.7KR0402R277 4.7KR0402

R252

R252

X_1.27KR1%0402

X_1.27KR1%0402

R264 10KR0402R264 10KR0402

R266 X_10KR0402R266 X_10KR0402

RX780/RS740/RS780 DEBUG PIN MAPPING

DEBUG_OUT0
DEBUG_OUT1

VCC3

C697

C697

X_C4.7u10X50805-RH

X_C4.7u10X50805-RH

ANALOG POWER X5R

COMM_EN 19

VCC3

ANALOG POWER X5R

TMDS_HPD0 19
RS740_DFT_GPIO5 11

RX780
RED(DFT_GPIO0)
GREEN(DFT_GPIO1)

DEBUG_OUT2 LVDS_BLON
DEBUG_OUT3
DEBUG_OUT4
DEBUG_OUT5
DEBUG_OUT6
DEBUG_OUT7

BLUE(DFT_GPIO3) TMDS_HPD
TXOUT_L2N(DBG_GPIO0)
TXCLK_LP(DBG_GPIO1)
TXOUT_L3N(DBG_GPIO2)
TXCLK_LN(DBG_GPIO3)

RX740/RS740/RS780 JTAG PIN MAPPING

RX780
TRST
TMS(TP220)

TEST_EN

PCIE_RST3(TP222)
TDI
TCK
TDO(TP218)

I2C_CLK I2C_CLK

PWM_GPIO6(TP219)

+1.8V_S0

X_Copper

X_Copper

RS780

Q43

Q43
N-P8503BMG_SOT23-3-RH

X_Copper

X_Copper

N-P8503BMG_SOT23-3-RH

D

D

S

S

G

G

RS780

RS740 RS780
LVDS_DIGON
LVDS_ENA_BL
LVDS_BLONY(DFT_GPIO2)

X
X
X
X

RS740/RS780
TEST_EN
DDC_DATA(TP223)
I2C_DATAI2C_DATA

TMDS_HPD(TP221)

+1.8V_S0

R235

R235

4.7KR0402

4.7KR0402

LVDS_DIGON
LVDS_ENA_BL

TMDS_HPD
AUX1N
AUX1P
HPD
AUX_CAL

+12V

RS780

SYSRESET#

A_RST#13,19

R289 X_0R0402R289 X_0R0402

RS740

If use A_RST#, ACC function will be fail.

5

take the pulling-down resistor of SYSRESET# out

4

RS740/RX780/RS780: SIDE-PORT MEMORY ENABLE

Enables Side port memory

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)
RS780: pin HSYNC
RX780: Not Appicable

3

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

10 760G&785G&880G-SYSTEM I/F

10 760G&785G&880G-SYSTEM I/F

10 760G&785G&880G-SYSTEM I/F

MS_7699 0A

MS_7699 0A

MS_7699 0A

10 42Friday, June 01, 2012

10 42Friday, June 01, 2012

10 42Friday, June 01, 2012

1

of

of

of

5

4

3

2

1

NB1D

NB1D

AB12

MEM_A0

AE16

MEM_A1

V11

MEM_A2

AE15

MEM_A3

AA12

MEM_A4

D D

C C

AB16

MEM_A5

AB14

MEM_A6

AD14

MEM_A7

AD13

MEM_A8

AD15

MEM_A9

AC16

MEM_A10

AE13

MEM_A11

AC14

MEM_A12

Y14

MEM_A13

AD16

MEM_BA0

AE17

MEM_BA1

AD17

MEM_BA2

W12

MEM_RAS#

Y12

MEM_CAS#

AD18

MEM_WE#

AB13

MEM_CS#

AB18

MEM_CKE

V14

MEM_ODT

V15

MEM_CKP

W14

MEM_CKN

AE12

MEM_COMPP

AD12

MEM_COMPN

AMD-215-0674007-00-A01-RH

AMD-215-0674007-00-A01-RH

PAR 4 OF 6

PAR 4 OF 6

SBD_MEM/DVO_I/F

SBD_MEM/DVO_I/F

MEM_DQ0
MEM_DQ1
MEM_DQ2
MEM_DQ3
MEM_DQ4
MEM_DQ5
MEM_DQ6
MEM_DQ7
MEM_DQ8

MEM_DQ9
MEM_DQ10
MEM_DQ11
MEM_DQ12
MEM_DQ13
MEM_DQ14
MEM_DQ15

MEM_DQS0P
MEM_DQS0N
MEM_DQS1P
MEM_DQS1N

MEM_DM0

MEM_DM1

IOPLLVDD18

IOPLLVDD

IOPLLVSS

MEM_VREF

AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21

Y17
W18
AD20
AE21

W17
AE19

AE23
AE24

AD23
AE18

+1.8V_S0
VCC1_1

MEM_VREF1

15 MILS WIDTH
15 MILS WIDTH

X_C2.2u6.3X5

X_C2.2u6.3X5

C217

C217

C257

C257
X_C2.2u6.3X5

X_C2.2u6.3X5

+1.8V_S0 VCC1_1

FOR RS780,R148,R162,C203 and C202 will be populated.

RS740/RX780/RS780 STRAPS

Note: for RS780, change R232 to 150R as AUX_CAL,
place close to pin C8

RS740_DFT_GPIO110

VSYNC#10,29

RS740_DFT_GPIO510

1.2V(RS740)

RS740/RX780/RS780: SIDE-PORT MEMORY ENABLE

RS740_DFT_GPIO010

HSYNC#10,29

Have not side port memory,AMD suggest HSYNC pull hign

R278 150R0402R278 150R0402

R262 3KR0402R262 3KR0402
R265 X_3KR0402R265 X_3KR0402

R275 X_3KR0402R275 X_3KR0402

R286 X_3KR0402R286 X_3KR0402

R261 X_3KR0402R261 X_3KR0402
R256 3KR0402R256 3KR0402

VCC3

RX780/RS780: STRAP_DEBUG_BUS_PCIE_ENABLE

MEM_VREF1

AMD: Please let MEM_VREF
short to GND when Sideport
is not used.

R239R239

RS740/RX780/RS780: LOAD_EEPROM_STRAPS

Selects Loading of STRAPS from EEPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
RS740: pin DFT_GPIO1

RS780: pin SUS_STAT#

RS740/RX780/RS780: STRAP_DEBUG_BUS_GPIO_ENABLE

Enables the Test Debug Bus using GPIO and/or memory IO
1 : Disable (RS740/RS780); Enable (RX780)
0 : Enable (RS740/RS780); Disable(RX780)
RS740: pin DFT_GPIO5

RS780: pin VSYNC

Enables Side port memory

1. Disable (RS740/RS780)
0 : Enable (RS740/RS780)
RS740: pin DFT_GPIO0

VCC3

RS780: pin HSYNC

Enables Test debug bus
using PCIE bus

1. Disable (can be enabled
thru nbcfg register)
0 : Enable

RS780: configurable thru register
setting only
RS740: Not supported

B B

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

11 760G&785G&880G-SPMEM/STRAPS

11 760G&785G&880G-SPMEM/STRAPS

11 760G&785G&880G-SPMEM/STRAPS

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

11 42Friday, June 01, 2012

11 42Friday, June 01, 2012

11 42Friday, June 01, 2012

of

of

of

5

4

3

2

1

RS740/RX780/RS780 POWER DIFFERENCE TABLE

PIN NAME
VDDHT
VDDHTRX
VDDHTTX
VDDA18PCIE

VDD18_MEM
VDDPCIE
VDDC
VDD_MEM
VDD33
IOPLLVDD18

RS740

NC

+1.2V
NC
+1.8V NC
NC
+1.2V +1.1V +1.1V
+1.2V

+1.8V/1.5V

+3.3V
+1.8V +1.8VNC

RX780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8VVDD18
NC

+1.1V
NC
NC

VDDPCIE 2.5A

A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9

K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16

AE10
AA11
Y11
AD10
AB10
AC10

H11
H12

VDD_PCIE

C311

C0.1u25Y0402-RH

C311

C0.1u25Y0402-RH

C306

X_C0.1u25Y0402-RH

C306

X_C0.1u25Y0402-RH

C261

C0.1u25Y0402-RH

C261

C0.1u25Y0402-RH

RS880P
VDDC RS880P: Nominal voltage is 1.2 V at 13 A

R255R255

VDDG33

C288

C288

C1u16X5-RH

C1u16X5-RH

C287

C287
C0.1u16Y0402

C0.1u16Y0402

C299

C299

C1u16X5-RH

C1u16X5-RH

C700

C700

C0.1u25Y0402-RH

C0.1u25Y0402-RH

RS780

+1.1V
+1.1V
+1.2V
+1.8V
+1.8V
+1.8V

+1.1V

+1.8V/1.5V

+3.3V

C262

C262

C315

C315

X_C0.1u25Y0402-RH

X_C0.1u25Y0402-RH

X_C1u16X5-RH

X_C1u16X5-RH

PIN NAME
IOPLLVDD

AVDDDI
AVDDQ
PLLVDD
PLLVDD18

VDDA18HTPLL
VDDLTP18
VDDLT18
VDDLT33

C701

C0.1u25Y

C701

C0.1u25Y

RS780 RS740

R267R267

RS740 RX780 RS780

+1.2V
+3.3V NC

+1.2V
+1.8V
+1.2VVDDA18PCIEPLL
+1.8V
+1.8V
+1.8V
+3.3V

CP9 X_CopperCP9 X_Copper

CP10 X_CopperCP10 X_Copper

L30 X_30L3A-15_0805-RHL30 X_30L3A-15_0805-RH

C320

C10u6.3X5-RH

C320

C10u6.3X5-RH

NB1_2V

C702

C0.1u25Y

C702

C0.1u25Y

C253

C22u6.3X50805-RH

C253

C22u6.3X50805-RH

RS880P
22UF

VCC3

NC

NC+1.8V +1.8V
NC+1.8V +1.8V

NC
+1.8V
+1.8V
NC
NC
NC

VCC1_1

C263

C10u6.3X5-RH

C263

C10u6.3X5-RH

+1.1V
+3.3VAVDDNC

+1.1V
+1.8V
+1.8V
+1.8V
+1.8V
+1.8V
NC

VSSAHT

VSSAHT

L17

L22

L7

VSSAPCIEM6VSSAPCIEN4VSSAPCIEP6VSSAPCIER1VSSAPCIER2VSSAPCIER4VSSAPCIEV7VSSAPCIEU4VSSAPCIEV8VSSAPCIEV6VSSAPCIEW1VSSAPCIEW2VSSAPCIEW4VSSAPCIEW7VSSAPCIEW8VSSAPCIEY6VSSAPCIE

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

L24

L25

P20

N22

M20

V19

R19

R22

R24

R25

U22

H20

W22

W24

VSSAHT

W25

NB1F

NB1F

VSSAPCIEA2VSSAPCIEB1VSSAPCIED3VSSAPCIED5VSSAPCIEE4VSSAPCIEG1VSSAPCIEG2VSSAPCIEG4VSSAPCIEH7VSSAPCIEJ4VSSAPCIER7VSSAPCIEL1VSSAPCIEL2VSSAPCIEL4VSSAPCIE

D D

PART 6/6

PART 6/6

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

VSSAHT

A25

VCC1_1

J22

E22

D23

H19

G22

G24

G25

VDDHT 0.6A

L29 30L3A-15_0805-RHL29 30L3A-15_0805-RH

C249

C10u6.3X5-RH

C249

C230

C230

C224

C224

C10u6.3X5-RH

C221

C221

C1u16X5-RH

C1u16X5-RH

C0.1u25Y0402-RH

C0.1u25Y0402-RH

C C

L6 30L3A-15_0805-RHL6 30L3A-15_0805-RH

C10u6.3X5-RH

C223

C223

C10u6.3X5-RH

C0.1u16Y0402

C0.1u16Y0402

VCCA_1V2

CP4 X_CopperCP4 X_Copper

FB1 X_220L2A-50FB1 X_220L2A-50

C10u10Y0805

C10u10Y0805

C251

C251

C250

C1u16X5-RH

C250

C1u16X5-RH

VDDHTRX

C0.1u25Y0402-RH

C0.1u25Y0402-RH

VDDHTRX 0.7A

C0.1u25Y0402-RH

C0.1u25Y0402-RH

C231

C231

X_C1u16X5-RH

X_C1u16X5-RH

C225

C225

C232

C232

VDDHTTX 0.4A

+1.8V_S0

FB7 220L2A-50FB7 220L2A-50

C285

B B

C10u6.3X5-RH

C10u6.3X5-RH

+1.8V_S0

C285

CP40

CP40

X_Copper

X_Copper

R257 X_0RR257 X_0R

RS780

C0.1u16X

C0.1u16X

VDDA18PCIE

C283

C282

C282

C283

C0.1u25Y0402-RH

C0.1u25Y0402-RH

15 MILS WIDTH

15 MILS WIDTH 15 MILS WIDTH

R247

R247

X_0R0402

X_0R0402

RS780

AA4

GROUND

GROUND

VSSAHT

VSSAHT

VSS

VSS

VSS

L12

Y21

P12

N13

M14

AD25

C246

X_C0.1u25Y0402-RH

C246

X_C0.1u25Y0402-RH

C220

C220

X_C10u6.3X5-RH

X_C10u6.3X5-RH

VDDHTTX

X_C0.1u25Y0402-RH

X_C0.1u25Y0402-RH

C233

C233

C284

C284

X_C0.1u25Y0402-RH

X_C0.1u25Y0402-RH

VDDG18

C703

C703
X_C1u16X5-RH

X_C1u16X5-RH

AB5

AB1

VSSAPCIE

VSSAPCIE

VSS

VSS

VSS

P15

R11

C245

C245

AB7

AC3

AC4

VSSAPCIE

VSSAPCIE

VSS

VSS

T12

R14

U14

C0.1u25Y0402-RH

C0.1u25Y0402-RH

AE1

AE4

AB2

VSSAPCIE

VSSAPCIE

VSSAPCIE

VSS

VSS

VSS

V12

U11

U15

AE14

VSSAPCIE

VSS

VSS

VSS

W11

W15

AC12

J17
K16
L16

M16

P16
R16
T16

H18

G19

F20
E21
D22
B23
A23

AE25
AD24
AC23
AB22
AA21

Y20

W19

V18
U17
T17
R17
P17

M17

J10
P10
K10

M10

L10

W9

H9
T10
R10

Y9
AA9
AB9
AD9
AE9

U10

F9

G9
AE11
AD11

D11

VSS

VSS

VSS

VSS

Y18

AA14

NB1E

NB1E

VDDHT
VDDHT
VDDHT
VDDHT
VDDHT
VDDHT
VDDHT

VDDHTRX
VDDHTRX
VDDHTRX
VDDHTRX
VDDHTRX
VDDHTRX
VDDHTRX

VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX
VDDHTTX

VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE
VDDA18PCIE

VDDG18
VDDG18
VDD18_MEM
VDD18_MEM

E14

E15

J12

K14

M11

L15

J15

VSSG8VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

K11

AB11

AB15

AB17

AB19

AE20

AB21

PART 5/6

PART 5/6

POWER

POWER

AMD-215-0674007-00-A01-RH

AMD-215-0674007-00-A01-RH

VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE
VDDPCIE

VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC

VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM
VDD_MEM

VDDG33
VDDG33

VDD18_MEM
RS780 without Side-Port/RX781/RS780C/RS780L/RS780MC:

A A

5

Connected to GND plane (preferred) or connected to 1.8V_S0 power rail.

4

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

12 760G&785G&880G-POWER

12 760G&785G&880G-POWER

12 760G&785G&880G-POWER

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

12 42Friday, June 01, 2012

12 42Friday, June 01, 2012

12 42Friday, June 01, 2012

of

of

of

5

C615 X_C150p25N0402C615 X_C150p25N0402

A_RST#_R

A_RX0P_C
A_RX0N_C
A_RX1P_C
A_RX1N_C
A_RX2P_C
A_RX2N_C
A_RX3P_C
A_RX3N_C

R429 562R1%0402R429 562R1%0402
R437 2.05KR1%0402R437 2.05KR1%0402

PCIE_PVDD

GPP0/1 is PCIEX1

A_RX0P9
A_RX0N9
A_RX1P9
A_RX1N9
A_RX2P9
A_RX2N9
A_RX3P9
A_RX3N9

A_TX0P9
A_TX0N9
A_TX1P9
A_TX1N9
A_TX2P9
A_TX2N9
A_TX3P9
A_TX3N9

L12

L12

30L3A-15_0805-RH

30L3A-15_0805-RH

C490

C490

X_C10u6.3X50805

X_C10u6.3X50805

SBSRCCLK18
SBSRCCLK#18

A_RST#

A_RST#10,19

D D

PLACE PCIE CAPS

outed with 85ohm ± 15% differential
impedance

C C

CLOSE TO U13

VCC_SB

PCIE_VDDR

R543 33R/4R543 33R/4

C528 C0.1u10X0402C528 C0.1u10X0402
C529 C0.1u10X0402C529 C0.1u10X0402
C494 C0.1u10X0402C494 C0.1u10X0402
C495 C0.1u10X0402C495 C0.1u10X0402
C526 C0.1u10X0402C526 C0.1u10X0402
C527 C0.1u10X0402C527 C0.1u10X0402
C496 C0.1u10X0402C496 C0.1u10X0402
C497 C0.1u10X0402C497 C0.1u10X0402

C519

C519
C1u6.3Y0402-RH

C1u6.3Y0402-RH

Reference to PA_SB700AJ8

FOR SB7XX A14

SB_OSCIN

32K_X1

32K_X2

R202 300R0402R202 300R0402

LDT_PWRGD
LDT_STOP#
LDT_RST#

VCC_DDR

CPU_HOT3

R431 X_R/2R431 X_R/2

R203 X_0R0402R203 X_0R0402

LDT_PWRGD3

LDT_STOP#3,10

LDT_RST#3,10

B B

Note: LDT_PG, LDT_STP# & LDT_RST# are OD
and require a PU to the CPU I/O rail. They are
also in the S5 domain to prevent glitching at
power up.

A A

SB_OSC_14M18

ALLOW_LDTSTOP10

4

SB1A

SB1A

N2

A_RST#

V23

PCIE_TX0P

V22

PCIE_TX0N

V24

PCIE_TX1P

V25

PCIE_TX1N

U25

PCIE_TX2P

U24

PCIE_TX2N

T23

PCIE_TX3P

T22

PCIE_TX3N

U22

PCIE_RX0P

U21

PCIE_RX0N

U19

PCIE_RX1P

V19

PCIE_RX1N

R20

PCIE_RX2P

R21

PCIE_RX2N

R18

PCIE_RX3P

R17

PCIE_RX3N

T25

PCIE_CALRP

T24

PCIE_CALRN

P24

PCIE_PVDD

P25

PCIE_PVSS

N25

PCIE_RCLKP/NB_LNK_CLKP

N24

PCIE_RCLKN/NB_LNK_CLKN

K23

NB_DISP_CLKP

K22

NB_DISP_CLKN

M24

NB_HT_CLKP

M25

NB_HT_CLKN

P17

CPU_HT_CLKP

M18

CPU_HT_CLKN

M23

SLT_GFX_CLKP

M22

SLT_GFX_CLKN

J19

GPP_CLK0P

J18

GPP_CLK0N

L20

GPP_CLK1P

L19

GPP_CLK1N

M19

GPP_CLK2P

M20

GPP_CLK2N

N22

GPP_CLK3P

P22

GPP_CLK3N

L18

25M_48M_66M_OSC

J21

25M_X1

J20

25M_X2

A3

X1

B3

X2

F23

ALLOW_LDTSTP

F24

PROCHOT#

F22

LDT_PG

G25

LDT_STP#

G24

LDT_RST#

SB,SB710,A11,FCBGA-528pin

SB,SB710,A11,FCBGA-528pin

3

PCI_CLK4

PCI_CLK0

PCI_CLK2 TPM_PCLK
PCICLK3_R

SB700

SB700

Part 1 of 5

Part 1 of 5

PCI EXPRESS INTERFACE

PCI EXPRESS INTERFACE

CLOCK GENERATOR

CLOCK GENERATOR

LPC

CPU

CPU

LPC

LDRQ1#/GNT5#/GPIO68

BMREQ#/REQ5#/GPIO65

RTC

RTC

RTC XTAL

RTC XTAL

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCICLK5/GPIO41

PCI CLKS

PCI CLKS

PCIRST#

FRAME#

DEVSEL#

PCI INTERFACE

PCI INTERFACE

TRDY#
STOP#

PERR#
SERR#
REQ0#
REQ1#

REQ2#
REQ3#/GPIO70
REQ4#/GPIO71

GNT3#/GPIO72
GNT4#/GPIO73

CLKRUN#

LOCK#

INTE#/GPIO33

INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36

LPCCLK0
LPCCLK1

LFRAME#

LDRQ0#

SERIRQ

RTCCLK

INTRUDER_ALERT#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8

AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE0#
CBE1#
CBE2#
CBE3#

IRDY#

PAR

GNT0#
GNT1#
GNT2#

LAD0
LAD1
LAD2
LAD3

VBAT

P4
P3
P1
P2
T4
T3

N1

U2
P7
V4
T1
V3
U1
V1
V2
T2
W1
T9
R6
R7
R5
U8
U5
Y7
W8
V9
Y8
AA8
Y4
Y3
Y2
AA2
AB4
AA1
AB3
AB2
AC1
AC2
AD1
W2
U7
AA7
Y1
AA6
W5
AA5
Y5
U6
W6
W4
V7
AC3
AD4
AB7
AE6
AB6
AD2
AE4
AD5
AC6
AE5
AD6
V5

AD3
AC4
AE2
AE3

G22
E22
H24
H23
J25
J24
H25
H22
AB8
AD7
V15

C3
C2
B2

PCI_CLK0
PCI_CLK1
PCI_CLK2
PCICLK3_R
PCI_CLK4
PCICLK5

SB_PCI_RST#

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30

AD31
PCI_CBE#0
PCI_CBE#1
PCI_CBE#2
PCI_CBE#3

PCI_GNT#2
PCI_GNT#3
PCI_GNT#4
PCI_CLKRUN#

PCI_GNT5#
PCI_REQ5#

INTR_ALERT#

SB_VBAT

RN18

RN18

8P4R-22R0402

8P4R-22R0402
1
3
5
7

R537 22R0402R537 22R0402

C613 C150p25N0402C613 C150p25N0402
R548 33R/4R548 33R/4

AD[31..0]

Adding some 0.1uF stitching
capacitors for crossing a split when
these signals change different
reference layer.

PCI_CBE#[3..0]

PCI_REQ#3
PCI_REQ#4

R523

R523

TP30TP30

X_10KR0402

X_10KR0402
TP9TP9
R512

R512

X_10KR0402

X_10KR0402

LPCCLK0
LPCCLK1

R507 10KR0402R507 10KR0402

TP7TP7

PCICLK4_SIO

2

PCICLK0_SLOT1

4
6
8

PCI_CBE#[3..0] 20

PCI_FRAME# 20
PCI_DEVSEL# 20
PCI_IRDY# 20
PCI_TRDY# 20
PCI_PAR 20
PCI_STOP# 20
PCI_PERR# 20

PCI_SERR# 20
PCI_REQ#0 20
PCI_REQ#1 20
PCI_REQ#2 20
PCI_REQ#3 20
PCI_REQ#4 20
PCI_GNT#0 20
PCI_GNT#1 20

PCI_LOCK# 20
PCI_INTE# 20

PCI_INTF# 20
PCI_INTG# 20
PCI_INTH# 20

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

VCC3

R531 X_100KR0402R531 X_100KR0402

PCICLK1_SLOT2 20

PCICLK5 17

SB_PCIRST# 21

AD[31..0] 20

VCC3

VCC3

TP8TP8

SERIRQ 21

PCICLK4_SIO 17,21
PCICLK0_SLOT1 20
TPM_PCLK 17,21
PCICLK3 17,20

C661

C661
X_0.1u/16v/Y5/4_B

X_0.1u/16v/Y5/4_B

LPCCLK0 17
LPCCLK1 17

LPC_FRAME# 21
LPC_DRQ#0 21

3VDUAL

C575

C575

C0.1u16X

C0.1u16X

2

1

For EMI

C604

PCICLK3

PCICLK0_SLOT1

PCICLK4_SIO

PCICLK1_SLOT2

TPM_PCLK

LPC_AD[3..0]

16mil

C1u10X

C1u10X

C568

C568

C604

X_C10p50N0402

X_C10p50N0402

C606

C606
C6.8p50N0402-RH

C6.8p50N0402-RH
C621

C621
C6.8p50N0402-RH

C6.8p50N0402-RH
C623

C623
C6.8p50N0402-RH

C6.8p50N0402-RH

C605

C605

C10p50N0402

C10p50N0402

32K_X1

Y6

Y6

32.768KHZ12.5P_D-LF

32.768KHZ12.5P_D-LF

R499

R499
X_20MR

X_20MR

PLACE THESE COMPONENTS CLOSE TO U600, AND
USE GROUND GUARD FOR 32K_X1 AND 32K_X2

LPC_AD[3..0] 21

1 2

R482 20MRR482 20MR

C586

C586
C18p50N

C18p50N

32K_X2

4

3

C578

C578
C18p50N

C18p50N

P=3.3*3.3/510=0.02135W

3VDUAL

X

Y

R476 510RR476 510R

change 3VUDAL and diode 1k R,change 0603

R463

R463

1KR

1KR

D27

D27
S-BAT54C_SOT23

S-BAT54C_SOT23

Z

VBAT

16mil

R462 1KRR462 1KR

VBATSB_VBAT

BAT1

BAT1

1 2

BAT2P/Holder

BAT2P/Holder

1
2

H1X2M_BLACK-RH

H1X2M_BLACK-RH

JBAT1

JBAT1

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

13 SB810&SB850-PCIE/PCI/CPU/LPC

13 SB810&SB850-PCIE/PCI/CPU/LPC

13 SB810&SB850-PCIE/PCI/CPU/LPC

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS_7699 0A

MS_7699 0A

MS_7699 0A

1

13 42Friday, June 01, 2012

13 42Friday, June 01, 2012

13 42Friday, June 01, 2012

of

of

of