MSI MS-7638 Schematics rev.1.0

PageTitle

Cover Sheet 1 Block Diagram/Device Map/GPIO Table/history 2, 3, 4, 5 CPU-CLK/Control/MISC/PEG

D D

CPU-Power,CPU-GND DDR III DIMM 1 / 2

,CPU-Memory

,9,78

10,11

MS-7638

CPU:

INTEL - Lynnfield/ Clarkdale LGA 1156

Ver: 1.0

System Chipset:

CLK GEN ICS4105 PCH-PCI-E/PCI/DMI/USB/CLK PCH-SATA/HOST/FAN/GPIO/Display PCH-SMB/LPC/AUDIO/RTC/SPI/JTAG/RST PCH-POWER,GND/NVRAM

PCIE x16 & x1, x1 Slots

C C

PCI SLOT LAN-RTL8111DL Audio Codec ALC889 23 MARVELL SATA3.0 IDE X1 VGA - D-Sub DVI-D

12 13 14 15 16,17 18SIO-Fintek F71889ED/Print Port/COM1 19 20 21 22 23 24 25 26SATA conn / FAN Control

INTEL-IBEXPEAK PCH (H - 57)

OnBoard Chipset:

Clock Gen:ICS 4105B HD Audio Codec:ALC889 LAN:RTL8111D 10/100/1000 SIO:F71889 Flash ROM: 64 Mb SPI (CHIP)

Main Memory:

DDRIII (800/1066/1333MHz) * 4 (Dual Channel)

Expansion Slots:

PCI Express (X16) Slot * 2 PCI Express (X1) Slot * 2 PCI Slot *3

IDE X1 JMB-368

USB

B B

ATX F_Panel/EMI/TPM/Buzzer/KB

ACPI Controller (uPI solution) DDR Power - uP6103 1-Phase

PCH Power - 1P05-Linear CPU_VTT Power - uP6103_1 Phase

GPU Power -ISL6314_1-Phase CPU Power - uP6206 3-Phase

36 VIA6315N 1394 Manual & Option parts

A A

27 28 29 30 31 32 33 34 35 36

PWM:

Controller: uP6206 ( 3-Phase use STD MOS -- 95W )

ACPI:

uPI+SIO

Other:

SATA(SATA2-300MB/s) *6 USB2.0 *10 (Rear*4 / Front*6) PRINT Header *1 COM pin header *2 TPM Header *1 on BOARD BUZZER D-SUB *1 DVI PORT*1 HDMI PORT*1

OV by uP6264 or SIO uP6103 (CPU_VTT) Linear (PCH) uP6103(DDR) GPU Power -ISL6314

BOM SKUs

H55:chiset S:solid cap EL:EL cap G:giga lan 8111DL M:Miga lan 8103EL 6: 6 ports DVI: DVI Stuff

MICRO-STAR INT'L CO.,LTD

MS-7638

MSI

Size Document Description Rev

Custom

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

Cover Sheet

MS-7638

138

Sheet of

INTEL CONFIDENTIAL

D D

INTEL

PCIE SLOT

16X

LGA 1156

DDRIII 1066,1333

128bit

DDRIII 1066,1333

UNBUFFERED DDRIII DIMM1

UNBUFFERED DDRIII DIMM2

DDRIII FIRST LOGICAL DIMM

FDI LINK X8 DMI X4

IBEXPEAK

C C

DVI

VGA

PORT:B

RGB

PCIE

PCIE X1 SLOT

JMB-368

GIGA LAN

PCH

USB-2USB-6 USB-3USB-4USB-5

B B

USB-7

USB-8 USB-9

USB-1

USB-0

USB 2.0

H55

HD AUDIO I/F

IDE*1

Audio Codec

SPI ROM

SPI I/F

SATA II I/F

SATA#0 SATA#1 SATA#2 SATA#3

SATA#4

PCI BUS

SATA#5

PCI SLOT #1

A A

KB/ MOUSE COM1/Print Port

LPC I/F

SIO

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MS-7638

MSI

Size Document Description Rev

Custom

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

MS-7638

Block Diagram

Sheet of

238

DDR DIMM config.

Device Address Clock CHA DIMM1 CHB DIMM2

D D

10100001B 10100000B

MEM_MA_CLK_H0/L0 H1/L1 MEM_MB_CLK_H0/L0 H1/L1

PCI Config.

DEVICE MCP1 INT Pin

PCI_INT#A

PCI Slot 1

PCI_INT#B PCI_INT#C PCI_INT#D

TPM

REQ#/GNT#

PCI_REQ0# PCI_GNT0#

IDSEL

AD16

CLOCK

PCH CLKOUT_PCI<0>

PCH CLKOUT_PCI<3>

SIO

PCH CLKOUT_PCI<2>

PCI RESET DEVICE

C C

Signals

PCIRST#_PCH PLTRST_BU1# JMB368 IDE PLTRST_BU2# PLTRST_BU3# PLTRST# SIO

B B

IBEXPEAK

Target

PCISLOT1

PCIE*16 / *1 LAN&TPM

A A

MICRO-STAR INT'L CO.,LTD

MS-7638

Device Map

MS-7638

Sheet of

338

MSI

Size Document Description Rev

Custom

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

D D

C C

B B

A A

MICRO-STAR INT'L CO.,LTD

MS-7638

MSI

Size Document Description Rev

Size Document Description Rev C

C Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

GPIO Table

MS-7638

438

Sheet of

History

1.2009-10-13 Change VCC_SENSE to CPU_VCC_SENSE

2.2009-10-13 Add HDMI circuit,change USB circuit,JSP1 circuit update

3.2009-10-13 update NCT3016 circuit ,add VTIN3 circuit for VRM MOS

4.2009-10-18 Add C589 C590

D D

5.2009-10-18 Add R561 R562 For HDMI HPDET

6.2009-10-20 Add R602,Swap HDMI wire for layout

7.2009-10-21 NCT3016 circuit update:add R637 Q65 R592,Change U27 pin16 tp NCT_GPIO16,delete C121

8.2009-10-21A NCT3016 citcui update:add Q85,chang SATA1&SATA2 to SATA1_2

9.2009-10-23 change JUSB2 & JUSB1 for layout

10.2009-10-23A NCT3016 circuit update:add R850

11.2009-10-24 delete VCCGATE and DUALGATE circuit

12.2009-10-26 delete C534

13.2009-10-26 Swap RN40 change to MS-7638-0A

添加

1. 2009-11-09

2. 2009-11-09 EUP-

C C

3. 2009-11-09 Page23

4. 2009-11-09 Page36

5. 2009-11-09

6. 2009-11-09

7. 2010-01-04 Power solution: R7=21K(R11-0213T13-W08) R110=34k(R11-0343T13-W08) R18=R51=R71=51.1K(R11-5112T12-W08, ocp=108a) R48=13K (R11-0133T23-W08, thermal balance) R364=43.2K(R11-4322T12-W08, GPU_CORE Droop)

8. 2010-01-11 C601 Add HDA co-lay PCIEx1,add R840 R841 RN40

B B

Remove BUZ1

9. 2010-01-11 JPW1&JBAT1

10.2010-01-11 R693

11.2010-01-13 Remove C179 for SI VGA

12.2010-01-13 R208 change to 330ohm for SI HDMI

13.2010-01-13

預留

14.2010-01-18 L3/L4/L5

15.2010-01-18 C337

16.2010-01-18 stuff R189,Q30 ,Remove D4 for SI

17.2010-01-18 stuff R536 R684 R690 Q74 Q76 Q82 Q83 for F71889ED LAA

18.2010-01-18 Remove R530 R545 R650 R683 R688 for F71889ED LAA

19.2010-01-18 ADD R844 C605,change R276(10K) R697(10R)for F71889ED LAA

A A

19.2010-01-18 ADD R88 R247,Remove R91 R246 R810 R818 for F71889ED LAA

1394---VIA 6315N

改用

F71889ED

添加去除

添加

PCIE 4X slot

添加两个

改

PCI slot

top

層，並上件

的料號請更換成

上件

R842

位置

上件

0.1u，C102/ C99/ C148/ C186

SATA3.0-23 MARVELL debug port

预留

N41-1030141-H06

120nH，C157/C165/C169

上件

20p for EMI

上件

0.1u，C412/C414/C419

上件

10p for EMI

MICRO-STAR INT'L CO.,LTD

MS-7638

MSI

Size Document Description Rev

Size Document Description Rev C

C Date:

Friday, January 22, 2010

Date:

Friday, January 22, 2010

Date:

Friday, January 22, 2010

History

MS-7638

538

Sheet of

AA8/Y8 ,these signals for 120 MHz from the Intel?5 Series Chipset CLKOUT_DP_P /CLKOUT_BCLK1_P and CLKOUT_DP_N / CLKOUT_BCLK1_N. Leave as NC on the PCH and connect directly to GND at the processor. 120MHz clock is used for embedded DisplayPort which is no supported on Desktop designs.

CLK133M_CPU_P13 CLK133M_CPU_N13

CK_DMI_P13 CK_DMI_N13

BACK SIDE

D D

R171 X_49.9R/1%R171 X_49.9R/1%

CPU_VTT

CPU_PWRGD15

VTT_PGD30,35

MEM_PWRGD15

H_PECI14,18

H_THERMTRIP#14

PM_SYNC14

R295 20R/1%R295 20R/1% R291 20R/1%R291 20R/1%

R299 100R/1%R299 100R/1% R298 24.9R/1%R298 24.9R/1% R300 130R/1%R300 130R/1%

R301 49.9/1%R301 49.9/1% R204 49.9/1%R204 49.9/1%

C C

SKTOCC#18

代翴　璉　

CPU_VTT

B B

R350 X_3KR350 X_3K R310 X_3KR310 X_3K R309 X_3KR309 X_3K

CFG 0~5 HAVE INTERNAL PULL-UPS

Configuration signals: The CFG signals have a default value of 1 if not terminated on the board. Refer to the Platform Design Guide for pull-down recommendations when logic low is desired. CFG[0]: PCI Express Bifurcation:

- With all Intel?5 Series Chipsets except P55 and P57 SKUs: Reserved (Only 1 x16 PCI Express supported by default)

- With Intel?5 Series Chipsets P55 and P57 SKUs only: 1 = 1 x16 PCI Express 0 = 2 x8 PCI Express

- With Workstation and Server Ibex Peak: 1 = 1 x16 PCI Express 0 = 2 x8 PCI Express CFG[1]: Reserved (Lynnfield processor PCI Express Port Bifurcation) CFG[2]: Reserved configuration lands. A test point may be placed on the board for this land. CFG[3]: PCI Express* Static Lane Numbering Reversal. A test point may be placed on the board for this land. Lane reversal will be applied across all 16 lanes. 1: No Reversal 0: Reversal In the case of Bifurcation with NO Lane Reversal, the physical lane mapping is as follows: Lanes 15:8 => Port 1 Lanes 7:0 Lanes 7:0 => Port 0 Lanes 7:0 In the case of Bifurcation WITH Lane Reversal, the physical lane mapping is as follows: Lanes 15:8 => Port 0 Lanes 0:7 Lanes 7:0 => Port 1 Lanes 0:7 CFG[6:4]: Reserved configuration lands. A

A A

test point may be placed on the board for this land. CFG[17:7]: Reserved configuration lands. Intel does not recommend a test point on the board for this land.

PEG CONFIG TABLE

SEL2 SEL1 SEL0 PCIE CONFIG

CK_DMI_P CK_DMI_N

H_TDO_TDI_M

TP5TP5

VTT_PGD MEM_PWRGD

H_PECI H_CATERR# H_PROCHOT# H_THERMTRIP# PM_SYNC

H_COMP2 H_COMP3

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

H_COMP1 H_COMP0 SKTOCC#

H_MCP_CFG0 H_MCP_CFG1 H_MCP_CFG2 H_MCP_CFG3 H_MCP_CFG4 H_MCP_CFG5

H_MCP_CFG6 H_MCP_CFG7 H_MCP_CFG8

TP10TP10

H_MCP_CFG9

TP12TP12

H_MCP_CFG10

TP30TP30

H_MCP_CFG11

TP29TP29

H_MCP_CFG12

TP11TP11

H_MCP_CFG13

TP31TP31

H_MCP_CFG14

TP28TP28

H_MCP_CFG15 H_MCP_CFG16

TP9TP9

H_MCP_CFG17

TP27TP27

H_MCP_CFG0 H_MCP_CFG1 H_MCP_CFG2 H_MCP_CFG3 H_MCP_CFG4 H_MCP_CFG5 H_MCP_CFG6 H_MCP_CFG7 H_MCP_CFG15

1 1 X 16 0 2 X 8

CLK133M_CPU_P CLK133M_CPU_N

Follow DG&CRB

CP3 X_COPPERCP3 X_COPPER CP2 X_COPPERCP2 X_COPPER

CPU_VTT

TP26TP26

R343 X_3KR343 X_3K R306 X_3KR306 X_3K R305 X_3KR305 X_3K R303 X_3KR303 X_3K R302 X_3KR302 X_3K R308 X_3KR308 X_3K R304 X_3KR304 X_3K R296 X_3KR296 X_3K R307 X_3KR307 X_3K

For DP port

CPURST# PROC_PWROK VCCP_PWRGD

PM_EXT_TS0 PM_EXT_TS1

TP_GFX_DPRSLPVR

CPU1E

AA7

BCLK[0]

AA6

BCLK[0]*

AA3

PEG_CLK

AA4

PEG_CLK*

BCLK[1]*

AA8

BCLK[1]

AF37

TDI_M

AF38

TD0_M

AF34

RSTIN*

AH36

PROC_PWROK

AH35

VCCPWRGOOD

AG37

VTTPWRGOOD

AH37

SM_DRAMPWROK

AG35

PECI

AG39

CATERR*

AH34

PROCHOT*

AF35

THERMTRIP*

AH39

PM_SYNC

AB5

PM_EXT_TS[0]*

AB4

PM_EXT_TS[1]*

B11

COMP2

C11

COMP3

AG1

SM_RCOMP[0]

AD1

SM_RCOMP[1]

AE1

SM_RCOMP[2]

AF2

COMP1

AF36

COMP0

AK38

SKTOCC*

CFG0

CFG1/RSVD

E10

CFG2/RSVD

F10

CFG3/PEG_LANE_REVERSAL

H10

CFG4/RSVD

CFG5/VSS

CFG6/FC_E9

CFG7/FC_F9

G12

CFG8/FC_G12

H12

CFG9/FC_H12

K10

CFG10/FC_K10

CFG11/FC_K8

J12

CFG12/FC_J12

CFG13/FC_L8

CFG14/FC_K9

K12

CFG15/FC_K12

CFG16/FC_H7

L11

CFG17/FC_L11

RSVD

J10

GFX_DPRSLPVR/RSVD

AV38

VSS

AK12

RSVD

AK13

RSVD

AK14

RSVD

AL12

RSVD

AM15

RSVD

AM16

RSVD

AM18

RSVD

AM19

RSVD

AM20

RSVD

AM21

RSVD

AU40

RSVD

AV1

RSVD

AV39

RSVD

AW2

RSVD

AW38

RSVD

AY37

RSVD

N12-160A010-F02

H_CATERR# PM_SYNC

H_PECI CPU_RESET_OUT# H_THERMTRIP#

H_PROCHOT#

XDP_CPU_PRDY#

R195 51RR195 51R R179 X_51RR179 X_51R

R180 X_51RR180 X_51R R184 51RR184 51R R197 X_51RR197 X_51R

R185 51RR185 51R

R196 51RR196 51R

MISC

5 OF 12

VID[0]/MSID[0] VID[1]/MSID[1] VID[2]/MSID[2] VID[3]/MSID[3] VID[4]/MSID[4] VID[5]/MSID[5]

VID[6] VID[7]

PSI*

GFX_VR_EN

GFX_IMON/RSVD

GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6]

FC_AE38

VTT_SELECT

FC_AG40

VCC_SENSE VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

VAXG_SENSE

VSSAXG_SENSE

ISENSE

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

TDO TCK

TMS

TRST* PRDY*

PREQ*

DBR*

BCLK_ITP*

BCLK_ITP

TAPPWRGOOD

RESET_OBS*

BPM[0]* BPM[1]* BPM[2]* BPM[3]* BPM[4]* BPM[5]* BPM[6]* BPM[7]*

RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD RSVD

H_VID0

U40

H_VID1

U39

H_VID2

U38

H_VID3

U37

H_VID4

U36

H_VID5

U35

H_VID6

U34

H_VID7

U33

CPU_PSI

AG38

GFX_VR_EN GFX_IMON

F12 F6

H_GFX_VID0

G10

H_GFX_VID1

B12

H_GFX_VID2

E12

H_GFX_VID3

E11

H_GFX_VID4

C12

H_GFX_VID5

G11

H_GFX_VID6

J11

TP_MCP_VCCVTT_VID0

AE38 AF39

TP_MCP_VCCVTT_VID2

AG40

CPU_VCC_SENSE

T35

CPU_VSS_SENSE

T34 AE35 AE36

GFX_VCC_SENSE_R

A13

GFX_VSS_SENSE_R

B13

VCCP_IMAX

T40 AL18

AK18 T39 M12 L12 AL15 AL14

CPU_TDO

AM38

CPU_TDI

AM37

TDI

CPU_TDO CPU_TDI CPU_TMS

CPU_TCK CPU_TRST#

demo board empty check list not empty

AN37 AN40 AM39

AJ38 AK37 AL40 AK40 AK39 AK34 AL39

AL33 AL32 AK33 AK32 AM31 AL30 AK30 AK31

AL17 AM17 AM25 AL29 AM30 AK29 AK28 AM29 AM28 AL27 AK27 AM26 AM27 AL26 AK26 AK25

CPU_TCK CPU_TMS CPU_TRST#

XDP_CPU_PRDY# XDP_CPU_PREQ# FP_RST# XDP_CPU_BCLK_N XDP_CPU_BCLK_P XDP_CPU_PWRGD CPU_RESET_OUT#

XDP_CPU_BPM_N0 XDP_CPU_BPM_N1 XDP_CPU_BPM_N2 XDP_CPU_BPM_N3 XDP_CPU_BPM_N4 XDP_CPU_BPM_N5 XDP_CPU_BPM_N6 XDP_CPU_BPM_N7

R187 51RR187 51R R186 51RR186 51R R192 51RR192 51R

R201 51RR201 51R R191 51RR191 51R

H_VID0 35 H_VID1 35

Follow MS7588-1.0

R194 X_1KR1%0402R194 X_1KR1%0402

R297 0RR297 0R

R385 0RR385 0R R384 0RR384 0R

R28 X_0R0402R28 X_0R0402

R173 0RR173 0R

demo board no connect

if not use XDP,add Test point

XDP_CPU_PWRGD

CPU_VTT

R176

R176 X_4.7K

X_4.7K

Q32

H_PROCHOT#

CPU_VTT

CPU_PSI

Q32

C E

X_3904_SOT23

CPU_VTT

R1 X_1KR1%0402

X_1KR1%0402

Follow MS7588-1.0

Q4 X_N-SST3904_SOT23

X_N-SST3904_SOT23

H_VID[7..2] 35

CPU_VTT

GFX_VR_EN 34 H_GFX_VID[6..0] 34

TP6TP6

VTT_SELECT 33

TP2TP2

CPU_VCC_SENSE 35 CPU_VSS_SENSE 35

GFX_VCC_SENSE 34

GFX_VSS_SENSE 34

VCCP_IMAX 35

Follow MS7588-1.0

TP8TP8

FP_RST# 15,29

TP4TP4 TP3TP3

TP22TP22 TP7TP7 TP1TP1 TP20TP20 TP21TP21 TP24TP24 TP25TP25 TP23TP23

PSI# 35

CPU_VTT

R193

1.5KR0402-1

SIO_TRIP# 14,18

CPU1C

DMI_RX0 DMI_RX0# DMI_RX1 DMI_RX1# DMI_RX2

DMI_RX2# DMI_RX3 DMI_RX3#

AM14 AM13

AK15 AK16

C9 D9 B8 C8 A7 A6 B6 C6 A5 B5 B4 C4 C3 D3 D2 E2 E1 F1 G3 G2 G1 H1

J3 J2

J1 K1 L2 L3 P3 P4 T3 T4

R1 T1 U3 U2 U1 V1

W3 W2

AC4 AD4

AC3 AD3

AC2

PEG_RX[0] PEG_RX[0]* PEG_RX[1] PEG_RX[1]* PEG_RX[2] PEG_RX[2]* PEG_RX[3] PEG_RX[3]* PEG_RX[4] PEG_RX[4]* PEG_RX[5] PEG_RX[5]* PEG_RX[6] PEG_RX[6]* PEG_RX[7] PEG_RX[7]* PEG_RX[8] PEG_RX[8]* PEG_RX[9] PEG_RX[9]* PEG_RX[10] PEG_RX[10]* PEG_RX[11] PEG_RX[11]* PEG_RX[12] PEG_RX[12]* PEG_RX[13] PEG_RX[13]* PEG_RX[14] PEG_RX[14]* PEG_RE[15] PEG_RX[15]*

DMI_RX[0] DMI_RX[0]* DMI_RX[1] DMI_RX[1]* DMI_RX[2] DMI_RX[2]* DMI_RX[3] DMI_RX[3]*

RSVD RSVD RSVD RSVD

CPU1D

FDI_FSYNC[0] FDI_LSYNC[0]

DISPLAY

DISPLAY LINK

LINK

FDI_FSYNC[1] FDI_LSYNC[1]

FDI_INT

4 OF 12

PEG

DMI

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

3 OF 12

VDDIO

FDI_TX[0]

FDI_TX[0]*

FDI_TX[1]

FDI_TX[1]*

FDI_TX[2]

FDI_TX[2]*

FDI_TX[3]

FDI_TX[3]*

FDI_TX[4]

FDI_TX[4]*

FDI_TX[5]

FDI_TX[5]*

FDI_TX[6]

FDI_TX[6]*

FDI_TX[7]

FDI_TX[7]*

EXP_A_RXP_019 EXP_A_RXN_019 EXP_A_RXP_119 EXP_A_RXN_119 EXP_A_RXP_219 EXP_A_RXN_219 EXP_A_RXP_319 EXP_A_RXN_319 EXP_A_RXP_419 EXP_A_RXN_419 EXP_A_RXP_519 EXP_A_RXN_519 EXP_A_RXP_619 EXP_A_RXN_619 EXP_A_RXP_719 EXP_A_RXN_719 EXP_A_RXP_819 EXP_A_RXN_819 EXP_A_RXP_919 EXP_A_RXN_919 EXP_A_RXP_1019 EXP_A_RXN_1019 EXP_A_RXP_1119 EXP_A_RXN_1119 EXP_A_RXP_1219 EXP_A_RXN_1219 EXP_A_RXP_1319 EXP_A_RXN_1319 EXP_A_RXP_1419 EXP_A_RXN_1419 EXP_A_RXP_1519 EXP_A_RXN_1519

DMI_RX013 DMI_RX0#13 DMI_RX113 DMI_RX1#13 DMI_RX213 DMI_RX2#13 DMI_RX313 DMI_RX3#13

FDI_FSYNC014 FDI_LSYNC014

FDI_FSYNC114 FDI_LSYNC114

FDI_INT14

FDI_FSYNC0 FDI_LSYNC0

FDI_FSYNC1 FDI_LSYNC1

FDI_INT

PEG_TX[0]

PEG_TX[0]*

PEG_TX[1]

PEG_TX[1]*

PEG_TX[2]

PEG_TX[2]*

PEG_TX[3]

PEG_TX[3]*

PEG_TX[4]

PEG_TX[4]*

PEG_TX[5]

PEG_TX[5]*

PEG_TX[6]

PEG_TX[6]*

PEG_TX[7]

PEG_TX[7]*

PEG_TX[8]

PEG_TX[8]*

PEG_TX[9]

PEG_TX[9]*

PEG_TX[10]

PEG_TX[10]*

PEG_TX[11]

PEG_TX[11]*

PEG_TX[12]

PEG_TX[12]*

PEG_TX[13]

PEG_TX[13]*

PEG_TX[14]

PEG_TX[14]*

PEG_TX[15]

PEG_TX[15]*

DMI_TX[0]

DMI_TX[0]*

DMI_TX[1]

DMI_TX[1]*

DMI_TX[2]

DMI_TX[2]*

DMI_TX[3]

DMI_TX[3]*

PEG_RBIAS

C7 D7 E7 E6 E5 F5 F3 F4 G6 G5 H4 H3 F7 G7 J6 J5 K3 K4 H8 J8 L6 L5 M4 M3 K7 L7 N6 N5 M8 N8 R5 R6

L1 M1 N3 N2 N1 P1 R2 R3

D11 C10 B10 A11

Break-out:10mil width, 6 mil space Other Area:10mil width, 15 mil space

FDI_TX0

FDI_TX0#

FDI_TX1

FDI_TX1#

FDI_TX2

FDI_TX2#

FDI_TX3

FDI_TX3#

FDI_TX4

FDI_TX4#

FDI_TX5

FDI_TX5#

FDI_TX6

FDI_TX6#

FDI_TX7

FDI_TX7#

CPU reset reserve

3VSB

R165

4.7K

R169 4.7KR169 4.7K

PLTRST#15,18

Q29

3904_SOT363

CPU_VTTCPU_VTT

R178

R178 150R

150R

6 1 3 4

CPURST#

MICRO-STAR INT'L CO.,LTD

MSI

Size Document Description Rev

Custom

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

Date:

Monday, January 11, 2010

EXP_A_TXP_0 19 EXP_A_TXN_0 19 EXP_A_TXP_1 19 EXP_A_TXN_1 19 EXP_A_TXP_2 19 EXP_A_TXN_2 19 EXP_A_TXP_3 19 EXP_A_TXN_3 19 EXP_A_TXP_4 19 EXP_A_TXN_4 19 EXP_A_TXP_5 19 EXP_A_TXN_5 19 EXP_A_TXP_6 19 EXP_A_TXN_6 19 EXP_A_TXP_7 19 EXP_A_TXN_7 19 EXP_A_TXP_8 19 EXP_A_TXN_8 19 EXP_A_TXP_9 19 EXP_A_TXN_9 19 EXP_A_TXP_10 19 EXP_A_TXN_10 19 EXP_A_TXP_11 19 EXP_A_TXN_11 19 EXP_A_TXP_12 19 EXP_A_TXN_12 19 EXP_A_TXP_13 19 EXP_A_TXN_13 19 EXP_A_TXP_14 19 EXP_A_TXN_14 19 EXP_A_TXP_15 19

DMI_TX0 DMI_TX0# DMI_TX1 DMI_TX1# DMI_TX2 DMI_TX2# DMI_TX3 DMI_TX3#

EXP_A_TXN_15 19 DMI_TX0 13

DMI_TX0# 13 DMI_TX1 13 DMI_TX1# 13 DMI_TX2 13 DMI_TX2# 13 DMI_TX3 13 DMI_TX3# 13

GRCOMP

GRBIAS

R294

R294 750/1%

750/1%

FDI_TX0 14 FDI_TX0# 14 FDI_TX1 14 FDI_TX1# 14 FDI_TX2 14 FDI_TX2# 14 FDI_TX3 14 FDI_TX3# 14

FDI_TX4 14 FDI_TX4# 14 FDI_TX5 14 FDI_TX5# 14 FDI_TX6 14 FDI_TX6# 14 FDI_TX7 14 FDI_TX7# 14

R172 X_1.3K/1%R172 X_1.3K/1%

C74

X_100p/16X

MS-7638

CPU-CNTL/CLK/MISC

R292

49.9/1%

CPURST#PLTRST#

R177

R177 X_665R/1%

X_665R/1%

Sheet of

638

CPU1A

MEM_MA_ADD[15..0]10

D D

MEM_MA_WE_L10 MEM_MA_CAS_L10 MEM_MA_RAS_L10

MEM_MA_BANK010 MEM_MA_BANK110 MEM_MA_BANK210

MEM_MA_CS_L010 MEM_MA_CS_L110

MEM_MA_CS_L210 MEM_MA_CS_L310

MEM_MA_CKE010 MEM_MA_CKE110 MEM_MA_CKE210 MEM_MA_CKE310

MEM_MA_ODT010 MEM_MA_ODT110 MEM_MA_ODT210 MEM_MA_ODT310

C C

MEM_MA_CLK_H010 MEM_MA_CLK_L010 MEM_MA_CLK_H110 MEM_MA_CLK_L110 MEM_MA_CLK_H210

MEM_MA_CLK_L210 MEM_MA_CLK_H310 MEM_MA_CLK_L310

B B

A A

MEM_MA_ADD0 MEM_MA_ADD1 MEM_MA_ADD2 MEM_MA_ADD3 MEM_MA_ADD4 MEM_MA_ADD5 MEM_MA_ADD6 MEM_MA_ADD7 MEM_MA_ADD8 MEM_MA_ADD9 MEM_MA_ADD10 MEM_MA_ADD11 MEM_MA_ADD12 MEM_MA_ADD13 MEM_MA_ADD14 MEM_MA_ADD15

MEM_MA_WE_L MEM_MA_CAS_L MEM_MA_RAS_L

MEM_MA_BANK0 MEM_MA_BANK1 MEM_MA_BANK2

MEM_MA_CS_L0 MEM_MA_CS_L1 MEM_MA_CS_L2 MEM_MA_CS_L3

MEM_MA_CKE0 MEM_MA_CKE1 MEM_MA_CKE2 MEM_MA_CKE3

MEM_MA_ODT0 MEM_MA_ODT1 MEM_MA_ODT2 MEM_MA_ODT3

MEM_MA_CLK_H0 MEM_MA_CLK_L0 MEM_MA_CLK_H1 MEM_MA_CLK_L1 MEM_MA_CLK_H2 MEM_MA_CLK_L2 MEM_MA_CLK_H3 MEM_MA_CLK_L3

DDR3_DRAMRST#

AW18

AY15 AV15 AU15

AW14

AY13 AV14

AW13

AU14

AW12

AT19 AU13

AW11

AU24 AT11 AR10

AT22 AU22 AT20

AV20 AU19 AU12

AV21

AW24

AU21 AU23

AU10

AW10

AV10 AY10

AV23 AV24

AW23

AY24

AR22 AR21 AP18 AN18 AN21 AP21 AP19 AN19

AV8

AK22

AM22

AL23 AK23

AL10

AM10

AP10 AN10 AR11 AP11

AK9 AL9

AK11

AM11

CPU1A

SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15]

SA_WE* SA_CAS* SA_RAS*

SA_BA[0] SA_BA[1] SA_BA[2]

SA_CS[0]* SA_CS[1]* SA_CS[2]* SA_CS[3]*

SA_CKE[0] SA_CKE[1] SA_CKE[2] SA_CKE[3]

SA_ODT[0] SA_ODT[1] SA_ODT[2] SA_ODT[3]

SA_CK[0] SA_CK[0]* SA_CK[1] SA_CK[1]* SA_CK[2] SA_CK[2]* SA_CK[3] SA_CK[3]*

SM_DRAMRST*

SA_CS[4]* SA_CS[5]* SA_CS[6]* SA_CS[7]*

SA_DQS[8] SA_DQS[8]*

SA_ECC_CB[0] SA_ECC_CB[1] SA_ECC_CB[2] SA_ECC_CB[3] SA_ECC_CB[4] SA_ECC_CB[5] SA_ECC_CB[6] SA_ECC_CB[7]

DDR_A

1 OF 12

SA_DQS[0]

SA_DQS[0]*

SA_DQS[1]

SA_DQS[1]*

SA_DQS[2]

SA_DQS[2]*

SA_DQS[3]

SA_DQS[3]*

SA_DQS[4]

SA_DQS[4]*

SA_DQS[5]

SA_DQS[5]*

SA_DQS[6]

SA_DQS[6]*

SA_DQS[7]

SA_DQS[7]*

SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7]

SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8]

SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63]

MEM_MA_DQS_H0

AK3

MEM_MA_DQS_L0

AJ3

MEM_MA_DQS_H1

AP2

MEM_MA_DQS_L1

AP3

MEM_MA_DQS_H2

AU4

MEM_MA_DQS_L2

AU3

MEM_MA_DQS_H3

AY6

MEM_MA_DQS_L3

AW6

MEM_MA_DQS_H4

AR28

MEM_MA_DQS_L4

AT29

MEM_MA_DQS_H5

AV32

MEM_MA_DQS_L5

AW32

MEM_MA_DQS_H6

AW36

MEM_MA_DQS_L6

AV35

MEM_MA_DQS_H7

AR39

MEM_MA_DQS_L7

AR38

MEM_MA_DM0

AJ2

MEM_MA_DM1

AN1

MEM_MA_DM2

AU1

MEM_MA_DM3

AV6

MEM_MA_DM4

AN29

MEM_MA_DM5

AW31

MEM_MA_DM6

AU35

MEM_MA_DM7

AT38

MEM_MA_DATA0

AH1

MEM_MA_DATA1

AJ4

MEM_MA_DATA2

AL2

MEM_MA_DATA3

AL1

MEM_MA_DATA4

AG2

MEM_MA_DATA5

AH2

MEM_MA_DATA6

AK1

MEM_MA_DATA7

AK2

MEM_MA_DATA8

AN3

MEM_MA_DATA9

AN2

MEM_MA_DATA10

AR3

MEM_MA_DATA11

AR2

MEM_MA_DATA12

AM3

MEM_MA_DATA13

AM2

MEM_MA_DATA14

AP1

MEM_MA_DATA15

AR4

MEM_MA_DATA16

AT4

MEM_MA_DATA17

AU2

MEM_MA_DATA18

AW3

MEM_MA_DATA19

AW4

MEM_MA_DATA20

AT3

MEM_MA_DATA21

AT1

MEM_MA_DATA22

AV2

MEM_MA_DATA23

AV4

MEM_MA_DATA24

AW5

MEM_MA_DATA25

AY5

MEM_MA_DATA26

AU8

MEM_MA_DATA27

AY8

MEM_MA_DATA28

AU5

MEM_MA_DATA29

AV5

MEM_MA_DATA30

AV7

MEM_MA_DATA31

AW7

MEM_MA_DATA32

AN27

MEM_MA_DATA33

AT28

MEM_MA_DATA34

AP28

MEM_MA_DATA35

AP30

MEM_MA_DATA36

AN26

MEM_MA_DATA37

AR27

MEM_MA_DATA38

AR29

MEM_MA_DATA39

AN30

MEM_MA_DATA40

AU30

MEM_MA_DATA41

AU31

MEM_MA_DATA42

AV33

MEM_MA_DATA43

AU34

MEM_MA_DATA44

AV30

MEM_MA_DATA45

AW30

MEM_MA_DATA46

AU33

MEM_MA_DATA47

AW33

MEM_MA_DATA48

AW35

MEM_MA_DATA49

AY35

MEM_MA_DATA50

AV37

MEM_MA_DATA51

AU37

MEM_MA_DATA52

AY34

MEM_MA_DATA53

AW34

MEM_MA_DATA54

AV36

MEM_MA_DATA55

AW37

MEM_MA_DATA56

AT39

MEM_MA_DATA57

AT40

MEM_MA_DATA58

AN38

MEM_MA_DATA59

AN39

MEM_MA_DATA60

AU38

MEM_MA_DATA61

AU39

MEM_MA_DATA62

AP39

MEM_MA_DATA63

AP40

DDR3_DRAMRST#

R285 1K/1%R285 1K/1%

C198

C198 X_0.1u/16X

X_0.1u/16X

MEM_MA_DQS_H0 10

MEM_MA_DQS_L0 10

MEM_MA_DQS_H1 10

MEM_MA_DQS_L1 10

MEM_MA_DQS_H2 10

MEM_MA_DQS_L2 10

MEM_MA_DQS_H3 10

MEM_MA_DQS_L3 10

MEM_MA_DQS_H4 10

MEM_MA_DQS_L4 10

MEM_MA_DQS_H5 10

MEM_MA_DQS_L5 10

MEM_MA_DQS_H6 10

MEM_MA_DQS_L6 10

MEM_MA_DQS_H7 10

MEM_MA_DQS_L7 10

MEM_MA_DM0 10 MEM_MA_DM1 10 MEM_MA_DM2 10 MEM_MA_DM3 10 MEM_MA_DM4 10 MEM_MA_DM5 10 MEM_MA_DM6 10 MEM_MA_DM7 10

MEM_MA_DATA[63..0] 10

VCC_DDR VCC_DDR

R286

R286 470R

470R

R282 470RR282 470R

R274 X_0RR274 X_0R

R278 470RR278 470R

Q50

2N3904

VCC_DDR

CPU1B

MEM_MB_ADD[15..0]11

MEM_MB_WE_L11 MEM_MB_CAS_L11 MEM_MB_RAS_L11

MEM_MB_BANK011 MEM_MB_BANK111 MEM_MB_BANK211

MEM_MB_CS_L011 MEM_MB_CS_L111 MEM_MB_CS_L211 MEM_MB_CS_L311

MEM_MB_CKE011 MEM_MB_CKE111 MEM_MB_CKE211 MEM_MB_CKE311

MEM_MB_ODT011 MEM_MB_ODT111 MEM_MB_ODT211 MEM_MB_ODT311

MEM_MB_CLK_H011 MEM_MB_CLK_L011 MEM_MB_CLK_H111

MEM_MB_CLK_L111 MEM_MB_CLK_H211 MEM_MB_CLK_L211

MEM_MB_CLK_H311 MEM_MB_CLK_L311

R283

150R

Q48

2N3904

R273

R273 X_0R

X_0R

R279

150R

Q47

2N3904

MEM_MB_ADD0 MEM_MB_ADD1 MEM_MB_ADD2 MEM_MB_ADD3 MEM_MB_ADD4 MEM_MB_ADD5 MEM_MB_ADD6 MEM_MB_ADD7 MEM_MB_ADD8 MEM_MB_ADD9 MEM_MB_ADD10 MEM_MB_ADD11 MEM_MB_ADD12 MEM_MB_ADD13 MEM_MB_ADD14 MEM_MB_ADD15

MEM_MB_WE_L MEM_MB_CAS_L MEM_MB_RAS_L

MEM_MB_BANK0 MEM_MB_BANK1 MEM_MB_BANK2

MEM_MB_CS_L0 MEM_MB_CS_L1 MEM_MB_CS_L2 MEM_MB_CS_L3

MEM_MB_CKE0 MEM_MB_CKE1 MEM_MB_CKE2 MEM_MB_CKE3

MEM_MB_ODT0 MEM_MB_ODT1 MEM_MB_ODT2 MEM_MB_ODT3

MEM_MB_CLK_H0 MEM_MB_CLK_L0 MEM_MB_CLK_H1 MEM_MB_CLK_L1 MEM_MB_CLK_H2 MEM_MB_CLK_L2 MEM_MB_CLK_H3 MEM_MB_CLK_L3

DDR3_DRAMRST#B 11

DDR3_DRAMRST#A 10

AU20 AU18 AV18 AU17 AY18 AV17

AW17

AU16 AT17 AY16

AY25 AW16 AW15 AW28

AY12

AV11

AU26 AW27 AW26

AU25 AW25

AV12

AY27 AW29

AV26

AV29

AW8

AY9

AU9

AV9

AU27

AU29

AV27

AU28

AR17

AR16

AT15

AR15

AN17

AN16

AR19

AR18

AM23 AM24

AL24

AK24

AR14

AR13

AR12

AT13

AN15

AP14 AM12

AN12

AN14

AP13

CPU1B

SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15]

SB_WE* SB_CAS* SB_RAS*

SB_BA[0] SB_BA[1] SB_BA[2]

SB_CS[0]* SB_CS[1]* SB_CS[2]* SB_CS[3]*

SB_CKE[0] SB_CKE[1] SB_CKE[2] SB_CKE[3]

SB_ODT[0] SB_ODT[1] SB_ODT[2] SB_ODT[3]

SB_CK[0] SB_CK[0]* SB_CK[1] SB_CK[1]* SB_CK[2] SB_CK[2]* SB_CK[3] SB_CK[3]*

SB_CS[4]* SB_CS[5]* SB_CS[6]* SB_CS[7]*

SB_DQS[8] SB_DQS[8]*

SB_ECC_CB[0] SB_ECC_CB[1] SB_ECC_CB[2] SB_ECC_CB[3] SB_ECC_CB[4] SB_ECC_CB[5] SB_ECC_CB[6] SB_ECC_CB[7]

DDR_B

2 OF 12

SB_DQS[0]

SB_DQS[0]*

SB_DQS[1]

SB_DQS[1]*

SB_DQS[2]

SB_DQS[2]*

SB_DQS[3]

SB_DQS[3]*

SB_DQS[4]

SB_DQS[4]*

SB_DQS[5]

SB_DQS[5]*

SB_DQS[6]

SB_DQS[6]*

SB_DQS[7]

SB_DQS[7]*

SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7]

SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8]

SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63]

MSI

MEM_MB_DQS_L0

AE5

MEM_MB_DQS_H1

AH6

MEM_MB_DQS_L1

AJ5

MEM_MB_DQS_H2

AN6

MEM_MB_DQS_L2

AM6

MEM_MB_DQS_H3

AR8

MEM_MB_DQS_L3

AP8

MEM_MB_DQS_H4

AT25

MEM_MB_DQS_L4

AR24

MEM_MB_DQS_H5

AP32

MEM_MB_DQS_L5

AR32

MEM_MB_DQS_H6

AR36

MEM_MB_DQS_L6

AR37

MEM_MB_DQS_H7

AL37

MEM_MB_DQS_L7

AM36

MEM_MB_DM0

AE4

MEM_MB_DM1

AH4

MEM_MB_DM2

AM7

MEM_MB_DM3

AT7

MEM_MB_DM4

AN24

MEM_MB_DM5

AN32

MEM_MB_DM6

AM33

MEM_MB_DM7

AK35

MEM_MB_DATA0

AD7

MEM_MB_DATA1

AD6

MEM_MB_DATA2

AH8

MEM_MB_DATA3

AJ8

MEM_MB_DATA4

AC7

MEM_MB_DATA5

AC6

MEM_MB_DATA6

AF5

MEM_MB_DATA7

AE6

MEM_MB_DATA8

AG5

MEM_MB_DATA9

AH7

MEM_MB_DATA10

AK6

MEM_MB_DATA11

AL4

MEM_MB_DATA12

AG6

MEM_MB_DATA13

AG4

MEM_MB_DATA14

AJ7

MEM_MB_DATA15

AK7

MEM_MB_DATA16

AL6

MEM_MB_DATA17

AN5

MEM_MB_DATA18

AP6

MEM_MB_DATA19

AR5

MEM_MB_DATA20

AL5

MEM_MB_DATA21

AM4

MEM_MB_DATA22

AN7

MEM_MB_DATA23

AP5

MEM_MB_DATA24

AT6

MEM_MB_DATA25

AR7

MEM_MB_DATA26

AR9

MEM_MB_DATA27

AM8

MEM_MB_DATA28

AN8

MEM_MB_DATA29

AR6

MEM_MB_DATA30

AL8

MEM_MB_DATA31

AT9

MEM_MB_DATA32

AN23

MEM_MB_DATA33

AP23

MEM_MB_DATA34

AR25

MEM_MB_DATA35

AR26

MEM_MB_DATA36

AT23

MEM_MB_DATA37

AP22

MEM_MB_DATA38

AP25

MEM_MB_DATA39

AT26

MEM_MB_DATA40

AT32

MEM_MB_DATA41

AP31

MEM_MB_DATA42

AR33

MEM_MB_DATA43

AM32

MEM_MB_DATA44

AT31

MEM_MB_DATA45

AR31

MEM_MB_DATA46

AR34

MEM_MB_DATA47

AT33

MEM_MB_DATA48

AR35

MEM_MB_DATA49

AT36

MEM_MB_DATA50

AN33

MEM_MB_DATA51

AP36

MEM_MB_DATA52

AP34

MEM_MB_DATA53

AT35

MEM_MB_DATA54

AN34

MEM_MB_DATA55

AP37

MEM_MB_DATA56

AL35

MEM_MB_DATA57

AM35

MEM_MB_DATA58

AJ36

MEM_MB_DATA59

AJ37

MEM_MB_DATA60

AN35

MEM_MB_DATA61

AM34

MEM_MB_DATA62

AJ35

MEM_MB_DATA63

AL36

MICRO-STAR INT'L CO.,LTD

Size Document Description Rev

Custom

Date:

CPU-Memory

Monday, January 18, 2010

MEM_MB_DQS_H0

AF4

MS-7638

MEM_MB_DQS_H0 11

MEM_MB_DQS_L0 11

MEM_MB_DQS_H1 11

MEM_MB_DQS_L1 11

MEM_MB_DQS_H2 11

MEM_MB_DQS_L2 11

MEM_MB_DQS_H3 11

MEM_MB_DQS_L3 11

MEM_MB_DQS_H4 11

MEM_MB_DQS_L4 11

MEM_MB_DQS_H5 11

MEM_MB_DQS_L5 11

MEM_MB_DQS_H6 11

MEM_MB_DQS_L6 11

MEM_MB_DQS_H7 11

MEM_MB_DQS_L7 11

MEM_MB_DM0 11 MEM_MB_DM1 11 MEM_MB_DM2 11 MEM_MB_DM3 11 MEM_MB_DM4 11 MEM_MB_DM5 11 MEM_MB_DM6 11 MEM_MB_DM7 11

MEM_MB_DATA[63..0] 11

Sheet of

738

CPU1F

CPU

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

CPU

POWER

6 OF 12

H26 H28 H29 H31 H32 H34 H35 H37 H38 H40 J18 J19 J21 J22 J24 J25 J27 J28 J30 J31 J33 J34 J36 J37 J39 J40 K17 K18 K20 K21 K23 K24 K26 K27 K29 K30 K32 K33 K35 K36 K38 K39 L17 L19 L20 L22 L23 L25 L26 L28 L29 L31 L32 L34 L35 L37 L38 L40 M17 M19 M21 M22 M24 M25 M27 M28 M30 M33 M34 M36 M37 M39 M40 N33 N35 N36 N38 N39 P33 P34 P35 P36 P37 P38 P39 P40 R33 R34 R35 R36 R37 R38 R39 R40

VCC1_8

A23 A24 A26 A27 A33 A35 A36 A38

D D

C C

B B

A A

B23 B25 B26 B28 B29 B31 B32 B34 B35 B37 B38 C23 C24 C25 C27 C28 C30 C31 C33 C34 C36 C37 C39 C40 D23 D24 D26 D27 D29 D30 D32 D33 D35 D36 D38 D39 E22 E23 E25 E26 E28 E29 E31 E32 E34 E35 E37 E38 E40 F21 F22 F24 F25 F27 F28 F30 F31 F33 F34 F36 F37 F39 F40 G20 G21 G23 G24 G26 G27 G29 G30 G32 G33 G35 G36 G38 G39 H19 H20 H22 H23 H25

AA33 AA34 AA35 AA36 AA37 AA38 AC33 AC34 AC35 AC36 AC37 AC38 AC39 AC40 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AE33 AE34 AE39 AE40 AF33 AG33 AJ31 AJ32

AJ21 AJ25 AJ27 AJ29 AK20 AK21 AL20 AL21

AC8

AE8 AJ17 AJ19 AK19

AC5 AJ23

AG8

AF8

AF7

CPU1G

V33 V34 V35 V36 V37 V38 V39 V40 Y33 Y34 Y35 Y36 Y37 Y38

VTT_01 VTT_02 VTT_03 VTT_04 VTT_05 VTT_06 VTT_07 VTT_08 VTT_09 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58

VTT_60

VCCPLL_01 VCCPLL_02 VCCPLL_03

7 OF 12

CPU

POWER

CPU1H

A14

VAXG_01

A15

VAXG_02

A17

VAXG_03

A18

VAXG_04

B14

VAXG_05

B15

VAXG_06

B17

VAXG_07

B18

VAXG_08

C14

VAXG_09

C15

VAXG_10

C17

VAXG_11

C18

VAXG_12

C20

VAXG_13

C21

VAXG_14

D14

VAXG_15

D15

VAXG_16

D17

VAXG_17

D18

VAXG_18

D20

VAXG_19

D21

VAXG_20

E14

VAXG_21

E15

VAXG_22

E17

VAXG_23

E18

VAXG_24

E20

VAXG_25

F14

VAXG_26

F15

VAXG_27

F17

VAXG_28

F18

VAXG_29

F19

VAXG_30

G14

VAXG_31

G15

VAXG_32

G17

VAXG_33

G18

VAXG_34

H14

VAXG_35

H15

VAXG_36

H17

VAXG_37

J14

VAXG_38

J15

VAXG_39

J16

VAXG_40

K14

VAXG_41

K15

VAXG_42

K16

VAXG_43

L14

VAXG_44

L15

VAXG_45

L16

VAXG_46

M14

VAXG_47

M15

VAXG_48

M16

VAXG_49

CPU

POWER

8 OF 12

VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66

T6 T7 T8 V7 V8 AB7

VCC_DDR

GPU_CORE Decoupling

CPU_VTTVCCPVCCP CPU_VTTCPU_VTT GPU_CORE

CPU1I

L10

VTT_67

M10

VTT_68

M11

VTT_69

VTT_70

VTT_71

VTT_72

VTT_73

VTT_74

VTT_75

VTT_76

VTT_77

VTT_78

VTT_79

GPU_CORE

背面

C172 22u/6.3X/8C172 22u/6.3X/8

C174 X_4.7u/10X/12C174 X_4.7u/10X/12

C180 22u/6.3X/8C180 22u/6.3X/8

C597 X_22u/6.3X/8C597 X_22u/6.3X/8

C596 X_22u/6.3X/8C596 X_22u/6.3X/8

C591 X_22u/6.3X/8C591 X_22u/6.3X/8

C593 X_22u/6.3X/8C593 X_22u/6.3X/8

CPU SOCKET CAVITY CAPS

AJ11

VDDQ_01

AJ13

VDDQ_02

AJ15

VDDQ_03

AT18

VDDQ_04

AT21

VDDQ_05

AT10

VDDQ_06

AU11

VDDQ_07

AV13

VDDQ_08

AV16

VDDQ_09

AV19

VDDQ_10

AV22 AV25 AV28

AW9 AY11 AY14 AY17 AY23 AY26

VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDQ_18 VDDQ_19

CPU

POWER

9 OF 12

CPU_VTT Decoupling

CPU_VTT CPU_VTT

C594 X_22u/6.3X/8C594 X_22u/6.3X/8

C175 22u/6.3X/8C175 22u/6.3X/8

C139 22u/6.3X/8C139 22u/6.3X/8

C149 22u/6.3X/8C149 22u/6.3X/8

C134 22u/6.3X/8C134 22u/6.3X/8

C127 22u/6.3X/8C127 22u/6.3X/8

C131 22u/6.3X/8C131 22u/6.3X/8

C144 22u/6.3X/8C144 22u/6.3X/8

C177 22u/6.3X/8C177 22u/6.3X/8C592 X_22u/6.3X/8C592 X_22u/6.3X/8

C155 22u/6.3X/8C155 22u/6.3X/8 C585 X_22u/6.3X/8C585 X_22u/6.3X/8

C158 22u/6.3X/8C158 22u/6.3X/8

VCC_DDR-Decoupling

VCC_DDR

C166 22u/6.3X/8C166 22u/6.3X/8

C595 X_22u/6.3X/8C595 X_22u/6.3X/8

C170 22u/6.3X/8C170 22u/6.3X/8

CPU SOCKET CAVITY CAPS

背面

C584 X_22u/6.3X/8C584 X_22u/6.3X/8

C588 X_22u/6.3X/8C588 X_22u/6.3X/8

C598 X_22u/6.3X/8C598 X_22u/6.3X/8

C590 X_22u/6.3X/8C590 X_22u/6.3X/8

CPU SOCKET CAVITY CAPS

CPU_VCCP-Decoupling

VCCP

C160 22u/6.3X/8C160 22u/6.3X/8

C162 22u/6.3X/8C162 22u/6.3X/8

C141 22u/6.3X/8C141 22u/6.3X/8

C161 22u/6.3X/8C161 22u/6.3X/8

C152 22u/6.3X/8C152 22u/6.3X/8

C576 X_22u/6.3X/8C576 X_22u/6.3X/8

C579 X_22u/6.3X/8C579 X_22u/6.3X/8

C570 X_22u/6.3X/8C570 X_22u/6.3X/8

C142 22u/6.3X/8C142 22u/6.3X/8

C586 X_22u/6.3X/8C586 X_22u/6.3X/8

C163 22u/6.3X/8C163 22u/6.3X/8

C129 22u/6.3X/8C129 22u/6.3X/8

C153 22u/6.3X/8C153 22u/6.3X/8

0603

C580 X_1u/10Y/6C580 X_1u/10Y/6

C589 X_1u/10Y/6C589 X_1u/10Y/6

C583 X_1u/10Y/6C583 X_1u/10Y/6

VCC1_8

C582 X_1u/10Y/6C582 X_1u/10Y/6

C176 22u/6.3X/8C176 22u/6.3X/8

C85

X_0.1u/10X

EMI

C75

X_0.1u/10X

CPU_VTT

C69

X_0.1u/10X

C130 22u/6.3X/8C130 22u/6.3X/8

C151 22u/6.3X/8C151 22u/6.3X/8

C150 22u/6.3X/8C150 22u/6.3X/8

C143 22u/6.3X/8C143 22u/6.3X/8

背面

C573 X_22u/6.3X/8C573 X_22u/6.3X/8

C572 X_22u/6.3X/8C572 X_22u/6.3X/8

C587 X_22u/6.3X/8C587 X_22u/6.3X/8

C574 X_22u/6.3X/8C574 X_22u/6.3X/8

C578 X_22u/6.3X/8C578 X_22u/6.3X/8

CPU SOCKET CAVITY CAPS

MICRO-STAR INT'L CO.,LTD

MS-7638

CPU-Power

MS-7638

Sheet of

838

MSI

Size Document Description Rev

Custom

Date:

Monday, January 18, 2010

Date:

Monday, January 18, 2010

Date:

Monday, January 18, 2010

CPU1J

A16

VSS

A25

VSS

A28

VSS

A34

VSS

A37

VSS

D D

C C

B B

A A

AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB40

AE37

AF40

AG34 AG36

AH33 AH38

AJ12 AJ14 AJ16 AJ18 AJ20 AJ22 AJ24 AJ26 AJ28 AJ30 AJ33 AJ34 AJ40

AK10 AK17 AK36

AL11 AL13 AL16 AL19 AL22 AL25 AL28

AL31 AL34 AL38

AM40

AN13 AN20 AN22 AN25 AN28 AN31

AN36

AP12 AP15 AP16 AP17 AP20 AP24 AP26 AP27 AP29

AP35

AG7 AH3

AK5 AK8

AM1 AK4

AM5 AM9

AN4

AN9

AA5

VSS

AB3

VSS VSS VSS VSS VSS VSS VSS VSS VSS

AB6

VSS

AB8

VSS

AC1

VSS

AD5

VSS

AD8

VSS

AE3

VSS VSS

AE7

VSS

AF1

VSS VSS

AF6

VSS VSS VSS

AH5

VSS VSS VSS VSS VSS

AJ1

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ6

VSS

AJ9

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AL3

VSS VSS VSS VSS

AL7

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

10 OF 12

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AP33 AP38 AP4 AP7 AP9 AR1 AR20 AR23 AR40 AT12 AT14 AT16 AT2 AT24 AT27 AT30 AR30 AT34 AT37 AT5 AU32 AT8 AV3 AV31 AV34 AU36 AU6 AY33 AY36 AY4 AY7 B16 B24 B27 B30 B33 B36 B7 B9 C13 C16 C19 C22 C26 C29 C32 C35 C38 C5 D10 D12 D13 D16 D19 D22 D25 D28 D31 D34 D37 D4 D40 D5 D6 D8 E13 E16 E19 E21 E24 E27 E3 E30 E33 E36 E39 E4 F11 F13 F16 F2 F20 F23 F26 F29 F32 F35 F38 F8 G13

W33 W34

CPU1K

G16

VSS

G19

VSS

G22

VSS

G25

VSS

G28

VSS

G31

VSS

G34

VSS

G37

VSS

G40

VSS

H11

VSS

H13

VSS

H16

VSS

H18

VSS

H21

VSS

H24

VSS

H27

VSS

H30

VSS

H33

VSS

H36

VSS

H39

VSS

J13

VSS

J17

VSS

J20

VSS

J23

VSS

J26

VSS

J29

VSS

J32

VSS

J35

VSS

J38

VSS

K11

VSS

K13

VSS

K19

VSS

K22

VSS

K25

VSS

K28

VSS

K31

VSS

K34

VSS

K37

VSS

K40

VSS

L13

VSS

L18

VSS

L21

VSS

L24

VSS

L27

VSS

L30

VSS

L33

VSS

L36

VSS

L39

VSS

M13

VSS

M18

VSS

M20

VSS

M23

VSS

M26

VSS

M29

VSS

M32

VSS

M35

VSS

M38

VSS

N34

VSS

N37

VSS

N40

VSS

T33

VSS

T36

VSS

T37

VSS

T38

VSS

VSS VSS VSS

11 OF 12

VSS VSS VSS VSS VSS

VSS_NCTF

GND

W35 W36 W37 W38 Y7 B39

VREF_DQ_B

TP_CGC DIMM_VREFA

TP19TP19

NOTE:R310,R316 STUFFED,IF DDR3 DIMM VREFDQ OPTION 2 UNSTUFFED.

FOLLOW DDR3 DIMM VREFDQ Platform Design Guide Change Option 3

FOLLOW WW11, 18 2009. Havendale and Clarkdale must stuff.

Channel A and B Output DDR3 DIMM DQ Reference Voltage. NOTE: This signal is reserved for possible future use, and may not be driven on initial steppings. Refer to the Platform Design Guide for DIMM DQ VREF implementation details.

stuff or unstuff ?????

VREF_DQ_A

close to DIMM

R353 X_0RR353 X_0R R351 X_0RR351 X_0R

DIMM_VREFB

AG3

AH40

AJ39

AN11

A12

AD2 AE2 AF3

AU7

AY3

CPU1L

VDDIO

RSVD

RSVD RSVD RSVD RSVD VSS RSVD RSVD

RSVD RSVD

NC/SPARE

12 OF 12

MICRO-STAR INT'L CO.,LTD

MS-7638

CPU-GND

MS-7638

Sheet of

938

MSI

Size Document Description Rev

Custom

Date:

Monday, January 18, 2010

Date:

Monday, January 18, 2010

Date:

Monday, January 18, 2010

DDRIII DIMM_A1 DDRIII DIMM_A2

VCC_DDR VCC3

DIMM2

DQ0

VDD51VDD DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

107

110

113

116

119

VSS

4 9

10 122 123 128 129

19 131 132 137 138

28 140 141 146 147

37 149 150 155 156

88 200 201 206 207

97 209 210 215 216

99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

101 104

170

173

176

179

VDD

DDR3

VSS

121

124

127

130

133

136

139

142

145

148

151

182

183

186

VDD

VSS

154

157

160

DIMM1

DQ0

DQ1

DQ2

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

DQ8

DQ9

DQ10

DQ11

131

DQ12

132

DQ13

137

DQ14

138

DQ15

DQ16

DQ17

DQ18

DQ19

140

DQ20

141

DQ21

146

DQ22

147

DQ23

DQ24

DQ25

DQ26

DQ27

149

DQ28

150

DQ29

155

DQ30

156

DQ31

DQ32

DQ33

DQ34

DQ35

200

DQ36

201

DQ37

206

DQ38

207

DQ39

DQ40

DQ41

DQ42

DQ43

209

DQ44

210

DQ45

215

DQ46

216

DQ47

DQ48

100

DQ49

105

DQ50

106

DQ51

218

DQ52

219

DQ53

224

DQ54

225

DQ55

108

DQ56

109

DQ57

114

DQ58

115

DQ59

227

DQ60

228

DQ61

233

DQ62

234

DQ63

VSS

101

VSS

104

VSS

5VDIMM

U12

VCC

BUS_SEL

SCL

SDA

GND

UP6262BMA8_SOT23-8-RH

VCC_DDR

VDD51VDD

VSS

107

110

VSS

113

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

116

119

121

124

127

130

133

136

VREF_CA_A

OUT1

VREF_CA_B

OUT2

OUT3

170

173

176

VDD

DDR3

VSS

139

142

145

148

179

VDD

VSS

151

MEM_MA_DATA[63..0]7

D D

VCC3

C67 C0.1u16Y0402C67 C0.1u16Y0402

C C

Place close to DIMM1

VCC_DDR

C87 C2.2u6.3YC87 C2.2u6.3Y C183 C220p10XC183 C220p10X C68 C2.2u6.3YC68 C2.2u6.3Y C93 C2.2u6.3YC93 C2.2u6.3Y

Place close to DIMM1 with DIMM2

VCC_DDR

C184 C1u6.3Y0402-RHC184 C1u6.3Y0402-RH

Place close to DIMM2

VCC_DDR

C145 C1u6.3Y0402-RHC145 C1u6.3Y0402-RH C117 C1u6.3Y0402-RHC117 C1u6.3Y0402-RH

B B

UPI VOLTAGE CONSOLE

VREF_CA_A

C146

C146 C0.1u16Y0402

C0.1u16Y0402

UPI VOLTAGE CONSOLE

VREF_DQ_A

C223

C223 C0.1u16Y0402

C0.1u16Y0402

A A

UPI VOLTAGE CONSOLE(2)

2.083325V

0x26:RH=18K,RL=13K

MEM_MA_DATA[63..0]

R258 1KR1%0402R258 1KR1%0402

R259

R259 1KR1%0402

1KR1%0402

R362 1KR1%0402R362 1KR1%0402

R360

R360 1KR1%0402

1KR1%0402

VCC_DDR

SMBCLK11,12,15,19,21,30,35

SMBDATA11,12,15,19,21,30,35

MEM_MA_DATA0 MEM_MA_DATA1 MEM_MA_DATA2 MEM_MA_DATA3 MEM_MA_DATA4 MEM_MA_DATA5 MEM_MA_DATA6 MEM_MA_DATA7 MEM_MA_DATA8 MEM_MA_DATA9 MEM_MA_DATA10 MEM_MA_DATA11 MEM_MA_DATA12 MEM_MA_DATA13 MEM_MA_DATA14 MEM_MA_DATA15 MEM_MA_DATA16 MEM_MA_DATA17 MEM_MA_DATA18 MEM_MA_DATA19 MEM_MA_DATA20 MEM_MA_DATA21 MEM_MA_DATA22 MEM_MA_DATA23 MEM_MA_DATA24 MEM_MA_DATA25 MEM_MA_DATA26 MEM_MA_DATA27 MEM_MA_DATA28 MEM_MA_DATA29 MEM_MA_DATA30 MEM_MA_DATA31 MEM_MA_DATA32 MEM_MA_DATA33 MEM_MA_DATA34 MEM_MA_DATA35 MEM_MA_DATA36 MEM_MA_DATA37 MEM_MA_DATA38 MEM_MA_DATA39 MEM_MA_DATA40 MEM_MA_DATA41 MEM_MA_DATA42 MEM_MA_DATA43 MEM_MA_DATA44 MEM_MA_DATA45 MEM_MA_DATA46 MEM_MA_DATA47 MEM_MA_DATA48 MEM_MA_DATA49 MEM_MA_DATA50 MEM_MA_DATA51 MEM_MA_DATA52 MEM_MA_DATA53 MEM_MA_DATA54 MEM_MA_DATA55 MEM_MA_DATA56 MEM_MA_DATA57 MEM_MA_DATA58 MEM_MA_DATA59 MEM_MA_DATA60 MEM_MA_DATA61 MEM_MA_DATA62 MEM_MA_DATA63

C100

C100 X_C2.2u6.3Y

X_C2.2u6.3Y

5VDIMM

R269

X_18KR1%0402

R267 X_13KR1%0402R267 X_13KR1%0402

SMBCLK SMBDATA

182

154

VDD

VSS

183

186

VDD

VSS

157

160

189

191

194

VDD

VSS

163

166

199

VREF_CA_A VREF_CA_B

VCC3

VTT_DDR

197

236

VDD

VDDSPD

VSS

202

205

208

167

120

240

187

198

MEM_MA_ADD0

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

211

214

217

220

223

226

229

232

SMBCLK_DDR11 SMBDATA_DDR11

188

MEM_MA_ADD1

181

FREE1

FREE249FREE3

FREE4

MEM_MA_ADD2

MEM_MA_ADD3

180

MEM_MA_ADD4

MEM_MA_ADD5

MEM_MA_ADD6

178

MEM_MA_ADD7

MEM_MA_ADD8

177

MEM_MA_ADD9

175

MEM_MA_ADD10

A10/AP

MEM_MA_ADD11

A11

MEM_MA_ADD12

174

A12

MEM_MA_ADD13

196

A13

MEM_MA_ADD14

172

A14

MEM_MA_ADD15 MEM_MA_ADD15

171

A15

CB0

CB1

CB2

CB3

158

CB4

159

CB5

164

CB6

165

CB7

MEM_MA_DQS_H0

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

DM0/DQS9

NC/DQS9#

DM1/DQS10

NC/DQS10#

DM2/DQS11

NC/DQS11#

DM3/DQS12

NC/DQS12#

DM4/DQS13

NC/DQS13#

DM5/DQS14

NC/DQS14#

DM6/DQS15

NC/DQS15#

DM7/DQS16

NC/DQS16#

DM8/DQS17

NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ VREFCA

VSS

MEC1

235

239

MEC1

MEC2

MEM_MA_DQS_L0

MEM_MA_DQS_H1

MEM_MA_DQS_L1

MEM_MA_DQS_H2

MEM_MA_DQS_L2

MEM_MA_DQS_H3

MEM_MA_DQS_L3

MEM_MA_DQS_H4

MEM_MA_DQS_L4

MEM_MA_DQS_H5

MEM_MA_DQS_L5

MEM_MA_DQS_H6

103

MEM_MA_DQS_L6

102

MEM_MA_DQS_H7

112

MEM_MA_DQS_L7

111 43 42

MEM_MA_DM0

125 126

MEM_MA_DM1

134 135

MEM_MA_DM2

143 144

MEM_MA_DM3

152 153

MEM_MA_DM4

203 204

MEM_MA_DM5

212 213

MEM_MA_DM6

221 222

MEM_MA_DM7

230 231 161 162

MEM_MA_ODT0

195

ODT0

MEM_MA_ODT1

ODT1

MEM_MA_CKE0

CKE0

MEM_MA_CKE1

169

CKE1

MEM_MA_CS_L0

193

CS0#

MEM_MA_CS_L1

CS1#

MEM_MA_BANK0

BA0

MEM_MA_BANK1

190

BA1

MEM_MA_BANK2

BA2

MEM_MA_WE_L

WE#

MEM_MA_RAS_L

192

RAS#

MEM_MA_CAS_L

CAS#

168

MEM_MA_CLK_H0

184

CK0

MEM_MA_CLK_L0

185

CK0#

MEM_MA_CLK_H1

MEM_MA_CLK_L1

VREF_DQ_A

VREF_CA_A

SMBCLK_DDR

118

SCL

SMBDATA_DDR

238

SDA

237

SA1

117

SA0

MEC2

MEC3

DDEIII-240_BLUE-R

DIMM1(CHANNEL-A)

MEC3

ADDRESS = 0:0 [SA1:SA0]

SMBCLK_DDR SMBDATA_DDR

MEM_MA_DM0 7 MEM_MA_DM1 7 MEM_MA_DM2 7 MEM_MA_DM3 7 MEM_MA_DM4 7 MEM_MA_DM5 7 MEM_MA_DM6 7 MEM_MA_DM7 7

MEM_MA_ODT0 7 MEM_MA_ODT1 7 MEM_MA_CKE0 7 MEM_MA_CKE1 7 MEM_MA_CS_L0 7 MEM_MA_CS_L1 7 MEM_MA_BANK0 7 MEM_MA_BANK1 7 MEM_MA_BANK2 7

MEM_MA_WE_L 7 MEM_MA_RAS_L 7 MEM_MA_CAS_L 7

MEM_MA_CLK_H0 7 MEM_MA_CLK_L0 7 MEM_MA_CLK_H1 7 MEM_MA_CLK_L1 7

C125

C0.1u16Y0402

R151 33R0402R151 33R0402 R154 33R0402R154 33R0402

MEM_MA_ADD[15..0] 7

MEM_MA_DQS_H0 7 MEM_MA_DQS_L0 7 MEM_MA_DQS_H1 7 MEM_MA_DQS_L1 7 MEM_MA_DQS_H2 7 MEM_MA_DQS_L2 7 MEM_MA_DQS_H3 7 MEM_MA_DQS_L3 7 MEM_MA_DQS_H4 7 MEM_MA_DQS_L4 7 MEM_MA_DQS_H5 7 MEM_MA_DQS_L5 7 MEM_MA_DQS_H6 7 MEM_MA_DQS_L6 7 MEM_MA_DQS_H7 7 MEM_MA_DQS_L7 7

C222

C222 C0.1u16Y0402

C0.1u16Y0402

SMBCLK 11,12,15,19,21,30,35 SMBDATA 11,12,15,19,21,30,35

DDR3_DRAMRST#A 7

Must stuff R173 R175

VTT_DDR

189

191

194

197

236

VDD

VDDSPD

VSS

163

166

199

202

205

208

167

120

240

187

198

MEM_MA_ADD0

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

211

214

217

220

223

226

229

232

MSI

188

MEM_MA_ADD1

181

FREE1

FREE249FREE3

FREE4

MEM_MA_ADD2

MEM_MA_ADD3

180

MEM_MA_ADD4

MEM_MA_ADD5

MEM_MA_ADD6

178

MEM_MA_ADD7

MEM_MA_ADD8

177

MEM_MA_ADD9

175

MEM_MA_ADD10

A10/AP

MEM_MA_ADD11

A11

MEM_MA_ADD12

174

A12

MEM_MA_ADD13

196

A13

MEM_MA_ADD14

172

A14

171

A15

CB0

CB1

CB2

CB3

158

CB4

159

CB5

164

CB6

165

CB7

MEM_MA_DQS_H0

DQS0

MEM_MA_DQS_L0

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS8#

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ VREFCA

VSS

MEC1

235

239

MEC1

MEM_MA_DQS_H1

DQS1

MEM_MA_DQS_L1

MEM_MA_DQS_H2

DQS2

MEM_MA_DQS_L2

MEM_MA_DQS_H3

DQS3

MEM_MA_DQS_L3

MEM_MA_DQS_H4

DQS4

MEM_MA_DQS_L4

MEM_MA_DQS_H5

DQS5

MEM_MA_DQS_L5

MEM_MA_DQS_H6

103

DQS6

MEM_MA_DQS_L6

102

MEM_MA_DQS_H7

112

DQS7

MEM_MA_DQS_L7

111 43

DQS8

MEM_MA_DM0

125 126

MEM_MA_DM1

134 135

MEM_MA_DM2

143 144

MEM_MA_DM3

152 153

MEM_MA_DM4

203 204

MEM_MA_DM5

212 213

MEM_MA_DM6

221 222

MEM_MA_DM7

230 231 161 162

MEM_MA_ODT2

195

ODT0

MEM_MA_ODT3

ODT1

MEM_MA_CKE2

CKE0

MEM_MA_CKE3

169

CKE1

MEM_MA_CS_L2

193

CS0#

MEM_MA_CS_L3

CS1#

MEM_MA_BANK0

BA0

MEM_MA_BANK1

190

BA1

MEM_MA_BANK2

BA2

MEM_MA_WE_L

WE#

MEM_MA_RAS_L

192

RAS#

MEM_MA_CAS_L

CAS#

DDR3_DRAMRST#A

168

MEM_MA_CLK_H2

184

CK0

MEM_MA_CLK_L2

185

CK0#

MEM_MA_CLK_H3

MEM_MA_CLK_L3

VREF_DQ_A

VREF_CA_A

SMBCLK_DDR

118

SCL

SMBDATA_DDR

238

SDA

237

SA1

117

SA0

MEC2

MEC3

MEC2

MEC3

Size Document Description Rev

Custom

Date:

VCC3

DDEIII-240_PINK-R

DIMM2(CHANNEL-A) ADDRESS = 0:1 [SA1:SA0]

MICRO-STAR INT'L CO.,LTD

DDR3 Chanel-A DIMM1/2

Wednesday, January 20, 2010

C124

C124 C0.1u16Y0402

C0.1u16Y0402

MS-7638

MEM_MA_ODT2 7 MEM_MA_ODT3 7 MEM_MA_CKE2 7 MEM_MA_CKE3 7 MEM_MA_CS_L2 7 MEM_MA_CS_L3 7

MEM_MA_CLK_H2 7 MEM_MA_CLK_L2 7 MEM_MA_CLK_H3 7 MEM_MA_CLK_L3 7

Sheet of

C225

C225 C0.1u16Y0402

C0.1u16Y0402

10 38

DDRIII DIMM_B1 DDRIII DIMM_B2

VCC_DDR

MEM_MB_DATA[63..0]7

DIMM3

8 7 6

DIMM3

DQ0

VDD51VDD

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

107

110

113

116

119

Vref-DQ : Reference voltage for DQ0 DQ63, CB0 CB7 and PAR_IN. When in single ended mode used for DQS0 DQS7.

Vref-CA : Reference voltage for A0-A15, BA0 BA2, RAS#, CAS#, WE#, S0#, S01#, CKE0, CKE1, ODT0 and ODT1. RESET#(Output) : A synchronously forces all registered output LOW when RESET# is LOW. This signal can be used during power up to ensure that CKE is LOW and DQs are High-Z.

V1_8SET VREF_DQ_A VREF_DQ_B

122 123 128 129

131 132 137 138

140 141 146 147

149 150 155 156

200 201 206 207

209 210 215 216

100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

101 104

V1_8SET

4 9

12 13 18 19

21 22 27 28

30 31 36 37

81 82 87 88

90 91 96 97

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

MEM_MB_DATA0

D D

EMI

VCC_DDR

C186

C102

0.1u/10X

VCC_DDR

C99

C148

0.1u/10X

C C

Place close to DIMM3

VCC_DDR

C136 C1u16YC136 C1u16Y

Place close to DIMM3 with DIMM4

VCC_DDR

C107 C1u16YC107 C1u16Y C88 C1u6.3Y0402-RHC88 C1u6.3Y0402-RH C185 C1u6.3Y0402-RHC185 C1u6.3Y0402-RH

B B

VREF_CA_B

C122

C122 C0.1u16Y0402

C0.1u16Y0402

VREF_DQ_B

C216

C216 C0.1u16Y0402

C0.1u16Y0402

UPI VOLTAGE CONSOLE(3)

A A

R346 X_3K/1%R346 X_3K/1%

5VDIMM

R352

R352 X_9.1K/1%

X_9.1K/1%

SMBCLK SMBDATA

R260 1KR1%0402R260 1KR1%0402

R250

R250 1KR1%0402

1KR1%0402

R376 1KR1%0402R376 1KR1%0402

R363

R363 1KR1%0402

1KR1%0402

VCC5 5VDIMM

R380

R380 X_0R

X_0R

R371 X_0RR371 X_0R R370 X_0RR370 X_0R

MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

VCC_DDR

C92

C92 X_C0.1u16Y0402

X_C0.1u16Y0402

VCC_DDR

0x28:RH=9.1K,RL=3K

R379

U16

X_0R

VCC

BUS_SEL

SCL

SDA

GND

UP6262BMA8_SOT23-8-RH

OUT1 OUT2 OUT3

170

173

176

179

VDD

DDR3

VSS

121

124

127

130

133

136

139

142

145

148

151

VCC3

VTT_DDR

182

183

186

189

191

194

197

236

VDD

VDDSPD

VSS

154

157

160

163

166

199

202

205

208

167

120

240

187

198

MEM_MB_ADD0

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

211

214

217

220

223

226

229

232

188

MEM_MB_ADD1

181

FREE1

FREE249FREE3

FREE4

MEM_MB_ADD2

MEM_MB_ADD3

180

MEM_MB_ADD4

MEM_MB_ADD5

MEM_MB_ADD6

178

MEM_MB_ADD7

MEM_MB_ADD8

177

MEM_MB_ADD9

175

MEM_MB_ADD10

A10/AP

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

DM0/DQS9

NC/DQS9#

DM1/DQS10

NC/DQS10#

DM2/DQS11

NC/DQS11#

DM3/DQS12

NC/DQS12#

DM4/DQS13

NC/DQS13#

DM5/DQS14

NC/DQS14#

DM6/DQS15

NC/DQS15#

DM7/DQS16

NC/DQS16#

DM8/DQS17

NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ VREFCA

VSS

MEC1

235

239

MEC1

MEC2

MEM_MB_ADD11

A11

MEM_MB_ADD12

174

A12

MEM_MB_ADD13

196

A13

MEM_MB_ADD14

172

A14

171

A15

CB0

CB1

CB2

CB3

158

CB4

159

CB5

164

CB6

165

CB7

MEM_MB_DQS_H0

MEM_MB_DQS_L0

MEM_MB_DQS_H1

MEM_MB_DQS_L1

MEM_MB_DQS_H2

MEM_MB_DQS_L2

MEM_MB_DQS_H3

MEM_MB_DQS_L3

MEM_MB_DQS_H4

MEM_MB_DQS_L4

MEM_MB_DQS_H5

MEM_MB_DQS_L5

MEM_MB_DQS_H6

103

MEM_MB_DQS_L6

102

MEM_MB_DQS_H7

112

MEM_MB_DQS_L7

111 43 42

MEM_MB_DM0

125 126

MEM_MB_DM1

134 135

MEM_MB_DM2

143 144

MEM_MB_DM3

152 153

MEM_MB_DM4

203 204

MEM_MB_DM5

212 213

MEM_MB_DM6

221 222

MEM_MB_DM7

230 231 161 162

MEM_MB_ODT0

195

ODT0

MEM_MB_ODT1

ODT1

MEM_MB_CKE0

CKE0

MEM_MB_CKE1

169

CKE1

MEM_MB_CS_L0

193

CS0#

MEM_MB_CS_L1

CS1#

MEM_MB_BANK0

BA0

MEM_MB_BANK1

190

BA1

MEM_MB_BANK2

BA2

MEM_MB_WE_L

WE#

MEM_MB_RAS_L

192

RAS#

MEM_MB_CAS_L

CAS#

168

MEM_MB_CLK_H0

184

CK0

MEM_MB_CLK_L0

185

CK0#

MEM_MB_CLK_H1

MEM_MB_CLK_L1

VREF_DQ_B

VREF_CA_B VREF_CA_B

SMBCLK_DDR SMBCLK_DDR

118

SCL

SMBDATA_DDR

238

SDA

237

SA1

117

SA0

MEC2

MEC3

DDEIII-240_BLUE-R

DIMM3(CHANNEL-B)

MEC3

ADDRESS = 1:0 [SA1:SA0]

VCC3

C132

C0.1u16Y0402

MEM_MB_ADD[15..0] 7

MEM_MB_DQS_H0 7 MEM_MB_DQS_L0 7 MEM_MB_DQS_H1 7 MEM_MB_DQS_L1 7 MEM_MB_DQS_H2 7 MEM_MB_DQS_L2 7 MEM_MB_DQS_H3 7 MEM_MB_DQS_L3 7 MEM_MB_DQS_H4 7 MEM_MB_DQS_L4 7 MEM_MB_DQS_H5 7 MEM_MB_DQS_L5 7 MEM_MB_DQS_H6 7 MEM_MB_DQS_L6 7 MEM_MB_DQS_H7 7 MEM_MB_DQS_L7 7

MEM_MB_DM0 7 MEM_MB_DM1 7 MEM_MB_DM2 7 MEM_MB_DM3 7 MEM_MB_DM4 7 MEM_MB_DM5 7 MEM_MB_DM6 7 MEM_MB_DM7 7

MEM_MB_ODT0 7 MEM_MB_ODT1 7 MEM_MB_CKE0 7 MEM_MB_CKE1 7 MEM_MB_CS_L0 7 MEM_MB_CS_L1 7 MEM_MB_BANK0 7 MEM_MB_BANK1 7 MEM_MB_BANK2 7

MEM_MB_WE_L 7 MEM_MB_RAS_L 7 MEM_MB_CAS_L 7 DDR3_DRAMRST#B 7

MEM_MB_CLK_H0 7 MEM_MB_CLK_L0 7 MEM_MB_CLK_H1 7 MEM_MB_CLK_L1 7

C217

C217 C0.1u16Y0402

C0.1u16Y0402

MEM_MB_DATA0 MEM_MB_DATA1 MEM_MB_DATA2 MEM_MB_DATA3 MEM_MB_DATA4 MEM_MB_DATA5 MEM_MB_DATA6 MEM_MB_DATA7 MEM_MB_DATA8 MEM_MB_DATA9 MEM_MB_DATA10 MEM_MB_DATA11 MEM_MB_DATA12 MEM_MB_DATA13 MEM_MB_DATA14 MEM_MB_DATA15 MEM_MB_DATA16 MEM_MB_DATA17 MEM_MB_DATA18 MEM_MB_DATA19 MEM_MB_DATA20 MEM_MB_DATA21 MEM_MB_DATA22 MEM_MB_DATA23 MEM_MB_DATA24 MEM_MB_DATA25 MEM_MB_DATA26 MEM_MB_DATA27 MEM_MB_DATA28 MEM_MB_DATA29 MEM_MB_DATA30 MEM_MB_DATA31 MEM_MB_DATA32 MEM_MB_DATA33 MEM_MB_DATA34 MEM_MB_DATA35 MEM_MB_DATA36 MEM_MB_DATA37 MEM_MB_DATA38 MEM_MB_DATA39 MEM_MB_DATA40 MEM_MB_DATA41 MEM_MB_DATA42 MEM_MB_DATA43 MEM_MB_DATA44 MEM_MB_DATA45 MEM_MB_DATA46 MEM_MB_DATA47 MEM_MB_DATA48 MEM_MB_DATA49 MEM_MB_DATA50 MEM_MB_DATA51 MEM_MB_DATA52 MEM_MB_DATA53 MEM_MB_DATA54 MEM_MB_DATA55 MEM_MB_DATA56 MEM_MB_DATA57 MEM_MB_DATA58 MEM_MB_DATA59 MEM_MB_DATA60 MEM_MB_DATA61 MEM_MB_DATA62 MEM_MB_DATA63

SMBCLK

SMBCLK10,12,15,19,21,30,35

SMBDATA

SMBDATA10,12,15,19,21,30,35

SMBCLK_DDR SMBDATA_DDR

SMBCLK_DDR 10 SMBDATA_DDR 10

VCC_DDR VCC3

DIMM4

DQ0

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VDD57VDD60VDD62VDD65VDD66VDD69VDD72VDD75VDD78VDD

VSS

107

110

113

116

119

VSS

4 9

10 122 123 128 129

19 131 132 137 138

28 140 141 146 147

37 149 150 155 156

88 200 201 206 207

97 209 210 215 216

99 100 105 106 218 219 224 225 108 109 114 115 227 228 233 234

2 5

8 11 14 17 20 23 26 29 32 35 38 41 44 47 80 83 86 89 92 95 98

101 104

170

173

176

179

VDD

DDR3

VSS

121

124

127

130

133

136

139

142

145

148

151

182

183

186

VDD

VSS

154

157

160

VTT_DDR

189

191

194

197

236

VDD

VDDSPD

VSS

163

166

199

202

205

208

167

120

240

187

198

MEM_MB_ADD0

VTT

RSVD

NC/TEST4

NC/PAR_IN

NC/ERR_OUT

VSS

211

214

217

220

223

226

229

232

MSI

188

MEM_MB_ADD1

181

FREE1

FREE249FREE3

FREE4

MEM_MB_ADD2

MEM_MB_ADD3

180

MEM_MB_ADD4

MEM_MB_ADD5

MEM_MB_ADD6

178

MEM_MB_ADD7

MEM_MB_ADD8

177

MEM_MB_ADD9

175

MEM_MB_ADD10

A10/AP

DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS8#

DM0/DQS9

NC/DQS9# DM1/DQS10 NC/DQS10# DM2/DQS11 NC/DQS11# DM3/DQS12 NC/DQS12# DM4/DQS13 NC/DQS13# DM5/DQS14 NC/DQS14# DM6/DQS15 NC/DQS15# DM7/DQS16 NC/DQS16# DM8/DQS17 NC/DQS17#

RESET#

CK1(NU)

CK1#(NU)

VREFDQ VREFCA

VSS

MEC1

235

239

MEC1

MEM_MB_ADD11

A11

MEM_MB_ADD12

174

A12

MEM_MB_ADD13

196

A13

MEM_MB_ADD14

172

A14

MEM_MB_ADD15MEM_MB_ADD15

171

A15

CB0

CB1

CB2

CB3

158

CB4

159

CB5

164

CB6

165

CB7

MEM_MB_DQS_H0

DQS0

MEM_MB_DQS_L0

MEM_MB_DQS_H1

DQS1

MEM_MB_DQS_L1

MEM_MB_DQS_H2

DQS2

MEM_MB_DQS_L2

MEM_MB_DQS_H3

DQS3

MEM_MB_DQS_L3

MEM_MB_DQS_H4

DQS4

MEM_MB_DQS_L4

MEM_MB_DQS_H5

DQS5

MEM_MB_DQS_L5

MEM_MB_DQS_H6

103

DQS6

MEM_MB_DQS_L6

102

MEM_MB_DQS_H7

112

DQS7

MEM_MB_DQS_L7

111 43

DQS8

MEM_MB_DM0

125 126

MEM_MB_DM1

134 135

MEM_MB_DM2

143 144

MEM_MB_DM3

152 153

MEM_MB_DM4

203 204

MEM_MB_DM5

212 213

MEM_MB_DM6

221 222

MEM_MB_DM7

230 231 161 162

MEM_MB_ODT2

195

ODT0

MEM_MB_ODT3

ODT1

MEM_MB_CKE2

CKE0

MEM_MB_CKE3

169

CKE1

MEM_MB_CS_L2

193

CS0#

MEM_MB_CS_L3

CS1#

MEM_MB_BANK0

BA0

MEM_MB_BANK1

190

BA1

MEM_MB_BANK2

BA2

MEM_MB_WE_L

WE#

MEM_MB_RAS_L

192

RAS#

MEM_MB_CAS_L

CAS#

DDR3_DRAMRST#B

168

MEM_MB_CLK_H2

184

CK0

MEM_MB_CLK_L2

185

CK0#

MEM_MB_CLK_H3

MEM_MB_CLK_L3

VREF_DQ_B

1 67 118

SCL

SMBDATA_DDR

238

SDA

237

SA1

117

SA0

MEC2

MEC3

MEC2

MEC3

Size Document Description Rev

Custom

Date:

VCC3

DDEIII-240_PINK-R

DIMM4(CHANNEL-B) ADDRESS = 1:1 [SA1:SA0]

MICRO-STAR INT'L CO.,LTD

DDR3 Chanel-B DIMM3/4

Wednesday, January 20, 2010

C0.1u16Y0402

MS-7638

MEM_MB_ODT2 7 MEM_MB_ODT3 7 MEM_MB_CKE2 7 MEM_MB_CKE3 7 MEM_MB_CS_L2 7 MEM_MB_CS_L3 7

MEM_MB_CLK_H2 7 MEM_MB_CLK_L2 7 MEM_MB_CLK_H3 7 MEM_MB_CLK_L3 7

C123

Sheet of

C226

C226 C0.1u16Y0402

C0.1u16Y0402

11 38

3VSB VCC3

R486

X_4.7K

SLP_S5#15,18,30 SLP_S4#15,18,30,31

D D

WDT#18,29,30

VRM_PGD15,30,35

SMBCLK10,11,15,19,21,30,35

SMBDATA10,11,15,19,21,30,35

R497 X_1K/1%R497 X_1K/1% R485 X_1K/1%R485 X_1K/1% R484 0RR484 0R R458 1K/1%R458 1K/1%

SMBCLK SMBDATA

X_4.7K

R500 0RR500 0R R501 0RR501 0R

R475

4.7K

CK_RESET#

DOC_0 DOC_1

U20

*RLATCH/RESET_IN#/RESET#

VTTPWRGD/WOL_STOP#

DOC_0**

DOC_1**

SCLK

SDATA

CPUT_LR CPUC_LR

PCIEXT_LR

PCIEXC_LR

DOT96T_LR

DOT96C_LR

SATACLKT_LR SATACLKC_LR

CLKGEN133M_P_R

CLKGEN133M_N_R

CLK100M_DMI_P_R

CLK100M_DMI_N_R

CLK96M_DOT_P_R

CLK96M_DOT_N_R

CLK100M_SATA_P_R

CLK100M_SATA_N_R

R502 0RR502 0R R503 0RR503 0R

R492 0RR492 0R R489 0RR489 0R

R473 0RR473 0R R471 0RR471 0R

R455 0RR455 0R R456 0RR456 0R

CLKGEN133M_P 13

CLKGEN133M_N 13

CLK100M_DMI_P 13 CLK100M_DMI_N 13

CLK96M_DOT_P 13 CLK96M_DOT_N 13

CLK100M_SATA_P 13 CLK100M_SATA_N 13

CLOCK GEN STRAPING

FS4

FS3

FS2

FSB

FSA

B0b4

0 0 0 0

B0b3

B0b2 0 0 0 0

FSA_14P8_REF

0 0 0 0

B0b1

B0b0 00 001 1 11

CPU Mhz

100.00

133.33

200.00

166.66

R463 4.7KR463 4.7K R457 X_4.7KR457 X_4.7K

Spread %

-0.5

VCC3

Place damping resistor close to clock-gen

FSLB

TP16TP16

VCC3

C C

VCC3

FB4 X_FB80/8FB4 X_FB80/8

CP9 X_COPPERCP9 X_COPPER

FB2 X_FB80/8FB2 X_FB80/8

CP4 X_COPPERCP4 X_COPPER

CK_14P8M_PCH13

C398

C373

C392

10u/10Y/8

C345

C345 10u/10Y/8

10u/10Y/8

C392

0.1u/16X

C342

0.1u/16X

CK_14P8M_PCH FSA_14P8_REF

C388

0.1u/16X

C357

0.1u/16X

R452 33RR452 33R

VCC3_CLK1

C389

0.1u/16X

VCC3_CLK2

C351

0.1u/16X

16 29

3 7

22 25 28

24_12M 48M/FSLB 25M

VDDCPU VDDPCIEX VDD96

VDDREF VDDSATA VDD25

REF/FSLA

GNDCPU

GNDPCIEX

GND96

GNDREF

GNDSATA

GND25

THERMAL_GND

ICS9LPRS4105B

FSLB

XTAL1

XTAL2

4 8 12

18 26 27

14.318MHZ16P_D

1 2

C333 22p/50NC333 22p/50N

C332 22p/50NC332 22p/50NC388

Pin16: 48MHz clock output. / 3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs, see input electrical characteristics for Vil_FS and Vih_FS values.

Pin19: 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.

R459 X_4.7KR459 X_4.7K R466 4.7KR466 4.7K

VCC3

DOC_0**:Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will transition to a preprogrammed value in the I2C.

B B

VCC3

DOC_1

R831 X_0RR831 X_0R

SIO_GPIO27

DOC_0

SIO_GPIO26

R822 0RR822 0R

VCC3

R836 X_0RR836 X_0R R835 0RR835 0R

SIO_GPIO2718

SIO_GPIO2618

A A

R838

8.2K/4

R837

8.2K/4

OC_SW1

OFF / ON

2A22B

1A11B

N73-0200081-D02

OFF OFF

OC_SW1

SW-DIPP2-RH

( Default ) OFF / OFF

OFF / ON ON / OFF ON / ON

OFF=1 ; ON=0

DOC

133 MHz ( default )

142 MHz

150 MHz

166 MHz

TABLE

CPU FREQUENCY

FSLB CK_14P8M_PCH

C353 X_10p/50NC353 X_10p/50N C334 X_10p/50NC334 X_10p/50N

MSI

EMI

R487 X_4.7KR487 X_4.7K R499 X_4.7KR499 X_4.7K

MICRO-STAR INT'L CO.,LTD

Size Document Description Rev

Custom

CLK ICS9LRS4105B

Date:

Monday, January 18, 2010

Date:

Monday, January 18, 2010

Date:

Monday, January 18, 2010

DOC_0 DOC_1

MS-7638

12 38

Sheet of

+ 25 hidden pages

MSI MS-7638 Schematics rev.1.0

Specifications and Main Features

Frequently Asked Questions

User Manual