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MS-7539
Schematics
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MSI MS-7539 Schematics

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CONFIDENTIAL
NVIDIA
STATUTORY OR OTHERWISE WITH RESPECT TO THE
MATERIALS) ARE BEING PROVIDED AS IS. NVIDIA MAKES NO WARRANTIES, EXPRESSED, IMPLIED,
MATERIALS, AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
ALL NVIDIA DESIGN SPECIFICATION, REFERENCE BOARDS, FILTERS, DRAWINGS, DIAGNOSTICS, LISTS AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY,
SANTA CLARA, CA 95050
2701 SAN TOMAS EXPRESSWAY
NVIDIA CORPORATION
DOC NUMBER
TITLE
DATE
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PAGE 1: COVER PAGE PAGE 2: BLOCK DIAGRAM PAGE 3: RESET MAP PAGE 4: CLOCK DISTRIBUTION PAGE 5: SOFTWARE MAPPING PAGE 6: JUMPERS & MCP7A GPIO PAGE 7: SIO GPIO PAGE 8: SOCKET 775 PART 1 PAGE 9: SOCKET 775 PART 2 PAGE 10: SOCKET 775 PART 3 PAGE 11: XDP CONN & GTLREF1 VREQ PAGE 12: MCP7A CPU PAGE 13: MCP7A MEM CH0 PAGE 14: MCP7A MEM CH1 PAGE 15: MCP7A DISPLAY PAGE 16: MCP7A PCIE PAGE 17: MCP7A PCI/LPC PAGE 18: MCP7A SATA/USB PAGE 19: MCP7A HDA/MII/MISC PAGE 20: MCP7A CORE/VTT POWER PAGE 21: MCP7A MEM POWER PAGE 22: MCP7A GND & JTAG HDR PAGE 23: DDR2 DIMM 1 PAGE 24: DDR2 DIMM 3 PAGE 25: DDR2 DIMM 0 PAGE 26: DDR2 DIMM 2 PAGE 27: DDR TERMINATION PAGE 28: SLOT 7 : PCI-E X1 PAGE 29: SOLT 6 : PCI-E X16 PAGE 30: SOLT 5 : PCI-E X16 PAGE 31: SLOTS 4 : PCI 1 & TERM PAGE 32: IEEE1394 PAGE 33: USB CONNECTORS PAGE 34: GBIT LAN PAGE 35: LPC HEADER & ROM SOCKET, PS2 PAGE 36: RGB & HDMI PORT PAGE 37: AUDIO CODEC PAGE 38: AUDIO CODEC JACKS PAGE 39: SIO PAGE 40: SERIAL PORT & BOARD SETTING PAGE 41: PARALLEL PORT PAGE 42: FAN CONTROLS/HEADERS PAGE 43: MTG/BAT/SPK PAGE 44: PWR CONN & FRONT PANEL PAGE 45: DUAL RAIL VREGS / STANDBY PWRGD PAGE 46: 4 PHASE CPU VREG PAGE 47: MEM VDDQ AND VTT VREGS PAGE 48: MCP7A CORE VREG PAGE 49: CPUVTT LINEAR VREG PAGE 50: EMI RESERVED PAGE 51: REV HISTORY PAGE 52: REV HISTORY PAGE 53: BASENET REPORT PAGE 54: BASENET REPORT PAGE 55: BASENET REPORT PAGE 56: CREF PART REPORT PAGE 57: CREF PART REPORT PAGE 58: CREF PART REPORT PAGE 59: CREF PART REPORT PAGE 60: CREF PART REPORT
MCP7A CRB 602-7R177-0000-F00 SCH REV 6.0 03/18/2008 FAB REV F BOM REV A
MCP7A CRB
Wed Mar 19 12:35:01 2008
602-7R177-0000-F00
COVER PAGE
PAGE 1 OF 60
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BLOCK DIAGRAM
POWER
SUPPLY
CONNECTOR
VREG
P4 SOCKET 775
FSB 800/1066/1333MHZ
128-BIT 533/667/800MHZ
DDRII SDRAM CONN 0
DDRII SDRAM CONN 1
DDRII SDRAM CONN 2
DDRII SDRAM CONN 3
PEX X8 SLOT
PEX X8 SLOT
PEX X1 SLOT
SPI 8MB FLASH
INTEGRATED SATA CONTROLLERS (X3)
X6 - SATA CONN
SERIAL CONN
PCI EXPRESS
PCI EXPRESS
PCI EXPRESS
NFORCE MCP7A
1427 BGA
HDA
RGB
HDMI
X12 USB2
PCI 33MHZ
7.1 AUDIO
ALC888S
RGB
HDMI
BACK PANEL CONN
USB2 PORTS 4-5 /GBIT LAN
USB2 PORTS 0-3
FRONT PANEL HDR
USB2 PORTS 6-7
USB2 PORTS 8-9
PCI SLOT 1
1394
SPDIF CONN
RCA CONN
LPC BUS 33MHZ
PS2 CONN
CO-LAYOUT
SIO
W83627DHG
LPT HEADER
LPC HEADER
Tue Oct 23 11:08:00 2007
MII/RGMII
MII/RGMII
88E1116R
USB2 PORTS 10-11
BLOCK DIAGRAM
602-7R177-0000-F00 6.0 2
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RESET MAP
P4 SKT
RESET*
PWRGOOD
MCP7A
PCI-E X1
PWR CONN
MCP_PWRGD CPU_RESET*
PS ON
PWR GOOD
TO DUAL VREG
TO MEM_VDDQ
REGULATOR PWRGD REGULATOR PWRGD
V_CPU
TO CPU_VTT
REGULATOR EN
SLP_S3*
PS_PWRGD
SLP_S3* PS_PWRGD
SLP_S5* CPU_VLD
CPU_ENABLE
PE_RESET*
PCI_RESET*
PCI_RESET*
MCP7A_CPU_PWRGD CPU_RST*
PE_RESET*
(3.3V)
PCI_RST_SLOTS_1*
PCI_RST_1394*
(3.3V)
(3.3V)
PCI-E X8
PCI-E X8
PCI SLOT 1
1394
PWRGD_SB
RGMII_RESET*
LAN PHY
RESET*
PWRGD_SB
MIIRESET*
LPC_RST*
HDA_RESET*
WAKE EVENTS
PCI-E (PE_WAKE*) PCI (PME*) LAN (RGMII) KB/MOUSE (SIO_PME*) USB (INT.) POWER BUTTON (INT.)
HDA_RST*
(3.3V)
AUDIO CODEC
LPC_RST_SIO*
LPC_RST_FLASH*
(3.3V)
SIO
HEADER
RESET MAP
3602-7R177-0000-F00 6.0Fri Oct 19 10:42:01 2007
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PCIE X8
P4
PCIE X8
PCIE X1
DIMM 0
DIMM 2
200/266/333 MHZ
MAIN CLOCKS TO CPU
XDP
CPU_CLK_IN* CPU_CLK_IN
BCLK_OUT_CPU_P BCLK_OUT_CPU_N
BCLK_OUT_MCP_P BCLK_OUT_MCP_N
BCLK_IN_MCP_N BCLK_IN_MCP_P
BCLK_OUT_ITP_P BCLK_OUT_ITP_N
MCP7A
PCIE X8 REF_CLK PCIE X8 REF_CLK* PCIE X8 REF_CLK PCIE X8 REF_CLK* PCIE X1 REF_CLK PCIE X1 REF_CLK*
MEMORY_0A_CLOCK[2:0] MEMORY_0A_CLOCK[2:0]*
MEMORY_0B_CLOCK[2:0] MEMORY_0B_CLOCK[2:0]*
MEMORY_1A_CLOCK[2:0] MEMORY_1A_CLOCK[2:0]*
MEMORY_1B_CLOCK[2:0] MEMORY_1B_CLOCK[2:0]*
DIMM 1
DIMM 3
100MHZ
3 3
3 3
3 3
3 3
MEMORY CLOCKS TO DIMMS
266/333/400MHZ
100MHZ
PCI SLOT 1
SIO
BUF_SIO_CLK
LPC_CLK0 PCI_CLK0 PCI_CLK1 PCI_CLK2
PCI_CLK_FB
XTAL_IN
25.0 MHZ XTAL_OUT
RTC XTAL_IN
32.768 KHZ RTC XTAL_OUT
MII_RXCLK MII_TXCLK
25 MHZ
AC_BITCLK
LAN INTERFACE
HDA LINK
ALL 33MHZ
25MHZ, 125MHZ
LAN
AUDIO
Fri Oct 19 10:46:42 2007
HEADER
1394
CLOCK DISTRIBUTION
602-7R177-0000-F00 6.0 4
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VREGS
+12V
SMBUS ADDRESS MAP
DEVICE DIMM0 CHANNEL 1A
DIMM1 CHANNEL 1B DIMM2 CHANNEL 0A DIMM3 CHANNEL 0B
SMBUS #
0 0 0 0
ADDRESS 1010 000
1010 001 1010 010 1010 011
+5V 5VSB
SLP_S3* DELAYED
5VSB
XSTR
DUAL FET
5VDUAL
ENABLE HIGH = +5V ENABLE LOW = 5VSB
3.3VSB
+3.3V
CPUVDD_EN
FROM MCP73
CPU_VTT
VREG
+1.2V_VTT
AC IN
SLP_S3* PS_ON*
P/S
+5V +3.3V 5VSB PWRGD_PS
SIO HDCP THERM SENSE GTLREF1 VREQ
PCIE X1 PHYS PCIE X16 PHYS PCIE X16 PHYS
PCI SLOT 1
1 1 1 1
1 1
1
0101 101 = 0X2D 0101 000 = 0X50 1001 100 = 0X4C 0X92
ARP ARP ARP1
ARP
CTRL FROM
PG PS
3.3VSB +3.3V
PWRGD_PS DELAYED
3VDUAL
+5V
FET
VCOREAUX
VREG
CPU_VCC
VREG
3VDUAL
1.1V_DUAL
CPU_VCC_PLL
CPU_VCC VOLTAGE FOR PLL
+3.3V
+5VDUAL
SLP_S5*
1.8V_SUS 3VDUAL
DIMM_VREF
+12V
MCP7A CORE VREG
MEM VDDQ
VREG
ENABLE = HIGH
VREG
CPU
VREG
+1.1V_CORE
+1.8V_SUS
+MEM_VTT
VTT VOLTAGE FOR TERMINATION
CPU_PWRGD TO MCP7A
+V_CPU
3VDUAL
+12V
LAN
1.8V VREG
AUDIO
5V
VREG
LAN
+1.8V
+5V_AUD
CPU_VTT_PWRGD
VIDS
SOT23
PCI INTERRUPT/IDSEL MAP
SLOT
4
1394
BUS #
01 01 0X07
DEV # IDSEL 0X06
22 23
SLT INTA* PCI_INTY* PCI_INTZ*
SLT INTB* PCI_INTZ* PCI_INTW*
SLT INTC* SLT INTD*
REQ/GNT
PCI_INTX* 0
1
3
1 2
Wed Nov 14 14:15:29 2007
SOT23-5/SC70
SOT89-5
5 4
321 1 32 21 3
SOT23-6
6
SOFTWARE MAPPING
45
SOT223
4
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MCP7A MULTIFUNCTION PINS PEB_CLKREQ#/GPIO_49
PEC_CLKREQ#/GPIO_50 TV_DAC_VSYNC/GPIO_45 TV_DAC_HSYNC/GPIO_44
PCI_PERR#/GPIO_43/RS232_DCD# PCI_REQ1#/FANRPM2 PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN# PCI_GNT1#/FANCNTL2 PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS# PCI_GNT4#/GPIO_53/RS232_SOUT# PCI_PME#/GPIO_30 LPC_DRQ1#/GPIO_19
HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA MII0_RXER/GPIO_36 MII0_COL/GPIO20/MSMB_DATA MII0_CRS/GPIO21/MSMB_CLK MII0_INTR/GPIO_35 MII0_PWRDWN/GPIO_37 USB_OC0#/GPIO_25 USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO
SMB_DATA1/MSMB_DATA SMB_CLK1/MSMB_CLK EXT_SMI#/GPIO_32 SUS_CLK/GPIO_34 SPI_DI/GPIO_8 SPI_DO/GPIO_9 SPI_CS0/GPIO_10 SPI_CLK/GPIO_11 FANCTL0/GPIO_61 FANRPM0/GPIO_60 FANCTL1/GPIO_62 FANRPM1/GPIO_63
GPIO_6/FERR#/IGPU_GPIO_6 GPIO_7/NFERR#/IGPU_GPIO_7
CRB Function PEB_CLKREQ*
PEC_CLKREQ* TV_DAC_VSYNC TV_DAC_VSYNC
MCP_COM_DCD1* PCI_REQ1* MCP_COM_DSR1* MCP_COM_CTS1* MCP_COM_RXD1* PCI_GNT1* MCP_COM_DTR1* MCP_COM_RTS1* MCP_COM_TXD1* PCI_PME* FP_AUDIO_PRESENCE*
HDA_SDATA_IN1/ MCP_KB_CLK
--- / MCP_KB_DATA MCP_MS_CK MCP_MS_DA NC NC NC RGMII0_INTR* RGMII0_PWRDWN* USB_OC10* USB_OC32* USB_OC54* USB_OC76*
SMB_SDA SMA_SCL EXT_SMI* CPU_GTLREF1_SEL SPI_DI SPI_DO SPI_CS* SPI_CLK CPUFAN_CNTL CPUFAN_TACH SYSFAN_CNTL SYSFAN_TACH
HDMI_CEC
---
I/O INIT REQ'D Comments I/O
I/O O O
I I O O I O I I O O O
I/O I/O I/O I/O I I O O O I I I I
I O I O
DEFAULT OUTPUT LOW I O O O O I O I
O I/O
IF USING AZALIADIGITAL HEADER FUNCTION, IT CAN NOT USE THE KEYBOARD FUNCTION.
CONNECT TO GND CONNECT TO GND CONNECT TO GND
NO USED
HPLUG_DET2/GPIO_22 DDC_CLK2/GPIO_23 DDC_DATA2/GPIO_24
HPLUG_DET2 DDC_CLK2 DDC_DATA2
I/O I/O I/O
JUMPER TABLE
JUMPER J1G3 J2H1
PAGE 19 40
DEFAULT
2-3 1-2
FUNCTION RESET CMOS NOT RTC BIOS ENABLE OR NOT TO DEBUG MODE
JUMPERS & MCP7A GPIO
Fri Oct 26 11:51:50 2007
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PIN NAME VID0
VID1 VID2 VID3 VID4 VID5 VID6 VID7
GP20/CPUFANOUT1/MSO GP21/CPUFANIN1/MSI GP22/SCE* GP23/SCK MCLK/GP25 MDATA/GP24 KDATA/GP26 KCLK/GP27
GP30 GP31 GP32/RSTOUT2*/SCL GP33/RSTOUT3*/SDA GP34 GP35 GP36 GP37 GP40/RIB* GP41/DCDB* GP42/SOUTB/IRTX/FAN_SET2
GP43/SINB*/IRRX GP44/DTRB* GP45/RTSB* GP46/DSRB* GP47/CTSB*
GP50/WDTO*/EN_VRM10 RSMRST*/GP51 SUSB*/GP52 PSON*/GP53 PWROK/GP54 GP55/SUSLED PSIN/GP56 PSOUT*/GP57
RIA*/GP60 DCDA*/GP61 COM_DCDA* I SOUTA/GP62/PENKBC SINA*/GP63 DTRA*/GP64/PNPCSV* RSTA*/GP65/HEFRAS DSRA*/GP66 CTSA*/GP67
HM_SMI*/OVT* BEEP/SO
CPUVCORE VIN0 VIN1 VIN2 VIN3
CPUFANOUT0 SYSFANOUT AUXFANOUT0
FUNCTION
--
--
--
--
--
--
--
--
--
--
--
-­MCLK MDATA KDATA KCLK
MEN_OV1 SIO_HDCP_WP SMB_CLK SMB_DATA YLW_STBLED MCP7A_CORE_OV2 MCP7A_CORE_OV1 MCP7A_CORE_OV0 MCP7A_CORE_AUX_OV2 MCP7A_CORE_AUX_OV1 FAN_SET2
MCP7A_CORE_AUX_OV0 MEM_OV0 CPU_VTT_OV2 CPU_VTT_OV1 CPU_VTT_OV0
SIO_WDTO* SIO_RSMRST* SLP_S3* PS_ON_R* GRN_PWRLED
-­PSIN* SIO_PSOUT*
COM_RIA* COM_TXD1
COM_SINA* COM_DTR1* COM_RTS1* COM_DSRA* COM_CTSA*
EXT_SMI*
-­+V_CPU
+1.8V_SUS +1.1V_CORE +5V +12V
SIO_CPUFAN_CNTL SIO_SYSFAN_CNTL SIO_AUXFAN_CNTL
I/O
I/O I/O I/O I/O I/O I/O I/O I/O
I I I I O I/O I/O O
I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O
O O I I O I/O I O
I O
I O O I I
O O
I I I I I
O O O
INIT REQ'D
YES YES YES YES
YES YES
Comments
BOARD ID0 BOARD ID1 BOARD ID2 TELL BIOS TO ENABLE DEBUG MODE
KB/MS DEFAULT USE SIO
INITIALIZE AS SMB_CLK INSTEAD OF RSTOUT INITIALIZE AS SMB_DATA INSTEAD OF RSTOUT
BIOS NEEDED OUTPUT HIGH PULL HIGH ON BOARD
BIOS NEEDED OUTPUT HIGH
COM_PORT DEFALT USE MCP7A
1.8V RAIL MEASURED USING EXTERNAL 4:5 DIVIDER
FAN DEFALT USE MCP7A FAN USE SIO
CPUFANIN0 SYSFANIN AUXFANIN0 SI/AUXFANIN1
CPUTIN SYSTIN AUXTIN
PECI
SIO_CPU_FAN_TACH SIO_SYSFAN_TACH SIO_AUXFAN_TACH
-­CPU THERM DIODE0
CPU THERM DIODE1 DISCRETE DIODE
CPU_PECI_SPIO
I I I I
I I I
I
Thu Dec 13 17:17:28 2007 7602-7R177-0000-F00 6.0
FAN DEFALT USE MCP7A FAN USE SIO
CPU_PECI DEFALT USE MCP7A
SIO GPIO
Page 8
BIBIBIBIBIBIINBIBIBIBIBIBIBIBIBIBIBIINBIINBIINBIBIBIBI
OUT
OUT
1 OF 5
A5*
A4*
A3*
A6* A7* A8* A9*
A11*
A10* A12*
A13* A14* A15* A16* A17* A18* A19* A20* A21* A22* A23* A24* A25* A26*
AP1*
AP0*
A35*
DBI0*
DSTBP0* DSTBN0*
ADSTB0* ADSTB1*
A27* A28* A29* A30* A31* A32* A33* A34*
DEFER*
DBSY*
BPRI*
BR0*
ADS*
DBI3*
DSTBN3*
DSTBP3*
DBI2*
DSTBP2* DSTBN2*
DBI1*
DSTBP1* DSTBN1*
BNR*
HITM*
HIT*
BINIT*
LOCK*
MCERR*
DRDY* TRDY*
RESET*
IERR*
D2*
D0* D1*
D3*
D7*
D6*
D10*
D8* D9*
D11*
D4*
D12*
D5*
D13*
D21*
D20*
D19*
D16*
D14*
D17* D18*
D15*
D22* D23*
D26* D27* D28* D29* D30* D31*
D25*
D24*
D33*
D32* D34*
D35* D36*
D39* D40* D41* D42*
D38*
D37*
D43* D44* D45* D46* D47* D48* D49* D50*
D53*
D52*
D51*
D54*
D63*
D55* D56* D57* D58*
D62*
D61*
D60*
D59*
REQ4*
REQ3*
REQ2*
REQ1*
REQ0*
DP2*
DP0* DP1*
DP3*
RS1*
RS0* RS2*
RSP*
BIBIIN
3 OF 5
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND GND GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND GND GND GND
GND GND GND
GND
GND
GND GND
GND GND
GND
GND
GND
GND GND
GND
GND GND GND GND
GND
GND GND GND
GND GND
GND
GND GND
GND
GND
GND
GND GND
GND
GND
GND GND
GND
GND GND GND
GND
GND
GND
GND
GND GND
GND GND
GND
GND GND
C
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PD_CPU_A24
A12 A15 A18 A2 A21 A24 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB7 AC3 AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 AG20 AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AH7 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28
U8E1 LGA_R
I230
SKT_775P
CPU_THERMDC1R
AJ29 AJ30
AK10 AK13 AK16 AK17
AK20 AK23 AK24 AK27 AK28 AK29 AK30
AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28
AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28
AN10 AN13 AN16 AN17
AN20 AN23 AN24 AN27 AN28
CPU_THERMDA1R
AJ4 AJ7
AK2
AK5 AK7
AL3 AL7 AM1
AM4 F22 AN1
AN2
F4
B1 B11 B14 B17 B20 B24
B5
B8 C10 C13 C16 C19 C22 C24
C4
C7 D12 D15 D18 D21 D24
D3
D5
D6
D9 E11 E14 E17
E2 E20 E25 E26 E27 E28
PD_CPU_E29
E29
E8 F10 F13 F16 F19
CPU_AL3_PD
12F4<>
12D6<>
12C7<
R12E6
1
0402_R
5%
0
CPU_THERMDC1
2
CPU_THERMDA1
2
1
5%
0402_R
0
R12E5
CPU_D<63..0>*
CPU_REQ<4..0>*
CPU_RS<2..0>*
TP_CPU_DP0* TP_CPU_DP1* TP_CPU_DP2* TP_CPU_DP3*
TP_775_RSP
39A8< 39A8<
0
B4
1
C5
2
A4
3
C6
4
A5
5
B6
6
B7
7
A7
8
A10
9
A11
10
B10
11
C11
12
D8
13
B12
14
C12
15
D11
16
G9
17
F8
18
F9
19
E9
20
D7
21
E10
22
D10
23
F11
24
F12
25
D13
26
E13
27
G13
28
F14
29
G14
30
F15
31
G15
32
G16
33
E15
34
E16
35
G18
36
G17
37
F17
38
F18
39
E18
40
E19
41
F20
42
E21
43
F21
44
G21
45
E22
46
D22
47
G22
48
D20
49
D17
50
A14
51
C15
52
C14
53
B15
54
C18
55
B16
56
A17
57
B18
58
C21
59
B21
60
B19
61
A19
62
A22
63
B22 J16
H15 H16 J17
0
K4
1
J5
2
M6
3
K6
4
J6
0
B3
1
F5
2
A3 H4
U8E1 LGA_R
SKT_775P
I229
Wed Jan 16 11:22:23 2008
3
L5
4
P6
5
M5
6
L4
7
M4
8
R4
9
T5
10
U6
11
T4
12
U5
13
U4
14
V5
15
V4
16
W5
17
AB6
18
W6
19
Y6
20
Y4
21
AA4
22
AD6
23
AA5
24
AB5
25
AC5
26
AB4
27
AF5
28
AF4
29
AG6
30
AG4
31
AG5
32
AH4
33
AH5
34
AJ5
35
AJ6
TP_775_AP0
U2
TP_775_AP1
U3 R6
AD5
CPU_DSTBP0*
B9
CPU_DSTBN0*
C8
CPU_DBI0*
A8
CPU_DSTBP1*
E12
CPU_DSTBN1*
G12
CPU_DBI1*
G11
CPU_DSTBP2*
G19
CPU_DSTBN2*
G20
CPU_DBI2*
D19
CPU_DSTBP3*
C17
CPU_DSTBN3*
A16
CPU_DBI3*
C20
D2 G8 F3
B2 G7
C1 E3 C2
D4 E4
C3
TP_775_BINIT
AD3 AB2
AB3
G23
CPU_A<35..3>*
CPU_ADSTB0* CPU_ADSTB1*
CPU_ADS* CPU_BPRI* CPU_BR0*
CPU_DBSY* CPU_DEFER*
CPU_DRDY* CPU_TRDY* CPU_BNR*
CPU_HIT* CPU_HITM*
CPU_LOCK*
CPU_IERR*
TP_CPU_MCERR*
CPU_RST*
12D6<>
12D6<> 12D6<>
12F6<> 12F6<> 12F6<>
12F6<> 12E6<> 12E6<>
12E6<> 12E6<> 12E6<>
12E6<> 12E6<> 12E6<>
12C6< 12C6<
12C6< 12C6<
12C6< 12C6< 12C6<
12C6< 12C6<
12C6<
VTT_OUT_RIGHT
VTT_OUT_LEFT
2
R13F6 62
5% 0402_R
1
+1.2V_VTT
2
R12F17 62
5% 0402_R
1
12C6<
2
R13D4 200
5% 0402_R
1
11C6< 12C4>
SOCKET 775 PART 1
6.0 8602-7R177-0000-F00
Page 9
INININININ
OUT
OUT
OUT
OUT
OUTININ
OUT
OUTININ
2 OF 5
VCCP
VCCP VCCP
VCCP
VCCP VCCP VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP VCCP
VCCP
VCCP
VCCP VCCP VCCP VCCP
VCCP VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP VCCP VCCP
VCCP
VCCP VCCP VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP VCCP VCCP VCCP
VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP VCCP VCCP VCCP
VCCP VCCP
VCCP
VCCP
VCCP
VCCP VCCP VCCP
VCCP VCCP VCCP
VCCP
VCCP VCCP VCCP
VCCP
BCLK0
STPCLK*
A20M* FERR*/PBE*
SMI*
IGNNE*
INTR
BCLK1
NMI INIT*
THERMDC THERMTRIP*
THERMDA
FC5
FC2
FC1
FC7
PROCHOT* PWRGOOD
BPM0*
BSEL2
BSEL1
BSEL0
VTT_PWRGD
BPM1*
BPM5*
BPM2* BPM3* BPM4*
TDI TMS
TDO TCK
TRST* DBR*
ITP_CLK1
ITP_CLK0
COMP0
GTLREF
COMP1
VID5
VID3 VID4
VID1 VID2
VID0
LL_ID1
LL_ID0
MSID1 MSID0
SKTOCC* TESTHI0
VSSA
VCCIOPLL
VCCA
BOOTSELECT
TESTHI1
TESTHI10
TESTHI8
TESTHI6
TESTHI4
TESTHI2 TESTHI3
TESTHI5 TESTHI7 TESTHI9 TESTHI11
TESTHI12 TESTHI13
OUTINININOUTINININOUTINININININOUTINOUTININININININ
OUT
OUT
OUTINOUT
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
12C4>
39C2<
VTT_OUT_RIGHT
2
R14F2
63.4
1% 0402_R
1
CPU_GTLREFR3
2
R14F3 107
1% 0402_R
1
VTT_OUT_RIGHT
2
1
2
1
EMPTY
2
R13F25 51
5% 0402_R
1
2
R13F24 51
5% 0402_R
1
VTT_OUT_RIGHT
1C13E5
1
1UF
0402_R X5R
6.3V
2 10%
10%
2
C14F2
1
1UF
0603_R X5R 16V 10%
2
VTT_OUT_RIGHT
R13F13
63.4
1% 0402_R
CPU_GTLREFR0
R13F14 107
1% 0402_R
VTT_OUT_RIGHT
EMPTY
2
R12F2 51
5% 0402_R
1
CPU_MSID1
CPU_MSID0
2
R12F1 51
5% 0402_R
1
C13F8 1UF
0402_R X5R
6.3V
2
10D2<
R13F12
1
C14F1 1UF
0402_R X5R
6.3V
10%2
0402_R
0402_R
C14F4
1
.1UF
0402_R X7R 16V
2 10%
R12F13 51
5% 0402_R
10
1
1
2
1%
R13F8
R13F10
11A4>
9A4<
9A4<
CPU_PECI_MCP
CPU_PECI_SPIO
11A4>
R14F4
VTT_OUT_LEFT
2
1
1%
0402_R
10
2
R12F12 51
5% 0402_R
1
11D5<
0402_R
C13F3
1
1UF
0603_R X5R 16V
10%2
PLL ANALOG FILTER
PLACE NEAR CPU SOCKET
1C13F7
1
1UF
0402_R X5R
6.3V
10%2
CPU_PECI_O
2
5%
20
2
5%
20
EMPTY
12C6< 12C6< 12C6< 12C6< 12C6> 12C6< 12C6< 12C6<
CPU_GTLREF3
C14F3
1
220PF
0402_R C0G 50V 5%
2
2
11
R12F14 51
5% 0402_R
46A5>
12B6> 49D1>
2
1
12B4> 12C4>
11C6< 46E7<
R13F27 51
5% 0402_R
2
1
R12F15 51
5% 0402_R
CPU_BPM<5..0>*
CPU_GTLREF0
C13F2
1C13F1
1
PLL 22UF CAP MUST BE:
ESR <= 0.35 OHMS
TRACE FROM 33UF CAP MUST BE WITHIN 750 MILS OF PIN PLACE INDUCTOR CLOSE TO CAP
.1UF
0402_R X7R 16V
2
10%2
ESL <= 1.4NH
10D4> 10D4>
10A6<
220PF
0402_R C0G 50V 5%
VTT_OUT_RIGHT
2
9C4<
1
9C4<
2/27/2008
CPU_THERMTRIP* CPU_PROCHOT*
MCP7A_CPU_PWRGD CPU_VTT_PWRGD
PLACE CLOSE TO CPU PINS
1
L6D1 10UH
2
C6D5 22UF
2/17
RDL_R ALUM 25V 20%
2
R12F3 51
5% 0402_R
1 1
2
1
2
R12F16 51
5% 0402_R
1
+1.2V_VTT
100MA
0805_R
SMD
R13F19 51
5% 0402_R
0 1 2 3 4 5
1
2
CPU TERMINATION
2
1
EMPTY R13F18 150
1% 0402_R
VTT_OUT_LEFT
2
1
2
1
R13F20 150
1% 0402_R
EMPTY
R13F22 200
1% 0402_R
2
1
R13F21 62
5% 0402_R
R8F2 62
5% 0402_R
EMPTY
ITP TERMINATION
12
0805_R X5R
6.3V 20%
2
1
XDP_TCK XDP_TRST*
R12F18 680
5% 0402_R
EMPTY
2
11
2
R14E1
49.9
1% 0402_R
12 MIL TRACE
R13F2 51
5% 0402_R
100MA
0805_R
SMD
11D1> 11D1>
1
L7D1 10UH
2
2
R8F1 51
5%
C6D8
10UF
2
R13F9 51
5% 0402_R0402_R
2
2
1
R13F4 51
5% 0402_R
EMPTY R10F1 130
1% 0402_R
44A6<
2
R12E8 51
5% 0402_R
1
12C3> 12C3> 12C2>
11D1> 11D1> 11D1>
11C6> 12D1> 12D1>
2
R8F3
2
49.9
1% 0402_R
1
1
BSEL0 BSEL1 BSEL2
XDP_TDI XDP_TDO XDP_TMS
XDP_FNTPNL_RST*
INTERPOSER_BCLK INTERPOSER_BCLK*
R13F7
49.9
1% 0402_R
39B8< 39A8<
12D1> 12D1>
9D6> 9D7>
9 MIL TRACE
2
R8F4
49.9
1% 0402_R
11
46E7<
VTT_OUT_LEFT
2
R12F4 51
5% 0402_R
11
9C1< 10C4>
VCCA VCCIOPLL VSSA
+1.2V_VTT
2
R13D3 51
5% 0402_R
2
11
CPU_VID<7..0>
9A7> 9A7>
R13D2 51
5% 0402_R
TESTHI_0 TESTHI_1 TESTHI_2-7 TESTHI_8 TESTHI_9 TESTHI_10 TESTHI_11 TESTHI_12
CPU_SLP*
Wed Feb 27 13:33:41 2008
CPU_CLK CPU_CLK*
CPU_A20M* CPU_FERR* CPU_IGNNE* CPU_SMI* CPU_STPCLK* CPU_INTR CPU_NMI CPU_INIT*
CPU_COMP2 CPU_COMP3
CPU_GTLREF3
CPU_PECI_O
CPU_THERMDA CPU_THERMDC
VTT_OUT_RIGHT
2
R12F21 150
1% 0402_R
1
CPU_COMP0 CPU_COMP1
LOAD_LN_ID0 LOAD_LN_ID1
CPU_MSID1
CPU_MSID0
TP_775_BOOTSEL TP_775_SKTOCC
U8E1 LGA_R
+V_CPU
SKT_775P
F28 G28
K3 R3 N2 P2 M3 K1 L1 P3
G2 R1 F2 G5
AL1 AK1 M2 AL2
N1 AM6
G29 H30 G30
0
AJ2
1
AJ1
2
AD2
3
AG2
4
AF2
5
AG3 AD1
AF1 AC1 AE1 AG1 AC2 AK3 AJ3
H1 A13
T1 V2
AA2
0
AM2
1
AL5
2
AM3
3
AL6
4
AK4
5
AL4 A23
C23 B23 V1 W1
Y1 AE8
F26 W3 F25 G25 G27 G26 G24 F24 G3 G4 H5 P1 W2 L2
I126
AA8
AB8 AC23 AC24 AC25 AC26 AC27 AC28 AC29 AC30
AC8 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30
AD8 AE11 AE12 AE14 AE15 AE18 AE19 AE21 AE22 AE23
AE9 AF11 AF12 AF14 AF15 AF18 AF19 AF21 AF22
AF8
AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30
AG8
AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30
AH8
AH9 AJ11 AJ12 AJ14 AJ15 AJ18 AJ19 AJ21 AJ22 AJ25 AJ26
AJ8
AJ9 AK11
CPU_VID<7..0>
VTT_OUT_RIGHT
5
RP9F1 RP9F1
680
0
1
VTT_OUT_RIGHT
7
RP9F1
680
2
2
3
VTT_OUT_RIGHT
7
RP9G1
680
2
4
5
VTT_OUT_RIGHT
5
RP9G1
680
4
6
7
SOCKET 775 PART 2
602-7R177-0000-F00
6
680
34
8
RP9F1 680
1
8
RP9G1 680
1
6
RP9G1 680
3
9B5>
6.0 9
46E7< 10C4>
Page 10
INININ
D
S
G
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININININININININ
OUT
IN
4 OF 5
VTT VTT
VTT
VTT VTT VTT VTT
VTT VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
FC3
VTT_SEL
VTT VTT
FC4 FC6
FC16
FC12
FC11
RSVD
RSVD RSVD
RSVD
RSVD RSVD
RSVD
RSVD
RSVD RSVD
RSVD
RSVD
RSVD
RSVD RSVD RSVD RSVD
RSVD
RSVD
RSVD
RSVD RSVD RSVD RSVD
RSVD
RSVD
RSVD
RSVD
GND
GND
GND
GND
GND
GND GND
GTLREF_SEL
VTT_OUT_LEFT
VTT_OUT_RIGHT
VSS_MB_REG
VCC_MB_REG
VCCSENSE VSSSENSE
GND GND GND GND GND GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND GND
GND GND
GND GND GND
GND
GND GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND GND
GND
GND GND
GND
GND
GND GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND GND GND
GND
IN
5 OF 5
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP VCCP
VCCP VCCP VCCP VCCP
VCCP
VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP
VCCP VCCP
VCCP
VCCP
VCCP VCCP
VCCP VCCP VCCP VCCP VCCP
VCCP
VCCP
VCCP
VCCP VCCP
VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP
VCCP
VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP VCCP
VCCP VCCP VCCP
VCCP
VCCP
VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP VCCP
VCCP
VCCP VCCP VCCP
VCCP
VCCP VCCP
VCCP
VCCP VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP VCCP VCCP VCCP
VCCP
VCCP VCCP
VCCP VCCP
VCCP
VCCP VCCP
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
10D4>
J30
K23 K24 K25 K26 K27 K28 K29 K30
M23 M24 M25 M26 M27 M28 M29 M30
N23 N24 N25 N26 N27 N28 N29 N30
T23 T24 T25 T26 T27 T28 T29 T30
U23 U24 U25 U26 U27 U28 U29 U30
W23 W24 W25 W26 W27 W28 W29 W30
Y23 Y24 Y25 Y26 Y27 Y28 Y29 Y30
AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL8 AL9 AM11 AM12 AM14 AM15 AM18 AM19 AM21 AM22 AM25 AM26 AM29 AM30 AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 AN25 AN26 AN29 AN30 AN8 AN9 J10 J11 J12 J13 J14 J15 J18 J19 J20 J21 J22 J23 J24 J25 J26 J27 J28 J29
U8E1 LGA_R
I128
SKT_775P
+V_CPU
J8 J9
K8 L8
M8
N8 P8 R8
T8
U8 V8
W8
Y8
CPU_G1
+V_CPU
VTT_OUT_LEFT
2
R14F5
49.9
1% 0402_R
1
2
R14F6 0
5% 0402_R
1
EMPTY
1
Y7 Y2 F7 G1 H10 H11 H12 H13 H14 H17 H18 H19 H20 H21 H22 H23 H24 H25 H26 H27 H28 Y5 H3 H6 H7 H8 H9 J4 J7 K2 K5 K7 L23 L24 L25 L26 L27 L28 L29 L3 L30 L6 L7 M1 M7 N3 N6 N7 P23 P24 P25 P26 P27 P28 P29 P30 P4 P7 R2 R23 R24 R25 R26 R27 R28 R29 R30 R5 R7 T3 T6 T7 U1 U7 V23 V24 V25 V26 V27 V28
R13F26
0
TESTHI_12
2
5%0402_R
U8E1 LGA_R
SKT_775P
I129
9A7>
+1.2V_VTT
A25 A26 A27 A28 A29 A30 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 VTT_OUT_LEFT
J1
AA1
CPU_VTT_SEL
F27
TP_GTLREF_SEL
H29
CPU_COMP4
J2
CPU_COMP5
T2 H2
AM5 AM7 AN7
AN5
AN6
AN3
AN4
A20
AC4
AE3
AE4
AE6
AH2
D14
D16
E23
E24
F23
F29
G10
B13
D23
AK6
V29
V30
6 7
VCC_MB_REG VSS_MB_REG
VCC_SENSE VSS_SENSE
TP_CPU_AC4 CPU_COMP7 TP_CPU_AE4
C9
TP_CPU_D1
D1
TP_CPU_D14
TP_CPU_E23
CPU_E5_PD
E5
TP_CPU_E6
E6
TP_CPU_E7
E7
TP_CPU_F23 TP_CPU_F29
SEL_50_60_OHM
F6
CPU_GTLREF2
CPU_COMP8 CPU_J3_PD
J3
TP_CPU_N4
N4 N5
TP_CPU_P5
P5
CPU_COMP6
Y3
CPU_RSVD_G6
G6
V3 V6
V7 W4 W7
9B5>
10A1> 10A1>
11A4>
2
1EMPTY
CPU_G1 CPU_C9 TESTHI_9 TESTHI_8
49A8<
9C1<
R14F1 51
5% 0402_R
VTT_OUT_RIGHT
CPU_VID<7..0>
R12E2
1
0402_R
R12E1
1
0402_R
R12E3
1
0402_R
R12E4
2
1
5%
0402_R
0
CPU_C9
10A1>
10B4<
10A1> 10A1>
2
5%
2
5%
0
EMPTY
2
5%
0
EMPTY
R13E1
2
1%
49.9
10D7< 10A1>
9A7> 9A7>
+1.2V_VTT
2
1
CPU_GTLREF1
0
1
0402_R
VTT_OUT_RIGHT
2
1
R13D1 150
5% 0402_R
CPU_VIDSEL
CPU_CORE_FB+ CPU_CORE_FB-
DIFF PAIR
10A1>
VTT_OUT_LEFT
R12E7 130
1% 0402_R
CPU_FORCE_PR*
CPU_VCC_PLL
C13D2
1C13D11
2
10UF
0805_R X5R 10V 10%
.01UF
0402_R X7R 16V
10%2
Wed Mar 19 10:49:03 2008
10D4>
46E7<
220PF
0402_R C0G 50V
5%2
1
0402_R
1
2
46D7< 46C7<
CPU_GTLREFR2
1
0402_R
1 C13E11 C13E2
.1UF
0402_R X7R 16V
2 10%
49D5>
EMPTY
R13F3
C13F5 220PF
0402_R C0G 50V 5%
EMPTY
R12F10
0402_R
2
1
5%
0402_R
2
1
2
C13F6 .1UF
0402_R X7R 16V 10%
1
0402_R
0
0402_R
R13F17
10
46D7<
5%
0
P_GTLREF
VTT_OUT_RIGHT
2
R13E4
63.4
1% 0402_R
1
R13E2
2
1%
2
10
46A5>
R13E3 107
1% 0402_R
1
EMPTY
R13F1
2
1
5%
0
R13F5
2
1
5%
0
EMPTY
VTT_OUT_RIGHT
2
R13F15
63.4
1% 0402_R
1
2
1%
2
R13F16 107
1% 0402_R
1
VTT_OUT_RIGHT
1
220PF
0402_R C0G 50V 5%
2
1 C13E3
1UF
0402_R X5R
6.3V 10%
2
CPU_BPM<5..0>*
0 1 2 3
IF USEING CPU_GTLREF1_SEL CONTROL, CHANGE R13F16 107 TO 137 OHM
1 C13F4
1UF
0402_R X5R
6.3V
10%2
EMPTY
EMPTY
2
R12F20 680
5% 0402_R
1
2
R12F19 51
5% 0402_R
EMPTY
1
R7D4
1
0402_R
2
35.7
R13F23
49.9
1% 0402_R
C7D2
1C7D3
0.1UF
0603_R X7R 16V
10%2
VTT_OUT_LEFT
2
R12F11 51
5% 0402_R
1
CPU_GTLREFR1
2
R9G14 383
1% 0402_R
1
Q9G1
3
2N7002
CPU_GTLREF1_SEL
1
S23_R
2
VTT_OUT_LEFT
R8F5
49.9
1% 0402_R
2
1
VTT_OUT_LEFT
2
1111
R14E2
24.9
1% 0402_R
VTT_OUT_RIGHT
2
1%
C7D1
1
1UF
0603_R X5R 16V 10%
2
VTT_OUT_RIGHT
2
R12F5
49.9
1% 0402_R
2
R7D2 100
1% 0402_R
2
R7D3
82.5
1% 0402_R
1
2
SOCKET 775 PART 3
11D5< 9B7<
11A4>
2
R7D1
88.7
1% 0402_R
11
R13F11
49.9
1% 0402_R
CPU_COMP4 CPU_COMP5 CPU_COMP6 CPU_COMP7 CPU_C9 CPU_COMP8
19D3>
10C5< 10C5< 10A5< 10B4< 10B4< 10A5>
10D4>
106.0602-7R177-0000-F00
Page 11
OUT
OUT
OUT
OUT
OUTINBI
TDO TMS
TDI
TRST*
VTT
VTT
TCK
GND GND
GND GND
GND GND
SCL SDA
RSVD
PRSNT*
GND GND GND GND GND GND GND GND
GND
GND
GND
PWRGOOD NC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC
FP_RST*
CLK* CPU_RST*
CLK
BPM0A*
BPM2A*
BPM3A*
BPM4A*
BPM5A*
BPM5B* BPM4B* BPM3B* BPM2B* BPM1B* BPM0B*
BPM1A*
OUT
OUT
OUT
OUTININININ
OUT
IN
OUT1
OUT0 OUT2
FS3
FS1
OUT3
FS0 FS2
SCL
VCC
SDA AD0
AD1
GNDPD GND
IN
BI
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
J13F1
0.5MM HDR2X30_XDP
9B7< 10D2<
12D1> 12D1>
12C4> 8A2<
9B5>
44A6<
9C7<
12B6>
CPU_RST* XDP_FNTPNL_RST* MCP7A_CPU_PWRGD
CPU_BPM<5..0>*
XDP_CLK XDP_CLK*
R9G1
5%0402_R
1K
VTT_OUT_RIGHT
1
0402_R
R9F1
CPU_RST_XDP*
21
2
5%
51
EMPTY
5
3
4
5
3
9
2
11
1
15
0
17 21
23 27 29 33 35
40 42
46 48
39 4
6 10 12 16 18 22 24 28 30 34 36 41 45 47
+1.2V_VTT
43 44
54 56 52 58 57
53 51
TP_XDP_RSVD
55
TP_XDP_PRSNT
60
1 2 7
8 13 14 19 20 25 26 31 32 37 38 49 50 59
R12G3
1
5%
0402_R
39
SMB_SCL SMB_SDA
R12G2
2
1
1%
0402_R
2
49.9
11A7<
15B4< 31A7<
XDP_TRST* XDP_TDI XDP_TDO XDP_TMS XDP_TCK
2
46C7< 39D6<
11A7<> 19C8> 29D7<> 31A7<> 46C7<
15A4<>
28C6<>
30D7<> 39D6<>
30D7<
29D7<
28C6< 19C8>
R9F2 27
5% 0402_R
1
9B6< 9C5< 9B5> 9B5< 9B6<
SMT_R
I20
+3.3V
C8G1
1
2
0402_R X7R
.1UF
16V 10%
28C6< 29D7< 30D7< 31A7< 39D6<
11C3<> 15A4<> 19C8> 28C6<> 29D7<>
31A7<> 39D6<> 46C7<
30D7<>
46C7<
15B4< 11C3<
19C8>
SMB_SCL SMB_SDA
13 2
1 9
11
15 3
U8G1 TDFN-15_R
DS4404
I2C ADDRESS = 92H GTLREF +/- 150MILLIVOLTS
10 12 14
8
7 6 5 4
CPU_GTLREFR0 CPU_GTLREFR1 CPU_GTLREFR2 CPU_GTLREFR3
GTLREF_FS0 GTLREF_FS1 GTLREF_FS2 GTLREF_FS3
9B7< 10C2< 10B4< 9D8<
I38
2
1
R8G2
2.49K
1% 0402_R
DEFAULT = 0.628 * VTT
2
1
R8G1
2.49K
1% 0402_R
2
R8G4
2.49K
1% 0402_R
1
2
R8G3
2.49K
1% 0402_R
1
Wed Jan 16 11:22:28 2008
XDP CONN & GTLREF1 VREQ
602-7R177-0000-F00
6.0 11
Page 12
<XR_PAGE_TITLE>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBIBIBIBIBIBIBIBIBIBIBIBIOUT
OUT
OUT
OUTININININININININ
IN
SEC 1 OF 11
CPU_D0# CPU_D1# CPU_D2#
CPU_D4#
CPU_D3# CPU_D5# CPU_D7#
CPU_D6# CPU_D8#
CPU_D9# CPU_D10# CPU_D11# CPU_D12#
CPU_D15#
CPU_D14#
CPU_D13#
CPU_D17#
CPU_D16#
CPU_D20#
CPU_D19#
CPU_D18#
CPU_D21# CPU_D22# CPU_D23#
CPU_D25#
CPU_D24#
CPU_D27#
CPU_D26# CPU_D28# CPU_D30#
CPU_D29# CPU_D31#
CPU_D32# CPU_D33#
CPU_D35#
CPU_D34#
CPU_D38#
CPU_D37#
CPU_D36#
CPU_D40#
CPU_D39# CPU_D41#
CPU_D42# CPU_D43#
CPU_D45#
CPU_D44# CPU_D46# CPU_D48#
CPU_D47# CPU_D49#
CPU_D50# CPU_D51# CPU_D52# CPU_D53#
CPU_D56#
CPU_D55#
CPU_D54#
CPU_D58#
CPU_D57#
CPU_D61#
CPU_D60#
CPU_D59#
CPU_D62# CPU_D63#
CPU_RESET#
BCLK_OUT_CPU_P BCLK_OUT_CPU_N
BCLK_OUT_ITP_P BCLK_OUT_ITP_N
BCLK_OUT_NB_P BCLK_OUT_NB_N
BCLK_IN_P CPU_BSEL0
BCLK_IN_N
CPU_BSEL1 CPU_BSEL2
CPU_PECI
CPU_THERMTRIP#
CPU_PROCHOT#
V1P1_PLL_CPU V1P1_PLL_FSB
BCLK_VML_COMP_VDD BCLK_VML_COMP_GND
CPU_DSTBP0# CPU_DSTBN0# CPU_DBI0#
CPU_A3# CPU_A5#
CPU_A4#
CPU_DSTBP1# CPU_DSTBN1# CPU_DBI1#
CPU_DSTBP2# CPU_DBI2#
CPU_DSTBN2#
CPU_DSTBN3#
CPU_DSTBP3# CPU_DBI3#
CPU_A6# CPU_A7# CPU_A8# CPU_A9# CPU_A10# CPU_A11# CPU_A12# CPU_A13# CPU_A14#
CPU_A16#
CPU_A15# CPU_A17#
CPU_A18# CPU_A19# CPU_A20# CPU_A21# CPU_A22# CPU_A23# CPU_A24# CPU_A25# CPU_A26# CPU_A27# CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32# CPU_A33# CPU_A34# CPU_A35#
CPU_ADSTB0# CPU_ADSTB1#
CPU_REQ0# CPU_REQ2#
CPU_REQ1#
CPU_REQ4#
CPU_REQ3#
CPU_ADS# CPU_BNR# CPU_BR0# CPU_BR1# CPU_BPRI# CPU_DBSY# CPU_DEFER#
CPU_HIT#
CPU_DRDY# CPU_HITM# CPU_TRDY#
CPU_LOCK# CPU_RS0#
CPU_RS1# CPU_RS2#
CPU_A20M#
CPU_FERR# CPU_IGNNE#
CPU_INIT# CPU_SMI#
CPU_NMI
CPU_INTR CPU_STPCLK#
CPU_PWRGD
CPU_DPSLP#
CPU_SLP#
CPU_DPWR#
CPU_DPRSTP#
CPU_COMP_VCC
CPU_COMP_GND
BIBIBIBIININININININININININOUT
OUT
IN
A
B
C
D
E
F
3 2 1
REV PAGE
DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
F
C
B
A
456 3 2 18 7
10/26
+1.2V_VTT
2
1
R16E4 62
5% 0402_R
8A6<
8B3<> 8A3<> 8B2<>
CPU_RS<2..0>*
03/18/2008
8B3<> 8B3<> 8B3<>
8B3<> 8B3<> 8B3<>
8B3<> 8B3<> 8B3<>
8B3<> 8B3<> 8B3<>
8D3<>
8C3<> 8B3<> 8A6<>
CPU_ADS* CPU_BNR* CPU_BR0*
9D7< 9D7< 9D7> 9D7< 9D7< 9D7< 9D7<
9D7< 9C7<
11C6<
THESE PINS ARE USED BY MOBILE CPU
VTT_OUT_RIGHT
CPU_A<35..3>* CPU_ADSTB0*
CPU_ADSTB1* CPU_REQ<4..0>*
8B3<
8A3<>
8A3< 8A3<> 8A3<> 8A3<> 8A3<>
8A3<
0
1
2
R6F2
2
1
1%
0402_R
49.9 R6F1
1
49.9
CPU_DSTBP0* CPU_DSTBN0* CPU_DBI0*
CPU_DSTBP1* CPU_DSTBN1* CPU_DBI1*
CPU_DSTBP2* CPU_DSTBN2* CPU_DBI2*
CPU_DSTBP3* CPU_DSTBN3* CPU_DBI3*
CPU_BPRI* CPU_DBSY* CPU_DEFER* CPU_DRDY* CPU_HIT* CPU_HITM* CPU_LOCK* CPU_TRDY*
CPU_FERR* CPU_A20M*
CPU_IGNNE*
CPU_INIT* CPU_SMI* CPU_INTR
CPU_NMI
CPU_STPCLK*
MCP7A_CPU_PWRGD
CPU_COMP_VCC
CPU_COMP_GND
1%20402_R
U5E1 BGA1437
T40 U40 V41
W39 W37 V35
N37 L36 N35
M39 M41 J41
3
AB35
4
AE37
5
AC33
6
AC35
7
AC34
8
AE35
9
AE34
10
AG39
11
AE33
12
AG38
13
AG37
14
AF35
15
AG35
16
AG34
17
AJ34
18
AG33
19
AJ38
20
AJ37
21
AJ35
22
AL37
23
AJ36
24
AL39
25
AL38
26
AJ33
27
AL35
28
AL34
29
AN37
30
AL33
31
AN38
32
AN35
33
AN36
34
AR39
35
AN34 AE36
AK35
0
AC38
1
AA33
2
AE38
3
AC37
4
AC39
AD42 AD43 AE40 AL32 AA41 AD39 AA40 AD41 AB42 AD40 AC43 AE41 AC41 AB41 AC42
AH40 AF41 AH39 AH42 AH41 AF42 AG41 AG42 AH43
AM33 AN33 AN32 AM32
AM43
AM42
I3502
MCP7A
CPU_D<63..0>*
0
Y41
1
Y43
2
Y40
3
W42
4
Y42
5
Y39
6
V42
7
W41
8
T41
9
T43
10
T42
11
T39
12
U41
13
R41
14
P42
15
R42
16
AA38
17
AA35
18
AA36
19
AA37
20
AA34
21
W33
22
W34
23
W35
24
W38
25
U33
26
U34
27
U35
28
U36
29
U37
30
R33
31
U38
32
R35
33
R34
34
P35
35
N34
36
R38
37
R37
38
N33
39
R39
40
N36
41
N38
42
L37
43
L38
44
L39
45
J37
46
J38
47
J39
48
H40
49
L42
50
P41
51
M40
52
N40
53
N41
54
K42
55
M42
56
M43
57
L41
58
H42
59
H41
60
J40
61
K41
62
H43
63
H39
CPU_RST*
H38
G42 G41
AL43 AL42
AL41 AK42
BCLK_IN*
AK41
BCLK_IN
AJ40
BSEL0
F41
BSEL1
D42
BSEL2
F42
CPU_PECI_MCP
E41
CPU_PROCHOT*
AJ41
CPU_THERMTRIP*
AG43
V1.1V_PLL_MCLK_DLCELL_FSB_CPU
AH28 AG28
AM39
CPU_CLK_COMP_P
AM40
CPU_CLK_COMP_N
8A2<
10/16
11C6<
0402_R
0402_R
8A6<>
CPU_CLK CPU_CLK*
CPU_ITP_CLK
EMPTY C15F11 15PF
0402_R C0G 50V
5%2
CPU_ITP_CLK*
EMPTY
C15F2
1
15PF
0402_R C0G 50V
5%2
+1.2V_VTT
+1.2V_VTT
2
2
R6D4
R6D3
470
470
5%
5% 0402_R 0402_R
11
9D8<
46A5>
9C7< 9C7>
14B2>
VTT_OUT_RIGHT
R6F4
2
1
1%
49.9
R6F3
1
49.9
03/18/2008
2
1%
9C5> 9C5>
R12F9
0402_R
1
0402_R
EMPTY
+1.2V_VTT
2
1
R6D5 470
5% 0402_R
0
R12F8
21
R12F6
2
1
5%
5%
0402_R
0
2
R12F7
2
1
5%
0
5%
0402_R
EMPTY
0
EMPTY
C6D2
1
15PF
0402_R C0G 50V 5%
2
XDP_CLK
XDP_CLK*
INTERPOSER_BCLK
INTERPOSER_BCLK*
9C5>
C6E11 15PF
0402_R C0G 50V
5%2
EMPTY
9D4< 9D4<
11C5< 11C5<
9B5< 9B5<
MCP7A CPU
6.0602-7R177-0000-F00
12
Tue Mar 18 11:08:51 2008
Page 13
BIBIBI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIBI
OUT
OUT
OUT
OUT
OUT
SEC 2 OF 11
MDQ0_0 MDQ0_1 MDQ0_2
MDQ0_4
MDQ0_3
MDQ0_6
MDQ0_5
MDQ0_9
MDQ0_7 MDQ0_8
MDQ0_11
MDQ0_10
MDQ0_14
MDQ0_12 MDQ0_13
MDQ0_16
MDQ0_15 MDQ0_17 MDQ0_19
MDQ0_18
MDQ0_21
MDQ0_20 MDQ0_22 MDQ0_24
MDQ0_23 MDQ0_25
MDQ0_26 MDQ0_27
MDQ0_29
MDQ0_28
MDQ0_31
MDQ0_30 MDQ0_32 MDQ0_34
MDQ0_33 MDQ0_35
MDQ0_36 MDQ0_37
MDQ0_39
MDQ0_38 MDQ0_40
MDQ0_41 MDQ0_42 MDQ0_43
MDQ0_45
MDQ0_44
MDQ0_47
MDQ0_46
MDQ0_50
MDQ0_48 MDQ0_49
MDQ0_52
MDQ0_51
MDQ0_55
MDQ0_53 MDQ0_54
MDQ0_57
MDQ0_56 MDQ0_58 MDQ0_60
MDQ0_59
MDQ0_62
MDQ0_61 MDQ0_63
MRAS0#
MRESET0#
MWE0#
MCAS0#
MEM_COMP_1P8V
MEM_COMP_GND
MDQS0_0_N MDQS0_1_P
MDQS0_2_P MDQS0_2_N
MDQS0_4_N
MDQS0_3_N MDQS0_4_P
MDQS0_5_N
MDQS0_7_P
MDQS0_6_P MDQS0_6_N
MDQS0_5_P
MDQS0_3_P
MDQS0_1_N
MDQS0_0_P
MDQS0_7_N
MDQM0_0 MDQM0_1 MDQM0_2 MDQM0_3 MDQM0_4 MDQM0_5 MDQM0_6 MDQM0_7
MA0_0 MA0_1 MA0_2
MA0_4
MA0_3 MA0_5 MA0_7
MA0_6 MA0_8
MA0_9 MA0_10
MA0_12
MA0_11 MA0_13
MA0_14 MBA0_0 MBA0_2
MBA0_1
MCS0A_1#
MCS0A_0#
MCKE0A_1
MCKE0A_0 MODT0A_0
MODT0A_1
MCLK0A_0_P MCLK0A_1_P
MCLK0A_0_N MCLK0A_1_N
MCLK0A_2_P MCLK0A_2_N
MCS0B_0# MCS0B_1#
MCKE0B_1
MCKE0B_0
MODT0B_1
MODT0B_0
MCLK0B_0_P MCLK0B_0_N MCLK0B_1_P MCLK0B_1_N
MCLK0B_2_N
MCLK0B_2_P
OUT
OUT
OUT
OUT
OUT
OUT
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
27A8<
27B8<
27C3< 26D5<
27C3< 26D5<
26C8<>
26C8<>
25D5<
25D5<
25C8<>
25C8<>
25C8< 26C8<
25B8< 26C8< 27B8<
27A8< 26D5<
27A8<
MEM_0A_CKE<1..0> MEM_0A_ODT<1..0>
27B3<
MEM_0B_CKE<1..0> MEM_0B_ODT<1..0>
25D5<
25D5<
26D5<
MEM_0_DQS<7..0> MEM_0_DQS<7..0>*
MEM_0_DQM<7..0>
MEM_0_ADD<14..0>
MEM_0_BA<2..0>
MEM_0A_CS<1..0>*
0 1 0 1
25C5< 25C5< 25C5< 25C5< 25C5< 25C5<
MEM_0B_CS<1..0>*
0 1 0 1
26C5< 26C5< 26C5< 26C5< 26C5< 26C5<
0 1 2 3 4 5 6 7
MEM_0A_CLK0
MEM_0A_CLK0*
MEM_0A_CLK1
MEM_0A_CLK1*
MEM_0A_CLK2
MEM_0A_CLK2*
MEM_0B_CLK0 MEM_0B_CLK0* MEM_0B_CLK1 MEM_0B_CLK1* MEM_0B_CLK2 MEM_0B_CLK2*
10 11 12 13 14
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7
0 1 2 3 4 5 6 7 8 9
0 1 2
0 1
0 1
AU39 AT39 AT35 AU35 AU30 AU29 AV25 AW25 AP13 AR13 AW7 AW8 AR8 AR9 AL10 AL11
AR34 AV35 AW29 AN27 AN13 AR10 AU5 AN5
AR19 AT19 AU19 AV19 AN21 AR21 AP21 AU21 AR22 AV21 AN19 AW21 AN23 AU15 AR23
AW17 AP19 AP23
AR18 AT15 AT23 AU23 AV15 AP15
BB20 BC20 BA24 AY24 AW33 AV33
AU17 AR15 AV23 AN25 AN17 AN15
BA21 BB21 BB24 BC24 AU33 AU34
U5E1 BGA1437
I153
MCP7A
AP35 AR35 AW38 AV38 AR38 AR37 AV39 AW39 AU37 AT37 AV31 AT31 AW37 AV37 AR33 AU31 AN31 AV29 AN29 AV27 AR31 AP31 AR29 AP29 AR27 AP27 AR25 AP25 AU27 AT27 AU25 AR26 AU13 AR14 AT11 AR11 AW13 AV13 AV11 AU11
AV9 AU9 AY5 AW6
AP11
AW9 AU8 AU7 AV5 AU6 AR5
AN10
AW5 AV6 AR7 AR6 AN7 AN6 AL7 AL6 AN9 AP9 AL9 AL8
AV17 AP17 AR17
AY32
AN41
AM41
Wed Jan 16 11:22:31 2008
MEM_0_DATA<63..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
MEM_0_RAS* MEM_0_CAS* MEM_0_WE*
TP_MRESET*
MEM_COMP_1P8V
MEM_COMP_GND
26C5< 25C5< 26C5< 25C5< 26C5< 25C5<
10/12
+1.8V_SUS
2
1%
2
1%
1
0603_R
1
0603_R
R6F5
40.2
R6F6
40.2
27A8<
27A8<
27A8<
26A3<> 25A3<>
MCP7A MEM CH0
136.0602-7R177-0000-F00
Page 14
OUTBIBIBIBI
OUT
OUT
OUT
OUTBIBI
OUT
OUT
OUT
OUT
OUT
OUT
SEC 3 OF 11
MDQ1_0 MDQ1_1 MDQ1_2 MDQ1_3 MDQ1_4 MDQ1_5
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_10
MDQ1_9
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_14 MDQ1_15 MDQ1_16
MDQ1_18
MDQ1_17
MDQ1_20
MDQ1_19 MDQ1_21 MDQ1_23
MDQ1_22 MDQ1_24
MDQ1_25 MDQ1_26
MDQ1_28
MDQ1_27
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_33
MDQ1_32 MDQ1_34
MDQ1_35 MDQ1_36
MDQ1_38
MDQ1_37 MDQ1_39 MDQ1_41
MDQ1_40 MDQ1_42
MDQ1_43 MDQ1_44 MDQ1_45 MDQ1_46
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_51
MDQ1_50
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_55 MDQ1_56 MDQ1_57
MDQ1_59
MDQ1_58
MDQ1_61
MDQ1_60 MDQ1_62
MDQ1_63
MRAS1# MCAS1#
V1P1_PLL_MCLK
MWE1#
V1P1_DLLDLCELL_AVDD
MDQS1_0_P MDQS1_1_P
MDQS1_0_N MDQS1_1_N
MDQS1_2_P MDQS1_2_N
MDQS1_4_P
MDQS1_3_N
MDQS1_3_P
MDQS1_5_P
MDQS1_4_N
MDQS1_6_N
MDQS1_6_P
MDQS1_5_N
MDQS1_7_P MDQS1_7_N
MDQM1_0 MDQM1_2
MDQM1_1 MDQM1_3
MDQM1_4 MDQM1_5 MDQM1_6 MDQM1_7
MA1_0 MA1_1
MA1_3
MA1_2 MA1_4 MA1_6
MA1_5 MA1_7
MA1_8 MA1_9 MA1_10 MA1_11 MA1_12 MA1_13 MA1_14
MBA1_1
MBA1_0 MBA1_2
MCS1A_0# MCKE1A_0
MCS1A_1#
MODT1A_0 MODT1A_1
MCKE1A_1
MCLK1A_0_P MCLK1A_0_N
MCLK1A_1_N
MCLK1A_1_P MCLK1A_2_P
MCLK1A_2_N
MCS1B_0# MCKE1B_0
MCS1B_1#
MODT1B_0
MCKE1B_1 MODT1B_1
MCLK1B_0_P MCLK1B_0_N MCLK1B_1_P MCLK1B_1_N
MCLK1B_2_N
MCLK1B_2_P
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
27A5<
27B5<
27A3<
27B3<
24C8<>
24C8<>
27A5< 24D5< 23D5<
23D5<
23D5<
24D5<
24D5<
23C8<>
23C8<>
23C8< 24C8<
23C8< 24C8< 27B5<
23D5< 27A5<
MEM_1A_CKE<1..0> MEM_1A_ODT<1..0>
24D5< 27A3<
MEM_1B_CKE<1..0> MEM_1B_ODT<1..0>
MEM_1_DQS<7..0> MEM_1_DQS<7..0>*
MEM_1_DQM<7..0>
MEM_1_ADD<14..0>
MEM_1_BA<2..0>
MEM_1A_CS<1..0>*
0 1 0 1
23C5< 23C5< 23C5< 23C5< 23C5< 23C5<
MEM_1B_CS<1..0>*
0 1 0 1
24C5< 24C5< 24C5< 24C5< 24C5< 24C5<
U5E1 BGA1437
0
0 1 2 3 4 5 6 7
MEM_1A_CLK0
MEM_1A_CLK0*
MEM_1A_CLK1
MEM_1A_CLK1*
MEM_1A_CLK2
MEM_1A_CLK2*
MEM_1B_CLK0 MEM_1B_CLK0* MEM_1B_CLK1 MEM_1B_CLK1* MEM_1B_CLK2 MEM_1B_CLK2*
10 11 12 13 14
0 1 2 3 4 5 6 7 8 9
0 1 2
AT42 AT43
1
BA43 AY42
2
BB37 BA37
3
BB33 BA33
4
BA10 AY11
5
BB6 BA6
6
AY2 AY1
7
AT2 AT1
0
AR42
1
AY43
2
BB38
3
BB34
4
BA11
5
AY7
6
BA2
7
AT5
BA18 BB25 BA25 BB26 BA26 BA27 AY27 BA28 AY28 BB28 BA17 BC28 AW28 BA14 BA29
BB17 BB18 BB29
0
BB16
1
BB14 BB30 AY31 AY15 BB13
BA19 AY19 BB22 BA22 BA42 BB42
0
BC16
1
BA13 BA30 BA31 AY16 BC13
BA20 AY20 AY23 BA23 BA41 BB41
I154
MCP7A
AP42 AR41 AU41 AU40 AN40 AP41 AT41 AT40 AW41 AW42 BC40 BA40 AV41 AV42 AW40 BB40 AY39 BA38 BB36 BA36 AY40 BA39 AW36 BC36 AY35 BA34 BB32 BA32 AY36 BA35 AW32 BC32 BA12 AY12
BB9
BB8 AW12 BB12 BB10
BA9
AY8
BA7
BC4
BB4
BC8
BA8
BA5
BB5
BB2
BA3
AW3
AW4
BC3
BB3
AY3
AY4
AU3
AU2
AR3
AR4
AV3
AV2
AT3
AT4
MEM_1_RAS*
AW16
MEM_1_CAS*
BA15
MEM_1_WE*
BA16
AH27
AG27
Wed Jan 16 11:22:32 2008
MEM_1_DATA<63..0>
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
27A5<
24C5<
23C5< 23C5< 23C5<
24C5< 24C5<
27A5< 27A5<
23A3<>
24A3<>
MCP7A MEM CH1
11/27
12B3<
C16E64
1
2.2UF
0402_R
6.3V
2
C16E61
1
4.7UF
0603_R X5RX5R
6.3V
10%220%
1500MA
+1.1V_CORE
L16E8
30
2
1
FB0603_R
6.0602-7R177-0000-F00
14
Page 15
<XR_PAGE_TITLE>
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIOUTBIIN
OUT
SEC 4 OF 11
IFPA_TXD3_P
IFPA_TXD2_N
IFPA_TXD2_P
IFPA_TXD1_N
IFPA_TXD3_N
IFPA_TXD1_P
IFPA_TXD0_N
IFPA_TXD0_P
IFPA_TXC_P IFPA_TXC_N
IFPB_TXD4_P IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD5_P IFPB_TXD6_P IFPB_TXD7_P
IFPB_TXD6_N IFPB_TXD7_N
V3P3_PLL_IFPAB
IFPAB_VPROBE
IFPAB_RSET
IFPB_TXC_N
IFPB_TXC_P
LCD_BKL_ON/GPIO_59
LCD_BKL_CTL/GPIO_57
DDC_DATA0
HPLUG_DET2/GPIO_22
DDC_CLK2/GPIO_23
DDC_DATA2/GPIO_24
DDC_CLK0
DDC_DATA3
HPLUG_DET3
DDC_CLK3
LCD_PANEL_PWR/GPIO_58
HDMI_TXD2_N/ML0_LANE0_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N
TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45
HDMI_RSET HDMI_VPROBE
V3P3_PLL_HDMI
DP_AUX_CH0_P DP_AUX_CH0_N
RGB_DAC_BLUE RGB_DAC_GREEN RGB_DAC_RED
RGB_DAC_VREF
RGB_DAC_RSET
RGB_DAC_VSYNC
RGB_DAC_HSYNC
TV_DAC_BLUE TV_DAC_GREEN TV_DAC_RED
XTALOUT_TV
TV_DAC_VREF
XTALIN_TV
TV_DAC_RSET
V1P1_PLL_DP V1P1_PLL_V
V1P1_PLL_CORE
OUT
OUTINBIINOUT
OUT
OUT
OUT
SERIAL EEPROM
2-WIRE
VCC
WP
SDA
SCL
A0 A1
GND
A2
A
B
C
D
E
F
3 2 1
REV PAGE
DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
F
C
B
A
456 3 2 18 7
36C8< 36C8< 36C8<
U5E1
G35 F35 F33 G33 J33 H33
D35 E35
BGA1437
MCP7A
B32 A32 D32 C32 D33 C33 B34 C34
B35 C35
HDMI_TXD0P HDMI_TXD0N HDMI_TXD1P HDMI_TXD1N HDMI_TXD2P HDMI_TXD2N
HDMI_TXC0P HDMI_TXC0N
36B6< 36B6< 36B6< 36B6< 36B4< 36B4<
36B6< 36B6<
J31
19C8>
28C6< 19C8>
J29 H29 L29 K29 L30 K30 N30 M30
L31 K31
IFPAB_RSET
E32
IFPAB_VPROBE
G31
M28
G39 E37 F40
DDC_DATA
A31
DDC_CLK
B31
HDMI_DDC_DATA
B30
HDMI_DDC_CLK
C30
HPLUG_DET2
C31
DDC_DATA3_R
E31
DDC_CLK3_R
D31
HPLUG_DET3
F31
29D7<
29D7<> 28C6<>
EMPTY
R16E5
1
0402_R
2
1%
9/27
2
C16E73
.1UF
1
0402_R X7R 16V 10%
EMPTY
36C8<>
36C8<
36A8< 36A8< 36A8>
+3.3V
C5D91
C5D101
4.7UF
.1UF
0603_R
0402_R
X5R
X7R
6.3V
16V
10%
2
10%
2
+5V
2
2
R5D19
R5D20
2.7K2.7K
5%
5%
0603_R
0603_R
1
1
1K
2
R5D18 22K
5% 0402_R
10/3
1
46C7< 39D6< 31A7< 30D7<
46C7< 39D6<> 31A7<> 30D7<>
DAC_BLUE DAC_GREEN DAC_RED
+1.1V_CORE
2
2
R5D22 150
1% 0402_R
1
1
PLACE NEAR MCP7A
L16E7
10NH
1
300MA
V1.1V_PLL_DP_XREF_CORE_V
2
SMD
0603_R
1
11/27
16B6<
R6D1 150
1% 0402_R
C16E69
4.7UF
0603_R X5R
6.3V
10%2
10/16
2
1
1 2 3 4
0402_R
1
36D8< 36D8<
R5D21
R6D2 150
1% 0402_R
C16E651
2.2UF
0402_R X5R
6.3V
20%2
U2J1
AT24C16BN-SH-B
SOIC_R
10/2
124
J30
V3P3_PLL_HDMI
2
R16E3 0
5% 0402_R
1
DAC_HSYNC DAC_VSYNC
8 7 6 5
21%
.01UF
C5D11
10/18
+3.3V
HDCP_WP
DAC_RSET
DAC_VREF
1
0402_R X7R 16V 10%
1
C3J2 .1UF
0402_R X7R 16V
10%2
2
C16E571
4.7UF
0603_R X5R
6.3V
10%2
+3.3V
2
1
M29
D43 C43
B40 A39 B39
A40 A41
C39 B38
C36 B36 A36
D36 C37
E36 A35
C38 D38
U27 U28 T28
I45
R2J8 10K
5% 0402_R
10/11
REMOVE FOR PRODUCTION
R2J3
1
2
5%00402_R
SIO_HDCP_WP
SMB_SCL SMB_SDA
39A6> 11A7<
11A7<>
11C3<
11C3<>
I61
USE FOR HDCP
MCP7A DISPLAY
6.0602-7R177-0000-F00
15
Wed Jan 16 11:22:33 2008
Page 16
<XR_PAGE_TITLE>
MECH
OUT
OUT
OUTINININOUTINOUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTININININ
SEC 5 OF 11
PE0_TX15_P PE0_TX14_P PE0_TX13_P
PE0_TX8_P
PE0_TX11_P
PE0_TX12_P PE0_TX10_P
PE0_TX9_P
PE0_TX3_P
PE0_TX7_P PE0_TX6_P PE0_TX5_P PE0_TX4_P
PE0_TX1_P
PE0_TX2_P PE0_TX0_P
PE0_TX15_N PE0_TX14_N
PE0_TX12_N
PE0_TX13_N PE0_TX11_N
PE0_TX10_N
PE0_TX9_N PE0_TX8_N PE0_TX7_N PE0_TX6_N PE0_TX5_N PE0_TX4_N
PE0_TX1_N
PE0_TX2_N
PE0_TX3_N
PE0_TX0_N
PE0_RX13_P
PE0_RX15_P PE0_RX14_P
PE0_RX11_P
PE0_RX12_P PE0_RX10_P
PE0_RX8_P
PE0_RX9_P PE0_RX7_P PE0_RX5_P
PE0_RX6_P PE0_RX4_P
PE0_RX3_P PE0_RX1_P
PE0_RX0_P
PE0_RX2_P
PE0_RX14_N PE0_RX13_N
PE0_RX15_N
PE0_RX0_N
PE0_RX1_N
PE0_RX3_N PE0_RX2_N
PE0_RX4_N
PE0_RX6_N PE0_RX5_N
PE0_RX8_N PE0_RX7_N
PE0_RX9_N
PE0_RX10_N
PE0_RX11_N
PE0_RX12_N
PE0_REFCLK_N
PE0_REFCLK_P
PE0_PRSNT_16#
PEE_PRSNT#/GPIO_46 PEF_PRSNT#/GPIO_47 PEG_PRSNT#/GPIO_48
PEB_CLKREQ#/GPIO_49 PED_CLKREQ#/GPIO_51
PEE_CLKREQ#/GPIO_16
PEC_CLKREQ#/GPIO_50
PEG_CLKREQ#/GPIO_18
PEF_CLKREQ#/GPIO_17
V1P1_PLL_XREF_XS
PE1_TX0_P PE1_TX1_P PE1_TX2_P PE1_TX3_P
PE1_TX0_N
PE1_TX3_N
PE1_RX0_P
PE1_TX2_N
PE1_TX1_N
PE1_RX2_P PE1_RX3_P
PE1_RX1_P
PE1_RX0_N PE1_RX1_N
PE1_RX3_N
PE1_RX2_N
PE1_REFCLK_N
PE1_REFCLK_P
PE2_REFCLK_P PE2_REFCLK_N
PE3_REFCLK_N
PE3_REFCLK_P
PE4_REFCLK_P PE4_REFCLK_N
PE5_REFCLK_P PE5_REFCLK_N
PE6_REFCLK_P PE6_REFCLK_N
PEC_PRSNT# PED_PRSNT#
PEB_PRSNT#
V1P1_PLL_PEX
PEX_CLK_COMP
PE_WAKE#
PEX_RST0#
OUTININ
OUT
OUT
A
B
C
D
E
F
3 2 1
REV PAGE
DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
F
C
B
A
456 3 2 18 7
+1.1V_CORE
+3.3V_DUAL
16C6> 16B6>
21A7< 19D3<
32B7< 44D2>
L16E4
10NH
2
1
SMD
0603_R300MA
4.7UF
0603_R X5R
10%
2
R3C4
PEXRESET0*
2
1
5%
0402_R
EMPTY
10K
R4C13
PE_WAKE*
2
1
5%
0402_R
10K
EMPTY
FOR A01 WAR
11 C16E25
2
C16E20
2.2UF
0402_R X5R
6.3V6.3V 20%
PEXRESET0*
PS_PWRGD
30D8> 29D8>
16F6< 16B6>
28C7>
15B6>
16C6>
16C6<
28C7<
28C7<
28C3>
28C3>
30D2< 30D2<
28C3< 28C3<
30B8> 28C7>
R4D3
R4D1
1
5%
0402_R
0
16B6>
1
0603_R
2.37K
V1.1V_PLL_DP_XREF_CORE_V
16F6<
30D8> 29D8> 28C7>
1 2
5%210402_R2
0
R4D8
2
1%
EMPTY
V1.1V_PEX_PLL
PE1_CLKREQ* PE2_CLKREQ*
+3.3V_DUAL
EMPTY
5
U3C1 74LVC1G08 SC70_R
4
I83
3
R3C3
2
1
5%
0402_R
0
TP_PE1_TXC PE2_TXC TP_PE1_TX2 TP_PE1_TX3
TP_PE1_TXC* PE2_TXC* TP_PE1_TX2* TP_PE1_TX3*
TP_PE1_RX PE2_RX TP_PE1_RX2 TP_PE1_RX3
TP_PE1_RX* PE2_RX* TP_PE1_RX2* TP_PE1_RX3*
PE_X8-2_REFCLK PE_X8-2_REFCLK*
PE2_REFCLK PE2_REFCLK*
PE_X8-2_PRESENT* PE2_PRESENT*
PEXRESET0*
PE_WAKE*
PE_CLK_COMP
+3.3V_DUAL
C3C10
.1UF
0402_R
X7R 16V
10% 2
EMPTY
1
PE_RESET*
D8 B8 A7 B6
C8 A8 B7 C6
K9 H9 F9 H7
J9 G9 E9 G7
G11 F11
J11 J10
G13 F13
J13 H13
L14 K14
N14 M14
D9 C10 B10 L18 M18 M19
D5 E8 M15 L16 M16 M17
K11 F17
A11
T16 T27
U5E1 BGA1437
I110
28C3<
30D2< 29D2<
MCP7A
15
M2
14
M4
13
L4
12
K2
11
J2
10
H1
9
H3
8
G3 F3 E2 D2 C1 B3 A4 C4 C5
M1 M3 L3 K3 J3 J1 H2 H4 F4 F2 E1 D1 B2 A3 B4 D4
N5 N7 N9
N11
L7 L9
L11
J5 J7 G5 C3 E4 E5 E6 D7 F7
N4 N6 P9
N10
L6 L8
L10
J4 J6 H5 D3 E3 F5 F6 C7 E7
PE_X8-1_REFCLK
E11
PE_X8-1_REFCLK*
D11
PE_X8-1_PRESENT*
C9
PE_X8-2_TXC<15..8>
7 6 5 4 3 2 1 0
PE_X8-2_TXC<15..8>*
15 14 13 12 11 10 9 8
PE_X8-2_RX<15..8>
15 14 13 12 11 10 9 8
PE_X8-2_RX<15..8>*
15 14 13 12 11 10 9 8
PE_X8-1_TXC<7..0>
PE_X8-1_TXC<7..0>*
7 6 5 4 3 2 1 0
PE_X8-1_RX<7..0>
7 6 5 4 3 2 1 0
PE_X8-1_RX<7..0>*
7 6 5 4 3 2 1 0
29D2< 29D2<
29B8>
30B8<
30B8<
30C2>
30C2>
29C2>
29C2>
29B8<
29B8<
HS5E1 HEATSINK MCP7A_PASSIVE_HEATSINK PASSIVE
I127
MCP7A PCIE
Tue Mar 18 12:13:57 2008
6.0602-7R177-0000-F00
16
Page 17
OUT
OUT
OUT
OUT
OUTBIIN
OUT
OUT
OUT
OUT
OUTININININ
OUT
OUT
OUT
OUT
OUTINININBI
BI
SEC 6 OF 11
PCI_REQ0#
PCI_REQ1#/FANRPM2
PCI_GNT0#
PCI_GNT1#/FANCTL2
PCI_CLKIN
PCI_CLK2
PCI_CLK1
PCI_CLK0
PCI_INTW# PCI_INTX#
PCI_INTZ#
PCI_INTY#
LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3
LPC_DRQ1#/GPIO_19
LPC_FRAME#
LPC_DRQ0#
LPC_CLK0
LPC_RESET0#
LPC_SERIRQ
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ2#/GPIO_40/RS232_DSR# PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
LPC_PWRDWN#/GPIO_54/EXT_NMI#
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_AD0 PCI_AD1 PCI_AD2 PCI_AD3
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD24
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD29 PCI_AD31
PCI_AD30
PCI_CBE0# PCI_CBE2#
PCI_CBE1# PCI_CBE3#
PCI_FRAME# PCI_TRDY#
PCI_IRDY#
PCI_PAR
PCI_STOP# PCI_DEVSEL#
PCI_SERR# PCI_PME#/GPIO_30
PCI_RESET1#
PCI_RESET0#
PCI_CLKRUN#/GPIO_42
BIBIBIBIBIBIOUTINOUT
OUT
OUT
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
40B8>
31A7> 31B3> 32C8>
32C8<> 31D7<>
32C8<> 31B7<>
MCP_COM_DCD1*
PCI_PERR*
31A7<
32C8<
+3.3V
2
R4E1
8.2K
5% 0402_R
1
R4E5
1
5%
0402_R
0
R4E6
1
5%
0402_R
0
PCI_RST_SLOTS_1*
PCI_RST_1394*
2
2
EMPTY
32C8<> 32C8<> 32C8<> 32C8<> 32D8<>
32C8> 32D8>
PCI_AD<31..0>
PCI_C/BE<3..0>*
31B3>
31B7>
R17E4
1
31B3> 31B3> 31A3> 31A3> 31B3>
31A7<>
31A7> 31A3>
2
5%0402_R
33
R4E19
1
0402_R
31B7<> 31B7<> 31B7<> 31B7<> 31B7<>
32C8<>
5%
33
PCI_FRAME* PCI_IRDY* PCI_TRDY* PCI_STOP* PCI_DEVSEL* PCI_PAR
PCI_SERR* PCI_PME*
PCI_RESET0*
2
PCI_RESET1*
U5E1 BGA1437
0
AC3
1
AE10
2
AC4
3
AE11
4
AB3
5
AC6
6
AB2
7
AC7
8
AC8
9
AA2
10
AC9
11
AC10
12
AC11
13
AA1
14
AA5
15
Y5
16
W3
17
W6
18
W4
19
W7
20
V3
21
W8
22
V2
23
W9
24
U3
25
W11
26
U2
27
U5
28
U1
29
U6
30
T5
31
U7
0
AA3
1
AA6
2
AA11
3
W10
Y4 AA10 Y3 Y2 AA9 Y1 AB9 AA7 T1 AD11
R10 R11
I112
MCP7A
T2 V9 T3 U9 T4
R3
U10
R4
U11
P3
R6 R7
PCI_CLK2
R8
PCI_CLKIN
R9
PCI_INTW*
P2
PCI_INTX*
N3
PCI_INTY*
N2
PCI_INTZ*
N1
LPC_AD_R<0>
AD3
LPC_AD_R<1>
AD2
LPC_AD_R<2>
AD1
LPC_AD_R<3>
AD5
LPC_DRQ0*
AE1
FP_AUDIO_PRESENCE*
AE2
LPC_FRAME_R*
AD4
LPC_SERIRQ
AE6
LPC_RESET*
AE5
AE12
AE9
Wed Jan 16 11:22:36 2008
PCI_REQ<1..0>*
0 1
MCP_COM_DSR1* MCP_COM_CTS1* MCP_COM_RXD1
PCI_GNT0*
PCI_GNT1*
MCP_COM_DTR1* MCP_COM_RTS1* MCP_COM_TXD1
PCI_CLK0
PCI_CLK1
1
0402_R
LPC_CLK0
R4E9
22
0402_R
0402_R
1
2
R17E5
2
1
5%
0402_R
22
EMPTY
31C3>
31B7>
31C3>
31B7>
31C3> 31B7> 31C3>
31B7>
2
R4E18
2
1
5%
0402_R
R4E14
1
R4E16
1
C4E2 10PF
0402_R C0G 50V 5%
EMPTY
R4E13
2
15%
22
0402_R
22
0402_R
39D2> 37B5>
39D2<>
LPC_RST_SIO*
2
5%
33
LPC_RST_FLASH*
2
5%
33
1
0402_R
0402_R
R4E3
R4E4
LPC_CLK_FLASH
2
5%
33
21
5%
33
15%
LPC_CLK_SIO
32D8>
R4E10
22
31B7<> 32C8< 40A8< 40B8< 40B8<
C17E51 10PF
0402_R C0G 50V
2
5%
2
5%
1
0402_R
C17E3
1
10PF
0402_R C0G 50V 5%
2
EMPTY
LPC_AD<3..0>
0 1 2 3
R4E17
1
0402_R
R17E3
22
5%
22
32C8<> 31D3> 31B7<>
2
2
5%
22 2
R3E1
8.2K
5% 0402_R
1
1
R4E12
8.2K
5% 0402_R
PCI_CLKSLOT1
2
+3.3V
2
1
C17E21 10PF
0402_R C0G 50V 5%
R4E8
8.2K
5% 0402_R
R17E2
22
EMPTY
EMPTY
PCI_CLK_1394
21
5%0402_R
LPC_FRAME*
39D6<
2
35D1<
35D1<
39D6<
MCP7A PCI/LPC
1
602-7R177-0000-F00
+3.3V+3.3V+3.3V
R4E7
8.2K
5% 0402_R
R4E15 10K
5% 0402_R
1
39D2<> 35D3<>
40B8> 40B8> 40B8>
STRAP
HDA_SDOUT LPC_FRAME
DEFAULT*
00 = LPC BIOS 01 = PCI BIOS 10 = SPI BIOS CS0 * 11 = SPI BIOS CS1
31A7<
32C8<
39D6< 35D3<
6.0 17
Page 18
BIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIBIINININ
IN
L1H8L1H
8
SEC 7 OF 11
USB0_N
USB0_P
USB1_P USB1_N
USB2_P USB2_N
USB3_P
USB6_P USB6_N
USB3_N
USB7_P
USB5_P USB5_N
USB4_N
USB4_P
USB9_P USB9_N
USB10_N
USB11_P
USB8_P USB8_N
USB7_N
USB10_P
USB11_N
USB_RBIAS_GND
V3P3_PLL_USB
USB_OC0#/GPIO_25 USB_OC1#/GPIO_26
USB_OC3#/GPIO_28/MGPIO
USB_OC2#/GPIO_27/MGPIO
V1P1_PLL_SP_SPREF
SATA_A0_TX_N
SATA_A0_TX_P
SATA_A1_TX_P SATA_A1_TX_N
SATA_A1_RX_N SATA_A1_RX_P
SATA_A0_RX_N SATA_A0_RX_P
SATA_B1_TX_P SATA_B1_TX_N
SATA_B0_TX_P SATA_B0_TX_N
SATA_B0_RX_P
SATA_B0_RX_N
SATA_B1_RX_P
SATA_B1_RX_N
SATA_C0_TX_N
SATA_C0_TX_P
SATA_C1_TX_N
SATA_C0_RX_P
SATA_C0_RX_N
SATA_C1_RX_P
SATA_C1_RX_N
SATA_C1_TX_P
SATA_LED#
V1P1_PLL_NV_H
SATA_TERMP
V1P1_PLL_SATA
OUT
L1H
8
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
SATA_DUAL_RA_SMD
J1K2 SMD_R BLACK
1
SATA_B0_TX_P_C
2
SATA_B0_TX_N_C
3 4
SATA_B0_RX_N_C
5
SATA_B0_RX_P_C
6 7
I75
J1K2 SMD_R
SATA_DUAL_RA_SMD
BLACK
8
9 2 10 11 12 13 14
I76
SATA_DUAL_RA_SMD
BLACK
1
SATA_C0_TX_P_C
2
SATA_C0_TX_N_C
3 4
SATA_C0_RX_N_C
5
SATA_C0_RX_P_C
6 7
I61
J3K1 SMD_R
SATA_DUAL_RA_SMD
J3K1 SMD_R BLACK
8
9 10 11 12 13 14
I72
SATA_DUAL_RA_SMD
J2K1 SMD_R BLACK
1
SATA_A0_TX_P_C
2
SATA_A0_TX_N_C
3 4
SATA_A0_RX_N_C
5
SATA_A0_RX_P_C
6 7
I38
J2K1 SMD_R BLACK
SATA_DUAL_RA_SMD
8
SATA_A1_TX_P_C
9
SATA_A1_TX_N_C
10 11
SATA_A1_RX_N_C
12
SATA_A1_RX_P_C
13 14
I60
10/16
SATA_B1_TX_P_C SATA_B1_TX_N_C
SATA_B1_RX_N_C SATA_B1_RX_P_C
SATA_C1_TX_P_C SATA_C1_TX_N_C
SATA_C1_RX_N_C SATA_C1_RX_P_C
PLACE CAPS AT CONN
C19J8
2
.01UF
C19J6
2
.01UF
PLACE CAPS AT CONN
C19J4
2
.01UF
C19J2
2
.01UF
PLACE CAPS AT CONN
C20J2
1
2
2
.01UF
C20J8
.01UF
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
2
.01UF
2
.01UF
C20J1
C20J7
PLACE CAPS AT CONN
C20J6
1
0402_R X7R
.01UF
16V 10%
C20J4
1
2
0402_R X7R
.01UF
16V 10%
PLACE CAPS AT CONN
C18J4
1
2
2
.01UF
C18J2
.01UF
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
2
.01UF
2
.01UF
C18J3
C18J1
PLACE CAPS AT CONN
C18J8
1
2
0402_R X7R
.01UF
16V 10%
C18J6
1
2
0402_R X7R
.01UF
16V 10%
+1.1V_CORE
L16E1
10NH
2
1
SMD
0603_R
300MA
C16E171
4.7UF
0603_R X5R
6.3V
2 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
SATA_B0_TX_P SATA_B0_TX_N
1
0402_R X7R 16V
SATA_B0_RX_N
10%
SATA_B0_RX_P
1
0402_R X7R 16V 10%
C20J5
1
2
0402_R X7R
.01UF
16V 10%
C20J3
1
2
0402_R X7R
.01UF
16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
C18J7
2
.01UF
C18J5
2
.01UF
C16E14
1
2.2UF
0402_R X5R
6.3V 20%
2
C19J7
1
2
0402_R X7R
.01UF
16V 10%
C19J5
1
2
0402_R X7R
.01UF
16V 10%
C19J3
1
2
0402_R X7R
.01UF
16V 10%
C19J1
1
2
0402_R X7R
.01UF
16V 10%
SATA_B1_TX_P SATA_B1_TX_N
SATA_B1_RX_N SATA_B1_RX_P
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
+1.1V_CORE
SATA_A0_TX_P SATA_A0_TX_N
SATA_A0_RX_N SATA_A0_RX_P
SATA_A1_TX_P SATA_A1_TX_N
SATA_A1_RX_N SATA_A1_RX_P
SATA_C0_TX_P SATA_C0_TX_N
SATA_C0_RX_N SATA_C0_RX_P
SATA_C1_TX_P SATA_C1_TX_N
SATA_C1_RX_N SATA_C1_RX_P
SATA_HDLED*
R4E11
SATA_TERMP
2
1
1%
2.49K
C16E19
1
2.2UF
0402_R X5R
6.3V
2
20%
NEAR CHIP'S BALL
10NH
300MA
11/27
44B5<
0402_R
V1.1V_SATA_PLL V1.1V_NV_SP_PLL
L16E5
2
1
SMD
0603_R
C16E28
1
4.7UF
0603_R X5R
6.3V 10%
2
U5E1 BGA1437
AJ7 AJ6
AJ5 AJ4
AJ11 AJ10
AJ9 AK9
AK2 AJ3
AJ2 AJ1
AM4 AL3
AL4 AK3
AN1 AM1
AM2 AM3
AP3 AP2
AN3 AN2
E12
AE3
AE16 AE17 AE18
C16E22
1
2
2.2UF
0402_R X5R
6.3V 20%
I43
Thu Feb 14 13:52:29 2008
MCP7A
INTERNAL PULL DOWN 19.5KOHM TO GND
C29 D29
C28 D28
A28 B28
F29 G29
K27 L27
J26 J27
F27 G27
D27 E27
K25 L25
H25 J25
F25 G25
K23 L23
L21 K21 J21 H21
A27
L28
USB_OC3210* USB_OC7654* USB_OC98* USB_OC1110*
USB_RBIAS_GND
V3.3V_PLL_USB
10/17
USB_0 USB_0*
USB_1 USB_1*
USB_2 USB_2*
USB_3 USB_3*
USB_4 USB_4*
USB_5 USB_5*
USB_6 USB_6*
USB_7 USB_7*
USB_8 USB_8*
USB_9 USB_9*
USB_10 USB_10*
USB_11 USB_11*
R5D14
1
0603_R
806
33D4> 33B4> 33D1> 33C3>
2/14/2008
2
1%
MCP7A SATA/USB
33D8<> 33D8<>
33C8<> 33C8<>
33C8<> 33C8<>
33B8<> 33B8<>
33A8<> 33A8<>
33A8<> 33A8<>
33A4<> 33A4<>
33A1<> 33A1<>
33C1<> 33C1<>
33C4<> 33C4<>
33B3<> 33B3<>
33B6<> 33B6<>
1
2
2.2UF
0402_R X5R
6.3V 20%
C16E66
1C16E63
4.7UF
0603_R X5R
6.3V
10%2
1500MA
30
1
0603_R
11/27
6.0602-7R177-0000-F00
L16E9
2
FB
+3.3V_DUAL
18
Page 19
<XR_PAGE_TITLE>
IN
OUTINININOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTINININININININOUTINOUT
OUTININ
OUT
OUTINININOUT
OUTININ
IN
D
S
G
D
S
G
OUT
OUTININ
OUTINOUT
OUTININ
OUT
OUTINOUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SEC 8 OF 11
JTAG_TDO
JTAG_TDI
JTAG_TRST#
GPIO_8/SPI_DI
GPIO_11/SPI_CLK
GPIO_10/SPI_CS0
GPIO_9/SPI_DO
JTAG_TCK JTAG_TMS
LLB#
LID#
RSTBTN#
PWRBTN#
SIO_PME#
KBRDRSTIN#
A20GATE
EXT_SMI#/GPIO_32
BUF_25MHZ
BUF_SIO_CLK
SUS_CLK/GPIO_34
SLP_S5#
SLP_RMGT#
PWRGD_SB
SLP_S3#
PS_PWRGD
CPUVDD_EN
CPU_VLD
CPU_DPRSLPVR
FANCTL0/GPIO_61 FANRPM0/GPIO_60
FANCTL1/GPIO_62 FANRPM1/GPIO_63
GPIO_14/MCP_VID1
THERM_DIODE_P THERM_DIODE_N
GPIO_15/MCP_VID2
GPIO_13/MCP_VID0
PKG_TEST
TEST_MODE_EN
GPIO_1/PWRDN_OK/SPI_CS1 GPIO_6/FERR#/IGPU_GPIO6
GPIO_7/NFERR#/IGPU_GPIO7
GPIO_12/SUS_STAT#/ACCLMTR_EXT_TRIG
MII_CRS/GPIO_21/MSMB_CLK
MII_COL/GPIO_20/MSMB_DATA
GPIO_4/HDA_DOCK_EN#/PS2_MS_CLK
GPIO_3/HDA_SDATA_IN2/PS2_KB_DATA
GPIO_2/HDA_SDATA_IN1/PS2_KB_CLK
GPIO_5/HDA_DOCK_RST#/PS2_MS_DATA
HDA_SDATA_IN0
HDA_SDATA_OUT
MII_TXD0
HDA_SYNC HDA_BITCLK
HDA_RESET#
HDA_PULLDN_COMP
SPKR
MII_TXD1 MII_TXD2 MII_TXD3
MII_RXD0 MII_RXD1
MII_RXD3
MII_RXD2
MII_TXCLK
MII_RXER/GPIO_36
MII_RXDV
MII_RXCLK
MII_TXEN
MII_MDC MII_MDIO
MII_PWRDWN/GPIO_37
MII_INTR/GPIO_35
MII_RESET#
V1P1_DUAL_MACPLL
MII_COMP_GND
MII_VREF
MII_COMP_VDD
SMB_CLK0
SMB_DATA0
SMB_ALERT#/GPIO_64
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
XTALOUT
XTALIN
XTALOUT_RTC
XTALIN_RTC
V3P3_VBAT
RTC_RST#
INTRUDER#
SERIAL FLASH
SPI
VCC
HOLD*
DI
SK
CS* DO
GND
WP*
OUT
OUTINOUT
IN
3 2 1
OUT
A
B
C
D
E
F
3 2 1
REV PAGE
DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
F
C
B
A
456 3 2 18 7
28C6<> 29D7<>
24D5<> 25D5<>
46C7<
23D5< 24D5< 25D5< 26D5<
19C5>
23D5<> 26D5<>
15A4<> 39D6<>
43D1>
15B4< 28C6< 29D7< 30D7< 46C7<
37D7< 37D7<
11C3<>
11C3< 11A7< 39D6< 31A7<
19B5>
INTRUDER*
STRAP
HDA_SDOUT LPC_FRAME
DEFAULT*
00 = LPC BIOS 01 = PCI BIOS 10 = SPI BIOS CS0 * 11 = SPI BIOS CS1
NETWORKING SELECT MII_TXD0 0 = MII 1 = RGMII *
+3.3V
2
R4C12
2.7K
5% 0603_R
1
2
R4C9 R5C1
2.7K
5% 0603_R
1
+3.3V_VBAT
2
R1G12
49.9K
1% 0603_R
1
HDA_RST* HDA_SYNC
2
1
THR_R
37A6< 37A6<
11A7<> 30D7<> 31A7<>
+3.3V
2
R3B1
8.2K
5% 0402_R
1
EMPTY
2
R3A6
8.2K
5% 0402_R
1
+3.3V
2
R4D2 10K
5% 0402_R
1
SIO CLOCK SELECT HDA_SYNC 0 = 14.31818 MHZ 1 = 24 MHZ *
+3.3V_DUAL
2
R5D16
1.47K
1% 0402_R
1
2
R5D17
1.47K
R5C4
2.7K
5% 0603_R
1% 0402_R
1
SMB_MEM_DA SMB_MEM_CL
+3.3V_DUAL
2.7K
5% 0603_R
2
1
SMB_SDA SMB_SCL
11/16
Y4D1
25.000MHZ
J1G1
1 2
I170
*DEFAULT PULL BATTERY TO CLEAR TIME
1
2
50PPM
HC49_R
18PFI163
2 5%
2
J1G3
1
THR_R
RTC_R
3 2 1
NOTES=[2-3]
C5D11
0402_R C0G 50V
R1G13
49.9K
1% 0603_R
C5D2
1
27PF 27PF
0402_R C0G 50V
5%2
I169
CLEAR CMOS - J1G3
CLEAR CMOS
1-2
NORMAL
2-3*
37C7< 37A6<
C5D8
1
.1UF
0402_R X7R 16V 10%
2
37D7< 37A6<
37D8>
1
R4D5
2
5%
22
0402_R
+3.3V_DUAL
2
1
34D7<
+1.1V_DUAL
R4C10
R5C2
1 C1F21
4.7UF
0603_R X5R
6.3V
10%2
R5D5 10K
5% 0402_R
1500MA
11/27
1
0402_R
HDA_SDOUT HDA_SDIN_0
R4D4
1
34D7<
34C7>
30
1
0603_R
1
0402_R
5%
0
HDA_BITCLK
22
34D7<
L16E6
2
C4D3
2
10PF
R4D6
1
0402_R
R4D7
1
0402_R
C4D1
1
0402_R C0G
10PF
50V 5%
2
5%20402_R
C4D21 10PF
0402_R C0G 50V
5%2
+3.3V_DUAL
RGMII0_TXD<3..0>
RGMII0_TXC
RGMII0_TXCTL
RGMII0_RXCTL
34C8<
34C8<>
34A2>
34B8<
34C8<
2
FB
2
5%
0
R5C5
1
2
C16E44
4.7UF
0603_R X5R
6.3V 10%
0402_R
0402_R
C16E45
1
2.2UF
0402_R X5R
6.3V 20%
2
R4C11
0
1
0
RGMII0_INTR* RGMII0_PWRDWN*
RGMII_RESET*
25%1
2
5%
11/16
32.768KHZ
Y5D1
4
1
PLA_4P_R
20PPM
I155
12.5PF
C5D51 18PF
0402_R C0G 50V 5%
2
22
22
1
0402_R
34D8>
34C7>
C5D4
1
18PF
0402_R C0G 50V
5%2
0402_R C0G 50V 5%
1
5%
5%
R5D3
2
2
2
49.9
+3.3V_DUAL
C4D4
1
0402_R C0G
10PF
50V 5%
37A7>
43B4<
2
1%
0 1 2 3
1
0402_R
RGMII0_RXD<3..0>
RGMII0_RXC
1
0402_R
R5D12
1
0402_R
49.9
2
R5D15
49.9
1% 0402_R
1
35B8<> 35B8<>
35A8<> 35A8<>
37D8<
R5D7
2
1
R5D6
1
5%
0402_R
0
0402_R
R5D10
0
2
5%
R5D8
0
1
0402_R
0
R5D11
2
5%
0
RGMII0_MDC RGMII0_MDIO
R5B5
1
MII_COMP_3P3V
2
1%
MII_COMP_GND
V1.1V_PLL_MAC_DUAL
19B8>
19B8< 43D1>
19E3>
19E3>
HDASYNC HDABCLK HDA_SDIN_1
MCP_KB_DA MCP_MS_CK MCP_MS_DA
HDARST*
SPEAKER
HDA_PULLDN_COMP
2
R5D9
21
5%
5%
0402_R
0
RGMII0_TXC_R
2
5%
RGMII0_TXCTL_R
RGMII0_PWRDWNR*
2
5%220402_R
MII_VREF
SMB_MEM_DA_R SMB_MEM_CL_R
SMB_SDA_R SMB_SCL_R
XTALIN XTALOUT
INTRUDER*
RTC_RST*
XTALIN_RTC XTALOUT_RTC
+3.3V_VBAT
C5D7
1
4.7UF
0603_R X5R
6.3V
10%2
SPI_CS* SPI_DI
EMPTY
U5E1
HDASDOUT
BGA1437
F15 G15 L15 E15 J14
J15 K17 L17
K15 C13
A15
RGMII0_TXD0_R
RGMII0_TXD1_R
RGMII0_TXD2_R
RGMII0_TXD3_R
B24 C24 C25 D25
D24
0 1 2 3
C23 B23 E24 A24
A23
C26 C22 F23 B26 B22
D21 C21 J22 G23
J23 E28
C27 B27
T23
K19 L19
F21 G21
M23
A16 B16
B20 C20
A19 B19
A20
I140
C5D6
1
.1UF
0402_R X7R 16V
10%2
NEAR THE V3P3_VBAT BALL WITH 1 INCH
+3.3V_DUAL
2
R4C7
1
2
1
10K
5% 0402_R
SPI_WP*
R4C8 10K
5% 0402_R
U4C1
MULTI_SOURCE
SOCKETW_R
1 2 3 4
MCP7A
E19 F19
G19 J19 J18
C15 B14
C14 D13
A20GATE
K13 C18
C16 D16
SIO_PME*
C19
SIO_KBRST*
L13 M25
LIB_LID*
M24
E23
BUF_SIO_CLK_R
AE7
CPU_GTLREF1_SEL
B18
DEFAULT SETTING TO LOW
J17 H17 G17 D20 E20
C17 D17 M22
A12 B12
C12
SYSFAN_TACH
D12 L24 E16 B15 L26
L20 M20 M21
JTAG_TDO_MCP_R JTAG_TCK_MCP JTAG_TMS_MCP JTAG_TRST_MCP*
SPI_DI SPI_DO
SPI_CS* SPI_CLK
EXT_SMI* PWRBTN*
FP_RESET*
BUF0_25MHZ_R
SLP_S5* SLP_S3* PWRGD_SB PS_PWRGD
CPU_PWRGD CPUVDD_EN
CPUFAN_CNTL CPUFAN_TACH
SYSFAN_CNTL
HDMI_CEC
0402_R
JTAG_TDI_MCP
JTAG_TDO_MCP
R5D2
2
1
5%220402_R
2
R5D1 10K
5% 0402_R
19A5> 19A3<
19A5<
19A3<
39B2>
39C2>
19E2>
44B1>
46B8<
44A4>
39D2>
19E2> 39B2>
19E2>
R16D1
BUF0_25MHZ
2
1
5%
22
10C1<
47D8<
19D2> 19C2> 43D5< 16E6<
39A6< 45A4> 21A7<
46E7> 49C8<
42B4< 42A2>
42A8< 42A4>
36A8<
44D8<
32B7<
34C8<
45B2<
44D2>
49D4<
1
39C2> 19E3<
19E3<
19E3<
39D2>
C17E11 10PF
0402_R C0G 50V
EMPTY
2 5%
47D8<
39A6< 44D8< 45B2<
0402_R
FOR A01 WAR
+3.3V_DUAL
EMPTY
EXT_SMI*
LIB_LID*
SIO_PME*
BUF_SIO_CLK
2
1
R17E1
5%
22
19D3>
19D3>
0402_R
0402_R
0402_R
SLP_S5*
SLP_S3*
R4C14
2
1
5%
10K
R16E7
2
1
5%
10K
R2J5
2
1
5%
10K
EMPTY
EMPTY
1
0603_R
EMPTY
1
0603_R
EMPTY
39D6<
R9J11
0
R6J6
0
S2G1 SWT_R
1 2 4
I194
2
5%
2
5%
3
22B6>
22B4<
22B4>
22B6<>
22B4>
+3.3V_DUAL
2/4/2008
EMPTY
REMOVE FOR PRODUCTION
MCP7A_THERM_DIODE_P
B11
MCP7A_THERM_DIODE_N
C11
TESTMODE
K22 L22
MCP7A SPI CLK STRAP
3
2
EMPTY
Q17C2 2N700210% 2N70022
1
S23_R
SPI_DO|SPI_CLK
*00 = 31MHZ
01 = 42MHZ 10 = 25MHZ 11 = 1MHZ
*DEFAULT
19E3> 19E3>
SLP_S3
+3.3V_DUAL
EMPTY
2
1
R4C3 10K
5% 0402_R
EMPTY
EMPTY
Q17C1
3
S23_R
2
2
R4C5 10K
5% 0402_R
1
SPI_CLK SPI_DO
2
R4C6
1
10K
5% 0402_R
1
2
R4C2 10K
5% 0402_R
1
8
SPI_HOLD*
7 6 5
C4C61
I1478MBIT
1UF
0402_R X5R
6.3V
2
R4C4 10K
5% 0402_R
1
39A8< 39A8<
2
R5D4 1K
5% 0402_R
1
45A4>
REMOVE FOR PRODUCTION
MCP7A HDA/MII/MISC
6.0 19
02/05/2008
Wed Mar 19 16:03:00 2008
602-7R177-0000-F00
Page 20
<XR_PAGE_TITLE>
SEC 9 OF 11
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPU_VTT V1P2_CPU_VTT
V1P2_CPUCLK_VTT
V1P1_PEX_DVDD0 V1P1_PEX_DVDD0
V1P1_PEX_DVDD0 V1P1_PEX_DVDD0 V1P1_PEX_DVDD0
V1P1_PEX_DVDD0 V1P1_PEX_DVDD0
V1P1_PEX_DVDD0
V1P1_PEX_DVDD1
V1P1_PEX_DVDD1
V1P1_PEX_AVDD0
V1P1_PEX_AVDD0 V1P1_PEX_AVDD0 V1P1_PEX_AVDD0
V1P1_PEX_AVDD0
V1P1_PEX_AVDD0
V1P1_PEX_AVDD0 V1P1_PEX_AVDD0 V1P1_PEX_AVDD0
V1P1_PEX_AVDD0 V1P1_PEX_AVDD0 V1P1_PEX_AVDD0
V1P1_PEX_AVDD0
V1P1_PEX_AVDD1 V1P1_PEX_AVDD1 V1P1_PEX_AVDD1
V1P1_SATA_DVDD0 V1P1_SATA_DVDD0
V1P1_SATA_DVDD0
V1P1_SATA_DVDD0 V1P1_SATA_DVDD1
V1P1_SATA_DVDD1
V1P1_SATA_AVDD0 V1P1_SATA_AVDD0 V1P1_SATA_AVDD0
V1P1_SATA_AVDD0 V1P1_SATA_AVDD0
V1P1_SATA_AVDD0
V1P1_SATA_AVDD0
V1P1_SATA_AVDD1 V1P1_SATA_AVDD1
V1P1_SATA_AVDD1 V1P1_SATA_AVDD1
V1P1_SATA_AVDD0 V1P1_SATA_AVDD0
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD
V1P0_CORE_VDD V1P0_CORE_VDD V1P0_CORE_VDD
V1P0_CORE_VDD
V1P1_HDMI_VDD
V1P0_CORE_VDD
A
B
C
D
E
F
3 2 1
REV PAGE
DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
F
C
B
A
456 3 2 18 7
10/8
10/30
+1.1V_CORE
U5E1 BGA1437
AA16 AA17 AA18 AA19 AA20 AA21 AA23
+1.1V_CORE
C17E6
1C17E91C17E41
10UF4.7UF4.7UF
0805_R
0603_R
0603_R X5R
6.3V
10%2
1C16E34
1C16E12
1
.1UF
0402_R X7R 16V 10%
2
C16E391 .1UF
0402_R X7R 16V
210%
2
C16E531 .1UF
0402_R X7R 16V
210%
2
C16E491 .1UF
0402_R X7R 16V
C17E111 .22UF
0402_R X5R 10V 10%
.1UF
0402_R X7R 16V
10%2
.1UF
0402_R X7R 16V 10%
2
1
C17E131 .1UF
0402_R X7R 16V
2
10%
210%
1
C17E101 .22UF
0402_R X5R 10V 10%
2
C16E48
1C16E58
1UF
0402_R X5R
6.3V 10%
2
C16E2 .1UF
0402_R X7R 16V 10%
C16E55 .1UF
0402_R X7R 16V
10%2
X5R
X5R
10V
6.3V 10%
2
10%
2
+1.1V_CORE
C16E46
1
C16E1
1
1UF
1UF
0402_R
0402_R
X5R
X5R
6.3V
6.3V 10%
2
10%
2
+1.1V_CORE
C16E27
1
C16E47
1
.1UF
.1UF
0402_R
0402_R
X7R
X7R
16V
16V
10%
2
10%2
+1.1V_CORE
C16E361
C17E12
1
.1UF
.22UF
0402_R
0402_R
X7R
X5R
16V
10V
10%
2
10%
2
V1P1_HDMI_VDD
2
R16E1
10/2
0
5% 0402_R
1
AA24 AA25 AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AC23 AC24 AC25 AC26 AC27 AC28 AD21 AD23 AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AF12 AF2 AF21 AF23 AF25 AF3 AF4 AF7 AF9 AG10 AG11 AG12 AG21 AG23 AG25 AG3 AG4 AG5 AG6 AG7 AG8 AG9 AH1 AH10 AH11 AH12 AH2 AH21 AH23 AH25 AH3 AH4 AH5 AH6 AH7 AH9 U25 V25 W21 W23 W25 W26 W27 W28 Y21 Y23
T25
MCP7A
AA32 AB32 AC32 AD32 AE32 AF32 AH32 AJ32 AK31 AK32 AL31
B41 B42 C40 C41 C42 D39 D40 D41 E38 E39 E40 F37 F38 F39 G36 G37 G38 H35 H37 J34 J35 J36 K33 K34 K35 L32 L33 L34 M31 M32 M33 N31 N32 P31 P32 R32 T32 U32 V32 W32 Y32
AG32
T17 U16 U17 V19 W16 W17 W18 W19
T19 U19
AA12 AB12 AC12 AD12
M12 N12 P12 R12 T12 U12 V12 W12 Y12
M13 N13 P13
AF19 AG16 AG17 AG19
AH17 AH19
AJ12 AK12 AK13 AL12 AL13 AM11 AM12 AN11 AN12
AL14 AM13 AM14 AN14
+1.2V_VTT
V1.1V_PEX_AVDD
V1.1V_SATA_AVDD
+1.2V_VTT
C16D1
1
C16E77
1
C16E68
1
C16E7121 1UF
0402_R X5R
6.3V 10%
1UF
0402_R X5R
6.3V 10%
2
C14D31
C14D2
1
.1UF
.1UF
0402_R
0402_R
X7R
X7R
16V
16V
10%
2
10%
2
2
1
4.7UF
0603_R X5R
6.3V 10%
C14D4 .1UF
0402_R X7R 16V
10%2
2
+1.2V_VTT
1 C14D1
2
10UF
0805_R X5R 10V 10%
10UF
0805_R X5R 10V 10%
NEAR CPU SIDE
+1.1V_CORE
C17E7
1
C16E561
C16E601
C16E211
C16E15
1
.1UF
0402_R X7R 16V 10%
2
1
C16E13
1
.1UF
0402_R X7R 16V
2 10%
10%
2
C16E311 .1UF
0402_R X7R 16V 10%
2
C16E16
1
C16E81
.1UF
.1UF
0402_R
0402_R
X7R
X7R
16V
16V
10%2
2 10%
2
C16E6 .1UF
0402_R X7R 16V
.1UF
0402_R X7R 16V
1UF
0402_R X5R
6.3V 10%
210%
C16E51
C16E10
1
1UF
1UF
0402_R
0402_R
X5R
X5R
6.3V
6.3V
2 10%
+1.1V_CORE
C16E401
4.7UF
0603_R X5R
6.3V 10%
2
C16E9
1
C16E241
10UF
4.7UF
0805_R
0603_R
X5R
X5R
10V
6.3V 10%
2
2
10%
4.7UF
1UF
0603_R
0402_R
X5R
X5R
6.3V
6.3V
10%2
10%2
+1.1V_CORE
L16E230
21
C16E11
1
C16E71
10UF
4.7UF
0805_R
0603_R
X5R
X5R
10V
6.3V
2 10%
10%
2210%
+1.1V_CORE
L16E3
2
1
FB
0603_R305000MA
FB0603_R5000MA
I73
MCP7A CORE/VTT POWER
6.0602-7R177-0000-F00
20
Wed Jan 16 11:22:41 2008
Page 21
SEC 10 OF 11
V1P0_VDD_AUXC
V1P0_VDD_AUXC V1P0_VDD_AUXC
V1P0_DUAL_RMGT V1P0_DUAL_RMGT
V3P3_DUAL V3P3_DUAL
V3P3_DUAL V3P3_DUAL
V3P3_DUAL_HDA
V3P3_DUAL_USB V3P3_DUAL_USB
V3P3_DUAL_USB
V3P3_DUAL_USB
V3P3_DUAL_HDA
V3P3_DUAL_RMGT V3P3_DUAL_RMGT
V3P3 V3P3
V3P3
V3P3 V3P3 V3P3
V3P3
V3P3_TVDAC_VDD
V3P3_RGBDAC_VDD
V3P3
V1P8_IFPA_VDD V1P8_IFPB_VDD
V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP V1P8_MEM_VDDP V1P8_MEM_VDDP V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
V1P8_MEM_VDDP
D
S
D
S
G
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
44D2> 32B7< 19D3< 16E6<
1
.1UF
0402_R X7R 16V
210%2
.1UF
0402_R X7R 16V 10%
C16E591
C16E23
1
.1UF
0402_R X7R 16V
2 10%
10%2
PREVENTION CIRCUIT
.1UF
0402_R X7R 16V
BACKDRIVE
.1UF
0402_R X7R 16V
C16E501
C16E52
1
C16E62
PS_PWRGD
22 10%
C16E291 .1UF
0402_R X7R 16V 10%
Q5D1
C16E671 .1UF
0402_R X7R 16V
10%2
1
3
2
C16E38
1
.1UF
0402_R X7R 16V
2 10%
1
0402_R
2N7002
S23_R
+1.8V_SUS
C16E43
1
.1UF
0402_R X7R 16V
10%2
+1.8V_SUS
C16E72
1
4.7UF
0603_R X5R
6.3V
10%2
1
R5D13
2
5%
10K
+3.3V
3
2
Q5D2 SI2305DS S23_R
1
2 10%
+1.8V_SUS
C16E54
4.7UF
0603_R X5R
6.3V
U5E1 BGA1437
AL30 AM15 AM17 AM19 AM21 AM23 AM25 AM27 AM29 AM31 AN16 AN18 AN20 AN22 AN24 AP16 AP18 AP20 AP22 AP24 AR16 AR20 AR24 AT17 AT21 AU16 AU18 AU20 AU22 AU24 AV16 AV20 AV24 AW15 AW19 AW24 AW27 AY17 AY18 AY25 AY26 AY29 BC17 BC25 BC29
I501
V3P3_HDMI_VDD
C16E511 .1UF
0402_R X7R 16V 10%
2
MCP7A
Wed Jan 16 11:22:43 2008
T21 U21 V21
U23 V23
G18 H19 J20 K20
G26 H27 J28 K28
J16 K16
J24 K24
AA8 AB10 AB11 AD10
AD9
AE8
Y10
Y9
K32
V3P3_RGBDAC_VDD
J32
M27
V1P8_IFPB_VDD
M26
C16E351 .1UF
0402_R X7R 16V
2
.1UF
0402_R X7R 16V 10%
2
C16E41C16E3 .1UF
0402_R X7R 16V 10%
1
2
V3.3V_TVRGB_DAC
R16E6
1
0402_R
10/2
2
1
+1.1V_DUAL
C16E33
1
4.7UF
0603_R X5R
6.3V
2 10%10%
C4E3
1
.1UF
0402_R X7R 16V
10%2
2
5%
0
R16E2 0
5% 0402_R
2
1
2
10/2
C4E41 .1UF
0402_R X7R 16V 10%
C16E76 .1UF
0402_R X7R 16V 10%
+3.3V
2 10%
C17E81
4.7UF
0603_R X5R
6.3V
C16E74
1
.1UF
0402_R X7R 16V 10%
2
+1.1V_DUAL
C16E411 .1UF
0402_R X7R 16V
2
10%
+3.3V_DUAL
C16E70
1
.1UF
0402_R X7R 16V 10%
2
C16E75
1
4.7UF
0603_R X5R
6.3V 10%
2
C16E301 .1UF
0402_R X7R 16V 10%
2
C16E37
1
.1UF
0402_R X7R 16V
10%2
+3.3V
L16E10
30
2
1
FB
0603_R
5000MA
MCP7A MEM POWER
602-7R177-0000-F00
+3.3V_DUAL
C16E32
1
4.7UF
0603_R X5R
6.3V
10%2
C16E26
1
.1UF
0402_R X7R 16V 10%
2
+3.3V_DUAL
C16E181
4.7UF
0603_R X5R
6.3V
2 10%
6.0 21
Page 22
<XR_PAGE_TITLE>
OUTINOUT
2101
9
SEC 11 OF 11
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
OUT
BI
A
B
C
D
E
F
3 2 1
REV PAGE
DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
F
C
B
A
456 3 2 18 7
M9M7M6
M10
M11
M34
M35
M37
M38
M5
P33
P11
P10N8N39
AY6
AY41
AY38
AY37
AY34
AY33
AY30
BC12
BC21
BC33
BC37
BC41
C2
D15
D14
D10
BC9
BC5
BA4
BA1
AY9
D18
D19
D22
D23
D26
D30
D34
F12
E33
E29
E25
E21
E17
E13D6D37
F20
F24
F28
G10F8F32
G12
G14
G16
G20
G22
G24
G28
G30
G32
G6
H11
G43
G40G4G34
H15
H23
H31
H34
K10J8J12
G8
K12
K18
K26
K7
L43AH37
L40
L35
L12
K40K4K37
L5
K8
U8
P34
P7
T10R5R43
R40
R36
P40P4P37
T11
T18
T20
T22
T24
T26
T33
T34
T35
T37
T38
T9T7T6
U20
U22
U24
U26
U39
U4
V10
V11
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V34
Y7
Y6
Y38
Y37
Y35
Y34
Y33
Y28
Y27
Y25
Y24
Y22
Y20
Y19
Y18
Y17
Y16
Y11W5W43
W40
W36
W24
W22
W20V7V40V4V37
MCP7A
AY10
AY13
AY14
AY21
I260
AY22
U5E1
BGA1437
AA39
AA22
AA4
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
AB25
AB26
AB27
AB28
AB33
AB34
AB37
AB4
AB40
AB7
AC22
AC36
AC40
AC5
AD16
AD17
AD18
AD19
AD20
AD22
AD24
AD25
AD26
AD27
AD28
AD33 F16
AD34
AD35
AD37
AD38
AD6
AD7
AE20
AE22
AE24
AE39
AE4
AF16
AF17
AF18
AF20
AF22
AF24
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG24
AG26
AG36
AG40
AH16
AH18
AH20
AH22
AH24
AH26
AH33
AH34
AH35
AH38
AJ39
AJ8
AK10
AK11
AK33
AK34
AK37
AK4
AK40
AK7
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM28
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AN26
AN28
AN30
AN39
AN4
AN8
AP10
AP12
AP14
AP26 U18
AP28
AP30
AP32
AP33
AP34
AP36
AP37
AP4
AP40
AP7
AR12
AR28
AR30
AR32
AR36
AR40
AR43
AT10
AT13
AT25
AT29
AT33
AT6
AT7
AT9
AU1
AU10
AU12
AU14
AU26
AU28
AU32
AU36
AU38
AU4
AV12
AV28
AV32
AV36
AV4
AV40 Y26
AV7
AW11
AW20
AW23
AW31
AW35
AW43
REMOVE FOR PRODUCTION
JTAG CONNECTOR LAYOUT: PLACE HEADERS CLOSE TOGETHER
11/1
19F1<
19F1<
JTAG_TMS_MCP JTAG_TDI_MCP
EMPTY
+3.3V_DUAL
2
1
R1B12 15K
5% 0603_R
2
R1B13 15K
5% 0603_R
1
EMPTY
+5V_DUAL
EMPTYEMPTY
J1B3 SMT_R
I261
2 4 6 8
10
2
R1B7 0
5% 0603_R
1
JTAG_TRST_M
0402_R
R1B6
1
0
JTAG_TCK_MCP JTAG_TDO_MCP JTAG_TRST_MCP*
2
5%
2
1
R1B11 15K
5% 0603_R
EMPTY
19F1< 19F1> 19F1<
2
R1C1 0
5% 0603_R
1
1 3 5 7 9
HDR2X5
MCP7A GND & JTAG HDR
6.0 22
Tue Mar 18 12:14:12 2008
602-7R177-0000-F00
Page 23
OUTBIINININININBIINININININININININBIBIININ
1.8V
A1
A0
A6
A5
A4
A3A2A7A9A8
A11
A10/AP
A12
A15
A14
A13
DM2/DQS11
DM1/DQS10
DM0/DQS9
DM3/DQS12
DM4/DQS13
DM5/DQS14
DQS0
DQS1
DQS3
DQS4
DQS2
DM8/DQS17
DM7/DQS16
DM6/DQS15
DQS5
DQS2*
DQS1*
DQS0*
DQS4*
DQS5*
DQS6
DQS7
NC/DQS8
DQS3*
NC/CB5
NC/CB4
NC/CB3
NC/CB2
NC/CB1
NC/CB0
DQS6*
NC/DQS8*
DQS7*
NC/CB6
NC
NC/DQS12*
NC/DQS13*
NC/DQS14*
NC/DQS11*
NC/DQS9*
NC/CB7
NC/DQS10*
NC/DQS15*
CK0
CK1
CK2
NC/DQS16*
NC/DQS17*
CK0*
CK1*
CK2*
WE*
S1*
S0*
RAS*
CAS*
CKE0
CKE1
TEST
PAR_IN
A16/BA2
ODT0
ODT1
BA0
BA1
ERR_OUT*
SA1
SA0
SA2
SDA
SCL
RESET*
VDDSPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ31
DQ30
DQ29
DQ28
DQ32
DQ37
DQ33
DQ34
DQ35
DQ36
DQ38
DQ39
DQ40
DQ41
DQ42
DQ44
DQ43
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ62
DQ59
DQ60
DQ61
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
DIMM 1
26D5<
25D5< 24D5<
25D5<> 26D5<>
24D5<>
19C8>
19C8>
CPU SKT
MCP7A
DATA 1 DATA 1 DATA 0 DATA 0
14D7<>
24C8<>
24C8<>
24C8<
14D7<>
14C7>
14C7> 24C8< 27B5<
MEM_1_DQS<7..0>* MEM_1_DQS<7..0> MEM_1_DQM<7..0>
MEM_1_ADD<14..0>
DIMM 3 DIMM 0 DIMM 2
0
183
188
63
182
61
10/15
ADDR 1/CNTL 1ADIMM 1 ADDR 1/CNTL 1B ADDR 0/CNTL 0A ADDR 0/CNTL 0B
14
13
12
11
10
987
6
54312
57
70
58
60
180
179
177
176
174
196
173
013
2
146
134
125
456
155
202
211
223
7
232
164
765
4
321
0
7
37
28
16
84
93
114
105
46
0
6
15
27A5< 24D5<
27A5< 27A5< 27A5<
4
321
92
83
36
27
24C5< 24C5<
104
27B5<
27A5< 27A5<
765
45
113
14B8>
14B7>
14B8> 14B7>
14A3<> 14A3<> 14A3<> 24C5<
14A7> 14A7> 14A7> 14A7> 14A7> 14B7>
48
43
42
49
161
SMB_MEM_CL SMB_MEM_DA
MEM_1A_ODT<1..0> MEM_1_BA<2..0> MEM_1A_CKE<1..0>
MEM_1A_CS<1..0>*
MEM_1_CAS* MEM_1_RAS* MEM_1_WE*
MEM_1A_CLK1*
MEM_1A_CLK1
MEM_1A_CLK2*
MEM_1A_CLK2
MEM_1A_CLK0*
MEM_1A_CLK0
19
135
126
168
167
162
147
156
203
212
224
233
165
137
185
220
138
186
221
73
192
74
0
193
1
76
0
52
1
171
71
201
54
190
1
0
195
77
102
+1.8V_SUS
2
1
2
1
+1.8V_SUS
+3.3V
186855
239
101
240
119
120
238
53
SM_MEM BUS ADDRESS DIMM 0 DIMM 1 DIMM 2 DIMM 3
R8G8 121
1% 0402_R
DIMM_VREF_CH1
R8G9 121
1% 0402_R
696467
59
172
184
178
187
189
1
197
1010 000 1010 001 1010 010 1010 011
C8G3 .1UF
0402_R X7R 16V
10%2
62
56
51
24C2<
181
191
1
194
787275
175
170
+1.8V_SUS
SOCKET_R
GRAY
J8G1
C6G2
1
10UF
0805_R X5R 10V 10%
2
DIMM240
4
C7J1
1
1UF
0402_R X5R
6.3V
10%2
9
122
10
128
123
C5G1
1
1UF
0402_R X5R
6.3V 10%
2
21
13
12
129
98765432130
10
131
22
12
11
C7H2
1
1UF
0402_R X5R
6.3V 10%
2
140
132
14
13
24
141
17
16
15
1
2
25
C6G1 .1UF
0402_R X7R 16V 10%
31
30
19
18
149
144
143
22
21
20
33
150
24
23
C5J51 .1UF
0402_R X7R 16V 10%
2
40
39
34
27
26
25
158
153
152
30
29
28
C6J6
1
.1UF
0402_R X7R 16V 10%
2
87
86
81
80
159
35
34
33
32
31
C7H321 .01UF
0402_R X7R 16V 10%
89
206
205
200
199
40
39
38
37
36
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
60
59
58
57
56
55
54
53
52
51
50
49
48
47
464445
43
42
41
Wed Jan 16 11:22:45 2008
11
852
236
235
230
63
62
61
MEM_1_DATA<63..0>
14
17
20
23
26
66
65
50
47
44
41
38
35
32
29
79
82
88
85
14D3<>
91
94
100
97
24A3<>
106
103
112
109
133
130
127
124
121
118
115
DDR2 DIMM 1
136
142
139
145
148
154
151
157
160
166
163
169
201
198
204
207
210
213
216
219
222
225
6.0602-7R177-0000-F00
228
231
234
I171
237
23
Page 24
INBIINBIINININININININININININININBIINBIIN
1.8V
A1
A0
A6
A5
A4
A3A2A7A9A8
A11
A10/AP
A12
A15
A14
A13
DM2/DQS11
DM1/DQS10
DM0/DQS9
DM3/DQS12
DM4/DQS13
DM5/DQS14
DQS0
DQS1
DQS3
DQS4
DQS2
DM8/DQS17
DM7/DQS16
DM6/DQS15
DQS5
DQS2*
DQS1*
DQS0*
DQS4*
DQS5*
DQS6
DQS7
NC/DQS8
DQS3*
NC/CB5
NC/CB4
NC/CB3
NC/CB2
NC/CB1
NC/CB0
DQS6*
NC/DQS8*
DQS7*
NC/CB6
NC
NC/DQS12*
NC/DQS13*
NC/DQS14*
NC/DQS11*
NC/DQS9*
NC/CB7
NC/DQS10*
NC/DQS15*
CK0
CK1
CK2
NC/DQS16*
NC/DQS17*
CK0*
CK1*
CK2*
WE*
S1*
S0*
RAS*
CAS*
CKE0
CKE1
TEST
PAR_IN
A16/BA2
ODT0
ODT1
BA0
BA1
ERR_OUT*
SA1
SA0
SA2
SDA
SCL
RESET*
VDDSPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ31
DQ30
DQ29
DQ28
DQ32
DQ37
DQ33
DQ34
DQ35
DQ36
DQ38
DQ39
DQ40
DQ41
DQ42
DQ44
DQ43
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ62
DQ59
DQ60
DQ61
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
DIMM 3
SMB_MEM_CL SMB_MEM_DA
MEM_1B_ODT<1..0> MEM_1_BA<2..0> MEM_1B_CKE<1..0>
MEM_1B_CS<1..0>* MEM_1_CAS*
MEM_1_RAS* MEM_1_WE*
MEM_1B_CLK1* MEM_1B_CLK1 MEM_1B_CLK2* MEM_1B_CLK2 MEM_1B_CLK0* MEM_1B_CLK0
19
147
126
135
168
162
167
156
203
212
224
233
165
185
137
220
186
138
221
73
192
74
0
193
1
0
201
1
0
1
+1.8V_SUS
+3.3V
18
55
68
77
54
52
171
71
190
195
102
239
240
101
119
120
238
76
27B3<
23D5< 27A5<
27A3< 27A3<
765
45
113
19C8>
19C8>
14A8>
14B7>
14A8> 14A7>
14A3<> 14A3<> 14A3<>
14A7> 14A7> 14A7> 14A7> 14A7> 14A7>
48
43
42
49
161
25D5< 23D5<
26D5<
46
0
6
25D5<> 23D5<>
23C5<
27A5<
23C5<
27A5<
23C5<
27A5<
423
1
92
83
36
27
15
104
26D5<>
MCP7A
DATA 1 DATA 1 DATA 0 DATA 0
14D7<>
23C8<>
27B5<
23C8<>
23C8<
23C8< 14C7>
14D7<>
14C7>
CPU SKT
DIMM 1 DIMM 3 DIMM 0 DIMM 2
MEM_1_DQS<7..0>* MEM_1_DQS<7..0> MEM_1_DQM<7..0>
MEM_1_ADD<14..0>
183
188
10/15
ADDR 1/CNTL 1A ADDR 1/CNTL 1B ADDR 0/CNTL 0A ADDR 0/CNTL 0B
37
84
93
105
76543
114
2
1
0
155
202
211
223
76543
232
164
7
28
16
2
1
0
14
13
12
11
10
9
61
60
180
58
87654
179
177
70
57
176
196
174
173
125
134
146
3
210
63
182
SM_MEM BUS ADDRESS DIMM 0 DIMM 1 DIMM 2 DIMM 3
23C1>
67
645359
69
172
DIMM_VREF_CH1
19751189
187
184
178
1010 000 1010 001 1010 010 1010 011
62
56
C8G21 .1UF
0402_R X7R 16V 10%
2
787275
191
181
170
175
1
194
SOCKET_R
BLACK
J8H1
DIMM240
9
4
3
0
122
10
128
123
13
12
129
21
987654321
10
131
22
12
11
140
132
14
13
24
141
17
16
15
25
31
30
19
18
149
144
143
22
21
20
34
33
150
25
24
23
152
40
39
28
27
26
80
159
158
153
32
31
30
29
200
199
87
86
81
37
36
35
34
33
205
38
206
39
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
Wed Jan 16 11:22:47 2008
235
230
229
117
62
61
60
59
23
20
17
14
11
8
5
2
236
63
MEM_1_DATA<63..0>
26
66
65
50
47
44
41
38
35
32
29
79
82
85
88
91
94
100
97
23A3<> 14D3<>
106
103
112
109
151
148
145
142
139
136
133
130
127
124
121
118
115
DDR2 DIMM 3
602-7R177-0000-F00
154
157
160
163
166
169
198
201
204
207
210
213
228
225
222
219
216
6.0 24
231
234
I162
237
Page 25
OUTBIININININININININININININININBIBIININBI
1.8V
A1
A0
A6
A5
A4
A3A2A7A9A8
A11
A10/AP
A12
A15
A14
A13
DM2/DQS11
DM1/DQS10
DM0/DQS9
DM3/DQS12
DM4/DQS13
DM5/DQS14
DQS0
DQS1
DQS3
DQS4
DQS2
DM8/DQS17
DM7/DQS16
DM6/DQS15
DQS5
DQS2*
DQS1*
DQS0*
DQS4*
DQS5*
DQS6
DQS7
NC/DQS8
DQS3*
NC/CB5
NC/CB4
NC/CB3
NC/CB2
NC/CB1
NC/CB0
DQS6*
NC/DQS8*
DQS7*
NC/CB6
NC
NC/DQS12*
NC/DQS13*
NC/DQS14*
NC/DQS11*
NC/DQS9*
NC/CB7
NC/DQS10*
NC/DQS15*
CK0
CK1
CK2
NC/DQS16*
NC/DQS17*
CK0*
CK1*
CK2*
WE*
S1*
S0*
RAS*
CAS*
CKE0
CKE1
TEST
PAR_IN
A16/BA2
ODT0
ODT1
BA0
BA1
ERR_OUT*
SA1
SA0
SA2
SDA
SCL
RESET*
VDDSPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ31
DQ30
DQ29
DQ28
DQ32
DQ37
DQ33
DQ34
DQ35
DQ36
DQ38
DQ39
DQ40
DQ41
DQ42
DQ44
DQ43
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ62
DQ59
DQ60
DQ61
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
SM_MEM BUS ADDRESS
DIMM 0
CPU SKT
MCP7A
10/15
DATA 1 DATA 1 DATA 0 DATA 0
DIMM 1 DIMM 0
DIMM 2
ADDR 1/CNTL 1A ADDR 1/CNTL 1BDIMM 3 ADDR 0/CNTL 0A ADDR 0/CNTL 0B
26D5<>
26D5<
24D5<>
27A8<
27A8< 27A8< 27A8<
27B8<
26D5<
27A8< 27A8<
26C5< 26C5< 26C5<
19C8> 23D5<>
13B8>
13B7>
13B8> 13B7>
13A3<> 13A3<> 13A3<>
13A7> 13A7> 13A7> 13A7> 13B7> 13B7>
19C8>
23D5<
24D5<
SMB_MEM_CL SMB_MEM_DA
MEM_0A_ODT<1..0> MEM_0_BA<2..0> MEM_0A_CKE<1..0>
MEM_0A_CS<1..0>* MEM_0_CAS*
MEM_0_RAS* MEM_0_WE*
MEM_0A_CLK1*
MEM_0A_CLK1
MEM_0A_CLK2*
MEM_0A_CLK2
MEM_0A_CLK0*
MEM_0A_CLK0
1
0
120
1
0
1
0
+1.8V_SUS
2
R9H1 121
1% 0402_R
1
2
R8H1 121
1% 0402_R
1
DIMM 0 DIMM 1 DIMM 2 DIMM 3
DIMM_VREF_CH0
1010 000 1010 001 1010 010 1010 011
47B4< 26C2<
13D7<> 26C8<>
26C8<> 13D7<>
13C7>
26C8<
13C7>
26C8<
27B8<
MEM_0_DQS<7..0>*
MEM_0_DQS<7..0>
MEM_0_DQM<7..0> MEM_0_ADD<14..0>
188
201
63
183
4613
182
60
18058179
10
98765
70
177
11
57
12
176
14
13
174
196
173
0
125
134
146
155
202
211
6754321
223
232
164
1
194
36
83
92
104
7654321
113
45
42
43
48
49
161
162
167
168
19
126
147
135
156
203
212
224
233
165
185
137
220
186
138
221
73
192
74
193
76
52
171
71
54
190
195
77
102
68
55
18
239
240
101
120
119
+1.8V_SUS
+3.3V
238
53
59
64
67
69
178
172
184
187
197
189
1
2
C8H3 .1UF
0402_R X7R 16V 10%
51
56
62
72
75
78
170
175
181
191
0
378493
7654321
105
114
46
6
27
15
0
7
28
16
DIMM240
J8H2
GRAY
SOCKET_R
349
10
122
123
128
129
12
13
2122131
140
132
1412425
30
31
143
144
149
150
343940
33
152
153
158
1598081
86
199
200
205
89
206
909596
208
214
209
2159899
107
108
217
218
227
226
110
111
116
117
229
230
235
236
234
231
228
225
222
219
216
213
210
207
204
201
198
169
166
163
160
157
154
151
148
145
142
139
136
133
130
127
124
121
118
115
112
109
106
103
100
97
94
91
88
85
82
79
66
65
50
47
44
41
38
35
26
232032
29
17
14
11
852
I163
237
201
9876543
10
12
11
14
13
17
16
15
19
18
22
21
20
25
24
23
27
26
32
31
302829
37
368735
34
33
38
39
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
Wed Jan 16 11:22:48 2008
62
61
60
59
63
MEM_0_DATA<63..0>
26A3<> 13D3<>
DDR2 DIMM 0
256.0602-7R177-0000-F00
Page 26
INININBIININININININININININININBIBIBIININ
1.8V
A1
A0
A6
A5
A4
A3A2A7A9A8
A11
A10/AP
A12
A15
A14
A13
DM2/DQS11
DM1/DQS10
DM0/DQS9
DM3/DQS12
DM4/DQS13
DM5/DQS14
DQS0
DQS1
DQS3
DQS4
DQS2
DM8/DQS17
DM7/DQS16
DM6/DQS15
DQS5
DQS2*
DQS1*
DQS0*
DQS4*
DQS5*
DQS6
DQS7
NC/DQS8
DQS3*
NC/CB5
NC/CB4
NC/CB3
NC/CB2
NC/CB1
NC/CB0
DQS6*
NC/DQS8*
DQS7*
NC/CB6
NC
NC/DQS12*
NC/DQS13*
NC/DQS14*
NC/DQS11*
NC/DQS9*
NC/CB7
NC/DQS10*
NC/DQS15*
CK0
CK1
CK2
NC/DQS16*
NC/DQS17*
CK0*
CK1*
CK2*
WE*
S1*
S0*
RAS*
CAS*
CKE0
CKE1
TEST
PAR_IN
A16/BA2
ODT0
ODT1
BA0
BA1
ERR_OUT*
SA1
SA0
SA2
SDA
SCL
RESET*
VDDSPD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VREF
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ8
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ31
DQ30
DQ29
DQ28
DQ32
DQ37
DQ33
DQ34
DQ35
DQ36
DQ38
DQ39
DQ40
DQ41
DQ42
DQ44
DQ43
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ62
DQ59
DQ60
DQ61
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
DIMM 2
SMB_MEM_CL SMB_MEM_DA
MEM_0B_ODT<1..0> MEM_0_BA<2..0> MEM_0B_CKE<1..0>
MEM_0B_CS<1..0>*
MEM_0_CAS* MEM_0_RAS* MEM_0_WE*
MEM_0B_CLK1* MEM_0B_CLK1 MEM_0B_CLK2* MEM_0B_CLK2 MEM_0B_CLK0* MEM_0B_CLK0
19
147
135
126
168
167
162
156
203
212
224
233
165
185
137
220
186
138
221
73
192
74
0
193
0
1
1
2
0
1
0
1
47B4<
+1.8V_SUS
+3.3V
18
55
68
77
171
71
190
54
195
102
239
240
101
119
120
238
76
52
27C3<
25D5<
27C3< 27B3<
45
113
19C8> 23D5<
19C8>
13A8>
13B7>
13A8> 13A7>
13A3<> 13A3<> 13A3<>
13A7> 13A7> 13A7> 13A7> 13A7> 13A7>
48
43
42
49
161
24D5<
25D5<
25D5<> 24D5<>
MCP7A
DATA 1 DATA 1 DATA 0 DATA 0
13D7<>
25C8<>
27B8<
25C8<>
25C8<
25B8<
13D7<>
13C7>
13C7>
CPU SKT
DIMM 1 DIMM 3 DIMM 0 DIMM 2
MEM_0_DQS<7..0>* MEM_0_DQS<7..0> MEM_0_DQM<7..0>
MEM_0_ADD<14..0>
183
188
10/15
ADDR 1/CNTL 1A ADDR 1/CNTL 1B ADDR 0/CNTL 0A ADDR 0/CNTL 0B
0
37
84
93
105
76543
114
46
6
15
201
7
346
5
201
14
13
12
11
10
9
61
60
180
58
87654
179
177
70
57
176
196
174
173
125
134
146
155
202
211
223
232
164
7
28
16
3
210
63
182
27
27A8<
27A8< 27A8< 27A8<
83
36
92
6754312
104
23D5<>
25C5< 25C5< 25C5<
SM_MEM BUS ADDRESS DIMM 0 DIMM 1 DIMM 2 DIMM 3
25C1>
67
69
596453
172
DIMM_VREF_CH0
197
189
187
178
184
1010 000 1010 001 1010 010 1010 011
75
72
62
56
51
78
1
C8H2 .1UF
0402_R X7R 16V
10%2
170
175
181
191
1
194
SOCKET_R
BLACK
J8J1
DIMM240
943
231
0
122
10
128
123
13
12
129
78654
22
21
132
131
121311910
141
140
15
14
30
25
24
16
144
143
31
2021191718
3324150
149
22
23
40
39
34
25
26
158
153
152
3031292728
87
863481
80
159
32
33
89
206
205
200
199
3839373536
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
605859
575556
4344424041
4849474546
5354525051
Wed Jan 16 11:22:49 2008
14
11
8
5292
236
235
230
636162
MEM_0_DATA<63..0>
17
20
23
26
66
65
50
47
44
41
38
35
32
79
82
85
88
91
94
100
97
25A3<> 13D3<>
106
103
112
109
151
148
145
142
139
136
133
130
127
124
121
118
115
DDR2 DIMM 2
602-7R177-0000-F00
154
157
160
163
166
169
198
201
204
207
210
213
228
225
222
219
216
6.0 26
231
234
I13
237
Page 27
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
INININININININININININININININININININININ
IN
PLACE NEAR ADDR/CTRL TRACES
+MEM_VTTV
1 C6J3
1
C6J1
12C6H2
1
.1UF
.1UF
0402_R
0402_R
X7R
X7R
16V
16V
10%
2
2
1
C7H1 .1UF
0402_R X7R 16V
2
10%
1 C6H4
.1UF
0402_R X7R 16V
2
10%
1
C6J11 .1UF
0402_R X7R 16V
2
10%
25B8<
10%
1 C6J15
.1UF
0402_R X7R 16V
10%2
1 C6H8 1
.1UF
0402_R X7R 16V
10%2
1 C6H6
.1UF
0402_R X7R 16V
10%2
13C7>
+MEM_VTTV
+MEM_VTTV
+MEM_VTTV
26C8<
.1UF
0402_R X7R 16V 10%
1 C5H2
.1UF
0402_R X7R 16V
2 10%
C5H6 1 .1UF
0402_R X7R 16V
2
10%
12C5J9
.1UF
0402_R X7R 16V 10%
C5H3 .1UF
0402_R X7R 16V
2 10%
1
2 10%
2
1 C6J18
2
25D5<
13B8>
26D5<
25D5<
13B7>
25D5<
13B8>
25D5<
13B7>
26C5<
25C5<
13A3<>
26C5<
25C5<
13A3<>
26C5<
25C5<
13A3<>
+1.8V_SUS
+1.8V_SUS
C5J12 .1UF
0402_R X7R 16V
+1.8V_SUS
C6J9 .1UF
0402_R X7R 16V 10%
+1.8V_SUS
.1UF
0402_R X7R 16V 10%
MEM_0_ADD<14..0>
MEM_0A_ODT<1..0>
MEM_0_BA<2..0>
MEM_0A_CKE<1..0>
MEM_0A_CS<1..0>*
MEM_0_CAS*
MEM_0_RAS*
MEM_0_WE*
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
0
1
2
0
1
0
1
0
1
RP6J2
1
47
RP6J3
3
47
RP6J3
4
47
RP6J3
2
47
RP6J3
1
47
RP6J4
3
47
RP6J4
4
47
RP6J4
1
47
RP6J4
2
47
RP6J5
4
47
RP6J2
2
47
RP6J5
3
47
RP6J5
2
47
RP5J1
1
47
RP6J6
4
47
RP5J2
2
47
RP5J1
4
47
RP6J5
1 8
47
RP6J2
4
47
RP6J2
3
47
RP6J6
3
47
R7J1
1
0402_R
RP6J1
2
47
RP5J1
2
47
RP5J2
1
47
RP6J1
1
47
RP6J1
3
47
8
6
5
7
8
6
5
8
7
C6J4
2
1
0402_R X7R
.1UF
16V
C5H1
.1UF
C6J8
.1UF
C5H5
.1UF
C6H3
.1UF
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
10%
C6H7
2
.1UF
2
2
2
2
5
7
6
7
8
5
7
C6H1
2
1
0402_R X7R
.1UF
16V 10%
C5J7
2
1
0402_R X7R
.1UF
16V 10%
C5H4
2
1
0402_R X7R
.1UF
16V 10%
C5J11
2
1
0402_R X7R
.1UF
16V 10%
24C8< 23C8<
14C7>
MEM_1_ADD<14..0>
5
23D5<
14B8>
MEM_1A_ODT<1..0>
5
6
23D5< 24D5<
14B7>
MEM_1_BA<2..0>
6
2
5%
47
7
7
8
8
6
23D5<
23D5<
23C5< 24C5<
23C5< 24C5<
23C5< 24C5<
14B8>
14B7>
14A3<>
14A3<>
14A3<>
MEM_1A_CKE<1..0>
MEM_1A_CS<1..0>*
MEM_1_CAS*
MEM_1_RAS*
MEM_1_WE*
Wed Jan 16 11:22:51 2008
RP6H2
0
1
8
47
RP6H3
1
4
5
47
RP6H3
2
3
6
47
RP6H3
3
2
7
47
RP6H3
4
1
8
47
RP6H4
5
3
6
47
RP6H4
6
4
5
47
RP6H4
7
1
8
47
RP6H4
8
2
7
47
RP6H5
9
4
5
47
RP6H2
10
3
6
47
RP6H5
11
3
6
47
RP6H5
12
2
7
47
RP5H2
13
4
5
47
RP6H6
14
4
5
47
RP5H2
0
3
6
47
RP5H1
1
1
8
47
RP6H2
0
4
5
47
RP6H2
1
2
7
47
RP6H5
2
1
8
47
RP6H6
0
3
6
47
RP6H6
1
1
8
47
RP6H1
0
3
6
47
RP5H1
1
2
7
47
RP5H2
2
7
47
RP6H1
1
8
47
RP6H1
4
5
47
2
2
C6J16
.1UF
C6J13
2
.1UF
C6H9
2
.1UF
C6H5
2
.1UF
C6J2
2
.1UF
C7J2
.1UF
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
1
0402_R X7R 16V 10%
26D5< 13A8>
26D5<
13A8>
26D5<
13A7>
24D5<
14A8>
24D5<
14A8>
14A7> 24D5<
MEM_0B_ODT<1..0>
MEM_0B_CKE<1..0>
MEM_0B_CS<1..0>*
MEM_1B_ODT<1..0>
MEM_1B_CKE<1..0>
MEM_1B_CS<1..0>*
0
1
0
1
0
1
0
1
0
1
0
1
RP5J2
3
47
RP5J1
3
47
RP6J6
2
47
RP6J6
1
47
RP6J1
4
47
RP5J2
4
47
RP5H2
1
47
RP5H1
4
47
RP6H6
2
47
1
0402_R
RP6H1
2
47
RP5H1
3
47
R6H1
6
6
7
8
5
5
8
5
7
2
5%
47
7
6
+MEM_VTTV
DDR TERMINATION
602-7R177-0000-F00 6.0 27
Page 28
INININ
OUT
OUT
X1 CONNECTOR
TDO
TDI
PRSNT1*
+12V +12V
TCK
GND
TMS
PERP0 PERN0
GND
+3.3V
GND
REFCLK+
+3.3V
REFCLK-
GND
PERST*
+12V GND SMCLK SMDAT GND
+12V
+12V
+3.3V
PETN0
PETP0
TRST* +3.3V_AUX WAKE*
RSVD GND
GND
PRSNT2*
GND
INBIOUTININ
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
SLOT 7
J4B1
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
CONN_R
I99
PCI_EXPRESS_X1
15U
A1 A2 A3 A4 A5 A6 A7 A8
A9 A10 A11
A12 A13 A14 A15 A16 A17 A18
1
0402_R X7R 16V 10%
PE2_TX
PE2_TX*
+12V+3.3V
+3.3V_DUAL
C4C5
2
.1UF
SMB_SCL SMB_SDA
R4B1
1
0402_R
10K
1
0402_R X7R 16V 10%
PE2_TRST*
2
5%
C4C3
2
.1UF
46C7< 39D6<>
46C7<
31A7<>
30D7<>
30D8> 29D8>
31A7< 30D7<
39D6<
29D7<>
29D7<
16C6<
15A4<> 19C8>
16B6>
16E6> 16E6>
16C6<
11A7<>
11C3<>
PE_WAKE*
PE2_TXC PE2_TXC*
PE2_PRESENT*
11A7<
11C3<
15B4<
19C8>
+12V
+3.3V
PE2_TCK PE2_TDI TP_PE2_TDO PE2_TMS
PE_RESET*
PE2_REFCLK PE2_REFCLK*
PE2_RX PE2_RX*
+3.3V
2
1
R4B3
5% 0402_R
+3.3V
2
1
R4C1 10K10K
5% 0402_R
1
0402_R
R4B2
10K
16E4>
16D6> 16D6>
16D6> 16D6>
2
5%
30D2< 29D2<
SLOT DECOUPLING
+12V
C4B1
1
2
1
.1UF
0402_R X7R 16V 10%
C4C2 .1UF
0402_R X7RALUM 16V
10%2
2
+3.3V
1
C2B31 1000UF
RDL_R ALUM 16V 20%
C4C7 1000UF
RDL_R
6.3V
20%2
C3B91 .1UF
0402_R X7R 16V 10%
2
2
C4B31 .1UF
0402_R X7R 16V 10%
2
C2B21 .1UF
0402_R X7R 16V 10%
2
C4B21 .1UF
0402_R X7R 16V 10%
Wed Jan 16 11:22:53 2008
SLOT 7 : PCI-E X1
286.0602-7R177-0000-F00
Page 29
INININ
OUT
OUTBIIN
OUTININ
OUT
X1 CONNECTOR
X8 CONNECTOR
X4 CONNECTOR
X16 CONNECTOR
PRSNT1*
+12V +12V
GND
+3.3V
+3.3V
TDO
PERST*
GND
GND
REFCLK+ REFCLK-
TMS
PERN0
PERP0
TCK TDI
GND
RSVD
GND
PERP1
PERN2
GND
PERN5
PERP5
GND
GND
PERN4
PERP4
GND
RSVD
RSVD
GND
PERN3
PERP3
GND
GND
PERP2
GND
PERN1
GND
RSVD
PERP6
GND
GND
GND
PERN8
PERP8
PERN7
GND
GND
GND
PERP7
PERP9
PERP10
GND
GND
PERN9
PERN6
GND
GND
GND
PERN11
PERP11
GND
PERP12 PERN12
GND
GND PERP13 PERN13
GND
GND PERP14 PERN14
GND
GND PERP15
GND
PERN10
PERN15
GND
+12V
+12V +12V
GND
PETN1
PETP1
GND
PETN0
TRST*
+3.3V
GND
SMDAT
SMCLK
+3.3V_AUX WAKE*
RSVD GND PETP0
GND PRSNT2* GND
GND
GND GND
PRSNT2*
RSVD
GND
GND
PETN5
PETP5
GND
GND
PETN4
PETP2 PETN2
PETN3
GND PETP4
GND
PETP3
PETP6
GND
GND
GND
GND
PETN8
PETN9
PETN10
PETP10
PETP8
GND
GND
PETN7
GND
GND
PETN6
PETP9
GND
PRSNT2*
PETP7
PETN15 GND
GND
GND
GND
GND
GND
GND
GND
GND PETP11 PETN11
PETP13 PETN13
PETN14
PETP14
PETN12
PETP12
GND
PETP15
PRSNT2* RSVD
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
39D6<> 31A7<>
46C7< 39D6<
30D8> 28C7>
16E2>
16D2>
16B3<
28C6<
30D7<
31A7<
28C6<>
30D7<>
16B6>
16C6<
PE_X8-1_TXC<7..0>
PE_X8-1_TXC<7..0>*
PE_X8-1_PRESENT*
PLACE CAPS NEAR CONNECTOR
19C8>
19C8>
15A4<>
PE_WAKE*
11C3<>
11A7< 11C3< 15B4<
11A7<> 46C7<
+12V
+3.3V+3.3V_DUAL
SMB_SCL SMB_SDA
R3C2
1
0402_R
10K
0
1
2
3
4
5
6
7
C3C4
2
1
0402_R
0
X7R
.1UF
16V 10%
C3C6
2
1
0402_R
1
X7R
.1UF
16V 10%
C3C8
2
1
0402_R
2
X7R
.1UF
16V 10%
C3D1
2
1
0402_R
3
X7R
.1UF
16V 10%
C3D3
2
1
0402_R
4
X7R
.1UF
16V 10%
C3D5
2
1
0402_R
5
X7R
.1UF
16V 10%
C3D7
0402_R
6
0402_R
7
21
X7R
.1UF
16V 10%
C3D9
2
1
X7R
.1UF
16V 10%
5%
0402_R
0402_R
0402_R
0402_R
0402_R
0402_R
0402_R
0402_R
2
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
PR_TRST*
C3C5
.1UF
C3C7
.1UF
C3C9
.1UF
C3D2
.1UF
C3D4
.1UF
C3D6
.1UF
C3D8
.1UF
C3D10
.1UF
PE0_TX0
PE0_TX0*
2
PE0_TX1
PE0_TX1*
2
PE0_TX2
PE0_TX2*
2
PE0_TX3
PE0_TX3*
2
PE0_TX4
PE0_TX4*
2
PE0_TX5
PE0_TX5*
2
PE0_TX6
PE0_TX6*
2
PE0_TX7
PE0_TX7*
2
02/04/2008
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82
J3B1 CONN_R
I135
PCI_EXPRESS_X16
GREEN
R_TYPE
A10 A11
A12 A13 A14 A15 A16 A17 A18
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82
FLASH
Mon Feb 04 11:02:23 2008
A1 A2 A3 A4 A5 A6 A7 A8 A9
0
1
2
3
4
5
6
7
+3.3V+12V
+3.3V
2
PE_TCK PE_TDI TP_PE_TDO PE_TMS
1
PE_RESET*
PE_X8-1_REFCLK
PE_X8-1_REFCLK* PE_X8-1_RX<7..0> PE_X8-1_RX<7..0>*
0
1
2
3
4
5
6
7
R3B6 10K
5% 0402_R
+3.3V
2
1
R3C1 10K
5% 0402_R
R3B3
2
1
5%0402_R
10K
16B3> 16B3> 16C2< 16C2<
X16 SLOT DECOUPLING
+12V
SLOT 6
30D2< 28C3< 16E4>
C3B3
C2B41 1000UF
RDL_R ALUM 16V
20%2
C3B71 .1UF
0402_R X7R 16V
10%2
SOLT 6 : PCI-E X16
1
.1UF
0402_R X7R 16V
2 10%
+3.3V
C3C111 1000UF
RDL_R ALUM
6.3V
20%2
+3.3V_DUAL
C2C10
1
100UF
RDL_R ALUM 25V 20%
2
1
2
C3B6 .1UF
0402_R X7R 16V 10%
C3C21 .1UF
X7R 16V
2
10%
1 C3C3
.1UF
0402_R X7R 16V 10%
2
1
2
C3B5 .1UF
0402_R X7R 16V 10%
2 10%
C4C41 .1UF
0402_R0402_R X7R 16V
296.0602-7R177-0000-F00
Page 30
INININ
OUT
OUTBIIN
OUT
IN
X1 CONNECTOR
X8 CONNECTOR
X4 CONNECTOR
X16 CONNECTOR
PRSNT1*
+12V +12V
GND
+3.3V
+3.3V
TDO
PERST*
GND
GND
REFCLK+ REFCLK-
TMS
PERN0
PERP0
TCK TDI
GND
RSVD
GND
PERP1
PERN2
GND
PERN5
PERP5
GND
GND
PERN4
PERP4
GND
RSVD
RSVD
GND
PERN3
PERP3
GND
GND
PERP2
GND
PERN1
GND
RSVD
PERP6
GND
GND
GND
PERN8
PERP8
PERN7
GND
GND
GND
PERP7
PERP9
PERP10
GND
GND
PERN9
PERN6
GND
GND
GND
PERN11
PERP11
GND
PERP12 PERN12
GND
GND PERP13 PERN13
GND
GND PERP14 PERN14
GND
GND PERP15
GND
PERN10
PERN15
GND
+12V
+12V +12V
GND
PETN1
PETP1
GND
PETN0
TRST*
+3.3V
GND
SMDAT
SMCLK
+3.3V_AUX WAKE*
RSVD GND PETP0
GND PRSNT2* GND
GND
GND GND
PRSNT2*
RSVD
GND
GND
PETN5
PETP5
GND
GND
PETN4
PETP2 PETN2
PETN3
GND PETP4
GND
PETP3
PETP6
GND
GND
GND
GND
PETN8
PETN9
PETN10
PETP10
PETP8
GND
GND
PETN7
GND
GND
PETN6
PETP9
GND
PRSNT2*
PETP7
PETN15 GND
GND
GND
GND
GND
GND
GND
GND
GND PETP11 PETN11
PETP13 PETN13
PETN14
PETP14
PETN12
PETP12
GND
PETP15
PRSNT2* RSVD
OUT
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
46C7< 39D6< 31A7<
39D6<> 31A7<> 29D7<>
29D8> 28C7> 16C6<
16E3>
16D3>
PE_X8-2_TXC<15..8>
PE_X8-2_TXC<15..8>*
16C6<
28C6< 19C8>
29D7<
16B6>
PE_X8-2_PRESENT*
19C8>
28C6<>
PLACE CAPS NEAR CONNECTOR
15B4<
15A4<>
PE_WAKE*
11C3<>
11A7<> 46C7<
8
9
10
11
12
13
14
15
11A7<
11C3<
SMB_SCL SMB_SDA
0402_R
8
0402_R
9
0402_R
10
0402_R
11
0402_R
12
0402_R
13
0402_R
14
0402_R
15
02/04/2008
+12V+3.3V+3.3V_DUAL
R2C4
1
0402_R
10K
C2C2
2
1
X7R
.1UF
16V 10%
C2C4
2
1
X7R
.1UF
16V 10%
C2C6
2
1
X7R
.1UF
16V 10%
C2C8
2
1
X7R
.1UF
16V 10%
C2D1
2
1
X7R
.1UF
16V 10%
C2D3
2
1
X7R
.1UF
16V 10%
C2D5
2
1
X7R
.1UF
16V 10%
C2D7
2
1
X7R
.1UF
16V 10%
5%
0402_R
0402_R
0402_R
0402_R
0402_R
0402_R
0402_R
0402_R
2
1
X7R 16V 10%
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
1
X7R 16V 10%
PR1_TRST*
C2C3
2
.1UF
C2C5
21
.1UF
C2C7
2
.1UF
C2C9
2
.1UF
C2D2
2
.1UF
C2D4
2
.1UF
C2D6
2
.1UF
C2D8
2
.1UF
PE0_TX8
PE0_TX8*
PE0_TX9
PE0_TX9*
PE0_TX10
PE0_TX10*
PE0_TX11
PE0_TX11*
PE0_TX12
PE0_TX12*
PE0_TX13
PE0_TX13*
PE0_TX14
PE0_TX14*
PE0_TX15
PE0_TX15*
B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11
B12 B13 B14 B15 B16 B17 B18
B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32
B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82
J2B1 CONN_R
I173
PCI_EXPRESS_X16
GREEN
R_TYPE
A10 A11
A12 A13 A14 A15 A16 A17 A18
A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32
A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82
FLASH
Mon Feb 04 10:38:11 2008
A1 A2 A3 A4 A5 A6 A7 A8 A9
8
9
10
11
12
13
14
15
+3.3V+12V
PE1_TCK PE1_TDI TP_PE1_TDO PE1_TMS
+3.3V
2
R2B1 10K
5% 0402_R
1
PE_RESET*
PE_X8-2_REFCLK
PE_X8-2_REFCLK* PE_X8-2_RX<15..8> PE_X8-2_RX<15..8>*
8
9
10
11
12
13
14
15
+3.3V
2
1
R2C2 10K
5% 0402_R
1
0402_R
R2C1
10K
2
5%
16D6> 16D6> 16D3< 16C3<
X16 SLOT DECOUPLING
+12V
SLOT 5
29D2< 28C3< 16E4>
C3B8
1
1000UF
RDL_R ALUM 16V
2
C2B11 .1UF
0402_R X7R 16V 10%
220%
SOLT 5 : PCI-E X16
C2B71 .1UF
0402_R X7R 16V 10%
2
+3.3V
C2C111
RDL_R ALUM
6.3V
2 20%
+3.3V_DUAL
1 C2B5
100UF
RDL_R ALUM 25V
20%2
1
2
C3B2 .1UF
0402_R X7R 16V 10%
2
1
2
C2C121 .1UF .1UF1000UF
0402_R X7R 16V 10%
C2C13 .1UF
0402_R X7R 16V 10%
1
2
C2B6 .1UF
0402_R X7R 16V 10%
1
2
C2C1
0402_R X7R 16V 10%
6.0602-7R177-0000-F00
30
Page 31
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
OUTININBIBIININ
OUT
OUTBIBIBIBIBIBI
OUTBIBI
OUT
OUT
OUT
OUT
TDO
3.3VAUX PRSNT1*
PRSNT2*
RSVD1 RSVD2 RSVD3 RSVD5
TCK TMS
TDI
+12V
TRST*
+5V
+5V
-12V
+5V
+5V
+5V
+5V
+5V
+5V
+5V
+5V +5V
+5V +5V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
+3.3V
GND
GND
GND
GND GND
GND
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
GND GND
GND GND
GND
V2.2
5V 32BIT
AD1
AD0 AD2
AD5 AD6
AD3 AD4
AD7
AD10
AD17
AD16
AD13
AD12
AD11
AD15
AD14
AD8 AD9
AD25
AD23
AD22
AD19
AD24 AD26
AD27
AD18 AD20
AD21
AD28 AD30
AD29 AD31
IDSEL CBE0*
CBE1* CBE2* CBE3*
GNT* PME*
REQ*
INTA* INTB*
INTD*
INTC*
FRAME*
DEVSEL*
RESET*
TRDY* IRDY* LOCK* SERR*
PERR*
STOP*
SBO*
PAR
REQ64* ACK64* CLOCK
KEY<A50> KEY<A51> KEY<B50> KEY<B51>
SDONE
BIBIOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
SLOT 4
J1B4
CONN_R
32C8<> 17D7<>
32C8<> 17B7<>
31C3>
32D8>
31C3> 31C3>
31B3> 31A3> 31A3> 31B3> 31B3>
11C3<> 15A4<>
31A3>
31B3>
31B3>
11C3< 15B4<
31C3>
31D3> 17D3<
17B7< 17B7<> 17B7<> 17B7<> 17B7<> 17B7<>
31B3>
17B8>
17B7> 17B7<> 32C8<> 11A7<>
17A8>
11A7<
31A3>
31A3>
17C1>
32C8<>
32D8> 32C8<> 32C8<> 32C8<> 32C8<> 32D8<>
32C8>
32C8>
28C6<> 29D7<> 30D7<> 39D6<> 46C7<
28C6< 29D7< 30D7< 39D6< 46C7<
19C8>
19C8>
PCI_AD<31..0>
PCI_C/BE<3..0>*
17C3< 17C3< 17C3< 17C3<
17C3>
PCI_PME* PCI_FRAME* PCI_TRDY* PCI_STOP* PCI_IRDY* PCI_DEVSEL* PCI_LOCK* PCI_PERR* PCI_SERR* PCI_PAR SMB_SDA PCI_RST_SLOTS_1* SMB_SCL
PCI_REQ64A* PCI_ACK64* PCI_CLKSLOT1
PCI_INTY* PCI_INTZ* PCI_INTW* PCI_INTX*
PCI_REQ<1..0>* PCI_GNT0*
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 22
0
A58
1
B58
2
A57
3
B56
4
A55
5
B55
6
A54
7
B53
8
B52
9
A49 B48 A47 B47 A46 B45 A44 A32 B32 A31 B30 A29 B29 A28 B27 A25 B24 A23 B23 A22 B21 A20 B20 A26
0
A52
1
B44
2
B33
3
B26 A6
B7 A7 B8
0
B18 A17
A19 A34 A36 A38 B35 B37 B39 B40 B42 A43 A41 A15 A40
A60 B60 B16
I82
WHITE
PCI124
A14
B4 B9
B11
A9 B10 A11 B14
B2
A1
A3
A4
A2
B1
B5
B6
A5
A8 A10 B61 A16 B62 A59 B59 A61 B19 A62
A21 A27 A33 A39 A45 B43 B41 B36 B31 B25 B54 A53
A12 A13 A18 A24 A30 A35 A37 A42 A48 A56
B3 B12 B13 B15 B17 B22 B28 B34 B38 B46 B49 B57
+3.3V_DUAL
TP_PCI2_B4 TP_PCI2_B9 TP_PCI2_B11 TP_PCI2_A9 TP_PCI2_B10 TP_PCI2_A11 TP_PCI2_B14
+12V
+5V
+3.3V
-12V
32C8<> 31B7<>
31B7>
31B7>
31B7>
32D8>
31B7>
32C8>
31A7>
32D8<>
31B7<>
32C8<>
31B7<>
32C8>
31A7>
32C8<>
31B7<>
32C8<>
31B7<>
32C8<> 31B7<>
32D8> 31B7>
17D3<
17C3<
17C3<
17C3<
17C3<
17B7>
17B7<>
17B7<>
31A7<>
17B8>
17B7<>
17B7<>
17B7<>
31A7>
31A7<
17B7<
PCI_REQ<1..0>*
PCI_INTW*
PCI_INTX*
PCI_INTY*
PCI_INTZ*
PCI_SERR*
PCI_DEVSEL*
PCI_IRDY*
PCI_LOCK*
PCI_PERR*
PCI_FRAME*
PCI_TRDY*
PCI_STOP*
PCI_ACK64*
PCI_REQ64A*
PCI_PME*
2
5%
2
5%
5
6
8
7
5
5
7
7
6
8
6
8
2
5%
2
5%
2
5%
+3.3V
+3.3V_DUAL
EMPTY
R2C3
0
1
0402_R
8.2K
R4E2
1
1
0402_R
8.2K
RP2C1
4
8.2K
RP2C1
3
8.2K
RP2C1
1
8.2K
RP2C1
2
8.2K
RP2D2
4
8.2K
RP2D1
4
8.2K
RP2D1
2
8.2K
RP2D2
2
8.2K
RP2D2
3
8.2K
RP2D1
1
8.2K
RP2D1
3
8.2K
RP2D2
1
8.2K
R1E4
1
0402_R
8.2K
R1E3
1
0402_R
8.2K
R2C5
1
0402_R
8.2K
PCI SLOT DECOUPLING
+3.3V
C2E4
2
1
RDL_R ALUM
100UF
25V 20%
C2D11
2
1
0402_R X7R
.1UF
16V 10%
C1E4
2
1
0402_R X7R
.1UF
16V 10%
C1C13
2
1
0603_R X5R
1UF
16V 10%
C1D2
2
1
0603_R X7R
0.1UF
16V 10%
C2D10
2
1
0402_R X7R
.1UF
16V 10%
+5V
C1C1
2
1
RDL_R ALUM
100UF
25V 20%
C1E2
2
1
RDL_R ALUM
22UF
25V 20%
C2E1
2
1
0402_R X7R
.1UF
16V 10%
C1C14
2
1
0603_R X7R
0.1UF
16V 10%
C1B9
2
1
0603_R X7R
0.1UF
16V 10%
C1C15
2
1
0402_R X7R
.1UF
16V 10%
C2E2
2
1
0603_R X7R
0.1UF
16V 10%
+3.3V_DUAL
1
RDL_R ALUM 25V 20%
2
100UF
C3C12
FOR A01 WAR
SLOTS 4 : PCI 1 & TERM
Tue Mar 18 12:14:16 2008
602-7R177-0000-F00
316.0
Page 32
OUT
AN
CAT
2101
TPA*
GND
GND
PWR
TPB*
TPA
GND
PWR
TPB
THERM
OUTINOUTININININ
OUT
OUTBIBIBIBI
OUT
OUTBIBIBIINBIININININBIINOUT
IEEE1394
VDDP
VDDP
VDDP
VDDP VDDP
AVDD
AVDD
AVDD
AVDD
AVDD
DVDD
DVDD DVDD
DVDD
DVDD
DVDD
DVDD
DVDD
CPS CNA
TPA0
TPBIAS0
TPA1*
TPA1
TPA0*
TPB0
TPB0*
TPB1
R0 R1
PLLVDD
TEST16
TEST17
TPB1*
TPBIAS1
TEST3 TEST2
TEST8
TEST9
PLLGND
TEST1
AGND
AGND
AGND
TEST0
AGND
AGND AGND
AGND
FILTER1
FILTER0
GND GND
GND
GND GND
GND
GND GND
GND GND
CYCLEOUT
REG18
REG18
IRQ12/PME*
INTA*
CYCLEIN
DEVSEL*
PERR*
SERR*
STOP*
TRDY*
IRDY*
FRAME*
C/BE3*
C/BE2*
GRST* PCIRST* PCI_CLKRUN*
PCLK REQ*
C/BE1*
C/BE0*
PAR
AD15
EGNT*
AD11
AD14 AD16
AD17
AD13
AD12
AD10
AD0 AD1 AD2
AD4 AD5
AD7
AD6
AD3
AD8 AD9
AD18 AD20
AD21 AD22
AD19
IDSEL
AD31
AD30
AD29
AD27 AD28
AD26
AD24 AD25
AD23
PC1 PC2
PC0
REG_EN*
GPIO2 GPIO3
SCL
SDA
XI XO
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
C1E3
.1UF
0402_R X7R
16V2 10%
R2F7
100
30PPM 20PF
2
1%
32C4> 32B4<
1
32C8< 32C4>
C2F8
1
.1UF
0402_R X7R 16V
2
10%
FW_1P8V_1
FW_1P88_2
EMPTY
R2F6
1
0402_R
IDSEL_1394
FW_DVDD
1
2 50V
0 1 2 3 4 5 6 7 8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 2623 27 28 29 30 31
FW_XI FW_XO
C1G10
33PF
0402_R C0G
5%
U1F1 TQFP_R
30 93
87 86
13 212
5%
0
53 49 50
52 54
58 57 56
73
0
60
1 2
47 34
3
14 85 12
16
1
19 18
84 82 81 80 79 77 76 74 71 70 69 67 66 65 63 61 46 45 43 42 41 40 38 37 32 31 29 28 26 25 24 22
36 99
98 97
90 89
92 91
5 6
9
I39
32B4<
FW_DVDD
31C3>
31B7>
31B7<> 31B7<> 31B7<> 31B7<> 31B7<>
31B3>
31B3>
2
R1F12 10K
5% 0402_R
1
31B7>
31A3>
31B3> 31B3> 31B3> 31A3> 31A3>
31A7<>
31A7>
31A7>
17C3<
17B7<
17B7<> 17B7<> 17B7<> 17B7<> 17B7<> 17B7<>
17B7>
17B8>
2
R1F10 10K
5% 0402_R
1
FW_DVDD
2
R2G8
4.7K
EMPTY
1
2
1
5% 0402_R
31B7<>
31D7<>
R1G16 1K
5% 0402_R
32B7>
17B7<> 31B7<>
17A8>
17C1>
17D3< 31D3>
17C3>
17D7<>
PS_PWRGD
2
R1F13
4.7K
5% 0402_R
1
1394_GRST*
27
1
8
RP1F1
220
RP1F1 220
FW_GPIO2 FW_GPIO3
65
34
RP1F1 220
RP1F1
220
32A7< 32A4<
PCI_INTZ*
PCI_PME*
PCI_DEVSEL* PCI_FRAME* PCI_IRDY* PCI_TRDY* PCI_STOP* PCI_PAR PCI_SERR* PCI_PERR*
32A7<
32A4< 32D7<
PCI_C/BE<3..0>*
1394_GRST*
PCI_RST_1394*
FW_CLKRUN*
PCI_CLK_1394
PCI_REQ<1..0>*
PCI_GNT1*
PCI_AD<31..0>
32D7< 32A4<
32B4<
32C4>
32C8<
FW_SDA FW_SCL
C1G12
1
33PF
0402_R C0G 50V
2
5%
1
21A7< 16E6< 19D3< 44D2>
32C8<
1
0402_R
Y1G1
24.576MHZ
2
HC49_R
I11
TSB43AB22A
+5V
20 35 48 62 78
107 108 120
15 27 39 51 59 72 88
100 106
96
116
115 114 113 112
1 2
800MA 0805_R FB
800MA 0805_R FB
+3.3V
+3.3V
0402_R
1
2
1
2
1
L1F1 80
L1F3 80
R1F1
390K
C1F5
1UF
FW_AVDD
C1F2
2
1UF
FW_DVDD
FW_CBL_PWR2
2
5%
R1F7
1
12
0603_R X5R 16V 10%
1
0603_R X5R 16V 10%
2
5%0402_R
1K
125
124 123 122 121
118 119
101 102 104 105
109 110 111 117 126 127 128
103
110 OHM DIFF PAIRS
FW_R0 FW_R1
7
FW_FILTER0
3
FW_FILTER1
4 8
1
0402_R
1
0402_R
R1F11
10K
R1F9
220
32C4>
5%
1
0402_R
5%
2
R1F8
6.34K
C1F19
.1UF
2
32B4< 32D7<
10 11
94 95
17 23 33 44 55 64 68 75 83
FW_DVDD
2
1%
21
10%
16V
0402_R
X7R
0402_R
32A7< 32C8<
32D4>
1
R1F14
FW_VDD_PLL
2
5%
220
32A4< 32C8<
1
2
Wed Jan 16 11:22:59 2008
32A4<
32A7< 32D7<
FW_DVDD
C2F5 22UF
0805_R X5R
6.3V 20%
FW_AVDD
32D7<
32A7<
32A4<
32C8<
32B4< 32C1>
32C4>
0805_R
C1F12
1
.1UF
0402_R X7R 16V
2
10% 10%
C2F10
1
.1UF
0402_R X7R 16V
2
10%
C1F8
1
22UF .1UF
0805_R X5R
6.3V 20%
2
800MA
+3.3V
FB
1
2
2
TPBIAS0
1
L1F4 80
2
C1F13
1000PF
0402_R X7R 16V
2
C1G111 1UF
0603_R X5R 16V 10%
DIGITAL VDD
1
C2F6
.1UF
0402_R X7R
16V2 10%
C1F14
1
.1UF
0402_R X7R 16V
2
10%
ANALOG VDD
C1F11
0402_R X7R 16V 10%
11
2
C1F9
.1UF
0402_R X7R
10%
1
216V
1
2
C1F3
.1UF
0402_R X7R 16V 10%
C1F1 .1UF
0402_R X7R 16V 10%
FW_TPA1 FW_TPA1*
C1F15
1
.1UF
0402_R X7R 16V
2
10%
C1F20
1
.1UF
0402_R X7R 16V
2
10%
2
1
2
C1F101 1UF
0603_R X5R 16V 10%
1
2
C1F18
.1UF
0402_R X7R 16V 10%
EMPTY
FW_TPB1 FW_TPB1*
C2F12 .1UF
0402_R X7R 16V 10%
+12V
TPBIAS1
1
1
R1F5
56.2
1%
0402_R
2
1
C2F11
1
.1UF
0402_R X7R 16V
2
10%
IEEE1394
0402_R
2
0402_R
2
C1F7
1
220PF
0402_R C0G
2
50V 5%
R1F4
56.2
1%
R1F3
56.2
1%
1812_R
1
.1UF
2
1
C2F4
0402_R X7R 16V 10%
RT1E1
1.5A
FW_CBL_PWR2
2
24V
1 C1F4
1UF
0603_R X5R 16V 10%
2
1
R1F2
56.2
1%
0402_R
2
1
R1F6
5.11K
1%
0402_R
2
+5V
5V 20,35,48,62,78
C2F14
1
1UF
0603_R X5R 16V 10%
2
5000MA 0603_R
2
1
FB
1
2
1
2
CR1F1 MBRS340T3G
SMC_R
1
L1F2 30
2
FW_FB_FNT1
C1F6
.1UF
0402_R X7R 16V 10%
C1F17
.1UF
0402_R X7R 16V 10%
1394_HEADER
C1F16
1
.1UF
0402_R X7R 16V
2
10%
1 2 3 4 5 6 7 8 10
32C4<
THR_R
J1F1
RED
I134
C2F13
1
.1UF
0402_R X7R
16V2 10%
6.0602-7R177-0000-F00
1
2 16V
C2F9
.1UF
0402_R X7R
10%
32
Page 33
OUTBIBI
2101
OUT
THERM
OUT
THERM
BIBIBIBIINBIBI
2101
2101
OUTBIBI
THERM
THERM
VCCGROUND
VCC D2- D2+ GND
VCC D3- D3+ GND
VCC D0- D0+ GND
VCC D1- D1+ GND
D3+ D3-
D2-
D1+
D2+
D1-
D0-
D0+
BIBIBIBIBIBIBIBIOUT
GND
8
GND
4
7
D+
3
D+D-65VCC
1D-2
VCC
VCC VCC
GND
GND
GND
GND
D0-
D0+
D1+
D1-
GND GND
BIBIBIBIBI
BI
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
PLACE NEAR CONN
R7B3
2
1
5%
0402_R
0
EMPTY
L7B2
18D2<> 18D2<>
USB_0 USB_0*
18D2<> 18C2<>
18C2<> 18C2<>
18C2<> 18C2<>
USB_1 USB_1*
USB_2 USB_2*
USB_3 USB_3*
67OHM
.33A
67OHM
.33A
CM_CHOKE
1 2
1
0402_R
1
0402_R
1 2
0402_R
1
0402_R
L6B3 .33A
1 2
1
0402_R
1
0402_R
L6A1 .33A
1 2
1
0402_R
2012_R
R7B4
R7B1
2012_R
R7B2
R6B17
R6B18
R6A1
R6A2
4
CM_CHOKE
3
2
5%
0
2
5%
0
L7B1
4
CM_CHOKE
3
21
5%
0
2
5%
0
67OHM 2012_R
4 3
2
5%
0
2
5%
0
67OHM 2012_RCM_CHOKE
4 3
2
5%
0
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
EMPTY
USB_0_FB USB_0_FB*
USB_1_FB USB_1_FB*
USB_2_FB USB_2_FB*
USB_3_FB USB_3_FB*
J7A1
USBX4
15 14
THR_R
13
9 5
1 11 10
18A2<> 18A2<>
7 6
3 2
I521
USB_11* USB_11
USBX4
16 12
22 21 20 19 18 17
8
4
1
0402_R
67OHM
2
.33A
1
.33A
67OHM
1
0402_R
0402_R
R1B4
2012_R 2012_R
R1B5
1
1
2
0 L1B2
0
R7B7
10K
1000UF
RDL_R ALUM
6.3V 20%
2
5%
EMPTY
3
CM_CHOKE
4
CM_CHOKE
L1B2
EMPTY
2
5%
USB_OC3210*
2
5%
2
R7B6 20K
5% 0402_R
EMPTY
1
C7A21C7A3 470PF
0402_R X7R 50V
10%2
+5V_DUAL
1
RT1B2
1.5A
1206_R 6V
2
VOLTAGE=5.00000
C1B5
1
470PF
0603_R C0G 50V
5%2
USB_11_FB* USB_11_FB
2 10%
C7A11 470PF
0402_R X7R 50V
RT7B1
2.6A
1
1812_R
C1B61 470PF
0603_R C0G 50V
5%2
BLUE J1B2
THR_R
1 3 5 7
I180
HDR2X5KEY9
2
6V
18B2<> 18B2<>
C1B1
1
1000UF
RDL_R ALUM
6.3V 20%
2
2
USB_10_FB*
4
USB_10_FB
6 8
TP_USB1110_12
10
18A2<
+5V_DUAL
1
0402_R
R1B9
10K
USB_9* USB_9
USB_OC1110*
2
5%
2
R1B10 20K
5% 0402_R
1
EMPTY
0402_R
67OHM
1
.33A
2
.33A
67OHM
1
0402_R
R1B2
2012_R 2012_R
R1B3
5%
0 L1B1
5%
0
0402_R
67OHM
.33A
0402_R
21
EMPTY
4
CM_CHOKE
3
CM_CHOKE
L1B1
2
R1A4
2
2012_R
R1A5
1
EMPTY
21
5%
0
EMPTY
L1A3
3
CM_CHOKE
41
EMPTY
L1A3
2
5%
0
USB_10* USB_10
+5V_DUAL
1
RT1B1
1.5A
1206_R 6V
2
VOLTAGE=5.00000
C1B3
1
470PF
0603_R C0G 50V
5%2
USB_9_FB* USB_9_FB
18A2<
18B2<> 18B2<>
C1B41 470PF
0603_R C0G 50V 5%
2
BLUE J1B1
THR_R
1 3
7
I202
HDR2X5KEY9
C1B21 1000UF
RDL_R ALUM
6.3V
20%2
2 4 65 4 8
10
1
0402_R
USB_8_FB* USB_8_FB
TP_USB98_12
R1B8
10K
2
5%
2
1
USB_OC98*
R1B1 20K
5% 0402_R
EMPTY
R1A2
1
0402_R
L1A2
3
2012_R
CM_CHOKE
L1A2
R1A3
1
0402_R
2
5%
0
67OHM
2
.33A
1
2
5%
0
EMPTY
EMPTY
18A2<
USB_8* USB_8
18B2<> 18B2<>
18C2<> 18C2<>
18C2<> 18C2<>
PLACE NEAR CONN
USB_4 USB_4*
USB_5 USB_5*
1
0402_R
67OHM
1
.33A
2
1
0402_R
1
0402_R
67OHM
1
.33A
2
1
0402_R
R6B6
2012_R
R6B7
R6B4
2012_R
R6B5
5%
0
L6B2
5%
0
5%
0
L6B1
5%
0
2
EMPTY
4
CM_CHOKE
3
EMPTY
2
2
EMPTY
4
CM_CHOKE
3
EMPTY
2
USB_4_FB USB_4_FB* USB_5_FB USB_5_FB*
33B2<
USB_VCC_7654
J6A1 THR_R
USBX2_RJ45_GIG_E_RES
USBX2_RJ45
3 2 7
6
4
8
I263
25 26 27 28
1 5
1
0402_R
R5A6
C6B11
1
1000UF
RDL_R ALUM
6.3V
2 20%
USB_OC7654*
2
5%
2
10K
1
1
18A2<
R5A7 20K
5% 0402_R
EMPTY
6V
2
+5V_DUAL
18B2<> 18B2<>
C6A1 470PF
0402_R X7R 50V
10%2
1
2
1812_R
C6B12 470PF
0402_R X7R 50V 10%
RT5A1
2.6A
1
Mon Feb 04 17:54:45 2008
USB_6* USB_6
02/04/2008
R5A5
2
1
5%
0402_R
0
EMPTY
L5A2
67OHM
.33A .33A
67OHM
2 1
1
0402_R
2012_R 2012_R
R5A4
5%
0
3
CM_CHOKE
4
CM_CHOKE
L5A2
EMPTY
2
USB_6_FB* USB_6_FB
BLUE J5A2
THR_R
1 3 5 7
I551
HDR2X5KEY9
USB_VCC_7654
2
USB_7_FB*
4
USB_7_FB
6 8
TP_USB76_12
10
USB CONNECTORS
33B6>
10/17
R5A3
2
1
5%
0402_R
0
EMPTY
L5A1
67OHM
.33A .33A
67OHM
1 2
1
0402_R
2012_R 2012_R
R5A2
0
4
CM_CHOKE
3
CM_CHOKE
L5A1 2
5%
EMPTY
USB_7* USB_7
6.0602-7R177-0000-F00
18B2<> 18B2<>
33
Page 34
IN
GRNGRN
YEL
250250
GND GND GND GND GND
CT
MDI0-
MDI1+
MDI0+
MDI1-
MDI3-
MDI3+
MDI2-
MDI2+
OUTINININOUT
OUT
OUTBIINININ
Gbit LAN PHY
AVDD
NC
AVDD
AVDD
AVDD
AVDDC AVDDC
DVDD DVDD
DVDD
DVDD
VDDO
VDDO
DIS_REG1.2V
AVDDR AVDDR
VDDOR
VDDOR
AVDDX
CTRL1.8V
NC
RSET
MDI0­MDI1+
MDI1­MDI2+
MDI2­MDI3+
MDI3-
MDI0+
LED2
LED0 LED1
HSDAC+ HSDAC-
TXD2 TXD0
TXD1
TXD3
TX_CTRL
RX_CLK
RX_CTRL
TRST*
TX_CLK
RXD0
RXD1
RXD2
RXD3
MDC
MDIO
TCK TDO
TMS
TDI
XTAL_OUT
XTAL_IN
COMA* CONFIG3
TSTPT
RESET*
CONFIG1 CONFIG0
CONFIG2
VREF
GND_PAD
OUT
IN
ADJ/GND
VOUT_TAB
VOUT_PINVIN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
19E6<
+3.3V_DUAL
19D6> 19D6>
KEEP STUBS <250 MILS
SEL FREQ LEFT OPEN FOR 25 MHZ CLK INPUT
19D2>
BUF0_25MHZ
19D6>
19D6>
+3.3V_DUAL
U6B1 SOT-223_R ADJ
3
C6C3
1
10UF
0805_R X5R 10V 10%
2
PHY HW DEFALT CONFIG CONFIG 0-1
CONFIG 2 CONFIG 3
19E6>
19D6> 19E6>
RGMII0_RXD<3..0>
2
R4B8
1.5K
5%
1
RGMII0_MDIO RGMII0_MDC
19D6< 19D6< 0402_R
3 2 1 0
EMPTY
1
2
2
HC49_R
I405
C4B5 18PF
0402_R C0G 50V 5%
EMPTY
Y4B1
50PPM 18PF
1
0402_R
R4B5
LAN1_XTAL1_R
2
1
5%
0
R4B4 0
5% 0402_R
EMPTY
2
25.000MHZ
RGMII_RESET*
+3.3V_DUAL
AMS1117_SOT223
PHY ADDRESS = 00001
RXCLK TRANSMITS W/DATA TXCLK DELAY = DISABLED
R5C7
2
1
1%
0402_R
1
0402_R
R5C6
1K
1K
2
1%
LAN_VREF
RGMII0_PWRDWN*
2 4
I4311
2
R1
1
LAN0_ADJ
2
R2
1
R6B2 576
1% 0402_R
R6B1 301
1% 0402_R
RGMII0_TXD<3..0>
RGMII0_TXCTL RGMII0_TXC
PLACE NEAR PHY
RGMII0_RXCTL RGMII0_RXC
LAN1_XTAL2_R
1
2
C4B6
1
18PF
0402_R C0G 50V 5%
2
2
R5B8
4.7K
5% 0402_R
1
1
+3.3V_DUAL
2
R5B6 10K
5% 0402_R
1
R4B6 0
5% 0402_R
+1.8V_DUAL_LAN0
C6B21 22UF
0805_R X5R
6.3V
20%2
U5B1 QFN64_R
62
3
61
2
59
1
58
0
63 60
55 54 51 50
TP_LAN0_TCK TP_LAN0_TDI TP_LAN0_TDO TP_LAN0_TMS LAN0_TRST*
49 53
45 48
42 43 44 41 11
32
R5C3
1
0402_R
R5B7
1
0402_R 5%
4.7K
RGMII0_RXCLK_R
2
5%
0
2
TP_LAN_TSTPT
EMPTYEMPTY
LAN1_XTAL1 LAN1_XTAL2
38 39 10 57
4 3 2 1 64
65
I432
34D1<
C6B31 120PF
0402_R C0G 50V 5%
2
NOTE:
1.VOUT=0.8V*(1+R1/R2)
2.1.8V_DUAL_LAN0 IS ACTUALLY AT 1.9V
BIOSENABLE AUTO-CROSSOVER PROGRAM LED TO MODE 3 COMA* MUST BE PROGRAMMED BEFORE RESET
88E1116R
LAN0_CONFIG3
2
R5B2 0
5% 0402_R
1
+3.3V_DUAL
C4B7
1
2
.1UF
0402_R X7R 16V 10%
21 22 27 28 29
34 37
14 15
16
5 13 40 47
7 46
52 56
C5C21 .1UF
0402_R X7R 16V
LAN0_MDI0+ LAN0_MDI0-
LAN0_MDI1+ LAN0_MDI1-
LAN0_MDI2+ LAN0_MDI2-
LAN0_MDI3+ LAN0_MDI3-
R4B7
1
0402_R
4.99K
LAN0_LED0 LAN0_LED1 LAN0_LED2
2
R5B3 0
5% 0402_R
EMPTY
1
12 17
TP_LAN0_CTRL1.8V
31 30
26 25
24 23
20 19
LAN0_RSET
33 18
TP_LAN0_HSDAC+
36
TP_LAN0_HSDAC-
35
6
8
9
R5C9 0
5% 0402_R
2
R5C8 0
5% 0402_R
EMPTY
1EMPTY
2
1
Wed Jan 16 11:23:04 2008
C5B2
1
2
C5B6 .1UF
0402_R X7R 16V 10%
1
2
.1UF
0402_R X7R 16V 10%
+DVDD_LAN0
1
0402_R
R5B1
22
C4B91
0402_R X7R 16V
10%2
C4B10
1
.1UF
0402_R0402_R X7R 16V
10%2
5%
C5B101 .1UF
0402_R X7R 16V
10%2
C5B9 .1UF
X7R 16V 10%
C5C1
1
.1UF
0402_R X7R 16V
10%210%2
2
1%
+3.3V_DUAL
2
C16B11 .01UF
0402_R X7R 16V
10%2
C4B11
1
.1UF
0402_R X7R 16V 10%
2
L4C1
30
2
1
FB
0603_R1500MA
C4C91 10UF
0805_R X5R 10V
10%2 10%2
RGMII0_INTR*
1
C4C10 10UF
0805_R X5R 10V
10%2
2
1
2 10%
R5B4 10K
5% 0402_R
C5B81 .1UF.1UF
0402_R X7R 16V
C4B8
1
.1UF
0402_R X7R 16V 10%
2
+3.3V_DUAL
+3.3V_DUAL
C4B4
1
.1UF
0402_R X7R 16V
10/11
1
2
C5B1 .1UF
0402_R X7R 16V 10%
C5B5
1
.1UF
0402_R X7R 16V 10%
2
EMPTY
1 C6B1
10UF
0805_R X5R
6.3V
20%2
19D6<
C16B2
1
.1UF
0402_R X7R 16V 10%
2
2
1
LAN0_CT
C5B13
1
0.1UF
0402_R X5R 10V 10%
2
EMPTY
EMPTY
GBIT LAN
+1.8V_DUAL_LAN0
1
R6B3 0
5% 0603_R
9 10
11 12
13 14
15 16
17
.01UF
0402_R X7R 16V
10%2
1
C5B721C5B11 .01UF
0402_R X7R 16V 10%
J6A1 THR_R USBX2_RJ45 USBX2_RJ45_GIG_E_RES
192221
C6B4
C6B5
0.1UF
0402_R X5R 10V
10%2
1
0.1UF
0402_R X5R 10V
10%2
18 23 24 29 30
I397
20
TP_LAN0_GRN_LED_AN
TP_LAN0_GRN_LED_CAT
EMPTY
34A6>
EMI CAPS
+3.3V_DUAL
C6B71 .1UF
0402_R X7R 16V
10%2
6.0 34602-7R177-0000-F00
Page 35
IN
IN
2101
9
IN
BI
KEYBOARD (PURPLE)
3
56
4
1
MOUSE (GREEN)
2
9
11
78
12
10
SHLD SHLD SHLD SHLD SHLD
GND PWR CLK
GND PWR CLK
DATA
DATA NC
NC
NC
NC
1
2
THERM
12121
2
BIBIBIBIBIBIBI
BI
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
REMOVE FOR PRODUCTION
39D2<>
39D6<
17B2<>
17B1>
LPC_AD<3..0>
LPC_FRAME*
0 1 2 3
HDR2X5KEY6
1 3 5 7 9
J1H1 THR_R
I270
+3.3V
LPC_CLK_FLASH
2 4
8
10
LPC_RST_FLASH*
17A2>
17A2>
10/16
+5V_DUAL
1206_R
RT10B1
1.5A
1
2
6V
KEYBRD_PWR1
3000MA
1
0805_R
L10A130
2
FB
KEYBRD_PWR2
19E5<
19E5< 37A7>
19E5>
19E5>
MCP_KB_DA
39B2>
HDA_SDIN_1
39C2>
39C2>
39C2>
MCP_MS_DA
MCP_MS_CK
RP9A1
1
0
SIO_KB_DA
RP9A1
2
0
SIO_KB_CK
RP9A1
3
0
SIO_MS_DA
SIO_MS_CK
RP9A1
4
0
C10A5
1
C10A61
470PF
.1UF
0402_R X7R 16V
10%2
KBDATA_FB
KBCLOCK_FB
MSDATA_FB
MSCLOCK_FB
C10A3
1
C10A2
1
2
470PF
0402_R X7R 50V 10%
2
470PF
0402_R X7R 50V 10%
2
0402_R X7R 50V 10%
C10A1
1
470PF
0402_R X7R 50V 10%
2
J10A1
CONN_R
15U
TP_J12A1_2
TP_J12A1_6
TP_J12A1_8
TP_J12A1_12
1 2 3 4 5 6
13 14 15 16 17
7 8 9 10
11
12
I92
PS2
LPC HEADER & ROM SOCKET, PS2
6.0 35602-7R177-0000-F00
4.7K
2
EMPTY
CR10B2
3
BAV99
I230
1
7
RP10A1
4.7K
2
2
8
RP10A1
1
CR9B3
3
BAV99
4.7K
EMPTY
I229
1
60OHM
4
.25
300MA
60OHM
2
.25
300MA
60OHM
3
.25
300MA
60OHM
1
.25
300MA
LP10A1
1206_R
LP10A1
1206_R
LP10A1
1206_R
LP10A1
1206_R
5
25%
7
25%
6
25%
8
25%
1
2 10%
C10A4 470PF
0402_R X7R 50V
5
RP10A1
4.7K
EMPTY
CR10A1 BAV99
I232
1
4
2
8
EMPTY
RP9A2
8
1
0
7
6
5
RP9A2
2
0
RP9A2
3
0
RP9A2
4
0
EMPTY
7
EMPTY
6
EMPTY
5
KBDATA_R
KBCLOCK_R
MSDATA_R
MSCLOCK_R
3
2
EMPTY
CR10B1
3
BAV99
I231
1
6
RP10A1
3
Tue Feb 05 14:00:27 2008
Page 36
THERM
16
GND
11
SDA
GND
GND
HSYNC
VSYNC
VCC
GND
SCL
15
17
RED
GRN
BLU
GND
6
10
1
5
12121
2
IN
1
2
GND
D1+
D1-
GND
CK+
RSVD
CK-
SDA
+5V
GND
TYPE A
D2+
D2-
GND
D0+
D0-
GND
CEC
SCL
GND
HPD
IN
IN
D
G
S
12121
2
INININBIINININININININININ
THERM
IN
D
G
S
2
1
OUTININ
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
2 22
CR8B2
3
BAV99
R8A9 150
1% 0603_R
1
EMPTY
I114
R8A10 150
1% 0603_R
CR8B3
3
BAV99
1
EMPTY
I115
12
15C6>
15C6>
15C7>
15C7>
15C3<>
15C7>
15C3>
DAC_HSYNC DAC_VSYNC DAC_RED DAC_GREEN
DDC_DATA DAC_BLUE
DDC_CLK
+3.3V
11/5
36A3<
+3.3V_DUAL
2
R7A2 27K
5%
EMPTY
0402_R
1
19C3<
15C3>
15C3<>
HDMI_CEC
HDMI_DDC_CLK HDMI_DDC_DATA
15C3<
HOTPLUG DETECTION
1
0402_R
R7A1
33
5%
HPLUG_DET2
+V_DDC_PULLUP
+3.3V
1
22
2
R8A4 10K
5% 0402_R
1
1
CR8B1
3
BAV99
212
EMPTY
Q7A1 2N7002 S23_R
3
CR8A1
R8A8 150
1% 0603_R
EMPTY
I111
1
600
1
350MA
+3.3V
3
I35
15E3>
15E3>
15E3>
15E3>
EMPTY
L7A1
0603_R
R8A5
1
0402_R
2
BAV99
S23_R
1
C8A8
1
5.6PF
0402_R C0G 50V
2
5%
2
FB
1K
100NH
300MA
2
1
2
5%
U9A1
74ACT08MTC
TSSOP14_R
L8A5
2
1
SMD
0603_R
HDMI_TXD1P HDMI_TXD1N
HDMI_TXD0P
C8A9
1
5.6PF
0402_R C0G 50V
2
C8A10
1
5.6PF
0402_R C0G 50V
2
5%5%
90OHM
90OHM
300MA
1
0402_R
1
.3A
2
.3A
1
0402_R
1 2
100NH
1
R7A5
2012_R
2012_R
R7A4
0603_R SMD
2
5%
L7A2
0
4
CM_CHOKE
L7A2
3
CM_CHOKE
2
5%
0
HDMI_TXD0N
15E3>
15E3>
2
R7A3
R8A2
2.7K
2.7K
5%
5%
0603_R
0603_R
1
1
0402_R
500MA
R8A3
180
1
33
0603_R
5%
2
L8A4
1
0402_R
2
FB
R8A1
2
5%
33
2000MA
2000MA
1
1
220
220
0603_R
0603_R
L8A1
L8A2
2
FB
2
FB
C8A2
1
470PF
0402_R X7R 50V 10%
2
R9B6
0603_R+5V
14
3
I98
U9A17
74ACT08MTC
TSSOP14_R
L8A6
2
C8A11
1
5.6PF
0402_R C0G
50V2 5%
EMPTY
EMPTY
HDMI_TXC0P HDMI_TXC0N
HDMI_CEC_C HDMI_DDC_CLK_R HDMI_DDC_DATA_R
+5V
RT8B1
1.5A
1
6V1206_R
Tue Mar 18 13:58:55 2008
21
5%
0
0402_R
C8A12
1
5.6PF
0402_R C0G
2 50V
5%
2
EMPTY
R9B5
1
100NH
300MA
0402_R
90OHM
90OHM
.3A
0402_R
33
1
2
1
1
5%
13 12
1
R14A4
2012_R.3A
2012_R
R14A3
1
0402_R
2
0603_R
L14A2
0
L14A2
0
R7B10
47K
1
0603_R
L8A7
2
SMD
EMPTY
2
5%
3
CM_CHOKE
4
CM_CHOKE
2
5%
5%
2
R9B2
0
1
2
EMPTY
EMPTY
2
5%
I91
C8A13
5.6PF
0402_R C0G 50V 5%
12
0402_R
Q8A1
1
2N7002 S23_R
+5V
1
0402_R
90OHM
1
.3A
90OHM
2
1
0402_R
R7B11
10K
3
RESERVED FOR FERRITE BEAD
L9A2
27NH
2
1
SMD
0603_R
500MA
111
0402_R
2
15E3>
15E3>
R14A2
2012_R
2012_R.3A
R14A1
2
5%
R9B1
3
EMPTY
2
5%
L14A1
0
4
CM_CHOKE
L14A1
3
CM_CHOKE
2
5%
0
+12V
2
5%
33
EMPTY
CR9A1 BAV99
I81
EMPTY
HDMI_TXD2P HDMI_TXD2N
500MA
21
27NH
1
0603_R
CR9B2
3
BAV99
L9A1
2
SMD
EMPTY
I79
1
+V_DDC_PULLUP
L8A3
42
1 2
FB
0805_R
4000MA
C8A1
1
2
0402_R X7R
.01UF
16V 10%
R9A4
2
1
5%
0402_R
33
R9A1
2
1
5%
0402_R
33
12PF
0402_R C0G 50V
1
1
2
1
R7A7
2012_R
2012_R
R7A6
C9A41C9A3 12PF
0402_R C0G 50V 5%
25%2
EMPTY
2
5%
L7A3
0
4
CM_CHOKE
L7A390OHM
3
CM_CHOKE
2
5%
0
3
+5V
EMPTY
1
0402_R
90OHM
.3A
.3A
0402_R
HDMI_TXD1P_C HDMI_TXD1N_C
HDMI_TXD0P_C HDMI_TXD0N_C
HDMI_TXC0P_C HDMI_TXC0N_C
36B7<
1
R9A2
2.7K
5%
0603_R
EMPTY
CR9A2 BAV99
I67
12
EMPTY
CR9B1
3
BAV99
I69
1
2
HDMI_TXD2P_C HDMI_TXD2N_C
10 9
+5V
1
R9A3
2.7K
5%
0603_R
22
RED_A
EMICAP1
GREEN_A
DDC_SDA BLUE_A
BUF_HSYNC_A
EMICAP2
BUF_VSYNC_A
DDC_SCL
EMPTY
C9A6
470PF
0603_R C0G 50V 5%
J7A2
CON_HDMI_A SMT_R
EMPTY
C8A7
1
470PF
0603_R C0G 50V
2
5%
EMPTY
1
2
EMPTY
C9A2
1
470PF
0603_R C0G 50V
2
5%
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
1
2
I1
20 21 22 23
RGB & HDMI PORT
C9A1
470PF
0603_R C0G 50V 5%
1 11
2 12
3 13
4 14 15
U9A1
74ACT08MTC
TSSOP14_R
8
I45
J8A2
I56
VGACONN
DB15E_R
C8A3
1
470PF
0402_R X7R 50V 10%
2
U9A1
74ACT08MTC
TSSOP14_R 4 5
6
I44
+5V
16
1
RT8B2
1.5A
1206_R
6V
2
1
L8B1
FB
42
2
C8A14
1
0.1UF
0603_R X7R 16V
2
10%
10
17
6
7
4000MA 0805_R
8
VGAPWR_FB
9
5
+5V
C8B2
1
2
.01UF
0402_R X7R 16V 10%
6.0602-7R177-0000-F00
36
Page 37
CAT AN
ADJ/GND
VOUT_TAB
VOUT_PINVIN
IN
OUT
OUTININ
CATAN
OUT
OUT
OUTINOUT
OUTINOUT
OUTINOUT
OUT
OUT
615
GND
GND
SIG
IN
OUTININININ
OUT
OUTININ
VREFO37
AVDD
AVDD
FRONT-R
FRONT-L
VREF
MIC2-VREFO
MIC1-VREFO
VREFO32
LINE1-VREFO
SURR-L
SPDIFO
SPDIFI/EAPD
NC
SENSE_B
AVSS AVSS
CENTER
LFE
JDREF
SURR-R
SIDESURR-R
LINE2-VREFO
SIDESURR-L
GPIO0/SPDIFO2
DVDD
SDATA-IN
SDATA-OUT
DVDD-IO
SENSE_A LINE2-L LINE2-R
RESET*
MIC2-L
SYNC
BEEP
MIC2-R
LINE1-R
GPIO1 LINE1-L
MIC1-R MIC1-L CD-L CD-R
BCLK
CD-GND
DVSS
DVSS
ININOUT
OUT
OUTINININOUTINININOUT
2101
9
INININ
IN
IO_PWR
GND GND
GND
+3.3V_DUAL
+3.3V_CORE
+12V
RST*
BCLK SYNC
RSVD
RSVD
RSVD
SDI
SDO
ININOUT
OUT
OUT
OUT
OUT
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
19F7<
19E5> 43B4<
IF WANT TO BUILD THIS FUNCTION, IT MUST USE THE SIO'S KEYBOARD FUNCTION
HDA_SDIN_0
SPEAKER
38C8>
38B8>
38C4>
38D7<
37D4>
37C7<
37C7<
37C7>
37D7>
37C2<
30 L2A1
21
FB0603_R1500MA
R3B5
2
1
5%
0402_R
10K
EMPTY
FRONT_JD MIC1_JD
SURR_BACK_JD LINEIN_JD
FP_MICVREF
FP_MIC2_L FP_MIC2_R FP_OUT_R FP_OUT_L
FP_IO_JD
37C4>
SPEAKER_R
C3B4
1
100PF
0402_R C0G 50V 5%
2
LINE2_VREFO
1
0402_R
1
0402_R
1
0402_R
19E5< 35B8<>
2
1
R3B2
R3B4 1K
5% 0402_R
R4A6
20K
R4A5
10K
RDL_R
ALUM
25V 20%
22
2
1
2
5%
C3A14
1UF
2
1%
2
1%
C2A3
1
1000PF
0402_R X7R 16V
2
10%
2
4.7UF
C3A1
100UF
1 C3A2
2
C2A1
1UF
0402_R X5R
6.3V 10%
1
0402_R
0402_R
1
0603_R X5R 16V 10%
R4A4
5.11K
R5A1
39.2K
BAT54A
CR2A1
3
S23_R
I244
2
37A6< 37A6<
2
1%
21
1%
37A6<
2
1
1
1206_R X7R
C2A2
16V
2
10%
4.7UF
C3B1
1
RDL_R
ALUM
100UF
25V 20%
3
S23_R
I251
HDA_SDIN_1
FP_MICVREF_D1
FP_MICVREF_D2
1
1206_R X7R 16V
1
10%
2
BAT54A
CR2A2
2
1
19F7> 37A6<
19E8> 19E8>
37B8> 37B8> 37B8> 37B8> 38B8> 38B8>
37B4<
38D7< 38D7< 19F6>
1
0402_R
R2A10
2
1%
0402_R
75
LINE2_VREFO_D1
LINE2_VREFO_D2
37C7< 37D7< 37D7< 37D7<
+3.3V
C3A8
1
.1UF
0402_R X7R 16V
10%2
10/8
R2A5
4.7K
R2A7
1
0402_R
1
0402_R
2
5%
0402_R
75
19F6> 19E8> 19E8> 19F7>
R1D1
C3A6
1
C3A10
1
2
HDA_SDOUT HDA_SDIN0_R HDA_SYNC HDA_RST* PC_BEEP SENSE_A FP_OUT_L FP_OUT_R FP_MIC2_L FP_MIC2_R AUD_MIC1_R AUD_MIC1_L
R2A6
1
4.7K
2
1%
1
0402_R
2
5%
22
.1UF
0402_R X7R 16V
2
10%
TP_HDA_CDL TP_HDA_CDR SPDIF_OUT_HDR TP_HDA_GPIO1
AUD_IN_L AUD_IN_R HDA_BITCLK
TP_HDA_CDGND
2
5%
FP_MIC2R_L
FP_MIC2R_R
FP_OUTR_R
FP_OUTR_L
R3A1
2
5%
4.7K
1
0402_R
4.7K
R2A8
10UF
0805_R X5R 10V 10%
1 9 5 8 10 11 12 13 14 15 16 17 22 21 18 20 2 3 23 24 6
4 7 19
2
5%
2
2
R3A2
22K
5%
0402_R
1
1
HDA_BITCLK HDA_RST* HDA_SYNC HDA_SDOUT HDA_SDIN1_R
U3A1 TQFP_R
I510
J2B2 THR_R
1 3 5 7 9
I288
HDR2X5KEY8
R2A9 22K
5% 0402_R
+3.3V
2
R2A4 10K
1% 0402_R
1
2
FP_AUDIO_PRESENCE*
4
FP_MIC2_JD_R
6
FP_OUT_JD_R
10
1 3 5 7 9 11 13 15
C3A15
1
.1UF
0402_R X7R 16V
2
10%
2
ALC888S
25 38
AUDAMPIN_L
35
AUDAMPIN_R
36
TP_HDA_PIN37
37
MIC1_VREFO_R
32
TP_HDALINE1_VREFO_L
29
FP_MICVREF
30
AUDIO_VREF
27
MIC1_VREFO_L
28
SURR_BACK_L
39
SURR_BACK_R
41
JDREF
40
SPDIF_IN_HDR
47
CEN_OUT
43
LFE_OUT
44
SPDIFO_RCA
48
SURR_SIDE_R
46
SURR_SIDE_L
45
LINE2_VREFO
31
HDA_DCVOL
33
SENSE_B
34 26 42
GPIO19 INTERNAL PULL 15K TO +3.3V
EMPTY
17B3<
R2A1
39.2K
1% 0402_R
2
R2A2 20K
1% 0402_R
11
2
J1D1 THR_R COLOR=BLACK GENDER=MALE
AZALIADIGITAL_HEADER
I566
Wed Jan 16 11:23:11 2008
C3A51 .1UF
0402_R X7R 16V 10%
10 14
16
+5VA
C3A16
1
10UF
0805_R X5R 10V 10%
2
37C4<
37C7>
+3.3V_DUAL
+12V
+3.3V
2 4 6 8
CR1A1
1
S23_R
MMBD4148
38C8< 38C8<
38A8<
37B8<
38B8< 38C4> 38C4>
37B4> 38D4< 38D4<
38B4> 38B4> 37A8<
SPDIF_OUT_HDR
3
C3A11
2
10UF
R3A3
0603_R
20.0K
0402_R
SPDIF_IN_HDR
37C2>
R1A1
2
1+12V
5%
0805_R
10
L1A1
30
2
1
FB
0603_R
1500MA
1
0805_R X5R 10V 10%
21
1%
R3A4
2
1
1%
10
1
100UF
RDL_R ALUM 25V
20%2
SPDIF_OUT_OPT
R3A7
2
1
1%0402_R
10K
R3A5
2
1
5%
0402_R
0
R3A8
2
1
1%
0402_R
5.11K
R2A3
1
0402_R101%
EMPTY
C2A8
.01UF
SPDIF_OUT_HDRC
0402_R X7R 16V 10%
2 1
SPDIFO_RCA
U1A1 SOT-223_R ADJ B130LAW
AMS1117_SOT223
3
C1A1
1C1A3
1UF
0805_R X7R 16V 10%
2
2
1
CEN_LFE_JD FP_IO_JD SURR_SIDE_JD
+5V
1200MA
+3.3V
EMPTY
2
R2A15 12K
5% 0402_R
1
SPDIF_IN_HDR_RC
2
2
R2A14 10K
5% 0402_R
1
R2A11
0402_R
C8A6
SPDIFO_RCA_L
1
2
0402_R X7R
.01UF
16V 10%
10
2 4
2
I4581
R1A6 301
1% 0402_R
R2
38A5<
37A3<
L2A2
120
1
0402_R
C2A11
2
.01UF
SPDIF_OUT_HDR_R
21
1%
2
1
1
NOTE: VOUT=1.25V*(1+R2/R1)+IADJ*R2 IADJ=60UA
38D4>
37B8>
38B4>
+5V_SPDIF_HDR
2
FB
VOLTAGE=5 V
SPDIF_IN_HDR_R
1
0402_R X7R 16V
1
10%
2
R2A12 10K
5% 0402_R
R8A7
1
0402_R
100
AUDIO CODEC
R1A7 100
1% 0402_R
R1
C2A7
1
1UF
0402_R X5R
6.3V 10%
2
C2A10 100PF
0402_R C0G 50V 5%
1
2 5%
SPDIFO_RCA_OUT
2
5%
2
R8A6 220
5% 0402_R
1
C1A4
1
.1UF
0402_R X7R 16V 10%
2
2
1
C2A6 100PF
0402_R C0G 50V
1
2
R2A13 75
1% 0402_R
1
+5VA
C2A5 .1UF
0402_R X7R 16V 10%
C8A5 100PF
0402_R C0G 50V
5%2
C2A41 47UF
RDL_R ALUM 25V
20%2
1
+5V_DUAL
CR2A3
2
SOD123_R
1 3 5
HDR2X3KEY2
J8A1
2 1
3 4
RCA_JACK HORIZ_OPEN_R COLOR=YELLOW I577
J2A1 THR_R
I543
6.0602-7R177-0000-F00
4 6
37
Page 38
0603_R
TIP
CENTER / LFE OUT (ORANGE)
RING
GND
JDET
LT
RT
SLEEVE
TIP
REAR SURR (BLACK)
RING
GND
JDET
LT
RT
SLEEVE
OUTININ
OUT
OUT
OUT
SIDE SURR (GRAY)
TIP
RING
GND
JDET
LT
RT
SLEEVE
OUT
OUT
OUT
VIN
VCC
GND
TIP
LINE IN (BLUE)
RING
GND
JDET
LT
RT
SLEEVE
TIP
FNT OUT (GREEN)
RING
GND
JDET
LT
RT
SLEEVE
INININ
OUTININ
IN
MIC IN (PINK)
TIP
RING
LT
JDET
GND
RT
SLEEVE
OUTINOUT
OUT
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
0603_R
L4A5
L3A3
2
FB
2
FB
LFE_L
LFE_R
C3A241 100PF
0402_R C0G 50V
5%2
1
C4A2 100PF
0402_R C0G 50V
5%2
J5A1
THR_R
32 33 34
35 1
AUDIO_JACK_6PORT
I227
37C8<
37C7>
37C7>
LINEIN_JD
AUD_IN_L
AUD_IN_R
2
2
C3A20
22UF
C3A19
22UF
1
1206_R X5R
6.3V 20%
1
1206_R X5R
6.3V 20%
L4A3
350MA
350MA
1
1
600
600
0603_R
0603_R
L4A2
2
FB
2
FB
AUDIN_L
AUDIN_R
C4A4
1
100PF
0402_R C0G 50V 5%
2
1
2
C4A5 100PF
0402_R C0G 50V 5%
J5A1
THR_R
62 63 64
65 41
AUDIO_JACK_6PORT
I269
37C2<
37C4>
37C4>
CEN_LFE_JD CEN_OUT
LFE_OUT
1206_R
6.3V
1206_R
6.3V
1
X5R 20%
1
X5R 20%
C3A13
22UF
C3A7
22UF
600
2
2
350MA
350MA
1
600
1
PLACE NEAR CONN
PLACE NEAR CONN
37D8<
37D4>
37D4>
37C8<
37C4>
37C7<
37C7<
37D4>
FRONT_JD
AUDAMPIN_L
AUDAMPIN_R
INCREASE VREF CAP IF
POP IS PRESENT
RDL_R
ALUM
RDL_R
ALUM
1
25V 20%
25V 20%
C4A1
100UF
C3A21
100UF
MIC1_JD
2
2
1
0603_R
C3A18
22UF
C3A17
22UF
1
0603_R
R3A9
2.2K
R4A3
2.2K
MIC1_VREFO_L
AUD_MIC1_L
AUD_MIC1_R
MIC1_VREFO_R
NOTE: MIC GROUND ROUT BACK TO CODEC ALONG WITH MIC_TRACE. TIE MIC_GND TO AGND NEAR CODEC
1
1206_R X5R
6.3V 20%
1
1206_R X5R
6.3V 20%
FB_AUDOUTR_L
2
FB_AUDOUTR_R
21
2
5%
2
5%
R4A1
2
1
1%
0402_R
75
R3A10
21
1%
0402_R
75
2
R3A11 22K
5% 0402_R
1
L3A4
350MA
350MA
600
1
600
1
0603_R
0603_R
L4A8
2
FB
2
FB
AUD_MIC_1L
AUD_MIC_1R
PLACE NEAR CONN
J5A1
L4A1
600
1
0603_R
350MA
600
1
350MA
2
R4A2 22K
5% 0402_R
1
FB_AUDOUT_L
2
FB
L4A4
FB_AUDOUT_R
2
FB0603_R
1
2
100PF
0402_R C0G 50V 5%
1C4A6
C4A3 100PF
0402_R C0G 50V
5%2
52 53 54
55 41
AUDIO_JACK_6PORT
THR_R
I271
37C8<
37C4<
37C4<
PLACE NEAR CONN
37C2<
37C4>
J5A1
2
C4A91 100PF
0402_R C0G 50V 5%
2
C3A251 100PF
0402_R C0G 50V 5%
THR_R
42 43 44
45 41
AUDIO_JACK_6PORT
I285
66 67 68 69
+5V_SPDIF
VOLTAGE=5.00000
C9A81 1UF
0603_R X5R 16V 10%
2
2
C9A71 .1UF
0402_R X7R 16V 10%
37C4>
L9A3
60
2
1
FB
0603_R
800MA
3PIN_DOOR_R
13.2MBPS
+5V
SPDIF_TX
J9A1
SURR_BACK_JD
SURR_BACK_L
SURR_BACK_R
SURR_SIDE_JD
SURR_SIDE_L
SURR_SIDE_R
1206_R
6.3V
1206_R
6.3V
1206_R
6.3V
1206_R
6.3V
1
X5R 20%
1
X5R 20%
1
X5R 20%
X5R 20%
C3A4
22UF
C3A3
22UF
C3A12
22UF
C3A9
22UF
J5A1
L4A7
600
2
21
350MA
350MA
1
600
1
0603_R
0603_R
L4A6
2
FB
2
FB
SURRB_L
SURRB_R
C4A7
1
100PF
0402_R C0G 50V
5%2
C4A81 100PF
0402_R C0G 50V
5%2
22 23 24
25 1
AUDIO_JACK_6PORT
THR_R
I233
PLACE NEAR CONN
J5A1
L3A2
600
2
2
350MA
350MA
1
600
1
0603_R
0603_R
L3A1
2
FB
2
FB
SURRS_L
SURRS_R
1 C3A22
100PF
0402_R C0G 50V
5%2
C3A231 100PF
0402_R C0G 50V
5%2
2 3 4
5 1
AUDIO_JACK_6PORT
THR_R
I239
PLACE NEAR CONN
2
37C2>
SPDIF_OUT_OPT
3 1
I323
AUDIO CODEC JACKS
Wed Jan 16 11:23:13 2008
6.0602-7R177-0000-F00 38
Page 39
ININBIININBIOUT
OUT
OUTINOUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTBIOUT
OUT
OUTBIOUT
OUTININININININBIINININININ
IN
AN
CAT
KBC I/F
ACPI I/F
LPC I/F
GPIO
FDC I/F
PARALLEL PORT I/F
(2 PORTS)
SERIAL PORT I/F
HARDWARE MONITOR I/F
3VSB
LAD0
LAD1
LDRQ* GP22/SCE GP23/SCK
LAD2
LAD3
SERIRQ
PME*
BEEP/SO
RSTOUT0*
RSTOUT1*
VBAT
VREF
PSOUT*/GP57
SYSFANOUT
CPUFANOUT0
VTT
PECISB
NC
NC
PECI
SST
KBRST
GA20M
GP20/CPUFANOUT1
SMI*/OVT* AUXFANOUT
KCLK/GP27 KDAT/GP26
MDAT/GP24
MCLK/GP25
PLED/FAN_SET
WD*
WE*
DIR*
STEP*
HEAD*
MOA*
DSA*
DRVDEN0
PD6
PD7 PD5
RTSA*/GP65/HEFRAS
DTRA*/GP64/PENROM*
SOUTA/GP62/PENKBC
GP45/RTSB* GP44/DTRB*
INIT*
AFD*
SLIN*
PD1 PD0
PD3
PD4 PD2
STB*
GP42/SOUTB/IRTX/FAN_SET2
3VCC 3VCC
RSTOUT2*/GP32/SCL RSTOUT3*/GP33/SDA
CASEOPEN*
LFRAME*
PSIN*/GP56
PCICLK LRESET*
AVCC IOCLK
3VCC
VIN3 VIN2
CPUVCORE AUXTIN
CPUFANIN0 SYSFANIN GP21/CPUFANIN1
CPUTIN
AUXFANIN0
SI/AUXFANIN1
SYSTIN
VID5
VID6
VID7
CPUD-
VIN1 VIN0
VID4 VID3
VID0
VID1
VID2
RDATA*
SINA/GP63 CTSA*/GP67
RIA*/GP60
DCDA*/GP61
GP47/CTSB*
GP43/SINB/IRRX
DSRA*/GP66
GP40/RIB*
GP41/DCDB* GP46/DSRB*
DSKCHG*
INDEX*
TRAK0*
WP*
ACK* PE
BUSY
GP50/WDTO*/EN_VRM10
RSMRST*/GP51 RSTOUT4*/GP34
PSON*/GP53
SUSB*/GP52 PWROK/GP54
GP55/SUSLED
GP31
GP30
GP35
SLCT ERR*
VSS
VSS
GP36 GP37
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUTINININININOUT
OUT
OUT
OUT
OUTININ
OUT
OUT
OUT
OUT
OUT
THERM
INININININININ
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
+12V
R2H3
1
1%
0402_R
56.2K R2H8
1
1%
0402_R
10K
AGND_SIO
+5V
R2H4
1
1%
0402_R
22.1K R2H9
1
1%
0402_R
10K
AGND_SIO
+V_CPU
39C2>
39B8<
SIO_AUXTIN
1
AGND_SIO
SIO_VREF CPU_THERMDA
CPU_THERMDC
19C3>
8D5>
1
RT2H1 10K
0603_R
NA_ EMPTY3 10%2
2
39B8< 39C2>
9C4>
9C4>
MCP7A_THERM_DIODE_P
CPU_THERMDA1
10/15
8D5>
19C3>
CPU_THERMDC1
MCP7A_THERM_DIODE_N
PLACE NEAR PWR PINS
+3.3V
C2J4
C1J3
1
.1UF
0402_R X7R 16V
10%2 10%2 20%2 10%2 10%2 10%2
1
.1UF
0402_R X7R 16V
2
2
2
2
1
0402_R
SIO_VREF
CR2H1 MMBD4148
S23_R
R2H23
C2J31 22UF
RDL_R ALUM 25V
29D7< 28C6<
30D7<
+1.8V_SUS
AGND_SIO
R2H6
10K
1
0402_R
1
0402_R
1
0402_R
1
0402_R
R2H22
C1H4
1
.1UF
0402_R X7R 16V
11C3<>
15A4<> 19C8>
29D7<>
30D7<>
5%
R2H25
R2H24
46C7<
43C2>
R2H11
1
0402_R
10K
R2H10
0402_R
40.2K
2
0402_R
C2H4
1
2200PF
0402_R X7R 25V
1
2
EMPTY
5%
0
2
5%
1
0
2 10%
2
5%
0
2
5%
EMPTY
0
+3.3V_DUAL
1
.1UF
0402_R X7R 16V
39D2<
2
1%
21
1%
R2H7
1
10K
R2H1
1
0402_R
R2H2
1
0402_R
C2H2 2200PF
0402_R X7R 25V
10%2
ISO2H2
1
25MIL
C2H1 2200PF
0402_R X7R 25V
ISO2H1
1
25MIL
15K
15K
19C8>
11A7<> 28C6<> 31A7<>
2
5%
EMPTY
2
5%
2
5%
EMPTY
2
0%
0
AGND_SIO
2
0%
0
AGND_SIO
C2J61C2J5 .1UF
0402_R X7R 16V
15B4< 11C3< 46C7< 31A7<
BATT_PWR_R
+1.1V_CORE
45B2<
44A1> 11A7<
0402_R
AGND_SIO
10/23
41B7>
12/13
44D8<
46B8<
AGND_SIO
35D3<
1
0402_R
R2H5
21
1%
10K
41B7>
41A7> 41B7> 41C7>
19D3>
C2H3
2
.1UF
19D1> 17A2> 17B1> 17B2>
SIO_PSIN*
SMB_SCL SMB_SDA
R2J1
2
5%
2M
42C4> 42A2> 42A3> 40B5>
40D8> 40C8> 40D8> 40C8< 40D8> 48A1< 49A6< 48A1< 48A1< 49A6<
41A7> 41A7>
41B7> 41A7>
41A5>
47A7< 47A7< 45A6< 15B4< 48B6< 19C2> 44D8< 44B2< 44B2< 48B6< 48B6<
1
0402_R X7R 16V 10%
MCP7A_CORE_AUX_OV0 MCP7A_CORE_AUX_OV1
MCP7A_CORE_AUX_OV2
MCP7A_CORE_OV2
MCP7A_CORE_OV1 MCP7A_CORE_OV0
30
1
1500MA
SIO_AVCC
BUF_SIO_CLK LPC_CLK_SIO LPC_FRAME*
LPC_RST_SIO*
SIO_CASEOPEN*
SIO_VIN3_12V SIO_VIN2_5V SIO_VIN1_1_2V SIO_VIN0_1_8V SIO_CPUVCORE
TP_VID7 TP_VID6 TP_VID5 TP_VID4 TP_VID3 TP_VID2 TP_VID1 TP_VID0 TP_AUXFANIN1
SIO_AUXFAN_TACH SIO_CPUFAN_TACH SIO_SYSFAN_TACH
SIO_BOARD_ID1
COM_RXD1 COM_CTS1* COM_DCD1* COM_RI1* COM_DSR1*
CPU_VTT_OV0
CPU_VTT_OV1
SIO_LPT_BUSY SIO_LPT_ACK* SIO_LPT_PE SIO_LPT_SLCT SIO_LPT_ERR*
MEM_OV2 MEM_OV1 SIO_RSMRST* SIO_HDCP_WP
SLP_S3* PS_ON_R* GRN_PWRLED YLW_STBYLED
SIO_WDTO*
L2H1
2
1
2
FB0603_R
R2J2 1K
5% 0402_R
EMPTY
U2J2
12 28 48 95
18 21 29 30
PQFP-128_R
+3.3V
68 90
89 76 96
97 98 99 100 102 103 105 104 121 122 123 124 125 126 127 128 58 111 112 113 119
15 17 14 13 3
53 49 56 57 50 82 78 84 85 79
33 34 32 31 45
92 91 75 88 87 73 72 71 70 69 64 77
20 55
I752
30
1
0603_R
1500MA
AGND_SIO
Wed Jan 16 11:23:15 2008
W83627DH
L2H2
2
FB
+3.3V_DUAL
61
LPC_AD<3..0>
3
24
2
25
1
26
0
27
LPC_SERIRQ
23
LPC_DRQ0*
22
SIO_BOARD_ID2
19
SIO_BOARD_DEBUG
2
SIO_PME*
86
BATT_PWR_R
74
SIO_PSOUT*
67
TP_SIO_RSTOUT1*
93
TP_SIO_RSTOUT0*
94
SIO_VREF
101
SIO_SYSFAN_CNTL
116
SIO_CPUFAN_CNTL
115
TP_SIO_BEEP
118
EXT_SMI*
5
SIO_AUXFAN_CNTL
7
SIO_BOARD_ID0
120
FAN_SET
117
TP_SIO_NC109
109
TP_SIO_NC110
110
TP_SIO_PECISB
106 107
CPU_PECI_SPIO
108
SIO_SST
114
SIO_MS_CK
65
SIO_MS_DA
66
SIO_KB_CK
62
SIO_KB_DA
63
SIO_KBRST*
60
A20GATE
59 11
10 16
8 9 6 4 1
COM_TXD1
54
COM_RTS1*
51
COM_DTR1*
52
FAN_SET2
83
CPU_VTT_OV2
80
MEM_OV0
81
7
35
6
36
5
37
4
38
3
39
2
40
1
41 42 43 44 46 47
SIO_LPT_PD<7..0>
0
SIO_LPT_SLCTIN* SIO_LPT_INIT* SIO_LPT_ALF* SIO_LPT_STROBE*
10/23
R2H21
1
0402_R
R2H20
0402_R
2
5%
10K
12/13
1
10K
49A6< 47A7<
SIO
40B5> 40B1>
39C7<
2
5%
+1.2V_VTT
17B3<
17B3<
19E2>
44B3<
39B8< 42A8< 42B4<
19E2> 42C8<
9D8<
35A7<> 35A7<> 35B7<> 35B7<> 19E3< 19E3<
0402_R
EMPTY
1
R2J4
41C7<
41C7< 41C7<
35D3<> 17B2<>
19E3<
43C2>
19E3<
40B5>
10K
41D7<
41C7<
C2H5
1
2
0402_R X7R
.1UF
16V 10%
AGND_SIO
+3.3V
+1.2V_VTT
1
C2H7 .1UF
0402_R
X7R 16V
2
10%
R2J14 1K
5% 0402_R
+3.3V
2
1
2
11
R2J16
4.7K
5% 0402_R
R2J15 1K
5% 0402_R
+3.3V
2
R2J13
4.7K
5% 0402_R
1
+3.3V
2
5%
2
40C8< 40C8< 40C8<
6.0 39602-7R177-0000-F00
Page 40
1
21
9
OUT
3 2 1
RXRXRXTXRX
RX
TX
TX
OUT
OUT
OUTININ
OUTININ
OUT
OUT
OUT
OUT
OUT
OUTINININOUT
PWR
VCC GND
+12V
-12V
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
2
.1UF
0402_R X7R 16V 10%
1
2
C1C9 470PF
0402_R X7R 50V 10%
EMPTY
+5V
C1C12
1C1C2
.1UF
0402_R X7R 16V 10%
2
J1C1 THR_R
2
1
4
3
6
5
8
7
9
I132
HDR2X5KEY10
YELLOW
C1C11
1
470PF
0402_R X7R 50V 10%
2
EMPTY
REMOVE FOR PRODUCTION
EMPTY
39B6>
COM_DCD1*
EMPTY
39B6>
39B6>
COM_DSR1*
COM_RXD1
RP1C2
2
0
EMPTY
39B1>
39B1>
COM_RTS1*
COM_TXD1
RP1C2
4
0
EMPTY
39B6>
COM_CTS1*
39B1>
COM_DTR1*
RP1C1
2
0
EMPTY
39B6>
COM_RI1*
RP1C1
4
0
RP1C2
1
0
7
RP1C2
3
0
5
EMPTY
RP1C1
1
0
7
RP1C1
3
0
5
8
EMPTY
6
8
EMPTY
6
U1C1 GD75232 TSSOP_R
19
I256
U1C1 GD75232 TSSOP_R
17
I254
15
13
U1C1 GD75232 TSSOP_R
6
I257
U1C1 GD75232 TSSOP_R
8
I251
2
U1C1 GD75232 TSSOP_R
18
I255
4
16
14
I253
I252
U1C1 GD75232 TSSOP_R
U1C1 GD75232 TSSOP_R
3
U1C1 GD75232 TSSOP_R
5
I258
7
912
DCD1
DSR1
RXD1*
TXD1*
CTS1
DTR1
RI1
RTS1
1
2
C1C3 470PF
0402_R X7R 50V 10%
EMPTY
1
2
C1C4 470PF
0402_R X7R 50V 10%
EMPTY
C1C5
1
470PF
0402_R X7R 50V 10%
2
EMPTY
1
2
+12V
C1C10
1
.1UF
0402_R X7R 16V
10%2
PLACE NEAR RS232 TX PINS
C1C8
EMPTY
1
2
470PF
0402_R X7R 50V 10%
C1C6 470PF
0402_R X7R 50V 10%
EMPTY
1
2
C1C7 470PF
0402_R X7R 50V 10%
-12V
EMPTY
EMPTY
R2H18 10K
5% 0402_R
R2H19 0
5% 0402_R
+3.3V
2
1
2
1
R1J3 10K
5% 0402_R
EMPTY
R1J4 0
5% 0402_R
+3.3V
J2H1 THR_R
I291
3
BIOS_DEBUG
2 1
1
0402_R
R2H15
SIO_BOARD_DEBUG
2
5%
0
NOTES=[1-2]
BOARD DEBUG - J2H1 1-2* 2-3
*DEFAULT DEBUG MODE: TELL BIOS TO ENABLE DEBUG MODE
NORMAL DEBUG MODE
39D2<
+3.3V
+3.3V
EMPTY
R2H16 10K
5% 0402_R
R2H17 0
5% 0402_R
2
1
2
11
2
17B8>
17D1>
17D1>
17C3>
17C3>
17D1>
17C3>
MCP_COM_DCD1* MCP_COM_DSR1* MCP_COM_RXD1 MCP_COM_RTS1* MCP_COM_TXD1 MCP_COM_CTS1* MCP_COM_DTR1*
RP1C4
3
0
RP1C4
1
0
RP1C3
3
0
RP1C4
5
4
0
6
RP1C4
7
2
0
8
RP1C3
5
4
0
6
RP1C3
7
2
0
RP1C3
8
1
0
39C2<
39B6<
39D2<
DEFAULT BOARD ID = 101 FOR REV E
SIO_BOARD_ID0 SIO_BOARD_ID1 SIO_BOARD_ID2
1
2
02/27/2008
-12V
GD75232 TSSOP_R
1 10
U1C1
+12V
20 11
+5V
BOARD SETTING
I259
SERIAL PORT & BOARD SETTING
Wed Mar 19 11:32:06 2008
602-7R177-0000-F00
6.0 40
Page 41
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
AN
CAT
IN
OUT
OUT
OUT
OUTININININ
OUT
IN
2
12
16
26
1
11
15
25
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
REMOVE FOR PRODUCTION
39A2<>
39A2>
39A2>
39A6<
41A5>
39A2<>
39A2>
41A7> 39B6<
39B6<
41A7>
39B6<
41A7>
39A6<
41A7>
SIO_LPT_PD<7..0>
SIO_LPT_STROBE* SIO_LPT_ALF* SIO_LPT_ERR* SIO_LPT_INIT* SIO_LPT_SLCTIN*
SIO_LPT_ACK* SIO_LPT_BUSY SIO_LPT_PE SIO_LPT_SLCT
RP1J3
1
33
RP1J3
3
33
0 1 2 3
4 5 6 7
8
RP1J3
2
33
6
RP1J3
4
33
RP1J2
4
33
RP1H1
4
33
7
5
RP1J2
3
5
33
RP1H1
3
5
33
2
R1H1 10K
5% 0603_R
1
RP1J2
2
6
33
RP1H1
2
6
33
8
RP1J1
2.2K
1 2
7
7
33
33
7
RP1J1
2.2K
RP1J2
1
RP1H1
1
8
8
6
RP1J1
2.2K
3 4
5
RP1J1
2.2K
+5V_LPT
8
RP1H2 10K
1
7
RP1H2 10K
2
6
RP1H2 10K
3
5
RP1H2 10K
4
SIO_LPT_PD0_R SIO_LPT_PD1_R SIO_LPT_PD2_R SIO_LPT_PD3_R
SIO_LPT_PD4_R SIO_LPT_PD5_R SIO_LPT_PD6_R SIO_LPT_PD7_R
+5V
2
CR1H1 1N4148W
SOD123_R
1
+5V_LPT
SIO_LPT_STROBE_R* SIO_LPT_ALF_R*
SIO_LPT_INIT_R* SIO_LPT_SLCTIN_R*
41C4>
41B4<
41A7>
41A7>
41A7>
41A7>
41A7>
41A7>
41A7>
41A7>
41A7>
41A5>
41A5>
41A5>
J1J1
41C2> 41D2> 41D2> 41D2> 41D2> 41D2> 41C2> 41C2> 41C2> 39B6<
41B7>
39B6<
41B7>
39B6<
41B7>
39A6<
41B7>
SIO_LPT_STROBE_R* SIO_LPT_PD0_R SIO_LPT_PD1_R SIO_LPT_PD2_R SIO_LPT_PD3_R SIO_LPT_PD4_R SIO_LPT_PD5_R SIO_LPT_PD6_R SIO_LPT_PD7_R
SIO_LPT_ACK* SIO_LPT_BUSY SIO_LPT_PE SIO_LPT_SLCT
THR_R
1 3 5 7 9
13 15 17 19 21 23 25
I19
HDR2X13
SIO_LPT_ALF_R*
2
SIO_LPT_ERR*
4
SIO_LPT_INIT_R*
6
SIO_LPT_SLCTIN_R*
8 10 1211 14 16 18 20 22 24 26
41C2>
41C7> 39A6< 41C2> 41C2>
Wed Jan 16 11:23:18 2008
PARALLEL PORT
416.0602-7R177-0000-F00
Page 42
CAT
AN
GND
PWR
TACH
OUT
OUT
OUT
OUTININ
OUT
GND
PWR
TACH
S
D
D
S
G
IN
GND
PWR
TACH
S
D
D
S
G
D
S
G
IN
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
MCP7A FAN_1
+12V
CHASSIS SYSTEM FAN_2
+12V
2
R4J2 1K
5%
+3.3V
39C2>
EMPTY
SIO_AUXFAN_CNTL
2
R4J1 1K
5% 0402_R
1
Q4J1
2N7002
S23_R
0402_R
1
2
R4J3 1K
5% 0402_R
1
1AUXFANCNTL*
2
3
C4J3
1
22UF
RDL_R ALUM 25V 20%
2
Q4J2 SI2305DS S23_R
AUXFANCNTL_D
3
1
2
CHASIS SYSTEM FAN_1
2
1
R4J4 0
5% 1206_R
1
2
1
2
+12V
EMPTY
AUXFAN_TACH_RR
R4J6
22K
5%
0402_R
R4J5
10K
5%
0402_R
3 2 1
J4J1 THR_R
I230
1
0402_R
1 C4J2
2
R4J7
4.7K
1UF
0603_R X5R 16V 10%
+12V
2
5%
SIO_AUXFAN_TACH
19D3>
39C6<
CPUFAN_CNTL
2
C10H3
1UF
1
0603_R X5R 16V 10%
3 2 1
1
J10H1 THR_R
I153
R10G1
200
CPU FAN
CPUFAN_TACH_RR
J10G1 4PIN_FAN_R
4+12V
+3.3V
2
1
2
5%0402_R
R10H2 1K
5% 0402_R
3
CR10H1 MMBD4148
S23_R
1
C10G1
2 1
0603_R X5R
1UF
16V 10%
CPUFAN_CNTLR
3 2 1
I86
+12V
2
1EMPTY
1
2
R10G6
4.7K
5% 0402_R
R10G5 22K
5% 0402_R
2
5%
0
R10G2
2
0
1
2
5%
EMPTY
R10G4 10K
5% 0402_R
2
R1H3 1K
5%
1
0402_R
1
SYSFANCNTL*
2
R1H7 1K
5% 0402_R
1
3
2
1
2
3
SYSFANCNTL_D
1 C1H2
22UF
RDL_R ALUM 25V 20%
2
Q1H1 SI2305DS S23_R
+5V
EMPTY
2
R2H13 1K
5% 0402_R
1
Q1H3
2N7002
3
S23_R
1
2
19D3>
SYSFAN_CNTL
DEFAULT MCP7A OUTPUT HIGH
10/8
0402_R
R2H12
21
5%
200
EMPTY
Q1H2
2N7002
S23_R
2
1
EMPTY
R1H2 0
5% 1206_R
SYSFAN_TACH_RR
1
R1H5
2
1
R1H6
2
3 2 1
22K
5%
0402_R
10K
5%
0402_R
J1H2 THR_R
I152
39C2>
SIO_SYSFAN_CNTL
1
0402_R
R2H14
510
2
5%
EMPTY
REMOVE FOR PRODUCTION
REMOVE FOR PRODUCTION
1
0402_R
1
2
R1H4
4.7K
C1H3 1UF
0603_R X5R 16V 10%
5%
2
0402_R
R1H9
1
0402_R
+12V
0
R1H8
5%
21
0
2
5%
EMPTY
39C2>
SYSFAN_TACH
SIO_SYSFAN_TACH
SIO_CPUFAN_CNTL
19C3<
R10H1
2
1
5%
0402_R
200
EMPTY
REMOVE FOR PRODUCTION
19D3<
39B6<
39B6<
CPUFAN_TACH
SIO_CPUFAN_TACH
REMOVE FOR PRODUCTION
FAN CONTROLS/HEADERS
1
0402_R
R10G3
1
0402_R
Wed Jan 16 11:23:19 2008
6.0602-7R177-0000-F00
42
Page 43
OUT
OUT
D
S
IN
IN
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
6
5
7
8
1
2
4
3
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
M4A1
BRD_MOUNT
BRDMNT
1
M2A1
BRD_MOUNT
2 3 4
I166
BRDMNT
1 2 3 4
I255
M10K1
BRD_MOUNT
BRDMNT
1 2 3 4
I169
M10G1
BRD_MOUNT
BRDMNT
1 2 3 4
I174
5 6 7 8
M4G1
BRD_MOUNT
BRDMNT
5 6 7 8
1 2 3 4
I167
5 6 7 8
M10B1
BRD_MOUNT
BRDMNT
5 6 7 8
1 2 3 4
I171
5 6 7 8
5 6 7 8
45A4> 19D3<
PWRGD_SB
EMPTY
3
1
2
M4K1
BRD_MOUNT
BRDMNT
1 2 3 4
I162
BATT_PWR
5 6 7 8
3
R1J2
1
0402_R
1K
21
J1K1 V_3PCOIN_R WHITE I236
2
5%
M1G1
BRD_MOUNT
BRDMNT
1 2 3 4
I256
5 6 7 8
Q1J1 SI2305DS S23_R
+3.3V_DUAL
2
R1J1 0
5% 0402_R
1
BAT54C
CR1J1
2
3
1
I210
BATT_PWR_R
+3.3V
EMPTY
2
R1E1 1K
5% 0402_R
1
+3.3V_VBAT
C1J2
C1J11
0.1UF
0603_R X7R 16V
10%2
1
0.1UF
0603_R X7R 16V
10%2
39D2< 39C7<
BOOT MODE SELECT DEFAULT: USER MODE
02/04/2008
+5V
19B8< 19B5>
Q1E1
S23_R
3
1
2
SPEAKER_EMITTER
J1E1
THR_R
I253
HDR1X4
1 2 3 4
37D8< 19E5>
SPEAKER
1
0402_R
R1E2
4.7K
2
5%
MMBT3904
SPEAKER_BASE
C1E11 1000PF
0402_R X7R 16V
10%2
MTG/BAT/SPK
Mon Feb 04 10:48:33 2008
436.0602-7R177-0000-F00
Page 44
AN
CAT
OUT
AN
CAT
IN
D
S
G
D
S
G
IN
OUTININ
OUT
21
9
OUT
OUT
IN
3.3V
3.3V
GND
5V
GND
GND
PWR_OK
5V
5VSB
12V
12V
3.3V
-12V
3.3V
GND
GND
PS_ON*
GND
GND
RES
5V
5V
GND
5V
D
S
G
INININ
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
J5K1
+5V_STBY
2
R5J2 22K
5% 0402_R
2
5%
0
2N7002
Q5J1
S23_R
1
1
PS_ON*
3
2
C5J31 470PF
0603_R C0G 50V 5%
2
39A6<
PS_ON_R*
EMPTY
19C2> 19D3> 39A6< 45B2<
R5J1
1
0402_R
SLP_S3*
ATX_1MTG_R
16
I192 ATX_PWR_24PIN
+5V_STBY+12V+5V-12V
+5V_STBY
1
0.1UF
0603_R X7R 16V 10%
2
1
13
2
14
3
15
4
5
17
6
18
7
19
8
20
9 21 10 22 11 23 12 24
+3.3V
TP_PWR_N5V
+3.3V
2
R6J5 22K
5% 0603_R
1
C6J5
1C6J7
470PF
0603_R C0G 50V
5%2
EMPTY
PWRGD_PS
45B4>
5VDUAL_FET_GATE
45B7<
CHIPSET POWERGOOD
0603_R
+1.1V_CORE
1
0603_R
R6J2
10K
1
5%
R5J3
10K
2
R6J4 10K
5% 0603_R
1
PWRGD_PS_BASE
2
EMPTY
+1.1V_CORE_PG_B
2
5%
2
C5J101 .22UF
0603_R X7R 16V 10%
2
1
R6J3
4.99K
1% 0402_R
MMBT3904
2N7002
Q6J1
S23_R
Q5J2
S23_R
+5V_STBY
2
1
3
1
2
3
1
2
R6J1 10K
5% 0603_R
PS_PWRGD_STG2
PS_PG_SC1
+3.3V_DUAL
2N7002
Q5J3
1
S23_R
2
R5J4 10K
5% 0603_R
1
3
2
PS_PWRGD
STANDBY_LED
+5V_DUAL
2
R10H3 330
5% 0603_R
1
YEL_SUSLED_AN
1
2
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2
POWER CONNECTOR FILTERING
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0.1UF
0603_R X7R 16V
10%2
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1
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2
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C9K11 100UF
ALUM 25V 20%
1C5J6
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1
2
C7K1
0.1UF
0603_R X7R 16V
10% 22
EMPTY
C6J14 22UF
RDL_R ALUM 25V 20%
C5J41 22UF
RDL_RRDL_R ALUM 25V
20%2
1
0.1UF
0603_R X7R 16V
10% 2
EMPTY
1C7K2
+3.3V
1
2
C6J17
0.1UF
0603_R X7R 16V 10%
C4K21
0.1UF
0603_R X7R 16V 10%
2
1
2
C4K3
0.1UF
0603_R X7R 16V 10%
1
+5V_DUAL
EMPTY
C1B8
1
C1B7
1
2
+3.3V_DUAL
1
2
4.7UF
1206_R X7R 16V 10%
C3F3 47UF
RDL_R ALUM 25V 20%
2
1
2
4.7UF
1206_R X7R 16V 10%
C3F2
0.1UF
0603_R X7R 16V 10%
EMPTY
C7K3
0.1UF
0603_R X7R 16V
+3.3V
1
-12V
C4J4 100UF
RDL_R ALUM 25V
20%2
1
210%
C4K1
0.1UF
0603_R X7R 16V 10%
1
2
C5J1 22UF
RDL_R ALUM 25V 20%
9B5> 11C6>
18A6>
+5V_STBY
C6J10
1
100UF
RDL_R ALUM 25V
20%2
XDP_FNTPNL_RST*
SATA_HDLED*
+3.3V
2
1
RST_SWR*
EMPTY
+3.3V_DUAL
R1G7
2
1
5%
0402_R
FOR A01 WAR
2
1
R2H26 10K
5% 0402_R
EMPTY
C1G6
1
470PF
0402_R X7R 50V 10%
2
FP_RESET*
C1G3
133
1UF
0603_R X5R 16V 10%
2
R12G1
1
0402_R
1
C1G8 470PF
0402_R X7R 50V
10%2
5%
0
1
2
2
Tue Mar 18 12:14:21 2008
R1G15 330
5% 0402_R
HDLED_PWR
EMPTY
C1G9 470PF
0402_R X7R 50V 10%
+5V
EMPTY
2
R1G14 0
5% 0603_R
1
J1G2 THR_R
1 3 5 7
9
HDR2X5KEY10
I126
FRONT_PANEL
19E3<
46B8<
5%
2
+3.3V_DUAL
2
R1G2 10K
5% 0402_R
1
PWRBTN*
39D6<
EMPTY
C1G1
1
470PF
0603_R C0G 50V 5%
2
EMPTY
19E3<
R1G4 0
5% 0402_R
+5V_DUAL
2
1
1
470PF
0402_R X7R 50V 10%
2
EMPTY
EMPTY
R1G11 330
5% 0402_R
1C1G4
2 10%
1
0402_R
C1G5 470PF
0402_R X7R 50V
0402_R
R1G10
EMPTY
C1G7
2
470PF
5%
0
1
2
5%
0
EMPTY
EMPTY
39D2>
R1G6
1
0402_R X7R 50V 10%
EMPTY
GRN_PWRLED
2
YLW_STBYLED PWRBTN_R*
0402_R
SIO_PSOUT*
+3.3V_DUAL
2
1
R1G9
2
1
5%
0
EMPTY
0402_R
39A6> 39A6>
R1G3 22K
5% 0402_R
SIO_PSIN*
R1G1
2
1
5%
33
EMPTY
R1G8
1
0402_R
33
+5V
2
R1G5 330
5% 0402_R
1
2 4 6 8
2
1
PWR CONN & FRONT PANEL
44602-7R177-0000-F00 6.0
Page 45
D D D D
S S S G
D
S
G
D D D D
S S S G
D
D
D
D
S
G
IN
D
S
G
D
S
G
OUT
OUT
OUT
-
+
OUT
CAT
ADJ
AN
D
S
G
D
S
G
D
S
G
D
S
G
IN
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
+5V_STBY
+5V_STBY
5
3
1
2
CR7J1
SC431L
SOT-23_R
1.240V
2
R7J3 200
5% 0402_R
1
2
C7J31 .01UF
0402_R X7R 16V 10%
2
1
3
5V_STBY_REF
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1
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3VDUAL_BASE_R
4
I457
Q7K1
2N7002
S23_R
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+5V_STBY
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1
3
1
2
+3.3V_DUAL
R7K2 22K
5% 0402_R
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+3.3V_DUAL
R7J4
1
0402_R
2
R7K6
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1
2
R7K4
2.67K
1% 0402_R
1
Q7K3
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20
1
3VDUAL_BASE
2
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1
3VDUAL_CTRL_DRAIN
Q7K4
3
2N7002
1
S23_R
2
R7K3
2
1
1%
0603_R
200
2
3
C7K4
1
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0603_R X7R 25V
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2
1
R7K5
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PLACE NEAR FETS
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2
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1 C7K51 C7K6
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RDL_R ALUM
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1
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1
3
2
1 2 3 4
1 2 3 4
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1
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RDL_R ALUM 25V 20%
2
Q1B1 FDS8896 SO8_R
I489 Q8K2
FDS8896 SO8_R
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C5J8
1
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2
8 7 6 5
PLACE NEAR REAR PANEL USB
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8
1
7 6 5
1 2 5 6
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RDL_R ALUM 10V
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C8J5
1
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2
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RDL_R ALUM 10V
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PLACE AT SI3447
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44D8< 39A6< 19D3>
2
1
Q2J1
3
1
2
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1
0402_R
R2J10
0
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R2J7 10K
5% 0402_R
PWRGD_SB
2
R2J6 0
5% 0402_R
1
1
2
C2J1 .1UF
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5%
2
1
Tue Feb 05 10:23:43 2008
43D5<
19D3<
2
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5% 0402_R
1
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1
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0402_R X7R 16V 10%
2
DUAL RAIL VREGS / STANDBY PWRGD
456.0602-7R177-0000-F00
MMBT3904
S23_R
C3J1
4.7UF
0603_R X5R
6.3V
Q3J1
+5V_STBY
2
1
3
1
2
R2J12
8.2K
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PWRGD_SB_N
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EMPTY
2N7002
S23_R
39A6>
+5V_DUAL
C8J4
1
330UF
RDL_R ALUM 10V 20%
2
PLACE AT BACK PANEL
+1.1V_DUAL
1
EMPTY
EMPTY
R3J1
20K
2
5%0603_R
EMPTY
+1.4V_DUAL_PWRGD_DLY
1
2 10%
CHECK IF IT IS OK FOR BJT??
Page 46
<XR_PAGE_TITLE>
OUT
IN
D
S
G
D
S
G
IN
D
S
G
IN
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
IN
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
UGATE
PHASE
LGATE
BOOT PVCC VCC PWM GND
+12V +12V
GND
GND
THERM
IN
OUTININ
IN
VCC
PVCC1_2
ISEN1+
UGATE1
BOOT1
PVCC3
PHASE1 LGATE1
BOOT2
ISEN1-
UGATE2
ISEN2-
ISEN2+
PHASE2 LGATE2
LGATE3
BOOT3
UGATE3 PHASE3
ISEN3+
ISEN4+
ISEN3-
EN_PH4
ISEN4-
PWM4
SS/RST/A0
VID7 VID6
VID2 VID1 VID0
VID5
PGOOD
VID4 VID3
EN
COMP
VRSEL
FB IDROOP
VDIFF
VSEN
OFS
RGND
SDA
SCL
REF
GND
FS
OUT
OUT
IN
D
S
G
D
S
G
-
+
-
+
INININ
IN
THERM
A
B
C
D
E
F
3 2 1
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DATE
TITLE
DOC NUMBER
CONFIDENTIAL
NVIDIA
6 4578
E
D
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C
B
A
456 3 2 18 7
31A7< 30D7< 29D7<
30D7<> 29D7<>
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19C8> 15A4<>
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1
5%
0402_R
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1
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R10F4 1K
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0402_R X7R 16V 10%
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R10F3 1K
5% 0402_R
1
2
R10F2 549
1% 0603_R
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2
3
0402_R
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1
R9G11
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R9G13 100
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1
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37 36 46 47 48 1 2 3 4 5
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0
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1
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0603_R X7R 16V 10%
2
EMPTY
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R9G15 120K
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S23_R
2
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3
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R9G8
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2
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1C9G9
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2
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SS
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R9G6 243K
1% 0603_R
1
BOTTOM PAD CONNECT TO GROUND THROUGH 8 VIAS
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13
14 15
16
18
17
12 7 8 11 45
9 49
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15K
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680PF
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EMPTY
C9G4
1
2
0603_R C0G
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50V 5%
2
R9G9 0
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1
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2
R10F8 2K
5% 0603_R
1
1
1
R10F6
130
R10F5
130
C9G3
1
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0603_R X7R 16V 10%
2
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5
MMBT3904
2
5%0603_R
MMBT3904
2
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1
C9G5
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0603_R X5R 16V
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10 29
42
R9G30
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1
31 32
33 30
35 34
26 25 28
19 20
40 39
38 41
44 43
21 22
24
PHASE1
0603_R
PHASE2
PHASE3
PHASE4
0603_R
R9G29
0603_R
5%
2.2
1
0603_R
1
0603_R
21 127
5%
2.2
1
0603_R
1
0603_R
R9G23
2
1
5%
2.2
1
0603_R
1
0603_R
1
0603_R
1
0603_R
23
+12V
2
R6B16
2.2
5% 0805_R
1
C6B13
1
1UF
0603_R X5R 16V 10%
2
R9G32
2.2
5% 0805_R
C9G24
1
1UF
0603_R X5R 16V 10%
2
C9G22
1
0603_R
X7R
0.1UF
16V 10%
R9G28
2
1%
174
R9G31
2
5%
4.7K
C9G23
0603_R
X7R
0.1UF
16V 10%
R9G19
2
1%
174
R9G21
2 1 2
5%
4.7K
C9G16
1
0603_R
X7R
0.1UF
16V 10%
R9G17
2
1%
174
R9G18
2
5%
4.7K
R9G22
2
1%
174
R9G24
2
5%
4.7K
2
C9G18
1
0.1UF
0603_R X7R 16V
1
10%
2
2 7 6 3 4
1
2
2
2
R9G27
2.2K
5% 0603_R
R9G20
2.2
5% 0805_R
0603_R
1 C9G13
1UF
0603_R X5R 16V
2 10%
C9G21
1
0603_R
X7R
0.1UF
16V 10%
C9G14
0603_R
X7R 16V 10%
C9G11
1
0603_R
X7R 16V 10%
C9G17
1
0603_R
X7R 16V 10%
1
0603_R
R6B12
1
2.2
U6B3 SM_IC_SO8
ISL6612CB
I877
ISENSE1
2
ISENSE2
0.1UF
ISENSE3
2
0.1UF
2
0.1UF
R9G25
2
5%
15K
2
5%
C9G25
1
0.1UF
0603_R X7R 16V 10%
2
C9G12
1
0.1UF
0603_R X7R 16V 10%
2
C9G81
0.1UF
0603_R X7R 16V 10%
2
ISENSE4
+12V
C6B10
1
0603_R
X7R
0.1UF
16V 10%
R9B3
1
0805_R
0
ISO8B1 25MIL
1
R9D1
1
0805_R
0
21
25MIL
ISO9F1
R8B1
1
0805_R
0
C9G15
1
0.1UF
0603_R X7R 16V
10%2
0805_R
1
1
ISO7B1 25MIL
R7B8
2
1
8
25MIL
ISO6B1
2
1
5
2
2
5% 0603_R
1
2
5%
Q9B2
DPAK_R
Q9C1
2
R9D2
2
10K
5% 0603_R
1
Q10D1
2
5%
DPAK_R
Q9E1
2
R8B2 10K
2
5%
5%
0603_R
1
Q8B2
DPAK_R
Q8C1
2
2
R7B9 10K
5% 0603_R
1
Q7B2
2
5%
DPAK_R
0
Q7B1
1
AOD472
1
DPAK_R
1
AOD472
1
DPAK_R
1
AOD472
1
DPAK_R
1
AOD472
1
DPAK_R
Q9C2
1
DPAK_R
2
AOD452
3
AOD472
Q9B1
2
2
1
3
3
DPAK_R
Q10D2
1
2
DPAK_R
AOD452
3
AOD472
Q10E1
2
2
1
3
3
DPAK_R
Q8C2
1
2
DPAK_R
AOD452
3
AOD472
Q8B1
2
2
1
3
3
DPAK_R
Q7C2
1
2
DPAK_R AOD452
3
AOD472
Q7C1
2
2
1
3
3
DPAK_R
12V_FILT
2
AOD452
3
C8B4
1
C9B4
1
10UF
1UF
1206_R
0805_R
X5R
X7R
16V
16V
10%2
10%
2
46F2>
46D2< 46C2<
+V_CPU
L9C1
.3UH
2
1
WW
TH_R
25MIL
ISO9C1
38A
C9C1
1
C9C2
1
C8C2
1
C9E31
820UF
2
ISO9C2 25MIL
1
2
1
820UF
RDL_R
RDL_R OSCON
2.5V
2.5V
2
2 20%
820UF
RDL_R OSCONOSCON OSCON
2.5V
2
20%220%
820UF
RDL_R
2.5V 20%
2
1 1
2
EMPTY
R8C2
2.2
5% 0805_R
C8C4 1000PF
0603_R X7R 16V 10%
EMPTY
ISENSE1 PHASE1
12V_FILT
2
AOD452
3
EMPTY
2
R9E1
2.2
5% 0805_R
1
C9E1
1
1000PF
0603_R X7R 16V 10%
2
EMPTY
1
2
C7B2 1UF
0805_R X7R 16V 10%
25MIL
ISO10E2
2
1
C10C1
1
10UF
1206_R X5R 16V
2 10%
.3UH
1
38A
ISENSE2
L10E1
1
2
WWTH_R
ISO10E1 25MIL
46C2< 46F2<
2
46D2< 46F2>
C8C11
820UF
820UF
RDL_R
RDL_R
OSCON
OSCON
2.5V
2.5V 20%
2
20%2
C13E41
C13E6
1
470UF
470UF
7343_R
7343_R
X7R
X7R
2.5V
2.5V
20%
2
20%
2
1
C8E31
22UF
22UF
1206_R
1206_R
X5R
X5R
6.3V
6.3V 20%
2
2
20%
820UF
820UF
RDL_R
RDL_R
OSCON
OSCON
2.5V
2.5V 20%
2
20%
2
C8E91C8E10
1C8E2
22UF
22UF
1206_R
1206_R
X5R
X5R
6.3V
6.3V
20%2
20%2
C7C2
1
C9E2
1
C8C3
1
PHASE2
AOD4523
2
1 1
2
R8C1
2.2
5% 0805_R
C7C3 1000PF
0603_R X7R 16V
12V_FILT
C9D2
1
1UF
0805_R X7R 16V 10%
2
EMPTY
EMPTY10%
25MIL2ISO8C1
1
C9D1
1
10UF
1206_R X5R 16V
10%2
.3UH
ISENSE3
1
2
PHASE3
AOD452
2
R7B5
2.2
5% 0805_R
1
C7B1
1
1000PF
0603_R X7R 16V
10%2
12V_FILT
C8B3
1
1UF
0805_R X7R 16V 10%
2
EMPTY
EMPTY
ISO7C1
25MIL
C7B3
1
10UF
1206_R X5R 16V
2 10%
2
1
2
3
ISENSE4
ISO8C2 25MIL
ISO7C2 25MIL
1
46D2<
46C2<
46F2>
L8C1
46F2<
WW2TH_R138A
2
1 C8E4
1206_R X5R
6.3V
20%2
1 C8E16
22UF
1206_R X5R
6.3V
2 20%
1
1206_R X5R
6.3V 20%
2
1
1206_R X5R
6.3V 20%
2
C8E12
1C8E1
22UF22UF22UF 22UF
1206_R X5R
6.3V
20%
2
1C8E15
22UF22UF
1206_R X5R
6.3V
20%
2
C8E11
1
1206_R X5R
6.3V
20%2
C8E13
1C8E14
22UF
1206_R X5R
6.3V
20%2
C8E8
22UF
22UF
1206_R
46F2<
46D2< 46F2>
L7C1.3UH
21
WW
TH_R38A
1206_R
X5R
X5R
6.3V
6.3V 20%
2
2 20%
C8E6
1
C8E51
22UF
22UF
1206_R
1206_R
X5R
X5R
6.3V
6.3V 20%
2
2
20%
22UF
22UF
1206_R
1206_R
X5R
X5R
6.3V
6.3V
20%2
20%
2
C8E17
1
C8E18
1C8E7
1
1
2
PHASE4
4 PHASE CPU VREG
Tue Mar 18 16:34:05 2008
602-7R177-0000-F00
6.0 46
+12V
+12V
+5V
Page 47
+5V_DUAL
VOUT
GND
RT9173
VCNTL_TAB
VCNTLVIN
REFEN
IN
AN
CAT
D
S
G
D
S
G
D
S
G
D
S
G
VCC UGATE PHASE LGATE
COMP/SD BOOT
GND
FB
INININ
IN
C
B
A
D
2 14 3
PAGEREVDOC NUMBER
TITLE
CONFIDENTIAL
NVIDIA
6 5
D
78
A
C
B
24 3 18 7 6 5
2
R9J9
10K
5%
0402_R
Q9J2
3
2N7002
19D3> 19D2>
SLP_S5*
R9J10
22K
5%
0603_R
EMPTY
R9J7
1
5.76K
2
S23_R
1
2
1%0402_R
C2
MEM_FB_FILT2
1
2
50V
180PF
2
C9J7
1
2
.01UF
MMBT3904
C1R2
C9J5
1
0402_R
C0G
5%
Q9J1
S23_R
1
0603_R X7R 16V 10%
3
1
2
MEM_REG_COMP
7 6 1 3
U9J1 SOIC8_R
+5V_DUAL
C9J10
1
1UF
0603_R X5R 16V 10%
2
ISL6545
1
C
C9J9 .1UF
0402_R X7R 16V
10%2
I643
MEM_BST
MEM_FB
CURRENT TRIP > 30A
C9J6
1
2
0402_R X7R
.1UF
16V 10%
2
R9J5 576
1% 0402_R
1
MEMORY VDDQ (NFORCE AND DIMMS) 20 AMPS @1.8V
PLACE ACROSS FETS
C9J11
1500UF
1500UF
RDL_R
RDL_R
ALUM
ALUM
6.3V
6.3V
20%2
20%2
RO
C3
5 2 8 4
2
R9J8
3.92K
1% 0402_R
1
C9J4
2
.047UF
MEM_FB_FILT
1
0603_R X7R 25V 10%
MEM_DH
MEM_LX
MEM_DL
11/29
1
0402_R
1
0402_R
R9J6
357
R9J4
1.24K
RS
MEM_HIGH_DRAIN
C9K2
11 C9J2
1UF
0603_R X5R 16V 10%
2
R3
2
1%
R1
2
1%
C9J8
1
4.7UF
0805_R X5R 10V 10%
2
AOD452
DPAK_R
AOD472
DPAK_R
10/15
Q9K1
Q9K2
+5V_DUAL
13A
TH_R
WW
2
1
3
2
1
3
1
L8J1 .31UH
2
1
2
C8K6 .1UF
0402_R X7R 16V 10%
NEED >1 CU PER FET
L10J1
.8UH
2
1
WWTH_R
R10K1
2.2
5% 0805_R
MEM_1P8V_R
C9K3 .01UF
0603_R X7R 16V 10%
30A
2
1
1
2
C10J11 1000UF
RDL_R ALUM
6.3V 20%
2
26C2< 25C1>
C10H21 1000UF
RDL_R ALUM
6.3V 20%
2
C9J121 1000UF
RDL_R ALUM
6.3V 20%
2
+1.8V_SUS
C10J2
1
22UF
1206_R X5R
6.3V 20%
2
C9H31 1UF
0603_R X5R 16V
+1.8V_SUS
EMPTY
C9H11 1UF
0603_R X5R 16V
10%2
2
C9H21
4.7UF
1206_R X7R 16V 10%
DIMM_VREF_CH0
C9H4
1
0.1UF
0603_R X7R 16V
10%210%2
MEMORY MEM_VTT
1A @ 0.9V
U9H1
1
4
TO-263_R I672
+3.3V_DUAL
C9H9
C9H10
C9H81
0.1UF
0603_R X7R 16V 10%
3 6
2
1
4.7UF
1206_R X7R 16V 10%
2
1
47UF
RDL_R ALUM 25V
20%2
5
2
R9H2
2
1K
5% 0402_R
1
C9H61 220UF
RDL_R ALUM
6.3V 20%
2
C9H7
1
220UF
RDL_R ALUM
6.3V 20%
2
2
C8H11 22UF
1206_R X5R
6.3V 20%
WILL BE POWERED IN S3
1
C9J3 22UF
1206_R X5R
6.3V
20%2
+MEM_VTTV
C9H51 1UF
0603_R X5R 16V
10%2
+1.8_RFB BITS
Q10H1
A03414
S23_R
+5V_DUAL
2
1
BLU_MEMLED_AN
1
2
3
1
2
R10H4 330
5% 0603_R
CR10H3 BLU
0603_R
2.8V 20MA
10/26
MEM_LED
VOLTAGE
OV2
OV1OV0
R9J3
6.81K
0402_R
2
1%
1
1 1 1 1
0 0 1 0 0
1 0 01 1
0 0
1 0 1 0 1 0 1 0
1.89V*
2.00V
2.10V
2.21V
2.30V
2.41V
2.51V
2.62V *DEFAULT
+1.8V_SUS
39B2>
39A6>
39A6>
MEM_OV0
MEM_OV1
MEM_OV2
R9J1
1.82K
0402_R
2
1%
1
R9J2
3.57K
0402_R
2
1%
1
NOTE: VOUT=0.6V*[(RS+RO)/RO] RO=(RS*0.6V)/(VOUT-0.6V)
Wed Jan 16 11:23:30 2008
MEM VDDQ AND VTT VREGS
47602-7R177-0000-F00 6.0
Page 48
INININ
ADJ
VOUTVIN EN GND GND GND GND
D
S
G
D
S
G
VCC UGATE PHASE LGATE
COMP/SD BOOT
GND
FB
INININ
C
B
A
D
1234
NVIDIA CONFIDENTIAL
TITLE
PAGEREVDOC NUMBER
6 5
D
8 7
A
C
B
24 3 158 7 6
+12V
1
2
C3H2 .1UF
0402_R X7R 16V 10%
+3.3V
13A
TH_R
2/14
1
L3H1 .31UH
WW
2
PLACE ACROSS FETS
MCP7A CORE VREG
1.1V @ 20A
2
C
C2F31 .1UF
0402_R X7R 16V 10%
5
MCP7A_CORE_DH
2 8
MCP7A_CORE_DL
4
2
R3F1
4.99K
1% 0402_R
1
2
1
C3G1
1
1500UF
RDL_R ALUM
6.3V
2
MCP7A_CORE_LX
11/29CURRENT LIMIT > 40A
C3
R2G6
2.21K
1% 0402_R
RO
C2G1
1
1500UF
RDL_R ALUM
6.3V
20%220%
C2G2
2
.022UF
1
1UF
0603_R 0805_R X5R 16V
10%2
7A_CORE_FB_FILT
1
0603_R X7R 25V 10%
1
0402_R
1
2 10%
R2G2
309
R2G4
1.65K
RS
C2G51C2H6 10UF
X5R 10V
1%
1%0402_R
Q2G1
AOD452
DPAK_R
Q2G2
AOD472
DPAK_R
R3
2
2
1
R1
2
1
3
2
3
2
R3G1
2.2
5% 0805_R
1
7A_CORE_SNUB
C3G5
1
.022UF
0603_R X7R 25V 10%
2
NEED >1 CU PER FET
11/12
L3G1
1.2UH 1
WW2TH_R
30A
C3F61 1000UF
RDL_R ALUM
6.3V 20%
2
C4E11 1000UF
RDL_R ALUM
6.3V 20%
C3F7
1
1000UF
RDL_R ALUM
6.3V 20%
22
1
2
EMPTY
C3F5 22UF
1206_R X5R
6.3V
EMPTY
220%
C3G31 22UF
1206_R X5R
6.3V
EMPTY
1
220%
C3G4 47UF
1206_R X5R
6.3V 20%
+1.1V_CORE
MCP7A_CORE_AUX_OV BITS
1 0 1 0 1 0 1 0
VOLTAGE
1.200V*
1.225V
1.251V
1.276V
1.302V
1.327V
1.352V
1.378V
OV0
1 1 1 1 0 0 0
OV1
1 1 0 0 1 1 0 00
OV2
*DEFAULT
+1.1V_DUAL
MCP7A CORE AUX
C2F1
2
50V
150PF
C2G3
2
2
.01UF
C3G21 .1UF
0402_R X7R 16V 10%
C2G4
1
0402_R 5%
C1
C0G
1
0402_R X7R 16V 10%
7A_CORE_REG_COMP
7 6 1 3
U2G1 SOIC8_R
I267
R2
1
0402_R
R2G7
6.49K
1%
C2
7A_CORE_FB_FILT2
2
+12V
1
1UF
0603_R X5R 16V 10%
2
ISL6545
MCP7A_CORE_FB
1.1V @ 850MA MAX
C2F2
39A6>
39A6>
39A6>
MCP7A_CORE_OV0
MCP7A_CORE_OV1
MCP7A_CORE_OV2
1
0402_R
1
0402_R
1
0402_R
R2G1
6.04K R2G3
12.1K R2G5
23.7K
2
1%
2
1%
2
1%
+3.3V_DUAL
C3F1
1
4.7UF
0603_R X5R
6.3V 10%
2
03/10/2008
MCP7A_CORE_OV BITS
1 0 1 0 1 0 1 0
VOLTAGE
1.047V*
1.090V
1.130V
1.172V
1.212V
1.253V
1.294V
1.336V *DEFAULT
NOTE: VOUT=0.8V*(1+R1/R2)
NOTE: VOUT=0.6V*[(RS+RO)/RO] RO=(RS*0.6V)/(VOUT-0.6V)
OV2
OV1
OV0
1
1
1
1
0
1 1 0 0 0 0
0 1 1
00
U2F1 SOIC-8_R
RT9183
ADJ
2 1 5 6 7 8
I292
2
3
R2F5 1K
1% 0402_R
1
R1
4
2
R2F4 2K
1% 0402_R
1
R2
1
2 20%
2
1
22UF
0805_R X5R
6.3V
R2F3
31.6K
1% 0402_R
NOTE: EST CURRENT 210MA
COREVIDAUX1
2
R2F1
15.8K
1% 0402_R
1
2
R2F2
7.87K
1% 0402_R
1
MCP7A_CORE_AUX_OV0
MCP7A_CORE_AUX_OV1
MCP7A_CORE_AUX_OV2
11/21
39B6>
39B6>
39B6>
MCP7A CORE VREG
48602-7R177-0000-F00 6.0
Page 49
OUT
D
S
G
AN
CAT
-
+
IN
IN
D D D D
S S S G
OUT
D D D D
S S S G
VCC UGATE PHASE LGATE
COMP/SD BOOT
GND
FB
INININ
LDO VREG
VOUT
ADJ
GND
VIN
EN
D
S
G
D
S
G
IN
IN
C
B
A
D
1234
NVIDIA CONFIDENTIAL
TITLE
PAGEREVDOC NUMBER
6 5
D
8 7
A
C
B
24 3 158 7 6
+5V
1
C6D6
1UF
0402_R
X5R
6.3V
2
19D3> 49D4<
CPUVDD_EN
10%
+5V
2
1
R6C1 10K
5% 0402_R
CPUVDD_EN_GATE
Q6C2
2N7002
S23_R
1
U6D1 SOT-25_R
1
3
300MA 2
2N7002
S23_R
3
2
R2
R6C10
1
0402_R
22.1K
RT9179
Q6C3
1
2
1%
C2
+12V
3
2
CPUVTT_FB_FILT2
2
1
50V
C6C5 .1UF
0402_R X7R 16V
10%2
C6C7
47PF
I47ADJ
C6C8
2
2200PF
0402_R
1
5
4
C1
R2CPU VCC FOR PLL
1
0402_R X7R 25V 10%
5%C0G
2
R6D6
280
1%
0402_R
1
R1
2
R6D7
1K
1%
0402_R
1
CPUVTT_REG_COMP
7 6 1
CPUVTT_FB
6.34K FOR NO VTTSEL
2
1
R6C9
7.68K
1% 0402_R
2
1
R6C7
36.5K
1% 0402_R
RO
Q6C4
10C4>
CPU_VTT_SEL
1
0402_R
R6C11
200
MMBT3904
2
5%
1
S23_R
39B6>
3
39B6>
2
39B2>
CPU_VCC_PLL
1
C6D7
1UF
0402_R
X5R
6.3V
210%
NOTE: VOUT=1.175*(1+R1/R2)
+12V
C7C11
C6C9
U6C1 SOIC8_R
1
2
1UF
0603_R X5R 16V 10%
2
.1UF
0402_R X7R 16V 10%
CISL6545
I258
CURRENT LIMIT > 15A
C3
2
R6C5
19.1K
1% 0402_R
1
CPU_VTT_OV0
CPU_VTT_OV1
CPU_VTT_OV2
5
CPUVTT_DH
2 8
CPUVTT_DL
43
2
R6C6
38.3K
1% 0402_R
1
2
1
2
6800PF
10A4<
FSB VTT 10 AMPS @ 1.2V
+3.3V
1
1
2 10%
C5C3 .1UF
0402_R X7R 16V
TH_R
13A
WW
1
L6C1 .31UH
2
C6C1 1500UF
RDL_R ALUM
6.3V
20%2
1
2
C6C2 .1UF
0402_R X7R 16V 10%
PLACE ACROSS FETS
C6C4
1
4.7UF
0603_R X5R
6.3V 10%
2
1 2 3 4
CPUVTT_PHASE
Q6C5
1 2 3 4
FDS8896 SO8_R
R7C1
2.55K
1% 0402_R
I238
R3
C6C6
2
1
CPUVTT_FB_FILT
1
0402_R X7R 50V 10%
R6C2
76.8K
1% 0402_R
1
0402_R
R6C3
1
0402_R
681
R6C4
6.34K
2
1%
R1
2
1%
RS
Q6C1 FDS8896 SO8_R
I237
8 7 6 5
19D3> 49C8<
CPUVDD_EN
10/5
45D7>
5V_STBY_REF
EMPTY
8 7 6 5
L6C2
1.8UH 1
WW2TH_R
1500UF
RDL_R ALUM
6.3V 20%
2
2
1
C6D4
1
.022UF
0603_R X7R 25V 10%
2
R6C12
2.2
5% 0805_R
14.3A
NOTE: VOUT=0.6V*[(RS+RO)/RO] RO=(RS*0.6V)/(VOUT-0.6V)
1 C6B9
1UF
0402_R X5R
6.3V 10%
2
2
R6B8
5.11K
1% 0402_R
1
VTT_PG_COMP_P
C6B6
1
1000PF
0402_R
X5R 10V
10%2
+1.2V_VTT
C6D111 C6D3 1500UF
RDL_R ALUM
6.3V 20%
2
3
CR6B1 BAR43
S23_R
1
VTT_PG_COMP_N
2
1
10/5
R6B14 10K
1% 0402_R
+1.2V_VTT
2
R6C8 10K
5% 0402_R
1
10/24
OV0
1 1 1 1 0 0 0 0
+5V_DUAL
5
3
1
2
1
0402_R
CPU_VTT
OV1 OV2
EMPTY
R6B15
2
1
5%
0402_R
0
C6B81 .1UF
0402_R X7R 16V 10%
2
U6B2 LMV321 SOT23-5_R
I263
R6B13
5%
62K
+5V_DUAL
EMPTY
2
R6B11
4.7K
5% 0402_R
1
2N7002
4
2
TRIP POINTS SET @ 1.04V, 0.79V WITH 250MV HYSTERESIS
VTT_PG_OUT
Q6B1
S23_R
CPU_VTT_PWRGD
3
1
2
VOLTAGE
1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0
1.20V
1.25V
1.30V
1.35V
1.40V
1.45V
1.50V
1.55V
*
*DEFAULT
46E7< 9C7<
IF CPU_VTT_SEL USED,
VTT_SEL= 1, VTT= 1.2V VTT_SEL= 0, VTT= 1.1V
USE RTOP = 6.34K, RBOT = 7.68K, RFET = 36.5K
CPUVTT LINEAR VREG
49602-7R177-0000-F00 6.0
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+1.8V_SUS
EMPTY
1
C4J1 .1UF .1UF
0402_R X7R 16V
2
10%
EMPTY
1 C5B12 1
0402_R X7R 16V
2 10%
EMPTY
EMPTY
1
C5D3 .1UF
0402_R X7R 16V
2
10%
EMPTY
1
C2J7 1 .1UF
0402_R X7R 16V
2
10%
EMPTY
1
C2E3 .1UF
0402_R X7R 16V
2 10%
EMPTY
C3H3 .1UF
0402_R X7R 16V
2
10%
EMPTY
EMPTY
EMPTY
C9A5 .1UF .1UF
0402_R X7R 16V
2
10%
EMPTY
1
C2F7 .1UF
0402_R X7R 16V
2
10%
EMPTY
1
C3J3 1 .1UF
0402_R X7R 16V
2
10%
1 C8A4 1
0402_R X7R 16V
2 10%
EMPTY
1
C3E1 .1UF
0402_R X7R 16V
2 10% 2
EMPTY
C5J2 1 .1UF
0402_R X7R 16V
2
10%
2
1
+3.3V
2
+3.3V
EMPTY
C5B3 1 .1UF .1UF
0402_R X7R 16V
10% 2
+3.3V
C4C8
0402_R X7R 16V 10%
EMPTY
C3F4 1 .1UF
0402_R X7R 16V
10% 2
C8K2 .1UF
0402_R X7R 16V 10%
EMPTY
C3H1 .1UF
0402_R X7R 16V 10%
[2463,-2141] [4003,4987] [8014,5701] [6685,5745] [3689,5421] [3219,4088] [3550,3489] [547,2396] [654,1291] [2194,1994] [1334,602] [1512,-1434] [958,-2364] [2242,-1145] [2170,-2139] [3735,-2061] [6523,-2837]
+3.3V
+5V
EMPTY
C10H1
2
1
0402_R X5R
0.1UF
16V 10%
[8494,-800]
EMPTY
C8J3
2
1
0402_R X5R
0.1UF
16V 10%
C9B2
2
1
0402_R X5R
0.1UF
16V 10%
EMPTY
[6911,-2412] [8293,5389]
EMPTY
C1J4
2
1
0402_R X5R
0.1UF
16V 10%
+5V_DUAL
+5V_DUAL
+3.3V_DUAL
EMPTY
1
C4C1 1 .1UF
0402_R X7R 16V
2
10%
EMPTY
[1018,6261] [3843,5610]
2
EMPTY
EMPTY
C2A9
2
1
0402_R X5R
0.1UF
16V 10%
C5A1
2
1
0402_R X5R
0.1UF
16V 10%
+3.3V
C3C1 .1UF
0402_R 0402_R X7R 16V 10%
1
2
C2D9 .1UF
X7R 16V 10%
EMPTY
[2472,4195] [1647,4183] [1316,2640]
ALL GND CONNECTION IS IN ANOTHER SIDE GROUND
[464,-2370]
EMPTY
EMPTY
1
C10G2 .1UF
0402_R X7R 16V
2
10% 10%
1
2
C10B1 .1UF
0402_R X7R 16V
1
C1H1 .1UF
0402_R X7R 16V 10% 10%
2
EMPTY
EMPTY
1
C5B4 .1UF
0402_R X7R 16V
2
EMPTY
+5V_DUAL
1
C10F1 1 .1UF
0402_R X7R 16V
2
10% 10%
2
C9H11 .1UF
0402_R X7R 16V
EMPTY
[8925,454] [8555,5299] [-381,-543] [3743,5473]
[8520,1065]* [8370,-595]*
*:GND CONNECTION IS ANOTHER MODE GROUND
EMPTY
+1.8V_SUS
1
C9J11 1 .1UF
0402_R X7R 16V 10% 10%
2
2
C10H4 .1UF
0402_R X7R 16V
EMPTY
[8301,-1917] [8911,-1423]
ADD GND VIA [2752,3322]
[2697,3408] [2806,3314] [7540,1190] [7362,563] [7322,489]
EMPTY
1 C1A2
.1UF
0402_R X7R 16V
2
10%
EMPTY
1
C1D1 1 C1G2 .1UF
0402_R X7R 16V
2 10%
EMPTY
.1UF
0402_R X7R 16V
2
10% 2 10%
+5V
1 C9B5
.1UF
0402_R X7R 16V
EMPTY
[-224,5996] [-253,2981] [-174,139] [8967,4762]
03/18/2008
EMI RESERVED
6.0602-7R177-0000-F00 50
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REV 0.1 07/03/2007
PRELIMINARY SCHEMATIC RELEASE
REV 0.8 09/06/2007
1.CHANGE MCP7A BALLOUT TO DATE 0828
2.CO-LAYOUT MCP7A'S COM PORT, PS2, FAN
REV 0.11 07/09/2007
DELETE BUFFER FOR MEMORY RESET DRIVING
CONTROL AND ACPI WITH SIO
REV 0.9 09/06/2007
CHANGE MCP7A BALLOUT TO DATE 0830
REV 0.12 07/10/2007
1.MODIFY PLL FILTER AND POWER DECOUPLING CAP.
2.ADD HDCP SERIAL EEPROM
3.MODIFY USB UNUSED PORT TERMINATION
REV 0.91 09/26/2007
1.CHANGE CONCEPT LIBRARY FROM MCP79 TO MCP7A
2.CHANGE FP_AUDIO_PRESENCE* SIGNAL FROM GPIO7 TO GPIO19
3.CHANGE SYSTEM FREQ.25MHZ X'TAL CAP. CP TO
REV 0.13 07/19/2007
MODIFY CIRCUIT FOR 7/17 BALLOUT
REV 0.14 07/20/2007
MODIFY CIRCUIT FOR PLL FILTER AND DE-
27PF
4.DELETE HYBRID POWER AND RESET CONTROL CIRCUIT FOR PCIE X8 SLI
5.MODIFY THE OV DIVIDING RESISTERS FOR MCP7A CORE AND AUX CORE POWER
COUPLING CAP.
REV 0.92 10/11/2007
REV 0.15 08/01/2007
1.CHANGE USB FROM 8 PORT TO 10 PORT AND DELETE TERMINATE RESISTER
2.ADD ONE PCI-E SLOT
3.ADD 1394 FUNCTION
4.DELETE LPC HEADER AND ADD LPC ROM SOCKET
5.DELETE TPM FUNCTION
6.DELETE H/W MONITOR & ADD SIO
7.ADD FLOPPY
8.CHANGE AUDIO CODEC FROM ALC888 TO ALC888S AND MODIFY SPDIF OUT CONN
9.ADD CPU GTLREF1 VOLTAGE REG DS4404
10.CHANGE THE MCP7A BALLOUT FROM VERSION
07/17 TO 07/28
REV 0.16 08/01/2007
1.CHANGE USB PORT FORM PORT8 TO PORT10
2.RE-ARRANGE THE DDR TERMINATED RES. SEQUENCE
REV 0.17 08/13/2007
1.REPLACE SPDIF OUT RCA CONN.TO PIN HEADER
2.ADD .1UF CAP TO VBAT POWER
3.ADD 4 HIGH SIDE MOSFET FOR CPU POWER
4.DELETE NEAR MEMORY DIMM CAP.
5.MODIFY RESISTER'S VALUE FOR EVERY OVER VOLTAGE REGULATION
6.ADD LPC HEADER
7.ADD CIRCUIT FOR PCIE HYBRID POWER FUNCTION
8.CHANGE MCP7A BALLOUT TO DATE 0807
REV 0.18 08/23/2007
1.CHANGE PCIE SLOT FROM X1 TO X16 AND MODIFY CIRCUIT TO DUAL X8 SLI.
1.CHANGE IFPAB_VPROBE PULL DOWN CAP. TO .1UF 200 OHM
3.MODIFY THE OV DIVIDING RESISTERS FOR DDR2 MEMORY POWER
4.MODIFY PLL FILTER AND DE-CAP. UNDER THE MCP7A CHIPSET
5.CHANGE USB RBIAS TO GND RESISTER 909 OHM
6.CHANGE SATA RA CONN. FROM DIP TO SMD
7.ADD 0 OHM TO GND FOR NOT USING IP POWER
REV 0.93 10/19/2007
1.MODIFY CPU_VTT_PWRGD COMPARE CIRCUIT
2.IMPELEMENT THE BOARD ID AND BIOS DEBUG FUNCTION
3.MODIFY MCP7A VCORE DE-CAP'S NUMBER
4.CORRECT MEMORY DIMM1 CHANEL 1B SMB ADRESS 010 TO 001
5.ADD GPIO TO CONTROL WP OF HDCP SERIAL ROM
6.CHANGE THE LAN PHY 88E1116 TO 88E1116R
7.DELETE MEMORY RESET CONNECTION TO 4 DIMM
8.CHANGE THE PCIE CONNECTOR TYPE
9.MODIFY THE OV DIVIDING RESISTERS FOR MCP7A DDRII MEMORY RANGE FROM 1.9V TO 2.6V
10.MODIFY DDRII MEMORY SMBUS ADDRESS DEFINATION
11.ADD MCP79 THERMAL SENSE CONNECT TO SIO
12.MODIFY THE TERMINATION RESISTER 49.9 OHM FOR BCLK_VML_COMP_VDD & _GND
13.ADD MORE TWO SATA PORT B0 AND B1
14.DELETE LPC ROM SOCKET
15.MOVE D-SUB RGB DAC TO TVOUT RGB DAC
16.ADD MORE TWO USB PORT
17.DELETE 1394 1 PORT ON THE BACK PANEL
18.MODIFY STRAPING FOR SPI BIOS CS0 DEFAULT SETTING
REV 0.18 08/23/2007
1.ADD SPDIF RCA CONNECTOR
2.ADD GPU HDA 2X8 HEADER
REV 0.94 11/12/2007
1.ADDING LPT PORT PIN HEADER & DELETE BUZZER
2.MODIFY VTT_POWER GOOD OP RESISTER VALUE
3.CHANGE MCP7A CONCEPT LIB FOR ADDING BR1 BALL
4.ADDING PULL HIGH 62OHM TO MCP7A BR1
5.ADDING MEMORY POWER BLUE LED
8.MODIFY JTAG PARTS AND CIRCUIT
9.ADDING EMI COMMON MODE CHOKE FOR HDMI
10.CHANGE THE USB RBIAS 909 TO 845 OHM
11.CHANGE MCP7A VCORE REGULATOR OUTPUT INDUCTOR
REV 1.01 11/16/2007
1.CHANGE SYSTEM 25MHZ LOAD CAP. TO 27PF AND
RTC XTAL LOAD CAP. TO 18PF
REV 1.02 11/27/2007
1.CHANGE MCP7A VCORE AND VCORE AUX VOLTAGE
OV SETTING DEFAULT 1.2V
2.CHANGE MCP7A VCORE AND MEMORY VDDQ OCP
RESISTERS TO 5.23K
3.FOR ALL PLL RAILS,THE CAP 0.1UF IS CHANGED
TO 2.2UF
4.FOR THESE FOUR RAILS,THE FERRITE BEAD IS
CHANGED TO 10NH INDUCTOR V1P1_PLL_PEX V1P1_PLL_SATA V1P1_PLL_SP_SPREF V1P1_PLL_XREF_XS 2.CHANGE MCP7A_CPU_PWGRD PULL UP RESISTER TO
REV 2.0 12/19/2007
PRELIMINARY SCHEMATIC RELEASE
1.SWAP GPIO SIO_HDCP_WP AND MEM_OV0
REV 3.0 12/24/2007
P13 CHANGE R6F5 PULL FROM +1.8_SUS TO GND R6F6 PULL FROM GND TO +1.8_SUS
ADDING THE EXTERNAL PULLS FOR MCP7A SIGNALS LISTED BELOW LLB# LID# PWRBTN# RSTBTN# EXT_SMI# PCI_PME# PEX_RST0# PE_WAKE# SIO_PME# JTAG_TDI JTAG_TMS JTAG_TRST# P16 ADD R3C4 R4C13 P19 ADD R4C14 R16E7 R2J5 R9J11 R6J6 P21 DEL C16E42 P22 ADD R1B11 R1B12 R1B13 P31 ADD R2C5 P44 STUFF R1G2 ADD R2H26 P46 CHANGE R9G7 R9G2 C9G2 C9G6 VALUE STUFF
C9G1 R9G8
REV 3.01 01/03/2008
P40 STUFF R2H18 EMPTY R2H19
REV 3.02 01/16/2008
P40 SETTING BOARD ID = 010 FOR FAB C
REV 4.0 02/05/2008
1.P19 EMPTY R9J11,R6J6 AND ADD BUTTON SWITCH FOR S3/S5 WORKABLE
2.P29,30 FIX PCI-E PRESENT# PIN CONNECTION
3.P40 SETTING BOARD ID = 110 FOR FAB D
4.P43 EMPTY R1E1 FOR STRAPPING USER MODE
5.P48 CHANGE VCORE DEFAULT TO 0.9V AND VCORE RANGE FROM 0.9V TO 1.35V
6.P33 MODIFY USB OC PROTECTION FOR PORT 7654
7.P19 ADD TWO NMMOSFET TO FIX SPI FREQUENCY STRAPPING
8.P35 MODIFY TO USE INTERNAL KBC
6.CHANGE 3 VORE DE-CAP VALUE FORM 0.1UF TO
0.22UF
7.ADDING EMI RESERVED PARTS
REV HISTORY
6.0602-7R177-0000-F00
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REV 5.0 02/27/2008
1.P18 CHANGE USB RBIAS TO 806 OHM
2.P9 REMOVE R13F22 ALLOWED THE CPU TO SEND THE CORRECT BSEL.
3.P40 SETTING BOARD ID = 101 FOR FAB E
REV 6.0 03/18/2008
1.P48 CHANGE VCORE DEFAULT TO 0.9V AND
VCORE RANGE FROM 1.05V TO 1.34V
2.P12 CHANGE CPU_COMP_VCC AND BCLK_VML_
COMP_VDD VOLTAGE FROM +1.2V_VTT TO VTT_ OUT_RIGHT
3.P19 LEAVE STUFFING OPTION FOR PUSH-
BUTTON SWITCH FOR SLP_S3#
4.P19 LEAVE STUFFING OPTION FOR TWO N-MOS
FET FOR SPI CLOCK FREQ STRAPPING WAR
5.LEAVE PULL RESISTORS STUFFING OPTION FOR
LLB*, PWRBN*, EXT_SMI*, LID*, PCI_PME*, PE_WAKE*, SIO_PME*, JTAG_TRST*, JTAG_TMS ,JTAG_TDI
6.P50 CHANGE THE EMI CAP RESERVED LOCATION
FROM C10B2 TO C9B5
7.P10 STUFFING PULL UP RESISTOR R13D1
8.P19 RESERVED DE-CAP FOR RTC_RESET#
9.P40 SETTING BOARD ID = 100 FOR FAB F
REV HISTORY
602-7R177-0000-F00
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Title: Basenet Report Design: mcp79_uatx_sli Date: Mar 19 16:42:31 2008
Base nets and synonyms for mcp79_uatx_sli_lib.MCP79_UATX_SLI(@mcp79_uatx_sli_lib.mc p79_uatx_sli(sch_1)) Base Signal Location([Zone][dir])
+1.1V_CORE_PG_B 44C3 +1.1V_DUAL 19D7 21C2 21C3 45A7 48B3 +1.4V_DUAL_PWRGD_DLY 45A7 +1.8V_DUAL_LAN0 34A6> 34D1< +1.8V_SUS 13A3 21C6 21C6 21C6 23A8 23C2 23D2 24C2 25C2 25D2 26C2 27C7 27C7 27D7 27D7 39C7 47A3 47C3 47C3 50B3 50D5 +3.3V 11B6 15B5 15B6 15D2 17B2 17B8 17D2 17D2 17D2 19D8 19E7 19F7 21A6 21B2 21B3 23C2 24C2 25B2 26C2 28A8 28D3 28D3 28D4 28D6 29B2 29D3 29D3 29D4 29D6 30B2 30D3 30D3 30D4 30D6 31B4 31D1 31D2 32B4 32C5 32D5 35D2 36A7 36B7 36C8 37A4 37B3 37B5 37D7 39A8 39B1 39B2 39B2 39C1 39D5 40B3 40B4 40B4 40B4 42C3 42D7 43C3 44B4 44B6 44C6 44C8 44D6 45D4 46E7 48D6 49C5 50C3 50C6 50C7 50D5 50D6 +3.3V_DUAL 16B7 16F5 16F5 18B1 19B4 19B5 19D1 19D6 19D7 19D7 19E1 19E6 19E6 21B2 21B3 21C1 22B6 28D6 29B2 29D6 30B2 30D6 31A1 31A2 31D4 34A1 34A3 34A5 34B7 34B8 34B8 34C3 34D3 34D8 36B7 37A4 39A7 39D3 43D3 44A2 44A8 44B1 44B5 44D2 45A4 45A5 45A6 45C5 45C6 45D3 47C1 48B4 50B4 +3.3V_VBAT 19B5> 19B8< 43D1> +5V 15C2 31B1 31B4 32A2 32D5 36A1 36A5 36B3 36B4 36D1 36D2 36D5 37C2 38A4 39C8 40A7 40D2 41C5 42B7 43B2 44A7 44B4 44B4 44C7 44D1 44D6 45D3 46B6 46B7 46B7 46B7 46C7 46F4 49C8 49D8 50A5 50B5 +5VA 37D1 37D4 +5V_DUAL 22B5 33A4 33C5 33D3 33D4 35B5 37D1 44B3 44B8 44D2 45A8 45C2 47B2 47D5 47D7 47D7 49D2 49D2 50B6 50D4 50D4 +5V_LPT 41B4< 41C4> +5V_SPDIF 38A4 +5V_SPDIF_HDR 37B2 +5V_STBY 44B6 44D3 44D5 44D6 44D7 45A6 45B3 45B6 45C4 45D5 45D6 45D8 +12V 28B8 28D4 28D5 29C2 29D4 29D6 30C2 30D4 30D6 31C4 32C2 36A4 37A4 37D4 39D8 40A8 40D3 42B5 42B5 42C1 42C2 42C5 42D3 42D6 44B7 44C7 44D6 45D4 46B4 46C4 46F4 46F4 48C7 48D7 49B7 49C6 +DVDD_LAN0 34D4 +V_CPU 9D2 10D7 10D8 39C8 46D6 46E1 +V_DDC_PULLUP 36A3< 36B7<
-12V 31C4 40A8 40D2 44C6 44D6 3VDUAL_BASE 45C5 3VDUAL_BASE_R 45C6 3VDUAL_CTRL_DRAIN 45C5 3VDUAL_REG_FB 45C7 5VDUAL_FET_GATE 44D4< 45B4> 5V_STBY_REF 45D7> 49C4< 7A_CORE_FB_FILT 48C5 7A_CORE_FB_FILT2 48D7 7A_CORE_REG_COMP 48D7 7A_CORE_SNUB 48C4 12V_FILT 46C2< 46D2< 46D2< 46F2> 46F2< 1394_GRST* 32B7> 32C8< A20GATE 19E3< 39B2> AUDAMPIN_L 37D4> 38C8< AUDAMPIN_R 37D4> 38C8< AUDIN_L 38D6 AUDIN_R 38D6 AUDIO_GND 37A6 37A7 37A8 37B5 37B5 37B5 37B7 37C3 37C5 37D1 37D2 37D4 37D4 37D4 38A2 38A2 38A5 38A6 38A6 38A6 38B2 38B2 38B2 38B5 38B5 38B6 38B6 38C2 38C5 38D2 38D2 38D2 38D5 38D5 38D6 43D6 43D7 50D3 AUDIO_VREF 37C5 AUD_IN_L 37C7> 38D7< AUD_IN_R 37C7> 38D7< AUD_MIC1_L 37C7< 38B8> AUD_MIC1_R 37C7< 38B8> AUD_MIC_1L 38B6 AUD_MIC_1R 38B6 AUXFANCNTL* 42D6 AUXFANCNTL_D 42D6 AUXFAN_TACH_RR 42C5 BATT_PWR 43C4
BATT_PWR_R 39C7< 39D2< 43C2> BCLK_IN 12C4 BCLK_IN* 12C4 BIOS_DEBUG 40B3 BLUE_A 36C2 BLU_MEMLED_AN 47A2 BSEL0 9C5> 12C3> BSEL1 9C5> 12C3> BSEL2 9C5> 12C2> BUF0_25MHZ 19D2> 34C8< BUF0_25MHZ_R 19D3 BUF_HSYNC_A 36C2 BUF_SIO_CLK 19D1> 39D6< BUF_SIO_CLK_R 19D3 BUF_VSYNC_A 36C2 CEN_LFE_JD 37C2< 38D4> CEN_OUT 37C4> 38D4< COM_CTS1* 39B6> 40C8> COM_DCD1* 39B6> 40D8> COM_DSR1* 39B6> 40D8> COM_DTR1* 39B1> 40C8< COM_RI1* 39B6> 40C8< COM_RTS1* 39B1> 40C8< COM_RXD1 39B6> 40D8> COM_TXD1 39B1> 40C8< COREVIDAUX1 48B3 CPUFAN_CNTL 19D3> 42B4< CPUFAN_CNTLR 42B2 CPUFAN_TACH 19D3< 42A2> CPUFAN_TACH_RR 42C2 CPUVDD_EN 19D3> 49C8< 49D4< CPUVDD_EN_GATE 49C7 CPUVTT_DH 49B6 CPUVTT_DL 49B6 CPUVTT_FB 49B6 CPUVTT_FB_FILT 49B5 CPUVTT_FB_FILT2 49B7 CPUVTT_PHASE 49B5 CPUVTT_REG_COMP 49B7 CPU_A*<35..3> 8D3<> 12D6<> CPU_A20M* 9D7< 12C6< CPU_ADS* 8B3<> 12C6< CPU_ADSTB0* 8C3<> 12D6<> CPU_ADSTB1* 8B3<> 12D6<> CPU_AL3_PD 8C7 CPU_BNR* 8A3<> 12C6< CPU_BPM*<5..0> 9B7< 10D2< 11D5< CPU_BPRI* 8B3< 12C6< CPU_BR0* 8B2<> 12C6< CPU_C9 10A1> 10B4< 10D4> CPU_CLK 9D4< 12D1> CPU_CLK* 9D4< 12D1> CPU_CLK_COMP_N 12B4 CPU_CLK_COMP_P 12B4 CPU_COMP0 9B4 CPU_COMP1 9B4 CPU_COMP2 9D4 CPU_COMP3 9D4 CPU_COMP4 10A1> 10C5< CPU_COMP5 10A1> 10C5< CPU_COMP6 10A1> 10A5< CPU_COMP7 10A1> 10B4< CPU_COMP8 10A1> 10A5> CPU_COMP_GND 12B6 CPU_COMP_VCC 12B6 CPU_CORE_FB+ 10B4> 46D7< CPU_CORE_FB- 10B4> 46C7< CPU_D*<63..0> 8A6<> 12F4<> CPU_DBI0* 8B3<> 12F6<> CPU_DBI1* 8B3<> 12E6<> CPU_DBI2* 8B3<> 12E6<> CPU_DBI3* 8B3<> 12E6<> CPU_DBSY* 8A3<> 12C6< CPU_DEFER* 8A3< 12C6< CPU_DRDY* 8A3<> 12C6< CPU_DSTBN0* 8B3<> 12F6<> CPU_DSTBN1* 8B3<> 12E6<> CPU_DSTBN2* 8B3<> 12E6<> CPU_DSTBN3* 8B3<> 12E6<> CPU_DSTBP0* 8B3<> 12F6<> CPU_DSTBP1* 8B3<> 12F6<> CPU_DSTBP2* 8B3<> 12E6<> CPU_DSTBP3* 8B3<> 12E6<> CPU_E5_PD 10B5 CPU_FERR* 9D7< 12C6< CPU_FORCE_PR* 10A3< 46A5> CPU_G1 10D4> 10D7< CPU_GTLREF0 9B7 CPU_GTLREF1 10C5 CPU_GTLREF1_SEL 10C1< 19D3> CPU_GTLREF2 10B5 CPU_GTLREF3 9C4< 9D6> CPU_GTLREFR0 9B7< 11A4> CPU_GTLREFR1 10C2< 11A4> CPU_GTLREFR2 10B4< 11A4>
CPU_GTLREFR3 9D8< 11A4> CPU_HIT* 8A3<> 12C6< CPU_HITM* 8A3<> 12C6< CPU_IERR* 8A4 CPU_IGNNE* 9D7> 12C6< CPU_INIT* 9D7< 12C6< CPU_INTR 9D7< 12C6< CPU_ITP_CLK 12D3 CPU_ITP_CLK* 12D3 CPU_J3_PD 10A5 CPU_LOCK* 8A3<> 12C6< CPU_MSID0 9A4< 9A7> CPU_MSID1 9A4< 9A7> CPU_NMI 9D7< 12C6< CPU_PECI_MCP 9D8< 12C4> CPU_PECI_O 9C4< 9D7> CPU_PECI_SPIO 9D8< 39C2< CPU_PROCHOT* 9C7< 12C4> 46A5> CPU_PWRGD 19D3< 46E7> CPU_REQ*<4..0> 8A6<> 12D6<> CPU_RS*<2..0> 8A6< 12C7< CPU_RST* 8A2< 11C6< 12C4> CPU_RST_XDP* 11C5 CPU_RSVD_G6 10A5 CPU_SLP* 9A4 CPU_SMI* 9D7< 12C6< CPU_STPCLK* 9D7< 12C6> CPU_THERMDA 9C4> 39B8< CPU_THERMDA1 8D5> 39A8< CPU_THERMDA1R 8D7 CPU_THERMDC 9C4> 39A8< CPU_THERMDC1 8D5> 39A8< CPU_THERMDC1R 8D7 CPU_THERMTRIP* 9C7> 12B4> CPU_TRDY* 8A3< 12C6< CPU_VCC_PLL 10A4< 49D5> CPU_VID<7..0> 9B5> 9C1< 10C4> 46E7< CPU_VIDSEL 10C3> 46D7< CPU_VTT_OV0 39B6> 49A6< CPU_VTT_OV1 39B6> 49A6< CPU_VTT_OV2 39B2> 49A6< CPU_VTT_PWRGD 9C7< 46E7< 49D1> CPU_VTT_SEL 10C4> 49A8< CTS1 40C4 DAC_BLUE 15C7> 36C8< DAC_GREEN 15C7> 36C8< DAC_HSYNC 15C6> 36D8< DAC_RED 15C7> 36C8< DAC_RSET 15C5 DAC_VREF 15C5 DAC_VSYNC 15C6> 36D8< DCD1 40D4 DDC_CLK 15C3> 36C8< DDC_CLK3_R 15C4 DDC_DATA 15C3<> 36C8<> DDC_DATA3_R 15C4 DDC_SCL 36C2 DDC_SDA 36C2 DIMM_VREF_CH0 25C1> 26C2< 47B4< DIMM_VREF_CH1 23C1> 24C2< DRSEL 46C5 DSR1 40D4 DTR1 40C4 DUALS_FET_GATE 45C5 EMICAP1 36C2 EMICAP2 36C2 EXT_SMI* 19E2> 19E3< 39C2> FAN_SET 39C3 FAN_SET2 39B3 FB_AUDOUTR_L 38C7 FB_AUDOUTR_R 38C7 FB_AUDOUT_L 38C6 FB_AUDOUT_R 38C6 FP_AUDIO_PRESENCE* 17B3< 37B5> FP_IO_JD 37B8> 37C2< FP_MIC2R_L 37B6 FP_MIC2R_R 37B6 FP_MIC2_JD_R 37B5 FP_MIC2_L 37B8> 37C7< FP_MIC2_R 37B8> 37C7< FP_MICVREF 37B8< 37D4> FP_MICVREF_D1 37B7 FP_MICVREF_D2 37B7 FP_OUTR_L 37B6 FP_OUTR_R 37B6 FP_OUT_JD_R 37B5 FP_OUT_L 37B8> 37D7> FP_OUT_R 37B8> 37C7> FP_RESET* 19E3< 44A4> 46B8< FRONT_JD 37D8< 38C8> FW_1P8V_1 32D7 FW_1P88_2 32D7 FW_AVDD 32A4< 32D4> FW_CBL_PWR2 32C1> 32C4< FW_CLKRUN* 32C7
FW_DVDD 32A4< 32A7< 32B4< 32C4> 32C8< 32D7< FW_FB_FNT1 32B1 FW_FILTER0 32B5 FW_FILTER1 32B5 FW_GPIO2 32A8 FW_GPIO3 32A8 FW_R0 32B5 FW_R1 32B5 FW_SCL 32A8 FW_SDA 32A8 FW_TPA1 32B3 FW_TPA1* 32B3 FW_TPB1 32B2 FW_TPB1* 32B2 FW_VDD_PLL 32B4 FW_XI 32A7 FW_XO 32A7 GND 8A7 8A8 9A8 9A8 9A8 9A8 9B5 9B5 9B6 9B7 9B7 9B8 9B8 9C5 9C5 9C7 9C8 9C8 9C8 10A2 10A3 10A3 10A4 10A4 10A5 10A5 10A7 10B2 10B2 10B3 10B3 10B3 10B5 10C2 10C3 10C3 10C3 10C4 10D7 11A4 11A6 11B3 11B6 11C1 12B3 12B6 12C3 12D2 12D2 12D3 13A3 14A1 14A2 15A6 15B3 15B5 15B6 15C3 15C3 15C6 15C6 15C6 15C6 15C6 15C6 15C6 15D3 15D3 15D6 16B6 16B7 16C6 16C6 16E5 16F5 17A2 17A4 17C2 17C3 17C3 18A1 18A2 18A2 18A5 18A6 18A6 18A6 18A7 18A7 18A8 18A8 18B8 18C8 18C8 18D8 19A3 19A4 19A4 19A5 19B3 19B5 19B5 19B6 19B6 19B7 19B7 19B7 19C6 19C6 19C7 19C7 19D2 19D5 19D7 19D7 19E2 19E6 19F6 19F6 19F6 19F7 20B3 20B4 20B4 20B6 20C3 20C3 20D6 20D6 20E3 20E3 20E6 20E7 21A3 21A3 21A3 21A3 21A3 21A5 21A6 21A6 21B2 21B2 21B3 21B3 21B6 21C1 21C1 21C2 21C3 21C3 21C6 22A4 22B5 22B5 22D1 22E1 23A1 23A6 23C1 23C2 23C2 24A1 24C1 24C2 25A1 25B2 25C1 25C2 26A1 26C1 26C2 27B6 27C3 28A8 28A8 28C2 28C4 28C5 28C6 29A2 29A4 29A6 29B2 29C2 29D3 29D6 30A2 30A4 30A6 30B2 30C2 30D3 30D6 31A1 31A1 31A4 31C1 31C4 32A1 32A2 32A3 32A4 32A5 32A5 32A7 32A7 32A7 32A7 32A8 32A8 32B1 32B2 32B2 32B2 32B3 32B4 32B5 32B8 32C4 32C4 32D3 32D4 32D7 33A2 33A3 33A5 33A5 33A5 33A5 33A6 33A7 33B4 33B4 33B4 33B5 33B5 33B5 33C2 33C3 33C5 33D2 33D2 33D3 33D3 33D5 33D5 33D5 33D5 34A1 34A2 34A5 34A7 34A7 34A7 34A8 34B1 34B4 34B6 34B7 34B8 34C2 34C3 34C4 34C4 34C7 34C7 34C7 34D2 34D4 35A1 35A2 35A3 35A4 35B3 35B3 35C2 36A1 36A1 36A2 36A4 36A5 36A6 36A7 36A7 36B2 36B2 36B2 36B2 36B3 36C1 36C1 36C3 36C3 36C4 36C4 36C5 36C5 36C5 36C6 36C6 36C6 36C7 36C7 36C7 36D1 36D2 36D5 36D7 37A2 37A2 37A2 37A4 37A8 37B1 37B2 37B2 37B2 37B2 37B3 37C2 37C6 37D3 37D6 37D6 37D7 37D7 37D8 38A4 38A4 38A4 39A1 39A2 39A4 39A5 39A5 39A7 39A8 39C1 39C2 40A4 40A4 40A4 40A7 40B3 40C1 40C2 40D2 40D2 40D3 41A6 42A5 42A6 42A6 42A7 42B1 42B5 42B5 42C2 42C2 42C5 42C6 42C6 42D3 42D4 42D5 42D5 43A1 43B2 43B5 43B6 43B6 43B7 43B7 43B8 43C4 43C5 43C6 43D2 43D3 44A3 44A5 44A7 44A8 44B1 44B3 44B3 44B3 44B4 44B4 44B4 44B4 44B5 44B6 44B6 44B6 44B6 44B7 44B7 44B7 44B7 44B7 44B8 44B8 44B8 44B8 44C1 44C2 44C2 44C3 44C3 44C3 44C5 44C6 44C6 44C7 44D7 45A3 45A4 45A4 45A5 45A6 45A6 45A7 45A8 45B1 45B2 45B3 45B4 45B5 45B5 45B6 45C2 45C3 45C4 45C4 45C6 45C6 45C8 45C8 45D6 46A4 46A4 46A6 46A6 46A7 46A7 46A7 46A7 46B1 46B2 46B2 46B2 46B2 46B3 46B4 46B4 46B5 46B5 46B6 46B6 46B6 46B6 46B7 46B7 46C1 46C1 46C1 46C2 46C2 46C2 46C2 46C3 46C3 46C3 46C4 46C5 46C6 46C6 46D1 46D1 46D1 46D1 46D1 46D1 46D1 46D2 46D2 46D2 46D2 46D3 46D3 46D4 46D4 46E1 46E1 46E1 46E1 46E2 46E2 46E2 46E2 46E3 46E3 46E4 46E4 46E5 46E5 46E7 46F3 46F3 46F4 46F4 46F4 47A2 47B2 47B3 47B3 47B3 47B3 47B6 47C1 47C1 47C2 47C4 47C5 47C5 47C6 47C6 47C6 47C6 47C7 47C7 47D5 47D7 47D7 47D8 48A3 48A4 48A4 48B3 48B6 48C4 48C4 48C5 48C6 48C7 48C7 48D5 48D6
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456 3 2 18 7
48D6 48D6 48D7 49A3 49A7 49A7 49B4 49B5 49B5 49B5 49B6 49B6 49B7 49B7 49C1 49C2 49C2 49C3 49C3 49C5 49C6 49C7 49C7 49D6 49D7 49D8 50A5 50B3 50B6 50B7 50C3 50C6 50D3 50D6 GREEN_A 36C2 GRN_PWRLED 39A6> 44B2< GRN_PWRLED_AN 44C1 GTLREF_FS0 11A5 GTLREF_FS1 11A5 GTLREF_FS2 11A5 GTLREF_FS3 11A5 HDABCLK 19F5 HDARST* 19E5 HDASDOUT 19F5 HDASYNC 19F5 HDA_BITCLK 19F6> 37A6< 37C7< HDA_DCVOL 37C5 HDA_PULLDN_COMP 19E5 HDA_RST* 19E8> 37A6< 37D7< HDA_SDIN0_R 37D6 HDA_SDIN1_R 37A6 HDA_SDIN_0 19F7< 37D8> HDA_SDIN_1 19E5< 35B8<> 37A7> HDA_SDOUT 19F7> 37A6< 37D7< HDA_SYNC 19E8> 37A6< 37D7< HDCP_WP 15B6 HDLED_PWR 44B4 HDMI_CEC 19C3< 36A8< HDMI_CEC_C 36A5 HDMI_DDC_CLK 15C3> 36A8< HDMI_DDC_CLK_R 36A5 HDMI_DDC_DATA 15C3<> 36A8< HDMI_DDC_DATA_R 36A5 HDMI_TXC0N 15E3> 36B6< HDMI_TXC0N_C 36A3 HDMI_TXC0P 15E3> 36B6< HDMI_TXC0P_C 36A3 HDMI_TXD0N 15E3> 36B6< HDMI_TXD0N_C 36A3 HDMI_TXD0P 15E3> 36B6< HDMI_TXD0P_C 36A3 HDMI_TXD1N 15E3> 36B6< HDMI_TXD1N_C 36B3 HDMI_TXD1P 15E3> 36B6< HDMI_TXD1P_C 36B3 HDMI_TXD2N 15E3> 36B4< HDMI_TXD2N_C 36B3 HDMI_TXD2P 15E3> 36B4< HDMI_TXD2P_C 36B3 HPLUG_DET2 15C3< 36A8> HPLUG_DET3 15C4 IDSEL_1394 32A7 IFPAB_RSET 15D4 IFPAB_VPROBE 15D4 INTERPOSER_BCLK 9B5< 12D1> INTERPOSER_BCLK* 9B5< 12D1> INTRUDER* 19B8> 19C5> ISENSE1 46D4 46E2 ISENSE2 46D2 46D4 ISENSE3 46C2 46C4 ISENSE4 46B2 46C4 JDREF 37C5 JTAG_TCK_MCP 19F1< 22B4> JTAG_TDI_MCP 19F1< 22B6> JTAG_TDO_MCP 19F1> 22B4< JTAG_TDO_MCP_R 19F3 JTAG_TMS_MCP 19F1< 22B6<> JTAG_TRST_M 22B5 JTAG_TRST_MCP* 19F1< 22B4> KBCLOCK_FB 35B3 KBCLOCK_R 35B6 KBDATA_FB 35B3 KBDATA_R 35B6 KEYBRD_PWR1 35B4 KEYBRD_PWR2 35B3 LAN0_ADJ 34A7 LAN0_CONFIG3 34B6 LAN0_CT 34C2 LAN0_LED0 34B4 LAN0_LED1 34B4 LAN0_LED2 34B4 LAN0_MDI0+ 34C4 LAN0_MDI0- 34C4 LAN0_MDI1+ 34C4 LAN0_MDI1- 34C4 LAN0_MDI2+ 34B4 LAN0_MDI2- 34B4 LAN0_MDI3+ 34B4 LAN0_MDI3- 34B4 LAN0_RSET 34B4 LAN0_TRST* 34C6 LAN1_XTAL1 34C7 LAN1_XTAL1_R 34C8 LAN1_XTAL2 34C7
LAN1_XTAL2_R 34C7 LAN_VREF 34B7 LFE_L 38D2 LFE_OUT 37C4> 38D4< LFE_R 38D2 LIB_LID* 19E2> 19E3< LINE2_VREFO 37A8< 37C4> LINE2_VREFO_D1 37B7 LINE2_VREFO_D2 37A7 LINEIN_JD 37C8< 38D7< LOAD_LN_ID0 9B4 LOAD_LN_ID1 9B4 LPC_AD<3..0> 17B2<> 35D3<> 39D2<> LPC_AD_R<0> 17B4 LPC_AD_R<1> 17B4 LPC_AD_R<2> 17B4 LPC_AD_R<3> 17B4 LPC_CLK0 17A4 LPC_CLK_FLASH 17A2> 35D1< LPC_CLK_SIO 17A2> 39D6< LPC_DRQ0* 17B3< 39D2> LPC_FRAME* 17B1> 35D3< 39D6< LPC_FRAME_R* 17B4 LPC_RESET* 17B4 LPC_RST_FLASH* 17A2> 35D1< LPC_RST_SIO* 17B2> 39D6< LPC_SERIRQ 17B3< 39D2<> MCP7A_CORE_AUX_OV0 39B6> 48A1< MCP7A_CORE_AUX_OV1 39B6> 48A1< MCP7A_CORE_AUX_OV2 39B6> 48A1< MCP7A_CORE_DH 48C6 MCP7A_CORE_DL 48C6 MCP7A_CORE_FB 48B7 MCP7A_CORE_LX 48C5 MCP7A_CORE_OV0 39A6> 48B6< MCP7A_CORE_OV1 39A6> 48B6< MCP7A_CORE_OV2 39A6> 48B6< MCP7A_CPU_PWRGD 9C7< 11C6< 12B6> MCP7A_THERM_DIODE_N 19C3> 39A8< MCP7A_THERM_DIODE_P 19C3> 39A8< MCP_COM_CTS1* 17D1> 40B8> MCP_COM_DCD1* 17B8> 40B8> MCP_COM_DSR1* 17D1> 40B8> MCP_COM_DTR1* 17C3> 40A8< MCP_COM_RTS1* 17C3> 40B8< MCP_COM_RXD1 17D1> 40B8> MCP_COM_TXD1 17C3> 40B8< MCP_KB_DA 19E5< 35B8<> MCP_MS_CK 19E5> 35A8<> MCP_MS_DA 19E5> 35A8<> MEM_0A_CKE<1..0> 13B8> 25D5< 27A8< MEM_0A_CLK0 13B7> 25C5< MEM_0A_CLK0* 13B7> 25C5< MEM_0A_CLK1 13A7> 25C5< MEM_0A_CLK1* 13A7> 25C5< MEM_0A_CLK2 13A7> 25C5< MEM_0A_CLK2* 13A7> 25C5< MEM_0A_CS*<1..0> 13B7> 25D5< 27A8< MEM_0A_ODT<1..0> 13B8> 25D5< 27B8< MEM_0B_CKE<1..0> 13A8> 26D5< 27C3< MEM_0B_CLK0 13A7> 26C5< MEM_0B_CLK0* 13A7> 26C5< MEM_0B_CLK1 13A7> 26C5< MEM_0B_CLK1* 13A7> 26C5< MEM_0B_CLK2 13A7> 26C5< MEM_0B_CLK2* 13A7> 26C5< MEM_0B_CS*<1..0> 13A7> 26D5< 27B3< MEM_0B_ODT<1..0> 13A8> 26D5< 27C3< MEM_0_ADD<14..0> 13C7> 25B8< 26C8< 27B8< MEM_0_BA<2..0> 13B7> 25D5< 26D5< 27A8< MEM_0_CAS* 13A3<> 25C5< 26C5< 27A8< MEM_0_DATA<63..0> 13D3<> 25A3<> 26A3<> MEM_0_DQM<7..0> 13C7> 25C8< 26C8< MEM_0_DQS*<7..0> 13D7<> 25C8<> 26C8<> MEM_0_DQS<7..0> 13D7<> 25C8<> 26C8<> MEM_0_RAS* 13A3<> 25C5< 26C5< 27A8< MEM_0_WE* 13A3<> 25C5< 26C5< 27A8< MEM_1A_CKE<1..0> 14B8> 23D5< 27A5< MEM_1A_CLK0 14B7> 23C5< MEM_1A_CLK0* 14A7> 23C5< MEM_1A_CLK1 14A7> 23C5< MEM_1A_CLK1* 14A7> 23C5< MEM_1A_CLK2 14A7> 23C5< MEM_1A_CLK2* 14A7> 23C5< MEM_1A_CS*<1..0> 14B7> 23D5< 27A5< MEM_1A_ODT<1..0> 14B8> 23D5< 27B5< MEM_1B_CKE<1..0> 14A8> 24D5< 27A3< MEM_1B_CLK0 14A7> 24C5< MEM_1B_CLK0* 14A7> 24C5< MEM_1B_CLK1 14A7> 24C5< MEM_1B_CLK1* 14A7> 24C5< MEM_1B_CLK2 14A7> 24C5< MEM_1B_CLK2* 14A7> 24C5< MEM_1B_CS*<1..0> 14A7> 24D5< 27A3< MEM_1B_ODT<1..0> 14A8> 24D5< 27B3<
MEM_1P8V_R 47C5 MEM_1_ADD<14..0> 14C7> 23C8< 24C8< 27B5< MEM_1_BA<2..0> 14B7> 23D5< 24D5< 27A5< MEM_1_CAS* 14A3<> 23C5< 24C5< 27A5< MEM_1_DATA<63..0> 14D3<> 23A3<> 24A3<> MEM_1_DQM<7..0> 14C7> 23C8< 24C8< MEM_1_DQS*<7..0> 14D7<> 23C8<> 24C8<> MEM_1_DQS<7..0> 14D7<> 23C8<> 24C8<> MEM_1_RAS* 14A3<> 23C5< 24C5< 27A5< MEM_1_WE* 14A3<> 23C5< 24C5< 27A5< MEM_BST 47C7 MEM_COMP_1P8V 13A4 MEM_COMP_GND 13A4 MEM_DH 47C6 MEM_DL 47C6 MEM_FB 47B7 MEM_FB_FILT 47B6 MEM_FB_FILT2 47C8 MEM_HIGH_DRAIN 47D5 MEM_LX 47C6 MEM_OV0 39B2> 47A7< MEM_OV1 39A6> 47A7< MEM_OV2 39A6> 47A7< MEM_REG_COMP 47C7 MIC1_JD 37C8< 38B8> MIC1_VREFO_L 37C4> 38B8< MIC1_VREFO_R 37D4> 38A8< MII_COMP_3P3V 19D5 MII_COMP_GND 19D5 MII_VREF 19D5 MSCLOCK_FB 35A3 MSCLOCK_R 35A6 MSDATA_FB 35A3 MSDATA_R 35A6 OFS 46C5 OVPSEL 46C5 PCI_ACK64* 31A3> 31A7> PCI_AD<31..0> 17D7<> 31D7<> 32C8<> PCI_C/BE*<3..0> 17B7<> 31B7<> 32C8<> PCI_CLK0 17C4 PCI_CLK1 17C4 PCI_CLK2 17C4 PCI_CLKIN 17C4 PCI_CLKSLOT1 17C1> 31A7< PCI_CLK_1394 17C1> 32C8< PCI_DEVSEL* 17B7<> 31B3> 31B7<> 32D8<> PCI_FRAME* 17B7<> 31B3> 31B7<> 32C8<> PCI_GNT0* 17C3> 31B7<> PCI_GNT1* 17C3> 32C8< PCI_INTW* 17C3< 31B7> 31C3> PCI_INTX* 17C3< 31B7> 31C3> PCI_INTY* 17C3< 31B7> 31C3> PCI_INTZ* 17C3< 31B7> 31C3> 32D8> PCI_IRDY* 17B7<> 31B3> 31B7<> 32C8<> PCI_LOCK* 31A7<> 31B3> PCI_PAR 17B7<> 31A7<> 32C8<> PCI_PERR* 17B8> 31A7> 31B3> 32C8> PCI_PME* 17B7< 31A3> 31B7> 32D8> PCI_REQ*<1..0> 17D3< 31B7<> 31D3> 32C8<> PCI_REQ64A* 31A3> 31A7< PCI_RESET0* 17A6 PCI_RESET1* 17A6 PCI_RST_1394* 17A8> 32C8< PCI_RST_SLOTS_1* 17A8> 31A7< PCI_SERR* 17B7> 31A7> 31B3> 32C8> PCI_STOP* 17B7<> 31A3> 31B7<> 32C8<> PCI_TRDY* 17B7<> 31A3> 31B7<> 32C8<> PC_BEEP 37D6 PD_CPU_A24 8D8 PD_CPU_E29 8A7 PE0_TX0 29D6 PE0_TX0* 29C6 PE0_TX1 29C6 PE0_TX1* 29C6 PE0_TX2 29C6 PE0_TX2* 29C6 PE0_TX3 29C6 PE0_TX3* 29C6 PE0_TX4 29C6 PE0_TX4* 29C6 PE0_TX5 29B6 PE0_TX5* 29B6 PE0_TX6 29B6 PE0_TX6* 29B6 PE0_TX7 29B6 PE0_TX7* 29B6 PE0_TX8 30D6 PE0_TX8* 30C6 PE0_TX9 30C6 PE0_TX9* 30C6 PE0_TX10 30C6 PE0_TX10* 30C6 PE0_TX11 30C6 PE0_TX11* 30C6 PE0_TX12 30C6
PE0_TX12* 30C6 PE0_TX13 30B6 PE0_TX13* 30B6 PE0_TX14 30B6 PE0_TX14* 30B6 PE0_TX15 30B6 PE0_TX15* 30B6 PE1_CLKREQ* 16C5 PE1_TCK 30D4 PE1_TDI 30D4 PE1_TMS 30D4 PE2_CLKREQ* 16C5 PE2_PRESENT* 16C6< 28C7> PE2_REFCLK 16D6> 28C3< PE2_REFCLK* 16D6> 28C3< PE2_RX 16D6> 28C3> PE2_RX* 16D6> 28C3> PE2_TCK 28C4 PE2_TDI 28C4 PE2_TMS 28C4 PE2_TRST* 28C6 PE2_TX 28C6 PE2_TX* 28C6 PE2_TXC 16E6> 28C7< PE2_TXC* 16E6> 28C7< PEXRESET0* 16B6> 16C6> 16F6< PE_CLK_COMP 16C5 PE_RESET* 16E4> 28C3< 29D2< 30D2< PE_TCK 29D4 PE_TDI 29D4 PE_TMS 29D4 PE_WAKE* 16B6> 16C6< 28C7> 29D8> 30D8> PE_X8-1_PRESENT* 16B3< 29B8> PE_X8-1_REFCLK 16B3> 29D2< PE_X8-1_REFCLK* 16B3> 29D2< PE_X8-1_RX*<7..0> 16C2< 29C2> PE_X8-1_RX<7..0> 16C2< 29C2> PE_X8-1_TXC*<7..0> 16D2> 29B8< PE_X8-1_TXC<7..0> 16E2> 29B8< PE_X8-2_PRESENT* 16C6< 30B8> PE_X8-2_REFCLK 16D6> 30D2< PE_X8-2_REFCLK* 16D6> 30D2< PE_X8-2_RX*<15..8> 16C3< 30C2> PE_X8-2_RX<15..8> 16D3< 30C2> PE_X8-2_TXC*<15..8> 16D3> 30B8< PE_X8-2_TXC<15..8> 16E3> 30B8< PHASE1 46D4 46E2 PHASE2 46D2 46D4 PHASE3 46C2 46C4 PHASE4 46B2 46C4 PR1_TRST* 30D6 PR_TRST* 29D6 PS_ON* 44D7 PS_ON_R* 39A6< 44D8< PS_PG_SC1 44C3 PS_PWRGD 16E6< 19D3< 21A7< 32B7< 44D2> PS_PWRGD_STG2 44D3 PWRBTN* 19E3< 44B1> PWRBTN_R* 44B3 PWRGD_PS 44D4> 45B7< PWRGD_PS* 45B6 PWRGD_PS_BASE 44C3 PWRGD_SB 19D3< 43D5< 45A4> PWRGD_SB_N 45A6 P_GTLREF 10B3 RED_A 36C2 RGMII0_INTR* 19D6< 34A2> RGMII0_MDC 19D6> 34C8< RGMII0_MDIO 19D6> 34C8<> RGMII0_PWRDWN* 19D6> 34B8< RGMII0_PWRDWNR* 19D5 RGMII0_RXC 19D6< 34C7> RGMII0_RXCLK_R 34C6 RGMII0_RXCTL 19D6< 34C7> RGMII0_RXD<3..0> 19E6< 34D8> RGMII0_TXC 19E6> 34D7< RGMII0_TXCTL 19D6> 34D7< RGMII0_TXCTL_R 19D5 RGMII0_TXC_R 19E5 RGMII0_TXD0_R 19E5 RGMII0_TXD1_R 19E5 RGMII0_TXD2_R 19E5 RGMII0_TXD3_R 19E5 RGMII0_TXD<3..0> 19E6> 34D7< RGMII_RESET* 19D6> 34C8< RI1 40C4 RST_SWR* 44B5 RTC_R 19B7 RTC_RST* 19C5 RTS1 40C4 RXD1* 40D4 SATA_A0_RX_N 18D6 SATA_A0_RX_N_C 18D8 SATA_A0_RX_P 18D6 SATA_A0_RX_P_C 18D8
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SATA_A0_TX_N 18D6 SATA_A0_TX_N_C 18D8 SATA_A0_TX_P 18D6 SATA_A0_TX_P_C 18D8 SATA_A1_RX_N 18C6 SATA_A1_RX_N_C 18C8 SATA_A1_RX_P 18C6 SATA_A1_RX_P_C 18C8 SATA_A1_TX_N 18D6 SATA_A1_TX_N_C 18D8 SATA_A1_TX_P 18D6 SATA_A1_TX_P_C 18D8 SATA_B0_RX_N 18C7 SATA_B0_RX_N_C 18C8 SATA_B0_RX_P 18C7 SATA_B0_RX_P_C 18C8 SATA_B0_TX_N 18C7 SATA_B0_TX_N_C 18C8 SATA_B0_TX_P 18C7 SATA_B0_TX_P_C 18C8 SATA_B1_RX_N 18B6 SATA_B1_RX_N_C 18B8 SATA_B1_RX_P 18B6 SATA_B1_RX_P_C 18B8 SATA_B1_TX_N 18B6 SATA_B1_TX_N_C 18B8 SATA_B1_TX_P 18B6 SATA_B1_TX_P_C 18B8 SATA_C0_RX_N 18B6 SATA_C0_RX_N_C 18B8 SATA_C0_RX_P 18B6 SATA_C0_RX_P_C 18B8 SATA_C0_TX_N 18B6 SATA_C0_TX_N_C 18B8 SATA_C0_TX_P 18B6 SATA_C0_TX_P_C 18B8 SATA_C1_RX_N 18A6 SATA_C1_RX_N_C 18A8 SATA_C1_RX_P 18A6 SATA_C1_RX_P_C 18A8 SATA_C1_TX_N 18B6 SATA_C1_TX_N_C 18A8 SATA_C1_TX_P 18B6 SATA_C1_TX_P_C 18A8 SATA_HDLED* 18A6> 44B5< SATA_TERMP 18A5 SEL_50_60_OHM 10B5 SENSE_A 37D6 SENSE_B 37C5 SIO_AUXFAN_CNTL 39C2> 42C8< SIO_AUXFAN_TACH 39C6< 42C4> SIO_AUXTIN 39B8 SIO_AVCC 39D6 SIO_BOARD_DEBUG 39D2< 40B1> SIO_BOARD_ID0 39C2< 40B5> SIO_BOARD_ID1 39B6< 40B5> SIO_BOARD_ID2 39D2< 40B5> SIO_CASEOPEN* 39C6 SIO_CPUFAN_CNTL 39C2> 42B4< SIO_CPUFAN_TACH 39B6< 42A2> SIO_CPUVCORE 39C6 SIO_HDCP_WP 15B4< 39A6> SIO_KBRST* 19E3< 39B2> SIO_KB_CK 35B7<> 39C2> SIO_KB_DA 35B7<> 39B2> SIO_LPT_ACK* 39B6< 41A7> 41B7> SIO_LPT_ALF* 39A2> 41C7< SIO_LPT_ALF_R* 41A5> 41C2> SIO_LPT_BUSY 39B6< 41A7> 41B7> SIO_LPT_ERR* 39A6< 41A5> 41C7> SIO_LPT_INIT* 39A2<> 41C7< SIO_LPT_INIT_R* 41A5> 41C2> SIO_LPT_PD0_R 41A7> 41D2> SIO_LPT_PD1_R 41A7> 41D2> SIO_LPT_PD2_R 41A7> 41D2> SIO_LPT_PD3_R 41A7> 41D2> SIO_LPT_PD4_R 41A7> 41D2> SIO_LPT_PD5_R 41A7> 41C2> SIO_LPT_PD6_R 41A7> 41C2> SIO_LPT_PD7_R 41A7> 41C2> SIO_LPT_PD<7..0> 39A2<> 41D7< SIO_LPT_PE 39B6< 41A7> 41B7> SIO_LPT_SLCT 39A6< 41A7> 41B7> SIO_LPT_SLCTIN* 39A2> 41C7< SIO_LPT_SLCTIN_R* 41A5> 41C2> SIO_LPT_STROBE* 39A2> 41C7< SIO_LPT_STROBE_R* 41A7> 41C2> SIO_MS_CK 35A7<> 39C2> SIO_MS_DA 35A7<> 39C2> SIO_PME* 19E2> 19E3< 39D2> SIO_PSIN* 39D6< 44A1> SIO_PSOUT* 39D2> 44B3< SIO_RSMRST* 39A6> 45A6< SIO_SST 39C3 SIO_SYSFAN_CNTL 39C2> 42A8<
SIO_SYSFAN_TACH 39B6< 42A3> SIO_VIN0_1_8V 39C6 SIO_VIN1_1_2V 39C6 SIO_VIN2_5V 39C6 SIO_VIN3_12V 39C6 SIO_VREF 39B8< 39B8< 39C2> SIO_WDTO* 39A6> 46B8< SLP_S3 19A2< 45A4> SLP_S3* 19C2> 19D3> 39A6< 44D8< 45B2< SLP_S5* 19D2> 19D3> 47D8< SMB_MEM_CL 19C8> 23D5< 24D5< 25D5< 26D5< SMB_MEM_CL_R 19C5 SMB_MEM_DA 19C8> 23D5<> 24D5<> 25D5<> 26D5<> SMB_MEM_DA_R 19C5 SMB_SCL 11A7< 11C3< 15B4< 19C8> 28C6< 29D7< 30D7< 31A7< 39D6< 46C7< SMB_SCL_R 19C5 SMB_SDA 11A7<> 11C3<> 15A4<> 19C8> 28C6<> 29D7<> 30D7<> 31A7<> 39D6<> 46C7< SMB_SDA_R 19C5 SPDIFO_RCA 37A3< 37C2> SPDIFO_RCA_L 37A2 SPDIFO_RCA_OUT 37A2 SPDIF_IN_HDR 37B4> 37C4< SPDIF_IN_HDR_R 37B2 SPDIF_IN_HDR_RC 37B3 SPDIF_OUT_HDR 37B4< 37C7> SPDIF_OUT_HDRC 37B3 SPDIF_OUT_HDR_R 37B2 SPDIF_OUT_OPT 37C2> 38A5< SPEAKER 19E5> 37D8< 43B4< SPEAKER_BASE 43B3 SPEAKER_EMITTER 43B2 SPEAKER_R 37D8 SPI_CLK 19A3< 19E3> SPI_CS* 19A5< 19E3> SPI_DI 19A5> 19E3> SPI_DO 19A3< 19E3> SPI_HOLD* 19A4 SPI_WP* 19A5 SS 46C5 SURRB_L 38C2 SURRB_R 38C2 SURRS_L 38B2 SURRS_R 38B2 SURR_BACK_JD 37C8< 38C4> SURR_BACK_L 37C4< 38C4> SURR_BACK_R 37C4< 38C4> SURR_SIDE_JD 37C2< 38B4> SURR_SIDE_L 37C4> 38B4> SURR_SIDE_R 37C4> 38B4> SYSFANCNTL* 42B6 SYSFANCNTL_D 42B6 SYSFAN_CNTL 19D3> 42A8< SYSFAN_TACH 19C3< 42A4> SYSFAN_TACH_RR 42A5 TESTHI_0 9A5 TESTHI_1 9A5 TESTHI_2-7 9A5 TESTHI_8 9A7> 10D4> TESTHI_9 9A7> 10D4> TESTHI_10 9A5 TESTHI_11 9A5 TESTHI_12 9A7> 10A6< TESTMODE 19C3 TPBIAS0 32D3 TPBIAS1 32C2 TP_775_AP0 8C4 TP_775_AP1 8C4 TP_775_BINIT 8A4 TP_775_BOOTSEL 9A4 TP_775_RSP 8A6 TP_775_SKTOCC 9A4 TP_AUXFANIN1 39C6 TP_CPU_AC4 10B5 TP_CPU_AE4 10B5 TP_CPU_D1 10B5 TP_CPU_D14 10B5 TP_CPU_DP0* 8A6 TP_CPU_DP1* 8A6 TP_CPU_DP2* 8A6 TP_CPU_DP3* 8A6 TP_CPU_E6 10B5 TP_CPU_E7 10B5 TP_CPU_E23 10B5 TP_CPU_F23 10B5 TP_CPU_F29 10B5 TP_CPU_MCERR* 8A4 TP_CPU_N4 10A5 TP_CPU_P5 10A5 TP_GTLREF_SEL 10C5 TP_HDALINE1_VREFO_L 37D5 TP_HDA_CDGND 37C6 TP_HDA_CDL 37C6 TP_HDA_CDR 37C6
TP_HDA_GPIO1 37C6 TP_HDA_PIN37 37D5 TP_J12A1_2 35B2 TP_J12A1_6 35B2 TP_J12A1_8 35A2 TP_J12A1_12 35A2 TP_LAN0_CTRL1.8V 34C4 TP_LAN0_GRN_LED_AN 34B1 TP_LAN0_GRN_LED_CAT 34B1 TP_LAN0_HSDAC+ 34B4 TP_LAN0_HSDAC- 34B4 TP_LAN0_TCK 34C6 TP_LAN0_TDI 34C6 TP_LAN0_TDO 34C6 TP_LAN0_TMS 34C6 TP_LAN_TSTPT 34C6 TP_MRESET* 13A4 TP_PCI2_A9 31D4 TP_PCI2_A11 31C4 TP_PCI2_B4 31D4 TP_PCI2_B9 31D4 TP_PCI2_B10 31D4 TP_PCI2_B11 31D4 TP_PCI2_B14 31C4 TP_PE1_RX 16E5 TP_PE1_RX* 16D5 TP_PE1_RX2 16D5 TP_PE1_RX2* 16D5 TP_PE1_RX3 16D5 TP_PE1_RX3* 16D5 TP_PE1_TDO 30D4 TP_PE1_TX2 16E5 TP_PE1_TX2* 16E5 TP_PE1_TX3 16E5 TP_PE1_TX3* 16E5 TP_PE1_TXC 16E5 TP_PE1_TXC* 16E5 TP_PE2_TDO 28C4 TP_PE_TDO 29D4 TP_PWR_N5V 44C6 TP_SIO_BEEP 39C3 TP_SIO_NC109 39C3 TP_SIO_NC110 39C3 TP_SIO_PECISB 39C3 TP_SIO_RSTOUT0* 39C3 TP_SIO_RSTOUT1* 39D3 TP_USB76_12 33A3 TP_USB98_12 33C2 TP_USB1110_12 33B4 TP_VID0 39C6 TP_VID1 39C6 TP_VID2 39C6 TP_VID3 39C6 TP_VID4 39C6 TP_VID5 39C6 TP_VID6 39C6 TP_VID7 39C6 TP_XDP_PRSNT 11C3 TP_XDP_RSVD 11C3 TXD1* 40C4 USB_0 18D2<> 33D8<> USB_0* 18D2<> 33D8<> USB_0_FB 33D7 USB_0_FB* 33D7 USB_1 18D2<> 33C8<> USB_1* 18C2<> 33C8<> USB_1_FB 33D7 USB_1_FB* 33D7 USB_2 18C2<> 33C8<> USB_2* 18C2<> 33C8<> USB_2_FB 33C7 USB_2_FB* 33C7 USB_3 18C2<> 33B8<> USB_3* 18C2<> 33B8<> USB_3_FB 33C7 USB_3_FB* 33C7 USB_4 18C2<> 33A8<> USB_4* 18C2<> 33A8<> USB_4_FB 33A7 USB_4_FB* 33A7 USB_5 18C2<> 33A8<> USB_5* 18C2<> 33A8<> USB_5_FB 33A7 USB_5_FB* 33A7 USB_6 18B2<> 33A4<> USB_6* 18B2<> 33A4<> USB_6_FB 33A3 USB_6_FB* 33A3 USB_7 18B2<> 33A1<> USB_7* 18B2<> 33A1<> USB_7_FB 33A3 USB_7_FB* 33A3 USB_8 18B2<> 33C1<> USB_8* 18B2<> 33C1<> USB_8_FB 33C2
USB_8_FB* 33C2 USB_9 18B2<> 33C4<> USB_9* 18B2<> 33C4<> USB_9_FB 33C3 USB_9_FB* 33C3 USB_10 18B2<> 33B3<> USB_10* 18B2<> 33B3<> USB_10_FB 33B4 USB_10_FB* 33B4 USB_11 18A2<> 33B6<> USB_11* 18A2<> 33B6<> USB_11_FB 33B5 USB_11_FB* 33B5 USB_OC98* 18A2< 33D1> USB_OC1110* 18A2< 33C3> USB_OC3210* 18A2< 33D4> USB_OC7654* 18A2< 33B4> USB_RBIAS_GND 18A3 USB_VCC_7654 33B2< 33B6> V1.1V_NV_SP_PLL 18A6 V1.1V_PEX_AVDD 20C4 V1.1V_PEX_PLL 16B5 V1.1V_PLL_DP_XREF_CO 15B6> 16B6< RE_V V1.1V_PLL_MAC_DUAL 19C5 V1.1V_PLL_MCLK_DLCEL 12B3< 14B2> L_FSB_CPU V1.1V_SATA_AVDD 20B4 V1.1V_SATA_PLL 18A6 V1P1_HDMI_VDD 20C6 V1P8_IFPB_VDD 21A4 V3.3V_PLL_USB 18A3 V3.3V_TVRGB_DAC 21B4 V3P3_HDMI_VDD 21A5 V3P3_PLL_HDMI 15D5 V3P3_RGBDAC_VDD 21B4 VCCA 9A5 VCCIOPLL 9A5 VCC_MB_REG 10C5 VCC_SENSE 10B5 VGAPWR_FB 36C1 VSSA 9A5 VSS_MB_REG 10B5 VSS_SENSE 10B5 VTT_PG_COMP_N 49C3 VTT_PG_COMP_P 49C3 VTT_PG_OUT 49C2 XDP_CLK 11C5< 12D1> XDP_CLK* 11C5< 12D1> XDP_FNTPNL_RST* 9B5> 11C6> 44A6< XDP_TCK 9B6< 11D1> XDP_TDI 9C5< 11D1> XDP_TDO 9B5> 11D1> XDP_TMS 9B5< 11D1> XDP_TRST* 9B6< 11D1> XTALIN 19C5 XTALIN_RTC 19B5 XTALOUT 19C5 XTALOUT_RTC 19B5 YEL_SUSLED_AN 44C2 YLW_STBYLED 39A6> 44B2<
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Title: Cref Part Report Design: mcp79_uatx_sli Date: Mar 19 16:42:31 2008
C1A1 CAP_0805_R [37D3] C1A2 CAP_0402_R [50A6] C1A3 CAPP_RDL_R [37D3] C1A4 CAP_0402_R [37D2] C1B1 CAPP_RDL_R [33C4] C1B2 CAPP_RDL_R [33D2] C1B3 CAP_0603_R [33D3] C1B4 CAP_0603_R [33D3] C1B5 CAP_0603_R [33C5] C1B6 CAP_0603_R [33C5] C1B7 CAP_1206_R [44B8] C1B8 CAP_1206_R [44B8] C1B9 CAP_0603_R [31B1] C1C1 CAPP_RDL_R [31B1] C1C2 CAP_0402_R [40D2] C1C3 CAP_0402_R [40C4] C1C4 CAP_0402_R [40C4] C1C5 CAP_0402_R [40C3] C1C6 CAP_0402_R [40C3] C1C7 CAP_0402_R [40C3] C1C8 CAP_0402_R [40C3] C1C9 CAP_0402_R [40C2] C1C10 CAP_0402_R [40D3] C1C11 CAP_0402_R [40C2] C1C12 CAP_0402_R [40D2] C1C13 CAP_0603_R [31C1] C1C14 CAP_0603_R [31B1] C1C15 CAP_0402_R [31A1] C1C16 CAP_0402_R [45C2] C1D1 CAP_0402_R [50A6] C1D2 CAP_0603_R [31C1] C1E1 CAP_0402_R [43B2] C1E2 CAPP_RDL_R [31B1] C1E3 CAP_0402_R [32D7] C1E4 CAP_0402_R [31C1] C1F1 CAP_0402_R [32A3] C1F2 CAP_0603_R [32C4] C1F3 CAP_0402_R [32A3] C1F4 CAP_0603_R [32C2] C1F5 CAP_0603_R [32D4] C1F6 CAP_0402_R [32B2] C1F7 CAP_0402_R [32B2] C1F8 CAP_0805_R [32A4] C1F9 CAP_0402_R [32A3] C1F10 CAP_0603_R [32D3] C1F11 CAP_0402_R [32A4] C1F12 CAP_0402_R [32B4] C1F13 CAP_0402_R [32B4] C1F14 CAP_0402_R [32A3] C1F15 CAP_0402_R [32A3] C1F16 CAP_0402_R [32A1] C1F17 CAP_0402_R [32A2] C1F18 CAP_0402_R [32A3] C1F19 CAP_0402_R [32B5] C1F20 CAP_0402_R [32A3] C1F21 CAP_0603_R [19B7] C1G1 CAP_0603_R [44B1] C1G2 CAP_0402_R [50A5] C1G3 CAP_0603_R [44A5] C1G4 CAP_0402_R [44B3] C1G5 CAP_0402_R [44B3] C1G6 CAP_0402_R [44B5] C1G7 CAP_0402_R [44A3] C1G8 CAP_0402_R [44B4] C1G9 CAP_0402_R [44B4] C1G10 CAP_0402_R [32A7] C1G11 CAP_0603_R [32B3] C1G12 CAP_0402_R [32A7] C1H1 CAP_0402_R [50B7] C1H2 CAPP_RDL_R [42B6] C1H3 CAP_0603_R [42B5] C1H4 CAP_0402_R [39A8] C1J1 CAP_0603_R [43D3] C1J2 CAP_0603_R [43D2] C1J3 CAP_0402_R [39A8] C1J4 CAP_0402_R [50B4] C2A1 CAP_1206_R [37B7] C2A2 CAP_1206_R [37B7] C2A3 CAP_0402_R [37B7] C2A4 CAPP_RDL_R [37D1] C2A5 CAP_0402_R [37B2] C2A6 CAP_0402_R [37A2] C2A7 CAP_0402_R [37B2] C2A8 CAP_0402_R [37B3] C2A9 CAP_0402_R [50D3] C2A10 CAP_0402_R [37B2] C2A11 CAP_0402_R [37B2] C2B1 CAP_0402_R [30C2] C2B2 CAP_0402_R [28B7] C2B3 CAPP_RDL_R [28B8]
C2B4 CAPP_RDL_R [29C2] C2B5 CAPP_RDL_R [30B2] C2B6 CAP_0402_R [30C1] C2B7 CAP_0402_R [30C2] C2C1 CAP_0402_R [30B1] C2C2 CAP_0402_R [30D6] C2C3 CAP_0402_R [30C6] C2C4 CAP_0402_R [30C6] C2C5 CAP_0402_R [30C6] C2C6 CAP_0402_R [30C6] C2C7 CAP_0402_R [30C6] C2C8 CAP_0402_R [30C6] C2C9 CAP_0402_R [30C6] C2C10 CAPP_RDL_R [29B2] C2C11 CAPP_RDL_R [30B2] C2C12 CAP_0402_R [30B2] C2C13 CAP_0402_R [30B2] C2D1 CAP_0402_R [30C6] C2D2 CAP_0402_R [30C6] C2D3 CAP_0402_R [30B6] C2D4 CAP_0402_R [30B6] C2D5 CAP_0402_R [30B6] C2D6 CAP_0402_R [30B6] C2D7 CAP_0402_R [30B6] C2D8 CAP_0402_R [30B6] C2D9 CAP_0402_R [50C3] C2D10 CAP_0402_R [31C1] C2D11 CAP_0402_R [31C1] C2E1 CAP_0402_R [31B1] C2E2 CAP_0603_R [31A1] C2E3 CAP_0402_R [50C7] C2E4 CAPP_RDL_R [31D1] C2F1 CAP_0603_R [48D7] C2F2 CAP_0805_R [48B3] C2F3 CAP_0402_R [48D6] C2F4 CAP_0402_R [32A2] C2F5 CAP_0805_R [32A4] C2F6 CAP_0402_R [32A4] C2F7 CAP_0402_R [50C7] C2F8 CAP_0402_R [32D7] C2F9 CAP_0402_R [32A1] C2F10 CAP_0402_R [32A4] C2F11 CAP_0402_R [32A2] C2F12 CAP_0402_R [32A3] C2F13 CAP_0402_R [32A1] C2F14 CAP_0603_R [32A2] C2G1 CAPP_RDL_R [48D6] C2G2 CAP_0603_R [48C5] C2G3 CAP_0402_R [48C7] C2G4 CAP_0402_R [48D7] C2G5 CAP_0805_R [48D5] C2H1 CAP_0402_R [39A7] C2H2 CAP_0402_R [39B7] C2H3 CAP_0402_R [39D6] C2H4 CAP_0402_R [39B7] C2H5 CAP_0402_R [39C2] C2H6 CAP_0603_R [48D5] C2H7 CAP_0402_R [39C1] C2J1 CAP_0402_R [45A5] C2J2 CAP_0402_R [45A4] C2J3 CAPP_RDL_R [39A8] C2J4 CAP_0402_R [39A8] C2J5 CAP_0402_R [39A7] C2J6 CAP_0402_R [39A7] C2J7 CAP_0402_R [50C8] C3A1 CAPP_RDL_R [37B7] C3A2 CAP_0402_R [37A7] C3A3 CAP_1206_R [38B3] C3A4 CAP_1206_R [38B3] C3A5 CAP_0402_R [37D4] C3A6 CAP_0805_R [37D6] C3A7 CAP_1206_R [38D3] C3A8 CAP_0402_R [37D7] C3A9 CAP_1206_R [38C3] C3A10 CAP_0402_R [37D6] C3A11 CAP_0805_R [37C3] C3A12 CAP_1206_R [38C3] C3A13 CAP_1206_R [38D3] C3A14 CAP_0603_R [37D7] C3A15 CAP_0402_R [37D4] C3A16 CAP_0805_R [37D4] C3A17 CAP_1206_R [38B7] C3A18 CAP_1206_R [38B7] C3A19 CAP_1206_R [38D7] C3A20 CAP_1206_R [38D7] C3A21 CAPP_RDL_R [38C7] C3A22 CAP_0402_R [38B2] C3A23 CAP_0402_R [38B2] C3A24 CAP_0402_R [38D2] C3A25 CAP_0402_R [38A6] C3B1 CAPP_RDL_R [37B7] C3B2 CAP_0402_R [30C2] C3B3 CAP_0402_R [29C2] C3B4 CAP_0402_R [37D8] C3B5 CAP_0402_R [29C1]
C3B6 CAP_0402_R [29C2] C3B7 CAP_0402_R [29C2] C3B8 CAPP_RDL_R [30C2] C3B9 CAP_0402_R [28B8] C3C1 CAP_0402_R [50C3] C3C2 CAP_0402_R [29B2] C3C3 CAP_0402_R [29B2] C3C4 CAP_0402_R [29D6] C3C5 CAP_0402_R [29C6] C3C6 CAP_0402_R [29C6] C3C7 CAP_0402_R [29C6] C3C8 CAP_0402_R [29C6] C3C9 CAP_0402_R [29C6] C3C10 CAP_0402_R [16F5] C3C11 CAPP_RDL_R [29B2] C3C12 CAPP_RDL_R [31A1] C3D1 CAP_0402_R [29C6] C3D2 CAP_0402_R [29C6] C3D3 CAP_0402_R [29C6] C3D4 CAP_0402_R [29C6] C3D5 CAP_0402_R [29B6] C3D6 CAP_0402_R [29B6] C3D7 CAP_0402_R [29B6] C3D8 CAP_0402_R [29B6] C3D9 CAP_0402_R [29B6] C3D10 CAP_0402_R [29B6] C3E1 CAP_0402_R [50C7] C3F1 CAP_0603_R [48B4] C3F2 CAP_0603_R [44A8] C3F3 CAPP_RDL_R [44A8] C3F4 CAP_0402_R [50C7] C3F5 CAP_1206_R [48C3] C3F6 CAPP_RDL_R [48C4] C3F7 CAPP_RDL_R [48C3] C3G1 CAPP_RDL_R [48D6] C3G2 CAP_0402_R [48C7] C3G3 CAP_1206_R [48C3] C3G4 CAP_1206_R [48C3] C3G5 CAP_0603_R [48C4] C3H1 CAP_0402_R [50C6] C3H2 CAP_0402_R [48D6] C3H3 CAP_0402_R [50C7] C3J1 CAP_0603_R [45A7] C3J2 CAP_0402_R [15B5] C3J3 CAP_0402_R [50C7] C4A1 CAPP_RDL_R [38C7] C4A2 CAP_0402_R [38D2] C4A3 CAP_0402_R [38C5] C4A4 CAP_0402_R [38D6] C4A5 CAP_0402_R [38D5] C4A6 CAP_0402_R [38C5] C4A7 CAP_0402_R [38C2] C4A8 CAP_0402_R [38C2] C4A9 CAP_0402_R [38A6] C4B1 CAP_0402_R [28B8] C4B2 CAP_0402_R [28B7] C4B3 CAP_0402_R [28B7] C4B4 CAP_0402_R [34C3] C4B5 CAP_0402_R [34C7] C4B6 CAP_0402_R [34C7] C4B7 CAP_0402_R [34D4] C4B8 CAP_0402_R [34D3] C4B9 CAP_0402_R [34D4] C4B10 CAP_0402_R [34C4] C4B11 CAP_0402_R [34D3] C4C1 CAP_0402_R [50C3] C4C2 CAP_0402_R [28A8] C4C3 CAP_0402_R [28C6] C4C4 CAP_0402_R [29B1] C4C5 CAP_0402_R [28C6] C4C6 CAP_0402_R [19A4] C4C7 CAPP_RDL_R [28A8] C4C8 CAP_0402_R [50D6] C4C9 CAP_0805_R [34C3] C4C10 CAP_0805_R [34C4] C4D1 CAP_0402_R [19F6] C4D2 CAP_0402_R [19F6] C4D3 CAP_0402_R [19F6] C4D4 CAP_0402_R [19F6] C4E1 CAPP_RDL_R [48C4] C4E2 CAP_0402_R [17A4] C4E3 CAP_0402_R [21B3] C4E4 CAP_0402_R [21B3] C4J1 CAP_0402_R [50D8] C4J2 CAP_0603_R [42D5] C4J3 CAPP_RDL_R [42C6] C4J4 CAPP_RDL_R [44B6] C4K1 CAP_0603_R [44B6] C4K2 CAP_0603_R [44B8] C4K3 CAP_0603_R [44B8] C5A1 CAP_0402_R [50D3] C5B1 CAP_0402_R [34D3] C5B2 CAP_0402_R [34D4] C5B3 CAP_0402_R [50D7] C5B4 CAP_0402_R [50B7]
C5B5 CAP_0402_R [34D2] C5B6 CAP_0402_R [34D4] C5B7 CAP_0402_R [34D2] C5B8 CAP_0402_R [34D3] C5B9 CAP_0402_R [34C4] C5B10 CAP_0402_R [34D4] C5B11 CAP_0402_R [34D2] C5B12 CAP_0402_R [50D7] C5B13 CAP_0402_R [34C2] C5C1 CAP_0402_R [34C4] C5C2 CAP_0402_R [34C4] C5C3 CAP_0402_R [49C5] C5D1 CAP_0402_R [19C7] C5D2 CAP_0402_R [19C7] C5D3 CAP_0402_R [50C8] C5D4 CAP_0402_R [19B6] C5D5 CAP_0402_R [19B6] C5D6 CAP_0402_R [19B5] C5D7 CAP_0603_R [19B5] C5D8 CAP_0402_R [19D7] C5D9 CAP_0603_R [15D3] C5D10 CAP_0402_R [15D3] C5D11 CAP_0402_R [15C6] C5G1 CAP_0402_R [23A7] C5H1 CAP_0402_R [27D6] C5H2 CAP_0402_R [27C8] C5H3 CAP_0402_R [27D8] C5H4 CAP_0402_R [27B6] C5H5 CAP_0402_R [27C6] C5H6 CAP_0402_R [27C8] C5J1 CAPP_RDL_R [44B6] C5J2 CAP_0402_R [50C7] C5J3 CAP_0603_R [44D7] C5J4 CAPP_RDL_R [44A7] C5J5 CAP_0402_R [23A6] C5J6 CAP_0603_R [44B7] C5J7 CAP_0402_R [27C6] C5J8 CAP_0805_R [45C2] C5J9 CAP_0402_R [27B8] C5J10 CAP_0603_R [44C3] C5J11 CAP_0402_R [27B6] C5J12 CAP_0402_R [27C8] C6A1 CAP_0402_R [33A5] C6B1 CAP_0805_R [34C2] C6B2 CAP_0805_R [34A7] C6B3 CAP_0402_R [34A7] C6B4 CAP_0402_R [34A2] C6B5 CAP_0402_R [34A2] C6B6 CAP_0402_R [49C3] C6B7 CAP_0402_R [34A1] C6B8 CAP_0402_R [49D2] C6B9 CAP_0402_R [49D3] C6B10 CAP_0603_R [46B4] C6B11 CAPP_RDL_R [33A5] C6B12 CAP_0402_R [33A5] C6B13 CAP_0603_R [46A4] C6C1 CAPP_RDL_R [49C5] C6C2 CAP_0402_R [49C5] C6C3 CAP_0805_R [34A8] C6C4 CAP_0603_R [49C5] C6C5 CAP_0402_R [49B7] C6C6 CAP_0402_R [49B5] C6C7 CAP_0402_R [49B7] C6C8 CAP_0402_R [49B7] C6C9 CAP_0603_R [49C6] C6D1 CAPP_RDL_R [49B3] C6D2 CAP_0402_R [12D2] C6D3 CAPP_RDL_R [49B3] C6D4 CAP_0603_R [49B4] C6D5 CAPP_RDL_R [9A7] C6D6 CAP_0402_R [49D8] C6D7 CAP_0402_R [49D6] C6D8 CAP_0805_R [9A6] C6E1 CAP_0402_R [12D2] C6G1 CAP_0402_R [23A6] C6G2 CAP_0805_R [23A8] C6H1 CAP_0402_R [27C6] C6H2 CAP_0402_R [27D8] C6H3 CAP_0402_R [27C6] C6H4 CAP_0402_R [27C8] C6H5 CAP_0402_R [27C4] C6H6 CAP_0402_R [27B8] C6H7 CAP_0402_R [27D6] C6H8 CAP_0402_R [27C8] C6H9 CAP_0402_R [27D4] C6J1 CAP_0402_R [27D8] C6J2 CAP_0402_R [27C4] C6J3 CAP_0402_R [27D8] C6J4 CAP_0402_R [27D6] C6J5 CAP_0603_R [44C5] C6J6 CAP_0402_R [23A6] C6J7 CAP_0603_R [44C6] C6J8 CAP_0402_R [27D6] C6J9 CAP_0402_R [27C8] C6J10 CAPP_RDL_R [44B6]
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456 3 2 18 7
C6J11 CAP_0402_R [27B8] C6J12 CAP_0603_R [44B7] C6J13 CAP_0402_R [27D4] C6J14 CAPP_RDL_R [44B7] C6J15 CAP_0402_R [27C8] C6J16 CAP_0402_R [27D4] C6J17 CAP_0603_R [44B8] C6J18 CAP_0402_R [27B8] C7A1 CAP_0402_R [33D5] C7A2 CAP_0402_R [33D5] C7A3 CAPP_RDL_R [33D5] C7B1 CAP_0603_R [46B2] C7B2 CAP_0805_R [46D2] C7B3 CAP_1206_R [46C2] C7C1 CAP_0402_R [49C6] C7C2 CAPP_RDL_R [46E1] C7C3 CAP_0603_R [46C2] C7D1 CAP_0603_R [10B2] C7D2 CAP_0603_R [10B3] C7D3 CAP_0402_R [10B3] C7H1 CAP_0402_R [27C8] C7H2 CAP_0402_R [23A7] C7H3 CAP_0402_R [23A6] C7J1 CAP_0402_R [23A7] C7J2 CAP_0402_R [27D4] C7J3 CAP_0402_R [45C8] C7J4 CAP_0402_R [45D6] C7J5 CAPP_RDL_R [45D4] C7K1 CAP_0603_R [44B7] C7K2 CAP_0603_R [44B7] C7K3 CAP_0603_R [44B6] C7K4 CAP_0603_R [45B5] C7K5 CAPP_RDL_R [45D3] C7K6 CAP_0603_R [45D3] C7K7 CAP_0402_R [45C3] C8A1 CAP_0402_R [36A4] C8A2 CAP_0402_R [36A6] C8A3 CAP_0402_R [36A1] C8A4 CAP_0402_R [50D7] C8A5 CAP_0402_R [37A2] C8A6 CAP_0402_R [37A3] C8A7 CAP_0603_R [36C2] C8A8 CAP_0402_R [36C6] C8A9 CAP_0402_R [36C6] C8A10 CAP_0402_R [36C6] C8A11 CAP_0402_R [36C5] C8A12 CAP_0402_R [36C5] C8A13 CAP_0402_R [36C5] C8A14 CAP_0603_R [36C1] C8B1 CAPP_RDL_R [46F4] C8B2 CAP_0402_R [36A1] C8B3 CAP_0805_R [46C2] C8B4 CAP_1206_R [46E2] C8B5 CAPP_RDL_R [46F3] C8C1 CAPP_RDL_R [46E1] C8C2 CAPP_RDL_R [46E1] C8C3 CAPP_RDL_R [46E1] C8C4 CAP_0603_R [46E2] C8E1 CAP_1206_R [46C1] C8E2 CAP_1206_R [46D1] C8E3 CAP_1206_R [46D1] C8E4 CAP_1206_R [46C1] C8E5 CAP_1206_R [46B1] C8E6 CAP_1206_R [46B1] C8E7 CAP_1206_R [46C1] C8E8 CAP_1206_R [46C1] C8E9 CAP_1206_R [46D1] C8E10 CAP_1206_R [46D1] C8E11 CAP_1206_R [46C1] C8E12 CAP_1206_R [46C1] C8E13 CAP_1206_R [46C1] C8E14 CAP_1206_R [46C1] C8E15 CAP_1206_R [46C1] C8E16 CAP_1206_R [46C1] C8E17 CAP_1206_R [46C1] C8E18 CAP_1206_R [46C1] C8G1 CAP_0402_R [11B6] C8G2 CAP_0402_R [24C1] C8G3 CAP_0402_R [23C1] C8H1 CAP_1206_R [47B1] C8H2 CAP_0402_R [26C1] C8H3 CAP_0402_R [25C1] C8J1 CAPP_RDL_R [45C4] C8J2 CAP_0603_R [45C4] C8J3 CAP_0402_R [50C4] C8J4 CAPP_RDL_R [45A8] C8J5 CAP_0603_R [45C2] C8K1 CAPP_RDL_R [45C3] C8K2 CAP_0402_R [50C7] C8K3 CAP_0402_R [45C3] C8K4 CAPP_RDL_R [45B1] C8K5 CAPP_RDL_R [45C2] C8K6 CAP_0402_R [47D5] C8K7 CAPP_RDL_R [45C3] C9A1 CAP_0603_R [36C2]
C9A2 CAP_0603_R [36C2] C9A3 CAP_0402_R [36C3] C9A4 CAP_0402_R [36C3] C9A5 CAP_0402_R [50D7] C9A6 CAP_0603_R [36C2] C9A7 CAP_0402_R [38A4] C9A8 CAP_0603_R [38A4] C9B1 CAPP_RDL_R [46F3] C9B2 CAP_0402_R [50C4] C9B3 CAP_1206_R [46F3] C9B4 CAP_0805_R [46E2] C9B5 CAP_0402_R [50A5] C9C1 CAPP_RDL_R [46E1] C9C2 CAPP_RDL_R [46E1] C9C3 CAP_0402_R [46F4] C9D1 CAP_1206_R [46C2] C9D2 CAP_0805_R [46C2] C9E1 CAP_0603_R [46D2] C9E2 CAPP_RDL_R [46E1] C9E3 CAPP_RDL_R [46E1] C9G1 CAP_0603_R [46D6] C9G2 CAP_0603_R [46D5] C9G3 CAP_0603_R [46C6] C9G4 CAP_0603_R [46C6] C9G5 CAP_0603_R [46E5] C9G6 CAP_0603_R [46D6] C9G7 CAP_0603_R [46C5] C9G8 CAP_0603_R [46C4] C9G9 CAP_0603_R [46C6] C9G10 CAP_0603_R [46C5] C9G11 CAP_0603_R [46C4] C9G12 CAP_0603_R [46D4] C9G13 CAP_0603_R [46E4] C9G14 CAP_0603_R [46D4] C9G15 CAP_0603_R [46C3] C9G16 CAP_0603_R [46D4] C9G17 CAP_0603_R [46C4] C9G18 CAP_0603_R [46C4] C9G19 CAP_0402_R [46E7] C9G20 CAP_0402_R [46E5] C9G21 CAP_0603_R [46D4] C9G22 CAP_0603_R [46E4] C9G23 CAP_0603_R [46D4] C9G24 CAP_0603_R [46E4] C9G25 CAP_0603_R [46D4] C9H1 CAP_0603_R [47C3] C9H2 CAP_1206_R [47C3] C9H3 CAP_0603_R [47B3] C9H4 CAP_0603_R [47B3] C9H5 CAP_0603_R [47B1] C9H6 CAPP_RDL_R [47B2] C9H7 CAPP_RDL_R [47B1] C9H8 CAP_0603_R [47C2] C9H9 CAPP_RDL_R [47C1] C9H10 CAP_1206_R [47C1] C9H11 CAP_0402_R [50B6] C9J1 CAPP_RDL_R [47D6] C9J2 CAPP_RDL_R [47D6] C9J3 CAP_1206_R [47B1] C9J4 CAP_0603_R [47B6] C9J5 CAP_0603_R [47C7] C9J6 CAP_0402_R [47C7] C9J7 CAP_0402_R [47C7] C9J8 CAP_0805_R [47D5] C9J9 CAP_0402_R [47D6] C9J10 CAP_0603_R [47D7] C9J11 CAP_0402_R [50B3] C9J12 CAPP_RDL_R [47C4] C9K1 CAPP_RDL_R [44A7] C9K2 CAP_0603_R [47D6] C9K3 CAP_0603_R [47C5] C10A1 CAP_0402_R [35A3] C10A2 CAP_0402_R [35A3] C10A3 CAP_0402_R [35A3] C10A4 CAP_0402_R [35A3] C10A5 CAP_0402_R [35B3] C10A6 CAP_0402_R [35B3] C10B1 CAP_0402_R [50B7] C10C1 CAP_1206_R [46D2] C10C2 CAP_1206_R [46F4] C10C3 CAP_0402_R [46F4] C10D1 CAPP_RDL_R [46F3] C10F1 CAP_0402_R [50B7] C10F2 CAP_0603_R [46A7] C10G1 CAP_0603_R [42C2] C10G2 CAP_0402_R [50B8] C10H1 CAP_0402_R [50D4] C10H2 CAPP_RDL_R [47C4] C10H3 CAP_0603_R [42D3] C10H4 CAP_0402_R [50B3] C10J1 CAPP_RDL_R [47C4] C10J2 CAP_1206_R [47C3] C13D1 CAP_0402_R [10A5] C13D2 CAP_0805_R [10A5] C13E1 CAP_0402_R [10A4]
C13E2 CAP_0402_R [10A4] C13E3 CAP_0402_R [10A3] C13E4 CAP_7343_R [46D1] C13E5 CAP_0402_R [9A8] C13E6 CAP_7343_R [46D1] C13F1 CAP_0402_R [9B7] C13F2 CAP_0402_R [9B7] C13F3 CAP_0603_R [9B8] C13F4 CAP_0402_R [10C3] C13F5 CAP_0402_R [10C4] C13F6 CAP_0402_R [10C3] C13F7 CAP_0402_R [9A8] C13F8 CAP_0402_R [9A8] C14D1 CAP_0805_R [20E3] C14D2 CAP_0402_R [20E3] C14D3 CAP_0402_R [20E3] C14D4 CAP_0402_R [20E3] C14F1 CAP_0402_R [9A8] C14F2 CAP_0603_R [9C8] C14F3 CAP_0402_R [9C7] C14F4 CAP_0402_R [9C8] C15F1 CAP_0402_R [12D3] C15F2 CAP_0402_R [12D3] C16B1 CAP_0402_R [34D3] C16B2 CAP_0402_R [34D2] C16D1 CAP_0805_R [20E3] C16E1 CAP_0402_R [20E7] C16E2 CAP_0402_R [20D7] C16E3 CAP_0402_R [21B4] C16E4 CAP_0402_R [21B3] C16E5 CAP_0402_R [20C3] C16E6 CAP_0402_R [20C4] C16E7 CAP_0603_R [20C3] C16E8 CAP_0402_R [20B4] C16E9 CAP_0805_R [20B3] C16E10 CAP_0402_R [20C3] C16E11 CAP_0805_R [20C3] C16E12 CAP_0402_R [20E7] C16E13 CAP_0402_R [20C4] C16E14 CAP_0402_R [18A7] C16E15 CAP_0402_R [20D4] C16E16 CAP_0402_R [20B4] C16E17 CAP_0603_R [18A7] C16E18 CAP_0603_R [21C1] C16E19 CAP_0402_R [18A6] C16E20 CAP_0402_R [16B6] C16E21 CAP_0402_R [20D4] C16E22 CAP_0402_R [18A5] C16E23 CAP_0402_R [21C8] C16E24 CAP_0603_R [20B3] C16E25 CAP_0603_R [16B7] C16E26 CAP_0402_R [21C1] C16E27 CAP_0402_R [20D6] C16E28 CAP_0603_R [18A6] C16E29 CAP_0402_R [21C7] C16E30 CAP_0402_R [21C2] C16E31 CAP_0402_R [20B4] C16E32 CAP_0603_R [21B2] C16E33 CAP_0603_R [21C3] C16E34 CAP_0402_R [20E7] C16E35 CAP_0402_R [21C3] C16E36 CAP_0402_R [20D6] C16E37 CAP_0402_R [21B2] C16E38 CAP_0402_R [21C6] C16E39 CAP_0402_R [20D7] C16E40 CAP_0603_R [20B4] C16E41 CAP_0402_R [21C3] C16E43 CAP_0402_R [21C6] C16E44 CAP_0603_R [19D6] C16E45 CAP_0402_R [19D6] C16E46 CAP_0402_R [20E6] C16E47 CAP_0402_R [20D7] C16E48 CAP_0402_R [20E7] C16E49 CAP_0402_R [20D7] C16E50 CAP_0402_R [21C7] C16E51 CAP_0402_R [21A5] C16E52 CAP_0402_R [21C7] C16E53 CAP_0402_R [20D7] C16E54 CAP_0603_R [21A6] C16E55 CAP_0402_R [20D7] C16E56 CAP_0402_R [20D3] C16E57 CAP_0603_R [15C6] C16E58 CAP_0402_R [20E7] C16E59 CAP_0402_R [21C8] C16E60 CAP_0402_R [20D3] C16E61 CAP_0603_R [14A1] C16E62 CAP_0402_R [21C7] C16E63 CAP_0402_R [18A2] C16E64 CAP_0402_R [14A2] C16E65 CAP_0402_R [15C6] C16E66 CAP_0603_R [18A1] C16E67 CAP_0402_R [21C7] C16E68 CAP_0402_R [20E3] C16E69 CAP_0603_R [15C6] C16E70 CAP_0402_R [21B3]
C16E71 CAP_0402_R [20E3] C16E72 CAP_0603_R [21C6] C16E73 CAP_0402_R [15D3] C16E74 CAP_0402_R [21A3] C16E75 CAP_0603_R [21A3] C16E76 CAP_0402_R [21A3] C16E77 CAP_0603_R [20E3] C17E1 CAP_0402_R [19D2] C17E2 CAP_0402_R [17C2] C17E3 CAP_0402_R [17C3] C17E4 CAP_0603_R [20E7] C17E5 CAP_0402_R [17C3] C17E6 CAP_0805_R [20E7] C17E7 CAP_0603_R [20D3] C17E8 CAP_0603_R [21B3] C17E9 CAP_0603_R [20E7] C17E10 CAP_0402_R [20D7] C17E11 CAP_0402_R [20D7] C17E12 CAP_0402_R [20D7] C17E13 CAP_0402_R [20D7] C18J1 CAP_0402_R [18B7] C18J2 CAP_0402_R [18B7] C18J3 CAP_0402_R [18B7] C18J4 CAP_0402_R [18B7] C18J5 CAP_0402_R [18A7] C18J6 CAP_0402_R [18A7] C18J7 CAP_0402_R [18A7] C18J8 CAP_0402_R [18A7] C19J1 CAP_0402_R [18C6] C19J2 CAP_0402_R [18C7] C19J3 CAP_0402_R [18D6] C19J4 CAP_0402_R [18D7] C19J5 CAP_0402_R [18D6] C19J6 CAP_0402_R [18D7] C19J7 CAP_0402_R [18D6] C19J8 CAP_0402_R [18D7] C20J1 CAP_0402_R [18C7] C20J2 CAP_0402_R [18C7] C20J3 CAP_0402_R [18B7] C20J4 CAP_0402_R [18B7] C20J5 CAP_0402_R [18B7] C20J6 CAP_0402_R [18B7] C20J7 CAP_0402_R [18C7] C20J8 CAP_0402_R [18C7] CR1A1 DIODE_S23_R [37D4] CR1F1 DIODE_SMC_R [32C2] CR1H1 DIODE_SOD123_R [41C5] CR1J1 DIODECC_S23_R [43D3] CR2A1 DIODECA_S23_R [37B7] CR2A2 DIODECA_S23_R [37A7] CR2A3 DIODE_SOD123_R [37D1] CR2H1 DIODE_S23_R [39B8] CR6B1 DIODE_S23_R [49D3] CR7J1 VOLTAGEREF_SOT-23_R [45C8] CR8A1 DIODESER_S23_R [36A7] CR8B1 DIODESER_S23 [36C7] CR8B2 DIODESER_S23 [36C7] CR8B3 DIODESER_S23 [36C7] CR9A1 DIODESER_S23 [36C4] CR9A2 DIODESER_S23 [36C3] CR9B1 DIODESER_S23 [36C3] CR9B2 DIODESER_S23 [36C4] CR9B3 DIODESER_S23_R [35A4] CR10A1 DIODESER_S23_R [35A5] CR10B1 DIODESER_S23_R [35A5] CR10B2 DIODESER_S23_R [35A4] CR10H1 DIODE_S23_R [42C2] CR10H2 LED_0603_R [44C2] CR10H3 LED_0603_R [47A2] CR10H4 LED_0603_R [44C1] HS5E1 HEATSINK_MCP7A_PASSIVE_HE [16F2] ATSINK ISO2H1 GNDISO_25MIL [39A7] ISO2H2 GNDISO_25MIL [39A7] ISO6B1 GNDISO_25MIL [46B3] ISO7B1 GNDISO_25MIL [46C3] ISO7C1 GNDISO_25MIL [46B2] ISO7C2 GNDISO_25MIL [46B2] ISO8B1 GNDISO_25MIL [46E3] ISO8C1 GNDISO_25MIL [46C2] ISO8C2 GNDISO_25MIL [46C2] ISO9C1 GNDISO_25MIL [46E2] ISO9C2 GNDISO_25MIL [46E2] ISO9F1 GNDISO_25MIL [46D3] ISO10E1 GNDISO_25MIL [46D2] ISO10E2 GNDISO_25MIL [46D2] J1B1 HDR2X5KEY9_THR_R [33C3] J1B2 HDR2X5KEY9_THR_R [33B5] J1B3 HDR2X5_SMT_R [22B5] J1B4 PCI124_CONN_R [31B5] J1C1 HDR2X5KEY10_THR_R [40C1] J1D1 AZALIADIGITAL_HEADER_THR_ [37A5] R J1E1 HDR1X4_THR_R [43B1] J1F1 1394_HEADER_THR_R [32B1]
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456 3 2 18 7
J1G1 HDR1X2_THR_R [19B7] J1G2 HDR2X5KEY10_THR_R [44B4] J1G3 HDR1X3_THR_R [19B7] J1H1 HDR2X5KEY6_THR_R [35D2] J1H2 FAN1X3_THR_R [42B5] J1J1 HDR2X13_THR_R [41A6] J1K1 BATTHLDR_V_3PCOIN_R [43C4] J1K2 SATA_DUAL_RA_SMD_SMD_R [18C8 18B8] J2A1 HDR2X3KEY2_THR_R [37B1] J2B1 PCI_EXPRESS_X16_CONN_R [30B5] J2B2 HDR2X5KEY8_THR_R [37B6] J2H1 HDR1X3_THR_R [40B3] J2K1 SATA_DUAL_RA_SMD_SMD_R [18D8 18D8] J3B1 PCI_EXPRESS_X16_CONN_R [29B5] J3K1 SATA_DUAL_RA_SMD_SMD_R [18A8 18B8] J4B1 PCI_EXPRESS_X1_CONN_R [28C5] J4J1 FAN1X3_THR_R [42D5] J5A1 AUDIO_JACK_6PORT_THR_R [38C1 38D1 38B1 38B5 38C5 38D5] J5A2 HDR2X5KEY9_THR_R [33A3] J5K1 ATX_PWR_24PIN_ATX_1MTG_R [44D6] J6A1 USBX2_RJ45_GIG_E_RES_THR_ [33A6] R J6A1 USBX2_RJ45_GIG_E_RES_THR_ [34C2] R J7A1 USBX4_THR_R [33C6] J7A2 CON_HDMI_A_SMT_R [36A2] J8A1 RCA_JACK_HORIZ_OPEN_R [37A1] J8A2 VGACONN_DB15E_R [36C1] J8G1 DIMM240_SOCKET_R [23B4] J8H1 DIMM240_SOCKET_R [24B4] J8H2 DIMM240_SOCKET_R [25B4] J8J1 DIMM240_SOCKET_R [26B4] J9A1 SPDIF_TX_3PIN_DOOR_R [38A4] J10A1 PS2_CONN_R [35B2] J10B1 ATX_12V_PWR_ATX_4P_CONN_R [46F5] _R J10G1 FAN1X4_4PIN_FAN_R [42C1] J10H1 FAN1X3_THR_R [42D3] J13F1 HDR2X30_XDP_SMT_R [11D4] L1A1 INDUCTOR_0603_R [37D3] L1A2 CHOKE_2012_R [33C2 33C2] L1A3 CHOKE_2012_R [33C3 33C3] L1B1 CHOKE_2012_R [33B4 33B4] L1B2 CHOKE_2012_R [33B5 33B5] L1F1 INDUCTOR_0805_R [32D5] L1F2 INDUCTOR_0603_R [32C2] L1F3 INDUCTOR_0805_R [32C5] L1F4 INDUCTOR_0805_R [32B4] L2A1 INDUCTOR_0603_R [37A8] L2A2 INDUCTOR_0402_R [37B2] L2H1 INDUCTOR_0603_R [39D5] L2H2 INDUCTOR_0603_R [39A4] L3A1 INDUCTOR_0603_R [38B2] L3A2 INDUCTOR_0603_R [38B2] L3A3 INDUCTOR_0603_R [38D2] L3A4 INDUCTOR_0603_R [38B7] L3G1 INDUCTOR_TH_R [48C4] L3H1 INDUCTOR_TH_R [48D6] L4A1 INDUCTOR_0603_R [38C6] L4A2 INDUCTOR_0603_R [38D6] L4A3 INDUCTOR_0603_R [38D6] L4A4 INDUCTOR_0603_R [38C6] L4A5 INDUCTOR_0603_R [38D2] L4A6 INDUCTOR_0603_R [38C2] L4A7 INDUCTOR_0603_R [38C2] L4A8 INDUCTOR_0603_R [38B7] L4C1 INDUCTOR_0603_R [34C3] L5A1 CHOKE_2012_R [33A2 33A2] L5A2 CHOKE_2012_R [33A3 33A3] L6A1 CHOKE_2012_R [33B7 33B7] L6B1 CHOKE_2012_R [33A7 33A7] L6B2 CHOKE_2012_R [33A7 33A7] L6B3 CHOKE_2012_R [33C7 33C7] L6C1 INDUCTOR_TH_R [49C5] L6C2 INDUCTOR_TH_R [49B4] L6D1 INDUCTOR_0805_R [9B7] L7A1 INDUCTOR_0603_R [36A7] L7A2 CHOKE_2012_R [36B6 36B6] L7A3 CHOKE_2012_R [36B3 36B3] L7B1 CHOKE_2012_R [33C7 33C7] L7B2 CHOKE_2012_R [33D7 33D7] L7C1 INDUCTOR_TH_R [46B2] L7D1 INDUCTOR_0805_R [9B6] L8A1 INDUCTOR_0603_R [36A6] L8A2 INDUCTOR_0603_R [36A6] L8A3 INDUCTOR_0805_R [36A4] L8A4 INDUCTOR_0603_R [36A6] L8A5 INDUCTOR_0603_R [36C6] L8A6 INDUCTOR_0603_R [36C6] L8A7 INDUCTOR_0603_R [36C5] L8B1 INDUCTOR_0805_R [36C1] L8C1 INDUCTOR_TH_R [46C2] L8J1 INDUCTOR_TH_R [47D5] L9A1 INDUCTOR_0603_R [36D4]
L9A2 INDUCTOR_0603_R [36D4] L9A3 INDUCTOR_0603_R [38A4] L9C1 INDUCTOR_TH_R [46E2] L10A1 INDUCTOR_0805_R [35B3] L10C1 INDUCTOR_TH_R [46F4] L10E1 INDUCTOR_TH_R [46D2] L10J1 INDUCTOR_TH_R [47C4] L14A1 CHOKE_2012_R [36B4 36B4] L14A2 CHOKE_2012_R [36B5 36B5] L16E1 INDUCTOR_0603_R [18A7] L16E2 INDUCTOR_0603_R [20C3] L16E3 INDUCTOR_0603_R [20B3] L16E4 INDUCTOR_0603_R [16B7] L16E5 INDUCTOR_0603_R [18A6] L16E6 INDUCTOR_0603_R [19D6] L16E7 INDUCTOR_0603_R [15C7] L16E8 INDUCTOR_0603_R [14B1] L16E9 INDUCTOR_0603_R [18B1] L16E10 INDUCTOR_0603_R [21B2] LP10A1 FBPAK_1206_R [35B4 35A4 35B4 35A4] M1G1 BRD_MOUNT_BRDMNT [43B5] M2A1 BRD_MOUNT_BRDMNT [43C7] M4A1 BRD_MOUNT_BRDMNT [43D6] M4G1 BRD_MOUNT_BRDMNT [43C7] M4K1 BRD_MOUNT_BRDMNT [43C5] M10B1 BRD_MOUNT_BRDMNT [43B7] M10G1 BRD_MOUNT_BRDMNT [43B7] M10K1 BRD_MOUNT_BRDMNT [43C7] Q1B1 MOSFETNSO8_SO8_R [45C2] Q1E1 NPN_S23_R [43B2] Q1H1 MOSFETPSOT23_S23_R [42B6] Q1H2 MOSFETNSOT23_S23_R [42A7] Q1H3 MOSFETNSOT23_S23_R [42A6] Q1J1 MOSFETPSOT23_S23_R [43D4] Q2G1 MOSFETNDPACK_DPAK_R [48C5] Q2G2 MOSFETNDPACK_DPAK_R [48C5] Q2J1 MOSFETNSOT23_S23_R [45A6] Q3J1 NPN_S23_R [45A6] Q4J1 MOSFETNSOT23_S23_R [42C6] Q4J2 MOSFETPSOT23_S23_R [42D6] Q5D1 MOSFETNSOT23_S23_R [21A6] Q5D2 MOSFETPSOT23_S23_R [21A6] Q5J1 MOSFETNSOT23_S23_R [44D7] Q5J2 NPN_S23_R [44C3] Q5J3 MOSFETNSOT23_S23_R [44D3] Q6B1 MOSFETNSOT23_S23_R [49C2] Q6C1 MOSFETNSO8_SO8_R [49B4] Q6C2 MOSFETNSOT23_S23_R [49C7] Q6C3 MOSFETNSOT23_S23_R [49C7] Q6C4 NPN_S23_R [49A7] Q6C5 MOSFETNSO8_SO8_R [49B5] Q6J1 MOSFETNSOT23_S23_R [44C3] Q7A1 MOSFETNSOT23_S23_R [36A7] Q7B1 MOSFETNDPACK_DPAK_R [46B3] Q7B2 MOSFETNDPACK_DPAK_R [46B3] Q7C1 MOSFETNDPACK_DPAK_R [46B2] Q7C2 MOSFETNDPACK_DPAK_R [46C2] Q7J1 MOSFETNSOT23_S23_R [45B3] Q7J2 NPNDPAK_DPAK_R [45C5] Q7K1 MOSFETNSOT23_S23_R [45B6] Q7K2 MOSFETNSOT23_S23_R [45B3] Q7K3 MOSFETNSOT23_S23_R [45B5] Q7K4 MOSFETNSOT23_S23_R [45C5] Q7K5 MOSFETNDPACK_DPAK_R [45D4] Q8A1 MOSFETNSOT23_S23_R [36A5] Q8B1 MOSFETNDPACK_DPAK_R [46C2] Q8B2 MOSFETNDPACK_DPAK_R [46C3] Q8C1 MOSFETNDPACK_DPAK_R [46C3] Q8C2 MOSFETNDPACK_DPAK_R [46C2] Q8G1 MOSFETNSOT23_S23_R [46B7] Q8G2 MOSFETNSOT23_S23_R [46B7] Q8K1 MOSFETPTSOP6_TSOP-6_R [45B2] Q8K2 MOSFETNSO8_SO8_R [45C2] Q9B1 MOSFETNDPACK_DPAK_R [46E2] Q9B2 MOSFETNDPACK_DPAK_R [46E3] Q9C1 MOSFETNDPACK_DPAK_R [46E3] Q9C2 MOSFETNDPACK_DPAK_R [46E2] Q9E1 MOSFETNDPACK_DPAK_R [46D3] Q9G1 MOSFETNSOT23_S23_R [10C2] Q9J1 NPN_S23_R [47D7] Q9J2 MOSFETNSOT23_S23_R [47D8] Q9K1 MOSFETNDPACK_DPAK_R [47C5] Q9K2 MOSFETNDPACK_DPAK_R [47C5] Q10D1 MOSFETNDPACK_DPAK_R [46D3] Q10D2 MOSFETNDPACK_DPAK_R [46D2] Q10E1 MOSFETNDPACK_DPAK_R [46D2] Q10F1 NPN_S23_R [46A6] Q10F2 NPN_S23_R [46A6] Q10H1 MOSFETNSOT23_S23_R [47A2] Q17C1 MOSFETNSOT23_S23_R [19A4] Q17C2 MOSFETNSOT23_S23_R [19A3] R1A1 RES_0805_R [37D3] R1A2 RES_0402_R [33C2] R1A3 RES_0402_R [33C2]
R1A4 RES_0402_R [33C3] R1A5 RES_0402_R [33C3] R1A6 RES_0402_R [37D2] R1A7 RES_0402_R [37D2] R1B1 RES_0402_R [33D2] R1B2 RES_0402_R [33B4] R1B3 RES_0402_R [33B4] R1B4 RES_0402_R [33B5] R1B5 RES_0402_R [33B5] R1B6 RES_0402_R [22B5] R1B7 RES_0603_R [22B5] R1B8 RES_0402_R [33D2] R1B9 RES_0402_R [33C4] R1B10 RES_0402_R [33C4] R1B11 RES_0603_R [22B4] R1B12 RES_0603_R [22B6] R1B13 RES_0603_R [22B5] R1C1 RES_0603_R [22B5] R1D1 RES_0402_R [37A6] R1E1 RES_0402_R [43B3] R1E2 RES_0402_R [43B3] R1E3 RES_0402_R [31A2] R1E4 RES_0402_R [31A2] R1F1 RES_0402_R [32C5] R1F2 RES_0402_R [32B2] R1F3 RES_0402_R [32B2] R1F4 RES_0402_R [32C2] R1F5 RES_0402_R [32C2] R1F6 RES_0402_R [32B2] R1F7 RES_0402_R [32C4] R1F8 RES_0402_R [32B5] R1F9 RES_0402_R [32A5] R1F10 RES_0402_R [32D8] R1F11 RES_0402_R [32B5] R1F12 RES_0402_R [32D8] R1F13 RES_0402_R [32B8] R1F14 RES_0402_R [32A4] R1G1 RES_0402_R [44B2] R1G2 RES_0402_R [44B1] R1G3 RES_0402_R [44A2] R1G4 RES_0402_R [44B3] R1G5 RES_0402_R [44B3] R1G6 RES_0402_R [44B3] R1G7 RES_0402_R [44A5] R1G8 RES_0402_R [44B2] R1G9 RES_0402_R [44A2] R1G10 RES_0402_R [44B3] R1G11 RES_0402_R [44B3] R1G12 RES_0603_R [19B7] R1G13 RES_0603_R [19B7] R1G14 RES_0603_R [44B4] R1G15 RES_0402_R [44B4] R1G16 RES_0402_R [32B8] R1H1 RES_0603_R [41C6] R1H2 RES_1206_R [42B5] R1H3 RES_0402_R [42B6] R1H4 RES_0402_R [42A5] R1H5 RES_0402_R [42A5] R1H6 RES_0402_R [42A5] R1H7 RES_0402_R [42B6] R1H8 RES_0402_R [42A5] R1H9 RES_0402_R [42A5] R1J1 RES_0402_R [43D3] R1J2 RES_0402_R [43C4] R1J3 RES_0402_R [40B4] R1J4 RES_0402_R [40A4] R2A1 RES_0402_R [37B5] R2A2 RES_0402_R [37B5] R2A3 RES_0402_R [37B3] R2A4 RES_0402_R [37B5] R2A5 RES_0402_R [37B7] R2A6 RES_0402_R [37B6] R2A7 RES_0402_R [37B6] R2A8 RES_0402_R [37A6] R2A9 RES_0402_R [37A6] R2A10 RES_0402_R [37B7] R2A11 RES_0402_R [37B2] R2A12 RES_0402_R [37A2] R2A13 RES_0402_R [37B2] R2A14 RES_0402_R [37B2] R2A15 RES_0402_R [37B2] R2B1 RES_0402_R [30D3] R2C1 RES_0402_R [30D3] R2C2 RES_0402_R [30D3] R2C3 RES_0402_R [31D2] R2C4 RES_0402_R [30D6] R2C5 RES_0402_R [31A2] R2F1 RES_0402_R [48A2] R2F2 RES_0402_R [48A2] R2F3 RES_0402_R [48A3] R2F4 RES_0402_R [48A3] R2F5 RES_0402_R [48B3] R2F6 RES_0402_R [32D7] R2F7 RES_0402_R [32A7] R2G1 RES_0402_R [48B5]
R2G2 RES_0402_R [48C5] R2G3 RES_0402_R [48B5] R2G4 RES_0402_R [48B5] R2G5 RES_0402_R [48B5] R2G6 RES_0402_R [48B6] R2G7 RES_0402_R [48D8] R2G8 RES_0402_R [32C8] R2H1 RES_0402_R [39B7] R2H2 RES_0402_R [39B7] R2H3 RES_0402_R [39D8] R2H4 RES_0402_R [39C8] R2H5 RES_0402_R [39C6] R2H6 RES_0402_R [39C8] R2H7 RES_0402_R [39B7] R2H8 RES_0402_R [39D8] R2H9 RES_0402_R [39C8] R2H10 RES_0402_R [39C7] R2H11 RES_0402_R [39C7] R2H12 RES_0402_R [42A7] R2H13 RES_0402_R [42B7] R2H14 RES_0402_R [42A7] R2H15 RES_0402_R [40B2] R2H16 RES_0402_R [40B4] R2H17 RES_0402_R [40A4] R2H18 RES_0402_R [40B4] R2H19 RES_0402_R [40A4] R2H20 RES_0402_R [39C2] R2H21 RES_0402_R [39C2] R2H22 RES_0402_R [39A7] R2H23 RES_0402_R [39A7] R2H24 RES_0402_R [39A7] R2H25 RES_0402_R [39A7] R2H26 RES_0402_R [44A5] R2J1 RES_0402_R [39C6] R2J2 RES_0402_R [39A5] R2J3 RES_0402_R [15B5] R2J4 RES_0402_R [39B2] R2J5 RES_0402_R [19E1] R2J6 RES_0402_R [45A5] R2J7 RES_0402_R [45A5] R2J8 RES_0402_R [15B5] R2J9 RES_0402_R [45A4] R2J10 RES_0402_R [45A5] R2J11 RES_0402_R [45A6] R2J12 RES_0402_R [45A6] R2J13 RES_0402_R [39B1] R2J14 RES_0402_R [39B1] R2J15 RES_0402_R [39B1] R2J16 RES_0402_R [39B1] R3A1 RES_0402_R [37B6] R3A2 RES_0402_R [37A6] R3A3 RES_0603_R [37C3] R3A4 RES_0402_R [37C3] R3A5 RES_0402_R [37C3] R3A6 RES_0402_R [19F7] R3A7 RES_0402_R [37C3] R3A8 RES_0402_R [37C3] R3A9 RES_0603_R [38B7] R3A10 RES_0402_R [38C7] R3A11 RES_0402_R [38C6] R3B1 RES_0402_R [19F7] R3B2 RES_0402_R [37D7] R3B3 RES_0402_R [29D3] R3B4 RES_0402_R [37D7] R3B5 RES_0402_R [37D8] R3B6 RES_0402_R [29D3] R3C1 RES_0402_R [29D3] R3C2 RES_0402_R [29D6] R3C3 RES_0402_R [16E5] R3C4 RES_0402_R [16B7] R3E1 RES_0402_R [17D2] R3F1 RES_0402_R [48C6] R3G1 RES_0805_R [48C4] R3J1 RES_0603_R [45A7] R4A1 RES_0402_R [38C7] R4A2 RES_0402_R [38C6] R4A3 RES_0603_R [38A7] R4A4 RES_0402_R [37D7] R4A5 RES_0402_R [37C7] R4A6 RES_0402_R [37C7] R4B1 RES_0402_R [28C6] R4B2 RES_0402_R [28C3] R4B3 RES_0402_R [28D3] R4B4 RES_0402_R [34C7] R4B5 RES_0402_R [34C8] R4B6 RES_0402_R [34C7] R4B7 RES_0402_R [34B4] R4B8 RES_0402_R [34C8] R4C1 RES_0402_R [28D3] R4C2 RES_0402_R [19B4] R4C3 RES_0402_R [19B4] R4C4 RES_0402_R [19A4] R4C5 RES_0402_R [19B3] R4C6 RES_0402_R [19A3] R4C7 RES_0402_R [19B5]
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456 3 2 18 7
R4C8 RES_0402_R [19A5] R4C9 RES_0603_R [19C8] R4C10 RES_0402_R [19C6] R4C11 RES_0402_R [19C6] R4C12 RES_0603_R [19C7] R4C13 RES_0402_R [16B7] R4C14 RES_0402_R [19E1] R4D1 RES_0402_R [16C6] R4D2 RES_0402_R [19E7] R4D3 RES_0402_R [16C6] R4D4 RES_0402_R [19F6] R4D5 RES_0402_R [19F7] R4D6 RES_0402_R [19F6] R4D7 RES_0402_R [19F6] R4D8 RES_0603_R [16C6] R4E1 RES_0402_R [17B7] R4E2 RES_0402_R [31D2] R4E3 RES_0402_R [17A3] R4E4 RES_0402_R [17A3] R4E5 RES_0402_R [17B7] R4E6 RES_0402_R [17B7] R4E7 RES_0402_R [17D2] R4E8 RES_0402_R [17B2] R4E9 RES_0402_R [17B4] R4E10 RES_0402_R [17B3] R4E11 RES_0402_R [18A6] R4E12 RES_0402_R [17D2] R4E13 RES_0402_R [17B3] R4E14 RES_0402_R [17B3] R4E15 RES_0402_R [17B2] R4E16 RES_0402_R [17A3] R4E17 RES_0402_R [17B3] R4E18 RES_0402_R [17B3] R4E19 RES_0402_R [17A7] R4J1 RES_0402_R [42C7] R4J2 RES_0402_R [42D6] R4J3 RES_0402_R [42D6] R4J4 RES_1206_R [42D5] R4J5 RES_0402_R [42C5] R4J6 RES_0402_R [42C5] R4J7 RES_0402_R [42C5] R5A1 RES_0402_R [37C7] R5A2 RES_0402_R [33A2] R5A3 RES_0402_R [33A2] R5A4 RES_0402_R [33A3] R5A5 RES_0402_R [33A3] R5A6 RES_0402_R [33B5] R5A7 RES_0402_R [33A5] R5B1 RES_0402_R [34A4] R5B2 RES_0402_R [34A5] R5B3 RES_0402_R [34A5] R5B4 RES_0402_R [34A3] R5B5 RES_0402_R [19D5] R5B6 RES_0402_R [34B7] R5B7 RES_0402_R [34C6] R5B8 RES_0402_R [34B7] R5C1 RES_0603_R [19C7] R5C2 RES_0402_R [19C6] R5C3 RES_0402_R [34C6] R5C4 RES_0603_R [19C7] R5C5 RES_0402_R [19C6] R5C6 RES_0402_R [34B7] R5C7 RES_0402_R [34B7] R5C8 RES_0402_R [34A4] R5C9 RES_0402_R [34A5] R5D1 RES_0402_R [19E2] R5D2 RES_0402_R [19F2] R5D3 RES_0402_R [19E6] R5D4 RES_0402_R [19C3] R5D5 RES_0402_R [19E6] R5D6 RES_0402_R [19E5] R5D7 RES_0402_R [19E6] R5D8 RES_0402_R [19E5] R5D9 RES_0402_R [19E5] R5D10 RES_0402_R [19E6] R5D11 RES_0402_R [19D6] R5D12 RES_0402_R [19D6] R5D13 RES_0402_R [21A6] R5D14 RES_0603_R [18A2] R5D15 RES_0402_R [19C6] R5D16 RES_0402_R [19D7] R5D17 RES_0402_R [19D7] R5D18 RES_0402_R [15C3] R5D19 RES_0603_R [15C2] R5D20 RES_0603_R [15C2] R5D21 RES_0402_R [15C6] R5D22 RES_0402_R [15C6] R5J1 RES_0402_R [44D7] R5J2 RES_0402_R [44D7] R5J3 RES_0603_R [44C4] R5J4 RES_0603_R [44D2] R6A1 RES_0402_R [33B7] R6A2 RES_0402_R [33B7] R6B1 RES_0402_R [34A7] R6B2 RES_0402_R [34A7]
R6B3 RES_0603_R [34C2] R6B4 RES_0402_R [33A7] R6B5 RES_0402_R [33A7] R6B6 RES_0402_R [33B7] R6B7 RES_0402_R [33A7] R6B8 RES_0402_R [49C3] R6B11 RES_0402_R [49C2] R6B12 RES_0603_R [46B4] R6B13 RES_0402_R [49C2] R6B14 RES_0402_R [49C3] R6B15 RES_0402_R [49D2] R6B16 RES_0805_R [46B4] R6B17 RES_0402_R [33C7] R6B18 RES_0402_R [33C7] R6C1 RES_0402_R [49C7] R6C2 RES_0402_R [49A5] R6C3 RES_0402_R [49B5] R6C4 RES_0402_R [49A5] R6C5 RES_0402_R [49A6] R6C6 RES_0402_R [49A5] R6C7 RES_0402_R [49A7] R6C8 RES_0402_R [49D2] R6C9 RES_0402_R [49A7] R6C10 RES_0402_R [49B7] R6C11 RES_0402_R [49A7] R6C12 RES_0805_R [49B4] R6D1 RES_0402_R [15C6] R6D2 RES_0402_R [15C6] R6D3 RES_0402_R [12C3] R6D4 RES_0402_R [12C3] R6D5 RES_0402_R [12C2] R6D6 RES_0402_R [49D7] R6D7 RES_0402_R [49C7] R6F1 RES_0402_R [12B6] R6F2 RES_0402_R [12B6] R6F3 RES_0402_R [12B4] R6F4 RES_0402_R [12B4] R6F5 RES_0603_R [13A3] R6F6 RES_0603_R [13A3] R6H1 RES_0402_R [27A2] R6J1 RES_0603_R [44D3] R6J2 RES_0603_R [44C4] R6J3 RES_0402_R [44C3] R6J4 RES_0603_R [44D3] R6J5 RES_0603_R [44D5] R6J6 RES_0603_R [19C1] R7A1 RES_0402_R [36A7] R7A2 RES_0402_R [36A7] R7A3 RES_0603_R [36A6] R7A4 RES_0402_R [36B6] R7A5 RES_0402_R [36B6] R7A6 RES_0402_R [36B3] R7A7 RES_0402_R [36B3] R7B1 RES_0402_R [33D7] R7B2 RES_0402_R [33C7] R7B3 RES_0402_R [33D7] R7B4 RES_0402_R [33D7] R7B5 RES_0805_R [46B2] R7B6 RES_0402_R [33D5] R7B7 RES_0402_R [33D5] R7B8 RES_0805_R [46B3] R7B9 RES_0603_R [46C3] R7B10 RES_0402_R [36A5] R7B11 RES_0402_R [36A4] R7C1 RES_0402_R [49B5] R7D1 RES_0402_R [10B1] R7D2 RES_0402_R [10B2] R7D3 RES_0402_R [10B2] R7D4 RES_0402_R [10B2] R7J1 RES_0402_R [27A6] R7J2 RES_0402_R [45B3] R7J3 RES_0402_R [45C8] R7J4 RES_0402_R [45C6] R7K1 RES_0402_R [45B3] R7K2 RES_0402_R [45B6] R7K3 RES_0603_R [45B5] R7K4 RES_0402_R [45C5] R7K5 RES_0603_R [45D4] R7K6 RES_0402_R [45C5] R7K7 RES_0402_R [45C5] R8A1 RES_0402_R [36A6] R8A2 RES_0603_R [36A6] R8A3 RES_0402_R [36A6] R8A4 RES_0402_R [36A7] R8A5 RES_0402_R [36A6] R8A6 RES_0402_R [37A2] R8A7 RES_0402_R [37A2] R8A8 RES_0603_R [36D7] R8A9 RES_0603_R [36D7] R8A10 RES_0603_R [36D7] R8B1 RES_0805_R [46D3] R8B2 RES_0603_R [46D3] R8C1 RES_0805_R [46C2] R8C2 RES_0805_R [46E2] R8F1 RES_0402_R [9A6]
R8F2 RES_0402_R [9D6] R8F3 RES_0402_R [9D5] R8F4 RES_0402_R [9B5] R8F5 RES_0402_R [10B2] R8G1 RES_0402_R [11A4] R8G2 RES_0402_R [11A3] R8G3 RES_0402_R [11A4] R8G4 RES_0402_R [11A4] R8G5 RES_0603_R [46B7] R8G6 RES_0402_R [46B7] R8G7 RES_0402_R [46B7] R8G8 RES_0402_R [23C2] R8G9 RES_0402_R [23C2] R8G10 RES_0805_R [46E4] R8H1 RES_0402_R [25C2] R9A1 RES_0402_R [36C3] R9A2 RES_0603_R [36D2] R9A3 RES_0603_R [36D2] R9A4 RES_0402_R [36C3] R9B1 RES_0402_R [36D4] R9B2 RES_0603_R [36D5] R9B3 RES_0805_R [46E3] R9B4 RES_0603_R [46E3] R9B5 RES_0402_R [36D5] R9B6 RES_0603_R [36D5] R9D1 RES_0805_R [46D3] R9D2 RES_0603_R [46E3] R9E1 RES_0805_R [46D2] R9F1 RES_0402_R [11B5] R9F2 RES_0402_R [11C1] R9G1 RES_0402_R [11C5] R9G2 RES_0603_R [46D6] R9G3 RES_0402_R [46C7] R9G4 RES_0402_R [46C7] R9G5 RES_0402_R [46D6] R9G6 RES_0603_R [46C5] R9G7 RES_0603_R [46D6] R9G8 RES_0603_R [46D5] R9G9 RES_0603_R [46C6] R9G10 RES_0603_R [46C6] R9G11 RES_0402_R [46D6] R9G12 RES_0603_R [46D6] R9G13 RES_0402_R [46C6] R9G14 RES_0402_R [10C2] R9G15 RES_0603_R [46C5] R9G16 RES_0402_R [46D6] R9G17 RES_0603_R [46C4] R9G18 RES_0603_R [46C4] R9G19 RES_0603_R [46D4] R9G20 RES_0805_R [46E4] R9G21 RES_0603_R [46D4] R9G22 RES_0603_R [46C4] R9G23 RES_0603_R [46D4] R9G24 RES_0603_R [46C4] R9G25 RES_0603_R [46C4] R9G26 RES_0402_R [46E7] R9G27 RES_0603_R [46C4] R9G28 RES_0603_R [46D4] R9G29 RES_0603_R [46D4] R9G30 RES_0603_R [46E4] R9G31 RES_0603_R [46D4] R9G32 RES_0805_R [46E4] R9H1 RES_0402_R [25C2] R9H2 RES_0402_R [47B2] R9J1 RES_0402_R [47B6] R9J2 RES_0402_R [47B6] R9J3 RES_0402_R [47B6] R9J4 RES_0402_R [47B6] R9J5 RES_0402_R [47B6] R9J6 RES_0402_R [47B6] R9J7 RES_0402_R [47C8] R9J8 RES_0402_R [47C6] R9J9 RES_0402_R [47D8] R9J10 RES_0603_R [47D8] R9J11 RES_0603_R [19D1] R10F1 RES_0402_R [9D5] R10F2 RES_0603_R [46A7] R10F3 RES_0402_R [46B7] R10F4 RES_0402_R [46B7] R10F5 RES_0603_R [46A6] R10F6 RES_0603_R [46A6] R10F7 RES_0603_R [46B6] R10F8 RES_0603_R [46B6] R10G1 RES_0402_R [42B3] R10G2 RES_0402_R [42A1] R10G3 RES_0402_R [42A1] R10G4 RES_0402_R [42B1] R10G5 RES_0402_R [42B1] R10G6 RES_0402_R [42C1] R10H1 RES_0402_R [42B3] R10H2 RES_0402_R [42C3] R10H3 RES_0603_R [44C1] R10H4 RES_0603_R [47B2] R10H5 RES_0603_R [44C1] R10K1 RES_0805_R [47C4]
R12E1 RES_0402_R [10B5] R12E2 RES_0402_R [10C5] R12E3 RES_0402_R [10B5] R12E4 RES_0402_R [10B5] R12E5 RES_0402_R [8D6] R12E6 RES_0402_R [8D6] R12E7 RES_0402_R [10A4] R12E8 RES_0402_R [9D5] R12F1 RES_0402_R [9A8] R12F2 RES_0402_R [9A8] R12F3 RES_0402_R [9A6] R12F4 RES_0402_R [9A5] R12F5 RES_0402_R [10B2] R12F6 RES_0402_R [12D2] R12F7 RES_0402_R [12D2] R12F8 RES_0402_R [12D2] R12F9 RES_0402_R [12D2] R12F10 RES_0402_R [10D3] R12F11 RES_0402_R [10B3] R12F12 RES_0402_R [9C8] R12F13 RES_0402_R [9C7] R12F14 RES_0402_R [9C7] R12F15 RES_0402_R [9C7] R12F16 RES_0402_R [9C6] R12F17 RES_0402_R [8A3] R12F18 RES_0402_R [9B6] R12F19 RES_0402_R [10C3] R12F20 RES_0402_R [10C3] R12F21 RES_0402_R [9C4] R12G1 RES_0402_R [44A4] R12G2 RES_0402_R [11D3] R12G3 RES_0402_R [11D3] R13D1 RES_0402_R [10C4] R13D2 RES_0402_R [9A4] R13D3 RES_0402_R [9A5] R13D4 RES_0402_R [8A2] R13E1 RES_0402_R [10B5] R13E2 RES_0402_R [10B4] R13E3 RES_0402_R [10A3] R13E4 RES_0402_R [10B3] R13F1 RES_0402_R [10D3] R13F2 RES_0402_R [9A5] R13F3 RES_0402_R [10D4] R13F4 RES_0402_R [9A5] R13F5 RES_0402_R [10D3] R13F6 RES_0402_R [8B2] R13F7 RES_0402_R [9C4] R13F8 RES_0402_R [9D7] R13F9 RES_0402_R [9A6] R13F10 RES_0402_R [9D7] R13F11 RES_0402_R [10B2] R13F12 RES_0402_R [9B8] R13F13 RES_0402_R [9B8] R13F14 RES_0402_R [9B8] R13F15 RES_0402_R [10D3] R13F16 RES_0402_R [10C3] R13F17 RES_0402_R [10C3] R13F18 RES_0402_R [9D6] R13F19 RES_0402_R [9A7] R13F20 RES_0402_R [9D6] R13F21 RES_0402_R [9D5] R13F22 RES_0402_R [9C6] R13F23 RES_0402_R [10B2] R13F24 RES_0402_R [9A8] R13F25 RES_0402_R [9A8] R13F26 RES_0402_R [10A7] R13F27 RES_0402_R [9C7] R14A1 RES_0402_R [36B4] R14A2 RES_0402_R [36B4] R14A3 RES_0402_R [36A5] R14A4 RES_0402_R [36B5] R14E1 RES_0402_R [9B5] R14E2 RES_0402_R [10A2] R14F1 RES_0402_R [10A4] R14F2 RES_0402_R [9D8] R14F3 RES_0402_R [9C8] R14F4 RES_0402_R [9D8] R14F5 RES_0402_R [10D7] R14F6 RES_0402_R [10D7] R16D1 RES_0402_R [19D3] R16E1 RES_0402_R [20C6] R16E2 RES_0402_R [21A3] R16E3 RES_0402_R [15D5] R16E4 RES_0402_R [12C7] R16E5 RES_0402_R [15D3] R16E6 RES_0402_R [21B3] R16E7 RES_0402_R [19E1] R17E1 RES_0402_R [19D2] R17E2 RES_0402_R [17C2] R17E3 RES_0402_R [17C3] R17E4 RES_0402_R [17A7] R17E5 RES_0402_R [17C3] RP1C1 RPAK_0805_R [40C7 40C7 40C7 40C7] RP1C2 RPAK_0805_R [40D7 40C7 40D7
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40D7] RP1C3 RPAK_0805_R [40B7 40A7 40B7 40A7] RP1C4 RPAK_0805_R [40B7 40B7 40B7 40B7] RP1F1 RPAK_0805_R [32A8 32A8 32A8 32A8] RP1H1 RPAK_1206_R [41D5 41D6 41D6 41D5] RP1H2 RPAK_1206_R [41B6 41B5 41B6 41B5] RP1J1 RPAK_1206_R [41C5 41C5 41C5 41C5] RP1J2 RPAK_1206_R [41D5 41D5 41D6 41D6] RP1J3 RPAK_1206_R [41C6 41C6 41C6 41C6] RP2C1 RPAK_1206_R [31C2 31C2 31C2 31C2] RP2D1 RPAK_1206_R [31B2 31B2 31A2 31B2] RP2D2 RPAK_1206_R [31B2 31B2 31A2 31B2] RP5H1 RPAK_0805_R [27B4 27B2 27A2 27A4] RP5H2 RPAK_0805_R [27B4 27B4 27A4 27B2] RP5J1 RPAK_0805_R [27A6 27B6 27D2 27B6] RP5J2 RPAK_0805_R [27B2 27A6 27B6 27D2] RP6H1 RPAK_0805_R [27A4 27A2 27A4 27A4] RP6H2 RPAK_0805_R [27C4 27D4 27A4 27B4] RP6H3 RPAK_0805_R [27D4 27D4 27D4 27D4] RP6H4 RPAK_0805_R [27C4 27C4 27C4 27C4] RP6H5 RPAK_0805_R [27B4 27C4 27A4 27C4] RP6H6 RPAK_0805_R [27A2 27A4 27A4 27B4] RP6J1 RPAK_0805_R [27A6 27A6 27A6 27C2] RP6J2 RPAK_0805_R [27A6 27D6 27B6 27C6] RP6J3 RPAK_0805_R [27D6 27D6 27D6 27D6] RP6J4 RPAK_0805_R [27C6 27C6 27C6 27C6] RP6J5 RPAK_0805_R [27C6 27B6 27C6 27B6] RP6J6 RPAK_0805_R [27C2 27B6 27C2 27A6] RP9A1 RPAK_0805_R [35A7 35A7 35B7 35B7] RP9A2 RPAK_0805_R [35A6 35A6 35B6 35B6] RP9F1 RPAK_1206_R [9C2 9B2 9C2 9B2] RP9G1 RPAK_1206_R [9B2 9A2 9A2 9B2] RP10A1 RPAK_0805_R [35B4 35B4 35B5 35B5] RT1B1 THERMISTOR_1206_R [33D3] RT1B2 THERMISTOR_1206_R [33C5] RT1E1 THERMISTOR_1812_R [32C2] RT2H1 THERMISTOR_0603_R [39B8] RT5A1 THERMISTOR_1812_R [33A5] RT7B1 THERMISTOR_1812_R [33D4] RT8B1 THERMISTOR_1206_R [36A5] RT8B2 THERMISTOR_1206_R [36C1] RT9G1 THERMISTOR_0603_R [46D6] RT10B1 THERMISTOR_1206_R [35B5] RT10F1 THERMISTOR_0603_R [46A7] S2G1 BUTTON_SWT_R [19C1] U1A1 AMS1117_SOT223_SOT-223_R [37D2] U1C1 DRIVER_RS232_TSSOP_R [40D5 40D5 40D5 40C5 40C5 40C5 40C5 40C5 40A7] U1F1 TSB43AB22A_TQFP_R [32D6] U2F1 RT9183_SOIC-8_R [48B3] U2G1 ISL6545_SOIC8_R [48C6] U2J1 EEPROM_2WIRE_8PIN_SOIC_R [15B6] U2J2 W83627DH_PQFP-128_R [39B4] U3A1 ALC888S_TQFP_R [37C5] U3C1 AND_GATE_5PIN_SC70_R [16E5] U4C1 FLASH_SPI_8PIN_SOCKETW_R [19A4] U5B1 88E1116R_QFN64_R [34D5] U5E1 MCP7A_BGA1437 [12D5] U5E1 MCP7A_BGA1437 [13C5] U5E1 MCP7A_BGA1437 [14C5] U5E1 MCP7A_BGA1437 [15D4] U5E1 MCP7A_BGA1437 [16D4] U5E1 MCP7A_BGA1437 [17C5] U5E1 MCP7A_BGA1437 [18C4]
U5E1 MCP7A_BGA1437 [19E4] U5E1 MCP7A_BGA1437 [20D5] U5E1 MCP7A_BGA1437 [21B5] U5E1 MCP7A_BGA1437 [22D5] U6B1 AMS1117_SOT223_SOT-223_R [34A8] U6B2 OPAMP_SOT23-5_R [49C2] U6B3 ISL6612CB_SM_IC_SO8 [46B4] U6C1 ISL6545_SOIC8_R [49B6] U6D1 RT9179_SOT-25_R [49D7] U7J1 OPAMP_SOT23-5_R [45C6] U8E1 SKT_775P_LGA_R [8B7 8B5] U8E1 SKT_775P_LGA_R [9B3] U8E1 SKT_775P_LGA_R [10B8 10B6] U8G1 DS4404_TDFN-15_R [11A5] U9A1 AND_GATE_14PIN_TSSOP14_R [36D5 36D1 36D6 36D2] U9G1 ISL6322_SM_IC_QFN48L [46D5] U9H1 RT9173_TO-263_R [47C2] U9J1 ISL6545_SOIC8_R [47C7] U10F1 COMPARATOR_SOIC-8_R [46B6 46A7] Y1G1 XTAL_HC49_R [32A7] Y4B1 XTAL_HC49_R [34C7] Y4D1 XTAL_HC49_R [19C7] Y5D1 XTAL_PLA_4P_R [19B6]
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602-7R177-0000-F00 606.0
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