MSI MS-7535 Schematics
1
1Cover Sheet
Block Diagram/Clock Map/Power Map 2-4
Diamondville 1.66G
Intel 945GC
Intel ICH7 - PCI & DMI & CPU & IRQ
Intel ICH7 - LPC & ATA & USB & GPIO 12
Intel ICH7 - POWER
Clock - ICS954119DFLF
LPC I/O - FINTEK7882F
LAN - Realtek RTL8101E
DDR II System Memory
Azalia - ALC662/ALC888
PCI Slot 1
A A
SATA/IDE Connectors
USB Connectors
ATX Connetcor & Front Panel
uPI ACPI
DDR Power solution
VGA Connector
& DDR II VTT Decoupling
5-6
7-10
11
13
14
15
16
17-18
19
20
21
22
23
24
25
26
DiamondVille
MS-7535
CPU:
DiamondVille SC(4W)
DiamondVille DC(8W)
System Chipset:
Intel 945GC (North Bridge)
Intel ICH7 (South Bridge)
On Board Chipset:
BIOS - SPI 4M
HD - ALC662/ALC888
LPC Super I/O - FINTEK7882F
LAN-- REALTEK RTL8101E
CLOCK - ICS954119DFLF
Main Memory:
DDR II *1 (Max 2GB)
Expansion Slots:
PCI2.3 SLOT * 1
PWM:
ISL6314CRZ SINGLE PHASES
Version 0B
VRM ISL6314CRZ
DC IN POWER
MANUAL PARTS
Change History
GPIO & PCI Config
27
28
29
30
31
MICRO-STAR INT'L CO.,LTD
Cover Sheet
MS-7535
Sheet of
132
0B
MSI
Size Document Description Rev
Custom
Wednesday, May 14, 2008
1
Date:
1
Block Diagram
ISL6314CRZ
SINGLE-Phase PWM
RGB
D_SUB
Diamondville
133/200/266
MHz
FSB
FSB 533
DDR2 533/667
2DDR II
DIMM
Modules
945GC
DMI
A A
IDE Primary
SATA 0~1
USB Port 0~7
ALC888/662
UltraDMA 33/66/100
SATA 2
USB 2.0
ICH7
PCI Slot 1
PCI 33MHz
LPC Bus
RTL8101E
PCIE
4M SPI
1
LPC SIO
ITE
IT8718F-HX
Keyboard
Mouse
COM PORT * 1
MICRO-STAR INT'L CO.,LTD
MSI
Size Document Description Rev
Custom
Wednesday, May 14, 2008
Date:
MS-7535
BLOCK DIAGRAM
Sheet of
232
0B
5
4
3
2
1
CLOCK MAP
D D
HCLK
Diamondville
MCHCLK
DOT96M
945GC
DDRCLKA
CH A
PCIECLK
PCIECLK
C C
ICS954119DFLF
SATACLK
ICHCLK
USB48MHz
ICH7
ICH14.318MHz
SIO48MHz
33MHz
HDCLK 24M
B B
PCIELAN_100M
ITE SIO
ALC662/888
RTL8101E
PCIEX1 100MHz
PCICLK[0..1]
LAN
PCI1
33MHz
A A
MICRO-STAR INT'L CO.,LTD
MSI
Size Document Description Rev
Custom
CLOCK MAP
Wednesday, May 14, 2008
5
4
3
2
Date:
MS-7535
1
Sheet of
332
0B
5
4
3
2
1
W83310DS Regula
Processor
Vcore=1.1V/3A
V_FSB_VTT=1.1V/2.5A
D D
VCCA=1.5V /130mA
ISL6314
VCCP
1.1V
VTT_DDR
0.9V
DDR2 DIMM conn(2) & term
0.9V SM Vtt-1.2A(S0)
1.8V Vdd/vddq-4.7A(S0,S1)
945GC
1.1V FSB Vtt-0.9A
1.8V DDR2 I/O-4.4A(S0,S1)
VTT Regulator
V_FSB_VTT
1.1V
1.8V DDR2 I/O-25mA(S3)
0.9V DDR2 VREF-2mA
0.9V DDR2 SB_VREF-10uA
DDR2 Resister Comp V-36mA
DDR2 Resis Comp SB_V-10uA
Divider
R
uP6103 Regulator
VCC_DDR
1.8V
1.5V Core-13.8A(Integrated)
1.5V Core-8.9A(Discrete)
C C
1.5V PCI Express&DMI-1.5A
1.5V PCIE&DMI PLL-45mA
1.5V HOST PLL-45mA
1.5V VCCA_DPLLA&B-55mA
Linear
V_1P5_CORE
1.5V
1.5V MPLL-66mA
2.5V DAC-70mA*
2.5V HV-3mA
2.5V CMOS-2.0mA
uP7707 Regulator
V_2P5_MCH
2.5V
ICH7
1.1V VCC_CPU-14mA
1.05V Core-2A
VCC1_5A*-1.01A
VCC1_5B*-0.77A
B B
5VRef-6mA
R
1.05V Regulator
V_1P05_CORE
1.05V
5VrefSus-10mA
+3.3V-0.33A
RTC-6uA(G3)
3.3V VccSus*-52mA
VccSus1_05V-See Note 1
uP7706 Regulator
3VSB
3.3V
uP7501 Regulator
5VDIMM
5V
VccUSBPLL-10mA
VccDMIPLL-50mA
VccSATAIPLL-50mA
L
L
PCI slot
+3.3Vaux-375mA(wake)
+3.3Vaux-20mA(no wake)
+3.3V-7.6A
+5.0V-5.0A
+12V-0.5A
-12V-0.1A
USB PS2
+5V-4A(S0,S1) +5V-345mA(S0,S1)
LAN
SIO
+3.3V
CLKGEN
+3.3V-560mA3VSB-
SPI ROM
3VSB-
Battery
Audio Codec
A A
+5VSB+12V +5V +3.3V
DC IN POWER
MSI
5
4
3
2
MICRO-STAR INT'L CO.,LTD
Size Document Description Rev
Custom
Wednesday, May 14, 2008
Date:
MS-7535
Power Map
1
Sheet of
432
0B
5
4
3
2
1
V_FSB_VTT
M19
H21
M20
D17
N21
G19
R19
C19
D19
C14
C18
C20
D20
C15
C16
M18
U18
R16
R15
U17
M15
P21
H20
N20
R20
N19
G20
L20
K19
L21
K20
P20
F19
E21
A16
E20
B18
B16
B17
A17
B14
B15
A14
B19
T16
T15
L16
J19
J20
J21
D6
G6
H6
K4
K5
J4
U9A
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
AP0
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
AP1
A20M#
FERR#
IGNNE#
STPCLK#
LINT0
LINT1
SMI#
NC1
NC2
NC3
NC4
NC5
NC6
NC7
H_REQ#[0..4]
H_A#[3..35]
H_RS#[0..2]
ADDR GROUP
0
ADDR GROUP
1
Diamondville
ADS#
BNR#
BPRI#
DEFER#
DRDY#
DBSY#
BR0#
IERR#
INIT#
LOCK#
CONTROL
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
HIT#
HITM#
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
BR1#
XDP/ITP SIGNALSTHERMH CLK
PROCHOT#
THERMDA
THERMDC
THERMTRIP#
BCLK[0]
BCLK[1]
RSVD3
RSVD2
RSVD1
V19
Y19
U21
T21
T19
Y18
T20
F16
V16
W20
D15
W18
Y17
U20
W19
AA17
V20
K17
J18
H15
J15
K18
J16
M17
N16
M16
L17
K16
V15
G17
E4
E5
H17
V11
V12
C21
C1
A3
H_ADS#
H_BNR#
H_BPRI#
H_DEFER#
H_DRDY#
H_DBSY#
H_BR#0
H_IERR#
H_INIT#_R
H_LOCK#
H_CPURST#
H_RS#0
H_RS#1
H_RS#2
H_TRDY#
H_HIT#
H_HITM#
H_BPM#0
H_BPM#1
H_BPM#2
H_BPM#3
H_BPM#4
H_BPM#5
H_TCK
H_TDI
H_TDO
H_TMS
H_TRST#
H_PROCHOT#
VTIN1
GNDHM
H_TRMTRIP#
H_ADS# 7
H_BNR# 7
H_BPRI# 7
H_DEFER# 7
H_DRDY# 7
H_DBSY# 7
H_BR#0 7
R81 1KR0402
H_LOCK# 7
H_CPURST# 7
H_TRDY# 7
H_HIT# 7
H_HITM# 7
TP20
TP32
TP13
VTIN1 15
GNDHM 15
H_TRMTRIP# 11
CK_H_CPU 14
CK_H_CPU# 14
TP11
TP12
TP7
V_FSB_VTT
CRB
R82
X_330R0402
8P4R-51R0402
RN2
1
2
3
4
5
6
7
8
R399 51R0402
R398 51R0402
H_REQ#[0..4]7
H_A#[3..35]7
H_RS#[0..2]7
D D
H_ADSTB#07
C C
H_ADSTB#17
H_A20M#11
H_FERR#11
H_IGNNE#11
H_STPCLK#11
H_INTR11
H_NMI11
ICH_H_SMI#11
B B
TP8
H_ADSTB#1
H_A20M#
H_FERR#
H_IGNNE#
H_STPCLK#
H_INTR
H_NMI
ICH_H_SMI#
TP9
TP14
TP16
TP15
TP18
TP17
TP19
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_ADSTB#0
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
TP21
PLACE AT CPU END OF ROUTE
R396 1KR0402
R397 62R0402
BOTTOM side
R100 51R0402
R393 51R0402
CRB
H_INIT# 11
V_FSB_VTT
H_TMS
H_TDI
H_TCK
H_TRST#
8P4R-56R/4
RN3
1
3
5
7
H_IERR#
H_PROCHOT#
H_BR#0
H_CPURST#
V_FSB_VTT
2
4
6
8
CPU_GTLREF
TP30
TP33
CPU_EXTBGREF
CPU_BSEL014
CPU_BSEL114
CPU_BSEL214
V_FSB_VTT V_FSB_VTT
TP31
TP27
TP29
TP26
TP23
TP22
TP25
TP28
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_DSTBN#0
H_DSTBP#0
H_DBI#0
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_DSTBN#1
H_DSTBP#1
H_DBI#1
W10
AA14
AA11
W12
AA16
W15
AA13
W13
W16
Y11
Y12
Y10
Y13
Y16
AA9
Y14
Y15
AA5
AA6
AA8
T17
N15
P17
W9
W3
W7
W6
W2
W4
M6
Y9
V9
Y8
U1
Y7
Y3
V3
U2
T3
V2
Y4
Y5
Y6
R4
A7
U5
V5
R6
N6
T6
J6
H5
G5
H_DBI#[0..3]7
H_D#[0..63]7
H_DSTBP#[0..3]7
H_DSTBN#[0..3]7
U9B
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DP#0
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
DP#1
GTLREF
ACLKPH
DCLKPH
BINIT#
EDM
EXTBGR
FORCEPR#
HFPLL
MCERR#
RSP#
BSEL[0]
BSEL[1]
BSEL[2]
Diamondville
H_DBI#[0..3]
H_D#[0..63]
H_DSTBP#[0..3]
H_DSTBN#[0..3]
D[32]#
D[33]#
DATA GRP0
DATA GRP1
MISC
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
DATA GRP2DATA GRP3
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
CORE_D
CMREF
DP#2
DP#3
SLP#
R3
R2
P1
N1
M2
P2
J3
N3
G3
H2
N2
L2
M3
J2
H1
J1
K2
K3
L1
M4
C2
G2
F1
D3
B4
E1
A5
C3
A6
F2
C6
B6
B3
C4
C7
D2
E2
F3
C5
D4
T1
T2
F20
F21
R18
R17
U4
V17
N18
A13
B7
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_DSTBN#2
H_DSTBP#2
H_DBI#2
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DSTBN#3
H_DSTBP#3
H_DBI#3
H_COMP0
H_COMP1
H_COMP2
H_COMP3
H_DPRSTP#
H_DPSLP#
H_DPWR#
H_PWRGD
H_CPUSLP#
CPU_GTLREF
TP24
TP6
0.5" max length
25 MIL AWAY FROM HIGH
SPEED SIGNAL
HCOMP0,2==>18MIL(24.9ohm)
HCOMP1,3==>5MIL(49.9ohm)
BOTTOM side
TP10
R402 24.9R1%0402
R401 49.9R1%0402
R93 24.9R1%0402
R90 49.9R1%0402
H_PWRGD 11
H_CPUSLP# 11
R97 1KR0402
R99 1KR0402
R400 1KR0402
CRB
V_FSB_VTT
C67
{VALUE}
R71
1KR1%0402
0.5" max
length
R75
2K_1%_0402
Title
Celeron 220 - Signal
Size Document Number Rev
Custom
2
Date: Sheet
MS-7535
0B
of
532Wednesday, May 14, 2008
1
PLACE AT CPU END OF ROUTE
A A
5
4
BOTTOM SIDE
C435
{VALUE}
3
R72
1KR1%0402
C68
{VALUE}
CPU_GTLREF CPU_EXTBGREF
0.5" max
length
R76
2K_1%_0402
5
4
3
2
1
U9D
A2
VSS
A4
VSS
A8
VSS
A15
D D
C C
B B
A A
A18
A19
A20
B13
B20
B21
C17
D14
D18
D21
E15
E16
E19
F17
F18
G13
G21
H13
H16
H18
H19
J13
J17
K13
K15
K21
L13
L15
L18
L19
M13
B1
B2
B5
B8
C8
D1
D5
D8
E3
E6
E7
E8
F4
F5
F6
F7
G1
G4
G7
G9
H3
H4
H7
H9
J5
J7
J9
K1
K6
K7
K9
L3
L4
L5
L6
L7
L9
M1
M5
M7
M9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Diamondville
GND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N9
N7
N5
N4
M21
N13
N17
P3
P4
P5
P6
P7
P9
P13
P15
P16
P18
P19
R1
R5
R7
R9
R13
R21
T4
T5
T7
T9
T10
T11
T12
T13
T18
U3
U6
U7
U15
U16
U19
V1
V4
V6
V7
V8
V13
V14
V18
V21
W1
W5
W8
W11
W14
W17
W21
Y1
Y2
Y20
Y21
AA2
AA3
AA4
AA7
AA10
AA12
AA15
AA18
AA19
AA20
V_FSB_VTT
VCORE
V10
A9
B9
A10
A11
A12
B10
B11
B12
C10
C11
C12
D10
D11
D12
E10
E11
E12
F10
F11
F12
G10
G11
G12
H10
H11
H12
J10
J11
J12
K10
K11
K12
L10
L11
L12
M10
M11
M12
N10
N11
N12
P10
P11
P12
R10
R11
R12
V_FSB_VTT
U9C
VCCF
VCCQ1
VCCQ2
VCCP1
VCCP2
VCCP3
VCCP4
VCCP5
VCCP6
VCCP7
VCCP8
VCCP9
VCCP10
VCCP11
VCCP12
VCCP13
VCCP14
VCCP15
VCCP16
VCCP17
VCCP18
VCCP19
VCCP20
VCCP21
VCCP22
VCCP23
VCCP24
VCCP25
VCCP26
VCCP27
VCCP28
VCCP29
VCCP30
VCCP31
VCCP32
VCCP33
VCCP34
VCCP35
VCCP36
VCCP37
VCCP38
VCCP39
VCCP40
VCCP41
VCCP42
VCCP43
VCCP44
VCCP45
Diamondville
C70
C1u6.3X50402
VTT1
VTT2
VTT3
VTT4
VTT5
VTT6
VTT7
VTT8
VTT9
VTT10
VTT11
VTT12
VTT13
VTT14
VTT15
VTT16
VTT17
VTT18
VTT19
VTT20
VTT21
VTT22
VTT23
VTT24
VTT25
VTT26
VTT27
VTT28
VTT29
VTT30
VTT31
POWER
VTT32
VCCPC64
VCCPC63
VCCPC62
VCCPC61
VCCA
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
VCCSENSE
VSSSENSE
C75
C10u6.3X5-RH
V_FSB_VTT
C9
D9
E9
F8
F9
G8
G14
H8
H14
J8
J14
K8
K14
L8
L14
M8
M14
N8
N14
P8
P14
R8
R14
T8
T14
U8
U9
U10
U11
U12
U13
U14
F14
F13
E14
E13
D7
F15
D16
E18
G15
G16
E17
G18
C13
D13
BOTTOM side
C436
X_C0.1U/10X/2
V_FSB_VTT
BOTTOM side
R395
0R0402
VID0
VID1
VID2
VID3
VID4
VID5
VID6
close to cpu socket
C439
C438
X_C1u6.3X50402
X_C10u6.3X5-RH
C426
X_C10u6.3X5-RH
BOTTOM
C433
X_C0.1U/10X/2
VCORE
R394
X_0R0402
Internal PLL super filter
VCC_SENSE 27
VSS_SENSE 27
LAYOUT NOTE:
Route VCCSENSE and VSSSENSE traces at
27.4Ohm(18mil) with 7 mil spacing.
Place PU and PD within 1 inch of CPU.
V_FSB_VTT
C432
X_C1u6.3X50402
C61
C1u6.3X50402
V_FSB_VTT
V_1P5_CORE
C431
BOTTOM
R70 2.2KR0402
R66 2.2KR0402
R64 2.2KR0402
R69 2.2KR0402
R74 2.2KR0402
R78 2.2KR0402
R77 2.2KR0402
R62 X_2.2KR0402
R60 X_2.2KR0402
R56 X_2.2KR0402
R53 X_2.2KR0402
R50 X_2.2KR0402
R61 X_2.2KR0402
R57 X_2.2KR0402
0.01uf and 10uf near B26
C60 C10u6.3X50805
C59 C0.01u10X0402
X_C1u6.3X50402
C428
X_C1u6.3X50402
C155
C10u6.3X50805
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID0
VID1
VID2
VID3
VID4
VID5
VID6
C84
X_C10u6.3X50805
C78
C10u6.3X50805
VID[0..6]
VID[0..6] 27
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO. , LTD.
Celeron 220 - Power / GND
MS-7535
0B
632Wednesday, May 14, 2008
1
of
5
N17
P17
P18
P20
VCC
VCC
H_A#32
H_A#33
H_A#34
H_A#35
V_FSB_VTT
R177
{VALUE}
R181
{VALUE}
VCC
P21
VCC
AA35
VCC
RSVRD1
HXSCOMP
K38
K35
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
AA37
V32
Y34
M36
V35
F38
AA41
D42
U39
U40
W42
E41
D41
K36
G37
E42
U41
W41
P40
W40
U42
V41
Y40
T40
Y43
T43
M31
M29
C30
AJ12
M18
A28
C27
B27
D27
D28
J39
J42
J37
AJ9
U18A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
H_A#[3..35]5
D D
H_ADSTB#05
H_ADSTB#15
C C
B B
ICH_SYNC#12
A A
V_FSB_VTT
PLTRST#11,15
R185 {VALUE}
H_REQ#[0..4]5
H_RS#[0..2]5
R169
{VALUE}
MCH_GTLREF_CPU
H_BPRI#5
H_BNR#5
H_LOCK#5
H_ADS#5
H_HIT#5
H_HITM#5
H_DEFER#5
H_TRDY#5
H_DBSY#5
H_DRDY#5
CK_H_MCH14
CK_H_MCH#14
CHIP_PWGD12,24
H_CPURST#5
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
TP35
H_BR#05
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
TP34
H_RS#0
H_RS#1
H_RS#2
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
C197
C2.2p50N0402
PLACE DIVIDER RESISTOR NEAR VTT
5
4
V_1P5_CORE
AA22
AB21
AB22
AB23
AC22
AD14
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF30
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AH1
AH2
AH4
AJ5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD31
RSVRD32
RSVRD33
RSVRD34
RSVRD2
RSVRD3
RSVRD4
RSVRD5
RSVRD6
RSVRD7
RSVRD8
RSVRD9
RSVRD10
RSVRD11
RSVRD12
RSVRD13
RSVRD14
RSVRD15
RSVRD16
RSVRD17
RSVRD18
RSVRD19
RSVRD20
RSVRD21
RSVRD22
RSVRD23
AA42
AA34
AA38
L15
M15
U27
R27
A43
M11
AG25
AG26
AG27
AJ24
AJ27
AK40
AL39
AW17
AW18
AY14
BC16
AD30
AC34
Y30
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
R182 {VALUE} R174 {VALUE}
HXSWING
C194
C0.1u10X0402-1
RSVRD30
RSVRD24
RSVRD25
RSVRD26
RSVRD27
RSVRD28
RSVRD29
AC30
AK21
AJ23
AJ26
AA30
Y33
AF31
AD31
U30
V31
V_FSB_VTT
3
AJ13
AJ14
AK2
AK3
AK4
AK14
AK15
AK20
R15
R17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD35
RSVRD36
RSVRD37
RSVRD38
RSVRD39
RSVRD40
RSVRD41
RSVRD42
NC1
AL29
AL20
AJ21
AL26
AK27
AJ29
AG29
V30
BC43
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
R171
124 OHM OVER 210 RESISTORS
{VALUE}
R179
{VALUE}
C186
C0.1u10X0402-1
CAPS SHOULD BE PLACED NEAR MCH PIN
4
3
R18
VCC
NC2
BC42
R20
BC2
VCC
NC3
R21
VCC
NC4
BC1
R23
VCC
NC5
BB43
R24
VCC
NC6
BB2
U15
U17
U18
U19
VCC
VCC
VCC
VCC
NC7
NC8
NC9
NC10
BB1
BA2
AW26
AW2
MCH_GTLREF_CPU
C191
X_C220p50N0402
U20
VCC
NC11
AV27
U21
VCC
NC12
AV26
U22
VCC
NC13
E35
U23
U24
VCC
VCC
NC14
NC15
C42C2B43
2
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
W24
W26
W27
Y15
VCC
NC16
VCC
NC17
B42
VCC
VCC
NC18
NC19
B41B3B2
VCC
NC20
M17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC21
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A42
Y17
Y18
Y19
Y21
Y23
Y25
Y27
AA15
AA17
VCC
VCC
VCC
VCC
AA18
VCC
VCC
AA19
VCC
VCC
AA20
VCC
VCC
VCC
KDINV_0#
HDINV_1#
HDINV_2#
HDINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
{VALUE}
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
V_1P5_CORE
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
K40
A38
E29
B32
K41
L43
F35
G34
J27
M26
E34
B37
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0
H_DSTBN#0
H_DSTBP#1
H_DSTBN#1
H_DSTBP#2
H_DSTBN#2
H_DSTBP#3
H_DSTBN#3
H_DSTBP#[0..3]5
H_DSTBN#[0..3]5
1
H_D#[0..63] 5
H_DBI#[0..3] 5
H_DSTBP#[0..3]
H_DSTBN#[0..3]
MICRO-STAR INT'L CO.,LTD
MSI
Size Document Description Rev
Custom
Wednesday, May 14, 2008
2
Date:
MS-7535
945GC - CPU Signals
1
732
Sheet of
0B
5
4
3
2
1
DQM_A[0..7]17
SCKE_A[0..1]17,18
DATA_A[0..63]17
D D
SCS_A#[0..1]17,18
RAS_A#17,18
CAS_A#17,18
WE_A#17,18
MAA_A[0..13]17,18
C C
ODT_A[0..1]17,18
SBS_A[0..2]17,18
DQS_A[0..7]17
DQS_A#[0..7]17
B B
DQS_A[0..7]
DQS_A#[0..7]
P_DDR_A017
N_DDR_A017
P_DDR_A117
N_DDR_A117
P_DDR_A217
N_DDR_A217
SCS_A#0
SCS_A#1
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
ODT_A0
ODT_A1
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR_A0
N_DDR_A0
P_DDR_A1
N_DDR_A1
P_DDR_A2
N_DDR_A2
VCC_DDR
C258
{VALUE}
R249
R246
{VALUE}
SMPCOMP_N
SMPCOMP_P
TP37
TP2
BB37
BA39
BA35
AY38
BA34
BA37
BB35
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
AW37
AY39
AY37
BB40
BC33
AY34
BA26
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
BB32
AY32
AK42
AK41
BA31
BB31
AH40
AH43
AU4
AR2
BA3
BB4
AY5
BB5
AY6
BA5
AL5
AJ6
AJ8
AM3
U18B
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACLK0
SACLK0#
SACLK1
SACLK1#
SACLK2
SACLK2#
SACLK3
SACLK3#
SACLK4
SACLK4#
SACLK5
SACLK5#
MCH_SRCOMP0
MCH_SRCOMP1
SMOCDCOMP0
SMOCDCOMP1
C0.1U/10X/2
DATA_A0
AP3
SADQ0
DATA_A1
AP2
SADQ1
DATA_A2
AU3
AL6
DATA_A3
DATA_A4
AV4
SADQ2
SADQ3
SBDQ0
SBDQ1
AL8
DATA_A5
AN1
SADQ4
SBDQ2
AP8
DATA_A6
AP4
AU5
SADQ5
SBDQ3
AP9
AJ11
DATA_A8
DATA_A7
AU2
SADQ6
SADQ7
SBDQ4
SBDQ5
AL9
DATA_A9
AW3
SADQ8
SBDQ6
AM10
DATA_A10
AY3
BA7
SADQ9
SBDQ7
AP6
AU7
DATA_A11
DATA_A12
BB7
AV1
SADQ10
SADQ11
SADQ12
SBDQ8
SBDQ9
SBDQ10
AV6
AV12
DATA_A14
DATA_A13
AW4
BC6
SADQ13
SBDQ11
AM11
AR5
DATA_A16
DATA_A15
AY7
AW12
SADQ14
SADQ15
SBDQ12
SBDQ13
AR7
AR12
DATA_A18
DATA_A17
AY10
BA12
SADQ16
SADQ17
SBDQ14
SBDQ15
AR10
AM15
DATA_A20
DATA_A19
BB12
BA9
SADQ18
SADQ19
SBDQ16
SBDQ17
AM13
AV15
DATA_A21
DATA_A22
BB9
BC11
SADQ20
SADQ21
SBDQ18
SBDQ19
AM17
AN12
DATA_A23
DATA_A24
AY12
AM20
SADQ22
SADQ23
SBDQ20
SBDQ21
AR13
AP15
DATA_A25
DATA_A26
AM18
AV20
SADQ24
SADQ25
SADQ26
SBDQ22
SBDQ23
SBDQ24
AT15
AM24
DATA_A27
DATA_A28
AM21
AP17
SADQ27
SADQ28
SBDQ25
SBDQ26
AM23
AV24
DATA_A29
DATA_A30
AR17
AP20
SADQ29
SADQ30
SBDQ27
SBDQ28
AM26
AP21
DATA_A32
DATA_A31
AT20
AP32
SADQ31
SBDQ29
AR21
AP24
DATA_A34
DATA_A33
AV34
AV38
SADQ32
SADQ33
SBDQ30
SBDQ31
AT24
AU27
DATA_A35
DATA_A36
AU39
AV32
SADQ34
SADQ35
SBDQ32
SBDQ33
AN29
AR31
DATA_A37
DATA_A38
AT32
AR34
SADQ36
SADQ37
SBDQ34
SBDQ35
AM31
AP27
DATA_A40
DATA_A39
AU37
AR41
SADQ38
SADQ39
SBDQ36
SBDQ37
AR27
AP31
DATA_A41
DATA_A42
AR42
AN43
SADQ40
SADQ41
SADQ42
SBDQ38
SBDQ39
SBDQ40
AU31
AP35
DATA_A43
DATA_A44
AM40
AU41
SADQ43
SBDQ41
AP37
AN32
DATA_A45
DATA_A46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
DATA_A47
DATA_A48
AN40
AL41
SADQ46
SADQ47
SBDQ44
SBDQ45
AU38
AM38
DATA_A49
DATA_A50
AL42
AF39
SADQ48
SADQ49
SBDQ46
SBDQ47
AM34
AL34
DATA_A52
DATA_A51
AE40
AM41
SADQ50
SADQ51
SBDQ48
SBDQ49
AJ34
AF32
DATA_A53
DATA_A54
AM42
AF41
SADQ52
SADQ53
SBDQ50
SBDQ51
AF34
AL31
DATA_A55
DATA_A56
AF42
AD40
SADQ54
SADQ55
SBDQ53
SBDQ52
AJ32
AG35
DATA_A57
DATA_A58
AD43
AA39
SADQ56
SADQ57
SADQ58
SBDQ54
SBDQ55
SBDQ56
AD32
AC32
DATA_A60
DATA_A59
AA40
AE42
SADQ59
SADQ60
SBDQ57
SBDQ58
AD34
Y32
DATA_A61
DATA_A62
AE41
AB41
SADQ61
SBDQ59
AA32
AF35
DATA_A63
AB42
SADQ62
SADQ63
SBDQ60
SBDQ61
AF37
AC33
SCKE_A0
BB25
SACKE0
SBDQ62
SBDQ63
AC35
SCKE_A1
AY25
BC24
SACKE1
BA14
BA25
SACKE2
SACKE3
SBCKE0
SBCKE1
AY16
BA13
DQM_A0
AR3
SBCKE2
SBCKE3
BB13
SADM0
DQM_A1
AY2
AD39
SADM1
SBDM7
DQM_A2
BB10
AJ39
SADM2
SBDM6
DQM_A3
AP18
AR38
SADM3
SBDM5
DQM_A4
AT34
AR29
DQM_A6
DQM_A7
DQM_A5
AC40
AG40
AP39
SADM7
SADM6
SADM5
SADM4
SBDM1
SBDM2
SBDM3
SBDM4
AW7
AP13
AP23
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1
SMVREF0
SBDM0
AL11
BA40
AW41
BA41
AW40
BA23
AY24
BB23
BB22
BB21
BA21
AY21
BC20
AY19
AY20
BA18
BA19
BB18
BA22
BB17
BA17
AW42
AY42
AV40
AV43
AU40
AW23
AY23
AY17
AM8
AM6
AV7
AR9
AV13
AT13
AU23
AR23
AT29
AV29
AP36
AM35
AG34
AG32
AD36
AD38
AM29
AM27
AV9
AW9
AL38
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
AM2
AM4
C262
C0.1U/10X/2
Parts Close To MCH
MCH_VREF_DDR
C255
C0.1U/10X/2
VCC_DDR
R248
{VALUE}
R251
{VALUE}
{VALUE}
A A
MICRO-STAR INT'L CO.,LTD
MSI
Size Document Description Rev
Custom
Wednesday, May 14, 2008
5
4
3
2
Date:
MS-7535
945GC - Memory Signals
1
832
Sheet of
0B
5
V_1P5_CORE
AA26
AB17
AB18
AB19
AB20
U18C
G12
EXPARXP0
F12
EXPARXN0
D11
EXPARXP1
D12
EXPARXN1
J13
EXPARXP2
H13
EXPARXN2
NOA_6
C10000p10X0402-RH
H10
U11
U10
AA9
AA10
AA6
AA7
AC9
AC8
H21
AK17
AL17
AK23
AK18
N21
C21
C19
D19
C18
E10
F10
J9
F7
F9
C4
D3
G6
J6
K9
K8
F4
G4
M6
M7
K2
L1
R8
R7
P4
N3
Y10
Y11
F20
Y7
Y8
B14
B16
F15
E15
F21
L20
K21
L21
L18
B20
B19
B17
B18
A18
EXPARXP3
EXPARXN3
EXPARXP4
EXPARXN4
EXPARXP5
EXPARXN5
EXPARXP6
EXPARXN6
EXPARXP7
EXPARXN7
EXPARXP8
EXPARXN8
EXPARXP9
EXPARXN9
EXPARXP10
EXPARXN10
EXPARXP11
EXPARXN11
EXPARXP12
EXPARXN12
EXPARXP13
EXPARXN13
EXPARXP14
EXPARXN14
EXPARXP15
EXPARXN15
EXP_EN
DMI RXP0
DMI RXN0
DMI RXP1
DMI RXN1
DMI RXP2
DMI RXN2
DMI RXP3
DMI RXN3
GCLKP
GCLKN
SDVOCTRLDATA
SDVOCTRLCLK
BSEL0
BSEL1
BSEL2
RSV_TP[0]
RSV_TP[1]
EXP_SLR
RSV_TP[2]
RSV_TP[3]
RSV_TP[4]
RSV_TP[5]
RSV_TP[6]
VCCAHPLL
VCCAMPLL
VCCADPLLA
VCCADPLLB
VCCA_EXPPLL
VCC2
VCCADAC
VCCADAC
VSSA_DAC
V_FSB_VTT
D D
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
V_2P5_NB
C236
C235
C0.1U/10X/2
L12
180L1.5A-90
I = 70mA
DMI_ITP_MRP_011
DMI_ITN_MRN_011
DMI_ITP_MRP_111
DMI_ITN_MRN_111
DMI_ITP_MRP_211
DMI_ITN_MRN_211
DMI_ITP_MRP_311
DMI_ITN_MRN_311
CK_PE_100M_MCH14
CK_PE_100M_MCH#14
H_BSL014
H_BSL114
H_BSL214
V_2P5_DAC_FILTERED
C237
C10u6.3X50805
C C
B B
V_2P5_NB
AA24
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
B23
A24
B24
B25
B26
AB24
VCC
VTT
C23
AB25
VCC
VTT
C25
AB26
VCC
VTT
C26
AB27
VCC
VTT
D23
AC15
VCC
VTT
D24
AC17
VCC
VTT
D25
4
AC18
E23
VCC
VTT
AC20
VCC
VTT
E24
AC24
VCC
VTT
E26
AC26
VCC
VTT
E27
AC27
VCC
VTT
F23
AD15
VCC
VTT
F27
AD17
VCC
VTT
G23
AD19
H23
AD23
AD25
AD21
VCC
VCC
VCC
VTT
VTT
VTT
J23
K23
L23
V_1P5_CORE
VCC
VTT
AD26
VCC
VTT
M23
AE17
VCC
VTT
N23
AE18
VCC
VTT
P23
AE20
VCC
AE22
VCC
AE24
VCC
AE26
VCC
VCC
AF21
AE27
VCC
VCC
AF23
AF15
VCC
VCC
AF25
AF17
AF26
VCC
VCC
AF19
VCC
VCC
AF27
VCC
AF29
AV18
AY43
VCCSM
VCC
AG15
AG17
AV21
VCCSM
VCCSM
VCC
VCC
AG18
AV23
AV31
VCCSM
VCC
AG19
AG20
AV42
VCCSM
VCCSM
VCC
VCC
AG21
AW13
AW15
VCCSM
VCC
AG22
AG23
AW20
AW21
VCCSM
VCCSM
VCC
VCC
AG24
AJ15
3
AW24
AW29
VCCSM
VCCSM
VCC
VCC
AJ17
AJ18
AW34
AW31
VCCSM
VCCSM
VCC
VCC
AJ20
AY41
AW35
VCCSM
VCCSM
BB16
BB20
VCCSM
VCCSM
AE4
BB24
BB28
BB33
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AE3
AE2
AD12
BB38
BB42
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AD10
AD8
BC13
BC18
BC22
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AD6
AD5
AD4
BC26
BC31
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AD2
AD1
BC35
BC40
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AC13
AC6
AC5
VCC_DDR
N5
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AA13
AA5
N11
N10N9N7
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
Y13
V13V9V10V7V6
R11
R10R5N12
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
V5
VCC_EXP
VCC_EXP
2
V_1P5_PCIEXPRESS
U13U8U7U6R13
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
EXPATXP0
EXPATXN0
EXPATXP1
EXPATXN1
EXPATXP2
EXPATXN2
EXPATXP3
EXPATXN3
EXPATXP4
EXPATXN4
EXPATXP5
EXPATXN5
EXPATXP6
EXPATXN6
EXPATXP7
EXPATXN7
EXPATXP8
EXPATXN8
EXPATXP9
EXPATXN9
EXPATXP10
EXPATXN10
EXPATXP11
EXPATXN11
EXPATXP12
EXPATXN12
EXPATXP13
EXPATXN13
EXPATXP14
EXPATXN14
EXPATXP15
EXPATXN15
DMI TXP0
DMI TXN0
DMI TXP1
DMI TXN1
DMI TXP2
DMI TXN2
DMI TXP3
DMI TXN3
EXP_COMPO
EXP_COMPI
HSYNC
VSYNC
GREEN
GREENB
BLUE#
DDC_DATA
DDC_CLK
DREFCLKINP
DREFCLKINN
EXTTS#
XORTEST
ALLZTEST
{VALUE}
V_1P5_PCIEXPRESS
RED
BLUE
RED#
IREF
D14
C13
A13
B12
A11
B10
C10
C9
A9
B7
D7
D6
A6
B5
E2
F1
G2
J1
J3
K4
L4
M4
M2
N1
P2
T1
T4
U4
U2
V1
V3
W4
W2
Y1
AA2
AB1
Y4
AA4
AB3
AC4
AC12
AC11
D17
C17
F17
K17
H18
G17
J17
J18
N18
N20
J15
H15
A20
J20
H20
K18
GRCOMP
V_1P5_CORE
VCC_DDR
MCH MEMORY DECOUPLING
DMI_MTP_IRP_0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3
R243 {VALUE}
VGA_RED
VGA_GREEN
VGA_BLUE
MCH_DDC_DATA
MCH_DDC_CLK
CK_96M_DREF
CK_96M_DREF#
R202 {VALUE}
DACREFSET
R216 {VALUE}
EXTTS
C214
X_C10p16N
C443 X_C10u6.3X50805
C444 X_C10u6.3X50805
C442 X_C10u6.3X50805
C440 X_C10u6.3X50805
C452 X_C10u6.3X50805
C446 X_C10u6.3X50805
C441 X_C10u6.3X50805
bottom side
C210 C2.2u6.3Y
C221 C2.2u6.3Y
C187 C0.1U/10X/2
C169 C2.2u6.3Y
C160 C0.1U/10X/2
C189 C2.2u6.3Y
DMI_MTP_IRP_0 11
DMI_MTN_IRN_0 11
DMI_MTP_IRP_1 11
DMI_MTN_IRN_1 11
DMI_MTP_IRP_2 11
DMI_MTN_IRN_2 11
DMI_MTP_IRP_3 11
DMI_MTN_IRN_3 11
V_1P5_PCIEXPRESS
HSYNC 26
VSYNC 26
MCH_DDC_DATA 26
MCH_DDC_CLK 26
CK_96M_DREF 14
CK_96M_DREF# 14
TP36
C354 Co-lay C283 BOTTOM SIDE
VGA_RED 26
VGA_GREEN 26
VGA_BLUE 26
C451 {VALUE}
C449 {VALUE}
C448 {VALUE}R191 {VALUE}
BOTTOM side
V_2P5_NB
﹛
1
V_1P5_CORE
bottom side
C447 X_C10u6.3X50805
C450 X_C10u6.3X50805
C445 {VALUE}
C453 {VALUE}
C261 C0.1U/10X/2
C253 C0.1U/10X/2
V_FSB_VTT
C208 C0.1U/10X/2
C205 C0.1U/10X/2
C206 C0.1U/10X/2
FSB GENERIC DECOUPLING
EMI:Close to Connector
V_1P5_CORE
VCCA_MPLL = 60mA
A A
V_1P5_CORE
VCCA_DPLLB = 55mA
L10 X_600L200mA-450
X_Copper
CP4
X_C10u6.3X50805
L13 {VALUE}
X_Copper
CP6
X_C10u6.3X50805
5
C219
C232
VCCA_MPLL
C220
C0.1U/10X/2
VCCA_DPLLB
C231
C0.1U/10X/2
V_1P5_CORE
VCCA_DPLLA = 55mA
V_1P5_CORE
VCCA_HPLL = 45mA
L11 {VALUE}
CP5
X_Copper
L8 {VALUE}
CP3
X_Copper
4
C228
X_C10u6.3X50805
C213
X_C10u6.3X50805
VCCA_DPLLA
C229
C0.1U/10X/2
VCCA_HPLL
C216
C0.1U/10X/2
V_1P5_CORE
V_1P5_PCIEXPRESS =
1.5A
V_1P5_CORE
L16
X_Copper
{VALUE}
CP9
CP8
X_Copper
X_Copper
L14 {VALUE}
CP7
VCCA_GPLL = 45mA
3
C263
C22u6.3X1206
C252
C0.1U/10X/2
C243
X_C10u6.3X50805
V_1P5_PCIEXPRESS
C260
C0.1U/10X/2
VCCA_GPLL
C239
C0.1U/10X/2
MICRO-STAR INT'L CO.,LTD
MSI
Size Document Description Rev
Custom
Wednesday, May 14, 2008
2
Date:
MS-7535
945GC PCI-Express & RBG Signals
Sheet of
1
932
0B
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