1
1Cover Sheet
Block Diagram/Clock Map/Power Map
Intel LGA775 CPU
Intel Bearlake - MCH
Intel ICH7 - PCI & DMI & CPU & IRQ
Intel ICH7 - LPC & ATA & USB & GPIO 13
Intel ICH7 - POWER
Clock - RTM 876-665
LPC I/O - Fintek 71882FG
LAN REALTEK RTL8111C/8101E
DDR II DIMM A
DDR II DIMM B
DDR II VTT Decoupling
Azalia - ALC888
PCI EXPRESS X16 Slot
A A
PCI Slot 1 & 2
ATA33/66/100 IDE & SATA Connectors
USB Connectors
ATX Connetcor & Front Panel
VGA Connector
UPI ACPI CONTROLLER
2-4
5-7
8-11
12
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Version 1.1
MS-7529
CPU:
Intel Conroe (65W Dual core)
System Chipset:
Intel Bearlake - MCH (North Bridge)
Intel ICH7R (South Bridge)
On Board Chipset:
BIOS -- SPI
HD -- ALC888
LPC Super I/O -- F71882FG
LAN-- REALTEK RTL8111C Co-lay RTL8101E
CLOCK -- RTM876-665
Main Memory:
DDR II *2 (Max 4GB)
Expansion Slots:
PCI2.3 SLOT * 2
PCI EXPRESS X16 SLOT
ST PWM:
Controller: 3 PHASES
GMCH VCORE
PWM-ST L6703TR
29
30
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MS-7529
MS-7529
Cover Sheet
Cover Sheet
Cover Sheet
MS-7529
MSI
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MSI
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Custom
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
1
Friday, May 16, 2008
Sheet of
Sheet of
Sheet of
133
133
133
1.1
1.1
1.1
Block Diagram
1
VRM 10.1
RT6703
3-Phase PWM
Analog
Video
Out
RGB
UltraDMA
33/66/100
Intel LGA775 Processor
FSB 800/1066/1333
200/266
/333MHz
FSB
Bearlake
GMCH
DMI
DDR2 667/800
DDRII
333/400
MHz
PCI
2DDR II
DIMM
Modules
PCI Slot 1
PCI Slot 2
IDE Primary
A A
SATA 0~3
USB Port 0~7
SATA
USB
ICH7
SPI
HD
LPC Bus
PCI EXPRESS X16
PCI EXPRESS
X16
Connector
SPI
ALC888
PCI
LPC SIO
RTL8111C
Fintek
F71882F
TPM
Keyboard
Floopy Parallel Serial
Mouse
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MS-7529
MS-7529
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Date:
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Date:
Friday, May 16, 2008
Date:
1
Friday, May 16, 2008
MS-7529
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Sheet of
Sheet of
Sheet of
233
233
233
1.1
1.1
1.1
5
4
3
2
1
CLOCK MAP
D D
HCLK
LGA775
MCHCLK
DOT96M
G31
DDRCLKA
CH A
CH B
DDRCLKB
PCIECLK
PCIECLK
C C
RTM876-660
SATACLK
ICHCLK
USB48MHz
ICH7
ICH14.318MHz
SIO48MHz
33MHz
Fintek SIO
HDCLK 24M
ALC888
B B
TPMCLK_33M
TPM
PCIELAN_100M
RTL8111C
PCIEX16 100MHz
PCICLK[0..1]
A A
5
4
33MHz
PCIE X 16
PCI1
PCI2
3
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CLOCK MAP
CLOCK MAP
CLOCK MAP
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
2
Friday, May 16, 2008
MS-7529
1
Sheet of
Sheet of
Sheet of
333
333
333
1.1
1.1
1.1
5
4
3
2
1
Processor
0.8375-1.6000V Core-125A
1.2V FSB Vtt-5.3A
VCCPLL
D D
C C
B B
VCC-IOPLL & VCCA
G31 MCH
1.2V FSB Vtt-0.9A
1.8V DDR2 I/O-4.4A(S0,S1)
1.8V DDR2 I/O-25mA(S3)
0.9V DDR2 VREF-2mA
0.9V DDR2 SB_VREF-10uA
DDR2 Resister Comp V-36mA
DDR2 Resis Comp SB_V-10uA
1.5V Core-13.8A(Integrated)
1.5V Core-8.9A(Discrete)
1.5V PCI Express&DMI-1.5A
1.5V PCIE&DMI PLL-45mA
1.5V HOST PLL-45mA
1.5V VCCA_DPLLA&B-55mA
1.5V MPLL-66mA
2.5V DAC-70mA*
2.5V HV-3mA
2.5V CMOS-2.0mA
ICH7
1.2V VCC_CPU-14mA
1.05V Core-0.86A
VCC1_5A*-1.01A
VCC1_5B*-0.77A
5VRef-6mA
5VrefSus-10mA
+3.3V-0.33A
RTC-6uA(G3)
3.3V VccSus*-52mA
VccSus1_05V-See Note 1
VccUSBPLL-10mA
VccDMIPLL-50mA
VccSATAIPLL-50mA
Divider
R
R
L
L
L6703 Regulator
VCCP
0.8375-1.6000V
VTT Regulator
V_FSB_VTT
1.2V
uP6103 Regulator
VCC_DDR
1.8V
uP6103 Regulator
V_1P5_CORE
1.5V
uP7707 Regulator
V_2P5_MCH
2.5V
1.05V Regulator
V_1P05_CORE
1.05V
uP7706 Regulator
3VSB
3.3V
uP7501 Regulator
5VDIMM
5V
W83310DS Regula
VTT_DDR
0.9V
DDR2 DIMM conn(4) & term
0.9V SM Vtt-1.2A(S0)
1.8V Vdd/vddq-4.7A(S0,S1)
PCIE X16 slot(1)
+12V-5.5A
+3.3Vaux-375mA(wake)
+3.3Vaux-20mA(no wake)
+3.3V-3.0A
PCIE X1 slot(1)
+12V-0.5A
+3.3Vaux-375mA(wake)
+3.3Vaux-20mA(no wake)
+3.3V-3.0A
PCI slot slot(4)
+3.3Vaux-375mA(wake)
+3.3Vaux-20mA(no wake)
+3.3V-7.6A
+5.0V-5.0A
+12V-0.5A
-12V-0.1A
USB
+5V-4A(S0,S1)
PS2
+5V-345mA(S0,S1)
CLKGEN
+3.3V-560mA
LAN
3VSB-
Battery
SIO
+3.3V
3VSB-
+5VSB+12V +5V +3.3V+12V
Audio Codec
SPI ROM
ATX
A A
2x2
ATX POWER
5
4
3
1394
MICRO-STAR INT'L CO.,LTD
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MS-7529
MS-7529
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Size Document Description Rev
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Custom
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Custom
Date:
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Date:
Friday, May 16, 2008
Date:
2
Friday, May 16, 2008
MS-7529
LGA775 - Signal
LGA775 - Signal
LGA775 - Signal
1
Sheet of
Sheet of
Sheet of
433
433
433
1.1
1.1
1.1
5
4
3
VCC_SENSE
VCC_SENSE 30
2
1
CPU SIGNAL BLOCK PULL HIGHT PULL DOWN
VSS_SENSE
H_A#[3..35]8
D D
H_A#8
H_A#10
H_A#5
H_A#6
H_A#7
H_A#3
H_A#31
H_A#28
H_A#29
H_A#30
H_A#27
H_A#24
H_A#25
H_A#26
H_A#22
H_A#21
H_A#23
H_A#18
H_A#17
H_A#20
H_A#19
H_A#16
H_A#15
H_A#11
H_A#12
H_A#13
A20#Y4A19#Y6A18#W6A17#
D37#
D36#
D35#
F17
G17
G18
H_D#37
H_D#35
H_D#36
H_A#14
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D34#
D33#
D32#
D31#
D30#
F15
E16
E15
G16
G15
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
D29#
D28#
F14
G14
H_D#28
H_D#29
H_A#32
H_A#33
H_A#34
H_A#35
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
AC5
AB5
AA5
AD6
G21
A27#
D44#
H_D#43
F21
A26#
D43#
H_D#42
E21
A25#
D42#
H_D#41
F20
A24#
D41#
H_D#40
4
E19
A23#
D40#
E18
H_D#39
A22#
D39#
H_D#38
AA4
A21#
D38#
F18
CPU1A
CPU1A
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
A14
E22
D17
D20
D22
G22
H_D#45
H_D#44
H_D#50
H_D#49
H_D#48
H_D#47
H_D#46
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
PECI
VTIN1
GNDHM
H_TRMTRIP#
H_PROCHOT#
H_IGNNE#
ICH_H_SMI#
H_A20M#
H_TESTHI13
R81
R81
CPU_BSEL0
CPU_BSEL1
CPU_BSEL2
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TEST
H_DBI#[0..3]8
H_IERR#6
H_FERR#12
H_STPCLK#12
H_INIT#12
H_DBSY#8
H_DRDY#8
H_TRDY#8
H_ADS#8
C C
H_CPUSLP#12
CPU_BSEL015,16
CPU_BSEL115,16
CPU_BSEL215,16
VTT_OUT_RIGHT
H_D#[0..63]8
RN26
RN26
8P4R-470R0402
8P4R-470R0402
B B
A A
H_LOCK#8
H_BNR#8
H_HIT#8
H_HITM#8
H_BPRI#8
H_DEFER#8
GNDHM16
H_TRMTRIP#12
H_PROCHOT#6
H_IGNNE#12
ICH_H_SMI#12
H_A20M#12
R99 X_0R0402R99 X_0R0402
H_BPM#1
R72 X_0R0402R72 X_0R0402
Kentsfield
CPU_BSEL015,16
CPU_BSEL115,16
CPU_BSEL215,16
H_PWRGD6,12
H_CPURST#6,8
V_FSB_VTT
135
246
5
PECI16
VTIN116
X_1KR0402
X_1KR0402
R77 X_51R0402R77 X_51R0402
7
8
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
G5
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
DBI0#
DBI1#
DBI2#
DBI3#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
PECI
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
B15
C14
H_D#53
H_D#52
D52#
C15
H_D#51
H_A#9
U6
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D27#
D26#
D25#
D24#
F12
F11
E13
D13
G13
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_A#4
D23#
D22#
E10
D10
H_D#21
H_D#22
AC2
L5
DBR#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
H_D#17
H_D#18
H_D#19
H_D#20
AN6
AN5
AN4
AN3
VSS_SENSE
VCC_SENSE
VCC_MB_REGULATION
D14#
B12
D11
C12
H_D#13
H_D#14
H_D#15
H_D#16
AJ3
AK3
ITP_CLK1
ITP_CLK0
VSS_MB_REGULATION
D13#
D12#D8D11#
D10#
B10
C11
H_D#10
H_D#11
H_D#12
VID5
VID7
VID6
AM7
AM5
AL4
VID6
RSVD/VID7
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A11
A10
H_D#6
H_D#7
H_D#8
H_D#9
3
VID2
VID3
VID1
VID4
AK4
AL6
AM3
AL5
VID5
VID4
VID3
VID2
FC5/CPU_GTLREF2
RSVD/CPU_GTLREF3
H_D#2
H_D#3
H_D#4
H_D#5
VID[0..7] 30
VID0
AM2
VID1
VID0
VID_SELECT
GTLREF_SEL
H_D#1
AN7
H1
GTLREF0
H2
GTLREF1
H29
E24
GTLREF2
F2
G10
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
TESTHI12
P1
TESTHI11
H5
TESTHI10
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
FORCEPH
G6
RSVD#G6
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
ADSTB1#
R6
ADSTB0#
C17
DSTBP3#
G19
DSTBP2#
E12
DSTBP1#
B9
DSTBP0#
A16
DSTBN3#
G20
DSTBN2#
G12
DSTBN1#
C8
DSTBN0#
L1
LINT1/NMI
K1
LINT0/INTR
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
B4
H_D#0
VTT_OUT_RIGHT
R66
R66
1KR1%0402
1KR1%0402
CPU_GTLREF0
CPU_GTLREF1
CPU_GTLREF1
CPU_GTLREF0
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
FORCEPH
RSVD_G6
H_RS#2
H_RS#1
H_RS#0
TEST-U3
TEST-U2
H_COMP5
R92 X_49.9R1%0402R92 X_49.9R1%0402
H_COMP4
R96 X_49.9R1%0402R96 X_49.9R1%0402
H_COMP3
H_COMP2
H_COMP1
H_COMP0
R134 49.9R1%0402R134 49.9R1%0402
TEST-J17
TEST-H16
TEST-H15
TEST-J16
VSS_SENSE 30
T7T7
T12T12
R102 X_R/2R102 X_R/2
R107 X_0R0402R107 X_0R0402
Kentsfield
R128 51R0402R128 51R0402
R129 51R0402R129 51R0402
R70 X_130R1%0402R70 X_130R1%0402
R105 X_51R0402R105 X_51R0402
T3T3
T2T2
T4T4
T10T10
T6T6
T5T5
H_ADSTB#1 8
H_ADSTB#0 8
H_DSTBP#3 8
H_DSTBP#2 8
H_DSTBP#1 8
H_DSTBP#0 8
H_DSTBN#3 8
H_DSTBN#2 8
H_DSTBN#1 8
H_DSTBN#0 8
H_NMI 12
H_INTR 12
VTT_OUT_RIGHT 6,7
VID_SEL 30
CPU_GTLREF0 6
CPU_GTLREF1 6
H_BPM#0 7
H_REQ#[0..4] 8
H_TESTHI12 7
H_BPM#2H_TESTHI9
H_BPM#3
V_FSB_VTT
VTT_OUT_RIGHT
VTT_OUT_LEFT
CK_H_CPU# 15
CK_H_CPU 15
H_RS#[0..2] 8
VTT_OUT_LEFT
1
3
5
7
RN9 8P4R-49.9R1%-1RN9 8P4R-49.9R1%-1
2
2
4
6
8
V_FSB_VTT
H_BR#0 6,8
MSI
MSI
MSI
RN4
RN4
8P4R-680R0402-RH
VID5
VID4
VID2
VID0
VID7
VID3
VID6
VID1
H_BPM#1
H_BPM#0
H_BPM#5
H_BPM#3
H_TRST#
H_BPM#4
H_TDO
H_TCK
H_TDI
H_BPM#2
H_TMS
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI13
H_TESTHI8
H_TESTHI1
8P4R-680R0402-RH
1
3
5
7
1
3
5
7
RN5
RN5
8P4R-51R0402
8P4R-51R0402
1
3
5
7
RN6
RN6
8P4R-51R0402
8P4R-51R0402
1
3
5
7
RN7
RN7
8P4R-51R0402
8P4R-51R0402
1
3
5
7
RN11 8P4R-51R0402RN11 8P4R-51R0402
1
3
5
7
RN10 8P4R-51R0402RN10 8P4R-51R0402
1
3
5
7
C63
C63
X_C0.1u16Y0402
X_C0.1u16Y0402
H_TEST VTT_OUT_LEFT
VTT_OUT_RIGHT
2
4
6
8
RN3
RN3
8P4R-680R0402-RH
8P4R-680R0402-RH
2
4
6
8
VTT_OUT_RIGHT
2
4
6
8
2
4
6
8
2
4
6
8
VTT_OUT_LEFT
VTT_OUT_LEFT
2
4
6
8
2
4
6
8
VTT_OUT_LEFT 6
R108 X_51R0402R108 X_51R0402
C61
C61
C0.1u16Y0402
C0.1u16Y0402
Kentsfield
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7529
MS-7529
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
MS-7529
LGA775 - Signal
LGA775 - Signal
LGA775 - Signal
1
533
533
533
Sheet of
Sheet of
Sheet of
1.1
1.1
1.1
5
VCCP
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
CPU1B
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y29
Y28
Y27
Y26
Y25
Y24
Y23
W30
W29
W28
W27
W26
W25
W24
W23
VCCP
D D
C C
AG8
VCC
AG9
VCC
VCCU8VCCV8VCC
AH11
VCC
VCC
U30
AH12
VCC
VCC
U29
AH14
VCC
VCC
U28
AH15
VCC
VCC
U27
4
AH18
U26
VCC
VCC
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
U23
AH25
VCC
VCCT8VCC
AH26
VCC
VCC
T30
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
VCC
VCC
T27
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
3
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN8VCCP8VCCR8VCC
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
T23
N30
N23
N24
N25
N26
N27
N28
N29
M24
M25
M26
M27
M28
M29
M30
K27
K28
K29
K30
M23
K26
K25
K24
K23
J30
VCC
VCC
2
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J10
J11
J12
AN8
AN9
AN25
AN26
AN29
AN30
A23
B23
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
H_VCCA
H_VSSA
H_VCCPLL
H_VCCA
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
V_FSB_VTT
C10u10Y0805
C10u10Y0805
CAPS FOR FSB GENERIC
VTT_SEL 28
1
V_FSB_VTT
C126
C126
C123
X_C10u10Y0805
C123
X_C10u10Y0805
*GTLREF VOLTAGE SHOULD BE 0.67 * VTT = 0.8V (At VTT=1.2V)
R90
R87
R87
115R1%0402-RH
VTT_OUT_RIGHT
B B
VTT_OUT_RIGHT
115R1%0402-RH
R93
R93
115R1%0402-RH
115R1%0402-RH
GTL_REF0
R88
R88
200R1%0402
200R1%0402
GTL_REF1
R97
R97
200R1%0402
200R1%0402
R90
10R1%0402
10R1%0402
C57
C57
C1u16Y
C1u16Y
R98
R98
10R1%0402
10R1%0402
C66
C66
C1u16Y
C1u16Y
CPU_GTLREF0 5
C58
C58
X_C220p50N0402
X_C220p50N0402
CPU_GTLREF1 5
C68
C68
X_C220p50N0402
X_C220p50N0402
*PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
*TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MILS
V_FSB_VTT V_1P5_CORE
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
L3 X_10u100mA_0805-RHL3 X_10u100mA_0805-RH
21
CP2CP2
C102
C102
C1u16Y
C1u16Y
C105
C105
C10u10Y0805
C10u10Y0805
H_VCCA
C112
C112
X_C10u10Y0805
X_C10u10Y0805
H_VSSA
CP3CP3
H_VCCPLL
C120
C120
X_C1u16Y
X_C1u16Y
C124
C124
X_C10u10Y0805
X_C10u10Y0805
VTT_PWRGOOD
PLACE AT CPU END OF ROUTE
A A
VTT_OUT_RIGHT5,7
VTT_OUT_LEFT5
VTT_OUT_RIGHT H_PROCHOT#
VTT_OUT_LEFT
5
R83 130R1%0402R83 130R1%0402
R89 62R0402R89 62R0402
R103 62R0402R103 62R0402
R91 X_100R0402R91 X_100R0402
R106 62R0402R106 62R0402
H_IERR#
H_CPURST#
H_PWRGD
H_BR#0
H_PROCHOT# 5
H_IERR# 5
H_CPURST# 5,8
H_PWRGD 5,12
H_BR#0 5,8
4
VID_GD#28,30
3
VTT_OUT_RIGHT
R78 1KR0402R78 1KR0402
R73
R73
680R0402-RH
680R0402-RH
CE
B
Q12
Q12
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
2
VTT_PWG
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7529
MS-7529
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
LGA775 - Power
LGA775 - Power
LGA775 - Power
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
MS-7529
1
633
633
633
Sheet of
Sheet of
Sheet of
1.1
1.1
1.1
5
V30
V29
VSS
AG17
VSS
AG20
VSS
AG23
VSS
AG24
VSSV3VSS
VSS
AG7
AH1
VSS
V28
VSS
VSS
AH10
CPU1C
CPU1C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
1122334
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
4
AG10
AG13
AG16
A12
A15
D D
C C
B B
A18
A21
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE5
AE7
AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29
AF3
AF30
AF6
AF7
A2
A6
A9
V27
VSS
VSS
AH13
V26
VSS
VSS
AH16
V25
VSS
VSS
AH17
V24
VSS
VSS
AH20
V23
VSS
VSS
AH23
4
U7
VSS
VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
AH3
AH6
AH7
AH24
3
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
R30
R29
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
VSS
AK28
VSS
AK29
VSS
AK30
AK5
VSS
AK7
VSS
VSS
AL10
L30
VSS
AL13
VSSL3VSS
VSS
AL16
L29
VSS
AL17
L28
VSS
VSS
AL20
L27
VSS
VSS
AL23
L26
VSS
VSS
AL24
L25
VSS
VSS
AL27
L24
VSS
VSS
AL28
L23
AL7
VSS
VSS
VSSK7VSS
VSS
AM1
K2
K5
VSS
VSS
VSS
AM10
AM13
AM16
H28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN1
AN2
AM4
AN10
AN13
AN16
AN17
AN20
AN23
AN24
AM17
AM20
AM23
AM24
AM27
AM28
AN27
VSS
VSS
H17
VSS
VSS
AN28
H14
VSS
VSSB1VSS
H13
B11
VSS
H12
VSS
VSS
B14
2
F7
H10
H11
VSS
VSS
VSS
COMP6
COMP7
RSVD/COMP8
RSVD#AE4
RSVD#D1
RSVD#D14
RSVD#E5
RSVD#E6
RSVD#E7
RSVD#E23
RSVD#F23
RSVD#J3
RSVD#N4
RSVD#P5
RSVD#AC4
IMPSEL#
MSID1
MSID0
VSS
VSS
VSS
B17
B20
B24
RSVD
FC28
FC27
FC26
FC23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Y3
AE3
B13
AE4
D1
D14
E5
E6
E7
E23
F23
AL3
J3
N4
P5
AC4
F6
V1
W1
U1
G1
E29
A24
F4
F22
F19
F16
F13
F10
E8
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
H_COMP6
H_COMP7
H_COMP8
1505
1477
1497
R85 X_49.9R1%0402R85 X_49.9R1%0402
R84 X_49.9R1%0402R84 X_49.9R1%0402
R132 24.9R1%0402R132 24.9R1%0402
T11T11
T9T9
T8T8
TP_MPG_NOBOOT_N
RN8 8P4R-51R0402RN8 8P4R-51R0402
1
3
5
7
R122 X_0R0402R122 X_0R0402
R123 X_1KR0402R123 X_1KR0402
05 Per FMB
05 Value FMB
2
4
6
8
H_TESTHI12
H_BPM#0
T1T1
MSID1 MSID0
0
0
1
VTT_OUT_RIGHT 5,6
H_TESTHI12 5
H_BPM#0 5
Kentsfield
0
1
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
MLCC
VCCP
C83
C83
X_C10U6.3Y1206
X_C10U6.3Y1206
A A
5
VCCP
C80
C80
C10U6.3Y1206
C10U6.3Y1206
4
(Place into CPU Socket Cavity)
C74
C84
C84
C10U6.3Y1206
C10U6.3Y1206
C76
C76
C10U6.3Y1206
C10U6.3Y1206
C74
X_C10U6.3Y1206
X_C10U6.3Y1206
C82
C82
X_C10U6.3Y1206
X_C10U6.3Y1206
C81
C81
C10U6.3Y1206
C10U6.3Y1206
C71
C71
C10U6.3Y1206
C10U6.3Y1206
ZIF-SOCK775-15U-IN,ZIF-SOCK775-15U-IN_TH
C85
C85
C10U6.3Y1206
C10U6.3Y1206
C73
C73
X_C10U6.3Y1206
X_C10U6.3Y1206
3
C72
C72
C10U6.3Y1206
C10U6.3Y1206
C75
C75
C10U6.3Y1206
C10U6.3Y1206
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7529
MS-7529
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
LGA775 - GND
LGA775 - GND
LGA775 - GND
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
2
Friday, May 16, 2008
MS-7529
1
733
733
733
Sheet of
Sheet of
Sheet of
1.1
1.1
1.1
5
NB1A
NB1A
J42
HA3#
L39
HA4#
J40
HA5#
L37
HA6#
L36
HA7#
K42
HA8#
N32
HA9#
N34
HA10#
M38
HA11#
N37
HA12#
M36
HA13#
R34
HA14#
N35
HA15#
N38
HA16#
U37
HA17#
N39
HA18#
R37
HA19#
P42
HA20#
R39
HA21#
V36
HA22#
R38
HA23#
U36
HA24#
U33
HA25#
R35
HA26#
V33
HA27#
V35
HA28#
Y34
HA29#
V42
HA30#
V38
HA31#
Y36
HA32#
Y38
HA33#
Y39
HA34#
AA37
HA35#
M34
HADSTB0#
U34
HADSTB1#
F40
HREQ0#
L35
HREQ1#
L38
HREQ2#
G43
HREQ3#
J37
HREQ4#
W40
HADS#
Y40
HTRDY#
W41
HDRDY#
T43
HDEFER#
Y43
HHITM#
U42
HHIT#
V41
HLOCK#
AA42
HBREQ0#
W42
HBNR#
G39
HBPRI#
U40
HDBSY#
U41
HRS0#
AA41
HRS1#
U39
HRS2#
R32
HCLKP
U32
HCLKN
AM17
PWROK
C31
HCPURST#
AM18
RSTIN#
J13
ICH_SYNC#
D23
HRCOMP
C25
HSCOMP
D25
HSCOMP#
B25
HSWING
D24
HDVREF
B24
HACCVREF
V_1P25_CORE
R159 49.9R1%0402R159 49.9R1%0402
R167 49.9R1%0402R167 49.9R1%0402
R283
R283
C158
C158
C0.01U/25X/2
C0.01U/25X/2
H_A#[3..35]
H_RS#[0..2]
5
H_ADSTB#05
H_ADSTB#15
H_REQ#[0..4]
H_ADS#5
H_TRDY#5
H_DRDY#5
H_DEFER#5
H_HITM#5
H_HIT#5
H_LOCK#5
H_BR#05,6
H_BNR#5
H_BPRI#5
ICH_SYNC#_R
16.5R/1%/2
16.5R/1%/2
C271
X_C22P50N0402
C271
X_C22P50N0402
HXSWING
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_DBSY#5
CK_H_MCH15
CK_H_MCH#15
CHIP_PWGD10,13,28
H_CPURST#5,6
PLTRST#10,12,16
R175
R175
H_RS#0
H_RS#1
H_RS#2
PLTRST#
HXRCOMP
HXSCOMP
HXSCOMPB
HXSWING
MCH_GTLREF
V_FSB_VTT
V_FSB_VTT
H_A#[3..35]5
D D
C C
H_REQ#[0..4]5
H_RS#[0..2]5
Place the Pull-up R close to ICH7
B B
ICH_SYNC#13
V_FSB_VTT
A A
VCC3
X_1KR0402
X_1KR0402
R281 0R0402R281 0R0402
HXSWING S/B 1/4*VTT +/- 2%
R156
R156
301R1%0402
301R1%0402
R163 49.9R1%0402R163 49.9R1%0402
R157
R157
100R/2
100R/2
P29
VTT
P27
AJ12
VTT
VCC
P26
VTT
VCC
AJ11
P24
AJ10
VTT
VCC
P23
AJ9
N29
VTT
VCC
AJ8
4
N26
N24
N23
M29
VTT
VTT
VTT
VTT
VTT
VCC
VCC
VCC
VCC
VCC
AJ7
AJ6
AJ5
AJ4
HXSCOMP
C154
C154
X_C2.7P/25N/2
X_C2.7P/25N/2
HXSCOMPB
C162
C162
X_C2.7P/25N/2
X_C2.7P/25N/2
4
3
AG19
AG18
AG17
AG15
AG14
AF26
AF25
AF24
AF22
AF20
AF18
AF17
AF15
AF14
AE27
AE26
AE25
AE23
AE21
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN9VCCN8VCCN6VCCN3VCCL6VCCJ6VCCJ3VCCJ2VCCG2VCC
N12
N11
AE19
M24
M23
L24
L23
K24
K23
J24
J23
H24
H23
G26
G24
G23
F26
F24
F23
E29
E27
E26
E23
D29
D28
D27
C30
C29
C27
B30
B29
B28
B27
A30
A28
R27
R26
R24
R23
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCY6VCC
VCC
VCC
VCCV9VCC
VCC
VCCU9VCCU6VCCU3VCC
AJ3
AJ2
AH4
AH2
AH1
AG13
AG12
AG11
AG10
AG9
AG8
AG7
AG6
AG5
AG4
AG3
AG2
AF13
AF12
AF11
AD24
AD22
AD20
AC25
AC23
AC21
AC19
AC13
AC6
AB24
AB22
AB20
AA25
AA23
AA21
AA19
AA13
AA3
Y24
Y22
Y20
Y13
V13
V12
V10
U13
U10
VCC
AE17
VCC
AD27
VCC
AD26
VCC
AD18
VCC
AD17
VCC
2
AD15
VCC
AD14
VCC
F11
AC27
AC26
VCC
VCC
VCCF9VCCD4VCC
AC17
VCC
C13
AC15
VCC
VCCC9VCC
AC14
VCC
P20
AB27
VCC
VCC
Y11
AB26
VCC
VCC
AG25
AB18
VCC
VCC
AG21
AB17
VCC
VCC
AG20
AA27
V_1P25_COREV_FSB_VTT
AA26
VCC
VCC
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
HDINV0#
HDINV1#
HDINV2#
HDINV3#
HDSTBP0#
HDSTBN0#
HDSTBP1#
HDSTBN1#
HDSTBP2#
HDSTBN2#
HDSTBP3#
HDSTBN3#
INTEL-LE82G31-A2-RH
INTEL-LE82G31-A2-RH
R40
P41
R41
N40
R42
M39
N41
N42
L41
J39
L42
J41
K41
G40
F41
F42
C42
D41
F38
G37
E42
E39
E37
C39
B39
G33
A37
F33
E35
K32
H32
B34
J31
F32
M31
E31
K31
G31
K29
F31
J29
F29
L27
K27
H26
L26
J26
M26
C33
C35
E41
B41
D42
C40
D35
B40
C38
D37
B33
D33
C34
B35
A32
D32
M40
J33
G29
E33
L40
M43
G35
H33
G27
H27
B38
D38
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_D#[0..63]5
H_DBI#[0..3]5
H_DSTBP#0 5
H_DSTBN#0 5
H_DSTBP#1 5
H_DSTBN#1 5
H_DSTBP#2 5
H_DSTBN#2 5
H_DSTBP#3 5
H_DSTBN#3 5
1
H_D#[0..63]
H_DBI#[0..3]
GTLREF VOLTAGE SHOULD BE 0.67*VTT=0.804V
V_FSB_VTT
V_FSB_VTT
R166 100R/2R166 100R/2
R170 51R0402R170 51R0402
R168
R168
200R1%0402
200R1%0402
C166
C166
C0.1U/16Y/2
C0.1U/16Y/2
3
MCH_GTLREF
C165
C165
X_C220P16X0402
X_C220P16X0402
C151
C151
X_C0.1U/16Y/2
X_C0.1U/16Y/2
C146
C146
C0.1U/16Y/2
C0.1U/16Y/2
2
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7529
MS-7529
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
G31 - CPU Signals
G31 - CPU Signals
G31 - CPU Signals
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
MS-7529
1
833
833
833
Sheet of
Sheet of
Sheet of
1.1
1.1
1.1
5
MEM_MB_DATA[0..63]19
MEM_MA_DATA[0..63]18
MEM_MA_ADD[0..14]18,20
MEM_MA0_CS_L[0..1]18,20
MEM_MB_DATA[0..63]
MEM_MA_DATA[0..63]
MEM_MA_ADD[0..14]
MEM_MA0_CS_L[0..1]
MEM_MB_DM[0..7]19
MEM_MA_DM[0..7]18
MEM_MB_ADD[0..14]19,20
MEM_MB_DM[0..7]
MEM_MA_DM[0..7]
MEM_MB_ADD[0..14]
4
MEM_MA_DQS_H[0..7]18
MEM_MA_DQS_L[0..7]18
MEM_MA_DQS_L[0..7]
3
MEM_MB_DQS_H[0..7]19
MEM_MB_DQS_L[0..7]19
MEM_MB_DQS_H[0..7]MEM_MA_DQS_H0[0..7]
MEM_MB_DQS_L[0..7]
MEM_MB_CKE0
MEM_MB_CKE1
2
MEM_MB0_CS_L[0..1]
1
MEM_MB_CKE[0..1] 19,20
MEM_MB0_CS_L[0..1] 19,20
D D
NB1B
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA_RAS_L18,20
MEM_MA_CAS_L18,20
MEM_MA_WE_L18,20
C C
MEM_MA0_ODT[0..1]18,20
MEM_MA_BANK[0..2]18,20
MEM_MA0_CLK_H018
VCC_DDR
MEM_MA0_CLK_L018
MEM_MA0_CLK_H118
MEM_MA0_CLK_L118
MEM_MA0_CLK_H218
MEM_MA0_CLK_L218
R211 20R1%0402R211 20R1%0402
R210 20R1%0402R210 20R1%0402
R146 20R1%0402R146 20R1%0402
R145 20R1%0402R145 20R1%0402
C236
C236
C0.1U16Y0402
C0.1U16Y0402
B B
MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA0_ODT0
MEM_MA0_ODT1
MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
AW35
BA35
BA34
BB38
BB33
AY35
BB34
BA31
BB25
BA26
BA25
AY25
BA23
AY24
AY23
BB23
BA22
AY33
BB22
AW21
AY38
BA21
AY37
BA38
BB35
BA39
BA33
AW32
BB21
AU4
AR3
BB3
BA4
BB9
BA9
AT20
AU18
AR41
AR40
AL41
AL40
AG42
AG41
AC42
AC41
AU31
AR31
AP27
AN27
AV33
AW33
AP29
AP31
AM26
AM27
AT33
AU33
AN2
AN3
BB40
BA40
NB1B
SCS_A0#
SCS_A1#
Reserved18
Reserved24
SRAS_A#
SCAS_A#
SWE_A#
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_A14
SODT_A0
SODT_A1
Reserved23
Reserved19
SBS_A0
SBS_A1
SBS_A2
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
Reserved3
Reserved4
Reserved1
Reserved2
Reserved5
Reserved6
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
MEM_MB_DATA0
MEM_MB_DATA1
AN7
AN8
SDQ_B0
SDQ_A0
AR5
AR4
MEM_MB_DATA3
MEM_MB_DATA2
AW5
AW7
SDQ_B1
SDQ_B2
SDQ_A1
SDQ_A2
AV3
AV2
MEM_MB_DATA4
MEM_MB_DATA5
AN5
AN6
SDQ_B3
SDQ_B4
SDQ_A3
SDQ_A4
AP3
AP2
MEM_MB_DATA7
MEM_MB_DATA6
AN9
AU7
SDQ_B5
SDQ_B6
SDQ_A5
SDQ_A6
AV4
AU1
MEM_MB_DATA8
MEM_MB_DATA9
AT11
AU11
SDQ_B7
SDQ_B8
SDQ_A7
SDQ_A8
AY2
AY3
MEM_MB_DATA10
MEM_MB_DATA11
AP13
AR13
SDQ_B9
SDQ_B10
SDQ_A9
SDQ_A10
BB5
AY6
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
AR11
AU9
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_A11
SDQ_A12
SDQ_A13
AW2
AW3
MEM_MB_DATA15
MEM_MB_DATA16
AV12
AU12
SDQ_B14
SDQ_B15
SDQ_A14
SDQ_A15
BA5
BB4
MEM_MB_DATA18
MEM_MB_DATA17
AU15
AV13
SDQ_B16
SDQ_B17
SDQ_A16
SDQ_A17
AY7
BC7
MEM_MB_DATA19
MEM_MB_DATA20
AU17
AT17
AU13
SDQ_B18
SDQ_B19
SDQ_A18
SDQ_A19
BB6
AY11
AW11
MEM_MB_DATA23
MEM_MB_DATA21
MEM_MB_DATA22
AM13
AV15
SDQ_B20
SDQ_B21
SDQ_B22
SDQ_A20
SDQ_A21
SDQ_A22
BA6
BA10
MEM_MB_DATA25
MEM_MB_DATA24
AW17
AV24
AT23
SDQ_B23
SDQ_B24
SDQ_A23
SDQ_A24
AT18
BB10
AR18
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA28
AT26
AP26
SDQ_B25
SDQ_B26
SDQ_B27
SDQ_A25
SDQ_A26
SDQ_A27
AT21
AU21
MEM_MB_DATA29
MEM_MB_DATA30
AU23
AW23
AR24
SDQ_B28
SDQ_B29
SDQ_A28
SDQ_A29
AP17
AP20
AN17
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
AN26
AW37
SDQ_B30
SDQ_B31
SDQ_B32
SDQ_A30
SDQ_A31
SDQ_A32
AV20
AV42
MEM_MB_DATA34
MEM_MB_DATA35
AV38
AN36
AN37
SDQ_B33
SDQ_B34
SDQ_A33
SDQ_A34
AP42
AU40
AN39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
AU35
AR35
SDQ_B35
SDQ_B36
SDQ_B37
SDQ_A35
SDQ_A36
SDQ_A37
AV40
AV41
MEM_MB_DATA40
MEM_MB_DATA39
AN35
AR37
AM35
SDQ_B38
SDQ_B39
SDQ_A38
SDQ_A39
AP41
AR42
AN41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA41
AM38
AJ34
SDQ_B40
SDQ_B41
SDQ_B42
SDQ_A40
SDQ_A41
SDQ_A42
AK42
AM39
MEM_MB_DATA45
MEM_MB_DATA44
AL38
AR39
SDQ_B43
SDQ_B44
SDQ_A43
SDQ_A44
AK41
AN40
MEM_MB_DATA47
MEM_MB_DATA46
AM34
AL37
AL32
SDQ_B45
SDQ_B46
SDQ_A45
SDQ_A46
AL42
AL39
AN42
MEM_MB_DATA50
MEM_MB_DATA48
MEM_MB_DATA49
AG38
AJ38
SDQ_B47
SDQ_B48
SDQ_B49
SDQ_A47
SDQ_A48
SDQ_A49
AJ40
AH43
MEM_MB_DATA51
MEM_MB_DATA52
AF35
AF33
AJ37
SDQ_B50
SDQ_B51
SDQ_A50
SDQ_A51
AJ42
AF39
AE40
MEM_MB_DATA55
MEM_MB_DATA53
MEM_MB_DATA54
AJ35
AG33
SDQ_B52
SDQ_B53
SDQ_B54
SDQ_A52
SDQ_A53
SDQ_A54
AJ41
AF41
MEM_MB_DATA57
MEM_MB_DATA56
AF34
AD36
AC33
SDQ_B55
SDQ_B56
SDQ_A55
SDQ_A56
AF42
AD40
AD43
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA58
AA34
AA36
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_A57
SDQ_A58
SDQ_A59
AB41
AA40
MEM_MB_DATA62
MEM_MB_DATA61
AD34
AF38
AC34
SDQ_B60
SDQ_B61
SDQ_A60
SDQ_A61
AE42
AE41
AC39
MEM_MB_DATA63
AA33
SDQ_B62
SDQ_B63
SDQ_A62
SDQ_A63
AB42
AY12
AW12
SCKE_B0
SCKE_B1
SCKE_A0
SCKE_A1
AY20
BC20
BB11
Reserved20
Reserved13
AY21
BA11
Reserved16
Reserved17
BA19
MEM_MB_DM3
MEM_MB_DM1
MEM_MB_DM0
AR7
SDM_B0
SDM_A0
AR2
AW9
BA2
SDM_B1
SDM_A1
MEM_MB_DM2
AW13
SDM_B2
SDM_A2
AY9
MEM_MB_DM4
AP23
SDM_B3
SDM_A3
AN18
AU37
SDM_B4
SDM_A4
AU43
MEM_MB_DM5
AM37
AM43
MEM_MB_DM6
AG39
SDM_B5
SDM_A5
AG40
SDM_B6
SDM_A6
MEM_MB_DM7
AD38
SDM_B7
SDM_A7
AC40
SCS_B0#
SCS_B1#
Reserved14
Reserved15
SRAS_B#
SCAS_B#
SWE_B#
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SMA_B14
SODT_B0
SODT_B1
Reserved21
Reserved22
SBS_B0
SBS_B1
SBS_B2
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
Reserved7
Reserved8
Reserved9
Reserved10
Reserved11
Reserved12
SVREF
SMRCOMPVOL
SMRCOMPVOH
BB27
BB30
AY27
AY31
AW26
AW29
BA27
BB17
AY17
BA17
BC16
AW15
BA15
BB15
BA14
AY15
BB14
AW18
BB13
BA13
AY29
AY13
BA29
BA30
BB29
BB31
AY19
BA18
BC12
MEM_MB_DQS_H0
AV6
MEM_MB_DQS_L0
AU5
AR12
AP12
AP15
AR15
AT24
AU26
AW39
AU39
AL35
AL34
AG35
AG36
AC36
AC37
MEM_MB0_CLK_H0
AV31
MEM_MB0_CLK_L0
AW31
MEM_MB0_CLK_H1
AU27
MEM_MB0_CLK_L1
AT27
MEM_MB0_CLK_H2
AV32
MEM_MB0_CLK_L2
AT32
AU29
AR29
AV29
AW27
AN33
AP32
MCH_VREF_A
AM6
AM8
DDR_RCOMPVOH
AM10
MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB0_ODT0
MEM_MB0_ODT1
MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
DDR_RCOMPVOL
MEM_MB_RAS_L 19,20
MEM_MB_CAS_L 19,20
MEM_MB_WE_L 19,20
MEM_MB0_CLK_H0 19
MEM_MB0_CLK_L0 19
MEM_MB0_CLK_H1 19
MEM_MB0_CLK_L1 19
MEM_MB0_CLK_H2 19
MEM_MB0_CLK_L2 19
C251 C0.01U25X0402C251 C0.01U25X0402
R231 1KR1%0402R231 1KR1%0402
R228
R228
3.01KR1%0402
3.01KR1%0402
R230 1KR1%0402R230 1KR1%0402
C252
C0.01U25X0402
C252
C0.01U25X0402
MEM_MB0_ODT[0..1] 19,20
MEM_MB_BANK[0..2] 19,20
R216
R216
1KR1%0402
1KR1%0402
C213
C0.1U16Y0402
C213
C0.1U16Y0402
1KR1%0402
1KR1%0402
VCC_DDR
C241
C0.1U16Y0402
C241
C0.1U16Y0402
R218
R218
VCC_DDR
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM0
MEM_MA_DATA8
MEM_MA_DATA2
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA0
MEM_MA_DATA5
MEM_MA_DATA7
MEM_MA_DATA1
MEM_MA_DATA6
MEM_MA_DATA9
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA10
MEM_MA_DATA12
A A
5
MEM_MA_DATA11
MEM_MA_DATA18
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA15
4
MEM_MA_DATA25
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA29
MEM_MA_DATA26
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA36
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA38
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA35
MEM_MA_DATA40
MEM_MA_DATA37
MEM_MA_DATA39
MEM_MA_DATA41
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA42
MEM_MA_DATA47
MEM_MA_DATA45
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA46
3
MEM_MA_DATA56
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA53
MEM_MA_DATA50
MEM_MA_DATA60
MEM_MA_DATA58
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA59
MEM_MA_DATA57
PLACE 0.1UF CAP CLOSE TO MCH
MEM_MA_CKE1
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_CKE0
MEM_MA_DM7
MEM_MA_CKE[0..1] 18,20
2
DDR_RCOMPVOH = 0.8 * VCC_DDR
DDR_RCOMPVOL = 0.2 * VCC_DDR
INTEL-LE82G31-A2-RH
INTEL-LE82G31-A2-RH
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7529
MS-7529
MS-7529
G31 - Memory Signals
G31 - Memory Signals
G31 - Memory Signals
1
933
933
933
Sheet of
Sheet of
Sheet of
1.1
1.1
1.1
V_1P25_CORE
Close to MCH A.S.A.P
R221 5.1KR0402R221 5.1KR0402
R222 5.1KR0402R222 5.1KR0402
R226 5.1KR0402R226 5.1KR0402
R227 5.1KR0402R227 5.1KR0402
EXP_EN: PCI Express* SDVO
Concurrent Select
0: Only SDVO or PCI-E Operational
1: SDVO and PCI-E operating
simultaneously via PCI Express-G
port
D D
EXP_SLR: PCI Express
Static Lane Reversal
0: BTX 1: ATX
V_1P25_CORE
VCC3
R177
R177
R189
R189
1KR0402
1KR0402
X_1KR0402
X_1KR0402
EXP_EN_HDR
R190
R190
X_1KR0402
X_1KR0402
C C
RN27
RN27
V_FSB_VTT
8P4R-470R0402
8P4R-470R0402
MCH_BSEL1
7
8
MCH_BSEL2
5
6
MCH_BSEL0
3
4
1
2
V_1P25_CORE
Route solder side
4mils width
B B
V_1P5_MCH
R176 0R0402R176 0R0402
R174 0R0402R174 0R0402
V_1P25_CORE
I = 225mA
V_1P25_CORE
A A
I = 90.6mA
V_1P25_CORE
5
DMI_ITP_MRP_0
DMI_ITP_MRP_1
DMI_ITP_MRP_2
DMI_ITP_MRP_3
EXP_A_RXP_022
EXP_A_RXN_022
EXP_A_RXP_122
EXP_A_RXN_122
EXP_A_RXP_222
EXP_A_RXN_222
EXP_A_RXP_322
EXP_A_RXN_322
EXP_A_RXP_422
EXP_A_RXN_422
EXP_A_RXP_522
EXP_A_RXN_522
EXP_A_RXP_622
EXP_A_RXN_622
EXP_A_RXP_722
EXP_A_RXN_722
EXP_A_RXP_822
EXP_A_RXN_822
EXP_A_RXP_922
EXP_A_RXN_922
EXP_SLR
CK_PE_100M_MCH15
CK_PE_100M_MCH#15
SDVOCTRLDATA22
L7 X_0.1U50mL7 X_0.1U50m
CP5CP5
L10 X_0.1U50mL10 X_0.1U50m
CP8CP8
EXP_A_RXP_1022
EXP_A_RXN_1022
EXP_A_RXP_1122
EXP_A_RXN_1122
EXP_A_RXP_1222
EXP_A_RXN_1222
EXP_A_RXP_1322
EXP_A_RXN_1322
EXP_A_RXP_1422
EXP_A_RXN_1422
EXP_A_RXP_1522
EXP_A_RXN_1522
DMI_ITP_MRP_012
DMI_ITN_MRN_012
DMI_ITP_MRP_112
DMI_ITN_MRN_112
DMI_ITP_MRP_212
DMI_ITN_MRN_212
DMI_ITP_MRP_312
DMI_ITN_MRN_312
SDVOCTRLCLK22 VSYNC 27
EXP_EN_HDR22
R364 X_0RR364 X_0R
CP28CP28
C175
X_C0.1U16Y0402
C175
X_C0.1U16Y0402
C179
C0.01U25X0402
C179
C0.01U25X0402
21
C156
C156
X_C0.22U16X
X_C0.22U16X
21
C171
C171
X_C10U10Y0805
X_C10U10Y0805
5
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
SDVOCTRLDATA
SDVOCTRLCLK
MCH_BSEL016
MCH_BSEL116
MCH_BSEL216
EXP_SLR
EXP_EN_HDR
VCC_CL_PLL
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
V_3P3_DAC
VCCD_CRT
VCCDQ_CRT
C178
X_C0.1U16Y0402
C178
X_C0.1U16Y0402
C180
C4.7U10Y0805
C180
C4.7U10Y0805
VCC3
L16 X_80L4_30_1206L16 X_80L4_30_1206
21
CP12CP12
CP13CP13
VCCA_MPLL
C155
C155
X_C10U10Y0805
X_C10U10Y0805
VCCA_DPLLB
C176
C176
C0.1U16Y0402
C0.1U16Y0402
V_1P25_CORE
NB1C
NB1C
F15
EXP_RXP0
G15
EXP_RXN0
K15
EXP_RXP1
J15
EXP_RXN1
F12
EXP_RXP2
E12
EXP_RXN2
J12
EXP_RXP3
H12
EXP_RXN3
J11
EXP_RXP4
H11
EXP_RXN4
F7
EXP_RXP5
E7
EXP_RXN5
E5
EXP_RXP6
F6
EXP_RXN6
C2
EXP_RXP7
D2
EXP_RXN7
G6
EXP_RXP8
G5
EXP_RXN8
L9
EXP_RXP9
L8
EXP_RXN9
M8
EXP_RXP10
M9
EXP_RXN10
M4
EXP_RXP11
L4
EXP_RXN11
M5
EXP_RXP12
M6
EXP_RXN12
R9
EXP_RXP13
R10
EXP_RXN13
T4
EXP_RXP14
R4
EXP_RXN14
R6
EXP_RXP15
R7
EXP_RXN15
W2
DMI_RXP0
V1
DMI_RXN0
Y8
DMI_RXP1
Y9
DMI_RXN1
AA7
DMI_RXP2
AA6
DMI_RXN2
AB3
DMI_RXP3
AA4
DMI_RXN3
B12
GCLKP
B13
GCLKN
G17
SDVO_CTRLDATA
E17
SDVO_CTRLCLK
G20
BSEL0
J20
BSEL1
J18
BSEL2
G18
RESERVED53
E18
EXP_SLR
J17
EXP_EN
Y32
VCC2
C23
VCCA_HPLL
A24
VCCA_MPLL
A22
VCCA_DPLLA
C22
VCCA_DPLLB
B15
VCCA_EXPPLL
C17
VCCA_DAC
B16
VCCA_DAC
A16
VCCA_EXP
C21
VCCD_CRT
B21
VCCDQ_CRT
D16
VSS
B17
VCC3_3
V_1P25_EXP
C160
C0.1U16Y0402
C160
C0.1U16Y0402
AD11
C249
C10U10Y0805
C249
C10U10Y0805
AL26
VCC2
VCC_EXP
VCC_EXP
AD10
C0.1U16Y0402
C0.1U16Y0402
AL24
AL23
AL21
AL20
AL18
AL17
VCC2
VCC2
VCC2
VCC2
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AD9
AD8
AD7
AD6
AD5
AD4
C243
C243
I = 90.6mA
V_1P25_CORE
I = 67.9mA
V_1P25_CORE
4
AL15
AK30
AK29
AK27
AJ31
AG31
AF31
AD32
AC32
AA32
AJ30
AJ29
AJ27
AG30
AG29
AG27
AG26
AF30
AF29
AF27
AD30
AD29
AC30
AC29
AL12
AL11
AL10
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
AE4
AE3
AD2
AD1
4
AE2
AC4
AC3
AC2
BC39
VCC_DDR VCC_DDR
L9 X_0.1U50mL9 X_0.1U50m
CP7CP7
C167
C167
X_C10U10Y0805
X_C10U10Y0805
L8 X_0.1U50mL8 X_0.1U50m
CP6CP6
C161
C161
X_C10U10Y0805
X_C10U10Y0805
BC34
BC30
21
21
BC26
BC22
BB39
BB37
BC18
BC14
VCCA_DPLLA
C169
C169
C0.1U16Y0402
C0.1U16Y0402
VCCA_HPLL
C170
C170
C0.1U16Y0402
C0.1U16Y0402
BB32
BB28
BB26
BB24
BB20
BB18
I = 71.6mA
I = 0.36mA
BB16
BB12
AY32
V_1P25_CORE
VCC3
3
AL9
AL8
AL7
AL6
AL5
AL4
AL3
AL2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCCSM
VCCSM
VCCSM
VCCSM
VCC_SMCLK
AV26
AV18
BB41
AW24
BA42
AW20
C140 C1U16YC140 C1U16Y
L13 X_0.1U50mL13 X_0.1U50m
CP10CP10
C194
C194
X_C10U10Y0805
X_C10U10Y0805
L11 X_0.1U50mL11 X_0.1U50m
CP9CP9
C186
C186
C10U10Y0805
C10U10Y0805
3
AK26
VCC2
VCC_SMCLK
AY42
AK24
AK23
AK21
AK20
AK18
AK17
AK15
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC_SMCLK
VCC_SMCLK
VCC_SMCLK
RESERVED25
RESERVED26
RESERVED27
H18
BB42
BA43
BB19
AN21
L6 X_10U100m_0805L6 X_10U100m_0805
V_CKDDR
R144 X_1R1%R144 X_1R1%
R142 X_1R1%R142 X_1R1%
21
21
V_3P3_DAC
C187
C187
C0.1U16Y0402
C0.1U16Y0402
AK3
AK2
AK1
AJ13
VCC2
VCC2
VCC2
VCC2
RESERVED28
RESERVED29
RESERVED30
RESERVED31
BB2
AN32
AM31
AW42
21
VCCA_GPLL
C193
C193
C0.1U16Y0402
C0.1U16Y0402
AD31
AC31
AA31
Y31
AJ26
AJ24
AJ23
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
RESERVED32
RESERVED33
RESERVED34
RESERVED35
RESERVED36
RESERVED37
AA9
AJ32
AL31
AF32
AA10
AG32
AM21
CP4CP4
C137 X_C10U10Y0805C137 X_C10U10Y0805
C188
C188
C0.01U25X0402
C0.01U25X0402
AJ21
VCC2
VCC2
RESERVED38
RESERVED39
AA11
AJ20
AJ18
AJ17
AJ15
VCC2
VCC2
VCC2
VCC2
RESERVED40
RESERVED41
RESERVED42
RESERVED43
Y12
U30
U31
R29
AJ14
AA30
AA29
Y30
VCC2
VCC2
VCC2
VCC2
RESERVED44
RESERVED45
RESERVED46
RESERVED47
R30
U12
U11
R12
2
Y29
V30
V29
U29
U27
VCC2
VCC2
VCC2
VCC2
RESERVED48
RESERVED49
RESERVED50
RESERVED51
F13
V31
R13
AP21
AA39
T17T17
2
AL13
AK14
AL29
AL27
VCC2
VCC2
VCC2
VCC2
VCC2
RESERVED52
TEST0
TEST1
BC1
BC43
T13T13
T19T19
EXP_TXN0
EXP_TXN1
EXP_TXN2
EXP_TXN3
EXP_TXN4
EXP_TXN5
EXP_TXN6
EXP_TXN7
EXP_TXN8
EXP_TXN9
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_TXP13
EXP_TXN13
EXP_TXP14
EXP_TXN14
EXP_TXP15
EXP_TXN15
EXP_COMPO
EXP_COMPI
DDC_DATA
DREFCLKP
DREFCLKN
V_1P25_PLTRST#
RESERVED54
RESERVED55
RESERVED56
TEST2
INTEL-LE82G31-A2-RH
INTEL-LE82G31-A2-RH
A43
T14T14
EXP_TXP0
EXP_TXP1
EXP_TXP2
EXP_TXP3
EXP_TXP4
EXP_TXP5
EXP_TXP6
EXP_TXP7
EXP_TXP8
EXP_TXP9
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
HSYNC
VSYNC
RED
GREEN
BLUE
RED#
GREEN#
BLUE#
DDC_CLK
REFSET
PWROK2
VREF2
ALLZTEST
XORTEST
MSI
MSI
MSI
1
D11
D12
B11
A10
C10
D9
B9
B7
D7
D6
B5
B6
B3
B4
F2
E2
F4
G4
J4
K3
L2
K1
N2
M2
P3
N4
R2
P1
U2
T2
V3
U4
V7
V6
W4
Y4
AC8
AC9
Y2
AA2
AC11
AC12
C15
D15
B18
C19
B20
C18
D19
D20
L13
M13
C14
D13
A20
AM15
AA12
AM5
AD13
AD12
K20
F20
A14
DMI_MTP_0
DMI_MTN_0
DMI_MTP_1
DMI_MTN_1
DMI_MTP_2
DMI_MTN_2
DMI_MTP_3
DMI_MTN_3
GRCOMP
R208 24.9R1%0402R208 24.9R1%0402
HSYNC
VSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
MCH_DDC_DATA
MCH_DDC_CLK
CK_96M_DREF
CK_96M_DREF#
REFSET
R178 1.3KR1%0402R178 1.3KR1%0402
CHIP_PWGD
CL_RST#
CL_VREF_MCH
T16T16
T18T18
T15T15
R233
R233
1.65KR1%0402
1.65KR1%0402
R234
R234
1KR0402
1KR0402
C244 C0.1U16Y0402C244 C0.1U16Y0402
C245 C0.1U16Y0402C245 C0.1U16Y0402
C224 C0.1U16Y0402C224 C0.1U16Y0402
C225 C0.1U16Y0402C225 C0.1U16Y0402
C229 C0.1U16Y0402C229 C0.1U16Y0402
C228 C0.1U16Y0402C228 C0.1U16Y0402
C226 C0.1U16Y0402C226 C0.1U16Y0402
C227 C0.1U16Y0402C227 C0.1U16Y0402
PLTRST# 8,12,16
EXP_A_TXP_0 22
EXP_A_TXN_0 22
EXP_A_TXP_1 22
EXP_A_TXN_1 22
EXP_A_TXP_2 22
EXP_A_TXN_2 22
EXP_A_TXP_3 22
EXP_A_TXN_3 22
EXP_A_TXP_4 22
EXP_A_TXN_4 22
EXP_A_TXP_5 22
EXP_A_TXN_5 22
EXP_A_TXP_6 22
EXP_A_TXN_6 22
EXP_A_TXP_7 22
EXP_A_TXN_7 22
EXP_A_TXP_8 22
EXP_A_TXN_8 22
EXP_A_TXP_9 22
EXP_A_TXN_9 22
EXP_A_TXP_10 22
EXP_A_TXN_10 22
EXP_A_TXP_11 22
EXP_A_TXN_11 22
EXP_A_TXP_12 22
EXP_A_TXN_12 22
EXP_A_TXP_13 22
EXP_A_TXN_13 22
EXP_A_TXP_14 22
EXP_A_TXN_14 22
EXP_A_TXP_15 22
EXP_A_TXN_15 22
DMI_MTP_IRP_0 12
DMI_MTN_IRN_0 12
DMI_MTP_IRP_1 12
DMI_MTN_IRN_1 12
DMI_MTP_IRP_2 12
DMI_MTN_IRN_2 12
DMI_MTP_IRP_3 12
DMI_MTN_IRN_3 12
V_1P25_CORE
HSYNC 27
VGA_RED 27
VGA_GREEN 27
VGA_BLUE 27
MCH_DDC_DATA 27
MCH_DDC_CLK 27
CK_96M_DREF 15
CK_96M_DREF# 15
CHIP_PWGD 8,13,28
C264
C264
X_C10P50N0402
X_C10P50N0402
MCH CORE DECOUPLING
V_1P25_CORE
R236
R236
1KR0402
CL_RST# CL_VREF_MCH
C272
C272
X_C0.01U25X0402
X_C0.01U25X0402
1KR0402
R237
R237
392R1%0402
392R1%0402
C281
C281
C0.01U25X0402
C0.01U25X0402
CL_VREF_MCH = 0.352V (FOR NOW)
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7529
MS-7529
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
G31 PCI-Express & RBG Signals
G31 PCI-Express & RBG Signals
G31 PCI-Express & RBG Signals
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
Date:
Friday, May 16, 2008
MS-7529
1
10 33
10 33
10 33
Sheet of
Sheet of
Sheet of
1.1
1.1
1.1