MSI MS-7524 Schematics

5

4

3

2

1

MSI

D D

MS-7524 Ver:0A

CPU:

Core2 Duo, Wolfdale, Kentsfield and Yorkfield
processors in LGA775 Package.

System Chipset:

North Bridge - Intel Eagle Lake P45/G45
North Bridge - Intel ICH10

On Board Chipset:

Clock Gen - SLG8XP548

C C

LPC Super I/O - Fintek F71882F
LAN - Intel82567
Audio Codec - ALC888
1394 Controller - JMB381
SATA Controller - JMB363

Main Memory:

DDR 2*4(Max4GB)

Expansion Slots:

PCI EXPRESS X16 SLOT *1
PCI EXPRESS X1 SLOT *1

B B

PCI SLOT * 2

PWM:

Intersil ISL6333 (3 Phases)

A A

5

4

Title Page

Cover Sheet 1
Block Diagram
LGA775

Eaglelake - FSB, PCIE, DMI, VGA, MSIC

Eaglelake - Memory DDR2

Eaglelake - Power / GND

ICH10 - PCI, USB, DMI, PCIE
ICH10 - Host, DMI, SATA, SPI, RTC, MSIC

ICH10 - Power, GND
DDR2 Channel-A / Channel-B

Clock Gen. - IDTCV184
SIO - F71882F, PS2

SATA / FAN Control
LAN - Intel82567

Codec RTL888

PCIE x16 & x1

PCI Slot 1 & 2

JMB381
Marvell

USB Connectors

VGA & HDMI
System Power / ACPI
DDR2 / NB Core Power
ISL6333 3-Phases
ATX Connector / F_Panel
Manual & Option Parts

Power Delivery

Reset & Power OK Map

GPIO Setting / PCI Routing

Revise History

Intel Power Comsumption

3

2

2
3,4,5
6, 8, 9
7
10, 11
12
13, 14
15
16, 17
18
19, 20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C
Date: Sheet

Date: Sheet

Date: Sheet

Thursday, December 27, 2007

Thursday, December 27, 2007

Thursday, December 27, 2007

MICRO-START INT'L CO.,LTD.

Cover Sheet

Cover Sheet

Cover Sheet

of

142

of

142

of

1

142

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

4

3

2

1

Block Diagram

Board Stack-up

(1080 Prepreg Considerations)

VRD 11

D D

ISL6333
3-Phase PWM

PCI_E X16
Connector

Analog

Video Out

PCI EXPRESS X16

RGB

PCI_E x4

C C

PCI_E x1

SATA-II 0~4

PCI_E x4
(2 PCI_E x1 option)

SATA2

Intel LGA775 Processor

FSB 800/1066/1333

FSB

Eaglelake
G/P
GMCH

DMI

ICH10

DDRII

HD Audio Link

PCI_E x1

PCI

DDR3 800/1066

4 DDR III
DIMM
Modules

HD Audio Codec

ALC 888

1394

JMB381

LAN

PCI-E RTL8111C

J1394_2

J1394_1

Solder Mask

PREPREG 2.7mils

CORE 50mils

PREPREG 2.7mils

Solder Mask

Single End 50ohm Top/Bottom : 4mils
USB2.0 - 90ohm : 15/4.5/7.5/4.5/15
SATA - 95ohm : 15/4/8/4/15
LAN - 100ohm : 15/4/8/4/15
PCIE - 95ohm : 15/4/8/4/15
IEEE1394 - 110ohm : 15/4/9/4/15
IDE : 15/4/8/4/15

1.9mils Cu plus plating

1 oz. (1.2mils)
Cu Power
Plane

1 oz. (1.2mils)
Cu GND
Plane

1.9mils Cu plus plating

PCI Slot 1

USB Port 0~11

PCI_E to PATA

B B

SATA-II

IDE

USB2.0

PCI_E x1

LPC Bus

LPC SIO

Fintek

SPI

F71882

SPI

Flash ROM

A A

5

4

Keyboard

Mouse

Floopy

Serial

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, November 21, 2007

Date: Sheet of

Wednesday, November 21, 2007

Date: Sheet of

Wednesday, November 21, 2007

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

Block Diagram

Block Diagram

Block Diagram

of

242

242

1

242

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

4

3

2

1

VCC_SENSE

VCC_SENSE 34

CPU SIGNAL BLOCK

VSS_SENSE

VID2

VID1

AM3

AL5

VID2

VID1

H_D#2

H_D#3

VID0

AM2

VID0

VID_SELECT

GTLREF0
GTLREF1

GTLREF_SEL

GTLREF2

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI12
TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

FORCEPH

RSVD#G6

BCLK1#
BCLK0#

RS2#
RS1#
RS0#

AP1#
AP0#

BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0

DP3#

DP2#

DP1#

DP0#

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

LINT1/NMI

LINT0/INTR

B4

ZIF-SOCK775-GF

ZIF-SOCK775-GF

H_D#0

H_D#1

VID[0..7] 34

AN7
H1
H2
H29
E24
F2
G10

AG3
AF2
AG2
AD2
AJ1
AJ2

J6
K6
M6
J5
K4

W2
P1
H5
G4
G3
F24
G24
G26
G27
G25
F25
W3
F26
AK6
G6

G28
F28

A3
F5
B3

U3
U2
F3
T2
J2
R1
G2
T1
A13

J17
H16
H15
J16

AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1

H_A#[3..35]6

D D

U8A

U8A

H_DBI#0

H_DBI#[0..3]6

H_IERR#4

H_FERR#13

H_STPCLK#13

H_INIT#13

H_DBSY#6

H_DRDY#6

H_TRDY#6

H_ADS#6

H_LOCK#6

H_BNR#6

H_HIT#6
H_HITM#6
H_BPRI#6

H_DEFER#6

H_TDI
H_TDO
H_TMS
H_TRST#

GNDHM19

H_IGNNE#13

H_A20M#13

H_TESTHI138

H_BPM#1

H_PWRGD4,14

PECI13,19
VTIN119

H_TCK
PECI
VTIN1
GNDHM
H_TRMTRIP#

H_PROCHOT#
H_IGNNE#
ICH_H_SMI#
H_A20M#
H_TESTHI13

R80 X_0R/2R80 X_0R/2

R110 X_51R0402R110 X_51R0402

C C

H_TRMTRIP#13

H_PROCHOT#4

ICH_H_SMI#13

Kentsfield

CPU_BSEL018
CPU_BSEL118
CPU_BSEL218

H_CPURST#4,6

H_D#[0..63]6

B B

H_DBI#1
H_DBI#2
H_DBI#3

CPU_BSEL0
CPU_BSEL1
CPU_BSEL2

H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54

A8
G11
D19
C20

AB2
AB3

R3

M3
AD3

P3

H4

B2

C1

E3

D2

C3

C2

D4

E4

G8

G7
AD1

AF1
AC1
AG1
AE1

G5
AL1
AK1

M2
AE8
AL2

N2

P2

K3

L2

AH2

N5
AE6

C9
D16
A20

Y1

V2
AA2

G29
H30
G30

N1
G23

B22
A22
A19
B19
B21
C21
B18
A17
B16
C18

DBI0#
DBI1#
DBI2#
DBI3#

IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#

DBSY#
DRDY#
TRDY#

ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#

TDI
TDO
TMS
TRST#
TCK
PECI
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13

RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED4
RESERVED5

BOOTSELECT
LL_ID0
LL_ID1

BSEL0
BSEL1
BSEL2

PWRGOOD
RESET#

D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

H_A#31

H_A#28

H_A#29

H_A#30

H_A#27

H_A#24

H_A#25

H_A#26

H_A#22

H_A#21

H_A#23

H_A#18

H_A#17

H_A#20

H_A#19

A24#

D41#

H_A#16

AA5

AD6

AA4

AB6

A23#

A22#

A21#

A20#Y4A19#Y6A18#W6A17#

D40#

D39#

D38#

D37#

D36#

D35#

D34#

F18

F17

E19

E18

E16

E15

G17

G18

H_D#40

H_D#39

H_D#38

H_D#37

H_D#33

H_D#34

H_D#35

H_D#36

H_A#32

H_A#35

H_A#33

H_A#34

AJ6

AJ5

AH5

AH4

AG5

AG4

AG6

AF4

AF5

AB4

AC5

AB5

A35#

A34#

A33#

A32#

A31#

A30#

A29#

A28#

A27#

A26#

A25#

D53#

D52#

D51#

D50#

D49#

D48#

D47#

D46#

D45#

D44#

D43#

D42#

F21

B15

A14

C14

C15

D17

H_D#53

H_D#52

H_D#51

H_D#50

H_D#49

F20

E22

E21

D20

D22

G22

G21

H_D#45

H_D#44

H_D#43

H_D#42

H_D#41

H_D#48

H_D#47

H_D#46

H_A#10

H_A#15

H_A#11

H_A#12

H_A#13

H_A#14

A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#

D33#

D32#

D31#

D30#

D29#

D28#

F15

F14

G16

G15

G14

H_D#27

H_D#28

H_D#29

H_D#30

H_D#31

H_D#32

H_A#8

H_A#7

H_A#9

U6

A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#

D27#

D26#

D25#

E13

D13

G13

H_D#24

H_D#25

H_D#26

D24#

F12

H_A#5

H_A#6

D23#

F11

D10

H_D#22

H_D#23

H_A#3

H_A#4

L5

D22#

D21#

D20#D7D19#E9D18#F9D17#F8D16#G9D15#

E10

H_D#19

H_D#20

H_D#21

FP_RST#

AN4

AC2

AN3

AN6

AN5

DBR#

VSS_SENSE

VCC_SENSE

VSS_MB_REGULATION

VCC_MB_REGULATION

D14#

D13#

B12

D11

C12

H_D#12

H_D#13

H_D#14

H_D#15

H_D#16

H_D#17

H_D#18

AJ3

ITP_CLK1

D12#D8D11#

C11

H_D#11

AK3

B10

H_D#10

VID5

VID7

VID6

AM5

AL4

AM7

VID6

ITP_CLK0

RSVD/VID7

D10#

D9#

D8#

D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#

A11

A10

H_D#6

H_D#7

H_D#8

H_D#9

VID3

VID4

AK4

AL6

VID5

VID4

VID3

FC5/CPU_GTLREF2

RSVD/CPU_GTLREF3

H_D#4

H_D#5

VSS_SENSE 34

VTT_OUT_RIGHT

R52

R52
1KR1%/2

1KR1%/2

CPU_GTLREF0
CPU_GTLREF1
GTLREF_SEL
CPU_MCH_GTLREF
CPU_GTLREF2
CPU_GTLREF3

H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0

H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0

H_TESTHI12
DPSLP#
H_TESTHI10
H_TESTHI9
H_TESTHI8

H_TESTHI2_7
H_TESTHI1

H_TESTHI0
FORCEPH
RSVD_G6

CK_H_CPU_DN
CK_H_CPU_DP

H_RS#2
H_RS#1
H_RS#0

TEST-U3
TEST-U2

H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0

TEST-J17
TEST-H16
TEST-H15
TEST-J16

T9

R121 X_0R/2R121 X_0R/2
R156 X_0R/2R156 X_0R/2

R169 51R/2R169 51R/2
R170 51R/2R170 51R/2

R106 X_130R/2R106 X_130R/2
R130 X_51R/2R130 X_51R/2

X_TPT4X_TP

T4
T3 X_TPT3 X_TP

R133 49.9R1%/2R133 49.9R1%/2
R122 49.9R1%/2R122 49.9R1%/2
R143 49.9R1%/2R143 49.9R1%/2
R119 49.9R1%/2R119 49.9R1%/2
R177 49.9R1%/2R177 49.9R1%/2

T5 X_TPT5 X_TP

X_TPT7X_TP

T7

X_TPT8X_TP

T8

X_TPT6X_TP

T6

H_ADSTB#1 6
H_ADSTB#0 6
H_DSTBP#3 6
H_DSTBP#2 6
H_DSTBP#1 6
H_DSTBP#0 6
H_DSTBN#3 6
H_DSTBN#2 6
H_DSTBN#1 6
H_DSTBN#0 6
H_NMI 13
H_INTR 13

CPU_GTLREF0 4
CPU_GTLREF1 4

X_TPT9X_TP

CPU_MCH_GTLREF 6
CPU_GTLREF2 4
CPU_GTLREF3 4

H_BPM#0 5
H_REQ#[0..4] 6

H_TESTHI12 5
DPSLP# 14

H_BPM#2
H_BPM#3

Kentsfield

VTT_OUT_RIGHT
VTT_OUT_LEFT

CK_H_CPU_DN 18
CK_H_CPU_DP 18

H_RS#[0..2] 6

H_COMP5_R

VTT_OUT_LEFT

V_FSB_VTT

V_FSB_VTT

VTT_OUT_RIGHT 4,5,34

H_BR#0 4,6

C56

C56
C0.1U16Y2

C0.1U16Y2

H_COMP5_R 8,14
VTT_OUT_LEFT 4

PULL HIGHT PULL DOWN

FP_RST#

RN2 8P4R-680R0402-RHRN2 8P4R-680R0402-RH

VID2

1

VID0
VID5
VID4
VID7
VID3
VID6
VID1

H_BPM#0
H_BPM#1
H_BPM#5
H_BPM#3

H_TRST#
H_BPM#4
H_TDO
H_TCK

H_TDI
H_BPM#2
H_TMS

H_TESTHI12
H_TESTHI9

H_TESTHI10

DPSLP#

H_TESTHI8
H_TESTHI1
H_TESTHI13

H_COMP5_R VTT_OUT_LEFT

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

RN3 8P4R-680R0402-RHRN3 8P4R-680R0402-RH

1

2

3

4

5

6

7

8

RN1 8P4R-51R/2RN1 8P4R-51R/2

1

2

3

4

5

6

7

8

RN6 8P4R-51R/2RN6 8P4R-51R/2

1

2

3

4

5

6

7

8

RN7 8P4R-51R/2RN7 8P4R-51R/2

RN8 8P4R-51R/2RN8 8P4R-51R/2

1

2

3

4

5

6

7

8

R108 51R/2R108 51R/2
R153 51R/2R153 51R/2

R115 51R/2R115 51R/2
R135 51R/2R135 51R/2

R155 49.9R1%/2R155 49.9R1%/2

Thermal TRIP

VTT_OUT_RIGHT

FORCEPH

R41 X_0R/2R41 X_0R/2

H_PROCHOT#

R42 X_0R/2R42 X_0R/2

VTT_OUT_RIGHT

R39

R39
X_10KR/2

X_10KR/2

B

Q4
X_2N3904Q4X_2N3904

CE

FP_RST# 13,14,36

VTT_OUT_RIGHT

C13

C13

C0.1U16Y2

C0.1U16Y2

VTT_OUT_LEFT

C60

C60
C0.1U16Y2

C0.1U16Y2

VCC3

R48

R48
10KR/2

10KR/2

ICH_THERM# 14

C58

C58
C0.1U16Y2

C0.1U16Y2

THRM#19

A A

5

4

3

2

R49 0R/2R49 0R/2

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet

MICRO-START INT'L CO.,LTD.

LGA775 - Signal

LGA775 - Signal

LGA775 - Signal

of

342

342

1

342

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

VCCP

AF22

AF21

AF8

U8B

U8B

VCCP

R139

R139

R17

R17

AF19

VCC#AF19

AF18
AF15
AF14
AF12
AF11

AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11

AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23

AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23

AB8
AA8

Q6

Q6

D

D

G

G

S

S

VCC#AF22

VCC#AF21

VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8

VCC#Y30

VCC#Y8

Y8

Y29

Y30

VCCP

R150 10R/2R150 10R/2 R32 10R/2R32 10R/2

C71

C71
C1U16Y3

C1U16Y3

R30 10R/2R30 10R/2

C15

C15
C1U16Y3

C1U16Y3

R29

R29
270RST/4

270RST/4

D D

C C

CPU CPU_GTLREF1_SEL GTL VOLTAGE

KENTSFIELD FSB
OVERCLOCKING

ALL OTHER CPUS

B B

0 0.685 VTT

1 0.630 VTT

*GTLREF VOLTAGE SHOULD BE

0.67 * VTT = 0.8V (At VTT=1.2V)

VTT_OUT_RIGHT

VTT_OUT_RIGHT

CPU_GTLREF2_SEL19

R131 124R1%0402R131 124R1%0402

210R1%0402

210R1%0402

R16 124R1%0402R16 124R1%0402

X_953R1%0402-RH

X_953R1%0402-RH

X_N-2N7002_SOT23

X_N-2N7002_SOT23

AG11

AF9

VCC#AF9

VCC#AF8

VCC#AG11

VCC#Y27

VCC#Y28

VCC#Y29

Y27

Y28

C77

C77
C220P50N2

C220P50N2

C22

C22
C220P50N2

C220P50N2

AG14

AG12

VCC#AG14

VCC#AG12

VCC#Y25

VCC#Y26

Y25

Y26

4

AG21

AG19

AG18

AG15

VCC#AG21

VCC#AG19

VCC#AG18

VCC#AG15

VCC#W30

VCC#W8W8VCC#Y23

VCC#Y24

Y23

Y24

W30

CPU_GTLREF0 3

CPU_GTLREF1 3

AG25

AG22

VCC#AG22

VCC#W29

W28

W29

AG27

AG26

VCC#AG26

VCC#AG25

VCC#W27

VCC#W28

W26

W27

AG29

AG28

VCC#AG28

VCC#AG27

VCC#W25

VCC#W26

W24

W25

AG30

AG8

VCC#AG30

VCC#AG29

VCC#W24

W23

3

AL11

AL12

AL14

AL15

AL18

AL19

AL21

AL22

AL25

AL26

AL29

AK8

VCC#AK15

VCC#M28

AK18

VCC#AK18

VCC#M27

M27

AK19

AK21

VCC#AK19

VCC#AK21

VCC#M25

VCC#M26

M25

M26

C23

C23
C220P50N2

C220P50N2

C73

C73
C220P50N2

C220P50N2

AK22

M24

AK25

VCC#AK22

VCC#M24

M23

AK26

VCC#AK25

VCC#AK26

AK9

VCC#AK8

VCC#AK9

VCC#AL11

VCC#AL12

VCC#K28

VCC#K29

VCC#K30

VCC#K8K8VCC#L8L8VCC#M23

K27

K28

K29

K30

CPU_GTLREF2 3

CPU_GTLREF3 3

VCC#AL14

VCC#K27

K26

AH8

AG9

VCC#AG8

VCC#AG9

VCC#U8U8VCC#V8V8VCC#W23

CPU_GTLREF1_SEL19

AH11

VCC#AH11

VCC#U30

U30

AH12

U29

AH14

VCC#AH14

VCC#AH12

VCC#U28

VCC#U29

U28

AH15

VCC#AH15

VCC#U27

U27

AH22

AH21

AH19

AH18

VCC#AH21

VCC#AH19

VCC#AH18

VCC#U24

VCC#U25

VCC#U26

U23

U24

U25

U26

VTT_OUT_RIGHT

V_FSB_VTT

AH26

AH25

VCC#AH25

VCC#AH22

VCC#T8T8VCC#U23

T30

AH27

AH28

AH29

AH30

VCC#AH27

VCC#AH26

VCC#AH28

VCC#AH29

VCC#T27

VCC#T28

VCC#T29

VCC#T30

T26

T27

T28

T29

R18 124R1%0402R18 124R1%0402

X_953R1%0402-RH

X_953R1%0402-RH

X_N-2N7002_SOT23

X_N-2N7002_SOT23

R120 124R1%0402R120 124R1%0402

AH9

AJ11

VCC#AH8

VCC#AH9

VCC#AH30

VCC#T24

VCC#T25

VCC#T26

T23

T24

T25

210R1%0402

210R1%0402

AJ12

AJ14

VCC#AJ11

VCC#AJ12

R19

R19

R123

R123

AJ8

AJ9

AK11

AK12

AK14

AJ25

VCC#AJ22

VCC#AJ25

VCC#N26

VCC#N27

N26

AJ26

VCC#AJ8

VCC#AJ26

VCC#N24

VCC#N25

N24

N25

C16

C16
C1U16Y3

C1U16Y3

AK15

VCC#AJ9

VCC#AK11

VCC#AK12

VCC#AK14

VCC#M29

VCC#M30

VCC#M8M8VCC#N23

N23

M28

M29

M30

R31

R31
270RST/4

270RST/4

R144 10R/2R144 10R/2

C69

C69
C1U16Y3

C1U16Y3

AJ15

AJ18

AJ19

AJ21

AJ22

VCC#AJ14

VCC#AJ15

VCC#AJ18

VCC#AJ19

VCC#AJ21

VCC#N28

VCC#N29

VCC#N30

VCC#N8N8VCC#P8P8VCC#R8R8VCC#T23

N27

N28

N29

N30

Q7

Q7

D

D

G

G

S

S

AL30

AM11

AM12

AM14

AM15

AM18

AM19

AM21

AM22

AL8

AL9

VCC#AL8

VCC#AL15

VCC#AL18

VCC#AL19

VCC#K24

VCC#K25

VCC#K26

K24

K25

VCC#AL9

VCC#AL21

VCC#AL22

VCC#AL25

VCC#AL26

VCC#AL29

VCC#AL30

VCC#J26

VCC#J27

VCC#J28

VCC#J29

VCC#J30

VCC#J8J8VCC#J9J9VCC#K23

J25

J26

J27

J28

J29

J30

K23

AM25

VCC#AM11

VCC#AM12

VCC#AM14

VCC#AM15

VCC#AM18

VCC#AM19

VCC#AM21

VCC#AM22

VCC#J18

VCC#J19

VCC#J20

VCC#J21

VCC#J22

VCC#J23

VCC#J24

VCC#J25

J15

J18

J19

J20

J21

J22

J23

J24

*PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
*TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MILS

V_FSB_VTT V_1P5_ICH

2

AM26

AM29

AM30

AN11

AN12

AN14

AN15

AM8

AM9

VCC#AM8

VCC#AM9

VCC#AN11

VCC#AN12

VCC#AN14

VCC#AM25

VCC#AM26

VCC#J14

VCC#J15

J14

L2 X_L10U_100mA_0805L2 X_L10U_100mA_0805

X_COPPER

X_COPPER

VCC#AN15

VCC#AM29

VCC#AM30

VCC#AN29

VCC#AN30

VCC#AN8

VCC#AN9

VCC#J10

VCC#J11

VCC#J12

VCC#J13

J10

J11

J12

J13

AN8

AN9

AN29

AN30

CP3

CP3

AN18

AN19

AN21

AN22

VCCA
VSSA

VCC#AN18

VCC#AN19

VCC#AN21

VCC#AN22

VCCPLL

VCC-IOPLL

VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30

VTTPWRGD

VTT_OUT_RIGHT

VTT_OUT_LEFT

VTT_SEL

RSVD#F29

VCC#AN25

VCC#AN26

1122334

AN25

AN26

C138

C138
C1U16Y3

C1U16Y3

4

H_VCCA

A23

H_VSSA

B23

H_VCCPLL

D23

H_VCCA

C23

A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30

VTT_PWG

AM6

VTT_OUT_RIGHT

AA1

VTT_OUT_LEFT

J1

VTT_SEL

F27
F29

ZIF-SOCK775-GF

ZIF-SOCK775-GF

C135

C135
C10U10Y5

C10U10Y5

H_VCCA

C130

C130
X_C10U10Y5

X_C10U10Y5

H_VSSA

C10U10Y5

C10U10Y5

H_VCCPLL 10

V_FSB_VTT

C136

C136

C131

C131

C10U10Y5

C10U10Y5

CAPS FOR FSB GENERIC

VTT_SEL 32

CP4

CP4

X_COPPER

X_COPPER

V_FSB_VTT

C10U16X6

C10U16X6

C162

C162

H_VCCPLL

C149

C149
X_C1U16Y3

X_C1U16Y3

1

C154

C154

C158

C158

C10000P25X2

C10000P25X2

C10U10Y5

C10U10Y5

VTT_PWG SPEC :

R6
X_10KR/2R6X_10KR/2

X_P-MMBT3906LT1_SOT23Q1X_P-MMBT3906LT1_SOT23

High > 0.9V
Low < 0.3V
Trise < 150ns

R53

R53
0R0402-1

0R0402-1

VTT_PWG

R64

R64
X_2.2KR/2

X_2.2KR/2

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet

MICRO-START INT'L CO.,LTD.

LGA775 - Power

LGA775 - Power

LGA775 - Power

MS-7524M1

MS-7524M1

MS-7524M1

1

0A

0A

0A

of

442

442

442

PLACE AT CPU END OF ROUTE

C1U6.3Y2

C1U6.3Y2

3

3VSB

CE

B

C57

C57

VTT_OUT_RIGHT3,5,34

VTT_OUT_LEFT3

A A

VTT_OUT_RIGHT

VTT_OUT_LEFT

5

R72 130R1%/2R72 130R1%/2
R104 62R/2R104 62R/2
R89 62R/2R89 62R/2

R116 X_100R/2R116 X_100R/2
R157 62R/2R157 62R/2

H_PROCHOT#
H_IERR#
H_CPURST#

H_PWRGD
H_BR#0

H_PROCHOT# 3
H_IERR# 3
H_CPURST# 3,6

H_PWRGD 3,14
H_BR#0 3,6

R109

2.4KR0402

2.4KR0402

R109

R105

R105

22.1KR1%0402

22.1KR1%0402

V_FSB_VTT

4

R81

R81
10KR/2

10KR/2

Q14

Q14
2N3904

2N3904

VTT_PWRGOOD

VID_GD# 34

B

R73

R73
1KR1%/2

1KR1%/2

3VSB

CE

R57

R57
10KR/2

10KR/2

Q11

Q11
2N3904

2N3904

3VSB 3VSB

R21

R21
X_10KR/2

X_10KR/2

CE

Q8

B

X_2N3904Q8X_2N3904

2

Q1

CE

B

5

D D

U8C

U8C

Y2

W4

VSS#Y7Y7VSS#Y5Y5VSS#Y2

A12

VSS#A12

A15

VSS#A15

A18

VSS#A18

A2

VSS#A2

A21

VSS#A21

A6

VSS#A6

A9

VSS#A9

AA23

VSS#AA23

AA24

VSS#AA24

AA25

VSS#AA25

AA26

VSS#AA26

AA27

VSS#AA27

AA28

VSS#AA28

AA29

VSS#AA29

AA3

VSS#AA3

AA30

VSS#AA30

AA6

VSS#AA6

AA7

VSS#AA7

AB1

VSS#AB1

AB23

C C

B B

AB24
AB25
AB26
AB27
AB28
AB29
AB30

AE10
AE13
AE16
AE17

AE20
AE24
AE25
AE26
AE27
AE28
AE29
AE30

AF10
AF13
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29

AF30

VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30

AB7

VSS#AB7

AC3

VSS#AC3

AC6

VSS#AC6

AC7

VSS#AC7

AD4

VSS#AD4

AD7

VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17

AE2

VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
VSS#AE29
VSS#AE30

AE5

VSS#AE5

AE7

VSS#AE7
VSS#AF10
VSS#AF13
VSS#AF16
VSS#AF17
VSS#AF20
VSS#AF23
VSS#AF24
VSS#AF25
VSS#AF26
VSS#AF27
VSS#AF28
VSS#AF29

AF3

VSS#AF3
VSS#AF30

AF6

VSS#AF6

AF7

VSS#AF7

VSS#W7W7VSS#W4

VSS#AG10

VSS#AG13

VSS#AG16

VSS#AG17

AG10

AG13

AG16

AG17

AG20

VSS#V7V7VSS#V6

VSS#AG20

4

V30

V29

V28

V27

V26

V25

V24

V23

R30

R29

R28

R27

V6

V3

VSS#V3

VSS#V30

VSS#V29

VSS#V28

VSS#AG23

VSS#AG24

VSS#AG7

VSS#AH1

VSS#AH10

AH1

AG7

AH10

AH13

AG23

AG24

T3

U7

R5

VSS#T7T7VSS#T6T6VSS#T3

VSS#U7

VSS#V27

VSS#V26

VSS#AH13

VSS#AH16

AH16

VSS#R7R7VSS#R5

VSS#V25

VSS#V24

VSS#V23

VSS#R30

VSS#R29

VSS#R28

VSS#AH17

VSS#AH20

VSS#AH23

VSS#AH24

VSS#AH3

VSS#AH6

VSS#AH7

VSS#AJ10

VSS#AJ13

VSS#AJ16

VSS#AJ17

VSS#AJ20

AH3

AH6

AH7

AJ10

AJ13

AJ16

AJ17

AJ20

AH17

AH20

AH23

AH24

AJ23

P30

P29

P28

P27

P26

P25

P24

R26

R25

R24

R23

P4

R2

VSS#P7P7VSS#P4

VSS#R2

VSS#R27

VSS#R26

VSS#R25

VSS#R24

VSS#R23

VSS#AJ23

VSS#AJ24

VSS#AJ27

VSS#AJ28

VSS#AJ29

VSS#AJ30

VSS#AJ4

AJ4

AJ7

AJ24

AJ27

AJ28

AJ29

AJ30

P23

M1

N3

VSS#N7N7VSS#N6N6VSS#N3

VSS#P30

VSS#P29

VSS#P28

VSS#P27

VSS#AJ7

VSS#AK10

VSS#AK13

VSS#AK16

VSS#AK17

AK10

AK13

AK16

AK17

VSS#M7M7VSS#M1

VSS#P26

VSS#P25

VSS#P24

VSS#P23

VSS#AK2

VSS#AK20

VSS#AK23

VSS#AK24

VSS#AK27

VSS#AK28

VSS#AK29

VSS#AK30

VSS#AK5

AK2

AK5

AK20

AK23

AK24

AK27

AK28

AK29

AK30

3

L6

L3

L30

L29

L28

L27

VSS#L7L7VSS#L6

VSS#L3

VSS#L30

VSS#L29

VSS#L28

VSS#AK7

VSS#AL10

VSS#AL13

VSS#AL16

VSS#AL17

VSS#AL20

AK7

AL10

AL13

AL16

AL17

AL20

AL23

J7

L26

L25

L24

L23

K2

K5

VSS#K7K7VSS#K5

VSS#L27

VSS#L26

VSS#L25

VSS#L24

VSS#L23

VSS#AL23

VSS#AL24

VSS#AL27

VSS#AL28

VSS#AL7

VSS#AM1

VSS#AM10

AL7

AM1

AL24

AL27

AL28

AM10

AM13

H28

H9

VSS#J4J4VSS#J7

VSS#K2

VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9

VSS#AM13

VSS#AM16

VSS#AM17

VSS#AM20

VSS#AM23

VSS#AM24

VSS#AM27

VSS#AM28

AM4

AM16

AM17

AM20

AM23

AM24

AM27

AM28

H20

H21

H22

H23

H24

H25

H26

H27

VSS#H21

VSS#H22

VSS#H23

VSS#H24

VSS#H25

VSS#H26

VSS#H27

VSS#H28

VSS#AM4

VSS#AN1

VSS#AN10

VSS#AN13

VSS#AN16

VSS#AN17

VSS#AN2

VSS#AN20

AN1

AN2

AN10

AN13

AN16

AN17

AN20

AN23

H10

H11

H12

H13

H14

H17

H18

H19

VSS#H20

VSS#AN23

AN24

F7

VSS#F7

VSS#H10

VSS#H11

VSS#H12

VSS#H13

VSS#H14

VSS#H17

VSS#H18

VSS#H19

VSS#AN24

VSS#AN27

AN27

COMP6
COMP7

RSVD/COMP8

RSVD#AE4

RSVD#D1

RSVD#D14

RSVD#E5
RSVD#E6

RSVD#E7
RSVD#E23
RSVD#F23

RSVD#J3

RSVD#N4

RSVD#P5

RSVD#AC4

IMPSEL#

VSS#F4
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10

VSS#E8
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20

VSS#E2
VSS#E17
VSS#E14
VSS#E11

VSS#D9

VSS#D6

VSS#D5

VSS#D3

VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12

VSS#C7

VSS#C4

VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10

VSS#B8

VSS#B5

VSS#AN28

VSS#B1B1VSS#B11

VSS#B14

VSS#B17

VSS#B20

VSS#B24

B11

B14

B17

B20

B24

AN28

Y3
AE3
B13

AE4
D1
D14
E5
E6
E7
E23
F23
AL3

RSVD

J3
N4
P5
AC4

F6
V1

MSID1

W1

MSID0

U1

FC28

G1

FC27

E29

FC26

A24

FC23

F4
F22
F19
F16
F13
F10
E8
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5

ZIF-SOCK775-GF

ZIF-SOCK775-GF

2

PSI#
H_COMP7
H_COMP8

X_TP

X_TP

T11

T11

X_TP

X_TP

T13

T13

X_TP

X_TP

T10

T10

X_TPT2X_TP

T2

R141 51R/2R141 51R/2
R117 X_51R/2R117 X_51R/2
R114 X_51R/2R114 X_51R/2

R118 X_0R/2R118 X_0R/2
R24 X_0R/2R24 X_0R/2

X_TP

X_TP

T12

T12

R172 X_1KR/2R172 X_1KR/2

R111 X_49.9R1%/2R111 X_49.9R1%/2
R99 X_49.9R1%/2R99 X_49.9R1%/2
R183 24.9R1%/2R183 24.9R1%/2

H_TESTHI12
H_BPM#0

PSI# 34

VTT_OUT_RIGHT 3,4,34

H_TESTHI12 3
H_BPM#0 3

Kentsfield

1

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

LGA775 - GND

LGA775 - GND

LGA775 - GND

MS-7524M1

MS-7524M1

MS-7524M1

1

of

542

542

542

0A

0A

0A

5

D D

C C

4

H_A#3

L36

H_A#4

L37

H_A#5

J38

H_A#6

F40

H_A#7

H39

H_A#8

L38

H_A#9

L43

H_A#10

N39

H_A#11

N35

H_A#12

N37

H_A#13

J41

H_A#14

N40

H_A#15

M45

H_A#16

R35

H_A#17

T36

H_A#18

R36

H_A#19

R34

H_A#20

R37

H_A#21

R39

H_A#22

U38

H_A#23

T37

H_A#24

U34

H_A#25

U40

H_A#26

T34

H_A#27

Y36

H_A#28

U35

H_A#29

AA35

H_A#30

U37

H_A#31

Y37

H_A#32

Y34

H_A#33

Y38

H_A#34

AA37

H_A#35

AA36

H_REQ#0

H_REQ#[0..4]3

H_ADSTB#03
H_ADSTB#13

H_DSTBP#03

H_DSTBN#03

H_DSTBP#13

H_DSTBN#13

H_DSTBP#23

H_DSTBN#23

H_DSTBP#33

H_DSTBN#33

H_DBI#[0..3]3

H_ADS#3
H_TRDY#3
H_DRDY#3

H_DEFER#3

H_HITM#3

H_HIT#3

H_LOCK#3

H_BR#03,4

H_BNR#3
H_BPRI#3

H_DBSY#3

H_RS#[0..2]3

H_CPURST#3,4

H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

H_RS#0
H_RS#1
H_RS#2

G38
K35

J39
C43
G39

J40
T39

C39
B39
K31

J31

J25
K25
C32
D32

B40

F33

F26
D30

J42

L40

J43
G44
K44
H45
H40

L42

J44
H37
H42
G43

L44
G42
D27

N25

NB1A

NB1A

FSB_AB_3
FSB_AB_4
FSB_AB_5
FSB_AB_6
FSB_AB_7
FSB_AB_8
FSB_AB_9
FSB_AB_10
FSB_AB_11
FSB_AB_12
FSB_AB_13
FSB_AB_14
FSB_AB_15
FSB_AB_16
FSB_AB_17
FSB_AB_18
FSB_AB_19
FSB_AB_20
FSB_AB_21
FSB_AB_22
FSB_AB_23
FSB_AB_24
FSB_AB_25
FSB_AB_26
FSB_AB_27
FSB_AB_28
FSB_AB_29
FSB_AB_30
FSB_AB_31
FSB_AB_32
FSB_AB_33
FSB_AB_34
FSB_AB_35

FSB_REQB_0
FSB_REQB_1
FSB_REQB_2
FSB_REQB_3
FSB_REQB_4

FSB_ADSTBB_0
FSB_ADSTBB_1

FSB_DSTBPB_0
FSB_DSTBNB_0
FSB_DSTBPB_1
FSB_DSTBNB_1
FSB_DSTBPB_2
FSB_DSTBNB_2
FSB_DSTBPB_3
FSB_DSTBNB_3

FSB_DINVB_0
FSB_DINVB_1
FSB_DINVB_2
FSB_DINVB_3

FSB_ADSB
FSB_TRDYB
FSB_DRDYB
FSB_DEFERB
FSB_HITMB
FSB_HITB
FSB_LOCKB
FSB_BREQ0B
FSB_BNRB
FSB_BPRIB
FSB_DBSYB
FSB_RSB_0
FSB_RSB_1
FSB_RSB_2
FSB_CPURSTB

RSVD_05

ELK_CRB

ELK_CRB

3

EAGLELAKE_DDR2

EAGLELAKE_DDR2

?

?

SYM_REV = 1.5

SYM_REV = 1.5

1 OF 7

1 OF 7

FSB

FSB

FSB_DB_0
FSB_DB_1
FSB_DB_2
FSB_DB_3
FSB_DB_4
FSB_DB_5
FSB_DB_6
FSB_DB_7
FSB_DB_8

FSB_DB_9
FSB_DB_10
FSB_DB_11
FSB_DB_12
FSB_DB_13
FSB_DB_14
FSB_DB_15
FSB_DB_16
FSB_DB_17
FSB_DB_18
FSB_DB_19
FSB_DB_20
FSB_DB_21
FSB_DB_22
FSB_DB_23
FSB_DB_24
FSB_DB_25
FSB_DB_26
FSB_DB_27
FSB_DB_28
FSB_DB_29
FSB_DB_30
FSB_DB_31
FSB_DB_32
FSB_DB_33
FSB_DB_34
FSB_DB_35
FSB_DB_36
FSB_DB_37
FSB_DB_38
FSB_DB_39
FSB_DB_40
FSB_DB_41
FSB_DB_42
FSB_DB_43
FSB_DB_44
FSB_DB_45
FSB_DB_46
FSB_DB_47
FSB_DB_48
FSB_DB_49
FSB_DB_50
FSB_DB_51
FSB_DB_52
FSB_DB_53
FSB_DB_54
FSB_DB_55
FSB_DB_56
FSB_DB_57
FSB_DB_58
FSB_DB_59
FSB_DB_60
FSB_DB_61
FSB_DB_62
FSB_DB_63

FSB_SWING

FSB_RCOMP

FSB_DVREF

FSB_ACCVREF

HPL_CLKINP
HPL_CLKINN

2

H_D#0

F44

H_D#1

C44

H_D#2

D44

H_D#3

C41

H_D#4

E43

H_D#5

B43

H_D#6

D40

H_D#7

B42

H_D#8

B38

H_D#9

F38

H_D#10

A38

H_D#11

B37

H_D#12

D38

H_D#13

C37

H_D#14

D37

H_D#15

B36

H_D#16

E37

H_D#17

J35

H_D#18

H35

H_D#19

F37

H_D#20

G37

H_D#21

J33

H_D#22

L33

H_D#23

G33

H_D#24

L31

H_D#25

M31

H_D#26

M30

H_D#27

J30

H_D#28

G31

H_D#29

K30

H_D#30

M29

H_D#31

G30

H_D#32

J29

H_D#33

F29

H_D#34

H29

H_D#35

L25

H_D#36

K26

H_D#37

L29

H_D#38

J26

H_D#39

M26

H_D#40

H26

H_D#41

F25

H_D#42

F24

H_D#43

G25

H_D#44

H24

H_D#45

L24

H_D#46

J24

H_D#47

N24

H_D#48

C28

H_D#49

B31

H_D#50

F35

H_D#51

C35

H_D#52

B35

H_D#53

D35

H_D#54

D31

H_D#55

A34

H_D#56

B32

H_D#57

F31

H_D#58

D28

H_D#59

A29

H_D#60

C30

H_D#61

B30

H_D#62

E27

H_D#63

B28
B24

A23
C22

B23
P29

P30

?

?

H_D#[0..63] 3H_A#[3..35]3

HXSWING
HXRCOMP

CK_H_MCH_DP
CK_H_MCH_DN

MCH_GTLREF

CK_H_MCH_DP 18
CK_H_MCH_DN 18

1

B B

HXRCOMP

R205

R205

16.5R1%/2

16.5R1%/2

HXSWING SHOULD BE 1/4*VTT

V_FSB_VTT

R194

R194
300R1%/2

300R1%/2

R196

R196
100R1%/2

100R1%/2

V_FSB_VTT

R204

R204

49.9R1%/2

49.9R1%/2
C209

C209
C10000P25X2

C10000P25X2

HXSWING

Really need or just reserve the invert?

PIN H L

DDR2MTYPE

EXP_SLR

Normal

EXP_EN

Concurrent

MCH_TCEN

Enable

*GTLREF VOLTAGE SHOULD BE

0.67*VTT=0.8V (At VTT=1.2V)

V_FSB_VTT

UPI VOLTAGE CONSOLE

CPU_MCH_GTLREF

R193

R193

57.6R1%0402-RH

57.6R1%0402-RH

49.9R1%0402

49.9R1%0402

R198

R198

C213

C213

100R1%0402

100R1%0402

C1U16Y3

C1U16Y3

DDR3
Reverse
Non-concurrent
Disable

R203

R203

Description

MEMORY TYPE
PCI_E Lane Reversal
PCI_E/SDVO co-existence
TLS confidentiality

CPU_MCH_GTLREF 3

MCH_GTLREF

C217

C217
C220P50N2

C220P50N2

R225, R226 is from changingof the demo board

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

Eagle - FSB

Eagle - FSB

Eagle - FSB

of

642

642

1

642

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

EAGLELAKE_DDR2

D D

C C

B B

MAA_A[0..14]16,17

MAA_A[0..14]

WE_A#

WE_A#16,17

CAS_A#

CAS_A#16,17

RAS_A#

RAS_A#16,17

SBS_A0

SBS_A016,17

SBS_A1

SBS_A116,17

SBS_A2

SBS_A216,17

SCS_A#0

SCS_A#016,17

SCS_A#1

SCS_A#116,17

SCS_A#2

SCS_A#216,17

SCS_A#3

SCS_A#316,17

SCKE_A0

SCKE_A016,17

SCKE_A1

SCKE_A116,17

SCKE_A2

SCKE_A216,17

SCKE_A3

SCKE_A316,17

ODT_A0

ODT_A016,17

ODT_A1

ODT_A116,17

ODT_A2

ODT_A216,17

ODT_A3

ODT_A316,17

P_DDR0_A

P_DDR0_A16

N_DDR0_A

N_DDR0_A16

P_DDR1_A

P_DDR1_A16

N_DDR1_A

N_DDR1_A16

P_DDR2_A

P_DDR2_A16

N_DDR2_A

N_DDR2_A16

P_DDR3_A

P_DDR3_A16

N_DDR3_A

N_DDR3_A16

P_DDR4_A

P_DDR4_A16

N_DDR4_A

N_DDR4_A16

P_DDR5_A

P_DDR5_A16

N_DDR5_A

N_DDR5_A16

T1X_TP T1X_TP

MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14

R267 X_0R0402R267 X_0R0402

BC41
BC35
BB32
BC32
BD32
BB31
AY31
BA31
BD31
BD30

AW43

BC30
BB30
AM42
BD28

AW42

AU42
AV42

AV45
AY44
BC28

AU43
AR40
AU44
AM43

BB27
BD27
BA27
AY26

AR42
AM44
AR44

AY37
BA37

AW29

AY29
AU37
AV37
AU33
AT33
AT30
AR30

AW38

AY38

BC24
AR43

BB40
AT44
AV40

AL40

AR6

EAGLELAKE_DDR2

NB1C

NB1C

DDR_A_MA_0
DDR_A_MA_1
DDR_A_MA_2
DDR_A_MA_3
DDR_A_MA_4
DDR_A_MA_5
DDR_A_MA_6
DDR_A_MA_7
DDR_A_MA_8
DDR_A_MA_9
DDR_A_MA_10
DDR_A_MA_11
DDR_A_MA_12
DDR_A_MA_13
DDR_A_MA_14

DDR_A_WEB
DDR_A_CASB
DDR_A_RASB

DDR_A_BS_0
DDR_A_BS_1
DDR_A_BS_2

DDR_A_CSB_0
DDR_A_CSB_1
DDR_A_CSB_2
DDR_A_CSB_3

DDR_A_CKE_0
DDR_A_CKE_1
DDR_A_CKE_2
DDR_A_CKE_3

DDR_A_ODT_0
DDR_A_ODT_1
DDR_A_ODT_2
DDR_A_ODT_3

DDR_A_CK_0
DDR_A_CKB_0
DDR_A_CK_1
DDR_A_CKB_1
DDR_A_CK_2
DDR_A_CKB_2
DDR_A_CK_3
DDR_A_CKB_3
DDR_A_CK_4
DDR_A_CKB_4
DDR_A_CK_5
DDR_A_CKB_5

DDR3_DRAMRSTB
DDR3_DRAM_PWROK
DDR3_A_CSB1
DDR3_A_MA0
DDR3_A_WEB
DDR3_B_ODT3

DDR_A

DDR_A

ELK_CRB

ELK_CRB

SYM_REV = 1.5

SYM_REV = 1.5

3 OF 7

3 OF 7

?

?

4

DDR_A_DQS_0

DDR_A_DQSB_0

DDR_A_DQS_1

DDR_A_DQSB_1

DDR_A_DQS_2

DDR_A_DQSB_2

DDR_A_DQS_3

DDR_A_DQSB_3

DDR_A_DQS_4

DDR_A_DQSB_4

DDR_A_DQS_5

DDR_A_DQSB_5

DDR_A_DQS_6

DDR_A_DQSB_6

DDR_A_DQS_7

DDR_A_DQSB_7

DDR_A_DM_0
DDR_A_DM_1
DDR_A_DM_2
DDR_A_DM_3
DDR_A_DM_4
DDR_A_DM_5
DDR_A_DM_6
DDR_A_DM_7

DDR_A_DQ_0
DDR_A_DQ_1
DDR_A_DQ_2
DDR_A_DQ_3
DDR_A_DQ_4
DDR_A_DQ_5
DDR_A_DQ_6
DDR_A_DQ_7
DDR_A_DQ_8

DDR_A_DQ_9
DDR_A_DQ_10
DDR_A_DQ_11
DDR_A_DQ_12
DDR_A_DQ_13
DDR_A_DQ_14
DDR_A_DQ_15
DDR_A_DQ_16
DDR_A_DQ_17
DDR_A_DQ_18
DDR_A_DQ_19
DDR_A_DQ_20
DDR_A_DQ_21
DDR_A_DQ_22
DDR_A_DQ_23
DDR_A_DQ_24
DDR_A_DQ_25
DDR_A_DQ_26
DDR_A_DQ_27
DDR_A_DQ_28
DDR_A_DQ_29
DDR_A_DQ_30
DDR_A_DQ_31
DDR_A_DQ_32
DDR_A_DQ_33
DDR_A_DQ_34
DDR_A_DQ_35
DDR_A_DQ_36
DDR_A_DQ_37
DDR_A_DQ_38
DDR_A_DQ_39
DDR_A_DQ_40
DDR_A_DQ_41
DDR_A_DQ_42
DDR_A_DQ_43
DDR_A_DQ_44
DDR_A_DQ_45
DDR_A_DQ_46
DDR_A_DQ_47
DDR_A_DQ_48
DDR_A_DQ_49
DDR_A_DQ_50
DDR_A_DQ_51
DDR_A_DQ_52
DDR_A_DQ_53
DDR_A_DQ_54
DDR_A_DQ_55
DDR_A_DQ_56
DDR_A_DQ_57
DDR_A_DQ_58
DDR_A_DQ_59
DDR_A_DQ_60
DDR_A_DQ_61
DDR_A_DQ_62
DDR_A_DQ_63

BC5
BD4
BB9
BC9
BD15
BB15
AR22
AT22
AH43
AH42
AD43
AE42
Y43
Y42
T44
T43

BC3
BD9
BD14
AV22
AK42
AE45
AA45
T42

BC2
BD3
BD7
BB7
BB2
BA3
BE6
BD6
BB8
AY8
BD11
BB11
BC7
BE8
BD10
AY11
BB14
BC14
BC16
BB16
BC11
BE12
BA15
BD16
AW21
AY22

?

?

AV24
AY24
AU21
AT21
AR24
AU24
AL41
AK43
AG42
AG44
AL42
AK44
AH44
AG41
AF43
AF42
AC44
AC42
AF40
AF44
AD44
AC41
AB43
AA42
W42
W41
AB42
AB44
Y44
Y40
V42
U45
R40
P44
V44
V43
R41
R44

DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7

DQM_A0
DQM_A1
DQM_A2
DQM_A3
DQM_A4
DQM_A5
DQM_A6
DQM_A7

DATA_A0
DATA_A1
DATA_A2
DATA_A3
DATA_A4
DATA_A5
DATA_A6
DATA_A7
DATA_A8
DATA_A9
DATA_A10
DATA_A11
DATA_A12
DATA_A13
DATA_A14
DATA_A15
DATA_A16
DATA_A17
DATA_A18
DATA_A19
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A24
DATA_A25
DATA_A26
DATA_A27
DATA_A28
DATA_A29
DATA_A30
DATA_A31
DATA_A32
DATA_A33
DATA_A34
DATA_A35
DATA_A36
DATA_A37
DATA_A38
DATA_A39
DATA_A40
DATA_A41
DATA_A42
DATA_A43
DATA_A44
DATA_A45
DATA_A46
DATA_A47
DATA_A48
DATA_A49
DATA_A50
DATA_A51
DATA_A52
DATA_A53
DATA_A54
DATA_A55
DATA_A56
DATA_A57
DATA_A58
DATA_A59
DATA_A60
DATA_A61
DATA_A62
DATA_A63

DQS_A0 16
DQS_A#0 16
DQS_A1 16
DQS_A#1 16
DQS_A2 16
DQS_A#2 16
DQS_A3 16
DQS_A#3 16
DQS_A4 16
DQS_A#4 16
DQS_A5 16
DQS_A#5 16
DQS_A6 16
DQS_A#6 16
DQS_A7 16
DQS_A#7 16

DQM_A[0..7]

DATA_A[0..63]

DQM_A[0..7] 16

DATA_A[0..63] 16

3

VCC_DDR

MAA_B[0..14]

WE_B#17
CAS_B#17
RAS_B#17

SBS_B017
SBS_B117
SBS_B217

SCS_B#017
SCS_B#117
SCS_B#217
SCS_B#317

SCKE_B017
SCKE_B117
SCKE_B217
SCKE_B317

ODT_B017
ODT_B117
ODT_B217
ODT_B317

P_DDR0_B17
N_DDR0_B17
P_DDR1_B17
N_DDR1_B17
P_DDR2_B17
N_DDR2_B17
P_DDR3_B17
N_DDR3_B17
P_DDR4_B17
N_DDR4_B17
P_DDR5_B17
N_DDR5_B17

R186 1KR1%/2R186 1KR1%/2

WE_B#
CAS_B#
RAS_B#

SBS_B0
SBS_B1
SBS_B2

SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3

SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3

ODT_B0
ODT_B1
ODT_B2
ODT_B3

P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
P_DDR3_B
N_DDR3_B
P_DDR4_B
N_DDR4_B
P_DDR5_B
N_DDR5_B

PLACE 0.1UF CAP
CLOSE TO MCH

R190

R190
1KR1%/2

1KR1%/2

MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
MAA_B14

C183

C183
C0.1U16Y2

C0.1U16Y2

MCH_VREF_A

SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3

MAA_B[0..14]17

BD24
BB23
BB24
BD23
BB22
BD22
BC22
BC20
BB20
BD20
BC26
BD19
BB19
BE38
BA19

BD36
BC37
BD35

BD26
BB26
BD18

BB35
BD39
BB37
BD40

BC18
AY20
BE17
BB18

BD37
BC39
BB38
BD42

AY33

AW33

AV31
AW31
AW35

AY35

AT31

AU31

AP31

AP30
AW37

AV35

BB44

AY42

BA43

BC43

BC44

AN29

AN30

AK33

AJ33

2

NB1D

NB1D

DDR_B_MA_0
DDR_B_MA_1
DDR_B_MA_2
DDR_B_MA_3
DDR_B_MA_4
DDR_B_MA_5
DDR_B_MA_6
DDR_B_MA_7
DDR_B_MA_8
DDR_B_MA_9
DDR_B_MA_10
DDR_B_MA_11
DDR_B_MA_12
DDR_B_MA_13
DDR_B_MA_14

DDR_B_WEB
DDR_B_CASB
DDR_B_RASB

DDR_B_BS_0
DDR_B_BS_1
DDR_B_BS_2

DDR_B_CSB_0
DDR_B_CSB_1
DDR_B_CSB_2
DDR_B_CSB_3

DDR_B_CKE_0
DDR_B_CKE_1
DDR_B_CKE_2
DDR_B_CKE_3

DDR_B_ODT_0
DDR_B_ODT_1
DDR_B_ODT_2
DDR_B_ODT_3

DDR_B_CK_0
DDR_B_CKB_0
DDR_B_CK_1
DDR_B_CKB_1
DDR_B_CK_2
DDR_B_CKB_2
DDR_B_CK_3
DDR_B_CKB_3
DDR_B_CK_4
DDR_B_CKB_4
DDR_B_CK_5
DDR_B_CKB_5

DDR_VREF

DDR_RPD
DDR_RPU
DDR_SPD
DDR_SPU

RSVD_01
RSVD_02
RSVD_03
RSVD_04

ELK_CRB

ELK_CRB

EAGLELAKE_DDR2

EAGLELAKE_DDR2

SYM_REV = 1.5

SYM_REV = 1.5

4 OF 7

4 OF 7

DDR_B

DDR_B

?

?

DDR_B_DQS_0

DDR_B_DQSB_0

DDR_B_DQS_1

DDR_B_DQSB_1

DDR_B_DQS_2

DDR_B_DQSB_2

DDR_B_DQS_3

DDR_B_DQSB_3

DDR_B_DQS_4

DDR_B_DQSB_4

DDR_B_DQS_5

DDR_B_DQSB_5

DDR_B_DQS_6

DDR_B_DQSB_6

DDR_B_DQS_7

DDR_B_DQSB_7

DDR_B_DM_0
DDR_B_DM_1
DDR_B_DM_2
DDR_B_DM_3
DDR_B_DM_4
DDR_B_DM_5
DDR_B_DM_6
DDR_B_DM_7

DDR_B_DQ_0
DDR_B_DQ_1
DDR_B_DQ_2
DDR_B_DQ_3
DDR_B_DQ_4
DDR_B_DQ_5
DDR_B_DQ_6
DDR_B_DQ_7
DDR_B_DQ_8

DDR_B_DQ_9
DDR_B_DQ_10
DDR_B_DQ_11
DDR_B_DQ_12
DDR_B_DQ_13
DDR_B_DQ_14
DDR_B_DQ_15
DDR_B_DQ_16
DDR_B_DQ_17
DDR_B_DQ_18
DDR_B_DQ_19
DDR_B_DQ_20
DDR_B_DQ_21
DDR_B_DQ_22
DDR_B_DQ_23
DDR_B_DQ_24
DDR_B_DQ_25
DDR_B_DQ_26
DDR_B_DQ_27
DDR_B_DQ_28
DDR_B_DQ_29
DDR_B_DQ_30
DDR_B_DQ_31
DDR_B_DQ_32
DDR_B_DQ_33
DDR_B_DQ_34
DDR_B_DQ_35
DDR_B_DQ_36
DDR_B_DQ_37
DDR_B_DQ_38
DDR_B_DQ_39
DDR_B_DQ_40
DDR_B_DQ_41
DDR_B_DQ_42
DDR_B_DQ_43
DDR_B_DQ_44
DDR_B_DQ_45
DDR_B_DQ_46
DDR_B_DQ_47
DDR_B_DQ_48
DDR_B_DQ_49
DDR_B_DQ_50
DDR_B_DQ_51
DDR_B_DQ_52
DDR_B_DQ_53
DDR_B_DQ_54
DDR_B_DQ_55
DDR_B_DQ_56
DDR_B_DQ_57
DDR_B_DQ_58
DDR_B_DQ_59
DDR_B_DQ_60
DDR_B_DQ_61
DDR_B_DQ_62
DDR_B_DQ_63

AW8
AW9
AT15
AU15
AR20
AR17
AU26
AT26
AR38
AR37
AK34
AL34
AF37
AF36
AB35
AD35

AY6
AR15
AU17
AV25
AU39
AL37
AJ35
AD37

AV7
AW4
BA9
AU11
AU7
AU8
AW7
AY9
AY13
AP15
AW15
AT16
AU13
AW13
AP16
AU16
AY17
AV17
AR21
AV20
AP17
AW16
AT20
AN20

?

?

AT25
AV26
AU29
AV29
AW25
AR25
AP26
AR29
AR36
AU38
AN35
AN37
AV39
AW39
AU40
AU41
AL35
AL36
AK36
AJ34
AN39
AN40
AK37
AL39
AJ38
AJ37
AF38
AE37
AK40
AJ40
AF34
AE35
AD40
AD38
AB40
AA39
AE36
AE39
AB37
AB38

DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7

DQM_B0
DQM_B1
DQM_B2
DQM_B3
DQM_B4
DQM_B5
DQM_B6
DQM_B7

DATA_B0
DATA_B1
DATA_B2
DATA_B3
DATA_B4
DATA_B5
DATA_B6
DATA_B7
DATA_B8
DATA_B9
DATA_B10
DATA_B11
DATA_B12
DATA_B13
DATA_B14
DATA_B15
DATA_B16
DATA_B17
DATA_B18
DATA_B19
DATA_B20
DATA_B21
DATA_B22
DATA_B23
DATA_B24
DATA_B25
DATA_B26
DATA_B27
DATA_B28
DATA_B29
DATA_B30
DATA_B31
DATA_B32
DATA_B33
DATA_B34
DATA_B35
DATA_B36
DATA_B37
DATA_B38
DATA_B39
DATA_B40
DATA_B41
DATA_B42
DATA_B43
DATA_B44
DATA_B45
DATA_B46
DATA_B47
DATA_B48
DATA_B49
DATA_B50
DATA_B51
DATA_B52
DATA_B53
DATA_B54
DATA_B55
DATA_B56
DATA_B57
DATA_B58
DATA_B59
DATA_B60
DATA_B61
DATA_B62
DATA_B63

DQM_B[0..7]

DATA_B[0..63]

1

DQS_B0 17
DQS_B#0 17
DQS_B1 17
DQS_B#1 17
DQS_B2 17
DQS_B#2 17
DQS_B3 17
DQS_B#3 17
DQS_B4 17
DQS_B#4 17
DQS_B5 17
DQS_B#5 17
DQS_B6 17
DQS_B#6 17
DQS_B7 17
DQS_B#7 17

DQM_B[0..7] 17

DATA_B[0..63] 17

SCROMP1,3 CLOSED TO VCC_DDR

C0.1U16Y2

C0.1U16Y2

VCC_DDR

C184

C184

R184 19.1R1%/2R184 19.1R1%/2
R185 19.1R1%/2R185 19.1R1%/2
R189 19.1R%/2R189 19.1R%/2
R187 19.1R1%/2R187 19.1R1%/2

SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

Eagle - Memory DDR2

Eagle - Memory DDR2

Eagle - Memory DDR2

of

742

742

1

742

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

D D

MCH_BSEL018
MCH_BSEL118
MCH_BSEL218

R256 X_1KR1%0402R256 X_1KR1%0402

EXP16_PRSNT#24

C C

B B

EXP16_PRSNT# EXP_EN

R260 X_1KR0402R260 X_1KR0402
R248 0R0402R248 0R0402

R234 X_1KR0402R234 X_1KR0402
R241 X_1KR0402R241 X_1KR0402

ITPM_ENB
Itegrated TPM Enable:
0=Enable iTPM
1=Disable iTPM

DualX8_Enable
0=2X8 PCIe Ports Enable
1=1X16 PCIe Port Enable

EXP_SLR

MCH_RFU_G15

MCH_TCEN

CLINK_DATA13
CLINK_CLK13

CLINK_RST13
CLINK_PWOK13

MCH_BSEL0
MCH_BSEL1
MCH_BSEL2

T14X_TP T14X_TP
T19X_TP T19X_TP

T15X_TP T15X_TP
T18X_TP T18X_TP
T17X_TP T17X_TP
T20X_TP T20X_TP
T16X_TP T16X_TP

CLINK_DATA
CLINK_CLK
CL_VREF_MCH
CLINK_RST
CLINK_PWOK

4

AN13

AN10
AN11

AN17

AW44

AN16
AD42

BE44
BD45

AK15

F17
G16
P15

M20

N17
K16
F15
G15
H17
L17

M17

J17
G20
J16

M16

J15
J20
F20

AY4
AY2

AW2
AN8

AR7

AN9

B45

W30

U32
R42

BE2

BD1

A44
B14

NB1E

NB1E

BSEL0
BSEL1
BSEL2
ALLZTEST
XORTEST
RSVD_36
EXP_SLR
RSVD_17
EXP_SM
ITPM_ENB

RSVD_10
CEN
BSCANTEST
RSVD_12
RSVD_13
RSVD_14
RSVD_15
DUALX8_ENABLE

CL_DATA
CL_CLK
CL_VREF
CL_RSTB
CL_PWROK

JTAG_TDI
JTAG_TDO
JTAG_TCK
JTAG_TMS

NC_01
NC_02
NC_03
NC_04
NC_05
NC_06
NC_07
NC_08
NC_09
NC_10
NC_11
NC_12
NC_13
NC_18
NC_19

ELK_CRB

ELK_CRB

?

?

EAGLELAKE_DDR2

EAGLELAKE_DDR2

SYM_REV = 1.5

SYM_REV = 1.5

MISC

MISC

5 OF 7

5 OF 7

VGA

VGA

DPL_REFCLKINN
DPL_REFSSCLKINP
DPL_REFSSCLKINN

DDPC_CTRLCLK

DDPC_CTRLDATA

CRT_HSYNC
CRT_VSYNC

CRT_RED

CRT_GREEN

CRT_BLUE

CRT_IRTN

CRT_DDC_DATA

CRT_DDC_CLK

DAC_IREF

DPL_REFCLKINP

RSTINB

PWROK

ICH_SYNCB

HDA_BCLK
HDA_RSTB

HDA_SDI

HDA_SDO

HDA_SYNC

DPRSTPB

SLPB

RSVD_18
RSVD_19
RSVD_20
RSVD_21
RSVD_25
RSVD_26
RSVD_27
RSVD_28
RSVD_29
RSVD_30
RSVD_31
RSVD_32
RSVD_33
RSVD_34
RSVD_35

HSYNC

D14

VSYNC

C14

VGA_RED

B18

VGA_GREEN

D18

VGA_BLUE

C18
F13

MCH_DDC_DATA

L15

MCH_DDC_CLK

M15

DACREFSET

B15

CK_DOT96_MCH_DP

E15

CK_DOT96_MCH_DN

D15

CK_SS_MCH_DP

G8

CK_SS_MCH_DN

G9

AN6
AR4
K15

AU4
AV4
AU2
AV1
AU3

J11
F11
P43
P42

A45
B2
BE1
BE45
R15
R14
T15
T14
AB15
R32
R31
U31
U30
L11
L13

?

?

CHIP_PWGD

MCH_AZA_BCLK
MCH_AZA_RSTB
MCH_AZA_SDI
MCH_AZA_SDO
MCH_AZA_SYNC

R180 0/4R180 0/4
R179 0R0402R179 0R0402

3

HSYNC 31
VSYNC 31

VGA_RED 31
VGA_GREEN 31
VGA_BLUE 31

MCH_DDC_DATA 31
MCH_DDC_CLK 31

CK_DOT96_MCH_DP 18
CK_DOT96_MCH_DN 18

PLTRST# 14,19
CHIP_PWGD 13,14,30,32
ICH_SYNC# 13,14

R274 X_0R0402R274 X_0R0402
R265 X_0R0402R265 X_0R0402
R279 X_0R0402R279 X_0R0402
R282 X_0R0402R282 X_0R0402
R280 X_0R0402R280 X_0R0402

H_TESTHI13

R266

R266

X_10KR0402

X_10KR0402

VCC3

H_COMP5_R 3,14
H_TESTHI13 3

2

Non-Graphic sku

CK_DOT96_MCH_DP

CK_DOT96_MCH_DN

CK_SS_MCH_DP

CK_SS_MCH_DN

Reserved for non-Graphic sku

HSYNC
VSYNC

Close to GMCH.
Change to 0-ohm for
non-Graphic sku

DACREFSET

CL_VREF_MCH = 0.349V
Close to GMCH

V_1P1_CORE

R281

R281
1KR1%/2

1KR1%/2

R271

R271

464R1%0402-RH

R290 is changed from Intel's review

464R1%0402-RH

R249 X_10KR0402R249 X_10KR0402

R243 X_10KR0402R243 X_10KR0402

R269 10KR0402R269 10KR0402

R268 10KR0402R268 10KR0402

R255 X_0R0402R255 X_0R0402
R252 X_0R0402R252 X_0R0402

R228 1K/4R228 1K/4

CL_VREF_MCH

C272

C272
C0.1U16Y2

C0.1U16Y2

V_1P1_CORE

V_1P1_CORE

1

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C
Date: Sheet

Thursday, January 03, 2008

Date: Sheet of

Thursday, January 03, 2008

Date: Sheet of

5

4

3

2

Thursday, January 03, 2008

MICRO-START INT'L CO.,LTD.

Eagle - MSIC

Eagle - MSIC

Eagle - MSIC

of

842

842

1

842

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

D D

C C

B B

4

EAGLELAKE_DDR2

EAGLELAKE_DDR2

NB1B

AA10

AB10

AD10
AD11

AE10

AB13
AD13

N10

R10
U10

AA9

AA7
AA6

AB9
AB3
AA2

AD7
AD8

AE9
AE6

AE7
AF9
AF8

J13

G13

F6
G7
H6
G4

J6

J7

L6

L7
N9

N7
N6
R7
R6
R9

U9
U6
U7

R4

P4

D9

E9

ELK_CRB

ELK_CRB

NB1B

PEG_RXP_0
PEG_RXN_0
PEG_RXP_1
PEG_RXN_1
PEG_RXP_2
PEG_RXN_2
PEG_RXP_3
PEG_RXN_3
PEG_RXP_4
PEG_RXN_4
PEG_RXP_5
PEG_RXN_5
PEG_RXP_6
PEG_RXN_6
PEG_RXP_7
PEG_RXN_7
PEG_RXP_8
PEG_RXN_8
PEG_RXP_9
PEG_RXN_9
PEG_RXP_10
PEG_RXN_10
PEG_RXP_11
PEG_RXN_11
PEG_RXP_12
PEG_RXN_12
PEG_RXP_13
PEG_RXN_13
PEG_RXP_14
PEG_RXN_14
PEG_RXP_15
PEG_RXN_15

DMI_RXP_0
DMI_RXN_0
DMI_RXP_1
DMI_RXN_1
DMI_RXP_2
DMI_RXN_2
DMI_RXP_3
DMI_RXN_3

EXP_CLKP
EXP_CLKN
SDVO_CTRLDATA
SDVO_CTRLCLK
RSVD_23
RSVD_22

SYM_REV = 1.5

SYM_REV = 1.5

EXP_A_RXP_024
EXP_A_RXN_024
EXP_A_RXP_124
EXP_A_RXN_124
EXP_A_RXP_224
EXP_A_RXN_224
EXP_A_RXP_330
EXP_A_RXN_330
EXP_A_RXP_424
EXP_A_RXN_424
EXP_A_RXP_524
EXP_A_RXN_524
EXP_A_RXP_624
EXP_A_RXN_624
EXP_A_RXP_724
EXP_A_RXN_724
EXP_A_RXP_824
EXP_A_RXN_824
EXP_A_RXP_924
EXP_A_RXN_924

EXP_A_RXP_1024

EXP_A_RXN_1024

EXP_A_RXP_1124

EXP_A_RXN_1124

EXP_A_RXP_1224

EXP_A_RXN_1224

EXP_A_RXP_1324

EXP_A_RXN_1324

EXP_A_RXP_1424

EXP_A_RXN_1424

EXP_A_RXP_1524

EXP_A_RXN_1524

DMI_ITP_MRP_012
DMI_ITN_MRN_012
DMI_ITP_MRP_112
DMI_ITN_MRN_112
DMI_ITP_MRP_212
DMI_ITN_MRN_212
DMI_ITP_MRP_312
DMI_ITN_MRN_312

CK_MCH_DP18

CK_MCH_DN18
SDVO_CTRL_DATA24,30
SDVO_CTRL_CLK24,30

EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15

DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3

CK_MCH_DP
CK_MCH_DN
SDVO_CTRL_DATA
SDVO_CTRL_CLK

2 OF 7

2 OF 7

?

?

PCIE

PCIE

DMI

DMI

3

PEG_TXP_0

PEG_TXN_0

PEG_TXP_1

PEG_TXN_1

PEG_TXP_2

PEG_TXN_2

PEG_TXP_3

PEG_TXN_3

PEG_TXP_4

PEG_TXN_4

PEG_TXP_5

PEG_TXN_5

PEG_TXP_6

PEG_TXN_6

PEG_TXP_7

PEG_TXN_7

PEG_TXP_8

PEG_TXN_8

PEG_TXP_9

PEG_TXN_9
PEG_TXP_10
PEG_TXN_10
PEG_TXP_11
PEG_TXN_11
PEG_TXP_12
PEG_TXN_12
PEG_TXP_13
PEG_TXN_13
PEG_TXP_14
PEG_TXN_14
PEG_TXP_15
PEG_TXN_15

DMI_TXP_0
DMI_TXN_0
DMI_TXP_1
DMI_TXN_1
DMI_TXP_2
DMI_TXN_2
DMI_TXP_3
DMI_TXN_3

EXP_RCOMPO

EXP_COMPI

EXP_ICOMPO

EXP_RBIAS

C11
B11
A10
B9
C9
D8
B8
C7
B7
B6
B3
B4
D2
C2
H2
G2
J2
K2
K1
L2
P2
M2
T2
R1
U2
V2
W4
V3
AA4
Y4
AC1
AB2

AC2
AD2
AD4
AE4
AE2
AF2
AF4
AG4

Y7
Y8
Y6
AG1

GRCOMP

EXP_A_TXP_0
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15

DMI_MTP_IRP_0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3

R264 49.9R1%0402R264 49.9R1%0402

EXP_RBIAS

EXP_A_TXP_0 30
EXP_A_TXN_0 30
EXP_A_TXP_1 30
EXP_A_TXN_1 30
EXP_A_TXP_2 30
EXP_A_TXN_2 30
EXP_A_TXP_3 30
EXP_A_TXN_3 30
EXP_A_TXP_4 24
EXP_A_TXN_4 24
EXP_A_TXP_5 24
EXP_A_TXN_5 24
EXP_A_TXP_6 24
EXP_A_TXN_6 24
EXP_A_TXP_7 24
EXP_A_TXN_7 24
EXP_A_TXP_8 24
EXP_A_TXN_8 24
EXP_A_TXP_9 24
EXP_A_TXN_9 24
EXP_A_TXP_10 24
EXP_A_TXN_10 24
EXP_A_TXP_11 24
EXP_A_TXN_11 24
EXP_A_TXP_12 24
EXP_A_TXN_12 24
EXP_A_TXP_13 24
EXP_A_TXN_13 24
EXP_A_TXP_14 24
EXP_A_TXN_14 24
EXP_A_TXP_15 24
EXP_A_TXN_15 24

DMI_MTP_IRP_0 12
DMI_MTN_IRN_0 12
DMI_MTP_IRP_1 12
DMI_MTN_IRN_1 12
DMI_MTP_IRP_2 12
DMI_MTN_IRN_2 12
DMI_MTP_IRP_3 12
DMI_MTN_IRN_3 12

R283 X_750R1%0402R283 X_750R1%0402
R275 750R1%0402R275 750R1%0402

DEMO BOARD CHANGE

2

V_1P1_CORE

V_1P1_CORE

1

Primary _PEG_Presence
Primary PCIe port Detect:
0=PCIe Card is in Primary Slot
1=PCIe Card is not in Primary Slot

A A

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

Eagle - PCIE

Eagle - PCIE

Eagle - PCIE

of

942

942

1

942

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

L14

V_1P1_CORE

L14

X_L10U_100mA_0805

X_L10U_100mA_0805

CP12

CP12
X_COPPER

X_COPPER

L8

L8

X_L10U_100mA_0805

X_L10U_100mA_0805

CP9

CP9

X_COPPER

X_COPPER

L7

L7

X_L10U_100mA_0805

X_L10U_100mA_0805

CP7

CP7

X_COPPER

X_COPPER

L9

L9

X_L10U_100mA_0805

X_L10U_100mA_0805

CP8

CP8

X_COPPER

X_COPPER

L15

L15

X_L10U_100mA_0805

X_L10U_100mA_0805

CP13

CP13
X_COPPER

X_COPPER

V_1P1_CORE

C635 X_C0.1u16Y0402C635 X_C0.1u16Y0402

C633 X_C0.1u16Y0402C633 X_C0.1u16Y0402
C269 X_C0.1u16Y0402C269 X_C0.1u16Y0402
C636 X_C0.1u16Y0402C636 X_C0.1u16Y0402

C271 X_C0.1u16Y0402C271 X_C0.1u16Y0402
C270 X_C0.1u16Y0402C270 X_C0.1u16Y0402
C632 X_C0.1u16Y0402C632 X_C0.1u16Y0402
C634 X_C0.1u16Y0402C634 X_C0.1u16Y0402
C293 X_C0.1u16Y0402C293 X_C0.1u16Y0402
C278 X_C0.1u16Y0402C278 X_C0.1u16Y0402

C273 X_C0.1u16Y0402C273 X_C0.1u16Y0402
C255 X_C0.1u16Y0402C255 X_C0.1u16Y0402
C309 X_C0.1u16Y0402C309 X_C0.1u16Y0402

C237 X_C0.1u16Y0402C237 X_C0.1u16Y0402
C225 X_C0.1u16Y0402C225 X_C0.1u16Y0402
C214 X_C0.1u16Y0402C214 X_C0.1u16Y0402

R237

R237
1R1%/2

1R1%/2
R238

R238
1R1%/2

1R1%/2
X_C10U10Y5

X_C10U10Y5

C2.2U6.3Y3

C2.2U6.3Y3

C259

C259

VCCA_MPLL

R208

R208
1R1%/2

1R1%/2
R207

R207
1R1%/2

1R1%/2

VCCA_HPLL

C223

C223

VCCA_DPLLA

VCCA_DPLLA

C224

C224

X_C10U10Y5

X_C10U10Y5

R262

R262
1R1%/2

1R1%/2
R261

R261
1R1%/2

1R1%/2
X_C10U10Y5

X_C10U10Y5

VCC_DDR

VCCA_GPLL

V_1P1_CORE

C236

C236
C0.1U16Y2

C0.1U16Y2

C229

C229
C0.1U16Y2

C0.1U16Y2

V_1P1_CORE

C280 C10u10Y0805C280 C10u10Y0805
C630 C10u10Y0805C630 C10u10Y0805
C629 C10u10Y0805C629 C10u10Y0805
C631 C10u10Y0805C631 C10u10Y0805
C628 C10u10Y0805C628 C10u10Y0805
C388 C10u10Y0805C388 C10u10Y0805
C246 C10u10Y0805C246 C10u10Y0805
C262 C10u10Y0805C262 C10u10Y0805

V_1P1_CORE

V_1P1_CORE

V_1P1_CORE

NB POWER

L12

D D

V_1P1_CORE

VCC3

V_1P1_CORE

C C

B B

VCC3

V_FSB_VTT

C150 X_C1u6.3Y0402-RHC150 X_C1u6.3Y0402-RH
C169 X_C1u6.3Y0402-RHC169 X_C1u6.3Y0402-RH
C144 X_C1u6.3Y0402-RHC144 X_C1u6.3Y0402-RH
C155 X_C1u6.3Y0402-RHC155 X_C1u6.3Y0402-RH
C178 X_C1u6.3Y0402-RHC178 X_C1u6.3Y0402-RH

X_L10U_100mA_0805

X_L10U_100mA_0805

X_COPPER

X_COPPER

L13

L13

L0.1U_50mA

L0.1U_50mA

R219

R219

X_C10U10Y5

X_C10U10Y5

200R1%0402

200R1%0402

L10

L10

X_L10U_100mA_0805

X_L10U_100mA_0805

CP10

CP10

X_COPPER

X_COPPER

L11

L11

L0.1U_50mA

L0.1U_50mA

X_C10U10Y5

X_C10U10Y5

VCCDQ_CRT

L12

CP11

CP11

C254

C254

C235

C235

V_FSB_VTT

VCCA_DPLLB

C243

C243
X_C10U10Y5

X_C10U10Y5

VCCA_EXP

C249

C249

C0.1U16Y2

C0.1U16Y2

V_1P1_HPL

C228

C228
X_C10U10Y5

X_C10U10Y5

V_3P3_DAC_FILTERED

C230

C230

C0.1U16Y2

C0.1U16Y2

R215

R215

200R1%0402

200R1%0402

C139 C10u10Y0805C139 C10u10Y0805
C204 C1u6.3Y0402-RHC204 C1u6.3Y0402-RH
C195 C1u6.3Y0402-RHC195 C1u6.3Y0402-RH
C210 X_C0.1u16Y0402C210 X_C0.1u16Y0402
C193 X_C0.1u16Y0402C193 X_C0.1u16Y0402

V_1P1_CORE 22A

A A

V_FSB_VTT 1.1A
V_1P5_ICH 1.8A

4

C256

C256
C0.1U16Y2

C0.1U16Y2

C219 C10U10Y5C219 C10U10Y5

C220

C220
X_C0.1U16Y2

X_C0.1U16Y2

C227

C227
C0.1U16Y2

C0.1U16Y2

VCCA_GPLLD

C266

C266

C264

C264
C0.1U16Y2

C0.1U16Y2

H_VCCPLL4

V_1P5_ICH

R278

R278

X_0R0402

X_0R0402

L19

L19

X_1u500mA_0805-RH-1

X_1u500mA_0805-RH-1

CP26

CP26

X_COPPER

X_COPPER

R214 X_0R0402R214 X_0R0402

V_3P3_DAC_FILTERED

V_1P1_CORE

R276

R276

0R0402

0R0402

R507 1R1%/2R507 1R1%/2
R508 1R1%/2R508 1R1%/2

C627

C627
C10U10Y5

C10U10Y5

V_FSB_VTT

VCCDQ_CRTH_VCCPLL

VCCA_GPLL
VCCA_MPLL
VCCA_HPLL
VCCA_GPLLD
V_1P1_HPL

VCCA_DPLLA
VCCA_DPLLB

VCC3

VCCA_EXP

C276

C276

X_C4.7u10Y0805

X_C4.7u10Y0805

R272

R272

X_0R0402

X_0R0402

R273

R273

0R0402

0R0402

VCC_CKDDR

C626

C626

C1U16Y3

C1U16Y3

V_1P1_CORE

R263 0R0402R263 0R0402

Separate when AMT is
supported

ELK_CRB

ELK_CRB

AK32

AM31
AM30

A25
B25
B26
C24
C26
D22
D23
D24
E23
F21
F22
G21
G22
H21
H22

J21

J22
K21
K22

L21

L22
M21
M22
N20
N21
N22
P20
P21
P22
P24
R20
R21

R23
R24
R22

B20

B16
A21
B22
B12
U33

D20
C20

D19
B19

E19
A17

AG2

AR2
B17

AL31
AL32

V_1P1_CORE

EAGLELAKE_DDR2

EAGLELAKE_DDR2

NB1F

NB1F

VTT_FSB_01
VTT_FSB_02
VTT_FSB_03
VTT_FSB_04
VTT_FSB_05
VTT_FSB_06
VTT_FSB_07
VTT_FSB_08
VTT_FSB_09
VTT_FSB_10
VTT_FSB_11
VTT_FSB_12
VTT_FSB_13
VTT_FSB_14
VTT_FSB_15
VTT_FSB_16
VTT_FSB_17
VTT_FSB_18
VTT_FSB_19
VTT_FSB_20
VTT_FSB_21
VTT_FSB_22
VTT_FSB_23
VTT_FSB_24
VTT_FSB_25
VTT_FSB_26
VTT_FSB_27
VTT_FSB_28
VTT_FSB_29
VTT_FSB_30
VTT_FSB_31
VTT_FSB_32

VTT_FSB_34
VTT_FSB_35
VTT_FSB_36

VCCDQ_CRT

VCCAPLL_EXP
VCCA_MPLL
VCCA_HPLL
VCCDPLL_EXP
VCCD_HPLL

VCCA_DPLLA
VCCA_DPLLB

VCCA_DAC_01
VCCA_DAC_02

VCC3_3_1
VCC_EXP

VCCAVRM_EXP
VCC_HDA

VSS_369

VCC_SMCLK_04
VCC_SMCLK_03
VCC_SMCLK_02
VCC_SMCLK_01
VCCCML_DDR

?

?

V_1P1_CORE

AA19

AA21

VCC_02

VCC_01

AA27

AA29

AA25

AA23

VCC_05

VCC_06

VCC_04

VCC_03

SYM_REV = 1.5

SYM_REV = 1.5

VCC_CL_03

VCC_CL_02

VCC_CL_01

AJ15

AK14

AM29

AB22

AB20

AA30

VCC_08

VCC_07

6 OF 7

6 OF 7

VCC_CL_05

VCC_CL_04

AM24

AM25

AM26

3

?

?

AC21

AC23

AC25

AC19

AC17

AB30

AB29

AC16

AB24

AB26

VCC_17

VCC_18

VCC_16

VCC_15

VCC_13

VCC_12

VCC_14

VCC_10

VCC_11

VCC_09

VCC_CL_15

VCC_CL_14

VCC_CL_13

VCC_CL_12

VCC_CL_11

VCC_CL_10

VCC_CL_09

VCC_CL_08

VCC_CL_07

VCC_CL_06

AJ32

AL30

AF32

AK31

AM15

AM16

AM17

AM20

AM21

AM22

AD26

AD22

AD24

AD16

AD17

AD20

AC29

AC27

VCC_25

VCC_26

VCC_22

VCC_23

VCC_24

VCC_21

VCC_20

VCC_19

VCC_CL_23

VCC_CL_22

VCC_CL_21

VCC_CL_20

VCC_CL_19

VCC_CL_18

VCC_CL_17

VCC_CL_16

AA32

AA33

AB32

AB33

AE32

AE33

AD32

AD33

AE27

AE25

AE23

AE21

AE17

AE19

AE16

AD29

VCC_34

VCC_33

VCC_32

VCC_30

VCC_31

VCC_29

VCC_28

VCC_27

POWER

POWER

VCC_CL_24

VCC_CL_28

VCC_CL_27

VCC_CL_26

VCC_CL_25

VCC_CL_31

VCC_CL_30

VCC_CL_29

Y32

Y33

AP1

AP2

AM2

AM3

AM4

AL29

AF23

AF20

AF21

AF22

AF19

AF17

AE29

AF16

VCC_40

VCC_41

VCC_42

VCC_39

VCC_38

VCC_35

VCC_36

VCC_37

VCC_CL_39

VCC_CL_38

VCC_CL_37

VCC_CL_36

VCC_CL_35

VCC_CL_34

VCC_CL_33

VCC_CL_32

AL20

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AG20

AG22

AG17

AG16

AF29

AF26

AF27

AF25

AF24

VCC_51

VCC_52

VCC_50

VCC_49

VCC_48

VCC_46

VCC_47

VCC_45

VCC_44

VCC_43

VCC_CL_48

VCC_CL_47

VCC_CL_46

VCC_CL_45

VCC_CL_44

VCC_CL_43

VCC_CL_42

VCC_CL_41

VCC_CL_40

AL19

AL17

AL16

AL15

AL14

AL12

AL11

AL10

VCC_CL_49

AL9

AG24

AL8

2

AJ21

AJ19

AJ17

AJ16

AG29

AG26

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_CL_54

VCC_CL_53

VCC_CL_52

VCC_CL_51

VCC_CL_50

AL2

AL4

AL5

AL6

AL7

T21

R29

R27

R26

R25

AJ25

AJ23

VCC_59

VCC_58

VCC_CL_55

VCC_66

VCC_65

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_CL_63

VCC_CL_62

VCC_CL_61

VCC_CL_60

VCC_CL_59

VCC_CL_58

VCC_CL_57

VCC_CL_56

AL1

AK30

AK29

AK27

AK26

AK25

AK24

AK23

AK22

U22

U21

T29

T26

T27

T25

T24

VCC_74

VCC_73

VCC_71

VCC_72

VCC_70

VCC_69

VCC_CL_71

VCC_CL_70

VCC_CL_69

VCC_CL_68

VCC_CL_67

VCC_CL_66

VCC_CL_65

VCC_CL_64

AJ30

AJ31

AK16

AK17

AK19

AK20

AK21

AG31

W21

U29

W19

U27

U26

U25

U24

U23

VCC_81

VCC_82

VCC_80

VCC_79

VCC_78

VCC_77

VCC_76

VCC_75

VCC_CL_79

VCC_CL_78

VCC_CL_77

VCC_CL_76

VCC_CL_75

VCC_CL_74

VCC_CL_73

VCC_CL_72

Y31

AF31

AA31

AB31

AE31

AC31

AD31

AG30

Y26

Y22

Y24

Y20

W27

W29

W25

W23

VCC_86

VCC_87

VCC_85

VCC_84

VCC_83

VCC_CL_84

VCC_CL_83

VCC_CL_80

VCC_CL_82

VCC_CL_81

Y29

Y30

W31

AJ27

AJ29

T22

VCC_91

VCC_89

VCC_90

VCC_88

VCC_98

VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104

VCC_EXP_1
VCC_EXP_2
VCC_EXP_3
VCC_EXP_4

VCC_EXP_5
VCC_EXP_06
VCC_EXP_07
VCC_EXP_08
VCC_EXP_09
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
VCC_EXP_13
VCC_EXP_14
VCC_EXP_15
VCC_EXP_16
VCC_EXP_17
VCC_EXP_18
VCC_EXP_19
VCC_EXP_20
VCC_EXP_21
VCC_EXP_22
VCC_EXP_23
VCC_EXP_24
VCC_EXP_25
VCC_EXP_26
VCC_EXP_27
VCC_EXP_28
VCC_EXP_29
VCC_EXP_30
VCC_EXP_31
VCC_EXP_32
VCC_EXP_33
VCC_EXP_34
VCC_EXP_35
VCC_EXP_36
VCC_EXP_37
VCC_EXP_38

VCC_SM_01
VCC_SM_02
VCC_SM_03
VCC_SM_04
VCC_SM_05
VCC_SM_06
VCC_SM_07
VCC_SM_08
VCC_SM_09
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15

VCC_CL_85

1

T23

VCC_96

VCC_97

AC4
AF3
F9
H4
L3
P3
V4

AJ1
AJ2
AK2
AK3
AK4
AK13
AK12
AK11
AK10
AK9
AK8
AK7
AK6
AJ14
AJ13
AJ12
AJ11
AJ10
AJ9
AJ8
AJ7
AJ6
AG15
AF15
AF14
AE15
AE14
AD15
AD14
AC15
AB14
AA15
AA14
Y15
Y14
W15
U15
U14

AP44
AT45
AV44
AY40
BA41
BB39
BD21
BD25
BD29
BD34
BD38
BE23
BE27
BE31
BE36

V_1P1_CORE

VCC_DDR

VCC3 20mA
VCC_DDR 5.6A

5

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
Custom

Custom

Custom

Thursday, January 03, 2008

Date: Sheet of

Thursday, January 03, 2008

Date: Sheet of

Thursday, January 03, 2008

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Eagle - Power

Eagle - Power

Eagle - Power

of

10 42

10 42

1

10 42

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

EAGLELAKE_DDR2

EAGLELAKE_DDR2

A3

A43

B44

BD43

AJ20
AJ22
AJ24
AJ26

A12
A15
A19
A27
A31
A36
A40

A8

AA1

AA8

AB4
AB6
AB7
AB8

AC5

AD3

AD6
AD9
AE1

AE8

AF6
AF7

AG5
AH2
AH3
AH4

NB1G

NB1G

VSS_001
VSS_002
VSS_003
VSS_004
VSS_005
VSS_006
VSS_007
VSS_008
VSS_009
VSS_010
VSS_011
VSS_012
VSS_013
VSS_014
VSS_015
VSS_016
VSS_017
VSS_018
VSS_019
VSS_020
VSS_021
VSS_022
VSS_023
VSS_024
VSS_025
VSS_026
VSS_027
VSS_028
VSS_029
VSS_030
VSS_031
VSS_032
VSS_033
VSS_034
VSS_035
VSS_036
VSS_037
VSS_038
VSS_039
VSS_040
VSS_041
VSS_042
VSS_043
VSS_044
VSS_045
VSS_046
VSS_047
VSS_048
VSS_049
VSS_050
VSS_051
VSS_052
VSS_053
VSS_054
VSS_055
VSS_056
VSS_057
VSS_058
VSS_059
VSS_060
VSS_061
VSS_062
VSS_063
VSS_064
VSS_065
VSS_066
VSS_067
VSS_068
VSS_069
VSS_070
VSS_071
VSS_072
VSS_073
VSS_074
VSS_075
VSS_076
VSS_077
VSS_078
VSS_079
VSS_080
VSS_081
VSS_082
VSS_083
VSS_084
VSS_085
VSS_086
VSS_087
VSS_088
VSS_089
VSS_090
VSS_091
VSS_092
VSS_093

ELK_CRB

ELK_CRB

C16

VSS_368

VSS_366

VSS_367A6VSS_365

VSS_371

VSS_372

SYM_REV = 1.5

SYM_REV = 1.5

6 OF 7

6 OF 7

VSS_094

VSS_095

VSS_096

VSS_097

VSS_098

VSS_099

VSS_100

VSS_101

AJ36

AJ39

AJ44

AJ45

AL38

AL44

AK35

AK38

AK39

D D

AA11
AA12
AA13
AA16
AA17
AA20
AA22
AA24
AA26
AA34
AA38
AA40
AA44

AB11
AB12
AB16
AB17
AB19
AB21
AB23
AB25
AB27
AB34

C C

B B

A A

AB36
AB39

AC20
AC22
AC24
AC26
AC45

AD12
AD19
AD21
AD23
AD25
AD27

AD34
AD36
AD39

AE11
AE12
AE13
AE20
AE22
AE24
AE26
AE34
AE38
AE40
AE44

AF10
AF11
AF12
AF13
AF33
AF35
AF39

AG19
AG21
AG23
AG25
AG27
AG45

C45

VSS_364C1VSS_363

VSS_102

AL45

VSS_103

F1

VSS_362

VSS_104

AN21

BC1

BC45

VSS_361

VSS_360

VSS_105

VSS_106

AN22

AN24

4

?

?

BD2

BD44

BE3

BE43

VSS_359

VSS_358

VSS_357

VSS_356

7OF 7

7OF 7

VSS_107

VSS_108

VSS_109

VSS_110

AN25

AN26

AN33

AN36

3

P31

R11

R12

R16

R17

R19

R30

R38

R45

T10

T11

T12

T13

T16

T17

T19

T20

T30

T31

T32

T33

T35

T38

T40

Y9

VSS_341

VSS_342

VSS_343

VSS_344

VSS_345

VSS_346

VSS_347Y2VSS_348

VSS_349

VSS_350

VSS_351

VSS_352Y3VSS_353

VSS_354

VSS_355

?

?

VSS_111

VSS_112

VSS_113

VSS_114

VSS_115

VSS_116

VSS_117

VSS_118

VSS_119

VSS_120

VSS_121

VSS_122

VSS_123

VSS_124

VSS_125

VSS_126

AN7

AP20

AP21

AP22

AP24

AP25

AN38

AR3

AP29

AP45

AR10

AR11

AR13

AR16

AR26

AR31

AR33

VSS_336

VSS_337

VSS_338

VSS_339W5VSS_340

VSS_127

VSS_128

VSS_129

VSS_130

AR8

AR35

AR39

W17

W16

W1

VSS_332W2VSS_333

VSS_334

VSS_335

VSS_331

VSS_330

VSS_329

GND

GND

VSS_131

VSS_132

VSS_133

VSS_134

VSS_135

VSS_137

VSS_136

AT1

AT2

AR9

AT11

AT13

AT17

AT24

U8

U44

U39

U36

VSS_328

VSS_327

VSS_326

VSS_140

VSS_139

VSS_138

AT35

AT29

AU22

AU20

W20

W22

W24

W26

W44

W45

Y10

Y11

Y12

Y13

Y16

Y17

Y19

Y21

Y23

Y25

Y27

Y35

Y39

U1

U20

U19

U17

U16

U13

U12

U11

VSS_285

VSS_286

VSS_287

VSS_288

VSS_289

VSS_290R2VSS_291

VSS_292

VSS_293

VSS_294R5VSS_295R8VSS_296

VSS_297

VSS_298

VSS_299

VSS_300

VSS_301

VSS_302

VSS_303

VSS_304T3VSS_305

VSS_306

VSS_307

VSS_308

VSS_309

VSS_310

VSS_311T4VSS_312

VSS_325

VSS_324

VSS_323

VSS_322

VSS_321

VSS_143

VSS_142

VSS_141

VSS_145

VSS_144

AU5

AU30

AU25

AU35

VSS_313T6VSS_314T7VSS_315T8VSS_316T9VSS_317

VSS_320

VSS_319

VSS_318

VSS_153

VSS_152

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_146

AU9

AU6

AV13

AV11

VSS_157

VSS_156

VSS_155

VSS_154

AV2

AV6

AV21

AV16

AV15

AV38

AV33

AV30

VSS_165

VSS_164

VSS_163

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

AV9

AV8

AW26

AW24

AW22

AW20

AW17

AW11

VSS_173

VSS_172

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_166

AY1

AW3

AY30

AY25

AY21

AY16

AY15

AW30

VSS_181

VSS_180

VSS_179

VSS_178

VSS_177

VSS_176

VSS_175

VSS_174

B34

B29

B27

B21

B10

BA5

BB21

BA23

AY45

2

P16

P17

P25

P26

VSS_280

VSS_281

VSS_282

VSS_283

VSS_284

VSS_182

BB25

N8

VSS_279

N38

VSS_278

N36

VSS_277

N33

VSS_276

N30

VSS_275

N29

VSS_274

N26

VSS_273

N16

VSS_272

N13

VSS_271

N11

VSS_270

M44

VSS_269

M25

VSS_268

M24

VSS_267

M1

VSS_266

L9

VSS_265

L8

VSS_264

L4

VSS_263

L39

VSS_262

L35

VSS_261

L30

VSS_260

L26

VSS_259

L20

VSS_258

L16

VSS_257

L10

VSS_256

K45

VSS_255

K33

VSS_254

K29

VSS_253

K24

VSS_252

K20

VSS_251

K17

VSS_250

K13

VSS_249

K11

VSS_248

J9

VSS_247

J8

VSS_246

J5

VSS_245

J4

VSS_244

J37

VSS_243

J3

VSS_242

H9

VSS_241

H8

VSS_240

H7

VSS_239

H44

VSS_238

H38

VSS_237

H33

VSS_236

H31

VSS_235

H30

VSS_234

H25

VSS_233

H20

VSS_232

H16

VSS_231

H15

VSS_230

H13

VSS_229

H11

VSS_228

H1

VSS_227

G35

VSS_226

G3

VSS_225

G29

VSS_224

G26

VSS_223

G24

VSS_222

G17

VSS_221

G11

VSS_220

F8

VSS_219

F45

VSS_218

F42

VSS_217

F4

VSS_216

F30

VSS_215

F2

VSS_214

F16

VSS_213

E5

VSS_212

E41

VSS_211

E31

VSS_210

E3

VSS_209

D7

VSS_208

D6

VSS_207

D39

VSS_206

D26

VSS_205

D25

VSS_204

D21

VSS_203

D16

VSS_202

D11

VSS_201

C5

VSS_200

C3

VSS_199

BE40

VSS_197

BE34

VSS_196

BE29

VSS_195

BE25

VSS_194

BE21

VSS_193

BE19

VSS_192

BE15

VSS_191

BE10

VSS_190

BD8

VSS_189

BD17

VSS_187

BD12

VSS_186

AD30

NC_14

AC30

NC_15

AF30

NC_16

AE30

NC_17

VSS_183

VSS_184

VSS_185

BB6

BB28

1

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

Date: Sheet of

Wednesday, January 02, 2008

5

4

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

Eagle - GND

Eagle - GND

Eagle - GND

of

11 42

11 42

1

11 42

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1

5

D D

C C

4

3

U27

U27B

U27

AC26
AC28

AD29
AD30

AA26
AA28

AB30
AB29
AF26
AE26

AF28
AF30

W28
W26

V30
V29

Y30
Y29

D29
D30
E26
E28
P30
P29
R26
R28
M30
M29
N26
N28
K30
K29
L26
L28
H30
H29
J26
J28
F30
F29
G26
G28

U26
U25

U27B

DMIORXN
DMIORXP
DMIOTXN
DMIOTXP
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP

PER6N_GLAN_RXN
PER6N_GLAN_RXP
PER6N_GLAN_TXN
PER6N_GLAN_TXP
PER1N
PER1P
PET1N
PET1P
PER2N
PER2P
PET2N
PET2P
PER3N
PER3P
PET3N
PET3P
PER4N
PER4P
PET4N
PET4P
PER5N
PER5P
PET5N
PET5P

DMIRCOMPO
DMICOMPI

DMICLK100N
DMICLK100P

PE_RN6_ICH

PE_RP6_ICH

C447 C0.1u16X0402C447 C0.1u16X0402
C457 C0.1u16X0402C457 C0.1u16X0402

JMB363_RXN

JMB363_RXP

C421 C0.1u16X0402C421 C0.1u16X0402
C422 C0.1u16X0402C422 C0.1u16X0402

PE2_1394_RX#

PE2_1394_RX

C417 C0.1u16X0402C417 C0.1u16X0402
C426 C0.1u16X0402C426 C0.1u16X0402

PE_RXN4
PE_RXP4

R350 24.9R1%/2R350 24.9R1%/2

12 mils width

CK_PE_100M_ICH_DN

CK_PE_100M_ICH_DP

DMI_MTN_IRN_0
DMI_MTP_IRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_0
DMI_MTN_IRN_1
DMI_MTP_IRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_1
DMI_MTN_IRN_2
DMI_MTP_IRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_2
DMI_MTN_IRN_3
DMI_MTP_IRP_3
DMI_ITN_MRN_3
DMI_ITP_MRP_3

PE_TN6
PE_TP6

JMB_TXN
JMB_TXP

JMB381_TXC#
JMB381_TXC

PE_TN4
PE_TP4

DMI_COMP

DMI_MTN_IRN_09

DMI_MTP_IRP_09

DMI_ITN_MRN_09

DMI_ITP_MRP_09

DMI_MTN_IRN_19

DMI_MTP_IRP_19

DMI_ITN_MRN_19

DMI_ITP_MRP_19

DMI_MTN_IRN_29

DMI_MTP_IRP_29

DMI_ITN_MRN_29

DMI_ITP_MRP_29

DMI_MTN_IRN_39

DMI_MTP_IRP_39

DMI_ITN_MRN_39

DMI_ITP_MRP_39

PE_RN6_ICH22
PE_RP6_ICH22
PE_TN6_ICH22
PE_TP6_ICH22

JMB363_RXN27

JMB363_RXP27

JMB363_TXN27

JMB363_TXP27
PE2_1394_RX#26
PE2_1394_RX26

PE2_1394_TXC#26
PE2_1394_TXC26

PE_RXN424
PE_RXP424

C449 C0.1u16X0402C449 C0.1u16X0402

PE_TXN424

C444 C0.1u16X0402C444 C0.1u16X0402

PE_TXP424

V_1P5_ICH

CK_PE_100M_ICH_DN18
CK_PE_100M_ICH_DP18

2

DMI

DMI

OC10B_GB46
OC11B_GB47

PCI-E

PCI-E

2 OF 6

2 OF 6

USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N

USBP9P
USBP10N
USBP10P
USBP11N
USBP11P

USB

USB

OC0B_GB59
OC1B_GP40
OC2B_GP41
OC3B_GP42
OC4B_GP43
OC5B_GP29
OC6B_GP30
OC7B_GP31
OC8B_GP44
OC9B_GB45

USBRBIASN
USBRBIASP

CLK48

ICH9DH

ICH9DH

AD6
AD5
AE3
AE2
AD1
AD2
AB6
AB5
AC3
AC2
AB1
AB2
Y6
Y5
AA3
AA2
Y1
Y2
V6
V5
W2
W3
V1
V2

P5
N3
P7
R7
N2
N1
N5
M1
P3
R6
T7
P1

AG1
AG2

AG3

USB0­USB0+
USB1­USB1+
USB2­USB2+
USB3­USB3+
USB4­USB4+
USB5­USB5+
USB6­USB6+
USB7­USB7+
USB8­USB8+
USB9­USB9+
USB10­USB10+
USB11­USB11+

Place near SB

C587 C0.1U16Y2C587 C0.1U16Y2
C593 C0.1U16Y2C593 C0.1U16Y2
C581 C0.1U16Y2C581 C0.1U16Y2
C575 C0.1U16Y2C575 C0.1U16Y2
C580 C0.1U16Y2C580 C0.1U16Y2
C579 C0.1U16Y2C579 C0.1U16Y2

USBRBIAS_ICH

CK_48M_USB_ICH

USB0- 29
USB0+ 29
USB1- 29
USB1+ 29
USB2- 28
USB2+ 28
USB3- 28
USB3+ 28
USB4- 29
USB4+ 29
USB5- 29
USB5+ 29
USB6- 28
USB6+ 28
USB7- 28
USB7+ 28
USB8- 29
USB8+ 29
USB9- 29
USB9+ 29
USB10- 28
USB10+ 28
USB11- 28
USB11+ 28

R463 22.6R1%/2R463 22.6R1%/2

CK_48M_USB_ICH 18

OC#0 29
OC#2 28
OC#4 29
OC#6 28
OC#8 29
OC#10 28

1

SB STRAPPING RESISTOR

U27A

U27A

PGNT#0
PGNT#1
PGNT#2
PGNT#3

PREQ#0
PREQ#1
PREQ#2
PREQ#3

PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#E
PIRQ#F
PIRQ#G
PIRQ#H

E3

C6

B3

R2

J8

R3

K5

F10

H8

E6
F5

G12

H5

A7

C7

F7

K7
G13
F13

G8

J5

E1

F1

A3

K6

L7

F2

G2

PAR
DEVSELB
PCICLK
PCIRSTB
IRDYB
PMEB
SERRB
STOPB
PLOCKB
TRDYB
PERRB
FRAMEB

GNTB0
GNTB1_GP51
GNTB2_GP53
GNTB3_GP55

REQB_0
REQB1_GP50
REQB2_GP52
REQB3_GP54

PIRQAB
PIRQBB
PIRQCB
PIRQDB
GP2_PIRQEB
GP3_PIRQFB
GP4_PIRQGB
GP5_PIRQHB

PCI

PCI

1 OF 6

1 OF 6

CXBEB_0
CXBEB_1
CXBEB_2
CXBEB_3

PAR25

DEVSEL#25

CK_P_33M_ICH18

R456 1KR1%/2R456 1KR1%/2
R402 X_1KR/2R402 X_1KR/2

B B

A A

BOOT SELECT STRAPS

BOOT DEVICE GNT#0 SPI_CS1#

FWH 1 1

SPI 0 1

PCI 01

SIGNAL H

GNT3 EN
GNT2

HDA_SDOUT/HDA_SYNC strap PCI_E port
configuration bit[1:0].Internal weak pull down.
00:1X/1X/1X/1X 11:0X/0X/4X

PGNT#0
SPI_CS1#

PGNT#[3:0]Internal Pull-up

PGNT#2

R444 X_1KR/2R444 X_1KR/2

PGNT#3

R449 X_1KR/2R449 X_1KR/2

DIS
N/A

5

SPI_CS1# 14

DES.

L

A16 OVERIDE

PCIE PORT CONFIG 2

SET

BIT 0 (5-6)

BIT

PCIRST_ICH10#25

4

CK_P_33M_ICH

R460 33R/2R460 33R/2

IRDY#25

PCI_PME#25

SERR#25

STOP#25
LOCK#25
TRDY#25

PERR#25

FRAME#25

PGNT#025
PGNT#125

PGNT#325

PREQ#025
PREQ#125
PREQ#225
PREQ#325

PIRQ#A25
PIRQ#B25
PIRQ#C25
PIRQ#D25

PIRQ#E25

PIRQ#F25
PIRQ#G25
PIRQ#H25

AD_0
AD_1
AD_2
AD_3
AD_4
AD_5
AD_6
AD_7
AD_8

AD_9
AD_10
AD_11
AD_12
AD_13
AD_14
AD_15
AD_16
AD_17
AD_18
AD_19
AD_20
AD_21
AD_22
AD_23
AD_24
AD_25
AD_26
AD_27
AD_28
AD_29
AD_30
AD_31

ICH9DH

ICH9DH

3

AD0

C10

AD1

C8

AD2

E9

AD3

C9

AD4

A5

AD5

E12

AD6

E10

AD7

B7

AD8

B6

AD9

B4

AD10

E7

AD11

A4

AD12

H12

AD13

F8

AD14

C5

AD15

D2

AD16

E5

AD17

G7

AD18

E11

AD19

G10

AD20

G6

AD21

D3

AD22

H6

AD23

G5

AD24

C1

AD25

C2

AD26

C3

AD27

D1

AD28

J7

AD29

F3

AD30

G1

AD31

H3

C_BE#0

F11

C_BE#1

G9

C_BE#2

C4

C_BE#3

E8

AD[31..0] 25

C_BE#[3..0] 25

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev
C

C

C

Thursday, January 03, 2008

Date: Sheet of

Thursday, January 03, 2008

Date: Sheet of

Thursday, January 03, 2008

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

ICH10 - PCI, USB, DMI, TPM

ICH10 - PCI, USB, DMI, TPM

ICH10 - PCI, USB, DMI, TPM

of

12 42

12 42

1

12 42

0AMS-7524M1

0AMS-7524M1

0AMS-7524M1