5
CONTENT SHEET
4
3
2
1
Cover Sheet, Block diagram
Intel LGA775 CPU - Signals/ Power/ GND
D D
Intel Bearlake - FSB, PCIE, DMI, VGA, MSIC
Intel Bearlake - Memory DDR2
Intel Bearlake - Power / GND
ICH9 - PCI, USB, DMI, TPM
ICH9 - Host, DMI, SATA, Audio, SPI, RTC, MSIC
ICH9 - Power, GND
DDR2 Chanel-A / Chanel-B
Clock Gen ICS9LPR906
C C
Super I/O Fintek F71882
Onboard VGA Port
SATA / e-SATA / FAN Control
LAN INTEL NINEVEH/EKRON
Audio Codec ALC888 20
PCIE Slot x16, x1
PCI Slot 1 & 2
Marvell 88SE6111 PCIE to IDE/ SATA
B B
USB Connectors
IEEE1394 VT6308
1-2
3-5
6
7
8-9
10
11
12
13-14
15
16
17
18
19
21
22
23
24
25
MS-7358
CPU:
System Chipset:
On Board Device:
Main Memory:
Expansion Slots:
Intel Pentium 4, Pentium D, Core2 Duo, Wolfdale, Kentsfield
and Yorkfield processors in LGA775 Package.
Intel Bearlake - Q35/G33 North Bridge
Intel ICH9 (DO/DH South Bridge)
CLOCK Gen ICS 9LPRS906
LPC Super I/O -- Fintek F71882F
LPC TPM -- SLB9635
LAN -- INTEL NINEVEH/EKRON
HD Audio Codec -- ALC888
1394 Controller -- VT6308 (2-port)
PCIE to PATA Bridge -- Marvel 88SE6111
Dual-channel DDR-II * 4
PCI EXPRESS X16 SLOT *1
PCI EXPRESS X1 SLOT *1
PCI SLOT * 2
uATX
Version: 1.0
System Power/ACPI Controller UPI
DDR2 / NB-Core Switching Power /AMT
VRD 11 - ISL6322 (4 Phases)
ATX Power-Con. / F_Panel
Manual & Option Parts
A A
Power Delivery
Reset & PWROK map
GPIO Setting & PCI Routing / Revision History
5
4
26
27
28
29
30
31
32
33-34
PWM:
Configration and BOM match up
Option
STD
VIIV Bearlake-G33/ICH9DH cfg-7358-Viiv 601-7358-10S 2007/08/29
Intersil ISL6322 (4 Phases) w/ ISL6612 driver
Function
Bearlake-Q33/ICH9DO
3
Orcad Configure
cfg-7358-STD
MICRO-STAR INT'L CO.,LTD
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Custom
COVER SHEET
COVER SHEET
COVER SHEET
Thursday, August 30, 2007
Thursday, August 30, 2007
2
Thursday, August 30, 2007
BOM
MS-7358
MS-7358
MS-7358
1
Sheet of Date:
Sheet of Date:
Sheet of Date:
1 34
1 34
1 34
0A
0A
0A
5
4
3
2
1
Block Diagram
Board Stack-up
(1080 Prepreg Considerations)
D D
VRD 11
ISL6322
4-Phase PWM
PCI_E X16
Connector
Analog
C C
Video Out
PCI_E x1
PCI EXPRESS X16
RGB
PCI_E x1
Intel LGA775 Processor
FSB 800/1066/1333
FSB
Bearlake
G/Q/P
GMCH
DMI
DDRII
HD Audio Link
GLCI/LCI
DDR3 800/1066
4 DDR II
DIMM
Modules
HD Audio Codec
ALC888
LAN
INTEL NINEVEH/EKRON
Solder Mask
Solder Mask
PREPREG 2.7mils
CORE 50mils
PREPREG 2.7mils
Single End 50ohm Top/Bottom : 4mils
USB2.0 - 90ohm : 15/4.5/7.5/4.5/15
SATA - 95ohm : 15/4/8/4/15
LAN - 100ohm : 15/4/8/4/15
PCIE - 95ohm : 15/4/8/4/15
IEEE1394 - 110ohm : 15/4/9/4/15
IDE : 15/4/8/4/15
ICH9
SATA-II 2~5
E-SATA(0~1)
B B
USB Port 0~11
PCI_E to PATA
Marvell
88SE6111
SATA2
SATA2
USB2.0
PCI_E x1
SPI
LPC Bus
PCI
LPC SIO
1394
VT6308
IR
Fintek
F71882
J1394_1
PCI Slot 1
1.9mils Cu plus plating
1 oz. (1.2mils)
Cu Power
Plane
1 oz. (1.2mils)
Cu GND
Plane
1.9mils Cu plus plating
SATA-II
A A
IDE
Keyboard
SPI
Flash ROM
5
SPI
Debug Port
4
TPM
SLB9635
Mouse
Floopy
3
Serial
VFD
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2
Thursday, August 30, 2007
MS-7358
MS-7358
MS-7358
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
0A
0A
2 34
2 34
2 34
0A
Sheet of Date:
Sheet of Date:
Sheet of Date:
1
5
4
3
2
1
VCC_SENSE
CPU SIGNAL BLOCK
VSS_SENSE
VID1
H_D#2
VID0
H_D#1
H_D#0
VID[0..7] 28
ZIF-SOCK775-GF
ZIF-SOCK775-GF
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
PECI
VTIN1
GNDHM
H_TRMTRIP#
H_PROCHOT#
H_IGNNE#
ICH_H_SMI#
H_A20M#
H_TESTHI13
R116 0R/2 R116 0R/2
H_A#[3..35] 6
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
U8A
U8A
H_A#35
H_D#53
H_D#52
H_A#33
H_A#34
H_D#51
H_D#50
H_A#31
H_A#32
H_D#49
H_D#48
H_A#29
H_A#30
H_D#47
H_D#46
H_A#28
H_A#27
H_D#45
H_D#44
H_A#25
H_A#26
H_D#43
H_D#42
H_A#24
H_A#23
H_D#41
H_D#40
H_A#22
H_A#21
H_D#39
H_D#38
H_A#20
H_A#19
H_D#37
H_D#36
H_A#18
H_A#17
H_D#34
H_D#35
H_A#16
H_A#15
H_D#32
H_D#33
H_A#13
H_A#14
H_D#30
H_D#31
H_A#11
H_A#12
H_D#28
H_D#29
H_A#10
H_A#9
H_D#26
H_D#27
H_A#8
H_A#7
H_D#24
H_D#25
H_A#5
H_A#6
H_D#22
H_D#23
H_A#3
H_A#4
H_D#20
H_D#21
H_D#18
H_D#19
H_D#16
H_D#17
H_D#14
H_D#15
H_D#12
H_D#13
H_D#10
H_D#11
H_D#9
VID7
H_D#8
VID6
H_D#7
VID5
H_D#6
VID3
VID4
H_D#4
H_D#5
VID2
H_D#3
D D
H_DBI#[0..3] 6
H_IERR# 4
H_FERR# 11
H_STPCLK# 11
H_INIT# 11
H_DBSY# 6
H_DRDY# 6
H_TRDY# 6
H_ADS# 6
H_D#[0..63] 6
H_DEFER# 6
H_TRMTRIP# 11
H_PROCHOT# 4
H_IGNNE# 11
ICH_H_SMI# 11
H_BPM#1
Kentsfield
CPU_BSEL0 15,16
CPU_BSEL1 15,16
CPU_BSEL2 15,16
H_PWRGD 4,11
H_CPURST# 4,6
H_LOCK# 6
H_BNR# 6
H_HIT# 6
H_HITM# 6
H_BPRI# 6
PECI 11,16
VTIN1 16
GNDHM 16
H_A20M# 11
C C
B B
A A
VCC_SENSE 28
VSS_SENSE 28
VTT_OUT_RIGHT
R89
R89
1KR1%/2
1KR1%/2
CPU_GTLREF0
CPU_GTLREF1
GTLREF_SEL
CPU_MCH_GTLREF
CPU_GTLREF2
CPU_GTLREF3
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
FORCEPH
RSVD_G6
CK_H_CPU_DN
CK_H_CPU_DP
H_RS#2
H_RS#1
H_RS#0
TEST-U3
TEST-U2
H_COMP5
R143 49.9R1%/2 R143 49.9R1%/2
H_COMP4
R157 49.9R1%/2 R157 49.9R1%/2
H_COMP3
R149 49.9R1%/2 R149 49.9R1%/2
H_COMP2
R172 49.9R1%/2 R172 49.9R1%/2
H_COMP1
R146 49.9R1%/2 R146 49.9R1%/2
H_COMP0
R200 49.9R1%/2 R200 49.9R1%/2
TEST-J17
TEST-H16
TEST-H15
TEST-J16
PULL HIGHT PULL DOWN
RN5 8P4R-680R RN5 8P4R-680R
VID2
VID0
VID5
VID4
VID7
VID3
VID6
VID1
H_BPM#0
H_BPM#1
H_BPM#5
H_BPM#3
H_TRST#
H_BPM#4
H_TDO
H_TCK
H_TDI
H_BPM#2
H_TMS
H_TESTHI12
H_TESTHI11
H_TESTHI9
H_TESTHI10
H_TESTHI8
H_TESTHI1
H_TESTHI13
VTT_OUT_RIGHT
FORCEPH
H_PROCHOT#
RN4 8P4R-680R RN4 8P4R-680R
RN7 8P4R-51R/2 RN7 8P4R-51R/2
RN8 8P4R-51R/2 RN8 8P4R-51R/2
RN9 8P4R-51R/2 RN9 8P4R-51R/2
RN10 8P4R-51R/2 RN10 8P4R-51R/2
R165 51R/2 R165 51R/2
R148 51R/2 R148 51R/2
R156 51R/2 R156 51R/2
Thermal TRIP
R117 X_0R/2 R117 X_0R/2
R111 X_0R/2 R111 X_0R/2
R135 0R/2 R135 0R/2
VRD_VIDSEL 28
CPU_GTLREF0 4
CPU_GTLREF1 4
T12 X_TP T12 X_TP
CPU_MCH_GTLREF 6
CPU_GTLREF2 4
CPU_GTLREF3 4
H_BPM#0 5
H_REQ#[0..4] 6
H_TESTHI12 5
Kentsfield
R130 0R/2 R130 0R/2
R166 0R/2 R166 0R/2
R190 51R/2 R190 51R/2 C89
R192 51R/2 R192 51R/2
R109 X_130R/2 R109 X_130R/2
R155 X_51R/2 R155 X_51R/2
T2 X_TP T2 X_TP
T1 X_TP T1 X_TP
T11 X_TP T11 X_TP
X_TPT4X_TP
T4
X_TPT3X_TP
T3
T10 X_TP T10 X_TP
H_ADSTB#1 6
H_ADSTB#0 6
H_DSTBP#3 6
H_DSTBP#2 6
H_DSTBP#1 6
H_DSTBP#0 6
H_DSTBN#3 6
H_DSTBN#2 6
H_DSTBN#1 6
H_DSTBN#0 6
H_NMI 11
H_INTR 11
H_BPM#2
H_BPM#3
V_FSB_VTT
VTT_OUT_RIGHT
VTT_OUT_LEFT
CK_H_CPU_DN 15
CK_H_CPU_DP 15
H_RS#[0..2] 6
V_FSB_VTT
VTT_OUT_RIGHT 4,5
H_BR#0 4,6
C86
C86
C0.1U16Y2
C0.1U16Y2
VTT_OUT_LEFT 4
THRM# 15,16
VTT_OUT_RIGHT
C71
C71
C0.1U16Y2
C0.1U16Y2
VTT_OUT_RIGHT
VTT_OUT_LEFT
VCC3
R108
R108
X_10KR/2
X_10KR/2
Q22
Q22
X_2N3904
X_2N3904
C89
C0.1U16Y2
C0.1U16Y2
C85
C85
C0.1U16Y2
C0.1U16Y2
R134
R134
10KR/2
10KR/2
ICH_THERM# 11
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Thursday, August 30, 2007
Thursday, August 30, 2007
5
4
3
2
Thursday, August 30, 2007
MS-7358
MS-7358
MS-7358
LGA775 - Signal
LGA775 - Signal
LGA775 - Signal
1
Sheet of Date:
Sheet of Date:
Sheet of Date:
3 34
3 34
3 34
0A
0A
0A
5
VCCP
U8B
D D
VCCP
U8B
4
3
2
H_VCCA
H_VSSA
H_VCCPLL
H_VCCA
H_VCCPLL 8
V_FSB_VTT
C164
C164
C10U10Y5
C10U10Y5
C10U10Y5
C10U10Y5
C156
C156
V_FSB_VTT
C10u16X51206-RH
C10u16X51206-RH
C196
C196
1
CAPS FOR FSB GENERIC
ZIF-SOCK775-GF
ZIF-SOCK775-GF
C168
C168
C1U16Y3
C1U16Y3
2
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
C163
C163
C10U10Y5
C10U10Y5
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
VTT_SEL 26
V_1P5_ICH
CP8
H_VCCA
C155
C155
X_C10U10Y5
X_C10U10Y5
H_VSSA
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
CP8
H_VCCPLL
C178
X_COPPER
X_COPPER
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MICRO-STAR INT'L CO.,LTD
LGA775 - Power
LGA775 - Power
LGA775 - Power
Thursday, August 30, 2007
Thursday, August 30, 2007
Thursday, August 30, 2007
C178
X_C1U16Y3
X_C1U16Y3
MS-7358
MS-7358
MS-7358
1
C184
C184
C10000P25X2
C10000P25X2
Sheet of Date:
Sheet of Date:
Sheet of Date:
C189
C189
C10U10Y5
C10U10Y5
4 34
4 34
4 34
0A
0A
0A
C C
VCCP
*GTLREF VOLTAGE SHOULD BE
0.67 * VTT = 0.8V (At VTT=1.2V)
VTT_OUT_RIGHT
B B
VTT_OUT_RIGHT
R152 115R1%/2R152 115R1%/2
C87
C87
X_C10U16X6
X_C10U16X6
R142 115R1%/2R142 115R1%/2
R154 10R/2 R154 10R/2 R167 10R/2 R167 10R/2
R158
R158
C96
C96
200R1%/2
200R1%/2
C1U16Y3
C1U16Y3
R150 10R/2 R150 10R/2
R145
R145
C92
C92
200R1%/2
200R1%/2
C1U16Y3
C1U16Y3
C101
C101
C220P50N2
C220P50N2
C93
C93
C220P50N2
C220P50N2
CPU_GTLREF0 3
CPU_GTLREF1 3
VTT_OUT_LEFT
V_FSB_VTT
R164 115R1%/2R164 115R1%/2
R123 115R1%/2R123 115R1%/2
R163
R163
200R1%/2
200R1%/2
R129
R129
200R1%/2
200R1%/2
C104
C104
C1U16Y3
C1U16Y3
R171 10R/2 R171 10R/2
C81
C81
C1U16Y3
C1U16Y3
C110
C110
C220P50N2
C220P50N2
C116
C116
C220P50N2
C220P50N2
CPU_GTLREF2 3
CPU_GTLREF3 3
*PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
*TRACE WIDTH TO CAPS MUST BE NO SMALLER THAN 12MILS
V_FSB_VTT
L7 X_L10U_100mA_0805 L7 X_L10U_100mA_0805
CP2
CP2
X_COPPER
X_COPPER
VTT_PWRGOOD
PLACE AT CPU END OF ROUTE
A A
VTT_OUT_RIGHT 3,5
VTT_OUT_LEFT 3
VTT_OUT_RIGHT
VTT_OUT_LEFT
5
R107 130R1%/2 R107 130R1%/2
R139 62R/2 R139 62R/2
R82 62R/2 R82 62R/2
R153 X_100R/2 R153 X_100R/2
R168 62R/2 R168 62R/2
H_PROCHOT#
H_IERR#
H_CPURST#
H_PWRGD
H_BR#0
H_PROCHOT# 3
H_IERR# 3
H_CPURST# 3,6
H_PWRGD 3,11
H_BR#0 3,6
4
VID_GD# 26,28
3
3VSB
R91
R91
X_1KR1%/2
X_1KR1%/2
R110
R110
1KR1%/2
1KR1%/2
VTT_OUT_RIGHT
R122
R122
680R/2
680R/2
Q19
Q19
2N3904
2N3904
1.2V VTT_PWRGOOD
VTT_PWG
U8C
U8C
5
4
3
2
1
D D
C C
B B
H_COMP6
H_COMP7
H_COMP8
T14 X_TP T14 X_TP
T15 X_TP T15 X_TP
T13 X_TP T13 X_TP
T9 X_TP T9 X_TP
R160 51R/2 R160 51R/2
R144 51R/2 R144 51R/2
R141 51R/2 R141 51R/2
R170 0R/2 R170 0R/2
R169 0R/2 R169 0R/2
X_TP
X_TP
T16
T16
R198 X_1KR/2 R198 X_1KR/2
R140 49.9R1%/2 R140 49.9R1%/2
R128 49.9R1%/2 R128 49.9R1%/2
R202 24.9R1%/2 R202 24.9R1%/2
H_TESTHI12
H_BPM#0
VTT_OUT_RIGHT 3,4
H_TESTHI12 3
H_BPM#0 3
Kentsfield
ZIF-SOCK775-GF
ZIF-SOCK775-GF
A A
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MS-7358
MS-7358
LGA775 - GND
LGA775 - GND
LGA775 - GND
MS-7358
1
Sheet of Date:
Sheet of Date:
Sheet of Date:
5 34
5 34
5 34
0A
0A
0A
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Thursday, August 30, 2007
Thursday, August 30, 2007
5
4
3
2
Thursday, August 30, 2007
5
U1MCH
U1MCH
U11B
U11B
H_ADS# 3
H_TRDY# 3
H_DRDY# 3
H_HITM# 3
H_HIT# 3
H_LOCK# 3
H_BR#0 3,4
H_BNR# 3
H_BPRI# 3
H_DBSY# 3
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_RS#0
H_RS#1
H_RS#2
C245
C245
X_C2.7P25N2
X_C2.7P25N2
HXSCOMPB
C241
C241
X_C2.7P25N2
X_C2.7P25N2
HXRCOMP
FSB
FSB
1 OF 7
1 OF 7
Q35
Q35
*GTLREF VOLTAGE SHOULD BE
0.67*VTT=0.8V (At VTT=1.2V)
V_FSB_VTT
CPU_MCH_GTLREF
R225
R225
100R1%/2
100R1%/2
R229
R229
200R1%/2
200R1%/2
R234
R234
49.9R1%/2
49.9R1%/2
C255
C255
C1U16Y3
C1U16Y3
H_A#[3..35] 3 H_D#[0..63] 3
D D
H_REQ#[0..4] 3
C C
B B
V_FSB_VTT HXSCOMP
V_FSB_VTT
H_ADSTB#0 3
H_ADSTB#1 3
H_DSTBP#0 3
H_DSTBN#0 3
H_DSTBP#1 3
H_DSTBN#1 3
H_DSTBP#2 3
H_DSTBN#2 3
H_DSTBP#3 3
H_DSTBN#3 3
H_DBI#[0..3] 3
H_DEFER# 3
H_RS#[0..2] 3
H_CPURST# 3,4
R226
R226
49.9R1%/2
49.9R1%/2
R220
R220
49.9R1%/2
49.9R1%/2
R237
R237
16.5R1%/2
16.5R1%/2
MCH_GTLREF
C252
C252
C220P50N2
C220P50N2
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
CK_H_MCH_DP
CK_H_MCH_DN
CPU_MCH_GTLREF 3
HXSWING SHOULD BE 1/4*VTT
V_FSB_VTT
A A
R217
R217
300R1%/2
300R1%/2
R219
R219
100R1%/2
100R1%/2
V_FSB_VTT
R228
R228
49.9R1%/2
49.9R1%/2
C247
C247
C10000P25X2
C10000P25X2
HXSWING
5
HXSWING
HXRCOMP
HXSCOMP
HXSCOMPB
MCH_GTLREF
4
CK_H_MCH_DP 15
CK_H_MCH_DN 15
4
CK_PE_100M_MCH_DP 15
CK_PE_100M_MCH_DN 15
SDVO_CTRL_DATA 21
SDVO_CTRL_CLK 21
X_470/4/8P4R
X_470/4/8P4R
MCH_BSEL0 15,16
MCH_BSEL1 15,16
MCH_BSEL2 15,16
EXP16_PRSNT# 21
Really need or just reserve the invert?
PIN H L Description
DDR2 MTYPE
EXP_SLR
Normal
EXP_EN
Concurrent
MCH_TCEN
Enable
EXP16_PRSNT#
DDR3
Reverse
Non-concurrent
Disable
CL_VREF_MCH = 0.349V
Close to GMCH
V_1P25_CL_MCH
R286
R286
1KR1%/2
1KR1%/2
R290
R290
392R1%/2
392R1%/2
MEMORY TYPE
PCI_E Lane Reversal
PCI_E/SDVO co-existence
TLS confidentiality
CL_VREF_MCH
C306
C306
C0.1U16Y2
C0.1U16Y2
3
EXP_A_RXP_0 21
EXP_A_RXN_0 21
EXP_A_RXP_1 21
EXP_A_RXN_1 21
EXP_A_RXP_2 21
EXP_A_RXN_2 21
EXP_A_RXP_3 21
EXP_A_RXN_3 21
EXP_A_RXP_4 21
EXP_A_RXN_4 21
EXP_A_RXP_5 21
EXP_A_RXN_5 21
EXP_A_RXP_6 21
EXP_A_RXN_6 21
EXP_A_RXP_7 21
EXP_A_RXN_7 21
EXP_A_RXP_8 21
EXP_A_RXN_8 21
EXP_A_RXP_9 21
EXP_A_RXN_9 21
EXP_A_RXP_10 21
EXP_A_RXN_10 21
EXP_A_RXP_11 21
EXP_A_RXN_11 21
EXP_A_RXP_12 21
EXP_A_RXN_12 21
EXP_A_RXP_13 21
EXP_A_RXN_13 21
EXP_A_RXP_14 21
EXP_A_RXN_14 21
EXP_A_RXP_15 21
EXP_A_RXN_15 21
DMI_ITP_MRP_0 10
DMI_ITN_MRN_0 10
DMI_ITP_MRP_1 10
DMI_ITN_MRN_1 10
DMI_ITP_MRP_2 10
DMI_ITN_MRN_2 10
DMI_ITP_MRP_3 10
DMI_ITN_MRN_3 10
V_FSB_VTT
RN30
RN30
R268 X_1KR1%/2 R268 X_1KR1%/2
R269 X_1KR/2 R269 X_1KR/2
R270 0R/2 R270 0R/2
R271 X_1KR/2 R271 X_1KR/2
R267 X_1KR/2 R267 X_1KR/2
3
CLINK_DATA 11
CLINK_CLK 11
CLINK_RST 11
CLINK_PWOK 11
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH_DP
CK_PE_100M_MCH_DN
SDVO_CTRL_DATA
SDVO_CTRL_CLK
RN31
RN31
8P4R-10KR/2
8P4R-10KR/2
MCH_BS0
MCH_BS1
MCH_BS2
T18 X_TP T18 X_TP
T19 X_TP T19 X_TP
MTYPE
EXP_SLR
T24 X_TP T24 X_TP
EXP_EN
MCH_RFU_G15
T23 X_TP T23 X_TP
MCH_TCEN
T20 X_TP T20 X_TP
T25 X_TP T25 X_TP
T26 X_TP T26 X_TP
T27 X_TP T27 X_TP
T22 X_TP T22 X_TP
T21 X_TP T21 X_TP
CLINK_DATA
CLINK_CLK
CL_VREF_MCH
CLINK_RST
CLINK_PWOK
X_TP
X_TP
T17
T17
U11A
U11A
Q35
Q35
U11E
U11E
Q35
Q35
U1MCH
U1MCH
PCIE
PCIE
DMI
DMI
MISC VGA
MISC VGA
2 OF 7
2 OF 7
5 OF 7
5 OF 7
2
2
EXP_A_TXP_0
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_MTP_IRP_0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3
GRCOMP
HSYNC
VSYNC
VGA_RED_R
VGA_GREEN_R
VGA_BLUE_R
MCH_DDC_DATA
MCH_DDC_CLK
DACREFSET
CK_DOT96_MCH_DP
CK_DOT96_MCH_DN
CHIP_PWGD
EXP_A_TXP_0 21
EXP_A_TXN_0 21
EXP_A_TXP_1 21
EXP_A_TXN_1 21
EXP_A_TXP_2 21
EXP_A_TXN_2 21
EXP_A_TXP_3 21
EXP_A_TXN_3 21
EXP_A_TXP_4 21
EXP_A_TXN_4 21
EXP_A_TXP_5 21
EXP_A_TXN_5 21
EXP_A_TXP_6 21
EXP_A_TXN_6 21
EXP_A_TXP_7 21
EXP_A_TXN_7 21
EXP_A_TXP_8 21
EXP_A_TXN_8 21
EXP_A_TXP_9 21
EXP_A_TXN_9 21
EXP_A_TXP_10 21
EXP_A_TXN_10 21
EXP_A_TXP_11 21
EXP_A_TXN_11 21
EXP_A_TXP_12 21
EXP_A_TXN_12 21
EXP_A_TXP_13 21
EXP_A_TXN_13 21
EXP_A_TXP_14 21
EXP_A_TXN_14 21
EXP_A_TXP_15 21
EXP_A_TXN_15 21
DMI_MTP_IRP_0 10
DMI_MTN_IRN_0 10
DMI_MTP_IRP_1 10
DMI_MTN_IRN_1 10
DMI_MTP_IRP_2 10
DMI_MTN_IRN_2 10
DMI_MTP_IRP_3 10
DMI_MTN_IRN_3 10
R272 24.9R1%/2 R272 24.9R1%/2
may instead with V_1P25_PCIE?
FB7 0R/3 FB7 0R/3
FB6 0R/3 FB6 0R/3
FB5 0R/3 FB5 0R/3
V_1P25_CORE
reserve a 0.1u cap
1
V_1P25_CORE
HSYNC 17
VSYNC 17
VGA_RED 17
VGA_GREEN 17
VGA_BLUE 17
MCH_DDC_DATA 17
MCH_DDC_CLK 17
CK_DOT96_MCH_DP 15
CK_DOT96_MCH_DN 15
Non-Graphic sku
CK_DOT96_MCH_DP
PLTRST# 10,11,16
CHIP_PWGD 11,26
ICH_SYNC# 11
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
CK_DOT96_MCH_DN
Reserved for non-Graphic sku
HSYNC
VSYNC
Close to GMCH.
Change to 0-ohm for
non-Graphic sku
DACREFSET
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
Bearlake - FSB, PCIE, DMI, VGA, MSIC
Bearlake - FSB, PCIE, DMI, VGA, MSIC
Bearlake - FSB, PCIE, DMI, VGA, MSIC
Thursday, August 30, 2007
Thursday, August 30, 2007
Thursday, August 30, 2007
MS-7358
MS-7358
MS-7358
1
R263 X_10KR/2 R263 X_10KR/2
R265 X_0R/2 R265 X_0R/2
R262 X_0R/2 R262 X_0R/2
R260 X_0R/2 R260 X_0R/2
R241 1.3KR1%/2 R241 1.3KR1%/2
Sheet of Date:
Sheet of Date:
Sheet of Date:
V_1P25_CORE
6 34
6 34
6 34
0A
0A
0A
5
U1MCH
NC
NC
Q35
Q35
U1MCH
3 OF 7
3 OF 7
U11C
U11C
MAA_A[0..14] 13,14
D D
SBS_A[0..2] 13,14
SCS_A#0 13,14
SCS_A#1 13,14
SCS_A#2 13,14
SCS_A#3 13,14
SCKE_A0 13,14
SCKE_A1 13,14
SCKE_A2 13,14
SCKE_A3 13,14
C C
B B
P_DDR0_A 13
N_DDR0_A 13
P_DDR1_A 13
N_DDR1_A 13
P_DDR2_A 13
N_DDR2_A 13
P_DDR3_A 13
N_DDR3_A 13
P_DDR4_A 13
N_DDR4_A 13
P_DDR5_A 13
N_DDR5_A 13
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
WE_A#
WE_A# 13,14
CAS_A#
CAS_A# 13,14
RAS_A#
RAS_A# 13,14
SBS_A0
SBS_A1
SBS_A2
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
SCKE_A0
SCKE_A1
SCKE_A2
SCKE_A3
ODT_A0
ODT_A0 13,14
ODT_A1
ODT_A1 13,14
ODT_A2
ODT_A2 13,14
ODT_A3
ODT_A3 13,14
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
DDR_A
DDR_A
T7 X_TP T7 X_TP
R273 0R/2 R273 0R/2
T6 X_TP T6 X_TP
T8 X_TP T8 X_TP
T5 X_TP T5 X_TP
DDR3
DDR3
4
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
DQM_A0
DQM_A1
DQM_A2
DQM_A3
DQM_A4
DQM_A5
DQM_A6
DQM_A7
DATA_A0
DATA_A1
DATA_A2
DATA_A3
DATA_A4
DATA_A5
DATA_A6
DATA_A7
DATA_A8
DATA_A9
DATA_A10
DATA_A11
DATA_A12
DATA_A13
DATA_A14
DATA_A15
DATA_A16
DATA_A17
DATA_A18
DATA_A19
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A24
DATA_A25
DATA_A26
DATA_A27
DATA_A28
DATA_A29
DATA_A30
DATA_A31
DATA_A32
DATA_A33
DATA_A34
DATA_A35
DATA_A36
DATA_A37
DATA_A38
DATA_A39
DATA_A40
DATA_A41
DATA_A42
DATA_A43
DATA_A44
DATA_A45
DATA_A46
DATA_A47
DATA_A48
DATA_A49
DATA_A50
DATA_A51
DATA_A52
DATA_A53
DATA_A54
DATA_A55
DATA_A56
DATA_A57
DATA_A58
DATA_A59
DATA_A60
DATA_A61
DATA_A62
DATA_A63
DQS_A0 13
DQS_A#0 13
DQS_A1 13
DQS_A#1 13
DQS_A2 13
DQS_A#2 13
DQS_A3 13
DQS_A#3 13
DQS_A4 13
DQS_A#4 13
DQS_A5 13
DQS_A#5 13
DQS_A6 13
DQS_A#6 13
DQS_A7 13
DQS_A#7 13
DQM_A[0..7] 13
DATA_A[0..63] 13
VCC_DDR
R289 1KR1%/2 R289 1KR1%/2
3
U11D
U11D
WE_B# 14
CAS_B# 14
RAS_B# 14
C302
C302
C0.1U16Y2
C0.1U16Y2
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
MAA_B14
WE_B#
CAS_B#
RAS_B#
SBS_B0
SBS_B1
SBS_B2
SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3
SCKE_B0
SCKE_B1
SCKE_B2
SCKE_B3
ODT_B0
ODT_B1
ODT_B2
ODT_B3
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
P_DDR3_B
N_DDR3_B
P_DDR4_B
N_DDR4_B
P_DDR5_B
N_DDR5_B
MCH_VREF_A
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
DDR_RCOMPVOL
DDR_RCOMPVOH
DDR_B
DDR_B
4 OF 7
4 OF 7
MAA_B[0..14] 14
SBS_B[0..2] 14
SCS_B#0 14
SCS_B#1 14
SCS_B#2 14
SCS_B#3 14
SCKE_B0 14
SCKE_B1 14
SCKE_B2 14
SCKE_B3 14
P_DDR0_B 14
N_DDR0_B 14
P_DDR1_B 14
N_DDR1_B 14
P_DDR2_B 14
N_DDR2_B 14
P_DDR3_B 14
N_DDR3_B 14
P_DDR4_B 14
N_DDR4_B 14
P_DDR5_B 14
N_DDR5_B 14
PLACE 0.1UF CAP
CLOSE TO MCH
R287
R287
1KR1%/2
1KR1%/2
ODT_B0 14
ODT_B1 14
ODT_B2 14
ODT_B3 14
Q35
Q35
U1MCH
U1MCH
2
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
DQM_B0 DQM_B0
DQM_B1 DQM_B1
DQM_B2 DQM_B2
DQM_B3 DQM_B3
DQM_B4 DQM_B4
DQM_B5 DQM_B5
DQM_B6 DQM_B6
DQM_B7 DQM_B7
DATA_B0 DATA_B0
DATA_B1 DATA_B1
DATA_B2 DATA_B2
DATA_B3 DATA_B3
DATA_B4 DATA_B4
DATA_B5 DATA_B5
DATA_B6 DATA_B6
DATA_B7 DATA_B7
DATA_B8 DATA_B8
DATA_B9 DATA_B9
DATA_B10 DATA_B10
DATA_B11 DATA_B11
DATA_B12 DATA_B12
DATA_B13 DATA_B13
DATA_B14 DATA_B14
DATA_B15 DATA_B15
DATA_B16 DATA_B16
DATA_B17 DATA_B17
DATA_B18 DATA_B18
DATA_B19 DATA_B19
DATA_B20 DATA_B20
DATA_B21 DATA_B21
DATA_B22 DATA_B22
DATA_B23 DATA_B23
DATA_B24 DATA_B24
DATA_B25 DATA_B25
DATA_B26 DATA_B26
DATA_B27 DATA_B27
DATA_B28 DATA_B28
DATA_B29 DATA_B29
DATA_B30 DATA_B30
DATA_B31 DATA_B31
DATA_B32 DATA_B32
DATA_B33 DATA_B33
DATA_B34 DATA_B34
DATA_B35 DATA_B35
DATA_B36 DATA_B36
DATA_B37 DATA_B37
DATA_B38 DATA_B38
DATA_B39 DATA_B39
DATA_B40 DATA_B40
DATA_B41 DATA_B41
DATA_B42 DATA_B42
DATA_B43 DATA_B43
DATA_B44 DATA_B44
DATA_B45 DATA_B45
DATA_B46 DATA_B46
DATA_B47 DATA_B47
DATA_B48 DATA_B48
DATA_B49 DATA_B49
DATA_B50 DATA_B50
DATA_B51 DATA_B51
DATA_B52 DATA_B52
DATA_B53 DATA_B53
DATA_B54 DATA_B54
DATA_B55 DATA_B55
DATA_B56 DATA_B56
DATA_B57 DATA_B57
DATA_B58 DATA_B58
DATA_B59 DATA_B59
DATA_B60 DATA_B60
DATA_B61 DATA_B61
DATA_B62 DATA_B62
DATA_B63 DATA_B63
DQS_B0 14
DQS_B#0 14
DQS_B1 14
DQS_B#1 14
DQS_B2 14
DQS_B#2 14
DQS_B3 14
DQS_B#3 14
DQS_B4 14
DQS_B#4 14
DQS_B5 14
DQS_B#5 14
DQS_B6 14
DQS_B#6 14
DQS_B7 14
DQS_B#7 14
DQM_B[0..7] 14
DATA_B[0..63] 14
1
Place close to GMCH
VCC_DDR
C238 C2.2U6.3Y3 C238 C2.2U6.3Y3
C281 X_C2.2U6.3Y3 C281 X_C2.2U6.3Y3
C274 C2.2U6.3Y3 C274 C2.2U6.3Y3
C251 C2.2U6.3Y3 C251 C2.2U6.3Y3
C226 C2.2U6.3Y3 C226 C2.2U6.3Y3
C261 C2.2U6.3Y3 C261 C2.2U6.3Y3
SCROMP1,3 CLOSED TO VCC_DDR
A A
VCC_DDR
5
4
R276 1KR1%/2 R276 1KR1%/2
R279
R279
3.01KR1%/2
3.01KR1%/2
R278 1KR1%/2 R278 1KR1%/2
C293
C293
C0.1U16Y2
C0.1U16Y2 C298
3
DDR_RCOMPVOL
DDR_RCOMPVOL = 0.2 * VCC_DDR
C297
C297
C10000P25X2
C10000P25X2
DDR_RCOMPVOH
DDR_RCOMPVOH = 0.8 * VCC_DDR
C298
C10000P25X2
C10000P25X2
MSI
MSI
MSI
2
VCC_DDR
C208
C208
C0.1U16Y2
C0.1U16Y2
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Thursday, August 30, 2007
Thursday, August 30, 2007
Thursday, August 30, 2007
R281 19.1R1%/2 R281 19.1R1%/2
R280 19.1R1%/2 R280 19.1R1%/2
R210 19.1R%/2 R210 19.1R%/2
R211 19.1R1%/2 R211 19.1R1%/2
MS-7358
MS-7358
MS-7358
Bearlake - Memory
Bearlake - Memory
Bearlake - Memory
1
Sheet of Date:
Sheet of Date:
Sheet of Date:
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
7 34
7 34
7 34
0A
0A
0A
5
4
3
2
1
NB POWER
D D
V_1P25_CORE
C C
V_1P25_CL_MCH
X_L10U_100mA_0805 X_L10U_100mA_0805
V_1P25_CORE
B B
X_L10U_100mA_0805
X_L10U_100mA_0805
L13
L13
L0.1U_50mA
L0.1U_50mA
VCC3
A A
X_C10U10Y5
X_C10U10Y5
For non-Graphic sku
change to 0-ohm (0402)
For non-Graphic sku
change to 0-ohm (0603)
X_L10U_100mA_0805 X_L10U_100mA_0805
X_L10U_100mA_0805
X_L10U_100mA_0805
X_COPPER
X_COPPER
X_COPPER X_COPPER
L12
L12
CP7
CP7
X_COPPER
X_COPPER
C278
C278
C0.1U16Y2
C0.1U16Y2
VCCD_CRT
VCCDQ_CRT
X_COPPER X_COPPER
L9L9
CP4CP4
L10
L10
CP5
CP5
C2.2U6.3Y3
C2.2U6.3Y3
X_C10U10Y5 X_C10U10Y5
C275
C275
5
R264
R264
1R1%/2
1R1%/2
R266R266
X_C10U10Y5
X_C10U10Y5
VCCA_MPLL
VCCA_HPLL
C248
C248
VCCA_DPLLB
C263
C263
X_C10U10Y5
X_C10U10Y5
R256 1R1%/2 R256 1R1%/2
C276
C276
C10000P25X2
C10000P25X2
C267
C267
C0.1U16Y2
C0.1U16Y2
C265
C265
C1U16Y3
C1U16Y3
R223
R223
1R1%/2
1R1%/2
1R1%/2 1R1%/2
C283
C283
C0.1U16Y2 C0.1U16Y2
C262
C262
C0.1U16Y2
C0.1U16Y2
C280
C280
C0.1U16Y2
C0.1U16Y2
C242 C10U10Y5 C242 C10U10Y5
C249
C249
C0.1U16Y2
C0.1U16Y2
For non-Graphic sku
Cxx change to 0-ohm
Rxx unstuff
VCC_DDR
H_VCCPLL 4
L8
L8
X_L10U_100mA_0805
X_L10U_100mA_0805
CP3CP3
H_VCCPLL
R209 1R1%/2 R209 1R1%/2
R208 1R1%/2 R208 1R1%/2
C202C202
If non-Graphic sku
Remove these resisters
VCCDQ_CRT
VCCD_CRT
R242 0R/2 R242 0R/2
VCCA_HPLL
VCCA_DPLLA
VCCA_DPLLB
VCC_CKDDR
C207
C207
C1U16Y3
C1U16Y3
4
V_FSB_VTT
U11F
U11F
V_1P25_CORE
POWER
POWER
V_1P25_PCIE
need decouping caps
V_1P25_CORE
L15L15
6 OF 7
V_FSB_VTT
C221 C1U6.3Y2 C221 C1U6.3Y2
C179 C1U6.3Y2 C179 C1U6.3Y2
C169 C1U6.3Y2 C169 C1U6.3Y2
C223 C1U6.3Y2 C223 C1U6.3Y2
C172 C1U6.3Y2 C172 C1U6.3Y2
C186 C1U6.3Y2 C186 C1U6.3Y2
CP25
CP25
X_COPPER
X_COPPER
3
V_FSB_VTT
C190 C10U10Y5 C190 C10U10Y5
C229 C1U6.3Y2 C229 C1U6.3Y2
C227 C0.1U16Y2 C227 C0.1U16Y2
C235 C0.1U16Y2 C235 C0.1U16Y2
C232 C0.1U16Y2 C232 C0.1U16Y2
C337 C10U10Y5 C337 C10U10Y5
C334 C10U10Y5 C334 C10U10Y5
C335 C10U10Y5 C335 C10U10Y5
C330 C10U10Y5 C330 C10U10Y5
C307 C0.1U16Y2 C307 C0.1U16Y2
C289 C0.1U16Y2 C289 C0.1U16Y2
C291 C0.1U16Y2 C291 C0.1U16Y2
V_1P25_CORE
BOTTOM
C288 C0.1U16Y2 C288 C0.1U16Y2
C290 C0.1U16Y2 C290 C0.1U16Y2
C333 X_C10U10Y5 C333 X_C10U10Y5
C331 X_C10U10Y5 C331 X_C10U10Y5
C336 X_C10U10Y5 C336 X_C10U10Y5
C692 X_C0.1U25Y3 C692 X_C0.1U25Y3
2
V_1P25_CL_MCH
C286 C0.1U16Y2 C286 C0.1U16Y2
C287 C0.1U16Y2 C287 C0.1U16Y2
C689 X_C10U10Y5 C689 X_C10U10Y5
C687 X_C10U10Y5 C687 X_C10U10Y5
C688 C0.1U16Y2 C688 C0.1U16Y2
MSI
MSI
MSI
6 OF 7
Q35
Q35
V_1P25_CL_MCH
Separate when AMT is
supported
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MS-7358
MS-7358
Bearlake - Power
Bearlake - Power
Bearlake - Power
1
MS-7358
Custom
Custom
Custom
X_COPPER X_COPPER
0A
0A
0A
5
4
3
2
1
D D
C C
B B
U11G
U11G
GND
GND
7 OF 7
7 OF 7
Q35
A A
5
4
3
Q35
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MICRO-STAR INT'L CO.,LTD
MSI
MSI
MSI
Size Document Description Rev
Size Document Description Rev
Size Document Description Rev
Custom
Custom
Custom
Thursday, August 30, 2007
Thursday, August 30, 2007
2
Thursday, August 30, 2007
MS-7358
MS-7358
MS-7358
Bearlake - GND
Bearlake - GND
Bearlake - GND
0A
0A
9 34
9 34
9 34
0A
Sheet of Date:
Sheet of Date:
Sheet of Date:
1