MSI MS-7342 Schematics

1

COVER SHEET
BLOCK DIAGRAM
GPIO & JUMPER SETTING
Intel LGA775-CPU
ATI - RS600

ATI - SB600
Clock Generator - ICS951463
VGA CONNECTOR

LAN-RTL8111B

USB CONNECTORS
IDE & SATA
SIO-W83627DHG&FAN&COM 1,2& KB/MS&FDD
Azalia CODEC(ALC888)
IEEE1394 TI TSB43AB23PDTG4

A A

MS7 ACPI Controller
VRM11 Intersil 6326 4Phase
PCI EXPRESS X16 & X 1 SLOT
PCI Slot 1 & 2

1
2

3
4-6
7-13

14-16DDR II DIMM 1and DIMM2 1 & 2 & 3 & 4
17-21

22

23

24

25

26

27-31

32

33

34-37

38

39

40

MS-7342

CPU:

Intel Prescott ( L2=2MB )
Intel Cendar Mill (65nm)
Intel Smithfield (90nm Dual core)
Intel Presler (65nm Dual core)
Intel Conroe (65nm Dual core)

System Chipset:

ATI - RS600 (North Bridge)
ATI - SB600 (South Bridge)

On Board Chipset:

BIOS --LPC FLASH 4Mb
Azalia CODEC(ALC 888)
LPC Super I/O --W83627DHG
LAN-RTL8111B
IEEE1394 -- TI TSB43AB23PDTG4
Clock Generator - ICS951463

Main Memory:

DDR II * 4 (Max 4GB)

Version 1.0

ATX & Front Panel
Auto BOM manual
CLOCK DISTRIBUTION CHART
POWER DELIVERY CHART

41

42

43

44

History 45

Expansion Slots:

PCI Express X16 SLOT * 1
PCI Express X1 SLOT * 1
PCI 2.2 SLOT * 2

Intersil PWM:

Controller:
Driver: Intersil 6614ACB

1

Intersil 6326 4 Phase

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

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COVER SHEET

COVER SHEET

COVER SHEET

Size Document Number Rev

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Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

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MS-7342 BLOCK DIAGRAM

LGA775 CONROE

CLOCK GEN
ICS951463

D D

VGA CON

PCIE GFX x16
/SDVO

4X1 PCIE INTERFACE

C C

USB-5
HDR

Gbit ETHERNET
RTL8111B-GR-RH

USB-4
HDR

2525

USB-3
REAR

USB-9
HDR

USB-2
REAR

25 25 25

USB-8
HDR

25 25 25 25

USB-1
REAR

USB-7
HDR

22

23

PCIE x16

33

PCIE x1 SLOT1

USB-0
REAR

25

USB-6
HDR

CRT

3924

PCI BUS

B B

CPU CORE POWER

38

IEEE1394
TSB43AB23PDTG4

30

PCI SLOT 1

40

PCI SLOT 0

40

CPU VTT POWER

RS600 CORE POWER

PCIE & SB POWER

35,36,37

ACPI CONTROLLER

LGA775 SMITHFIELD
LGA775 PENTIUM D, EE
LGA775 PRESCOTT

4X DATA
2X ADDRESS

ATI NB - RS600

AGTL+ P4 CPU I/F
DUAL DDR2/3 CHANNEL
INTEGRATED GRAPHICS
TVOUT/TMDS/SDVO
1 X16/2 X8 PCIE VIDEO I/F
1 X4 PCIE I/F FOR SB
4 X1 PCIE I/F

USB 2.0

ATI SB - SB600

AGTL+
533/800/1066MHz

7,8,9,10,11,12,13

PCIE

X4

USB2.0 (10)
SATA2 (4 PORTS)
AC97 2.3
HD AUDIO 1.0
ATA 66/100/133
ACPI 1.1
LPC I/F
SPI I/F
INTERNAL RTC
PCI/PCI BRIDGE

17, 18, 19, 20, 21

LPC BUS

4,5,6

DDR II 400/533/667/800

A CHANNEL

DDR II 400/533/667/800

B CHANNEL

I2C

NB STRAPS

AZALIA

SERIAL ATA 2.0

ATA 66/100/133

UNBUFFERED
DDR2 DIMM

240-PIN DDR II DIMM

UNBUFFERED
DDR2 DIMM

240-PIN DDR II DIMM

UNBUFFERED
DDR2 DIMM

240-PIN DDR II DIMM

UNBUFFERED

11

DDR2 DIMM

240-PIN DDR II DIMM

HD AUDIO HDR

AZALIA CODEC

SATA#0 SATA#1

IDE1

26

32

32

14,15,16

14,15,16

14,15,16

14,15,16

2626

SATA#2

26 26

SATA#3

DDR2 DRAM POWER

ATX CON & DUAL POWER

A A

5

37

41

34,35,36,37

LPC SIO W83627DHG

SERIAL

KBD

FLOPPY

4

LPT

2930 30 29

3

MOUSE

PORT

FLASH
BIOS

27

31

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

Title

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Block Diagram

Block Diagram

Block Diagram

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

245Tuesday, December 26, 2006

245Tuesday, December 26, 2006

245Tuesday, December 26, 2006

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SB600 GPIO Config.

GPIO Pin

SATA_IS3#/GPIO0
ROM_CS#/GPIO1

D D

SPKR/GPIO2
FANOUT0/GPIO3
SATA_IS2#/GPIO4
SHUTDOWN#/GPIO5
GHI#/SATA_IS1#/GPIO6
WD_PWRGD/GPIO7
DDC1_SDA/GPIO8
DDC1_SCL/GPIO9
SATA_IS0#/GPIO10
SPI_DO/GPIO11
SPI_DI/GPIO12
LAN_RST#/GPIO13
ROM_RST#/GPIO14
IDE_D[0..15]/GPIO[15..30]
SPI_HOLD#/GPIO31

C C

SPI_CS#/GPIO32
INTE#/GPIO33
INTF#/GPIO34
INTG#/GPIO35
INTH#/GPIO36
DPSLP_OD#/GPIO37
AC_BITCLK/GPIO38
AC_SDOUT/GPIO39
AC_SYNC/GPIO40
SPDIF_OUT/PCICLK7/GPIO41
ACZ_SDIN0/GPIO42
ACZ_SDIN1/GPIO43
ACZ_SDIN2/GPIO44
AC_RST#/GPIO45
AC_SDIN3/GPIO46

B B

SPI_CLK/GPIO47
FANOUT1/GPIO48
FANOUT2/GPIO49
FANIN0/GPIO50
FANIN1/GPIO51
FANIN2/GPIO52
VIN[0..7]/GPIO[53..60]
TEMPIN0/GPIO61
TEMPIN1/GPIO62
TEMPIN2/GPIO63
TEMPIN3/TALERT#/GPIO64
BMREQ#/REQ5#/GPIO65
LLB#/GPIO66
SATA_ACT#/GPIO67
LDRQ1#/GNT5#/GPIO68

A A

RTC_IRQ#/GPIO69
REQ3#/GPIO70
REQ4#/GPIO71
GNT3#/GPIO72
GNT4#/GPIO73

5

Type

I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
OD(3.3V)
I/O(3.3V)
I/O(S5_3.3V)/VBAT
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)
I/O(3.3V)

4

Unused

Function

DDR_GPIO0
SPKR

Unused

SB_GPIO4
SB_GPIO5
BIOS_WP#
BIOS_WP#
SB_GPIO8
ATADET0
SB_GPIO10

Unused
Unused
Unused
Unused

PDD[0..15]

Unused
Unused

PCI_INTA#
PCI_INTB#
PCI_INTC#
PCI_INTD#
PULL HIGH 10K TO 3.3V

Unused

AC_SDATA_OUT

Unused
Unused
Unused
Unused
Unused
Unused

SDATA__IN_R

Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused

PREQ#5

Unused

SATALED#
LDRQ#1

Unused

PREQ#3
PREQ#4

Unused
Unused

SB600 GPM Config.

USB_OC0#/GPM#0

GPM Pin Type Function

USB_OC1#/GPM#1
USB_OC2#/GPM#2
USB_OC3#/GPM#3
USB_OC4#/GPM#4
USB_OC5#/DDR3_RST#/GPM#5
BLINK/GPM#6
SYS_RESET#/GPM#7
USB_OC8#/AZ_DOCK_RST#/GPM#8
USB_OC9#/SLP_S2#/GPM#9

I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)

SB600 GPOC Config.

SCL0/GPOC0#
SDA0/GPOC1#
SCL1/GPOC2#
SDA1/GPOC3#

GPOC Pin Type Function

I/O(3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)

SB600 EXTEVENT & GEVENT Config.

RI#/EXTEVENT0#

GPM Pin Type Function

LPC_SMI#/EXTEVENT1#
SMBALERT#/THRMTRIP#/GEVENT2#
LPC_PME#/GEVENT3#
PCI_PME#/GEVENT4#
S3_STATE/GEVENT5#
USB_OC6#/GEVENT6#
USB_OC7#GEVENT7#
WAKE#/GEVENT8#

I/O(S5_3.3V)
I/O(3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)
I/O(S5_3.3V)

PCI Config.

DEVICE

PCI Slot 1

PCI Slot 2

1394

3

MCP1 INT Pin

REQ#/GNT#

PCI_INTA#
PCI_INTB#
PCI_INTC#

PREQ#0

PGNT#0
PCI_INTD#
PCI_INTB#
PCI_INTC#
PCI_INTD#

PREQ#1

PGNT#1
PCI_INTA#

PCI_INTC# PREQ#2

PGNT#2

2

IDSEL

AD16

AD17

AD18 1394_PCLK

Title

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GPIO Configuration

GPIO Configuration

GPIO Configuration

Size Document Number Rev

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Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

OC#1
OC#1
OC#1
SB_PCIE_RST#
OC#2
OC#2

Unused

FP_RST#
OC#3
OC#3

SCLK
SDATA
SMB_CLK
SMB_DATA

OBR_GPIO#
LPC_SMI#
H_THERMTRIP#
SIO_PME#
PCI_PME#

Unused

OC#2
OC#2
WAKE#

CLOCK

PCICLK0

PCICLK1

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

345Tuesday, December 26, 2006

345Tuesday, December 26, 2006

345Tuesday, December 26, 2006

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CPU SIGNAL BLOCK

C45

C45
X_C10U6.3X51206

D D

H_DBI#[0..3]7

CPU_GTLREF25

H_FERR#17

H_STPCLK#17

H_INIT#17

H_DBSY#7

H_DRDY#7

H_TRDY#7

THERMDA_CPU27,28

H_PROCHOT#17,38

R88 X_0R0402R88 X_0R0402

H_D#[0..63]7

8

H_ADS#7

H_LOCK#7

H_BNR#7

H_HIT#7

H_HITM#7

H_BPRI#7

H_DEFER#7

VTIN_GND27,28

H_IGNNE#17

ICH_H_SMI#17

H_A20M#17

TP2TP2

H_FSBSEL022
H_FSBSEL122
H_FSBSEL222

CPUPWRGD17

H_CPURST#7

H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK

TRMTRIP#
H_PROCHOT#

H_TESTHI13

R74 X_62R0402R74 X_62R0402

C C

H_SLP#17

CPU_GTLREF35

B B

A A

H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3

H_IERR#
H_FERR#

H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54

H_A#[3..33]7

A8
G11
D19
C20

F2
AB2
AB3

R3

M3
AD3

P3

H4

B2

C1

E3

D2

C3

C2

D4

E4

G8

G7
AD1

AF1
AC1
AG1
AE1
AL1
AK1

M2
AE8
AL2

N2

P2

K3

L2
AH2

N5
AE6

C9
G10
D16
A20

Y1

V2
AA2

G29
H30
G30

N1
G23
B22

A22
A19
B19
B21
C21
B18
A17
B16
C18

U6A

U6A

DBI0#
DBI1#
DBI2#
DBI3#

EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#

DBSY#
DRDY#
TRDY#

ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#

TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13

RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5

BOOTSELECT
LL_ID0
LL_ID1

BSEL0
BSEL1
BSEL2

PWRGOOD
RESET#
D63#

D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

7

D53#

B15

C14

H_D#52

H_D#53

D52#

D51#

C15

H_D#51

D50#

A14

D17

H_D#49

H_D#50

AJ6

A35#

D49#

D48#

D20

H_D#48

H_A#33

AJ5

AH5

A34#

D47#

D22

G22

H_D#46

H_D#47

H_A#32

AH4

A33#

A32#

D46#

D45#

E22

H_D#45

H_A#30

H_A#31

AG5

AG4

A31#

D44#

F21

G21

H_D#43

H_D#44

H_A#29

AG6

A30#

A29#

D43#

D42#

E21

H_D#42

H_A#28

H_A#27

AF4

AF5

A28#

A27#

D41#

D40#

F20

E19

H_D#40

H_D#41

H_A#26

H_A#25

AB4

AC5

A26#

D39#

F18

E18

H_D#38

H_D#39

H_A#24

H_A#23

AB5

A25#

A24#

D38#

D37#

F17

H_D#36

H_D#37

AA5

A23#

D36#

G17

6

H_A#22

H_A#21

AD6

AA4

A22#

D35#

E16

G18

H_D#34

H_D#35

H_A#18

H_A#19

H_A#20

A21#

A20#Y4A19#Y6A18#W6A17#

D34#

D33#

D32#

E15

G16

G15

H_D#32

H_D#33

H_D#31

H_A#17

H_A#15

H_A#14

H_A#16

AB6

A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#

D31#

D30#

D29#

D28#

D27#

F15

F14

G14

G13

H_D#30

H_D#27

H_D#29

H_D#28

H_A#12

H_A#13

D26#

E13

D13

H_D#25

H_D#26

H_A#11

D25#

D24#

F12

H_D#24

H_A#10

H_A#9

U6

D23#

F11

D10

H_D#23

H_D#22

H_A#3

H_A#6

H_A#8

H_A#5

H_A#7

H_A#4

L5

A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#

D22#

D21#

D20#D7D19#E9D18#F9D17#F8D16#G9D15#

E10

H_D#17

H_D#19

H_D#20

H_D#21

H_D#18

H_D#16

AC2

D11

C12

H_D#15

H_D#14

DBR#

D14#

D13#

B12

H_D#13

5

AJ3

AN4

AN3

AN6

AN5

ITP_CLK1

VSS_SENSE

VCC_SENSE

VSS_MB_REGULATION

VCC_MB_REGULATION

D12#D8D11#

D10#

D9#

D8#

D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#

B10

A11

A10

C11

H_D#8

H_D#7

H_D#9

H_D#12

H_D#10

H_D#11

AK3

ITP_CLK0

H_D#5

H_D#6

VID3

VID4

VID0

VID2

VID5

VID1

VID7

VID6

AM7

AM5

AL4

AK4

AL6

AM3

AL5

AM2

VID6#

VID5#

VID4#

VID3#

VID2#

VID1#

VID0#

VID_SELECT

GTLREF0

RSVD#AM7

GTLREF1

GTLREF_SEL

GTLREF2

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

PCREQ#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI12
TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1

TESTHI0
FORCEPH
RSVD#G6

BCLK1#
BCLK0#

RS2#
RS1#
RS0#

AP1#
AP0#

BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0

DP3#

DP2#

DP1#

DP0#

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

LINT1/NMI

LINT0/INTR

ZIF-SOCK775-15u-in,ZIF-SOCK775-15u-in_TH

ZIF-SOCK775-15u-in,ZIF-SOCK775-15u-in_TH

B4

H_D#0

H_D#2

H_D#3

H_D#4

H_D#1

X_C10U6.3X51206

VID[0..7] 38

1KR0402

1KR0402

AN7
H1
H2

TP_GTLREF_SEL

H29

MCH_GTLREF_CPU

E24

H_BPM#5

AG3

H_BPM#4

AF2

H_BPM#3

AG2

H_BPM#2

AD2

H_BPM#1

AJ1

H_BPM#0

AJ2
G5

H_REQ#4

J6

H_REQ#3

K6

H_REQ#2

M6

H_REQ#1

J5

H_REQ#0

K4

H_TESTHI12

W2

H_TESTHI11

P1

H_TESTHI10

H5

H_TESTHI9

G4

H_TESTHI8

G3
F24
G24
G26
G27
G25

H_TESTHI2_7

F25

H_TESTHI1

W3

H_TESTHI0

F26

H_FORCEPH

AK6

RSVD_G6

G6
G28

F28

H_RS#2

A3

H_RS#1

F5

H_RS#0

B3
U3

U2
F3

H_COMP5

T2

H_COMP4

J2

H_COMP3

R1

H_COMP2

G2

H_COMP1

T1

H_COMP0

A13
J17

H16
H15
J16

AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1

VTT_OUT_RIGHT

TRMTRIP#

4

R35

R35

H_FORCEPH 38

TP3TP3
TP4TP4

R85 49.9R1%0402R85 49.9R1%0402
R91 49.9R1%0402R91 49.9R1%0402
R83 49.9R1%0402R83 49.9R1%0402
R93 49.9R1%0402R93 49.9R1%0402
R82 49.9R1%0402R82 49.9R1%0402
R116 49.9R1%0402R116 49.9R1%0402

TP14TP14
TP17TP17
TP15TP15
TP13TP13

H_NMI 17
H_INTR 17

R62

R62

62R0402

62R0402

VCC_VRM_SENSE

VSS_VRM_SENSE

VTT_OUT_RIGHT

VID_SEL 38

CPU_GTLREF0 5
CPU_GTLREF1 5

TP16TP16

NB_GTLREF 7

PECI 27

H_REQ#[0..4] 7

H_BR#0

R86 62R0402R86 62R0402

MSID1

H_TESTHI1

R118 62R0402R118 62R0402
R119 62R0402R119 62R0402

R79 X_62R0402R79 X_62R0402

CK_H_CPU# 22
CK_H_CPU 22

H_RS#[0..2] 7

H_BR#0

H_ADSTB#1 7
H_ADSTB#0 7
H_DSTBP#3 7
H_DSTBP#2 7
H_DSTBP#1 7
H_DSTBP#0 7
H_DSTBN#3 7
H_DSTBN#2 7
H_DSTBN#1 7
H_DSTBN#0 7

R64

R64

1KR0402

1KR0402

B

Q12

Q12
N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

V_FSB_VTT

VTT_OUT_LEFT

R133 X_62R0402R133 X_62R0402

VCC3

R12

R12

1KR0402

1KR0402

CE

VCC_VRM_SENSE 38

VSS_VRM_SENSE 38

RN12

RN12
8P4R-51R0402

8P4R-51R0402

VTT_OUT_LEFT

RN11

RN11
8P4R-51R0402

8P4R-51R0402

VTT_OUT_LEFT 5

H_BR#0 7
VTT_OUT_LEFT 5

C63

C63
C0.1U16Y0402

C0.1U16Y0402

H_THERMTRIP# 20

3

MSID1
H_TESTHI1

VTT_OUT_RIGHT5,6,19,27

C66

C66

C0.1U16Y0402

C0.1U16Y0402

VTT_OUT_LEFT

V_FSB_VTT

BSEL

1

02

FSB FREQUENCY

TABLE

267 MHZ (1067)000

0

01 200 MHZ (800)
1

0 0 133 MHZ (533)

Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1

MSID1 6

H_TESTHI1 6

2
4
6
8
2
4
6
8

2
4
6
8

H_PROCHOT# 17,38

H_CPURST# 7VTT_OUT_LEFT5
MSID0 6

H_FSBSEL1 22
H_FSBSEL0 22
H_FSBSEL2 22

445Tuesday, December 26, 2006

445Tuesday, December 26, 2006

445Tuesday, December 26, 2006

1

VTT_OUT_RIGHT

H_FERR#
H_BPM#3

H_BPM#5
H_BPM#1
H_BPM#0
H_TDI
H_BPM#2
H_TDO
H_BPM#4

H_TRST#
H_IERR#
H_TMS
H_TCK

of

of

of

VID1

RN4 8P4R-680RRN4 8P4R-680R

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

R63 62R0402R63 62R0402

RN5 8P4R-62R0402RN5 8P4R-62R0402

1
3
5
7

RN6 8P4R-62R0402RN6 8P4R-62R0402

1
3
5
7

RN7 8P4R-62R0402RN7 8P4R-62R0402

1
3
5
7

C65

C65

C0.1U16Y0402

C0.1U16Y0402

VTT_OUT_RIGHT

C57 C0.1U16Y0402C57 C0.1U16Y0402
C53 C0.1U16Y0402C53 C0.1U16Y0402

VID2
VID3
VID4
VID0

RN3 8P4R-680RRN3 8P4R-680R

VID5
VID6
VID7

PLACE BPM TERMINATION NEAR CPU

PLACE AT CPU END OF ROUTE

R66 62R0402R66 62R0402

FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED

1
3
5
7

RN35

RN35
8P4R-470R0402

8P4R-470R0402

Title

Title

Title

Intel LGA775 - Signals

Intel LGA775 - Signals

Intel LGA775 - Signals

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

2

H_PROCHOT#VTT_OUT_RIGHT

H_CPURST#

1

2

H_TESTHI13

3

4

MSID0

5

6

7

8

RN8

RN8
8P4R-62R0402

8P4R-62R0402

H_FSBSEL1

2

H_FSBSEL0

4

H_FSBSEL2

6
8

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

8

VCCP

AF9

AF8

AF22

AF21

U6B

AF19
AF18
AF15
AF14
AF12
AF11

AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11

AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23

AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23

AB8

AA8

U6B

VCC#AF19
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8

VCCP

VCC#AF8

VCC#AF22

VCC#AF21

VCC#Y29

VCC#Y30

VCC#Y8

Y8

Y29

Y30

VCC#AF9

VCC#Y28

Y28

VCCP

D D

C C

AG14

AG12

AG11

VCC#AG14

VCC#AG12

VCC#AG11

VCC#Y25

VCC#Y26

VCC#Y27

Y25

Y26

Y27

AG19

AG18

AG15

VCC#AG19

VCC#AG18

VCC#AG15

VCC#W8W8VCC#Y23

VCC#Y24

Y23

Y24

AG21

VCC#AG21

VCC#W30

W30

AG26

AG25

AG22

VCC#AG26

VCC#AG25

VCC#AG22

VCC#W27

VCC#W28

VCC#W29

W27

W28

W29

AG29

AG28

AG27

VCC#AG29

VCC#AG28

VCC#AG27

VCC#W24

VCC#W25

VCC#W26

W24

W25

W26

7

AG30

AG9

AG8

VCC#AG9

VCC#AG8

VCC#AG30

VCC#U8

VCC#V8

VCC#W23

V8

U8

W23

AH14

AH12

AH11

VCC#AH14

VCC#AH12

VCC#AH11

VCC#U28

VCC#U29

VCC#U30

U28

U29

U30

AH19

AH18

AH15

VCC#AH19

VCC#AH18

VCC#AH15

VCC#U25

VCC#U26

VCC#U27

U25

U26

U27

AH25

AH22

AH21

VCC#AH25

VCC#AH22

VCC#AH21

VCC#T8

VCC#U23

VCC#U24

T8

U23

U24

AH27

AH26

AH28

VCC#AH27

VCC#AH26

VCC#AH28

VCC#T28

VCC#T29

VCC#T30

T28

T29

T30

AH8

AH29

AH30

VCC#AH8

VCC#AH29

VCC#AH30

VCC#T25

VCC#T26

VCC#T27

T25

T26

T27

AH9

AJ11

AJ12

VCC#AH9

VCC#AJ11

VCC#T23

VCC#T24

R8

T23

T24

6

AJ14

AJ15

AJ18

VCC#AJ12

VCC#AJ14

VCC#AJ15

VCC#N8

VCC#P8

VCC#R8

P8

N8

N30

AJ19

AJ21

AJ22

VCC#AJ18

VCC#AJ19

VCC#AJ21

VCC#N28

VCC#N29

VCC#N30

N27

N28

N29

AJ8

AJ25

AJ26

VCC#AJ22

VCC#AJ25

VCC#AJ26

VCC#N25

VCC#N26

VCC#N27

N24

N25

N26

AJ9

AK11

VCC#AJ8

VCC#AJ9

VCC#AK11

VCC#M8

VCC#N23

VCC#N24

M8

N23

AK12

AK14

AK15

VCC#AK12

VCC#AK14

VCC#AK15

VCC#M28

VCC#M29

VCC#M30

M28

M29

M30

AK18

AK19

AK21

VCC#AK18

VCC#AK19

VCC#M26

VCC#M27

M25

M26

M27

AK22

AK25

AK26

VCC#AK21

VCC#AK22

VCC#AK25

VCC#M23

VCC#M24

VCC#M25

L8

M23

M24

AL11

AK8

AK9

VCC#AK8

VCC#AK9

VCC#AK26

VCC#K30

VCC#K8

VCC#L8

K8

K29

K30

5

AL12

AL14

AL15

VCC#AL11

VCC#AL12

VCC#AL14

VCC#K27

VCC#K28

VCC#K29

K26

K27

K28

AL18

AL19

AL21

VCC#AL15

VCC#AL18

VCC#AL19

VCC#K24

VCC#K25

VCC#K26

K23

K24

K25

AL22

AL25

AL26

VCC#AL21

VCC#AL22

VCC#AL25

VCC#J8

VCC#J9J9VCC#K23

J8

J30

AL29

AL30

AL8

VCC#AL26

VCC#AL29

VCC#AL30

VCC#J28

VCC#J29

VCC#J30

J27

J28

J29

AL9

AM11

VCC#AL8

VCC#AL9

VCC#AM11

VCC#J25

VCC#J26

VCC#J27

J25

J26

AM12

AM14

AM15

VCC#AM12

VCC#AM14

VCC#AM15

VCC#J22

VCC#J23

VCC#J24

J22

J23

J24

AM18

AM19

AM21

VCC#AM18

VCC#AM19

VCC#J20

VCC#J21

J19

J20

J21

AM22

AM25

AM26

VCC#AM21

VCC#AM22

VCC#AM25

VCC#AM26

VCC#J14

VCC#J15

VCC#J18

VCC#J19

J14

J15

J18

4

AM8

AM29

AM30

VCC#AM8

VCC#AM29

VCC#AM30

VCC#J11

VCC#J12

VCC#J13

J11

J12

J13

AM9

AN11

AN12

VCC#AM9

VCC#AN11

VCC#AN9

VCC#J10

J10

AN8

AN9

AN14

AN15

AN18

VCC#AN12

VCC#AN14

VCC#AN15

VCC#AN18

VTT_OUT_RIGHT

VTT_OUT_LEFT

VCC#AN26

VCC#AN29

VCC#AN30

VCC#AN8

AN26

AN29

AN30

AN19

AN21

AN22

VCC#AN19

VCC#AN21

VCC#AN22

VCC-IOPLL

VTTPWRGD

VTT_SEL

RSVD#F29

VCC#AN25

AN25

3

H_VCCA

A23

VCCA
VSSA

VCCPLL

VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30

H_VSSA

B23

VCCPLL

D23

H_VCCA

C23

A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30

VTT_PWG

AM6

VTT_OUT_RIGHT

AA1

VTT_OUT_LEFT

J1

VTT_SEL

F27
F29

ZIF-SOCK775-15u-in,ZIF-SOCK775-15u-in_TH

ZIF-SOCK775-15u-in,ZIF-SOCK775-15u-in_TH

V_FSB_VTT

VTT_OUT_RIGHT 4,6,19,27
VTT_OUT_LEFT 4

VTT_SEL 37

2

V_FSB_VTT

C166

C166
C10U10Y0805

C10U10Y0805
C183

C183
C10U10Y0805

C10U10Y0805
C160

C160
C10U10Y0805

C10U10Y0805

CAPS FOR FSB GENERIC

1

VTT_OUT_RIGHT

GTLREF VOLTAGE SHOULD BE

0.63*VTT = 0.756V

B B

VTT_OUT_RIGHT VTT_OUT_LEFT

GTLREF VOLTAGE SHOULD BE

0.63*VTT = 0.756V

A A

R65 61.9R1%0402R65 61.9R1%0402 R199 10R0402R199 10R0402

R67

R67
107R1%0402

107R1%0402

R193 61.9R1%0402R193 61.9R1%0402

R192

R192
107R1%0402

107R1%0402

VTT_OUT_LEFT

VCC5_SB

R24

R24
1KR0402

1KR0402

VID_GD#34,36,38

8

R84 4.7KR0402R84 4.7KR0402

R69 10R0402R69 10R0402

C58

C58
C1U6.3Y0402-RH

C1U6.3Y0402-RH

R188 10R0402R188 10R0402

C68

C68
C1U6.3Y0402-RH

C1U6.3Y0402-RH

R77 680R0402R77 680R0402

B

C60

C60
C220P16X0402

C220P16X0402

C67

C67
C220P16X0402

C220P16X0402

VTT_PWG

CE

Q13

Q13

N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

7

C59

C59
C1U6.3Y0402-RH

C1U6.3Y0402-RH

CPU_GTLREF0 4

CPU_GTLREF1 4

6

VTT_OUT_LEFT

GTLREF VOLTAGE SHOULD BE

0.63*VTT = 0.756V

GTLREF VOLTAGE SHOULD BE

0.63*VTT = 0.756V

R211 61.9R1%0402R211 61.9R1%0402

R217 X_61.9R1%0402R217 X_61.9R1%0402

R203

R203
107R1%0402

107R1%0402

R218

R218

X_107R1%0402

X_107R1%0402

+1.8V

C150

C150
C1U6.3Y0402-RH

C1U6.3Y0402-RH

5

C70

C70
C1U6.3Y0402-RH

C1U6.3Y0402-RH

R214 X_10R0402R214 X_10R0402

C73

C73
X_C1U6.3Y0402-RH

X_C1U6.3Y0402-RH

R107 2.2RR107 2.2R

U7

SC431LCSK-1TRT_SOT23-3L

SC431LCSK-1TRT_SOT23-3L

U7

C69

C69
C220P16X0402

C220P16X0402

C71

C71
X_C220P16X0402

X_C220P16X0402

1

2

3

4

R111

R111
1KR1%0402

1KR1%0402

R110

R110

4.75KR1%0402

4.75KR1%0402

CPU_GTLREF2 4

CPU_GTLREF3 4

C139

C139
C10U10Y0805

C10U10Y0805

VCCPLL

C136

C136
C1U6.3Y0402-RH

C1U6.3Y0402-RH

3

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS

V_FSB_VTT

CP2 X_CP003CP2 X_CP003

L7 X_30L3_15_0805L7 X_30L3_15_0805

21

C146

C146
C1U6.3Y0402-RH

C1U6.3Y0402-RH

Title

Title

Title

Size Document Number Rev

Size Document Number Rev

Size Document Number Rev

Date: Sheet

Date: Sheet

Date: Sheet

C138

C138
C10U10Y0805

C10U10Y0805

Intel LGA775 - Power

Intel LGA775 - Power

Intel LGA775 - Power

Custom

Custom

Custom

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

MS-7342-061226K1 1.0

2

C132

C132
X_C10U10Y0805

X_C10U10Y0805

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

MICRO-START INT'L CO.,LTD.

VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns

H_VCCA

H_VSSA

of

of

of

545Tuesday, December 26, 2006

545Tuesday, December 26, 2006

545Tuesday, December 26, 2006

1