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MS-7328
Schematics
40 pgs1.2 Mb0

MSI MS-7328 Schematics

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PageTitle
MS-7328 VER:0A
uATX(244mm X 244mm)
Cover Sheet 1 Block disgram 2 GPIO SPEC
D D
CPU:
AMD M2
System Chipset:
North Bridge --- SIS 761GX South Bridge --- SIS 966L
OnBoard Chipset:
Clock Gen:RTM866-759 AC'97 Codec:Reltek ALC655
C C
LAN:RTL 8201CLC (10/100) SIO:Winbond W83627 DHG Ver:C
Clock Distribution Power Sequence1-3 AMD M2_HT AMD M2 First Logic DDR2 DIMM DDR2.Termination Clock GEN Vcore RT8802 761GX -1 (PCI-E) 761GX -2 (MuTOL & Other) 761GX -3 (Power & GND) 761GX-4 (Power & Decoupling)
Main Memory:
966L-1 PCI, IDE, and MuTIOL
DDRI (533/667MHz) * 2
Expansion Slots:
PCI Express (X16) Slot * 1 PCI Express (X1) Slot * 1 PCI Slot * 2
B B
PWM:
Controller:RT8802A+3PHASE
ACPI:
WINBOND / MS6 Ver: RBF
Other:
966L-3 USB and SATA 966L-4 Power and Ground IDE Connectors PCIE X16 PCIE X1 PCI Connectors 1&2 USB Port RTL ALC655 RTL8201CL
3 4 5,6,7 8 9,10,11 12 13 14 15 16 17 18 19 20 21966L-2 PCI_Ex/GPIO 22 23 24 25 26 27 28 29
30 W83627 DHG&Floppy&ROM 31 ACPI Power Controller(MS-6) 32 VGA Connector & Fan 33
A A
KB/MS/LPT/COM Connectors Front Panel&System Regulator
34
35
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MSI
MS-7328 0A
MS-7328 0A
MS-7328 0A
1
of
140Tuesday, August 22, 2006
140Tuesday, August 22, 2006
140Tuesday, August 22, 2006
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1
VRM RT8802A
DESKTOP Athlon 64
3-Phase PWM
D D
HyperTransport LINK0
AM2
LINK0 16x16
DDR2 533,667
DDR2 533,667
External Clock Generator
UNBUFFERED DDR2 DIMM1
240-PIN DDR FIRST LOGICAL DIMM
UNBUFFERED DDR2 DIMM2
240-PIN DDR SECOND LOGICAL DIMM
SIS NB
DESKTOP
CRT
PCIE X16
C C
Rear port x 4
PCIE X16
USB2.0
Front port x 4
PCIE X1
Realtek 8201CL 10/100
PCIE X1
PCI BUS
761GX
MuTIOL
SIS SB
DESKTOP 966L
USB2.0 (4+4) SATA*2 AC97 ATA 66/100/133*2 LPC I/F INT RTC PCI SLOT*2 PCIE X1*1
AC LINK
SATA Link
ATA 66/100/133
VGA CON
ALC 655
SATA Port #1~2
IDE1
B B
PCI SLOT 2
761GX CORE & PCIE POWER & NB,SB POWER SEQUENCE
A A
ACPI MS6 CONTROLLER & DDR MEMORY POWER
5
4
PCI SLOT 1
W83627 DHG
LPTFLOPPY
*1 *1 *2
3
SERIAL
PORTS
FAN CONTROL
LPC I/F
FLASH BIOS
4M
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Block diagram
Block diagram
Block diagram
MSI
MS-7328 0A
MS-7328 0A
MS-7328 0A
1
of
240Wednesday, August 16, 2006
of
240Wednesday, August 16, 2006
of
240Wednesday, August 16, 2006
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PCI RESET DEVICE
Signals HDDRST# PCIDEVRST# LPC PCISLOTRST# PCIE x16,PCIE x1,PCI slot1&2
D D
Target
Primary IDE
JUMPER SETTING
JCMOS1 JAUD1
(1-2)NORMAL
(5-6) LINEOUT_R (9-10) LINEOUT_L
(2-3)CLEAR
DDR DIMM Config.
DEVICE
DIMM 1
DIMM 2
C C
1010000XB
1010001XB
CLOCKADDRESS
MEMCLK_H0/MEMCLK_L0 MEMCLK_H1/MEMCLK_L1 MEMCLK_H2/MEMCLK_L2 MEMCLK_H0/MEMCLK_L0 MEMCLK_H0/MEMCLK_L0 MEMCLK_H0/MEMCLK_L0
4
PCI Config.
DEVICE MCP1 INT Pin
PCI Slot 1
PCI Slot 2
LAN
LPC
SIO
PIRQ#A
PIRQ#C PIRQ#D PIRQ#C PIRQ#D PIRQ#A PIRQ#B
REQ#/GNT#
PREQ#0 PGNT#0
PREQ#1 PGNT#1
3
IDSEL
AD21
AD22
CLOCK
PCICLK1PIRQ#B
PCICLK2
LAN_PCLK
LPC_PCLK
SIO_PCLK
2
SB/GPIO
Name Function Description
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
NA
BIOS_WP#
THERM#(OVT# of SIO)
1K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
1K ohm Pull up to VCC3
NA
NA
1K ohm Pull up to 3VDUAL
NA
NA
LDTREQ#(SIS ap note A761GX-0-003)
NA
1
USB
Rear
Front
B B
A A
Port DATA +/-
USB1
LAN_USB1
JUSB1
JUSB2
USB1­USB1+ USB0­USB0+
USB2­USB2+ USB3­USB3+
USB4­USB4+ USB5­USB5+
USB6­USB6+ USB7­USB7+
OC#
USB_OC#1
( OC#0~1 )
USB_OC#2
( OC#2~3 )
USB_OC#4
( OC#4~5 )
USB_OC#6
( OC#6~7 )
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MS-7328 0A
MS-7328 0A
MS-7328 0A
Date: Sheet
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MSI
GPIO Spec
GPIO Spec
GPIO Spec
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340Wednesday, August 16, 2006
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340Wednesday, August 16, 2006
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340Wednesday, August 16, 2006
DIMM1 DIMM2
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D D
5,0,7
3 PAIR MEM CLK
Athlon64 uFCPGA M2
C C
4,1,6
3 PAIR MEM CLK
Single Chanel
14.318MHZ OSC INPUT
1 PAIR CPU CLK
200MHZ
EXTERNAL CLK GEN.
1PAIR NB CLK
200MHZ
NB-OSC
14.318MHZ
NB PCIE CLK
100MHZ
V-OSC
14.318MHZ
PCIE CLK
100MHZ
SB PCIE CLK
100MHZ
SB-OSC
14.318MHZ OSC INPUT
SIS761GX
PCIE GFX SLOT - 16 LANES
100MHZ
SB PCIE CLK
INPUT FOR SATA
USB CLK
48MHZ
SB_PCLK33
33MHZ
SATACLK
SIS SB
966L
AC97_BITCLK
32.768KHZ OSC INPUT
PCIE CLK
100MHZ
SUPER IO
AC97 CODEC
PCIE x1 SLOT
14.318MHZ
SIO_PCLK
33MHZ
100MHZ
KB_CLK
MS_CLK
B B
PCI CLK1
33MHZ
PCI CLK2
33MHZ
SIO_PCLK
33MHZ
PCI SLOT1
PCI SLOT2
LPC
KEYBOARD
MOUSE
A A
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Clock Distribution
Clock Distribution
Clock Distribution
MSI
MS-7328 0A
MS-7328 0A
MS-7328 0A
1
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440Wednesday, August 16, 2006
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440Wednesday, August 16, 2006
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440Wednesday, August 16, 2006
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D D
C C
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B B
A A
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Custom
Custom
Custom
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Power Sequence1
Power Sequence1
Power Sequence1
MSI
<Doc> <RevCode>
<Doc> <RevCode>
<Doc> <RevCode>
of
540Tuesday, August 15, 2006
540Tuesday, August 15, 2006
540Tuesday, August 15, 2006
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5
D D
C C
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1
B B
A A
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Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
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Power Sequence2
Power Sequence2
Power Sequence2
MSI
<Doc> <RevCode>
<Doc> <RevCode>
<Doc> <RevCode>
of
640Tuesday, August 15, 2006
640Tuesday, August 15, 2006
640Tuesday, August 15, 2006
1
5
D D
C C
4
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1
B B
A A
Title
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Custom
Custom
Custom
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Power Sequence3
Power Sequence3
Power Sequence3
MSI
<Doc> <RevCode>
<Doc> <RevCode>
<Doc> <RevCode>
of
740Tuesday, August 15, 2006
740Tuesday, August 15, 2006
740Tuesday, August 15, 2006
1
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CLKIP[1..0] CLKIN[1..0]
N6
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
N3
L0_CLKIN_H(0)
N2
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
U1
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
U6
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
R6
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
M4
L0_CADIN_H(11)
M5
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
M6
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
U3
L0_CADIN_H(7)
U2
L0_CADIN_L(7)
R1
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
R3
L0_CADIN_H(5)
R2
L0_CADIN_L(5)
N1
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
M1
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
CADIP[15..0] CADIN[15..0]
CADOP[15..0] CADON[15..0]
CLKOP[1..0] CLKON[1..0]
D D
CLKIP116 CLKIN116
VDD_12_A
C C
CLKIP016 CLKIN016
R1 51R1%0402R1 51R1%0402 R2 51R1%0402R2 51R1%0402
CTLIP016 CTLIN016
CLKIP1 CLKIN1 CLKIP0 CLKIN0
CTLIP1 CTLIN1 CTLIP0 CTLIN0
CADIP15 CADIN15 CADIP14 CADIN14 CADIP13 CADIN13 CADIP12 CADIN12 CADIP11 CADIN11 CADIP10 CADIN10 CADIP9 CADIN9 CADIP8 CADIN8
CADIP7 CADIN7 CADIP6 CADIN6 CADIP5 CADIN5 CADIP4 CADIN4 CADIP3 CADIN3 CADIP2 CADIN2 CADIP1 CADIN1 CADIP0 CADIN0 CADON0
U1A
U1A
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
CLKIP[1..0] 16 CLKIN[1..0] 16
CADIP[15..0] 16 CADIN[15..0] 16
CADOP[15..0] 16 CADON[15..0] 16
CLKOP[1..0] 16 CLKON[1..0] 16
AD5 AD4 AD1 AC1
Y6 W6 W2 W3
Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4
Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1
CLKOP1 CLKON1 CLKOP0 CLKON0
CTLOP0 CTLON0
CADOP15 CADON15 CADOP14 CADON14 CADOP13 CADON13 CADOP12 CADON12 CADOP11 CADON11 CADOP10 CADON10 CADOP9 CADON9 CADOP8 CADON8
CADOP7 CADON7 CADOP6 CADON6 CADOP5 CADON5 CADOP4 CADON4 CADOP3 CADON3 CADOP2 CADON2 CADOP1 CADON1 CADOP0
CLKOP1 16 CLKON1 16 CLKOP0 16 CLKON0 16
TP1TP1 TP2TP2
CTLOP0 16 CTLON0 16
B B
A A
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AMD M2_HT
AMD M2_HT
AMD M2_HT
MSI
MS-7328 0A
MS-7328 0A
MS-7328 0A
1
of
840Wednesday, August 23, 2006
of
840Wednesday, August 23, 2006
of
840Wednesday, August 23, 2006
5
MA0_CLK_H[2..0]12,13 MA0_CLK_L[2..0]12,13
MA0_CS#[1..0]12,13
MA0_ODT012,13
D D
MA_CAS#12,13 MA_WE#12,13 MA_RAS#12,13
MA_BANK[2..0]12,13
MA_CKE113 MA_CKE012,13
MA_ADD[15..0]12,13 MA_DQS_H[7..0]12 MA_DQS_L[7..0]12
MA_DM[7..0]12
MA_DATA[63..0]12
C C
MB0_CLK_H[2..0]12,13 MB0_CLK_L[2..0]12,13
MB0_CS#[1..0]12,13
MB0_ODT012,13
MB_CAS#12,13 MB_WE#12,13 MB_RAS#12,13
MB_BANK[2..0]12,13
MB_CKE113 MB_CKE012,13
MB_ADD[15..0]12,13 MB_DQS_H[7..0]12 MB_DQS_L[7..0]12
B B
MB_DM[7..0]12
MB_DATA[63..0]12
MA0_CLK_H[2..0] MA0_CLK_L[2..0] MA0_CS_#[1..0]
MA0_ODT0
MA_CAS# MA_WE# MA_RAS#
MA_BANK[2..0]
MA_CKE1 MA_CKE0
MA_ADD[15..0] MA_DQS_H[7..0] MA_DQS_L[7..0] MA_DM[7..0] MA_DATA[63..0]
MB0_CLK_H[2..0] MB0_CLK_L[2..0] MB0_CS#[1..0]
MB0_ODT0
MB_CAS# MB_WE# MB_RAS#
MB_BANK[2..0]
MB_CKE1 MB_CKE0
MB_ADD[15..0] MB_DQS_H[7..0] MB_DQS_L[7..0] MB_DM[7..0] MB_DATA[63..0]
MA0_CLK_H2 MA0_CLK_L2 MA0_CLK_H1 MA0_CLK_L1 MA0_CLK_H0 MA0_CLK_L0
MA0_CS#1 MA0_CS#0
MA0_ODT0
MA_CAS# MA_WE# MA_RAS#
MA_BANK2 MA_BANK1 MA_BANK0
MA_CKE1 MA_CKE0
MA_ADD15 MA_ADD14 MA_ADD13 MA_ADD12 MA_ADD11 MA_ADD10 MA_ADD9 MA_ADD8 MA_ADD7 MA_ADD6 MA_ADD5 MA_ADD4 MA_ADD3 MA_ADD2 MA_ADD1 MA_ADD0
MA_DQS_H7 MA_DQS_L7 MA_DQS_H6 MA_DQS_L6 MA_DQS_H5 MA_DQS_L5 MA_DQS_H4 MA_DQS_L4 MA_DQS_H3 MA_DQS_L3 MA_DQS_H2 MA_DQS_L2 MA_DQS_H1 MA_DQS_L1 MA_DQS_H0 MA_DQS_L0
MA_DM7 MA_DM6 MA_DM5 MA_DM4 MA_DM3 MA_DM2 MA_DM1 MA_DM0
AG21 AG20
AC25 AA24
AC28 AE20
AE19
AD27 AA25
AC27
AB25 AB27 AA26
AA27
AC26
AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28
AF15 AF19 AJ25
AH29
G19 H19 U27 U26
G20 G21 V27 W27
N25 Y27
M25 M27
N24 N26
P25 Y25 N27 R24 P27 R25 R26 R27
U25 W24
D29 C29 C25 D25 E19
G15
B29 E24 E18 H15
L27
T25 T27
F19 F15
MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0)
MA0_CS_L(1) MA0_CS_L(0)
MA0_ODT(0) MA1_CLK_H(2)
MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0)
MA1_CS_L(1) MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L MA_WE_L MA_RAS_L
MA_BANK(2) MA_BANK(1) MA_BANK(0)
MA_CKE(1) MA_CKE(0)
MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0)
MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0)
MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0)
4
U1B
U1B
MEMORY INTERFACE A
MEMORY INTERFACE A
MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10)
MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)
MA_DQS_H(8) MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0)
AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14
J28 J27
J25 K25
J26 G28 G27 L24 K27 H29 H27
MA_DATA63 MA_DATA62 MA_DATA61 MA_DATA60 MA_DATA59 MA_DATA58 MA_DATA57 MA_DATA56 MA_DATA55 MA_DATA54 MA_DATA53 MA_DATA52 MA_DATA51 MA_DATA50 MA_DATA49 MA_DATA48 MA_DATA47 MA_DATA46 MA_DATA45 MA_DATA44 MA_DATA43 MA_DATA42 MA_DATA41 MA_DATA40 MA_DATA39 MA_DATA38 MA_DATA37 MA_DATA36 MA_DATA35 MA_DATA34 MA_DATA33 MA_DATA32 MA_DATA31 MA_DATA30 MA_DATA29 MA_DATA28 MA_DATA27 MA_DATA26 MA_DATA25 MA_DATA24 MA_DATA23 MA_DATA22 MA_DATA21 MA_DATA20 MA_DATA19 MA_DATA18 MA_DATA17 MA_DATA16 MA_DATA15 MA_DATA14 MA_DATA13 MA_DATA12 MA_DATA11 MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MB0_CLK_H2 MB0_CLK_L2 MB0_CLK_H1 MB0_CLK_L1 MB0_CLK_H0 MB0_CLK_L0
MB0_CS#1 MB0_CS#0
MB0_ODT0
MB_CAS# MB_WE# MB_RAS#
MB_BANK2 MB_BANK1 MB_BANK0
MB_CKE1 MB_CKE0
MB_ADD15 MB_ADD14 MB_ADD13 MB_ADD12 MB_ADD11 MB_ADD10 MB_ADD9 MB_ADD8 MB_ADD7 MB_ADD6 MB_ADD5 MB_ADD4 MB_ADD3 MB_ADD2 MB_ADD1 MB_ADD0
MB_DQS_H7 MB_DQS_L7 MB_DQS_H6 MB_DQS_L6 MB_DQS_H5 MB_DQS_L5 MB_DQS_H4 MB_DQS_L4 MB_DQS_H3 MB_DQS_L3 MB_DQS_H2 MB_DQS_L2 MB_DQS_H1 MB_DQS_L1 MB_DQS_H0 MB_DQS_L0
MB_DM7 MB_DM6 MB_DM5 MB_DM4 MB_DM3 MB_DM2 MB_DM1 MB_DM0
3
U1C
U1C
MEMORY INTERFACE B
AJ19
AK19
AE30 AC31
AD29 AL19
AL18
W29 W28
AE29 AB31
AD31
AC29 AC30 AB29
AA31 AA28
M31 M29
AE31
AA29
AA30 AK13
AJ13
AK17
AJ17 AK23 AL23 AL28 AL29
AJ14 AH17
AJ23 AK29
A18 A19 U31 U30
C19 D19
N31
N28 N29
N30 P29
P31 R29 R28 R31 R30 T31 T29 U29 U28
D31 C31 C24 C23 D17 C17 C14 C13
C30 A23 B17 B13
MEMORY INTERFACE B
MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0)
MB0_CS_L(1) MB0_CS_L(0)
MB0_ODT(0) MB1_CLK_H(2)
MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0)
MB1_CS_L(1) MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L MB_WE_L MB_RAS_L
MB_BANK(2) MB_BANK(1) MB_BANK(0)
MB_CKE(1) MB_CKE(0)
MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0)
MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0)
MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0)
MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10)
MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0)
AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13
J31 J30
J29 K29
K31 G30 G29 L29 L28 H31 G31
MB_DATA63 MB_DATA62 MB_DATA61 MB_DATA60 MB_DATA59 MB_DATA58 MB_DATA57 MB_DATA56 MB_DATA55 MB_DATA54 MB_DATA53 MB_DATA52 MB_DATA51 MB_DATA50 MB_DATA49 MB_DATA48 MB_DATA47 MB_DATA46 MB_DATA45 MB_DATA44 MB_DATA43 MB_DATA42 MB_DATA41 MB_DATA40 MB_DATA39 MB_DATA38 MB_DATA37 MB_DATA36 MB_DATA35 MB_DATA34 MB_DATA33 MB_DATA32 MB_DATA31 MB_DATA30 MB_DATA29 MB_DATA28 MB_DATA27 MB_DATA26 MB_DATA25 MB_DATA24 MB_DATA23 MB_DATA22 MB_DATA21 MB_DATA20 MB_DATA19 MB_DATA18 MB_DATA17 MB_DATA16 MB_DATA15 MB_DATA14 MB_DATA13 MB_DATA12 MB_DATA11 MB_DATA10
MB_DATA9 MB_DATA8 MB_DATA7 MB_DATA6 MB_DATA5 MB_DATA4 MB_DATA3 MB_DATA2 MB_DATA1 MB_DATA0
2
1
A A
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
M2_2 DDR2
M2_2 DDR2
M2_2 DDR2
MSI
MS-7328 0A
MS-7328 0A
MS-7328 0A
1
of
940Wednesday, August 23, 2006
of
940Wednesday, August 23, 2006
of
940Wednesday, August 23, 2006
5
4
3
2
1
VDD_18_SUS
VDD_18_SUS
L1
R8
R8 15R1%0805
C13
C13
C10U16Y1206
C10U16Y1206
D D
15R1%0805
R14
R14 15R1%0805
15R1%0805
VDD_18_SUS
R19 300R0402R19 300R0402 R20 300R0402R20 300R0402
R21 300R0402R21 300R0402 R22 300R0402R22 300R0402 R23 300R0402R23 300R0402
PLACE NEAR CPU SOCKET
CPU_M_VREF
C15
C15
C1000P50X0402
C1000P50X0402
C14
C14
C0.1U25Y0402-RH
C0.1U25Y0402-RH
CPU_DBREQ# CPU_TCK
CPU_TMS CPU_TDI CPU_TRST#
C16
C16
C1000P50X0402
C1000P50X0402
CPUCLK0_H14 CPUCLK0_L14
VDDA_25
CPUCLK0_H CPUCLK0_L
HT Bus Level shift
Q2
3VDUAL
3VDUAL
Q2
D S
Q21
Q21
D S
G
N-2N7002_SOT23
N-2N7002_SOT23
G
-LDTRST_NB-LDTRST_L
N-2N7002_SOT23
N-2N7002_SOT23
C C
CPU_GD32
-LDTRST_NB16
-LDTRST_NB
CPU_PWRGD_L CPU_PWRGDCPU_PWRGD
L1
40L3_25_0805
40L3_25_0805
2 1
C4.7U10Y0805
C4.7U10Y0805
C9
C9
C8
C8
C3300P50X
C3300P50X
C11 C3900P50XC11 C3900P50X
R6
R6
169R1%0402
169R1%0402
C12 C3900P50XC12 C3900P50X
AMD:R6 to169R 08/15/06
CPU_VDDA_25
12
C10
C10
C0.22U16X
C0.22U16X
CLKIN_H CLKIN_L
VDD_18_SUS
VCC_VRM_SENSE15 VSS_VRM_SENSE15
TP6TP6
R10 39.2/4/1%R10 39.2/4/1% R12 39.2/4/1%R12 39.2/4/1%
R15 300R0402R15 300R0402 R16 300R0402R16 300R0402
TP8TP8 TP10TP10 TP12TP12 TP14TP14 TP15TP15
THERMDC_CPU31
THERMDA_CPU31
CPU_PWRGD_L
-LDTSTOP_L
-LDTRST_L CPU_PRESENT#
CPU_SIC CPU_SID
CPU_TDI CPU_TRST# CPU_TCK CPU_TMS
CPU_DBREQ#
VCC_VRM_SENSE VSS_VRM_SENSE
CPU_VTT_SENSE
CPU_M_VREF CPU_M_ZN CPU_M_ZP
CPU_TEST25_H CPU_TEST25_L CPU_PLLTEST0 CPU_PLLTEST1
CPU_BP3 CPU_BP2 CPU_BP1 CPU_BP0 CPU_SSEN_B
CLKIN_H CLKIN_L
AL10 AJ10
AH10
AH11
AJ11
C10 D10
AL3
AL6 AK6
AL9
E12
F12
A10 B10 F10
AJ7
AH9
AJ5 AG9 AG8 AH7 AJ6
A8 B8
C9 D8 C7
A5
G2 G1
E9 F6
D6
E7 F8
C5
E5
U1D
U1D
MISC
MISC
VDDA1 VDDA2
CLKIN_H CLKIN_L
PWROK LDTSTOP_L RESET_L
CPU_PRESENT_L
THERMTRIP_L
SIC SID
TDI TRST_L TCK TMS
DBREQ_L VDD_FB_H
VDD_FB_L VTT_SENSE
M_VREF M_ZN M_ZP
TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9
TEST17 TEST16 TEST15 TEST14 TEST12
TEST7 TEST6 TEST5 TEST4 TEST3 TEST2
VID(5) VID(4) VID(3) VID(2) VID(1) VID(0)
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H VDDIO_FB_L
PSI_L
HTREF1 HTREF0
TEST29_H
TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H
TEST28_L
TEST27 TEST26 TEST10
TEST8
300R0402R3300R0402
CPU_VID5
D2
CPU_VID4
D1
CPU_VID3
C1
CPU_VID2
E3
CPU_VID1
E2
CPU_VID0
E1
CPU_THERMTRIP#
AK7
PROCHOT#
AL7
CPU_TDO
AK10
CPU_DBRDY
B6
CPU_VDDIO_FB_H
AK11
CPU_VDDIO_FB_L
AL11
CPU_PSI_L
F1
CPU_HTREF1
V8
CPU_HTREF0
V7
CPU_TEST29_H
C11
CPU_TEST29_L
D11
AK8
CPU_TEST23
AH8 AJ9
CPU_SCAN_EN
AL8
CPU_SC2
AJ8 J10
H9 AK9
CPU_TEST26
AK5 G7 D4
R3
R4
300R0402R4300R0402
TP7TP7
R9 44.2R1%R9 44.2R1% R11 44.2R1%R11 44.2R1%
TP9TP9 TP11TP11 TP13TP13
TP16TP16
R18 300R0402R18 300R0402
R5
300R0402R5300R0402
VDD_18_SUS
R7 300R0402R7 300R0402
R17 300R0402R17 300R0402
VDD_18_SUS
CPU_VID5 15 CPU_VID4 15 CPU_VID3 15 CPU_VID2 15 CPU_VID1 15 CPU_VID0 15
PROCHOT# 21
1 2
3VDUAL
147
U47A X_LVC07A_SOIC14U47A X_LVC07A_SOIC14
-LDTSTOP_NB16
B B
VCC_DDR
VCC3
R494
Q45
Q45
R494 X_4.7KR0402
X_4.7KR0402
2 4 6 8 10 12 14 16 18 20 22 24 26
-LDTRST_NBJ1_LDT_RST
J1_LDT_RST
VRM_GD15,32
-LDTRST_NB16
CPU_GD32
4
-LDTRST_NB
CPU_GD
3
R325
R325
X_1KR0402
KEY
KEY
X_1KR0402
X_N-MMBT3904_NL_SOT23
X_N-MMBT3904_NL_SOT23
J1
J1
SW1 X_SW-TACT4PSSW1 X_SW-TACT4PS
1 2
CPU_DBREQ# CPU_DBRDY CPU_TCK CPU_TMS CPU_TDI CPU_TRST#
A A
CPU_TDO
3 4
5
R63 X_100R0402R63 X_100R0402
VCC_DDR
1 3 5 7
9 11 13 15 17 19 21 23
X_hdr_k8_hdt/B
X_hdr_k8_hdt/B
1 2
3VDUAL
147
U47B X_LVC07A_SOIC14U47B X_LVC07A_SOIC14
3 4
3VDUAL
5 6
3VDUAL
9 8
3VDUAL
147
U47E
U47E
11 10
X_LVC07A_SOIC14
X_LVC07A_SOIC14
3VDUAL
147
U47F
U47F
13 12
X_LVC07A_SOIC14
X_LVC07A_SOIC14
147
U47C X_LVC07A_SOIC14U47C X_LVC07A_SOIC14
147
U47D
U47D
X_LVC07A_SOIC14
X_LVC07A_SOIC14
R477 0R0402R477 0R0402
R478
R478 0R0402
0R0402
R479
R479
0R0402
0R0402
-LDTSTOP_L-LDTSTOP_NB
R480
R480 X_0R0402
X_0R0402
-LDTRST_L
-LDTRST_L
R481
R481 X_0R0402
X_0R0402
CPU_PWRGD_L
R482
R482 X_0R0402
X_0R0402
CPU_THERMTRIP#
2
VDD_18_SUS
AMD:R474,R475,R476 to 300R 08/15/06
VDD_18_SUS
CP24 X_COPPERCP24 X_COPPER
VDD_12_A
R13
R13
80.6R1%0402
80.6R1%0402
For DHG ADD R464, add R462
SIO_THERM_SIC31
SIO_THERM_SID31
3VDUAL
R856
R856
24.9KR1%0402
24.9KR1%0402
R855
R855
10KR0402
10KR0402
Title
Title
Title
MSI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7328 0A
MS-7328 0A
MS-7328 0A
Date: Sheet
Date: Sheet
Date: Sheet
R474 300R0402R474 300R0402 R475 300R0402R475 300R0402 R476 300R0402R476 300R0402
R25 1KR1%0402R25 1KR1%0402
R27 X_300R0402R27 X_300R0402 R28 510R0402R28 510R0402 R29 510R0402R29 510R0402 R26 300R0402R26 300R0402
R464 0R0402R464 0R0402
R462 0R0402R462 0R0402
VDD_18_SUS
R466
R466 10KR0402
10KR0402
Q43
Q43 N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
Q44
Q44 N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
M2_3 CTRL & DEBUG
M2_3 CTRL & DEBUG
M2_3 CTRL & DEBUG
1
CPU_PWRGD_L
-LDTSTOP_L
CPU_PRESENT#
CPU_SID CPU_TEST25_H CPU_TEST25_L CPU_SIC
CPU_SIC
CPU_SID
SB_THERMTRIP# 21
10 40Monday, August 28, 2006
10 40Monday, August 28, 2006
10 40Monday, August 28, 2006
-LDTRST_L
of
of
of
5
4
3
2
1
VCCP
U1F
U1F
VDD1
VDD1
A4
VDD1
A6
VDD2
AA8
VDD3
AA10
VDD4
AA12
VDD5
AA14
VDD6
AA16
VDD7
AA18
VDD8
AB7
D D
C C
B B
AB11
AC10
AE10
AB9 AC4
AC5 AC8
AD2 AD3 AD7 AD9
AF7 AF9 AG4 AG5 AG7 AH2 AH3
E10
G10 G12
H11 H23
K11 K13 K15 K17 K19 K21 K23
Y17 Y19
VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41 VDD42
F5
VDD43
F7
VDD44
F9
VDD45
F11
VDD46
G6
VDD47
G8
VDD48 VDD49 VDD50
H7
VDD51 VDD52 VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75 VDD150 VDD151
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74
VSS240 VSS241
A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5 AE9 AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16
VCCP
M11 M13 M15 M17 M19
N10 N12 N14 N16 N18
P11 P13 P15 P17 P19
R10 R12 R14 R16 R18 R20
U10 U12 U14 U16 U18 U20
V11 V13 V15 V17 V19 V21
W10 W12 W14 W16 W18 W20
Y11 Y13 Y15 Y21
U1I
U1I
VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4
VTT5 VTT6 VTT7 VTT8 VTT9
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28
VDD_12_A
H6 H5 H2 H1
AK12 AJ12 AH12 AG12 AL12
K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15
C56
C56
C4.7U6.3X5-1
C4.7U6.3X5-1
1 2
Place near Socket M2
C21
C21
1 2 C4.7U6.3X5-1
C4.7U6.3X5-1
C0.22U16X
C0.22U16X
C29
C29
C0.22U16X
C0.22U16X
C36
C36
C37
C37
C0.22U16X
C0.22U16X
C44
C44 C0.22U10Y0402
C0.22U10Y0402
Bottom Side
VDD_12_A
C30
C30
C1000P50X
C1000P50X
C22
C22
C0.22U16X
C0.22U16X
C1000P50X
C1000P50X
C31
C31
C38
C38
C1000P50X
C1000P50X
C23
C23
C0.22U16X
C0.22U16X
AMD: Change C24 C25 to 180pF
C32
C32 C180P50N0402
C180P50N0402
C1000P50X
C1000P50X
C41
C41
C39
C39
C180P50N0402
C180P50N0402
C45
C45 C0.22U10Y0402
C0.22U10Y0402
C4.7U6.3X5-1
C4.7U6.3X5-1
C20
C20
C19
C19
1 2
1 2 C4.7U6.3X5-1
C4.7U6.3X5-1
Place as Close to Socket M2 as Possible
VTT_DDR_SUS
C4.7U6.3X5-1
C4.7U6.3X5-1
C27
C27
C28
1 2
C4.7U6.3X5-1
C4.7U6.3X5-1
C35
C35
1 2
C43
C43 C0.22U10Y0402
C0.22U10Y0402
C28
C0.22U16X
C0.22U16X
1 2 C4.7U6.3X5-1
C4.7U6.3X5-1
VTT_DDR_SUS
1 2 C4.7U6.3X5-1
C4.7U6.3X5-1
VDD_18_SUS
C42
C42 C0.22U10Y0402
C0.22U10Y0402
C26
C26
C34
C34
VDD_18_SUS
C24
C24 C180P50N0402
C180P50N0402
C33
C33
C180P50N0402
C180P50N0402
C40
C40 C180P50N0402
C180P50N0402
C46
C46 C0.22U10Y0402
C0.22U10Y0402
C25
C25
C180P50N0402
C180P50N0402
U1G
U1G
VDD2
L14 L16 L18
T11 T13 T15 T17 T19 T21
VDD2
VDD1 VDD2 VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7 VDD8 VDD9 VDD10 VDD11 VDD12
N8
VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
P7
VDD19
P9
VDD20 VDD21 VDD22 VDD23 VDD24 VDD25
R4
VDD26
R5
VDD27
R8
VDD28 VDD29 VDD30 VDD31 VDD32 VDD33 VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38 VDD39 VDD40 VDD41 VDD42 VDD43 VDD44
U8
VDD45 VDD46 VDD47 VDD48 VDD49 VDD50 VDD51
V9
VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58
W4
VDD59
W5
VDD60
W8
VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71 VDD72 VDD73 VDD74 VDD75
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75
AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18 H22 H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18
VCCP
AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 AC12 AC14 AC16 AC18 AC20 AC22 AD11 AD23 AE12 AF11
M21 M23
W22
L20 L22
N20 N22 P21 P23 R22 T23 U22 V23
Y23
U1H
U1H
VDD3
VDD3
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD29 VDD30 VDD31 VDD32
5
GND
6
GND
7
GND
8
GND
1
GND
2
GND
3
GND
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65
N17 N19 N21 N23 P2 P3 P8 P10 P12 P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22
C18
C18
C4.7U6.3X5-1
C4.7U6.3X5-1
1 2
VTT_DDR_SUS VTT_DDR_SUS
D12 C12
AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30 AF30
M24 M26 M28 M30
B12 A12
P24 P26 P28 P30 T24 T26 T28 T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29
VDD_18_SUS
VDDIO
VDDIO
AJ4
VLDT_A1
AJ3
VLDT_A2
AJ2
VLDT_A3
AJ1
VLDT_A4 VTT1
VTT2 VTT3 VTT4
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29
Place Decoupling Capacitors on Bottom Side underneath Socket M2
VCCP
C54
C22U6.3X50805-RH
C22U6.3X50805-RH
C70
C70
C4.7U6.3X5-1
C4.7U6.3X5-1
C54
C55
C55
C22U6.3X50805-RH
C22U6.3X50805-RH
12
C72
C72
C4.7U6.3X5-1
C4.7U6.3X5-1
4
C73
C73
C0.22U16X
C0.22U16X
C22U6.3X50805-RH
C22U6.3X50805-RH
C74
C74
C0.01U50X
C0.01U50X
C75
C75
C10P16N
C10P16N
C47
C47
C48
C48
VCCP VDD_18_SUS
C22U6.3X50805-RH
C22U6.3X50805-RH
A A
C62
C62
C63
C63
C0.22U16X
C0.22U16X
C64
C64
C0.22U16X
C0.22U16X
C22U6.3X50805-RH
C22U6.3X50805-RH
C0.22U16X
C0.22U16X
C65
C65
5
C49
C49
C22U6.3X50805-RH
C22U6.3X50805-RH
C0.22U16X
C0.22U16X
C50
C50
C66
C66
C180P50N
C180P50N
C22U6.3X50805-RH
C22U6.3X50805-RH
C67
C67
C22U6.3X50805-RH
C22U6.3X50805-RH
C51
C51
C22U6.3X50805-RH
C22U6.3X50805-RH
C68
C68
C22U6.3X50805-RH
C22U6.3X50805-RH
C52
C52
C22U6.3X50805-RH
C22U6.3X50805-RH
12
C53
C53
12
C69
C69
C4.7U6.3X5-1
C4.7U6.3X5-1
AMD Add C147,C154,C155,C465,C475,C482
VCCP
12
C149
C149
C4.7U6.3X5-1
C4.7U6.3X5-1
C147
C147
C22U6.3X50805-RH
C22U6.3X50805-RH
Bottom Side
C154
C154
C22U6.3X50805-RH
C22U6.3X50805-RH
C155
C155
C22U6.3X50805-RH
C22U6.3X50805-RH
3
C465
C465
C22U6.3X50805-RH
C22U6.3X50805-RH
C475
C475
C22U6.3X50805-RH
C22U6.3X50805-RH
C482
C482
C22U6.3X50805-RH
C22U6.3X50805-RH
2
C71 C180P50NC71 C180P50N C61 C180P50NC61 C180P50N C60 C180P50NC60 C180P50N
AMD Add C71,C61,C60
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
M2_4 PWR & GND
M2_4 PWR & GND
M2_4 PWR & GND
MSI
MS-7328 0A
MS-7328 0A
MS-7328 0A
1
of
11 40Monday, August 28, 2006
of
11 40Monday, August 28, 2006
of
11 40Monday, August 28, 2006
5
VDD_18_SUS
170
175
181
191
194
78
172
178
184
187
189
197
VCC3 VCC3
238
MA_ADD0
188
MA_ADD1
D D
C C
MA_DQS_H0 MA_DQS_H1 MA_DQS_H2 MA_DQS_H3 MA_DQS_H4 MA_DQS_H5 MA_DQS_H6 MA_DQS_H7
MA_DQS_L0 MA_DQS_L1 MA_DQS_L2 MA_DQS_L3 MA_DQS_L4 MA_DQS_L5 MA_DQS_L6 MA_DQS_L7
B B
MA_CAS# MA_WE#
MA0_CS#0 MA0_CS#1 MA_CKE0
MA0_CLK_H0 MA0_CLK_H1 MA0_CLK_H2 MA0_CLK_L0 MA0_CLK_L1 MA0_CLK_L2
183
MA_ADD2
63
MA_ADD3
182
MA_ADD4
61
MA_ADD5
60
MA_ADD6
180
MA_ADD7
58
MA_ADD8
179
MA_ADD9
177
MA_ADD10
70
MA_ADD11
57
MA_ADD12
176
MA_ADD13
196
MA_ADD14
174
MA_ADD15
173
MA_BANK0
71
MA_BANK1
190
MA_BANK2
54
MA_DM0
125
MA_DM1
134
MA_DM2 MA_DATA24
146
MA_DM3
155
MA_DM4
202
MA_DM5
211
MA_DM6
223
MA_DM7
232 164
126 135 147 156 203 212 224 233 165
7 16 28 37 84 93
105 114
46
6 15 27 36 83 92
104 113
45 42
43 48 49
161 162 167 168
MA_RAS#
192
74 73
193
76 52
171 185
137 220 186 138 221
VDD
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
BA0 BA1 BA2
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
NC(DQS9#) NC(DQS10#) NC(DQS11#) NC(DQS12#) NC(DQS13#) NC(DQS14#) NC(DQS15#) NC(DQS16#) NC(DQS17#)
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS8#
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
RAS# CAS# WE#
S0# S1# CKE0 CKE1
CK0 CK1 CK2 CK0# CK1# CK2#
VDD69VDD
VSS
237
A A
MA0_CLK_H[2..0]9,13 MA0_CLK_L[2..0]9,13
MA_DQS_H[7..0]9 MA_DQS_L[7..0]9
MA_DM[7..0]9 MA_BANK[2..0]9,13 MA_ADD[15..0]9,13
MA_DATA[63..0]9
MA0_CLK_H[2..0] MA0_CLK_L[2..0]
MA_DQS_H[7..0]
MA_DQS_L[7..0] MA_DM[7..0] MA_BANK[2..0] MA_ADD[15..0] MA_DATA[63..0]
5
VDD
VDD53VDD
VDD59VDD64VDD
VDD67VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
216
219
222
225
228
231
234
VDDQ62VDDQ
VDDQ72VDDQ
VDDQ75VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
166
169
198
201
204
207
210
213
MA0_ODT09,13 MB_ADD[15..0]9,13 MA_CKE09,13 MA_CAS#9,13 MA_WE#9,13 MA_RAS#9,13
MA0_CS#[1..0]9,13
2
VDDQ
VDDQ51VDDQ
VDDQ56VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
127
130
133
136
139
142
145
148
151
154
157
160
163
MA0_ODT0 MA_CKE0 MA_CAS# MA_WE# MA_RAS# MA0_CS#[1..0]
4
3
2
1
VDD_18_SUS
170
175
181
191
194
78
172
178
184
187
189
238
188 183
63
182
61 60
180
58 179 177
70
57 176 196 174 173
71 190
54 125
134 146 155 202 211 223 232 164
126 135 147 156 203 212 224 233 165
16
28
37
84
93 105 114
46
15
27
36
83
92 104 113
45
42
43
48
49 161 162 167 168
192
74
73 193
76
52 171
185 137 220 186 138 221
MB0_CLK_H[2..0]9,13
MB0_CLK_L[2..0]9,13
MB_DATA[63..0]9
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15
BA0 BA1 BA2
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
NC(DQS9#) NC(DQS10#) NC(DQS11#) NC(DQS12#) NC(DQS13#) NC(DQS14#) NC(DQS15#) NC(DQS16#) NC(DQS17#)
7
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
6
DQS0# DQS1# DQS2# DQS3# DQS4# DQS5# DQS6# DQS7# DQS8#
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
RAS# CAS# WE#
S0# S1# CKE0 CKE1
CK0 CK1 CK2 CK0# CK1# CK2#
MB0_CS#[1..0]9,13
197
VDD
VDD53VDD
VDD59VDD64VDD
VDD67VDD
VDD69VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
216
219
222
225
228
231
234
237
MB0_ODT09,13 MB_CAS#9,13 MB_WE#9,13
MB_CKE09,13
MB0_ODT0 MB_CAS# MB_WE# MB0_CS#[1..0] MB_CKE0 MB0_CLK_H[2..0] MB0_CLK_L[2..0] MB_DATA[63..0]
VDDQ62VDDQ
VDDQ72VDDQ
VDDQ75VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
166
169
198
201
204
207
210
213
2
DIMM1
DIMM1
VSS85VSS82VSS79VSS66VSS65VSS50VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS
MA_DATA0
3
DQ0
MA_DATA1
4
DQ1
MA_DATA2
9
DQ2
MA_DATA3
10
DQ3
MA_DATA4
122
DQ4
MA_DATA5
123
DQ5
MA_DATA6
128
DQ6
MA_DATA7
129
DQ7
MA_DATA8
12
DQ8
MA_DATA9
13
DQ9
MA_DATA10
21
DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
NC(TEST)
NC(Err_Out#)
NC(Par_In)
ODT0 ODT1
RESET#
VREF
VSS
106
109
112
115
118
121
124
103
100
MB_DQS_H[7..0]9
SMBCLK14,21,25,26,27,31,32 SMBDAT14,21,25,26,27,31,32
MB_BANK[2..0]9,13
MB_DM[7..0]9
MB_DQS_L[7..0]9
DDRII-240_blue-RH
DDRII-240_blue-RH
VSS88VSS91VSS94VSS97VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MB_RAS#9,13
4
SCL SDA
SA0 SA1 SA2
NC
MA_DATA11
22
MA_DATA12
131
MA_DATA13
132
MA_DATA14
140
MA_DATA15
141
MA_DATA16
24
MA_DATA17
25
MA_DATA18
30
MA_DATA19
31
MA_DATA20
143
MA_DATA21
144
MA_DATA22
149
MA_DATA23
150 33
MA_DATA25
34
MA_DATA26
39
MA_DATA27
40
MA_DATA28
152
MA_DATA29
153
MA_DATA30
158
MA_DATA31
159
MA_DATA32
80
MA_DATA33
81
MA_DATA34
86
MA_DATA35
87
MA_DATA36
199
MA_DATA37
200
MA_DATA38
205
MA_DATA39
206
MA_DATA40
89
MA_DATA41
90
MA_DATA42
95
MA_DATA43
96
MA_DATA44
208
MA_DATA45
209
MA_DATA46
214
MA_DATA47
215
MA_DATA48
98
MA_DATA49
99
MA_DATA50
107
MA_DATA51
108
MA_DATA52
217
MA_DATA53
218
MA_DATA54
226
MA_DATA55
227
MA_DATA56
110
MA_DATA57
111
MA_DATA58
116
MA_DATA59
117
MA_DATA60
229
MA_DATA61
230
MA_DATA62
235
MA_DATA63
236
SMBCLK
120
SMBDAT
119 239
240 101
102 55 68 19
MA0_ODT0
195 77
18 1
SMBCLK SMBDAT MB_ADD[15..0] MB_BANK[2..0] MB_DM[7..0] MB_DQS_H[7..0] MB_DQS_L[7..0]
MB_RAS#
VDD_18_SUS
R30
R30
10KR0402
10KR0402
VDD_18_SUS
56.2R1%0402
56.2R1%0402
56.2R1%0402
56.2R1%0402
C76
C76 C0.1U25Y0402-RH
R32
R32
C0.1U25Y0402-RH
MEM_VREF
C77
R33
R33
C77 C0.1U25Y0402-RH
C0.1U25Y0402-RH
3
MB_ADD0 MB_ADD1 MB_ADD2 MB_ADD3 MB_ADD4 MB_ADD5 MB_ADD6 MB_ADD7 MB_ADD8 MB_ADD9 MB_ADD10 MB_ADD11 MB_ADD12 MB_ADD13 MB_ADD14 MB_ADD15
MB_BANK0 MB_BANK1 MB_BANK2
MB_DM0 MB_DM1 MB_DM2 MB_DM3 MB_DM4 MB_DM5 MB_DM6 MB_DM7
MB_DQS_H0 MB_DQS_H1 MB_DQS_H2 MB_DQS_H3 MB_DQS_H4 MB_DQS_H5 MB_DQS_H6 MB_DQS_H7
MB_DQS_L0 MB_DQS_L1 MB_DQS_L2 MB_DQS_L3 MB_DQS_L4 MB_DQS_L5 MB_DQS_L6 MB_DQS_L7
MB_RAS# MB_CAS# MB_WE#
MB0_CS#0 MB0_CS#1 MB_CKE0
MB0_CLK_H0 MB0_CLK_H1 MB0_CLK_H2 MB0_CLK_L0 MB0_CLK_L1 MB0_CLK_L2
C78
C78 C100P50N0402
C100P50N0402
2
VDDQ
VDDQ51VDDQ
VDDQ56VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
124
127
130
133
136
139
142
145
148
151
154
157
160
163
Title
Title
Title
MSI
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7328 0A
MS-7328 0A
MS-7328 0A
Date: Sheet
Date: Sheet
Date: Sheet
DIMM2
DIMM2
VSS85VSS82VSS79VSS66VSS65VSS50VSS47VSS44VSS41VSS38VSS35VSS32VSS29VSS26VSS23VSS20VSS17VSS14VSS11VSS8VSS5VSS
3
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
120
SCL
119
SDA
239
SA0
240
SA1
101
SA2
102
NC(TEST)
NC(Par_In)
NC
ODT0 ODT1
RESET#
VREF
VSS88VSS91VSS94VSS97VSS
DDRII-240_blue-RH
DDRII-240_blue-RH
55 68 19
195 77
18 1
NC(Err_Out#)
First Logic DDR2 DIMM
First Logic DDR2 DIMM
First Logic DDR2 DIMM
1
MB_DATA0 MB_DATA1 MB_DATA2 MB_DATA3 MB_DATA4 MB_DATA5 MB_DATA6 MB_DATA7 MB_DATA8 MB_DATA9 MB_DATA10 MB_DATA11 MB_DATA12 MB_DATA13 MB_DATA14 MB_DATA15 MB_DATA16 MB_DATA17 MB_DATA18 MB_DATA19 MB_DATA20 MB_DATA21 MB_DATA22 MB_DATA23 MB_DATA24 MB_DATA25 MB_DATA26 MB_DATA27 MB_DATA28 MB_DATA29 MB_DATA30 MB_DATA31 MB_DATA32 MB_DATA33 MB_DATA34 MB_DATA35 MB_DATA36 MB_DATA37 MB_DATA38 MB_DATA39 MB_DATA40 MB_DATA41 MB_DATA42 MB_DATA43 MB_DATA44 MB_DATA45 MB_DATA46 MB_DATA47 MB_DATA48 MB_DATA49 MB_DATA50 MB_DATA51 MB_DATA52 MB_DATA53 MB_DATA54 MB_DATA55 MB_DATA56 MB_DATA57 MB_DATA58 MB_DATA59 MB_DATA60 MB_DATA61 MB_DATA62 MB_DATA63
SMBCLK SMBDAT
VDD_18_SUS
MB0_ODT0
MEM_VREFMEM_VREF
VCC3
R31
R31
10KR0402
10KR0402
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12 40Wednesday, August 23, 2006
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12 40Wednesday, August 23, 2006
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12 40Wednesday, August 23, 2006
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