MSI MS-7324 Schematics
1
COVER SHEET
BLOCK DIAGRAM
CLOCK MAP
POWER MAP
1
2
MS-7324M1 VER:0A
3
4
CPU: [95Watt]
Intel Conroe
GPIO & JUMPER SETTING
Intel LGA775-CPU
VRM11 Intersil 6312 3Phase
Intel Lakeport -MCH
DDR II DIMM 1and DIMM2 1 & 2&3 & 4
PCI EXPRESS X16 SLOT
VGA CONNECTOR
Clock Generator - ICS954119
5
6-8
9
10-13
14-16
17
18
19
Intel Prescott, Cendar Mill, Smithfield Under 95Watt
System Chipset:
Intel Lakeport - GMCH (North Bridge)
Intel ICH7 DH (South Bridge)
Main Memory:
DDR II * 4 (Max 4GB)
On Board Chipset:
ICH7 DH
A A
PCI Slot 1 & 2
20-22
23
BIOS -- FWH FLASH 4Mb
Azalia CODEC -- ALC888
FWH
LAN - 82562EZ
VIA VT-6308P
24
25
26
LPC Super I/O -- W83627DHG
LAN - Intel 82562EZ
1394 -- VIA VT-6308P
Clock Generator - ICS954119
USB CONNECTORS
Azalia CODEC(ALC888)
SIO-W83627DHG & KB/MS/FDD/VFCD
27
28
29
Expansion Slots:
PCI Express X16 SLOT * 1
PCI Express X1 SLOT * 1
ATX,F_ PANEL,FAN CONTROL
30
PCI 2.3 SLOT * 2, 2Master
IDE & SATA&LPT
MS7 ACPI Controller
Auto BOM manual
PWOK MAP
31
32
33
34
35History
Intersil PWM:
VRM11 ISL6312 3-phase
1
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
Date: Sheet of
MICRO-START INT'L CO.,LTD.
COVER SHEET
COVER SHEET
COVER SHEET
MS-7324M1
MS-7324M1
MS-7324M1
of
135Tuesday, August 01, 2006
135Tuesday, August 01, 2006
135Tuesday, August 01, 2006
A
A
A
VRM_GD
1
VTT_PWG
PCIRST#2
HD_RST#
VRM 11
3-Phase PWM
Intersil 6312
P.28
PCI EXPRESS X16
Connector
P.15
P.19
IDE Primary
P.18
UltraDMA
33/66/100
Intel LGA775 Processor
FSB
H_PWRGD
H_CPURST#
Lakeport
MCH
P.6~9
DMI
PLRST#
VRM_GD
DDRII
266/333
MHz
PWR_GD
P.3~5
Block Diagram
4 DDR II
DIMM
Modules
PCIRST_ICH7#
PWR_GD
PCIRST#1
PCI Slot 1
PCI Slot 2
MS7
VID_GD
RSMRST#
PCIRST#2
HD_RST#
PWR_OK
SLP_S4#
SERIAL ATA1
SERIAL ATA2
SERIAL ATA3
A A
SERIAL ATA4
USB2.0
USB Port0~ 7
INTEL
82562GZ
Azalia Codec
ALC888
P.18
P.25
P.16
USB
RSMRST#
Azalia
LPC Bus
ICH7
P.10~12
JFP1
PWRBTN#
SLP_S3#
PHY
PCI
PCI-E 1X
ATX1
P.23 P.15
PCI-E 1X
LAN Giga
INTEL
82573GZ
P.30
LAN 10/100
INTEL
82562GZ
1394
VIA
VT6308P
PCIRST#2
P.17
P.26
PCIRST#1
RSMRST#
PWRBTIN FP_RST#
PLRST#
FWH
P.30
Keyboard
Mouse
P.14
P.14
LPC SIO
W83627DHG
P.14
Floopy Parallel
P.14 P.18
PSON#
PCIRST#2
1
PWR_OK
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
Date: Sheet
MICRO-START INT'L CO.,LTD.
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
MS-7324M1
MS-7324M1
MS-7324M1
of
235Tuesday, August 01, 2006
235Tuesday, August 01, 2006
235Tuesday, August 01, 2006
A
A
A
5
4
3
2
1
HCLK
LGA775
CLOCK MAP
D D
ICS954119 1/2
Clock
Generator
C C
MCHCLK
DOTCLK
96MHz
ICHCLK
SATACLK
USB48MHz
ICH14.318MHz
SIO48MHz
Lakeport
MCH
ICH7
W83627DHG
LPC IO
ICS954119 2/2
Clock
Generator
PCI_E1PCI_E1_100MHz
PCI-Express X 16
PCI_E1CK_PE_100M_1PORT
PCI-Express X 1
INTELCK_PE_100M_LAN
LAN_82562GZ
1394_PCLK
33MHz
B B
FWH_PCLK
33MHz
VT6306
1394
FWH
SIO_PCLK
33MHz
A A
5
PCICLK[0..3]
33MHz
PCI1
PCI2
Title
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Title
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Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
CLOCK MAP
CLOCK MAP
CLOCK MAP
MS-7324M1
MS-7324M1
MS-7324M1
1
of
335Tuesday, August 01, 2006
of
335Tuesday, August 01, 2006
of
335Tuesday, August 01, 2006
A
A
A
5
POWER MAP
4
3
2
1
D D
C C
B B
ATX POWER
+12V +5V +3.3V +5VSB
MSI
ACPI
Controller
38.81*1.8/5/0.8 = 17.46A
5VDIMM
MS - 7
4+9.4+15.3+2.6+1.31+6.2 = 38.81A
MSI
MS6 +
V_1P5_CORE
V_1P05_CORE
V_FSB_VTT
6.2A
125A 5.3A
VCC_DDR
17.87A
1.31A
1.875A
6.5A
5A
12.6A
PCI_E1
LGA775VRM 11
Lakeport
4A
MCH
13.8A + 1.5A
= 15.3A
9.4A
DDR2 X 4
1.2A
TBD (2.57A)
1.31A
ICH7
0.7A
PCI_E3
0.9A
14mA
PCI1
PCI2
VIA
1394 VT6308P
VLAN25
VLAN12
VLAN25
INTEL
3.775A
Tekoa
VLAN12
and
VCC3_SB VTT_DDR
W83627DHG
1.2A
82562EZ
5VDUAL
A A
5
4A
4
4.0A
USB
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
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Date: Sheet of
Date: Sheet of
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
POWER MAP
POWER MAP
POWER MAP
MS-7324M1
MS-7324M1
MS-7324M1
1
of
435Tuesday, August 01, 2006
435Tuesday, August 01, 2006
435Tuesday, August 01, 2006
A
A
A
8
7
6
5
4
3
2
1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name
GPIO[0] SIO_SMI# AB18 I/O Vcc3p3 N Y 5 1 NA(Pull high vcc3)
GPIO[1] PREQ#5 C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
GPIO[6] unmuxed AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
FWH
GPIO Pin# Power Tol Signal Name
FPGI[0] 6 Main 3.3 pull-down
FPGI[1] 5 Main 3.3 pull-down
FPGI[2] 4 Main 3.3 pull-down
FPGI[3] 3 Main 3.3 pull-down
FPGI[4] 30 Main 3.3 pull-down
GPIO[7] THERM(#) AC18 I/O Vcc3p3 N Y 3.3 Input (GPI7)THERM(#) function
GPIO[8] SIO_PME# E21 I/O VccSus3p3 N Y 3.3 Input SIO_PME#
GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
PCI Config.
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input SMB_ALERT#(only pull high vcc3_sb)
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A PGNT#5
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input NA(pull high vcc3)
C C
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input PULL HIGH VCC3
GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change LAN_DISABLE#
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 NC
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 Test point
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 Test point
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 Connect a jump connector
GPIO[29] OC5# C3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[30] OC6# A2 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[31] OC7# B3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[32] unmuxed AG18 I/O Vcc3p3 N N 3.3 1 CLEAR_CMOS#
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 BIOS_WP#
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
B B
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A PGNT#4
DDRII DIMM Config.
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
SIO W83627DHG
PIN NAME NOTESInput/OutputPIN# USAGE
GP31 91 OUT FAN_CTRL
A A
JUMPER SETTING
Note: FWH GPs should only be used for static options,
do not put dynamic nets on these
CLOCKREQ#/GNT#MCP1 INT Pin IDSELDEVICE
PCI1
PIRQ#A PCI_CLK0
PIRQ#B
PCI2
PIRQ#C
PIRQ#D PREQ#4
PIRQ#E PREQ#31394 1394_PCLK
DEVICE ADDRESS
DIMM 1
DIMM 2
A0H
A1H
A2H
DIMM 2
JBAT1
A3H
(1-2)NORMAL
PREQ#0
PGNT#0
PGNT#1
PREQ#2
PGNT#2
PGNT#4
PGNT#3
CLOCK
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1
MCLK_A2/MCLK_A#2
MCLK_A3/MCLK_A#3
MCLK_A4/MCLK_A#4
MCLK_A5/MCLK_A#5
MCLK_B0/MCLK_B#0
MCLK_B1/MCLK_B#1DIMM 3
MCLK_B2/MCLK_B#2
MCLK_B3/MCLK_B#3
MCLK_B4/MCLK_B#4
MCLK_B5/MCLK_B#5
(2-3)CLEAR
AD16
AD17PREQ#1
AD20
AD19
PCI_CLK1
PCI_CLK2AD18
PCI_CLK3
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
GPIO MAP
GPIO MAP
GPIO MAP
MS-7324M1
MS-7324M1
MS-7324M1
of
535Tuesday, August 01, 2006
of
535Tuesday, August 01, 2006
of
535Tuesday, August 01, 2006
1
A
A
A
8
7
6
5
4
3
2
1
AN4
AN3
AN6
AN5
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D13#
D12#D8D11#
D10#
D9#
B12
B10
A11
C11
H_D#12
H_D#13
H_D#9
H_D#11
H_D#10
R68 X_1KRR68 X_1KR
VID6
VID7
AM5
AM7
AJ3
AK3
RSVD
ITP_CLK1
ITP_CLK0
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A10
H_D#7
H_D#8
H_D#4
H_D#5
H_D#6
H_D#3
VCC_VRM_SENSE
VSS_VRM_SENSE
VID5
VID4
AL4
AK4
VID6#
VID5#
VID4#
VID_SELECT
GTLREF_SEL
CS_GTLREF
LINT0/INTR
H_D#1
H_D#2
CPU SIGNAL BLOCK
D D
H_DBI#0
H_INIT#[20]
H_BPRI#[10]
H_A20M#[20]
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_TESTHI13VTT_OUT_LEFT
R54 62RR54 62R
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_DBI#[0..3][10]
H_IERR#[7]
H_FERR#[7,20]
H_STPCLK#[20]
H_DBSY#[10]
H_DRDY#[10]
H_TRDY#[10]
C C
B B
A A
H_BNR#[10]
H_HITM#[10]
H_DEFER#[10]
THERMDA_CPU[29]
THERMDC_CPU[29]
TRMTRIP#[20]
H_PROCHOT#[7]
H_IGNNE#[20]
ICH_H_SMI#[20]
R90 62RR90 62R
VTT_OUT_RIGHT
H_FSBSEL0[7,12,19]
H_FSBSEL1[7,12,19]
H_FSBSEL2[7,12,19]
H_PWRGD[7,20]
H_CPURST#[7,10]
H_D#[0..63][10]
H_ADS#[10]
H_LOCK#[10]
H_HIT#[10]
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
H_A#[3..31][10]
U3A
U3A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
H_D#53
D53#
D52#
C14
H_D#52
D51#
A14
C15
H_D#51
H_D#50
D50#
D49#
D17
H_D#49
AJ6
AJ5
A35#
D48#
D20
G22
H_D#48
H_D#47
AH5
A34#
A33#
D47#
D46#
D22
H_D#46
H_A#31
AH4
AG5
A32#
D45#
E22
G21
H_D#44
H_D#45
H_A#30
AG4
A31#
A30#
D44#
D43#
F21
H_D#43
H_A#29
H_A#28
AG6
AF4
A29#
D42#
F20
E21
H_D#42
H_D#41
H_A#27
AF5
A28#
A27#
D41#
D40#
E19
H_D#40
H_A#26
H_A#25
AB4
AC5
A26#
A25#
D39#
D38#
F18
E18
H_D#38
H_D#39
H_A#23
H_A#24
AB5
AA5
A24#
D37#
F17
G17
H_D#36
H_D#37
H_A#22
AD6
A23#
A22#
D36#
D35#
G18
H_D#35
H_A#20
H_A#21
AA4
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
E16
E15
H_D#33
H_D#34
H_A#19
H_A#18
D32#
G16
G15
H_D#31
H_D#32
H_A#17
AB6
D31#
D30#
F15
H_D#30
H_A#14
H_A#13
H_A#12
H_A#11
H_A#16
H_A#15
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D29#
D28#
D27#
D26#
D25#
D24#
F14
F12
E13
D13
G14
G13
H_D#25
H_D#24
H_D#29
H_D#26
H_D#28
H_D#27
H_A#6
H_A#8
H_A#10
H_A#7
H_A#9
U6
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
F11
E10
D10
H_D#19
H_D#22
H_D#23
H_D#21
H_D#20
H_A#5
H_A#4
H_D#18
H_D#17
H_A#3
L5
D11
H_D#15
H_D#16
AC2
DBR#
D14#
C12
H_D#14
VID2
VID0
VID1
VID3
AL6
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
GTLREF0
GTLREF1
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
RSVD
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B4
H_D#0
FP_RST# [21,30]
VCC_VRM_SENSE [9]
VSS_VRM_SENSE [9]
VID[0..7] [9]
R6 1KRR6 1KR
AN7
H1
H2
TP_GTLREF_SEL
H29
MCH_GTLREF_CPU
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
H_TESTHI9
G4
H_TESTHI8
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
RSVD_AK6
AK6
RSVD_G6
G6
G28
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
U3
U2
F3
T2
J2
R1
G2
T1
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
TP6TP6
TP5TP5
VTT_OUT_RIGHT
CPU_GTLREF0
CPU_GTLREF1
PECI [29]
RN8 8P4R-62RRN8 8P4R-62R
1 2
3 4
5 6
7 8
R75 62RR75 62R
R129 62RR129 62R
R66 62RR66 62R
R125 62RR125 62R
R11 X_62RR11 X_62R
R77 X_62RR77 X_62R
CK_H_CPU# [19]
CK_H_CPU [19]
H_RS#[0..2] [10]
RN58 8P4R-62RRN58 8P4R-62R
1 2
3 4
5 6
7 8
R72 62RR72 62R
R131 62R0402R131 62R0402
TP7TP7
TP11TP11
TP10TP10
TP8TP8
H_ADSTB#1 [10]
H_ADSTB#0 [10]
H_DSTBP#3 [10]
H_DSTBP#2 [10]
H_DSTBP#1 [10]
H_DSTBP#0 [10]
H_DSTBN#3 [10]
H_DSTBN#2 [10]
H_DSTBN#1 [10]
H_DSTBN#0 [10]
H_NMI [20]
H_INTR [20]
VRD_VIDSEL [9]
CPU_GTLREF0 [7]
CPU_GTLREF1 [7]
TP9TP9
MCH_GTLREF_CPU [10]
H_REQ#[0..4] [10]
VTT_OUT_LEFT
V_FSB_VTT
VTT_OUT_RIGHT [7,8,29]
VTT_OUT_LEFT [7]
C42
C42
X_C0.1U25Y
X_C0.1U25Y
BSEL
1
02
FSB FREQUENCY
TABLE
267 MHZ (1067)000
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
RN4
RN4
8P4R-680R
8P4R-680R
VID4
1
VID2
VID5
VID0
VID7
VID3
VID6
H_BR#0 [7,10]
VTT_OUT_RIGHT
C25 C0.1U25YC25 C0.1U25Y
C11 C0.1U25YC11 C0.1U25Y R47 49.9R1%R47 49.9R1%
VID1
PLACE BPM TERMINATION NEAR CPU
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN29
RN29
8P4R-680R
8P4R-680R
RN3 8P4R-51R-LFRN3 8P4R-51R-LF
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
RN6 8P4R-51R-LFRN6 8P4R-51R-LF
R34 X_49.9R1%R34 X_49.9R1%
R64 49.9R1%R64 49.9R1%
VTT_OUT_RIGHT
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TMS
H_TDI
H_BPM#2
H_BPM#4
H_TDO
H_TRST#
H_TCK
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
Intel LGA775 - Signals
Intel LGA775 - Signals
Intel LGA775 - Signals
MS-7324M1
MS-7324M1
MS-7324M1
of
635Tuesday, August 01, 2006
of
635Tuesday, August 01, 2006
of
635Tuesday, August 01, 2006
1
A
A
A
8
VCCP
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
U3B
AF19
AF18
AF15
AF14
AF12
AF11
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AE9
AD8
AC8
AB8
AA8
VCCP
U3B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y23
Y24
Y25
Y26
Y27
Y28
Y29
W30
VCCP
D D
C C
AG22
VCC
VCC
W29
AG25
VCC
VCC
W28
AG26
VCC
VCC
W27
AG27
VCC
VCC
W26
AG28
W25
VCC
VCC
AG29
VCC
VCC
W24
7
AG30
VCC
W23
AG8
VCC
AG9
VCC
VCCU8VCCV8VCC
AH11
VCC
VCC
U30
AH12
VCC
VCC
U29
AH14
VCC
VCC
U28
AH15
VCC
VCC
U27
AH18
VCC
VCC
U26
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
U23
AH25
VCC
VCCT8VCC
AH26
VCC
VCC
T30
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
VCC
VCC
T27
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
AJ11
T23
VCC
AJ12
VCC
AJ14
VCC
AJ15
6
VCC
VCCN8VCCP8VCCR8VCC
AJ18
N30
VCC
VCC
AJ19
N29
VCC
VCC
AJ21
N28
VCC
VCC
AJ22
N27
VCC
VCC
AJ25
N26
VCC
VCC
AJ26
VCC
VCC
N25
5
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
K25
K26
K27
K28
K29
N23
N24
M27
M28
M29
M30
K30
M23
M24
M25
M26
AM18
VCC
VCC
J21
AM19
VCC
VCC
J20
AM21
VCC
VCC
J19
AM22
VCC
VCC
J18
AM25
VCC
VCC
J15
AM26
VCC
VCC
J14
4
AM29
VCC
VCC
J13
AM30
VCC
VCC
J12
AM8
J11
VCC
VCC
AM9
VCC
VCC
J10
AN11
VCC
VCC
AN9
AN12
VCC
VCC
AN8
AN14
AN15
AN18
AN19
VCC
VCC
VCC
VCC
VTT_OUT_RIGHT
VTT_OUT_LEFT
VCC
VCC
VCC
VCC
AN25
AN26
AN29
AN30
AN21
AN22
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTTPWRGD
VTT_SEL
RSVD
HS11HS22HS33HS4
A23
B23
D23
C23
A25
VTT
A26
VTT
A27
VTT
A28
VTT
A29
VTT
A30
VTT
B25
VTT
B26
VTT
B27
VTT
B28
VTT
B29
VTT
B30
VTT
C25
VTT
C26
VTT
C27
VTT
C28
VTT
C29
VTT
C30
VTT
D25
VTT
D26
VTT
D27
VTT
D28
VTT
D29
VTT
D30
VTT
AM6
AA1
J1
F27
F29
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
4
3
H_VCCA
H_VSSA
H_VCCPLL
H_VCCABB
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
R1220RR122
0R
CP9CP9
1 2
V_FSB_VTT
V_FSB_VTT
C78 C10U10Y0805C78 C10U10Y0805
C128 C10U10Y0805C128 C10U10Y0805
C87 C10U10Y0805C87 C10U10Y0805
V_1P5_CORE
CAPS FOR FSB GENERIC
2
C138
C138
C10U10Y0805
C10U10Y0805
1
VTT_OUT_LEFT
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
B B
VTT_OUT_LEFT
R89 124R1%R89 124R1%
R78 124R1%R78 124R1%
R88
R88
210R1%
210R1%
R86
R86
210R1%
210R1%
R91 10R-1R91 10R-1
C44
C44
C0.1U25Y
C0.1U25Y
R74 10R-1R74 10R-1
C43
C43
C0.1U25Y
C0.1U25Y
C45
C45
C100P50N
C100P50N
C39
C39
C100P50N
C100P50N
CPU_GTLREF0 [6]
V_FSB_VTT
L4 10U125m_0805-1L4 10U125m_0805-1
CPU_GTLREF1 [6]
PLACE AT CPU END OF ROUTE
H_IERR#
7
H_PROCHOT#
H_CPURST#
H_PWRGD
H_BR#0
H_FERR# [6,20]
H_PROCHOT# [6]
H_CPURST# [6,10]
H_PWRGD [6,20]
H_BR#0 [6,10]
H_IERR# [6]
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
RN24
RN24
1
3
5
7
8P4R-470R
8P4R-470R
6
5
VTT_OUT_RIGHT[6,8,29]
VTT_OUT_LEFT[6]
A A
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
V_FSB_VTT
R387 62RR387 62R
R23 100RR23 100R
R130 62RR130 62R
R87 X_100RR87 X_100R
R69 62RR69 62R
R61 62RR61 62R
H_FERR#
PLACE AT ICH END OF ROUTE
8
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
H_VCCABB
2
4
6
8
L5 10U125m_0805-1L5 10U125m_0805-1
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
4
VID_GD#[9,32]
H_FSBSEL1 [6,12,19]
H_FSBSEL0 [6,12,19]
H_FSBSEL2 [6,12,19]
VTT_OUT_RIGHT
VCC5_SB
R63
R63
1KR
1KR
R62 10KRR62 10KR
C75
C75
X_C1U10Y
X_C1U10Y
R53 680RR53 680R
C82
C82
C10U10Y0805
C10U10Y0805
VTT_PWG
Q4
Q4
N-PMBS3904_SOT23-RH
N-PMBS3904_SOT23-RH
3
C85
C85
C10U10Y0805
C10U10Y0805
H_VCCA
H_VSSA
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
C38
C38
X_C1U10Y
X_C1U10Y
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
Intel LGA775 - Power
Intel LGA775 - Power
Intel LGA775 - Power
MS-7324M1
MS-7324M1
MS-7324M1
A
A
A
of
735Tuesday, August 01, 2006
of
735Tuesday, August 01, 2006
of
735Tuesday, August 01, 2006
1
8
7
6
5
4
3
2
1
V_FSB_VTT
D D
C C
B B
VTT_OUT_RIGHT[6,7,29]
E23
VSS
AF16
RSVD
VSS
AF17
TP15TP15
VSS
AF20
R71 62RR71 62R
TP12TP12
F23
F6
RSVDE5RSVDE6RSVDE7RSVD
VSS
VSS
VSS
VSS
AF23
AF24
AF25
AF26
R1386
30R1%0402-RH
R1386
30R1%0402-RH
H_COMP8
B13
RSVD
IMPSEL#
VSS
VSS
VSS
AF27
AF28
AF29
VSS
AF3
R67
R67
62R
62R
P5
RSVDJ3RSVDN4RSVD
VSS
VSS
VSS
AF6
AF7
AF30
VSS
MSID[1]V1MSID[0]
VSS
AG10
W1
AG13
VSS
R65
R65
62R
62R
AC4
RSVD
VSS
AG16
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
R58
R58
R28
R28
60.4R1%
60.4R1%
60.4R1%
60.4R1%
TP14TP14
H_COMP6
H_COMP7
AE3
AE4
VSS
AE29
COMP6Y3COMP7
VSS
VSS
AE5
AE7
AE30
RSVD
VSS
AF10
D14
RSVDD1RSVD
VSS
AF13
U3C
U3C
A12
VSS
A15
VSS
A18
VSS
A2
VSS
A21
VSS
A24
VSS
A6
VSS
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2005 Perf FMB 0 0
R59
R59
2005 Value FMB 0 1
X_62R
X_62R
V30
V29
V28
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
AG17
AG20
AG23
AG24
AG7
VSS
AH1
VSS
VSS
AH10
VSS
AH13
AH16
VSS
VSS
AH17
VSSV3VSS
VSS
AH20
VSS
AH23
VSS
VSS
AH24
V27
AH3
VSS
VSS
V26
AH6
V25
VSS
VSS
AH7
MSID1 MSID0
V24
V23
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
VSS
AJ24
VSS
AJ27
VSS
AJ28
VSS
R30
AJ29
VSS
R29
AJ30
VSS
VSS
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
AN1
VSS
VSS
AN10
AN13
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
AN16
VSS
AN17
H28
AN2
VSS
VSS
VSS
VSS
AN20
AN23
VSS
VSS
AN24
VSS
VSS
VSS
VSS
AN27
VSS
VSS
AN28
VSS
VSS
VSS
VSSB1VSS
B11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B14
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
VSS
AL17
VSS
AL20
VSS
AL23
VSS
AL24
VSS
AL27
VSS
L30
AL28
VSS
VSSL3VSS
VSS
AL3
L29
L28
L27
VSS
VSS
VSS
VSS
VSS
AL7
AM1
AM10
L26
VSS
VSS
AM13
L25
VSS
VSS
AM16
L24
VSS
VSS
AM17
L23
VSS
VSS
AM20
VSSK7VSS
VSS
AM23
K5
VSS
AM24
K2
VSS
AM27
VSS
AM28
VSS
AM4
A A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
Intel LGA775 - GND
Intel LGA775 - GND
Intel LGA775 - GND
MS-7324M1
MS-7324M1
MS-7324M1
of
835Tuesday, August 01, 2006
of
835Tuesday, August 01, 2006
of
835Tuesday, August 01, 2006
1
A
A
A
5
4
3
2
1
U_GATE1
R508
R508
10KR
10KR
L_GATE1
U_GATE2
R485
R485
10KR
10KR
L_GATE2
U_GATE3
R256
R256
10KR
10KR
L_GATE3
VREG_12V
C543
C543
C0.01U16X0402
C0.01U16X0402
VIN
DS
Q40
Q40
G
N-P0903BD_TO252
N-P0903BD_TO252
DS
G
N-P75N02LDG_TO252
Q26
Q26
N-P75N02LDG_TO252
N-P75N02LDG_TO252
N-P75N02LDG_TO252
VIN
DS
Q37
Q37
G
N-P0903BD_TO252
N-P0903BD_TO252
DS
G
Q25
Q25
N-P75N02LDG_TO252
N-P75N02LDG_TO252
N-P75N02LDG_TO252
N-P75N02LDG_TO252
VIN
DS
Q10
Q10
G
N-P0903BD_TO252
N-P0903BD_TO252
DS
G
Q13
Q13
N-P75N02LDG_TO252
N-P75N02LDG_TO252
L27
L27
CH-1.2U18A-LF
CH-1.2U18A-LF
12
CD1000U16EL20-RH
CD1000U16EL20-RH
C493
C493
C501
C501
C10U16Y1206
C10U16Y1206
C1U16Y
C1U16Y
DS
G
Q39
Q39
C466
C466
C474
C474
C10U16Y1206
C10U16Y1206
C1U16Y
C1U16Y
DS
G
Q27
Q27
C232
C232
C233
C233
C10U16Y1206
C10U16Y1206
C1U16Y
C1U16Y
DS
G
Q15
Q15
N-P75N02LDG_TO252
N-P75N02LDG_TO252
+
+
12
+
+
+
+
12
+
+
12
EC17
EC17
EC16
EC16
X_CD1000U16EL20-RH
X_CD1000U16EL20-RH
CD1000U16EL20-RH
CD1000U16EL20-RH
+
+
12
EC63
EC63
CD1000U16EL20-RH
CD1000U16EL20-RH
12
EC64
EC64
EC59
EC59
CD1000U16EL20-RH
CD1000U16EL20-RH
Vcore 0.8V~1.55V/85A
L26
R457
R457
2.2R0805
2.2R0805
C407
C407
C1000P50X0402
C1000P50X0402
ISEN_1
ISEN1
R368
R368
2.2R0805
2.2R0805
C384
C384
C1000P50X0402
C1000P50X0402
ISEN_2
ISEN2
R257
R257
2.2R0805
2.2R0805
C264
C264
C1000P50X0402
C1000P50X0402
ISEN_3
ISEN3
L26
CH-0.25U40A-RH-1
CH-0.25U40A-RH-1
CP42CP42
L28
L28
CH-0.25U40A-RH-1
CH-0.25U40A-RH-1
CP40CP40
L25
L25
CH-0.25U40A-RH-1
CH-0.25U40A-RH-1
CP37CP37
VCCP
21
CP41CP41
21
CP39CP39
21
CP38CP38
C529
C529
C0.1U16Y0402
C0.1U16Y0402
VCCP
EL Capacitors
+
+
12
EC65
EC65
CD560U4OS-2
CD560U4OS-2
CD560U4OS-2
CD560U4OS-2
VCCP
OS-CON Capactiors
+
+
12
EC26
EC26
CD560U4OS-2
CD560U4OS-2
CD560U4OS-2
CD560U4OS-2
VCCP
+
+
12
EC30
EC30
X_CD560U4OS-2
X_CD560U4OS-2
CD560U4OS-2
CD560U4OS-2
VCCP
EC31
EC31
C22U10Y1206
C22U10Y1206
X_C22U10Y1206
X_C22U10Y1206
VCCP
EC78
EC78
C22U10Y1206
C22U10Y1206
X_C22U10Y1206
X_C22U10Y1206
VCCP
+
+
12
+
+
12
EC85
EC85
X_C100U2SP-LF
X_C100U2SP-LF
X_C100U2SP-LF
X_C100U2SP-LF
VIN
C528
C528
C0.1U16Y0402
C0.1U16Y0402
+
+
12
+
+
12
EC68
EC68
X_CD560U4OS-2
X_CD560U4OS-2
+
+
12
+
+
12
EC29
EC29
CD560U4OS-2
CD560U4OS-2
+
+
12
+
+
12
EC24
EC24
CD560U4OS-2
CD560U4OS-2
EC34
EC34
EC33
EC33
C22U10Y1206
C22U10Y1206
C22U10Y1206
C22U10Y1206
EC71
EC71
EC61
EC61
C22U10Y1206
C22U10Y1206
C22U10Y1206
C22U10Y1206
Solder Side
EC72
EC72
EC86
EC86
X_C22U10Y1206
X_C22U10Y1206
X_C22U10Y1206
X_C22U10Y1206
EC67
EC67
EC56
EC56
VCCP
EC21
EC21
C22U10Y1206
C22U10Y1206
EC70
EC70
X_C22U10Y1206
X_C22U10Y1206
EC66
EC66
X_C22U10Y1206
X_C22U10Y1206
EC79
EC79
X_C22U10Y1206
X_C22U10Y1206
VCCP
+
+
12
EC84
EC84
X_C100U2SP-LF
X_C100U2SP-LF
C22U10Y1206
C22U10Y1206
EC88
EC88
EC87
EC87
C22U10Y1206
C22U10Y1206
C22U10Y1206
C22U10Y1206
EC38
EC38
EC62
EC62
C22U10Y1206
C22U10Y1206
EC69
EC69
EC46
EC46
C22U10Y1206
C22U10Y1206
EC81
EC81
EC80
EC80
X_C22U10Y1206
X_C22U10Y1206
EC90
EC90
EC89
EC89
VCC5
R552
R552
VREG_12V
2.2R0805
2.2R0805
V_6312
R531
VCC5
D D
VRM_GD[19,32]
Place
close to
inductor
C C
VCC_VRM_SENSE[6]
VSS_VRM_SENSE[6]
V_6312
SMBCLK[14,17,19,21,25,32]
SMBDATA[14,17,19,21,25,32]
B B
A A
R549 3KR1%0402R549 3KR1%0402
R536 0R0402R536 0R0402
RT2
RT2
X_4.7KRT-RH
X_4.7KRT-RH
R544
R544
1.6KR1%0402
1.6KR1%0402
R533 X_100KR0402R533 X_100KR0402
R525 X_4.99KR1%0402R525 X_4.99KR1%0402
R526 X_1KR0402R526 X_1KR0402
R515 X_0R0402R515 X_0R0402
R519 X_0R0402R519 X_0R0402
R548 100R0402R548 100R0402
R555 0R0402R555 0R0402
R547 0R0402R547 0R0402
R554 100R0402R554 100R0402
C479
C479
X_C100P50N0402
X_C100P50N0402
20KR1%0402
20KR1%0402
VID_GD#[7,32]
R70
R70
X_4.7KR0402
X_4.7KR0402
VID[0..7][6]
R541 20KR1%0402R541 20KR1%0402
C508 X_C680P50X0402C508 X_C680P50X0402
R528
R528
VID_GD#
C445 C1000P50X0402C445 C1000P50X0402
C481 C1000P50X0402C481 C1000P50X0402
VRD_VIDSEL[6]
C507 C1500P50X0402C507 C1500P50X0402
C506 C12P50N0402C506 C12P50N0402
R516
R516
0R0402
0R0402
C517
C517
X_C0.1U16Y0402
X_C0.1U16Y0402
R522
R522
0R0402
0R0402
R500
R500
10KR0402
10KR0402
C449
C449
C1000P50X0402
C1000P50X0402
R542 0R0402R542 0R0402
R557 X_750R1%0402R557 X_750R1%0402
R553 X_10KR0402R553 X_10KR0402
Reserve for
ISL6312A
C496
C496
VID7[6]
VID6[6]
VID5[6]
VID4[6]
VID3[6]
VID2[6]
VID1[6]
VID0[6]
C509
C509
X_C0.01U16X0402
X_C0.01U16X0402
C516
C516
X_C0.1U16Y0402
X_C0.1U16Y0402
R503
R503
C0.01U16X0402
C0.01U16X0402
120KR
120KR
VREG_12V
B
VID_PG
R527
R527
240KR0402
240KR0402
R497
R497
10KR0402
10KR0402
VID_PG
CE
Q41
Q41
N-PMBS3904_SOT23-RH
N-PMBS3904_SOT23-RH
C447
C447
C1000P50X0402
C1000P50X0402
U20
U20
37
PGOOD
36
EN
46
VID7
47
VID6
48
VID5
1
VID4
2
VID3
3
VID2
4
VID1
5
VID0
6
VRSEL
13
COMP
14
FB
15
IDROOP
16
VDIFF
18
VSEN
17
RGND
12
OFS
7
DRSEL
8
OVPSEL
11
REF
45
FS
9
SS
BOTTOM PAD
CONNECT TO GND
Through 8 VIAs
C531
C531
C4.7U10Y0805
C4.7U10Y0805
10
PVCC1_2
VCC
BOOT1
UGATE1
PHASE1
LGATE1
ISEN1+
ISEN1-
BOOT2
UGATE2
PHASE2
LGATE2
ISEN2+
ISEN2-
PVCC3
BOOT3
UGATE3
PHASE3
LGATE3
ISEN3+
ISEN3-
ISEN4+
ISEN4-
PWM4
EN_PH4
GND
49
ISL6312CRZ_QFN48-RH
ISL6312CRZ_QFN48-RH
7X7 QFN
R498
R498
2.2KR0402
2.2KR0402
R531
2.2R0805
2.2R0805
C494
C494
C1U16Y
C1U16Y
29
BOOT1
31
32
33
30
35
34
27
26
25
28
19
20
42
40
39
38
41
44
43
21
22
24
23
R523 2.2R0805R523 2.2R0805
ISEN1+
R509 0R0402R509 0R0402
ISEN1-
C491 C0.1U10X0402C491 C0.1U10X0402
R517 X_4.7KR1%0402R517 X_4.7KR1%0402
R518
R518
BOOT2
R534 2.2R0805R534 2.2R0805
ISEN2+
R539 0R0402R539 0R0402
ISEN2-
C532 C0.1U10X0402C532 C0.1U10X0402
R546 X_4.7KR1%0402R546 X_4.7KR1%0402
R556 4.7KR1%0402R556 4.7KR1%0402
R490 2.2R0805R490 2.2R0805
C441 C1U16YC441 C1U16Y
BOOT3
R496 2.2R0805R496 2.2R0805
ISEN3+ ISEN3
R510 0R0402R510 0R0402
ISEN3-
C448 C0.1U10X0402C448 C0.1U10X0402
R499 X_4.7KR1%0402R499 X_4.7KR1%0402
R493 4.7KR1%0402R493 4.7KR1%0402
V_6312
Disable PH4 the
EN_PHN(pin23) should
be pull-hi 5V
4.7KR1%0402
4.7KR1%0402
C487 C0.1U16XC487 C0.1U16X
C511 C0.1U16XC511 C0.1U16X
C443 C0.1U16XC443 C0.1U16X
X_C0.01U16X0402
X_C0.01U16X0402
VREG_12VVCCP
VREG_12V
C547
C547
3
4
JPW1
JPW1
PWR-2X2M_white-4.2pitch-RH
PWR-2X2M_white-4.2pitch-RH
UGATE1
PHASE1
LGATE1
ISEN1
C463
C463
C0.1U16Y0402
C0.1U16Y0402
ISEN_1
UGATE2
PHASE2
LGATE2
ISEN2
C530
C530
C0.1U16Y0402
C0.1U16Y0402
ISEN_2
UGATE3
PHASE3
LGATE3
C426
C426
C0.1U16Y0402
C0.1U16Y0402
ISEN_3
Disable PH4 the
EN_PHN(pin23) should
be pull-hi 5V
5
1
1
3
3
1
4
2
4
2
2
R511
R511
UGATE1
1R0805
1R0805
PHASE1
R489
R489
LGATE1
0R0805
0R0805
R487
R487
UGATE2
1R0805
1R0805
PHASE2
R436
R436
LGATE2
0R0805
0R0805
R212
R212
UGATE3
1R0805
1R0805
PHASE3
R254
R254
LGATE3
0R0805
0R0805
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
MICRO-START INT'L CO.,LTD.
VRM11 Intersil 6312 3Phase
VRM11 Intersil 6312 3Phase
VRM11 Intersil 6312 3Phase
MS-7324M1
MS-7324M1
MS-7324M1
1
of
935Tuesday, August 01, 2006
935Tuesday, August 01, 2006
935Tuesday, August 01, 2006
A
A
A
8
H_A#[3..31][6]
D D
H_ADSTB#0[6]
H_ADSTB#1[6]
C C
B B
PLTRST#[20,24,29]
ICH_SYNC#[21]
R142 16.9R1%R142 16.9R1%
H_BR#0[6,7]
H_BPRI#[6]
H_BNR#[6]
H_LOCK#[6]
H_ADS#[6]
H_REQ#[0..4][6]
H_HIT#[6]
H_HITM#[6]
H_DEFER#[6]
H_TRDY#[6]
H_DBSY#[6]
H_DRDY#[6]
H_RS#[0..2][6]
CK_H_MCH[19]
CK_H_MCH#[19]
PWR_GD[21,32]
H_CPURST#[6,7]
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
7
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
AF6
VCC
RSVRD
AA34
VCC
RSVRD
AA38
VCC
RSVRD
L15
M15
VCC
VCC
RSVRD
RSVRD
U27
AF7
VCC
RSVRD
A43
R27
U6A
U6A
H_A#3 H_D#0
J39
HA3#
H_A#4
K38
HA4#
VCC
VCC
VCC
VCC
VCC
RSVRD
AA35
VCC
RSVRD
AA42
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
M34
M38
AA37
M36
AA41
W42
G37
W41
W40
M31
M29
AJ12
M18
J42
K35
J37
N35
R33
N32
N34
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
V35
F38
D42
U39
U40
E41
D41
K36
E42
U41
P40
U42
V41
Y40
T40
Y43
T43
AJ9
C30
A28
C27
B27
D27
D28
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
AF8
VCC
VCC
RSVRD
RSVRD
M11
AF9
VCC
RSVRD
AG25
AF10
VCC
RSVRD
AG26
AF11
AF12
VCC
RSVRD
AJ24
AG27
6
AF13
VCC
VCC
RSVRD
RSVRD
AJ27
AF14
VCC
RSVRD
AK40
AF30
AG2
VCC
RSVRD
AL39
AW17
AG3
VCC
VCC
RSVRD
RSVRD
AW18
V_1P5_CORE
AG4
AG5
AG6
VCC
VCC
RSVRD
RSVRD
AY14
BC16
AD30
AG7
VCC
VCC
RSVRD
RSVRD
AC34
AG8
VCC
RSVRD
Y30
AG9
AG10
VCC
RSVRD
Y33
AF31
AG11
VCC
VCC
RSVRD
RSVRD
AD31
AG12
VCC
RSVRD
U30
AG13
VCC
RSVRD
V31
AG14
VCC
RSVRD
AA30
AH1
VCC
RSVRD
AC30
AH2
AH4
VCC
RSVRD
AJ23
AK21
AJ5
VCC
VCC
RSVRD
RSVRD
AJ26
AJ13
VCC
RSVRD
AL29
AJ14
VCC
RSVRD
AL20
5
AK2
VCC
RSVRD
AJ21
AK3
AK4
VCC
RSVRD
AL26
AK27
AK14
VCC
VCC
RSVRD
RSVRD
AJ29
AK15
AK20
VCC
RSVRD
V30
AG29
R15
VCC
VCC
RSVRD
R17
R18
VCC
NC
BC43NCBC42
VCC
R20
R21
VCC
NC
BC2NCBC1
VCC
R23
VCC
NC
BB43
R24
U15
VCC
VCC
NC
BB2NCBB1NCBA2
4
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NCC2NC
NCB3NCB2NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E35
B43NCB42NCB41
A42
Y17
Y18
Y19
Y21
Y23
Y25
C42
AW2
AV27NCAV26
AW26
Y27
AA15
AA17
AA18
W24
VCC
VCC
AA19
W26
VCC
VCC
AA20
W27
Y15
VCC
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
3
M17
P41
HD0#
M39
HD1#
VCC
VCC
P42
HD2#
M42
HD3#
N41
HD4#
M40
HD5#
L40
HD6#
M41
HD7#
K42
HD8#
G39
HD9#
J41
HD10#
G42
HD11#
G40
HD12#
G41
HD13#
F40
HD14#
F43
HD15#
F37
HD16#
E37
HD17#
J35
HD18#
D39
HD19#
C41
HD20#
B39
HD21#
B40
HD22#
H34
HD23#
C37
HD24#
J32
HD25#
B35
HD26#
J34
HD27#
B34
HD28#
F32
HD29#
L32
HD30#
J31
HD31#
H31
HD32#
M33
HD33#
K31
HD34#
M27
HD35#
K29
HD36#
F31
HD37#
H29
HD38#
F29
HD39#
L27
HD40#
M24
HD41#
J26
HD42#
K26
HD43#
G26
HD44#
H24
HD45#
K24
HD46#
F24
HD47#
E31
HD48#
A33
HD49#
E40
HD50#
D37
HD51#
C39
HD52#
D38
HD53#
D33
HD54#
C35
HD55#
D34
HD56#
C34
HD57#
B31
HD58#
C31
HD59#
C32
HD60#
D32
HD61#
B30
HD62#
D30
HD63#
K40
KDINV_0#
A38
HDINV_1#
E29
HDINV_2#
B32
HDINV_3#
K41
L43
F35
G34
J27
M26
E34
B37
[INTEL-QG82945P-A1-LF]
[INTEL-QG82945P-A1-LF]
V_1P5_CORE
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 [6]
H_DSTBN#0 [6]
H_DSTBP#1 [6]
H_DSTBN#1 [6]
H_DSTBP#2 [6]
H_DSTBN#2 [6]
H_DSTBP#3 [6]
H_DSTBN#3 [6]
2
H_D#[0..63] [6]
1
H_DBI#[0..3] [6]
V_FSB_VTT
A A
R146 60.4R1%0402R146 60.4R1%0402
HXSCOMP
C122
C122
X_C2.2P50N
X_C2.2P50N
V_FSB_VTT
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
PLACE DIVIDER RESISTOR NEAR VTT
R143
R143
301R1%
301R1%
R145
R145
84.5R1%
84.5R1%
R144 62R0402R144 62R0402
C121
C121
C0.01U16X0402
C0.01U16X0402
HXSWING
V_FSB_VTT
MCH_GTLREF
R141
R141
124R1%0402
124R1%0402
R139
R139
210R1%0402
210R1%0402
CAPS SHOULD BE PLACED NEAR MCH PIN
8
7
6
5
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
C115
C115
C0.1U16Y0402
C0.1U16Y0402
C117
C117
X_C220P50N
X_C220P50N
4
R135 0RR135 0R
MCH_GTLREF_CPU [6]
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
Intel Lakeport - CPU
Intel Lakeport - CPU
Intel Lakeport - CPU
MS-7324M1
MS-7324M1
MS-7324M1
of
10 35Tuesday, August 01, 2006
of
10 35Tuesday, August 01, 2006
of
10 35Tuesday, August 01, 2006
1
A
A
A
8
7
6
5
4
3
2
1
DATA_A37
DATA_A38
AT32
AR34
SADQ36
SADQ37
SADQ38
SBDQ34
SBDQ35
SBDQ36
AP27
AM31
DATA_B35
DATA_B36
DATA_A40
DATA_A39
AU37
AR41
SADQ39
SBDQ37
AP31
AR27
DATA_B37
DATA_B38
DATA_A41
DATA_A42
AR42
AN43
SADQ40
SADQ41
SBDQ38
SBDQ39
AP35
AU31
DATA_B40
DATA_B39
SCKE_A[0..3][14,16]
DATA_A43
DATA_A44
AM40
AU41
SADQ42
SADQ43
SBDQ40
SBDQ41
AP37
AN32
DATA_B42
DATA_B41
5
DATA_A45
DATA_A46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
DATA_B43
DATA_B44
DATA_A48
DATA_A47
AN40
AL41
SADQ46
SADQ47
SBDQ44
SBDQ45
AU38
AM38
DATA_B46
DATA_B45
DATA_A49
DATA_A50
AL42
AF39
SADQ48
SADQ49
SBDQ46
SBDQ47
AL34
AM34
DATA_B47
DATA_B48
DATA_A51
SADQ50
SBDQ48
DATA_B49
DATA_A[0..63][14]
DATA_A16
DATA_A21
DATA_A6
DATA_A4
AN1
SADQ3
SADQ4
SBDQ1
SBDQ2
AP8
DATA_B2
DATA_A5
AP4
SADQ5
SBDQ3
AP9
DATA_B3
AU5
SADQ6
SBDQ4
AJ11
DATA_B4
DATA_A7
AU2
SADQ7
SBDQ5
AL9
DATA_B5
DATA_A8
AW3
SADQ8
SBDQ6
AM10
DATA_B6
DATA_A9
AY3
AP6
DATA_B7
DATA_A10
BA7
SADQ9
SADQ10
SBDQ7
SBDQ8
AU7
DATA_B8
DATA_A12
DATA_A11
BB7
AV1
SADQ11
SBDQ9
AV6
AV12
DATA_B10
DATA_B9
DATA_A14
DATA_A13
AW4
BC6
SADQ12
SADQ13
SBDQ10
SBDQ11
AR5
AM11
DATA_B11
DATA_B12
DATA_A15
AY7
AW12
SADQ14
SADQ15
SBDQ12
SBDQ13
AR7
AR12
DATA_B14
DATA_B13
DATA_A17
AY10
SADQ16
SBDQ14
AR10
DATA_B15
DATA_A0
DATA_A1
DATA_A3
D D
SCS_A#[0..3][14,16]
RAS_A#[14,16]
CAS_A#[14,16]
WE_A#[14,16]
MAA_A[0..13][14,16]
ODT_A[0..3][14,16]
C C
SBS_A[0..2][14,16]
DQS_A0[14]
DQS_A#0[14]
DQS_A1[14]
DQS_A#1[14]
DQS_A2[14]
DQS_A#2[14]
DQS_A3[14]
DQS_A#3[14]
DQS_A4[14]
DQS_A#4[14]
DQS_A5[14]
DQS_A#5[14]
DQS_A6[14]
DQS_A#6[14]
DQS_A7[14]
DQS_A#7[14]
P_DDR0_A[14]
N_DDR0_A[14]
P_DDR1_A[14]
N_DDR1_A[14]
P_DDR2_A[14]
N_DDR2_A[14]
P_DDR3_A[14]
N_DDR3_A[14]
B B
VCC_DDR
A A
P_DDR4_A[14]
N_DDR4_A[14]
P_DDR5_A[14]
N_DDR5_A[14]
R194 80.6R1%R194 80.6R1%
R193 80.6R1%R193 80.6R1%
C183
C183
C0.1U25Y
C0.1U25Y
8
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SMPCOMP_N
SMPCOMP_P MCH_VREF_AMCH_VREF_B
SMPCOMP_P
SMPCOMP_N
U6B
U6B
BB37
SACS0#
BA39
SACS1#
BA35
SACS2#
AY38
SACS3#
BA34
SARAS#
BA37
SACAS#
BB35
SAWE#
BA32
SAMA0
AW32
SAMA1
BB30
SAMA2
BA30
SAMA3
AY30
SAMA4
BA27
SAMA5
BC28
SAMA6
AY27
SAMA7
AY28
SAMA8
BB27
SAMA9
AY33
SAMA10
AW27
SAMA11
BB26
SAMA12
BC38
SAMA13
AW37
SAODT0
AY39
SAODT1
AY37
SAODT2
BB40
SAODT3
BC33
SABA0
AY34
SABA1
BA26
SABA2
AU4
SADQS0
AR2
SADQS0#
BA3
SADQS1
BB4
SADQS1#
AY11
SADQS2
BA10
SADQS2#
AU18
SADQS3
AR18
SADQS3#
AU35
SADQS4
AV35
SADQS4#
AP42
SADQS5
AP40
SADQS5#
AG42
SADQS6
AG41
SADQS6#
AC42
SADQS7
AC41
SADQS7#
BB32
SACLK0
AY32
SACLK0#
AY5
SACLK1
BB5
SACLK1#
AK42
SACLK2
AK41
SACLK2#
BA31
SACLK3
BB31
SACLK3#
AY6
SACLK4
BA5
SACLK4#
AH40
SACLK5
AH43
SACLK5#
AL5
MCH_SRCOMP0
AJ6
MCH_SRCOMP1
AJ8
SMOCDCOMP0
AM3
SMOCDCOMP1
[INTEL-QG82945P-A1-LF]
[INTEL-QG82945P-A1-LF]
DATA_B[0..63][15]
DATA_A2
AP3
AP2
AU3
AV4
SADQ0
SADQ1
SADQ2
SBDQ0
AL6
AL8
DATA_B0
DATA_B1
7
DATA_A18
DATA_A19
BA12
BB12
SADQ17
SADQ18
SBDQ15
SBDQ16
AM15
AM13
DATA_B17
DATA_B16
DATA_A20
BA9
BB9
SADQ19
SADQ20
SBDQ17
SBDQ18
AV15
AM17
DATA_B18
DATA_B19
6
DATA_A22
DATA_A23
BC11
AY12
SADQ21
SADQ22
SBDQ19
SBDQ20
AN12
AR13
DATA_B21
DATA_B20
DATA_A24
DATA_A25
AM20
AM18
SADQ23
SADQ24
SBDQ21
SBDQ22
AT15
AP15
DATA_B23
DATA_B22
DATA_A26
DATA_A27
AV20
AM21
SADQ25
SADQ26
SBDQ23
SBDQ24
AM24
AM23
DATA_B24
DATA_B25
DATA_A29
DATA_A28
AP17
AR17
SADQ27
SADQ28
SBDQ25
SBDQ26
AV24
AM26
DATA_B27
DATA_B26
DATA_A31
DATA_A30
AP20
AT20
SADQ29
SADQ30
SBDQ27
SBDQ28
AP21
AR21
DATA_B28
DATA_B29
DATA_A32
DATA_A33
AP32
AV34
SADQ31
SADQ32
SBDQ29
SBDQ30
AT24
AP24
DATA_B31
DATA_B30
DATA_A34
DATA_A35
AV38
AU39
SADQ33
SADQ34
SBDQ31
SBDQ32
AU27
AN29
DATA_B32
DATA_B33
DATA_A36
AV32
SADQ35
SBDQ33
AR31
DATA_B34
DATA_A52
AE40
AM41
SADQ51
SADQ52
SBDQ49
SBDQ50
AJ34
AF32
DATA_B50
DATA_A53
DATA_A54
AM42
AF41
SADQ53
SBDQ51
AL31
AF34
DATA_B52
DATA_B51
SCKE_B[0..3][15,16]
DATA_A56
DATA_A55
AF42
AD40
SADQ54
SADQ55
SBDQ52
SBDQ53
AJ32
AG35
DATA_B54
DATA_B53
DQM_A[0..7][14]
DATA_A57
DATA_A58
AD43
AA39
SADQ56
SADQ57
SBDQ54
SBDQ55
AD32
AC32
DATA_B55
DATA_B56
DQM_B[0..7][15]
DATA_A60
DATA_A59
AA40
AE42
SADQ58
SADQ59
SBDQ56
SBDQ57
Y32
AD34
DATA_B57
DATA_B58
DATA_A61
DATA_A62
AE41
AB41
SADQ60
SADQ61
SBDQ58
SBDQ59
AF35
AA32
DATA_B60
DATA_B59
DATA_A63
AB42
SADQ62
SADQ63
SBDQ60
SBDQ61
AF37
AC33
DATA_B61
DATA_B62
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SBDQ62
SBDQ63
AC35
DATA_B63
4
SCKE_A3
SCKE_A2
BC24
BA25
SACKE1
SACKE2
SBCKE0
BA14
AY16
SCKE_B0
SCKE_B1
SACKE3
SBCKE1
SBCKE2
BA13
BB13
SCKE_B3
SCKE_B2
DQM_A1
DQM_A0
AY2
AR3
SADM0
SBCKE3
AD39
DQM_B7
DQM_A2
BB10
SADM2
SADM1
SBDM6
SBDM7
AJ39
DQM_B6
DQM_A3
AP18
SADM3
SBDM5
AR38
DQM_B5
DQM_A4
DQM_A5
AT34
SADM4
SBDM4
AR29
DQM_B3
DQM_B4
DQM_A6
AP39
SADM5
SBDM3
AP23
DQM_B2
DQM_A7
AC40
AG40
SADM6
SBDM2
AW7
AP13
DQM_B1
SBCS0#
SBCS1#
SBCS2#
SADM7
SBCS3#
SBRAS#
SBCAS#
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1
SMVREF0
SBDM0
SBDM1
AL11
DQM_B0
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBBA0
SBBA1
SBBA2
SCS_B#0
BA40
SCS_B#1
AW41
SCS_B#2
BA41
SCS_B#3
AW40
RAS_B#
BA23
CAS_B#
AY24
WE_B#
BB23
MAA_B0
BB22
MAA_B1
BB21
MAA_B2
BA21
MAA_B3
AY21
MAA_B4
BC20
MAA_B5
AY19
MAA_B6
AY20
MAA_B7
BA18
MAA_B8
BA19
MAA_B9
BB18
MAA_B10
BA22
MAA_B11
BB17
MAA_B12
BA17
MAA_B13MAA_A13
AW42
ODT_B0
AY42
ODT_B1
AV40
ODT_B2
AV43
ODT_B3
AU40
SBS_B0
AW23
SBS_B1
AY23
SBS_B2
AY17
DQS_B0
AM8
DQS_B#0
AM6
DQS_B1
AV7
DQS_B#1
AR9
DQS_B2
AV13
DQS_B#2
AT13
DQS_B3
AU23
DQS_B#3
AR23
DQS_B4
AT29
DQS_B#4
AV29
DQS_B5
AP36
DQS_B#5
AM35
DQS_B6
AG34
DQS_B#6
AG32
DQS_B7
AD36
DQS_B#7
AD38
P_DDR0_B
AM29
N_DDR0_B
AM27
P_DDR1_B
AV9
N_DDR1_B
AW9
P_DDR2_B
AL38
N_DDR2_B
AL36
P_DDR3_B
AP26
N_DDR3_B
AR26
P_DDR4_B
AU10
N_DDR4_B
AT10
P_DDR5_B
AJ38
N_DDR5_B
AJ36
AM2
MCH_VREF_A
AM4
PLACE 0.1UF CAP CLOSE TO MCH
3
SCS_B#[0..3] [15,16]
RAS_B# [15,16]
CAS_B# [15,16]
WE_B# [15,16]
MAA_B[0..13] [15,16]
ODT_B[0..3] [15,16]
SBS_B[0..2] [15,16]
DQS_B0 [15]
DQS_B#0 [15]
DQS_B1 [15]
DQS_B#1 [15]
DQS_B2 [15]
DQS_B#2 [15]
DQS_B3 [15]
DQS_B#3 [15]
DQS_B4 [15]
DQS_B#4 [15]
DQS_B5 [15]
DQS_B#5 [15]
DQS_B6 [15]
DQS_B#6 [15]
DQS_B7 [15]
DQS_B#7 [15]
P_DDR0_B [15]
N_DDR0_B [15]
P_DDR1_B [15]
N_DDR1_B [15]
P_DDR2_B [15]
N_DDR2_B [15]
P_DDR3_B [15]
N_DDR3_B [15]
P_DDR4_B [15]
N_DDR4_B [15]
P_DDR5_B [15]
N_DDR5_B [15]
C179
C179
C0.1U25Y
C0.1U25Y
VCC_DDR
C178
PLACE 0.1UF CAP CLOSE TO MCH
R199 1KR1%R199 1KR1%
R196
R196
1KR1%
1KR1%
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
C178
C0.1U25Y
C0.1U25Y
CP3
CP3
X_COPPER
X_COPPER
R198 X_0RR198 X_0R
MCH_VREF_A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Intel Lakeport - Memory
Intel Lakeport - Memory
Intel Lakeport - Memory
MS-7324M1
MS-7324M1
MS-7324M1
MCH_VREF_B
11 35Tuesday, August 01, 2006
11 35Tuesday, August 01, 2006
11 35Tuesday, August 01, 2006
1
of
of
of
A
A
A
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