MSI MS-7310 Schematics rev.1.0
5
4
3
2
1
MS-7310 VER:1.0 ATX(10/100M Lan)
PageTitle
Cover Sheet 1
*AMD PGA 940 K8-Processor (DDR2)
D D
*Nvidia CK8S04
*Winbond 83627EHF and DHFLPC I/O
*VSC8601 / RTL8201CL
*USB 2.0 support (10 Port,integrated into Chip)
*ALC655 6 channel S/W Audio
*DDR DIMM * 2
*PCI-EXPRESS X16 SLOT * 1
*PCI-EXPRESS X1 SLOT * 1
*PCI SLOT * 3
C C
Block Diagram 2
GPIO SPEC
3
AMD K9 ->940 PGA Socket 4,5,6
System Memory
DDR DIMM 1 & 2
DDR2 Termination Resistors
Intersil 6566 3Phase
SYSTEM CHIP NVIDIA CK8S-04
PCI -Express PORT
ATA66/100/133 IDE connector VccDDR powe
PCI 1
PCI 2 & 3
7
8
9
10,11,12,13,14,15
16
17
18
19
20USB Port
LPC I/O & ROM & Floppy&Fan
KeyBoard/Mouse/LPT/COM Connectors
LAN VSC8601 / RTL8201CL
ALCALC655 6 channel S/W Audio
ACPI Power CONTROLLER (MS-6)
System Regulator&Front Panel
Decoupling Cap.
B B
Power Sequence
History
OPTION PARTS
21
22
23
24
25
26
27
28
29
30
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
MS-7310
MS-7310
MS-7310
1
Last Revision Date:
Last Revision Date:
Last Revision Date:
Tuesday, July 25, 2006
Tuesday, July 25, 2006
Tuesday, July 25, 2006
Sheet
Sheet
Sheet
Rev
Rev
Rev
1.0
1.0
1.0
130
130
130
of
of
of
5
4
3
2
1
Block Diagram
Intersil 6566
3Phase
D D
PCI EXPRESS
X16
Connector
C C
Gigabit LAN
10/100 LAN
PCI EXPRESS X16
RGMII/MII
K9 940
Crushk8-04
PCI EXPRESS X 1
D
D
I
I
M
M
M
M
2
1
PCI EXPRESS X1
X 4
Serial ATA
I
D
E
Dual ATA
B B
33/66/100/133
1
PCI-33
LPC BUS
3 PCI Slots
USB 2.0
SUPER I/OBIOS
AC97
Codec
A A
AC-LINK
Dual USB 1.1 OHCI
/2.0 EHCI 10
Ports
Keyboard
Mouse
Floopy
Parallel
Rear x4 Front x6
5
4
3
2
Serial
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Block Diagram
Block Diagram
Block Diagram
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
Rev
Rev
Rev
1.0
1.0
MS-7310
MS-7310
MS-7310
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 24, 2006
Monday, July 24, 2006
Monday, July 24, 2006
Sheet
Sheet
Sheet
1
1.0
230
230
230
of
of
of
5
4
3
2
1
GPIO FUNCTION
CK8S-04
D D
NAME Function Description
GPIO_1
GPIO_2/CPU_SLP*
GPIO_3/CPU_CLKRUN*
GPIO_4/SUS_STAT*
NC
NC
S/IO GPIO Function Define
Function definePIN NAME
BIOS WRITE PROTECTPin70/GP44
PCI Routing
DEVICES INT#
INT#B
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
INT#D
INT#A
INT#B
INT#C
IDSEL
AD23
AD24
AD25
REQ#/GNT#
PREQ#2
PGNT#2
PREQ#3
PGNT#3
PREQ#4
PGNT#4
CLOCK
PCICLK4
PCICLK2
PCICLK3
GPIO_5/SYS_ERR*
C C
B B
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
GPIO Spec.
GPIO Spec.
GPIO Spec.
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
MS-7310
MS-7310
MS-7310
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 24, 2006
Monday, July 24, 2006
Monday, July 24, 2006
Sheet
Sheet
Sheet
330
330
330
1
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
4
3
2
1
HT_CLKIN_H110
HT_CLKIN_L110
HT_CLKIN_H010
HT_CLKIN_L010
R78 51R/4R78 51R/4
R79 51R/4R79 51R/4
HT_CTLIN_H010
HT_CTLIN_L010
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
C133
C133
C4.7U10Y0805
C4.7U10Y0805
C107
C107
C4.7U10Y0805
C4.7U10Y0805
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
C122
C122
C0.22U16X
C0.22U16X
L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
C121
C121
C0.22U16X
C0.22U16X
CPU1A
CPU1A
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
C115
C115
C180P50N
C180P50N
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
C127
C127
C180P50N
C180P50N
HT_CLKOUT_H1 10
HT_CLKOUT_L1 10
HT_CLKOUT_H0 10
HT_CLKOUT_L0 10
HT_CTLOUT_H0 10
HT_CTLOUT_L0 10
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
TP19TP19
TP18TP18
VCC_DDR
CPU_CLK#10
R49
R49
_15R1%0805-1
_15R1%0805-1
R48
R48
_15R1%0805-1
_15R1%0805-1
CPU_CLK10
VDDA_25
L6 80L3_40_0805L6 80L3_40_0805
VCC_DDR
R74
R74
39.2R1%
39.2R1%
R73
R73
39.2R1%
39.2R1%
CPU_M_VREF
C58
C58
C0.1U16X
C0.1U16X
2 1
C3900P50X
C3900P50X
C51
C51
C50C3900P50X C50C3900P50X
VCC_DDR
CPU_STRAP_HI_E11
CPU_STRAP_LO_F11
C55
C55
C1000P50X
C1000P50X
VDDA25
R52
R52
_169R1%-1
_169R1%-1
CPUCLKIN
CPUCLKIN#
C10
C10
X_C1000P50X
X_C1000P50X
R65 300R1%R65 300R1%
R72 X_300R1%R72 X_300R1%
CPU_M_VREF
TP14TP14
R33 300RR33 300R
R42 300RR42 300R
TP11TP11
THERMDC_CPU21
THERMDA_CPU21
CPU_SID21
TP17TP17
C43
C43
C4.7U16Y1206
C4.7U16Y1206
CPU_SIC21
TP35TP35
TP36TP36
TP33TP33
TP34TP34
TP31TP31
TP2TP2
TP1TP1
TP12TP12
TP10TP10
TP16TP16
TP9TP9
TP21TP21
CPU_PWRGD10
VDDA25
C0.22U16X
C0.22U16X
C57
C57
C53
CPU_PWRGD_L
HT_STOP_L
LDT_RST_L
CPU_PRESENT_L
COREFB+9
COREFB-9
CPU_VTT_SENSE
CPU_TEST25_H
CPU_TEST25_L
C53
C3300P50X
C3300P50X
COREFB+
COREFB-
AK6
AL10
AJ10
AH10
AH11
AJ11
AH9
AG9
AG8
AH7
C10
D10
A8
B8
C9
D8
C7
AL3
AL6
AL9
A5
G2
G1
E12
F12
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
E5
AJ5
AJ6
CPU1D
CPU1D
MISC
MISC
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
THERMTRIP_L
SIC
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
3VDUAL
147
HT_STOP#10
HT_STOP#
PG_VCORE9,25
LDT_RST10
LDT_RST LDT_RST_L
CPU_PWRGD CPU_PWRGD_L
U1AU1A
1 2
3VDUAL
147
U1DU1D
9 8
3VDUAL
3 4
3VDUAL
13 12
3VDUAL
147
U1CU1C
5 6
147
147
U1FU1F
TP13TP13
D2
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
TDO
D1
C1
E3
E2
E1
AK7
AL7
AK10
VID4
VID3
VID2
VID1
VID0
CPU_THRIP_L
PROCHOT_L
B6
AK11
AL11
CPU_PSI_L
F1
PSI_L
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
R71 300RR71 300R
AK5
G7
D4
HT Bus Level shift
HT_STOP_L
U1BU1B
VCC_DDR
R22
R22
300R
300R
TP37TP37
VCC_DDR
TP32TP32
CPU_VDDIOFB_H
CPU_VDDIOFB_L
TP15TP15
TP24TP24
TP22TP22
TP23TP23
TP20TP20
VCC_DDR
CPU_THRIP_L CPU_THRIP#
VCC2_5
1
3
5
7
VCC_DDR
1
3
5
7
C104
C104
C1000P50X
C1000P50X
TP8TP8
TP7TP7
R67
R67
300R
300R
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
VCC_DDR
R31
R31
330R
330R
B
CE
Q3
Q3
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
RN2
RN2
2
4
6
8
8P4R-330R
8P4R-330R
RN3
RN3
2
4
6
8
8P4R-330R
8P4R-330R
C105
C105
C1000P50X
C1000P50X
R43
R43
80.6R1%
80.6R1%
LDT_RST
CPU_PWRGD
CPU_THRIP#
HT_STOP#
HT_STOP_L
CPU_THRIP_L
CPU_PWRGD_L
LDT_RST_L
VID[0..4] 9
VCC_DDR
R66
R66
300R
300R
VDD_12_A
R69 44.2R1%R69 44.2R1%
R70 44.2R1%R70 44.2R1%
R77 1KRR77 1KR
R50 510RR50 510R
R51 510RR51 510R
CPU_THRIP# 10
VCC_DDR
From C51D
CPU Side
HT_CADIN_H[15..0]10
HT_CADIN_L[15..0]10
HT_CADOUT_H[15..0]10
HT_CADOUT_L[15..0]10
D D
VDD_12_A
C106
C106
C4.7U10Y0805
C4.7U10Y0805
VDD_12_A
C C
B B
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
3VDUAL
147
U1EU1E
11 10
5
4
3
2
Micro Star Restricted Secret
Title
Title
Title
ATHLON64 HT I/F CTRL & DEBUG
ATHLON64 HT I/F CTRL & DEBUG
ATHLON64 HT I/F CTRL & DEBUG
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
MS-7310
MS-7310
MS-7310
1
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 31, 2006
Monday, July 31, 2006
Monday, July 31, 2006
Sheet
Sheet
Sheet
430
430
430
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
4
3
2
1
MEM_MA_DQS_L[7..0]7
MEM_MA_DQS_H[7..0]7
MEM_MA_DM[7..0]7
MEM_MB_DQS_L[7..0]7
MEM_MB_DQS_H[7..0]7
MEM_MB_DM[7..0]7
D D
CPU1B
CPU1B
MEMORY INTERFACE A
MEM_MA0_CLK_H27,8
MEM_MA0_CLK_L27,8
MEM_MA0_CLK_H17,8
MEM_MA0_CLK_L17,8
MEM_MA0_CLK_H07,8
MEM_MA0_CLK_L07,8
MEM_MA0_CS_L17,8
MEM_MA0_CS_L07,8
MEM_MA0_ODT07,8
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
AG21
AG20
AC25
AA24
AC28
AE20
AE19
AD27
AA25
G19
H19
U27
U26
G20
G21
V27
W27
AC27
C C
MEM_MA_CAS_L7,8
MEM_MA_WE_L7,8
MEM_MA_RAS_L7,8
MEM_MA_BANK27,8
MEM_MA_BANK17,8
MEM_MA_BANK07,8
MEM_MA_CKE07,8
MEM_MA_ADD[15..0]7,8
B B
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AB25
AB27
AA26
AA27
AC26
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AJ25
AH29
N25
Y27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
U25
W24
D29
C29
C25
D25
E19
G15
B29
E24
E18
H15
L27
T25
T27
F19
F15
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
MEM_MA_DATA18
C26
MEM_MA_DATA17
G23
MEM_MA_DATA16
F23
MEM_MA_DATA15
E22
MEM_MA_DATA14
E21
MEM_MA_DATA13
F17
MEM_MA_DATA12
G17
MEM_MA_DATA11
G22
MEM_MA_DATA10
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DATA[63..0] 7
MEM_MB0_CLK_H27,8
MEM_MB0_CLK_L27,8
MEM_MB0_CLK_H17,8
MEM_MB0_CLK_L17,8
MEM_MB0_CLK_H07,8
MEM_MB0_CLK_L07,8
MEM_MB0_CS_L17,8
MEM_MB0_CS_L07,8
MEM_MB0_ODT07,8
MEM_MB_CAS_L7,8
MEM_MB_WE_L7,8
MEM_MB_RAS_L7,8
MEM_MB_BANK27,8
MEM_MB_BANK17,8
MEM_MB_BANK07,8
MEM_MB_CKE07,8
MEM_MB_ADD[15..0]7,8
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AJ19
AK19
AE30
AC31
AD29
AL19
AL18
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
AA31
AA28
M31
M29
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AH17
AJ23
AK29
A18
A19
U31
U30
C19
D19
N31
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
CPU1C
CPU1C
MEMORY INTERFACE B
MEMORY INTERFACE B
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DATA[63..0] 7
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
ATHLON64 DDR MEMORY I/F
ATHLON64 DDR MEMORY I/F
ATHLON64 DDR MEMORY I/F
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
MS-7310
MS-7310
MS-7310
1
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 31, 2006
Monday, July 31, 2006
Monday, July 31, 2006
Sheet
Sheet
Sheet
530
530
530
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
4
3
2
1
VCCP
CPU1F
CPU1F
VDD1
VDD1
A4
VDD1
A6
VDD2
AA8
VDD3
D D
C C
B B
AA10
AA12
AA14
AA16
AA18
AB11
AC10
AE10
AB7
AB9
AC4
AC5
AC8
AD2
AD3
AD7
AD9
AF7
AF9
AG4
AG5
AG7
AH2
AH3
E10
F11
G10
G12
H11
H23
K11
K13
K15
K17
K19
K21
K23
Y17
Y19
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41
VDD42
F5
VDD43
F7
VDD44
F9
VDD45
VDD46
G6
VDD47
G8
VDD48
VDD49
VDD50
H7
VDD51
VDD52
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
VDD150
VDD151
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
VCCP
M11
M13
M15
M17
M19
N10
N12
N14
N16
N18
P11
P13
P15
P17
P19
R10
R12
R14
R16
R18
R20
U10
U12
U14
U16
U18
U20
V11
V13
V15
V17
V19
V21
W10
W12
W14
W16
W18
W20
Y11
Y13
Y15
Y21
CPU1G
CPU1G
VDD2
L14
L16
L18
T11
T13
T15
T17
T19
T21
VDD2
VDD1
VDD2
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
N8
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
P7
VDD19
P9
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
U8
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
V9
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
VDD72
VDD73
VDD74
VDD75
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
VCCP
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
M21
M23
N20
N22
R22
U22
W22
L20
L22
P21
P23
T23
V23
Y23
CPU1H
CPU1H
VDD3
VDD3
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
5
GND
6
GND
7
GND
8
GND
1
GND
2
GND
3
GND
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
VTT_DDR
VCC_DDR
VCCP
C535
C535
C0.22U16X
C0.22U16X
VCCP
C526
C526
X_C22U6.3X1206
X_C22U6.3X1206
VDD_12_A
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
C544
C544
C0.22U16X
C0.22U16X
C525
C525
X_C22U6.3X1206
X_C22U6.3X1206
VDDIO
VDDIO
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
C541
C541
C0.22U16X
C0.22U16X
C530
C530
X_C22U6.3X1206
X_C22U6.3X1206
CPU1I
CPU1I
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
C514
C514
C0.01U50X
C0.01U50X
H6
H5
H2
VTT_DDR
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
C521
C521
C180P50N/4/B
C180P50N/4/B
C519
C519
X_C22U6.3X1206
X_C22U6.3X1206
VLDT_RUN_B
C22U6.3X1206
C22U6.3X1206
C522
C522
C61
C61
C4.7U16Y1206
C4.7U16Y1206
C22U6.3X1206
C22U6.3X1206
C527
C527
C22U6.3X1206
C22U6.3X1206
C520
C520
C524
C524
C22U6.3X1206
C22U6.3X1206
X_C22U6.3X1206
X_C22U6.3X1206
C531
C531
X_C22U6.3X1206
X_C22U6.3X1206
C540
C540
C515
C515
X_C22U6.3X1206
X_C22U6.3X1206
C517
C517
C22U6.3X1206
C22U6.3X1206
C534
C534
X_C22U6.3X1206
X_C22U6.3X1206
C516
C516
X_C22U6.3X1206
X_C22U6.3X1206
X_C22U6.3X1206
X_C22U6.3X1206
C539
C539
VTT_DDR
C48
C48
C59
C59
C28
C28
C46
C26
C27
C27
C54
C29
C29
C0.22U16X
C0.22U16X
A A
VTT_DDR
C129
C129
C0.22U16X
C0.22U16X
C54
C0.22U16X
C0.22U16X
C131
C131
C0.22U16X
C0.22U16X
5
C4.7U10Y0805
C4.7U10Y0805
C139
C139
C4.7U10Y0805
C4.7U10Y0805
C26
C4.7U10Y0805
C4.7U10Y0805
C141
C141
C4.7U10Y0805
C4.7U10Y0805
C46
C10P16N
C10P16N
C134
C134
C10P16N
C10P16N
C10P16N
C10P16N
C109
C109
C10P16N
C10P16N
C1000P50X
C1000P50X
C102
C102
C1000P50X
C1000P50X
C1000P50X
C1000P50X
C125
C125
C1000P50X
C1000P50X
VCC_DDR VCC_DDR
C66
C66
C528
C528
C518
C518
C0.22U16X
C0.22U16X
C0.22U16X
C0.22U16X
4
C0.22U16X
C0.22U16X
C138
C138
C4.7U10Y0805
C4.7U10Y0805
C181
C181
C4.7U10Y0805
C4.7U10Y0805
3
C533
C533
X_C22U6.3X1206
X_C22U6.3X1206
C536
C536
C22U6.3X1206
C22U6.3X1206
C112
C112
C4.7U10Y0805
C4.7U10Y0805
C170
C170
C4.7U10Y0805
C4.7U10Y0805
2
C523
C523
C0.22U16X
C0.22U16X
C130
C130
C0.22U16X
C0.22U16X
C62
C62
C543
C543
C0.22U16X
C0.22U16X
C0.01U50X
C0.01U50X
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
ATHLON64 PWR & GND
ATHLON64 PWR & GND
ATHLON64 PWR & GND
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
C169
C169
C180P50N
C180P50N
MS-7310
MS-7310
MS-7310
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 31, 2006
Monday, July 31, 2006
Monday, July 31, 2006
Sheet
Sheet
Sheet
1
Rev
Rev
Rev
0A
0A
0A
630
630
630
of
of
of
5
MEM_MA_DQS_H[7..0]5
MEM_MA_DQS_L[7..0]5
69
VDD6
64
VDD753VDD859VDD9
170
VDD1067VDD11
VDDQ1
172
178
184
187
189
197
VDD1
VDD2
VDD3
VDD4
164
D D
C C
MEM_MA_ADD[15..0]5,8
B B
MEM_MA_DM[7..0]5
SMB_MEM_CLK14
SMB_MEM_DATA14
MEM_MA_BANK25,8
MEM_MA_BANK15,8
MEM_MA_BANK05,8
MEM_MA0_CLK_H05,8
MEM_MA0_CLK_L05,8
MEM_MA0_CLK_H15,8
MEM_MA0_CLK_L15,8
MEM_MA0_CLK_H25,8
MEM_MA0_CLK_L25,8
MEM_MA_CKE05,8
MEM_MA_RAS_L5,8
MEM_MA_CAS_L5,8
MEM_MA0_CS_L05,8
MEM_MA0_CS_L15,8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
R100 33RR100 33R
R94 33RR94 33R
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA_CKE0
MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA0_CS_L0
MEM_MA0_CS_L1
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
SMB_MEMCLK
SMB_MEMDATA
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
VDD5
4
VCC3VCC_DDR
175
181
191
194
72
78
238
DIMM1DIMM1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VDDQ1075VDDQ11
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
TEST
ODT0
ODT1
ERR_OUT_L
PAR_IN
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
NC1
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
MEM_MA_DATA10
21
13
12
129
128
123
122
10
9
4
3
73
1
102
195
77
55
68
19
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_WE_L
VDDR_VREF
MEM_MA0_ODT0
MEM_MA_DATA[63..0] 5
MEM_MA_WE_L 5,8
MEM_MA0_ODT0 5,8
VDDR_VREF
C6
C0.1U25YC6C0.1U25Y
3
MEM_MB_DQS_H[7..0]5
MEM_MB_DQS_L[7..0]5
164
MEM_MB_DM[7..0]5
VCC3
MEM_MB_BANK25,8
MEM_MB_BANK15,8
MEM_MB_BANK05,8
MEM_MB_ADD[15..0]5,8
MEM_MB0_CLK_H05,8
MEM_MB0_CLK_L05,8
MEM_MB0_CLK_H15,8
MEM_MB0_CLK_L15,8
MEM_MB0_CLK_H25,8
MEM_MB0_CLK_L25,8
MEM_MB_CKE05,8
MEM_MB_RAS_L5,8
MEM_MB_CAS_L5,8
MEM_MB0_CS_L05,8
MEM_MB0_CS_L15,8
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
SMB_MEMCLK
SMB_MEMDATA
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB_CKE0
MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB0_CS_L0
MEM_MB0_CS_L1
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
7
6
VCC_DDR
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
2
1
VCC3
69
170
175
181
191
194
72
78
VDDQ651VDDQ756VDDQ862VDDQ9
VDDQ1075VDDQ11
238
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
WE_L
VREF
TEST
ODT0
ODT1
ERR_OUT_L
PAR_IN
NC1
DIMM2DIMM2
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3
73
1
102
195
77
55
68
19
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_WE_L
VDDR_VREF
MEM_MB0_ODT0
MEM_MB_DATA[63..0] 5
MEM_MB_WE_L 5,8
VDDR_VREF
C14
C14
C0.1U25Y
C0.1U25Y
MEM_MB0_ODT0 5,8
172
178
184
187
189
197
64
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VCC_DDR
DIMM 1 DIMM 2
A A
5
ADDR=1010000B
4
R14
R14
56.2R1%
56.2R1%
R15
R15
56.2R1%
56.2R1%
C13
C13
C0.1U16X
C0.1U16X
VDDR_VREF
VDDR_VREF
C5
C0.1U16XC5C0.1U16X
3
C7
C7
C1000P50X
C1000P50X
2
ADDR=1010001B
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
MS-7310
MS-7310
MS-7310
1
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 31, 2006
Monday, July 31, 2006
Monday, July 31, 2006
Sheet
Sheet
Sheet
730
730
730
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
4
3
2
1
MEM_MA_ADD[15..0]5,7
C151
C151
C0.1U16X
C0.1U16X
VCC_DDR
C148
C148
C0.1U16X
C0.1U16X
C137
C137
C0.1U16X
C0.1U16X
C150
C150
C0.1U16X
C0.1U16X
MEM_MA_ADD15
C144
C144
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
C140
C140
C0.1U16X
C0.1U16X
VTT_DDR
MEM_MA_BANK2
RN10 8P4R-47R0402RN10 8P4R-47R0402 C124
1
MEM_MA_BANK25,7
MEM_MB_BANK25,7
D D
MEM_MA_BANK05,7
MEM_MA_RAS_L5,7
MEM_MB0_CS_L05,7
MEM_MA0_CS_L05,7
MEM_MB_BANK05,7
MEM_MB_RAS_L5,7
MEM_MA_BANK15,7
MEM_MB0_CS_L15,7
C C
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MA_ADD12
RN11 8P4R-47R0402RN11 8P4R-47R0402 C88 C22P50N0402C88 C22P50N0402
MEM_MA_ADD9
MEM_MB_ADD11
MEM_MB_ADD7
MEM_MB_ADD6
RN13 8P4R-47R0402RN13 8P4R-47R0402
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MB_ADD5
MEM_MA_ADD1
RN15 8P4R-47R0402RN15 8P4R-47R0402
MEM_MA_ADD2
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MA_BANK0
RN20 8P4R-47R0402RN20 8P4R-47R0402
MEM_MA_RAS_L
MEM_MB0_CS_L0
MEM_MA0_CS_L0
MEM_MB_BANK0
RN18 8P4R-47R0402RN18 8P4R-47R0402
MEM_MB_RAS_L
MEM_MA_BANK1
MEM_MA_ADD10
MEM_MB_ADD13
MEM_MB0_CS_L1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
R82 47R0402R82 47R0402
R83 47R0402R83 47R0402
MEM_MA0_CLK_H25,7
MEM_MA0_CLK_L25,7
MEM_MA0_CLK_H15,7
MEM_MA0_CLK_L15,7
MEM_MA0_CLK_H05,7
MEM_MA0_CLK_L05,7
MEM_MB0_CLK_H25,7
MEM_MB0_CLK_L25,7
MEM_MB0_CLK_H15,7
MEM_MB0_CLK_L15,7
MEM_MB0_CLK_H05,7
MEM_MB0_CLK_L05,7
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
C124
C1.5P50N0402
C1.5P50N0402
C56
C56
C1.5P50N0402
C1.5P50N0402
C75
C75
C1.5P50N0402
C1.5P50N0402
C116
C116
C1.5P50N0402
C1.5P50N0402
C52
C52
C1.5P50N0402
C1.5P50N0402
C72
C72
C1.5P50N0402
C1.5P50N0402
C123
C123
C0.1U16X
C0.1U16X
VTT_DDR
C0.1U16X
C0.1U16X
C529 C22P50N0402C529 C22P50N0402
C538 C22P50N0402C538 C22P50N0402
C561 C22P50N0402C561 C22P50N0402
C542 C22P50N0402C542 C22P50N0402
C545 C22P50N0402C545 C22P50N0402
C557 C22P50N0402C557 C22P50N0402
C537 C22P50N0402C537 C22P50N0402
C546 C22P50N0402C546 C22P50N0402
C547 C22P50N0402C547 C22P50N0402
C549 C22P50N0402C549 C22P50N0402
C548 C22P50N0402C548 C22P50N0402
C551 C22P50N0402C551 C22P50N0402
C550 C22P50N0402C550 C22P50N0402
C552 C22P50N0402C552 C22P50N0402
C553 C22P50N0402C553 C22P50N0402
C555 C22P50N0402C555 C22P50N0402
C559 C22P50N0402C559 C22P50N0402
C560 C22P50N0402C560 C22P50N0402
C558 C22P50N0402C558 C22P50N0402
C532 C22P50N0402C532 C22P50N0402
C554 C22P50N0402C554 C22P50N0402
C556 C22P50N0402C556 C22P50N0402
Decoupling Between Processor and DIMMs
C25
C25
C82
C0.1U16X
C0.1U16X
C82
C0.1U16X
C0.1U16X
VCC_DDR
Layout: Spread out on VTT pour
C86
C86
C79
C0.1U16X
C0.1U16X
C79
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
C132
C132
C90
C90
C0.1U16X
C0.1U16X
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
C113
C113
C0.1U16X
C0.1U16X
C71 C22P50N0402C71 C22P50N0402
C67 C22P50N0402C67 C22P50N0402
C126 C22P50N0402C126 C22P50N0402
C73 C22P50N0402C73 C22P50N0402
C76 C22P50N0402C76 C22P50N0402
C111 C22P50N0402C111 C22P50N0402
C78 C22P50N0402C78 C22P50N0402
C81 C22P50N0402C81 C22P50N0402
C84 C22P50N0402C84 C22P50N0402
C85 C22P50N0402C85 C22P50N0402
C95 C22P50N0402C95 C22P50N0402
C91 C22P50N0402C91 C22P50N0402
C96 C22P50N0402C96 C22P50N0402
C97 C22P50N0402C97 C22P50N0402
C103 C22P50N0402C103 C22P50N0402
C118 C22P50N0402C118 C22P50N0402
C119 C22P50N0402C119 C22P50N0402
C114 C22P50N0402C114 C22P50N0402
C74 C22P50N0402C74 C22P50N0402
C101 C22P50N0402C101 C22P50N0402
C108 C22P50N0402C108 C22P50N0402
C147
C147
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
C24
C24
VCC_DDR
MEM_MB_ADD[15..0]5,7
RN9 8P4R-47R0402RN9 8P4R-47R0402
MEM_MA_CKE05,7
B B
MEM_MB_BANK15,7
MEM_MA_WE_L5,7
MEM_MA_CAS_L5,7
MEM_MB_WE_L5,7
MEM_MA0_ODT05,7
MEM_MB_CKE05,7
MEM_MB_CAS_L5,7
MEM_MA0_CS_L15,7
MEM_MB0_ODT05,7
A A
5
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MB_ADD8
MEM_MA_ADD11
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD4
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MA_ADD3
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MA_ADD0
MEM_MB_ADD10
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MB_WE_L
MEM_MA0_ODT0
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_CAS_L
MEM_MA_ADD13
MEM_MA0_CS_L1
MEM_MB0_ODT0
1
3
5
7
RN12 8P4R-47R0402RN12 8P4R-47R0402
1
3
5
7
RN14 8P4R-47R0402RN14 8P4R-47R0402
1
3
5
7
RN16 8P4R-47R0402RN16 8P4R-47R0402
1
3
5
7
RN21 8P4R-47R0402RN21 8P4R-47R0402
1
3
5
7
RN8 8P4R-47R0402RN8 8P4R-47R0402
1
3
5
7
RN22 8P4R-47R0402RN22 8P4R-47R0402
1
3
5
7
VTT_DDR
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
4
3
VTT_DDR
C149
C149
C0.1U16X
C0.1U16X
C117
C117
C0.1U16X
C0.1U16X
C31
C31
C0.1U16X
C0.1U16X
C83
C83
C0.1U16X
C0.1U16X
C32
C32
C0.1U16X
C0.1U16X
C77
C77
C0.1U16X
C0.1U16X
C100
C100
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
2
C152
C152
C110
C110
C0.1U16X
C0.1U16X
C135
C135
C0.1U16X
C0.1U16X
C69
C69
C146
C146
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
DDR Terminatior
DDR Terminatior
DDR Terminatior
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
C142
C142
C128
C128
C0.1U16X
C0.1U16X
MS-7310
MS-7310
MS-7310
C93
C93
C0.1U16X
C0.1U16X
C0.1U16X
C0.1U16X
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 31, 2006
Monday, July 31, 2006
Monday, July 31, 2006
Sheet
Sheet
Sheet
1
C33
C33
Rev
Rev
Rev
0A
0A
0A
830
830
830
of
of
of
Voltage Regular Module
VCC3 VCC
R32
R32
VID[0..4]4
1KR
C3
C0.1U25YC3C0.1U25Y
VCC
1KR
C37
C37
C0.1U25Y
C0.1U25Y
R4 5.1KR1%R4 5.1KR1%
C12
C12
X_C1000P50X
X_C1000P50X
C0.01U50X
C0.01U50X
R10 X_75KR1%R10 X_75KR1%
R21 X_75KR1%R21 X_75KR1%
R27 9.1KR1%-LFR27 9.1KR1%-LF
COP COMP
C220P50NC17 C220P50NC17
R23 1KRR23 1KR
X_C560P50XC9 X_C560P50XC9
C22
C22
R29 150KRR29 150KR
R28 1.5KRR28 1.5KR
C34 C0.047U16XC34 C0.047U16X
R11
R11
4.7KR
4.7KR
PG_VCORE4,25
PWM_EN14,25
R12 51RR12 51R
VCCP
COREFB+4
COREFB-4
CHECK THIS! CONNECT TO
BULK CAPACITOR
R13 51RR13 51R
Close low side
mosfet
C5600P50XC4 C5600P50XC4
R16 X_750RR16 X_750R
C21
C21
C0.01U50X
C0.01U50X
VCCP
VID4
VID3
VID2
VID1
VID0
OFS
C16
C16
C0.01U50X
C0.01U50X
ISL6566CR_QFN40
ISL6566CR_QFN40
FB
VDIFF
FS
REF
C35
C35
C0.01U50X
C0.01U50X
U2
U2
38
VID4
39
VID3
40
VID2
1
VID1
2
VID0
3
DACSEL/VID5
35
PGOOD
37
ENLL
8
COMP
9
FB
10
VDIFF
12
VSEN
11
RGND
6
OFST
36
FS
5
REF
4
VRM10
13
OCSET
14
ICOMP
15
ISUM
16
IREF
R44 12KR1%R44 12KR1%
R47 12KR1%R47 12KR1%
R45 12KR1%R45 12KR1%
VCC
+12VIN
DZ1
DZ1
S-1N5817_DO214AC
S-1N5817_DO214AC
C15
C15
C4.7U10Y0805
C4.7U10Y0805
7
PVCC1
BOOT1
VCC
UGATE1
PHASE1
ISEN1
LGATE1
PVCC2
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PVCC3
BOOT3
UGATE3
PHASE3
ISEN3
LGATE3
GND
41
BOTTOM PAD CONNECT TO GND
THROUGH 10 vias
PHASE1
PHASE2
PHASE3
C157
C157
X_C0.01U50X
X_C0.01U50X
12VP1
33
BOOT1
30
31
29
32
34
24
26
27
28
25
23
18
21
20
22
19
17
R36 2.2R0805R36 2.2R0805
U_G1
PHASE1
R34 2KR1%0402R34 2KR1%0402
L_G1
12VP2
BOOT2
R38 2.2R0805R38 2.2R0805
U_G2
PHASE2
R37 2.2KR1%-LFR37 2.2KR1%-LF
L_G2
12VP3
BOOT3
R39 2.2R0805R39 2.2R0805
U_G3
PHASE3
R40 2.49KR1%R40 2.49KR1%
L_G3
JPW1
JPW1
3
GND
12V
4
GND
12V
PWR-2X2M
PWR-2X2M
C41 C1U16Y0805C41 C1U16Y0805
R41 2.2R0805R41 2.2R0805
C44
C44
C0.1U25X
C0.1U25X
C39 C1U16Y0805C39 C1U16Y0805
R46 2.2R0805R46 2.2R0805
C42
C42
C0.1U25X
C0.1U25X
C38 C1U16Y0805C38 C1U16Y0805
R30 2.2R0805R30 2.2R0805
C45
C45
C0.1U25X
C0.1U25X
TDP = 115 W
VR_TDC = 101 A
Icc(max) = 119 A
1
2
+12VP_FET
+
+
+
+12VIN
+12VIN
+12VIN
C580
C580
X_C0.1U25X
X_C0.1U25X
C581
C581
X_C0.1U25X
X_C0.1U25X
C582
C582
X_C0.1U25X
X_C0.1U25X
CD1000U16EL20-2
CD1000U16EL20-2
U_G1
R56 1R0805R56 1R0805
R54 10KRR54 10KR
PHASE1
L_G1
R24 X_10KRR24 X_10KR
U_G2
R59 1R0805R59 1R0805
R58 10KRR58 10KR
PHASE2
L_G2
R55 X_10KRR55 X_10KR
R68 1R0805R68 1R0805
R75 10KRR75 10KR
PHASE3
L_G3
R60 X_10KRR60 X_10KR
+
N-P70N02LDG_TO252
N-P70N02LDG_TO252
N-P70N02LDG_TO252
N-P70N02LDG_TO252
N-P70N02LDG_TO252
N-P70N02LDG_TO252
EC10
EC10
EC13
EC13
CD1000U16EL20-2
CD1000U16EL20-2
UG1
EC7
EC7
CD1000U16EL20-2
CD1000U16EL20-2
UG2
EC4
EC4
CD1000U16EL20-2
CD1000U16EL20-2
UG3U_G3
G
G
+12VP_FET
+
+
G
G
+12VP_FET
+
+
G
G
Tejas Tcase = [P x 0.213] + 43.3
Prescott Tcase = [P x 0.25] +
43.3
C60 C4.7U35Y1206C60 C4.7U35Y1206
C98 C1U16Y0805C98 C1U16Y0805
DS
Q5N-P60N03LD_TO252 Q5N-P60N03LD_TO252
X_N-P70N02LDG_TO252
X_N-P70N02LDG_TO252
DS
Q2
Q2
G
C94 X_C4.7U35Y1206C94 X_C4.7U35Y1206
C64 C1U16Y0805C64 C1U16Y0805
DS
Q8N-P60N03LD_TO252 Q8N-P60N03LD_TO252
X_N-P70N02LDG_TO252
X_N-P70N02LDG_TO252
DS
Q6
Q6
G
C65 C4.7U35Y1206C65 C4.7U35Y1206
C40 C1U16Y0805C40 C1U16Y0805
DS
Q11N-P60N03LD_TO252 Q11N-P60N03LD_TO252
X_N-P70N02LDG_TO252
X_N-P70N02LDG_TO252
DS
Q9
Q9
G
X_C4.7U35Y1206
X_C4.7U35Y1206
R53
DS
DS
DS
R53
Q4
Q4
2.2R0805
2.2R0805
C49
C49
C1000P50X
C1000P50X
R57
R57
2.2R0805
2.2R0805
Q7
Q7
C63
C63
C1000P50X
C1000P50X
R64
R64
2.2R0805
2.2R0805
Q10
Q10
C99
C99
C1000P50X
C1000P50X
COIL4CH-1.2U18A COIL4CH-1.2U18A
+12VIN
C158
C158
COIL1
COIL1
0.25uH/40A
0.25uH/40A
0.8375~1.6V / 119A
COIL2
COIL2
0.25uH/40A
0.25uH/40A
COIL3
COIL3
0.25uH/40A
0.25uH/40A
VCCP
VCCP
VCCP
EL Capacitors
VCCP
EC6
EC6
+
+
CD1800U6.3EL20-1
CD1800U6.3EL20-1
EC5
EC5
+
+
CD1800U6.3EL20-1
CD1800U6.3EL20-1
EC8
EC8
+
+
CD1800U6.3EL20-1
CD1800U6.3EL20-1
EC2
EC2
+
+
EC12
EC12
+
+
1 2
EC9
EC9
+
+
CD1800U6.3EL20-1
CD1800U6.3EL20-1
X_CD1800U6.3EL20-1
X_CD1800U6.3EL20-1
X_.CD3300U6.3EL25
X_.CD3300U6.3EL25
Rds(on)=8.7mΩ(@4.5V,30A),Vgs(on)=1.2~2V,Id=50A,Ciss=3110pf,Qg=10nC,Vds=25V,Vgs=±20VIPF06N03LA
ESR<13mΩ,Ripple cur.<2.7A,LC<12uA,105CC100U2SP
.CD3300U6.3EL25 ESR<12mΩ,Ripplecur.<2800mA,105C,longlife3000hrs,KZGSeries
ESR=6mΩ,Ripplecur.=4400mA,Lc.<500uA,105C/2000hrs560u_2.5V
1800UF/6.3V ESR<12mΩ, Ripplecur<2350mA,105C, longlife change from 2000hrs to 3000hrs ,KZJ series
0.6u/20%, Isat=40A,Rdc=1.2m ohm,PEW wire0.6uH/40A
CH-1.2U18A 1.2u/20%,Dip-2/vertical7.5mm,1.2ψ/5.5turns,18A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
DDR Terminatior
DDR Terminatior
DDR Terminatior
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
MS-7310
MS-7310
MS-7310
Last Revision Date:
Last Revision Date:
Last Revision Date:
Monday, July 31, 2006
Monday, July 31, 2006
Monday, July 31, 2006
Sheet
Sheet
Sheet
930
930
930
Rev
Rev
Rev
0A
0A
0A
of
of
of
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