MSI MS-7309 Schematic 0A
5
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Date: 2009.10.11
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4
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MS-7309
D D
CPU:
AMD AM2 Socket940
System Chipset:
North Bridge --- MCP61-P/S/V
South Bridge --- NA
OnBoard Chipset:
Clock Gen:NA
AC'97 Codec:ALC861/883, Azalia 8 channel codec(with 1 SPDIF out)
C C
B B
LAN(PHY):Realtek RT8201CL(10/100)/Realtek RT8211B(Giga)
SIO:Fintek 882(with smart fan control-3/4 pin co-lay)
Flash ROM:4MB SPI
IEEE 1394:VIA VT6307/VT6308
Main Memory:
DDRII (400/533/667/800MHz) * 2 (Dual Channel)
Expansion Slots:
PCI Express (X16) Slot * 1
PCI Express (X1) Slot * 1
PCI Slot * 2
PWM:
Controller:ISL6566CRZ (3-Phase)
ACPI:
WINBOND / MS6 Ver: RBF
uATX(244mm X 205mm)
Cover Sheet 1
Block disgram 2
Device MAP
GPIO Table 4
Clock Distribution
CPU:AM2
DDR2 DIMM(Dual Channel)
Vcore:ISL6566CR(3 Phase)
MCP61
PEX CONN
PCI CONN
IDE,FAN,VGA CONN
USB
LAN
Azalia Codec
IEEE1394
SIO:F71882FG
ACPI Power Controller:MS-6
KB/MS,LPT,COM,Floppy CONN
System Regulators
Option Parts
For EMI
History 34
Power Delivery 35
PageTitle
3
5
6,7,8,9
10,11
12
13-19
20
21
22
23
24
25
26
27
28
29
30
31Front Pannel
32
33
Other:
A A
IDE(DMA133) *1
FDD *1
SATA(SATA2-300MB/S) *2
USB2.0 *8(Rear*4 Front*4)
COM PORT *1
LPT PORT *1
5
Title
Title
Title
Cover Sheet
Cover Sheet
Cover Sheet
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet of
Date: Sheet of
4
3
2
Date: Sheet
1
of
135Tuesday, July 18, 2006
135Tuesday, July 18, 2006
135Tuesday, July 18, 2006
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AMD
VRM ISL6566CR
3-Phase PWM
D D
HyperTransport LINK0
PCIE X16
PCIE X1
Rear port x 4
C C
Front port x 4
Realtek
RT8201CL(10/100)
Realtek
RT8211B(Giga)
PCIE X16
PCIE X1
USB2.0
1G
nVIDIA
AM2-940
LINK0
16x16
MCP61
DDR400/533/667/800
DDRII
DDR400/533/667/800
CRT
AC LINK
SATA-II Link
VGA CON
UNBUFFERED DDR
DIMM1
240-PIN DDRII
UNBUFFERED DDR
DIMM2
240-PIN DDRII
Azalia CODEC
ALC861(8CH)
SATA-II Port
#1~2
ATA 66/100/133
IDE*1
PCI BUS
B B
A A
IEEE 1394
VIA
VT6307/6308
Rear x1
Front x1
5
PCI SLOT x2
ACPI MS6
CONTROLLER
MS11 for
DDR Power
Fintek 882
KB &
FLOPPY
LPT
*1 *1 *1 *1
MOUSE
4
SERIAL
PORTS
FAN
CONTROL
Vcore
CONTROL
LPC
LPC Pin
Header
3
SPI SPI
Header
SPI FLASH ROMSPI Pin
4M
Title
Title
Title
Block diagram
Block diagram
Block diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet of
2
Date: Sheet of
1
of
235Monday, July 17, 2006
235Monday, July 17, 2006
235Monday, July 17, 2006
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PCI RESET DEVICE
MCP61
Signals
PCI_RESET0*
PCI_RESET1*
D D
PCI_RESET2* MS6
PCI_RESET3*
LPC_RESET*
Target
PCISLOT1
PCISLOT2
1394
LPC/SIO
MS6
Signals Target
HDD_RST# IDE
DDR DIMM Config.
DEVICE
C C
DIMM 1
CH-A
DIMM 2
CH-B
USB
Rear
B B
Front
10100000B
10100001B
Port DATA +/-
USB1
LAN_USB1
JUSB1
JUSB2
CLOCKADDRESS
MEM_MA0_CLK_H0/L0
MEM_MA0_CLK_H1/L1
MEM_MA0_CLK_H2/L2
MEM_MB0_CLK_H0/L0
MEM_MB0_CLK_H1/L1
MEM_MB0_CLK_H2/L2
OC#
USB0USB0+
USB1USB1+
USB2USB2+
USB3USB3+
USB4USB4+
USB5USB5+
USB6USB6+
USB7USB7+
USB_OC#0
( OC#0~1 )
USB_OC#2
( OC#2~3 )
USB_OC#4
( OC#4~5 )
USB_OC#6
( OC#6~7 )
PCI Config.
DEVICE MCP1 INT Pin
PCI_INT#Y
PCI Slot 1
PCI_INT#W
PCI_INT#X
PCI_INT#X
PCI Slot 2
IEEE1394 PCI_INT#Z
LPC
SIO
PCI_INT#Y
PCI_INT#Z
PCI_INT#W
REQ#/GNT#
PCI_REQ1#
PCI_GNT1#
PCI_REQ2#
PCI_GNT2#
PCI_GNT0#
IDSEL
AD26
AD25
AD24
CLOCK
PCI_CLKSLOT1PCI_INT#Z
(PCICLK1)
PCI_CLKSLOT2
(PCICLK2)
PCICLK_1394PCI_REQ0#
(PCICLK0)
LPC_PCLK
SIO_PCLK
CPU VID TABLE
VID
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000 1.1500V
10001
10010
10011 1.0750V
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
VOLTAGE
1.5500V
1.5250V
1.5000V
1.4750V
1.4500V
1.4250V
1.4000V
1.3750V
1.3500V
1.3250V
1.3000V
1.2750V
1.2500V
1.2250V
1.2000V
1.1750V
1.1250V
1.1000V
1.0500V
1.0250V
1.0000V
0.9750V
0.9500V
0.9250V
0.9000V
0.8750V
0.8500V
0.8250V
0.8000V
0.7750V
A A
Title
Title
Title
Device Map
Device Map
Device Map
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
5
4
3
2
Date: Sheet
Date: Sheet
Date: Sheet
of
335Monday, July 17, 2006
of
335Monday, July 17, 2006
of
335Monday, July 17, 2006
1
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MCP61 GPIO TABLE
D D
C C
B B
PIN NAME
THERMTRIP*/GPIO58
PROCHOT*/GPIO20
MII_RXER/GPIO36
MII_COL/GPIO13/MI2C_DATA
MII_CRS/GPIO14/MI2C_CLK
RGMII/MII_INTR*/GPIO35
RGMII/MII_PWRDWN*/GPIO37
MII_RESET*/GPIO12
DDC_CLK/GPIO17
DDC_DATA/GPIO19
PCI_REQ2*/GPIO40.RS232_DSR*
PCI_REQ3*/GPIO38/RS232_CTS*
PCI_GNT2*/GPIO41/RS232_DTR*
PCI_GNT3*/GPIO39/RS232_RTS*
PCI_PERR*/GPIO43/RS232_DCD*
PCI_PME*/GPIO30
LPC_PWRDWN*/GPIO54/EXT_NMI*
LPC_DRQ0*/GPIO50
LPC_DRQ1*/GPIO15/FANRPM1
CABLE_DET_P/GPIO63
SATE_LED*/GPIO57
HDA_SDATA_OUT0/GPIO45
HDA_SDATA_IN0/GPIO22
HDA_SDATA_IN1/GPIO23/MGPIO0
HDA_SYNC/GPIO44
GPIO_1
GPIO_2/NMI*/PS2_CLK0
GPIO_3/SMI*/PS2_DATA0
GPIO_4/SCI_INTR/PS2_CLK1
GPIO_5/INIT*/PS2_DATA2
GPIO_6/FERR*/SYS_FERR*
GPIO_7/NFERR*/SYS_PERR*
GPIO_8/SPI_DI
GPIO_9/SPI_DO
GPIO_10/SPI_CS
GPIO_11/SPI_CLK
USB_OC0*/GPIO25
USB_OC1*/GPIO26
USB_OC2*/GPIO27
USB_OC3*/GPIO28/MGPIO_1
USB_OC4*/GPIO29
A20GATE/GPIO55
EXT_SMI*/GPIO32
RI*/GPIO33
SIO_PME*/GPIO31
KBRDRSTIN*/GPIO56
SUS_CLK/GPIO34
THERM*/GPIO59
FANRPM0/GPIO60
FANCTL0/GPIO61
FANCTL1/GPIO62
THERM_SIC/GPIO48
THERM_SID0/GPIO49
PE_WAKE*/GPIO21
FUNCTION
CPU_THERMTRIP*
PROCHOT*
MII_RXER
MII_COL
MII_CRS
Pull High 10K to 3VDUAL
-MII_RESET*
DDC_CLK
DDC_DATA
PCI_REQ2*
Pull High 10K to 3VDUAL
PCI_GNT2*
-PCI_PERR*
PCI_PME*
-LPC_DRQ0*
--
CABLE_DET_P
SATE_LED*
HDA_SDATA_OUT
HDA_SDATA_IN0
-HDA_SYNC
--
--
--
--
--
--
--
--
--
--
-USB_Rear_1_0OC*
USB_Rear_3_2OC*
USB_FNTPNL_5_4OC*
USB_FNTPNL_7_6OC*
Pull High 10K to 3VDUAL(USB not USE)
AGATE20
EXT_SMI*
Internal 10K pull-up to vcc3
SIO_PME*
SIO_KBRST*
-THERM*
--
--
-Internal 10K pull-up to vcc3
-PE_WAKE*
SIO GPIO TABLE
GROUP
UART & SIR
Hardware Monitor
ACPI Function Pins
VID Controller
PIN NAME
IRTX/GPIO42
IRRX/GPIO43
GPIO17
FANIN3/GPIO40
FAN_CTL3/GPIO41
PME#/GPIO25
GPIO10/SPISLK/FININ4
GPIO11/SPI_CS0#/FAN_CTL4
FPIO12/SPI_MISO/FANCTL1_1
GPIO13/SPI_MOSI/BEEP
GPIO14/FWH_DIS/WDTRST#/SPI_CS1#
GPIO15/LED_VSB/ALERT#
GPIO16/LED_VCC/Turbo2#
PCIRST1#/GPIO20
PCIRST2#/GPIO21
PCIRST3#/GPIO22
GPIO23/RSTCON#
ATXPG_IN/GPIO24
PWROK/GPIO32
PWSIN#/GPIO26
PWSOUT#/GPIO27
S3#/GPIO30
PSON#/GPIO31
RSMRST#/GPIO33
VIDOUT0/GPIO0
VIDOUT1/GPIO1
VIDOUT2/GPIO2
VIDOUT3/GPIO3
VIDOUT4/GPIO4
VIDOUT5/GPIO5/SIC
SLOTOCC#/GPIO6
GPIO7/Turbo1#/WDTRST#
FUNCTION
--
--
--
--
-PME#
SPI_SLK
SPI_CS0#
SPI_MISO
SPI_MOSI
SPI_CS1#
-CPU_FAN_GPO
--
--
--
-ATXPG_IN
-PWSIN#
PWSOUT#
S3#
PSON#
--
VIDOUT0
VIDOUT1
VIDOUT2
VIDOUT3
VIDOUT4
SIC
SLOTOCC#
--
A A
Title
Title
Title
GPIO Table
GPIO Table
GPIO Table
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
435Monday, July 17, 2006
435Monday, July 17, 2006
435Monday, July 17, 2006
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AMD
AM2
MEMORY_A0_CLK[2:0]
MEMORY_A0_CLK[2:0]#
3 PAIR MEM CLK
DIMM1-CHADIMM2-CHB
HT_CPU_RXCLK[1:0]#
D D
HT_CPU_RXCLK[1:0]
HT_CPU_TXCLK[1:0]
HT_CPU_TXCLK[1:0]#
CPUCLK_IN
CPUCLK_IN#
MEMORY_B0_CLK[2:0]
MEMORY_B0_CLK[2:0]#
3 PAIR MEM CLK
Dual Chanel
NVIDIA
CLKOUT_200MHZ
CLKOUT_200MHZ#
C C
HT_CPU_TXCLK[1:0]
HT_CPU_TXCLK[1:0]#
HT_CPU_RXCLK[1:0]
HT_CPU_RXCLK[1:0]#
MCP61
B B
PE0_REFCLK
PE0_REFCLK#
PE1_REFCLK
PE1_REFCLK#
BUF_SIO
LPC_CLK0
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
24MHZ
SIO_PCLK
PCICLK_1394
PCICLK_SLOT1
PCICLK_SLOT2
PEX_X16
PEX_X1
SIO
SPI_CLK
PCICLK
1394
PCICLK
SPI ROM
#1
SPI_CLK
#2
PCI_SLOT1
PCI_SLOT2
PCI_CLKIN
LPC_CLK1
LPC_PCLK
LPC HEADER
HDA CODEC
HDA_BITCLK
32.768 KHZ
A A
25 MHZ
RTC_XTAL
XTAL_IN
XTAL_OUT
MII_TXCLK
MII_RXCLK
BUF_25MHZ
5
4
HDA_BITCLK
MII_TXCLK
BUF_25MHZ
3
MII_RXCLK
HDA_BITCLK
LAN PHY
MII_TXCLK
MII_RXCLK
BUF_25MHZ
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet of
2
Date: Sheet of
1
of
535Monday, July 17, 2006
535Monday, July 17, 2006
535Monday, July 17, 2006
5
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L0_CLKIN_H(1)
L0_CLKIN_L(1)
L0_CLKIN_H(0)
L0_CLKIN_L(0)
L0_CTLIN_H(1)
L0_CTLIN_L(1)
L0_CTLIN_H(0)
L0_CTLIN_L(0)
L0_CADIN_H(15)
L0_CADIN_L(15)
L0_CADIN_H(14)
L0_CADIN_L(14)
L0_CADIN_H(13)
L0_CADIN_L(13)
L0_CADIN_H(12)
L0_CADIN_L(12)
L0_CADIN_H(11)
L0_CADIN_L(11)
L0_CADIN_H(10)
L0_CADIN_L(10)
L0_CADIN_H(9)
L0_CADIN_L(9)
L0_CADIN_H(8)
L0_CADIN_L(8)
L0_CADIN_H(7)
L0_CADIN_L(7)
L0_CADIN_H(6)
L0_CADIN_L(6)
L0_CADIN_H(5)
L0_CADIN_L(5)
L0_CADIN_H(4)
L0_CADIN_L(4)
L0_CADIN_H(3)
L0_CADIN_L(3)
L0_CADIN_H(2)
L0_CADIN_L(2)
L0_CADIN_H(1)
L0_CADIN_L(1)
L0_CADIN_H(0)
L0_CADIN_L(0)
CADIP[0..15]
CADIN[0..15]
CADOP[0..15]
CADON[0..15]
CPU1A
CPU1A
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
CADOP15
Y5
CADON15
Y4
CADOP14
AB6
CADON14CADIN14
AA6
CADOP13
AB5
CADON13
AB4
CADOP12
AD6
CADON12
AC6
CADOP11
AF6
CADON11
AE6
CADOP10
AF5
CADON10
AF4
CADOP9
AH6
CADON9
AG6
CADOP8
AH5
CADON8
AH4
CADOP7
Y1
CADON7
W1
CADOP6
AA2
CADON6
AA3
CADOP5
AB1
CADON5
AA1
CADOP4
AC2
CADON4
AC3
CADOP3
AE2
CADON3
AE3
CADOP2
AF1
CADON2
AE1
CADOP1
AG2
CADON1
AG3
CADOP0
AH1
CADON0
AG1
CADIP[0..15]13
CADIN[0..15]13
CADOP[0..15]13
CADON[0..15]13
CLKIP113
D D
VCC1_2HT
C C
CLKIN113
CLKIP013
CLKIN013
R108 49.9R1%/4R108 49.9R1%/4
R109 49.9R1%/4R109 49.9R1%/4
CTLIP013
CTLIN013
CADIP15
CADIN15
CADIP14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
N6
P6
N3
N2
V4
V5
U1
V1
U6
V6
T4
T5
R6
T6
P4
P5
M4
M5
L6
M6
K4
K5
J6
K6
U3
U2
R1
T1
R3
R2
N1
P1
L1
M1
L3
L2
J1
K1
J3
J2
4
CLKOP1 13
CLKON1 13
CLKOP0 13
CLKON0 13
TP11TP11
TP10TP10
CTLOP0 13
CTLON0 13
CPUCLKO_H13
Layout : Place R63
within 0.5 inch of CPU
CPUCLKO_L13
R99
R99
300R/4
300R/4
SIO_THERM_SIC27
SIO_THERM_SID27
If SI is not used,the SID
pin can be left unconnector
and SIC should have a 300
ohm pulldown to VSS
VCC_DDR
R105
R105
39.2R1%/6
39.2R1%/6
R106
R106
39.2R1%/6
39.2R1%/6
VCC_DDR
R58
R58
15R1%/6
15R1%/6
15 mils
CPU_M_VREF
C60
R57
R57
15R1%/6
15R1%/6
C63
C63
C0.1u10X/4
C0.1u10X/4
C60
C102p50X/6
C102p50X/6
VCC_DDR
C64
C64
C392p50X/6
C392p50X/6
C67
C67
C392p50X/6
C392p50X/6
MEMZN
MEMZP
3
VDDA_25
R101
R101
300R/4
300R/4
SIO_THERM_SIC
SIO_THERM_SID
R98
R98
X_300R/4
X_300R/4
10/5/10
VCC_DDR
L1
80S-2A/8L180S-2A/8
2 1
R63
R63
169R1%/6
169R1%/6
5/6/20
CPUCLKIN_H
CPUCLKIN_L
VCC_DDR
TP19TP19
TP15TP15
TP14TP14
TP21TP21
TP2TP2
COREFB_H12
COREFB_L12
TP9TP9
R59 510R/6R59 510R/6
R62 510R/6R62 510R/6
THERMDC_CPU27
THERMDA_CPU27
C53
C53
C4.7u16Y/1206
C4.7u16Y/1206
R107 1KR/4R107 1KR/4
CPU_TEST25_H
CPU_TEST25_L
R50 300R/4R50 300R/4
R51 300R/4R51 300R/4
TP5TP5
TP7TP7
TP8TP8
TP4TP4
TP12TP12
C59
C59
C0.22u16X/6
C0.22u16X/6
LDT_PWRGD_L
LDT_STOP#_L
LDT_RST#_L
CPU_PRESENT_L
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB_H
COREFB_L
CPU_VTT_SENSE
VDDA25
C57
C57
C332p50X/4
C332p50X/4
CPU_M_VREF
AL10
AJ10
AH10
AH11
AJ11
C10
D10
A8
B8
C9
D8
C7
AL3
AL6
AK6
AL9
A5
G2
G1
E12
F12
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AG9
AG8
AH7
AJ6
CPU1D
CPU1D
MISC
MISC
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
THERMTRIP_L
SIC
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
2
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
PROCHOT_L
TDO
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
D2
D1
C1
E3
E2
E1
AK7
AL7
AK10
CPU_DBRDY
B6
CPU_VDDIOFB_H
AK11
CPU_VDDIOFB_L
AL11
CPU_PSI_L
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
VID4
VID3
VID2
VID1
VID0
CPU_THRIP#
PROCHOT#
CPU_TDOCPU_TDI
HTREF1
HTREF0
FBCLKOUT
FBCLKOUT#
8/5/20
R110 300R/4R110 300R/4
VCC_DDR
TP1TP1
CPU_THRIP# 13
TP17TP17
TP3TP3
TP6TP6
R56
R56
80.6R1%/6
80.6R1%/6
TP20TP20
TP16TP16
TP18TP18
TP13TP13
VCC_DDR
R75
R75
X_300R/4
X_300R/4
VCC_DDR
Layout :
1)Place R56 within
0.5 inch
R100
R100
300R/4
300R/4
VCC_DDR
1
R102
R102
X_300R/4
X_300R/4
VID[0..4] 27
C157
C157
C102p50X/4
C102p50X/4
PROCHOT# 13
Layout : Place
with in 1 inch
R103 44.2R1%/6R103 44.2R1%/6
R104 44.2R1%/6R104 44.2R1%/6
C158
C158
C102p50X/4
C102p50X/4
VCC1_2HT
For S3 issue(LDT RST can not still low)
If pop U4,remove RN6;
Else remove U4 & RN5, then pop RN6
VCC_DDR
RN7
RN7
8P4R-330R/6
8P4R-330R/6
1
2
4
6
8
-LDTSTOP
CPU_GD
-LDT_RST
LDT_RST#_L
LDT_PWRGD_L
LDT_STOP#_L
1
3
5
7
-LDTSTOP13
ATX_PWR_OK18,27,28,31
RN6
RN6
8P4R-0R/6
8P4R-0R/6
LDT_STOP#_L
2
LDT_PWRGD_L
4
LDT_RST#_L
6
8
B B
A A
5
3
5
7
4
-LDTSTOP
ATX_PWR_OK
-LDT_RST
CPU_GD
-LDTSTOP
VCC_DDR
147
1 2
VCC_DDR
147
3 4
RN5
RN5
X_8P4R-330R/6
X_8P4R-330R/6
1
3
5
7
U4A
U4A
X_7407_SOIC14
X_7407_SOIC14
U4B
U4B
X_7407_SOIC14
X_7407_SOIC14
3
2
4
6
8
VDDA_25
LDT_STOP#_L
CPU_GD13
ATX_PWR_OK18,27,28,31
ATX_PWR_OK18,27,28,31
ATX_PWR_OK LDT_PWRGD_L
ATX_PWR_OK
-LDT_RST13
CPU_GD
-LDT_RST
VCC_DDR
U4D
U4D
147
X_7407_SOIC14
X_7407_SOIC14
9 8
VCC_DDR
U4F
U4F
147
X_7407_SOIC14
X_7407_SOIC14
13 12
VCC_DDR
U4C
U4C
147
X_7407_SOIC14
X_7407_SOIC14
5 6
VCC_DDR
U4E
U4E
147
X_7407_SOIC14
X_7407_SOIC14
11 10
2
LDT_RST#_L
Title
Title
Title
CPU-HT & Straps
CPU-HT & Straps
CPU-HT & Straps
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet of
Date: Sheet of
Date: Sheet
1
of
635Friday, September 22, 2006
635Friday, September 22, 2006
635Friday, September 22, 2006
5
www.kythuatvitinh.com
MEMORY INTERFACE A
D D
C C
B B
MEM_MA0_CLK_H210,11
MEM_MA0_CLK_L210,11
MEM_MA0_CLK_H110,11
MEM_MA0_CLK_L110,11
MEM_MA0_CLK_H010,11
MEM_MA0_CLK_L010,11
MEM_MA0_CS_L110,11
MEM_MA0_CS_L010,11
MEM_MA0_ODT010,11
MEM_MA_CAS_L10,11
MEM_MA_WE_L10,11
MEM_MA_RAS_L10,11
MEM_MA_BANK210,11
MEM_MA_BANK110,11
MEM_MA_BANK010,11
MEM_MA_CKE010,11
MEM_MA_ADD[15..0]10,11
MEM_MA_DQS_H710
MEM_MA_DQS_L710
MEM_MA_DQS_H610
MEM_MA_DQS_L610
MEM_MA_DQS_H510
MEM_MA_DQS_L510
MEM_MA_DQS_H410
MEM_MA_DQS_L410
MEM_MA_DQS_H310
MEM_MA_DQS_L310
MEM_MA_DQS_H210
MEM_MA_DQS_L210
MEM_MA_DQS_H110
MEM_MA_DQS_L110
MEM_MA_DQS_H010
MEM_MA_DQS_L010
MEM_MA_DM710
MEM_MA_DM610
MEM_MA_DM510
MEM_MA_DM410
MEM_MA_DM310
MEM_MA_DM210
MEM_MA_DM110
MEM_MA_DM010
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
AC25
AA24
AC28
AE20
AE19
AD27
AA25
AC27
AB25
AB27
AA26
AA27
AC26
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
AF15
AF19
AJ25
AH29
G19
H19
U27
U26
G20
G21
V27
W27
N25
Y27
M25
M27
N24
N26
P25
Y25
N27
R24
P27
R25
R26
R27
U25
W24
D29
C29
C25
D25
E19
G15
B29
E24
E18
H15
L27
T25
T27
F19
F15
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
CPU1B
CPU1B
4
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
C26
G23
F23
E22
E21
F17
G17
G22
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11
MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DATA[63..0] 10
3
MEM_MB0_CLK_H210,11
MEM_MB0_CLK_L210,11
MEM_MB0_CLK_H110,11
MEM_MB0_CLK_L110,11
MEM_MB0_CLK_H010,11
MEM_MB0_CLK_L010,11
MEM_MB0_CS_L110,11
MEM_MB0_CS_L010,11
MEM_MB0_ODT010,11
MEM_MB_CAS_L10,11
MEM_MB_WE_L10,11
MEM_MB_RAS_L10,11
MEM_MB_BANK210,11
MEM_MB_BANK110,11
MEM_MB_BANK010,11
MEM_MB_CKE010,11
MEM_MB_ADD[15..0]10,11
MEM_MB_DQS_H710
MEM_MB_DQS_L710
MEM_MB_DQS_H610
MEM_MB_DQS_L610
MEM_MB_DQS_H510
MEM_MB_DQS_L510
MEM_MB_DQS_H410
MEM_MB_DQS_L410
MEM_MB_DQS_H310
MEM_MB_DQS_L310
MEM_MB_DQS_H210
MEM_MB_DQS_L210
MEM_MB_DQS_H110
MEM_MB_DQS_L110
MEM_MB_DQS_H010
MEM_MB_DQS_L010
MEM_MB_DM710
MEM_MB_DM610
MEM_MB_DM510
MEM_MB_DM410
MEM_MB_DM310
MEM_MB_DM210
MEM_MB_DM110
MEM_MB_DM010
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AC31
AD29
AD31
AC29
AC30
AH17
AJ19
AK19
U31
U30
AE30
AL19
AL18
C19
D19
W29
W28
AE29
AB31
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AJ23
AK29
C30
A23
B17
B13
A18
A19
2
MEMORY INTERFACE B
MEMORY INTERFACE B
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
CPU1C
CPU1C
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
1
MEM_MB_DATA[63..0] 10
A A
Title
Title
Title
CPU-Memory
CPU-Memory
CPU-Memory
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet of
5
4
3
2
Date: Sheet of
1
of
735Friday, September 22, 2006
735Friday, September 22, 2006
735Friday, September 22, 2006
5
www.kythuatvitinh.com
SLOTOCC#_CPU 27
VCORE
CPU1F
CPU1F
VDD1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD150
VDD151
VDD1
A4
A6
AA8
AA10
D D
C C
B B
AA12
AA14
AA16
AA18
AB7
AB9
AB11
AC4
AC5
AC8
AC10
AD2
AD3
AD7
AD9
AE10
AF7
AF9
AG4
AG5
AG7
AH2
AH3
E10
F11
G10
G12
H11
H23
J12
J14
J16
J18
J20
J22
J24
K11
K13
K15
K17
K19
K21
K23
L10
L12
Y17
Y19
B3
B5
B7
C2
C4
C6
C8
D3
D5
D7
D9
E4
E6
E8
F5
F7
F9
G6
G8
H7
J8
K7
K9
L4
L5
L8
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
VCORE
M11
M13
M15
M17
M19
N10
N12
N14
N16
N18
P11
P13
P15
P17
P19
R10
R12
R14
R16
R18
R20
T11
T13
T15
T17
T19
T21
U10
U12
U14
U16
U18
U20
V11
V13
V15
V17
V19
V21
W10
W12
W14
W16
W18
W20
Y11
Y13
Y15
Y21
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
N8
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
P7
VDD19
P9
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
U8
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
V9
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
VDD72
VDD73
VDD74
VDD75
CPU1G
CPU1G
VDD2
VDD2
4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
VCORE
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
L20
L22
M21
M23
N20
N22
P21
P23
R22
T23
U22
V23
W22
Y23
3
CPU1H
CPU1H
VDD3
VDD3
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
5
GND
6
GND
7
GND
8
GND
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
VCC_DDR
VCC1_2HT
VTT_DDR
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
CPU1I
CPU1I
VDDIO
VDDIO
2
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
H6
H5
H2
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
VLDT_RUN_B
VTT_DDR
C86
C86
C4.7u10Y/8
C4.7u10Y/8
C81
C81
X_C103p50X/6
X_C103p50X/6
C82
C82
X_C103p50X/6
X_C103p50X/6
1
C85
C85
X_C103p50X/6
X_C103p50X/6
A A
Title
Title
Title
CPU-Power & GND
CPU-Power & GND
CPU-Power & GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
835Friday, September 22, 2006
835Friday, September 22, 2006
835Friday, September 22, 2006
of
of
1
of
5
www.kythuatvitinh.com
4
3
2
1
VTT_DDR
C188
C194
C194
X_C180p50N/4
X_C180p50N/4
C189
C189
C180p50N/4
C180p50N/4
C466
C466
C10u6.3X/1206/B
C10u6.3X/1206/B
C188
C102p50X/6
C102p50X/6
C39
C39
C102p50X/6
C102p50X/6
C55
C55
C102p50X/6
C102p50X/6
C23
C23
C102p50X/6
C102p50X/6
C457
C457
C10u6.3X/1206/B
C10u6.3X/1206/B
C462
C462
C10u6.3X/1206/B
C10u6.3X/1206/B
C66
C48
C48
C0.22u16X/6
C0.22u16X/6
C177
C177
C0.22u16X/6
C0.22u16X/6
C66
C4.7u10Y/8
C4.7u10Y/8
C62
C62
X_C4.7u10Y/8
X_C4.7u10Y/8
C454
C454
C10u6.3X/1206/B
C10u6.3X/1206/B
C448
C448
C10u6.3X/1206/B
C10u6.3X/1206/B
C47
C47
C0.22u16X/6
D D
C C
B B
C0.22u16X/6
VTT_DDR
C181
C181
C0.22u16X/6
C0.22u16X/6
VCORE
C463
C463
C10u6.3X/1206/B
C10u6.3X/1206/B
VCORE
C458
C458
C10u6.3X/1206/B
C10u6.3X/1206/B
C58
C58
C4.7u10Y/8
C4.7u10Y/8
C192
C192
C4.7u10Y/8
C4.7u10Y/8
C259
C259
X_C180p50N/4
X_C180p50N/4
C168
C168
X_C180p50N/4
X_C180p50N/4
C443
C443
X_C22u6.3X/1206/B
X_C22u6.3X/1206/B
C440
C440
C10u6.3X/1206/B
C10u6.3X/1206/B
VCC_DDR
VCC_DDR
C447
C447
C10u6.3X/1206/B
C10u6.3X/1206/B
C453
C453
X_C22u6.3X/1206/B
X_C22u6.3X/1206/B
C456
C456
X_C22u6.3X/1206/B
X_C22u6.3X/1206/B
C171
C171
X_C22u6.3X/1206
X_C22u6.3X/1206
C469
C469
C0.22u16X/6/B
C0.22u16X/6/B
C450
C450
X_C0.22u16X/6/B
X_C0.22u16X/6/B
C442
C442
X_C22u6.3X/1206/B
X_C22u6.3X/1206/B
C155
C155
C2.2u6.3X/6
C2.2u6.3X/6
C173
C173
C0.22u16X/6
C0.22u16X/6
C439
C439
C10u6.3X/1206/B
C10u6.3X/1206/B
C136
C136
X_C22u6.3X/1206
X_C22u6.3X/1206
C90
C90
C0.22u16X/6
C0.22u16X/6
C444
C444
X_C0.22u16X/6/B
X_C0.22u16X/6/B
C92
C92
C2.2u6.3X/6
C2.2u6.3X/6
C97
C97
C2.2u6.3X/6
C2.2u6.3X/6
C73
C73
X_C22u6.3X/1206
X_C22u6.3X/1206
C146
C146
C103p50X/6
C103p50X/6
C461
C461
C10u6.3X/1206/B
C10u6.3X/1206/B
C91
C91
C180p50N/4
C180p50N/4
VCC1_2HT
C156
C156
C0.22u16X/6
C0.22u16X/6
VCC1_2HT
C191
C191
X_C4.7u16Y/1206
X_C4.7u16Y/1206
C159
C159
C0.22u16X/6
C0.22u16X/6
C166
C166
C4.7u16Y/1206
C4.7u16Y/1206
C174
C174
X_C0.22u16X/6
X_C0.22u16X/6
C179
C179
C0.22u16X/6
C0.22u16X/6
C162
C162
X_C0.22u16X/6
X_C0.22u16X/6
C187
C187
X_C0.22u16X/6
X_C0.22u16X/6
C182
C182
C4.7u16Y/1206
C4.7u16Y/1206
C185
C185
X_C0.22u16X/6
X_C0.22u16X/6
C93
C470
C437
C437
X_C0.22u16X/6/B
X_C0.22u16X/6/B
A A
C470
X_C0.22u16X/6/B
X_C0.22u16X/6/B
C436
C436
X_C0.22u16X/6/B
X_C0.22u16X/6/B
5
C93
C180p50N/4
C180p50N/4
C438
C438
X_C103p50X/6/B
X_C103p50X/6/B
Title
Title
Title
CPU-Decoupling
CPU-Decoupling
CPU-Decoupling
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet
4
3
2
Date: Sheet
1
of
935Thursday, September 14, 2006
of
935Thursday, September 14, 2006
of
935Thursday, September 14, 2006
5
www.kythuatvitinh.com
DIMM1
DIMM1
102
68
19
MEM_MA_DATA[63..0]7
D D
C C
B B
MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63
55
NC
NC
3
RC118RC0
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
100
VSS
VSS
103
106
VSS
109
NC/TEST
VSS
VSS
112
115
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
118
121
170
197
181
142
VDD7
VSS
175
VDD8
VSS
145
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
148
151
154
VDDQ469VDDQ7
VSS
VSS
VSS
157
160
163
172
166
191
194
75
VDD6
VDD3
VSS
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
139
187
VDDQ5
VSS
169
184
VDDQ6
VSS
198
178
VDDQ7
VSS
VSS
201
189
VDDQ8
VSS
204
67
VDDQ9
VSS
207
210
238
VSS
213
VDDSPD
VSS
4
CB042CB143CB248CB349CB4
VSS
VSS
216
219
222
VSS
225
161
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK1#(CK0#)
VSS
VSS
228
231
162
167
168
CB5
CB6
CB7
MEM_MA_DQS_H0
7
DQS0
MEM_MA_DQS_L0
6
DQS0#
MEM_MA_DQS_H1
16
DQS1
MEM_MA_DQS_L1
15
DQS1#
MEM_MA_DQS_H2
28
DQS2
MEM_MA_DQS_L2
27
DQS2#
MEM_MA_DQS_H3
37
DQS3
MEM_MA_DQS_L3
36
DQS3#
MEM_MA_DQS_H4
84
DQS4
MEM_MA_DQS_L4 MEM_MB_DATA10
83
DQS4#
MEM_MA_DQS_H5
93
DQS5
MEM_MA_DQS_L5
92
DQS5#
MEM_MA_DQS_H6
105
DQS6
MEM_MA_DQS_L6
104
DQS6#
MEM_MA_DQS_H7
114
DQS7
MEM_MA_DQS_L7
113
DQS7#
46
DQS8
45
DQS8#
MEM_MA_ADD0
188
A0
MEM_MA_ADD1
183
A1
MEM_MA_ADD2
63
A2
MEM_MA_ADD3
182
A3
MEM_MA_ADD4
61
A4
MEM_MA_ADD5
60
A5
MEM_MA_ADD6
180
A6
MEM_MA_ADD7
58
A7
MEM_MA_ADD8
179
A8
MEM_MA_ADD9
177
A9
MEM_MA_ADD10
70
A10_AP
MEM_MA_ADD11
57
A11
MEM_MA_ADD12
176
A12
MEM_MA_ADD13
196
A13
MEM_MA_ADD14
174
A14
MEM_MA_ADD15
173
A15
MEM_MA_BANK2
54
A16/BA2
MEM_MA_BANK1
190
BA1
MEM_MA_BANK0
71
BA0
MEM_MA_WE_L
73
WE#
MEM_MA_CAS_L
74
CAS#
MEM_MA_RAS_L
192
RAS#
MEM_MA_DM0
125
126
MEM_MA_DM1
134
135
MEM_MA_DM2
146
147
MEM_MA_DM3
155
156
MEM_MA_DM4
202
203
MEM_MA_DM5
211
212
MEM_MA_DM6
223
224
MEM_MA_DM7
232
233
164
165
MEM_MA0_ODT0
195
ODT0
77
ODT1
52
CKE0
171
CKE1
MEM_MA0_CS_L0
193
CS0#
MEM_MA0_CS_L1
76
CS1#
MEM_MA0_CLK_H0
185
CK0(DU)
MEM_MA0_CLK_L0
186
CK0#(DU)
MEM_MA0_CLK_H1
137
CK1(CK0)
MEM_MA0_CLK_L1
138
MEM_MA0_CLK_H2
220
CK2(DU)
MEM_MA0_CLK_L2
221
CK2#(DU)
SMB_MEM_CLK
120
SCL
SMB_MEM_DATA
119
SDA
VDDR_VREF
1
VREF
239
SA0
240
SA1
101
SA2
VSS
VSS
VSS
DDRII-240_GREEN
DDRII-240_GREEN
234
237
ADDRESS: 1010 000(A0)
MEM_MA_DQS_H0 7
MEM_MA_DQS_L0 7
MEM_MA_DQS_H1 7
MEM_MA_DQS_L1 7
MEM_MA_DQS_H2 7
MEM_MA_DQS_L2 7
MEM_MA_DQS_H3 7
MEM_MA_DQS_L3 7
MEM_MA_DQS_H4 7
MEM_MA_DQS_L4 7
MEM_MA_DQS_H5 7
MEM_MA_DQS_L5 7
MEM_MA_DQS_H6 7
MEM_MA_DQS_L6 7
MEM_MA_DQS_H7 7
MEM_MA_DQS_L7 7
MEM_MA_ADD[15..0] 7,11
MEM_MA_BANK2 7,11
MEM_MA_BANK1 7,11
MEM_MA_BANK0 7,11
MEM_MA_WE_L 7,11
MEM_MA_CAS_L 7,11
MEM_MA_RAS_L 7,11
MEM_MA_DM[7..0] MEM_MB_DM[7..0]
MEM_MA0_ODT0 7,11
MEM_MA_CKE0 7,11
MEM_MA0_CS_L0 7,11
MEM_MA0_CS_L1 7,11
MEM_MA0_CLK_H0 7,11
MEM_MA0_CLK_L0 7,11
MEM_MA0_CLK_H1 7,11
MEM_MA0_CLK_L1 7,11
MEM_MA0_CLK_H2 7,11
MEM_MA0_CLK_L2 7,11
SMB_MEM_CLK 18
SMB_MEM_DATA 18
C42
C42
C0.1u10X/4
C0.1u10X/4
MEM_MB_DATA[63..0]7
MEM_MA_DM[7..0] 7 MEM_MB_DM[7..0] 7
3
DIMM2
MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63
DIMM2
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
102
68
19
55
NC
3
RC118RC0
DQ0
4
DQ1
9
NC/TEST
DQ2
10
DQ3
DQ4
DQ5
DQ6
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
DQ12
DQ13
DQ14
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
DQ20
DQ21
DQ22
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
DQ28
DQ29
DQ30
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
DQ36
DQ37
DQ38
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
DQ44
DQ45
DQ46
DQ47
98
DQ48
99
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VSS
VSS
VSS
VSS
100
103
106
109
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
VSS
112
115
118
121
191
75
VDD3
VSS
VSS
VSS
VSS
VSS
124
127
130
133
136
2
VCC3VCC_DDRVCC3VCC_DDR
170
197
172
187
184
189
67
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
151
154
157
160
VDDQ5
VDDQ6
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
163
166
169
198
178
VDDQ7
VSS
201
VDDQ8
VSS
VSS
204
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VSS
VSS
VSS
VSS
139
142
145
148
VDDQ9
VSS
207
210
VSS
238
VDDSPD
VSS
213
216
CB042CB143CB248CB349CB4
VSS
VSS
219
222
VSS
VSS
225
161
162
CB5
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#
A10_AP
A16/BA2
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
VSS
VSS
VSS
228
231
234
167
168
CB6
CB7
7
DQS0
6
16
DQS1
15
28
DQS2
27
37
DQS3
36
84
DQS4
83
93
DQS5
92
105
DQS6
104
114
DQS7
113
46
DQS8
45
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
57
A11
176
A12
196
A13
174
A14
173
A15
54
190
BA1
71
BA0
73
WE#
74
CAS#
192
RAS#
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
ODT0
77
ODT1
52
CKE0
171
CKE1
193
CS0#
76
CS1#
185
186
137
138
220
221
120
SCL
119
SDA
1
VREF
239
SA0
240
SA1
101
SA2
VSS
DDRII-240_ORANGE
DDRII-240_ORANGE
237
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MB_RAS_L
MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7
MEM_MB0_ODT0
MEM_MB0_CS_L0
MEM_MB0_CS_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
SMB_MEM_CLK
SMB_MEM_DATA
VDDR_VREF
VCC3
MEM_MB_DQS_H0 7
MEM_MB_DQS_L0 7
MEM_MB_DQS_H1 7
MEM_MB_DQS_L1 7
MEM_MB_DQS_H2 7
MEM_MB_DQS_L2 7
MEM_MB_DQS_H3 7
MEM_MB_DQS_L3 7
MEM_MB_DQS_H4 7
MEM_MB_DQS_L4 7
MEM_MB_DQS_H5 7
MEM_MB_DQS_L5 7
MEM_MB_DQS_H6 7
MEM_MB_DQS_L6 7
MEM_MB_DQS_H7 7
MEM_MB_DQS_L7 7
MEM_MB_BANK2 7,11
MEM_MB_BANK1 7,11
MEM_MB_BANK0 7,11
MEM_MB_WE_L 7,11
MEM_MB_CAS_L 7,11
MEM_MB_RAS_L 7,11
MEM_MB0_ODT0 7,11
MEM_MB_CKE0 7,11
MEM_MB0_CS_L0 7,11
MEM_MB0_CS_L1 7,11
MEM_MB0_CLK_H0 7,11
MEM_MB0_CLK_L0 7,11
MEM_MB0_CLK_H1 7,11
MEM_MB0_CLK_L1 7,11
MEM_MB0_CLK_H2 7,11
MEM_MB0_CLK_L2 7,11
SMB_MEM_CLK 18
SMB_MEM_DATA 18
C41
C41
X_C0.1u10X/4
X_C0.1u10X/4
PLACE CLOSE TO DIMM PINPLACE CLOSE TO DIMM PIN
MEM_MB_ADD[15..0] 7,11
1
ADDRESS: 1010 001(A2)
VCC_DDR
C29
C29
R35
R35
X_C0.1u10X/4
X_C0.1u10X/4
56.2R1%/6
56.2R1%/6
R33
R33
56.2R1%/6
56.2R1%/6
C33
C33
C36
C36
X_C0.1u10X/4
X_C0.1u10X/4
C102p50X/6
C102p50X/6
A A
5
4
SMB_MEM_CLK SMB_MEM_DATAVDDR_VREF
3
2
D15
D15
BAV99_SOT23
BAV99_SOT23
1
3VDUAL3VDUAL
3
2
D13
D13
BAV99_SOT23
BAV99_SOT23
1
3
Title
Title
Title
DIMM-DDR II
DIMM-DDR II
DIMM-DDR II
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
MS-7309 0A
Date: Sheet
Date: Sheet
2
Date: Sheet
1
of
of
of
10 35Friday, September 22, 2006
10 35Friday, September 22, 2006
10 35Friday, September 22, 2006
5
www.kythuatvitinh.com
RTT:Place Behind DIMMs
VTT_DDR
RN16
RN16
8P4R-47R/4
MEM_MA_BANK27,10
MEM_MA_ADD147,10
D D
C C
VTT_DDR
B B
VTT_DDR
MEM_MB_ADD97,10
MEM_MB_ADD117,10
MEM_MA_ADD127,10
MEM_MB_ADD77,10
MEM_MA_ADD117,10
MEM_MA_ADD87,10
MEM_MA_ADD67,10
MEM_MA_ADD57,10
MEM_MB_ADD57,10 MEM_MA_ADD17,10
MEM_MB_ADD37,10
MEM_MA_ADD27,10
MEM_MB_ADD17,10
MEM_MB_ADD27,10
MEM_MB_BANK07,10
MEM_MA_BANK17,10
MEM_MA_ADD107,10
MEM_MB_RAS_L7,10
MEM_MA_WE_L7,10
MEM_MB_WE_L7,10
MEM_MA_CAS_L7,10
MEM_MA0_ODT07,10
MEM_MA_ADD137,10
MEM_MA0_CS_L17,10
C127
C127
C0.1u10X/4
C0.1u10X/4
C178
C178
X_C0.1u10X/4
X_C0.1u10X/4
C126
C126
C0.1u10X/4
C0.1u10X/4
C172
C172
X_C0.1u10X/4
X_C0.1u10X/4
MEM_MA_BANK2
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MB_ADD9 MEM_MB_ADD11
MEM_MB_ADD11
MEM_MA_ADD12
MEM_MB_ADD7
MEM_MA_ADD11
MEM_MA_ADD8
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MB_ADD5
MEM_MB_ADD3
MEM_MA_ADD2
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_BANK0
MEM_MA_BANK1
MEM_MA_ADD10
MEM_MB_RAS_L
MEM_MA_WE_L
MEM_MB_WE_L
MEM_MA_CAS_L
MEM_MA0_ODT0
MEM_MA_ADD13
MEM_MA0_CS_L1
C183
C121
C121
C0.1u10X/4
C0.1u10X/4
C183
C0.1u10X/4
C0.1u10X/4
C129
C129
X_C0.1u10X/4
X_C0.1u10X/4
C180
C180
X_C0.1u10X/4
X_C0.1u10X/4
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
C115
C115
C0.1u10X/4
C0.1u10X/4
8P4R-47R/4
2
4
6
8
RN17
RN17
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN20
RN20
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN22
RN22
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN24
RN24
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN26
RN26
8P4R-47R/4
8P4R-47R/4
2
4
6
8
R113
R113
47R/4
47R/4
R117
R117
47R/4
47R/4
C110
C110
C0.1u10X/4
C0.1u10X/4
C123
C123
C0.1u10X/4
C0.1u10X/4
C106
C106
C0.1u10X/4
C0.1u10X/4
C108
C108
C0.1u10X/4
C0.1u10X/4
MEM_MB_CKE07,10
MEM_MB_ADD157,10MEM_MA_ADD157,10
MEM_MB_ADD147,10
MEM_MA_ADD97,10
MEM_MA_ADD77,10
MEM_MB_ADD87,10
MEM_MB_ADD67,10
MEM_MA_ADD47,10
MEM_MA_ADD37,10
MEM_MB_ADD47,10
MEM_MB_ADD07,10
MEM_MB_BANK17,10
MEM_MA_ADD07,10
MEM_MB_ADD107,10
MEM_MA_BANK07,10
MEM_MA_RAS_L7,10
MEM_MB0_CS_L07,10
MEM_MA0_CS_L07,10
MEM_MB_BANK27,10
MEM_MB_ADD127,10
MEM_MA_CKE07,10
MEM_MB_CAS_L7,10
MEM_MB0_ODT07,10
MEM_MB_ADD137,10
MEM_MB0_CS_L17,10
4
C193
C193
C0.1u10X/4
C0.1u10X/4
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MA_ADD9
MEM_MA_ADD7
MEM_MB_ADD8
MEM_MB_ADD6
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MB_ADD4
MEM_MA_ADD1
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MA_ADD0
MEM_MB_ADD10
MEM_MA_BANK0
MEM_MA_RAS_L
MEM_MB0_CS_L0
MEM_MA0_CS_L0
MEM_MB_BANK2
MEM_MB_ADD12
MEM_MA_CKE0
MEM_MB_CAS_L
MEM_MB0_ODT0
MEM_MB_ADD13
MEM_MB0_CS_L1
C184
C184
C0.1u10X/4
C0.1u10X/4
C176
C176
C0.1u10X/4
C0.1u10X/4
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
C153
C153
C0.1u10X/4
C0.1u10X/4
RN14
RN14
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN18
RN18
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN21
RN21
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN23
RN23
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN25
RN25
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN15
RN15
8P4R-47R/4
8P4R-47R/4
2
4
6
8
RN28
RN28
8P4R-47R/4
8P4R-47R/4
2
4
6
8
VTT_DDR
C164
C164
C0.1u10X/4
C0.1u10X/4
3
C152
C152
C0.1u10X/4
C0.1u10X/4
C131
C131
C0.1u10X/4
C0.1u10X/4
2
Place Between Processor and DIMMs
VCC_DDR
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
C22p50N/4/BC446 C22p50N/4/BC446
C22p50N/4/BC441 C22p50N/4/BC441
C22p50N/4/BC479 C22p50N/4/BC479
C22p50N/4/BC445 C22p50N/4/BC445
C22p50N/4/BC449 C22p50N/4/BC449
C22p50N/4/BC476 C22p50N/4/BC476
C22p50N/4/BC455 C22p50N/4/BC455
C22p50N/4/BC459 C22p50N/4/BC459
C22p50N/4/BC452 C22p50N/4/BC452
C22p50N/4/BC465 C22p50N/4/BC465
C22p50N/4/BC460 C22p50N/4/BC460
C22p50N/4/BC464 C22p50N/4/BC464
C22p50N/4/BC467 C22p50N/4/BC467
C22p50N/4/BC468 C22p50N/4/BC468
C22p50N/4/BC471 C22p50N/4/BC471
C22p50N/4/BC474 C22p50N/4/BC474
C22p50N/4/BC475 C22p50N/4/BC475
C22p50N/4/BC478 C22p50N/4/BC478
C22p50N/4/BC477 C22p50N/4/BC477
C22p50N/4/BC451 C22p50N/4/BC451
C22p50N/4/BC472 C22p50N/4/BC472
C22p50N/4/BC473 C22p50N/4/BC473
MEM_MA0_CLK_H27,10
MEM_MA0_CLK_L27,10
MEM_MA0_CLK_H17,10
MEM_MA0_CLK_L17,10
MEM_MA0_CLK_H07,10
MEM_MA0_CLK_L07,10
MEM_MB0_CLK_H27,10
MEM_MB0_CLK_L27,10
MEM_MB0_CLK_H17,10
MEM_MB0_CLK_L17,10
MEM_MB0_CLK_H07,10
MEM_MB0_CLK_L07,10
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
1
C22p50N/4C101 C22p50N/4C101
C22p50N/4C95 C22p50N/4C95
C22p50N/4C160 C22p50N/4C160
C22p50N/4C98 C22p50N/4C98
C22p50N/4C100 C22p50N/4C100
C22p50N/4C142 C22p50N/4C142
C22p50N/4C109 C22p50N/4C109
C22p50N/4C103 C22p50N/4C103
C22p50N/4C107 C22p50N/4C107
C22p50N/4C116 C22p50N/4C116
C22p50N/4C105 C22p50N/4C105
C22p50N/4C120 C22p50N/4C120
C22p50N/4C111 C22p50N/4C111
C22p50N/4C118 C22p50N/4C118
C22p50N/4C124 C22p50N/4C124
C22p50N/4C132 C22p50N/4C132
C22p50N/4C133 C22p50N/4C133
C22p50N/4C150 C22p50N/4C150
C22p50N/4C147 C22p50N/4C147
C22p50N/4C102 C22p50N/4C102
C22p50N/4C125 C22p50N/4C125
C22p50N/4C130 C22p50N/4C130
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
VCC_DDR
C165
C165
C1.5p50N/4
C1.5p50N/4
C54
C54
C1.5p50N/4
C1.5p50N/4
C113
C113
C1.5p50N/4
C1.5p50N/4
C163
C163
C1.5p50N/4
C1.5p50N/4
C65
C65
C1.5p50N/4
C1.5p50N/4
C117
C117
C1.5p50N/4
C1.5p50N/4
VCC_DDR
A A
Title
Title
Title
DIMM-Termination
DIMM-Termination
DIMM-Termination
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
MS-7309 0A
MS-7309 0A
5
4
3
2
MS-7309 0A
Date: Sheet
Date: Sheet
Date: Sheet
11 35Friday, September 22, 2006
11 35Friday, September 22, 2006
11 35Friday, September 22, 2006
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