MSI MS-7307 Schematics

5

4

3

2

1

MSI

MS-7307 Ver:0A

D D

C C

B B

CPU:

AMD 940 Athlon 64/Sempron

System Chipset:

NVIDIA C51PV / C51PVG
NVIDIA MCP 51

On Board Chipset:

LPC Super I/O -- SMSC 5127
LAN Realtek 8201CL
Azalia Codec --ALC888
BIOS --LPC FLASH ROM 4M

Main Memory:

DDR * 2 (Max 2GB)

Expansion Slots:

PCI-E X 16 *1
PCI 2.3 Slot * 3

PWM:

Controller--Intersil ISL6566CR 3 Phase

Title Page

Cover Sheet 1
Block Diagram
AMD M2 940
DDR2 DIMM 1 & 2
DDR2 Termination Resistors

2
3,4,5
6

7
North bridge C51PVG 8-10
South bridge MCP51 11-14
PCI Slot 1,2 ,3
PCI-Express X 16
SIO-LPC5127 / BIOS
LAN Realtek 8201CL

Azalia CODEC & Interanl SPK

USB connectors
MS-6 ACPI Controller & MS-11
PWM - ISL6566CR
IDE &FDD & FAN
ATX Connector / Front Panel
VGA Connector
MANUAL PARTS
GPIO SPEC
POWER MAP
POWER OK MAP
RESET MAP
History

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

A A

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

5

4

3

2

http://www.msi.com.tw

Cover Sheet

Cover Sheet

Cover Sheet

MS-7307H1

MS-7307H1

MS-7307H1

1

Last Revision Date:

Last Revision Date:

Last Revision Date:

Tuesday, April 11, 2006

Tuesday, April 11, 2006

Tuesday, April 11, 2006

Sheet

Sheet

Sheet

Rev

Rev

Rev

0A

0A

0A

131

131

131

of

of

of

5

4

3

2

1

BLOCK DIAGRAM

D D

POWER

SUPPLY

CONNECTOR

PEX X16

VREG

PCI EXPRESS

SOCKET 940

K9

NFORCE

CRUSH 51

DDR SDRAM CONN 0

128-BIT 400/533/667/MHZ

DDR SDRAM CONN 1

HT 16X16 1GHZ

VGA CONN

468 BGA

C C

PRIMARY IDE

SECONDARY IDE

X4 - SATA CONN

B B

FLOPPY CONN

PS2/KBRD CONN

PARALLEL CONN

SERIAL CONN

SERIAL HDR

ATA 133

INTEGRATED SATA 1/2

SIO

LPC SUPER I/O
5127

LPC BUS 33MHZ

LPC HDR

4MB FLASH

NFORCE
MCP 51

508 BGA

HT 8X8 1GHZ

AZAILIA/AC97

X8 USB2

PCI 33MHZ

Realtek RTL8201CL

Realtek ALC 888 (Azalia, 5.1Channel)

BACK PANEL CONN

USB2 PORTS 0-1
DOUBLE STACK

USB2 PORTS 2-3
X2/GBIT LAN

FRONT PANEL HDR

USB2 PORTS 4-5

USB2 PORTS 6-7

NA

PCI SLOT 1

PCI SLOT 2

PCI SLOT 3

A A

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

5

4

3

2

http://www.msi.com.tw

Block Diagram

Block Diagram

Block Diagram

MS-7307H1

MS-7307H1

MS-7307H1

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

Tuesday, April 11, 2006

Tuesday, April 11, 2006

Tuesday, April 11, 2006

2

2

2

Rev

Rev

Rev

0A

0A

0A

31

31

31

of

of

of

5

4

3

2

1

HT_CLKIN_H18

HT_CLKIN_L18

HT_CLKIN_H08

HT_CLKIN_L08

R88 51R/4R88 51R/4
R89 51R/4R89 51R/4

HT_CTLIN_H08

HT_CTLIN_L08

HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8

HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0

HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]

C181

C181
C4.7U10Y0805

C4.7U10Y0805

5

C149

C149

C133

C133

C0.22U16X

C4.7U10Y0805

C4.7U10Y0805

C0.22U16X

N6

L0_CLKIN_H(1)

P6

L0_CLKIN_L(1)

N3

L0_CLKIN_H(0)

N2

L0_CLKIN_L(0)

V4

L0_CTLIN_H(1)

V5

L0_CTLIN_L(1)

U1

L0_CTLIN_H(0)

V1

L0_CTLIN_L(0)

U6

L0_CADIN_H(15)

V6

L0_CADIN_L(15)

T4

L0_CADIN_H(14)

T5

L0_CADIN_L(14)

R6

L0_CADIN_H(13)

T6

L0_CADIN_L(13)

P4

L0_CADIN_H(12)

P5

L0_CADIN_L(12)

M4

L0_CADIN_H(11)

M5

L0_CADIN_L(11)

L6

L0_CADIN_H(10)

M6

L0_CADIN_L(10)

K4

L0_CADIN_H(9)

K5

L0_CADIN_L(9)

J6

L0_CADIN_H(8)

K6

L0_CADIN_L(8)

U3

L0_CADIN_H(7)

U2

L0_CADIN_L(7)

R1

L0_CADIN_H(6)

T1

L0_CADIN_L(6)

R3

L0_CADIN_H(5)

R2

L0_CADIN_L(5)

N1

L0_CADIN_H(4)

P1

L0_CADIN_L(4)

L1

L0_CADIN_H(3)

M1

L0_CADIN_L(3)

L3

L0_CADIN_H(2)

L2

L0_CADIN_L(2)

J1

L0_CADIN_H(1)

K1

L0_CADIN_L(1)

J3

L0_CADIN_H(0)

J2

L0_CADIN_L(0)

SW1 X_SW-TACT4PSSW1 X_SW-TACT4PS

1
2

VCC_DDR

1
3
5
7

9
11
13
15
17
19
21
23

X_hdr_k8_hdt/B

X_hdr_k8_hdt/B

HYPERTRANSPORT

HYPERTRANSPORT

3
4

KEY

KEY

C194

C194
C0.22U16X

C0.22U16X

CPU1A

CPU1A

L0_CLKOUT_H(1)

L0_CLKOUT_L(1)

L0_CLKOUT_H(0)

L0_CLKOUT_L(0)

L0_CTLOUT_H(1)

L0_CTLOUT_L(1)

L0_CTLOUT_H(0)

L0_CTLOUT_L(0)

L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)

L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)

L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)

R16 X_100RR16 X_100R

J1

J1

C190

C190
C180P50N

C180P50N

LDT_RST_L

AD5
AD4
AD1
AC1

Y6
W6
W2
W3

Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4

Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1

2
4
6
8
10
12
14
16
18
20
22
24
26

C157

C157
C180P50N

C180P50N

HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8

HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0

LDT_RST_L

4

HT_CLKOUT_H1 8
HT_CLKOUT_L1 8
HT_CLKOUT_H0 8
HT_CLKOUT_L0 8

TP15TP15
TP14TP14

HT_CTLOUT_H0 8
HT_CTLOUT_L0 8

VCC_DDR

CPU_CLK#8

R48

R48
_15R1%0805-1

_15R1%0805-1

R47

R47
_15R1%0805-1

_15R1%0805-1

CPU_CLK8

VDDA_25

L1 80L3_40_0805L1 80L3_40_0805

VCC_DDR

R84

R84

39.2R1%

39.2R1%

R83

R83

39.2R1%

39.2R1%

CPU_M_VREF

C59

C59
C0.1U16X

C0.1U16X

2 1

C3900P50X

C3900P50X

C50

C50

C49C3900P50X C49C3900P50X

VCC_DDR

CPU_STRAP_HI_E11
CPU_STRAP_LO_F11

C55

C55
C1000P50X

C1000P50X

VDDA25

R52

R52

_169R1%-1

_169R1%-1

CPUCLKIN
CPUCLKIN#

C6

C6
X_C1000P50X

X_C1000P50X

R76 300R1%R76 300R1%
R82 X_300R1%R82 X_300R1%

CPU_M_VREF

TP10TP10

R31 300RR31 300R
R39 300RR39 300R

TP6TP6

THERMDC_CPU18
THERMDA_CPU18

3

VDDA25

C37

C37

C0.22U16X

C0.22U16X

C58

C58

C52

C52
C3300P50X

CPU_PWRGD_L
HT_STOP_L
LDT_RST_L

CPU_PRESENT_L

CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS

CPU_DBREQ_L

COREFB-22

CPU_VTT_SENSE

CPU_TEST25_H
CPU_TEST25_L

HT_STOP#8

C3300P50X

COREFB+
COREFB-

C10
D10

AL3

AL6

AK6

AL10
AJ10

AH10

AL9

E12

F12

AH11

AJ11

A10
B10
F10

AJ7

AH9

AJ5
AG9
AG8

AH7

AJ6

HT_STOP#

A8
B8

C9
D8
C7

A5
G2

G1

E9
F6
D6

E7
F8
C5

E5

C4.7U16Y1206

C4.7U16Y1206

COREFB+22

TP13TP13

TP2TP2
TP1TP1

TP7TP7
TP8TP8 TP18TP18

TP5TP5
TP17TP17

VRM_GD21,22

LDT_RST8

CPU_PWRGD8

LDT_RST LDT_RST_L

CPU_PWRGD CPU_PWRGD_L

CPU1D

CPU1D

MISC

MISC

VDDA1
VDDA2

CLKIN_H
CLKIN_L

PWROK
LDTSTOP_L
RESET_L

CPU_PRESENT_L

THERMTRIP_L

SIC
SID

TDI
TRST_L
TCK
TMS

DBREQ_L
VDD_FB_H

VDD_FB_L
VTT_SENSE

M_VREF
M_ZN
M_ZP

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9

TEST17
TEST16
TEST15
TEST14
TEST12

TEST7
TEST6
TEST5
TEST4
TEST3
TEST2

3VDUAL

147

U1AU1A

1 2

3VDUAL

147

U1DU1D

9 8

3VDUAL

3 4

3VDUAL

13 12

3VDUAL

147

U1CU1C

5 6

3VDUAL

147

U1EU1E

11 10

VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)

PROCHOT_L

TDO

DBRDY

VDDIO_FB_H

VDDIO_FB_L

PSI_L

HTREF1
HTREF0

TEST29_H

TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

HT Bus Level shift

147

U1BU1B

147

U1FU1F

2

D2
D1
C1
E3
E2
E1

AK7
AL7

AK10

CPU_DBRDY

B6
AK11

AL11

CPU_PSI_L

F1

V8
V7

C11
D11

AK8
AH8
AJ9
AL8
AJ8

J10
H9
AK9
AK5
G7
D4

HT_STOP_L

TP9TP9

VID4
VID3
VID2
VID1
VID0

CPU_THRIP_L

CPU_TDO

CPU_VDDIOFB_H
CPU_VDDIOFB_L

R81 300RR81 300R

VCC_DDR

R19

R19
300R

300R

VCC_DDR

C130

R78

R78
300R

300R

TP4TP4

TP3TP3

C130
C1000P50X

C1000P50X

R41

R41

80.6R1%

80.6R1%

CPU_PRESENT_L
CPU_TEST25_H

CPU_TEST25_L

TP12TP12

TP20TP20

TP19TP19TP11TP11

TP16TP16

VCC_DDR

VCC_DDR

R28

R28
330R

330R

B

CPU_THRIP_L CPU_THRIP#

VCC2_5

VCC_DDR

CE

Q2

Q2
N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

RN1

RN1

1
3
5
7

RN2

RN2

1
3
5
7

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

LDT_RST

2

CPU_PWRGD

4

CPU_THRIP#

6

HT_STOP#

8

8P4R-330R

8P4R-330R

HT_STOP_L

2

CPU_THRIP_L

4

CPU_PWRGD_L

6

LDT_RST_L

8

8P4R-330R

8P4R-330R

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

ATHLON64 HT I/F CTRL & DEBUG

ATHLON64 HT I/F CTRL & DEBUG

ATHLON64 HT I/F CTRL & DEBUG

VCC_DDR

C131

C131
C1000P50X

C1000P50X

R79 44.2R1%R79 44.2R1%
R80 44.2R1%R80 44.2R1%

R87 1KRR87 1KR
R49 510RR49 510R

R51 510RR51 510R

MS-7307H1

MS-7307H1

MS-7307H1

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

VID[0..4] 22

R77

R77
300R

300R

PROCHOT_L 18

VCC1_2HT

VCC_DDR

CPU_THRIP# 11

From C51D

CPU Side

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Wednesday, April 19, 2006

331

331

331

of

of

of

Rev

Rev

Rev

0A

0A

0A

HT_CADIN_H[15..0]8

HT_CADIN_L[15..0]8

HT_CADOUT_H[15..0]8

HT_CADOUT_L[15..0]8

D D

VCC1_2HT

C132

C132
C4.7U10Y0805

C4.7U10Y0805

VCC1_2HT

C C

B B

CPU_DBREQ_L
CPU_DBRDY
CPU_TCK
CPU_TMS

A A

CPU_TDI
CPU_TRST_L
CPU_TDO

5

4

3

2

1

MEM_MA_DQS_L[7..0]6

MEM_MA_DQS_H[7..0]6

MEM_MA_DM[7..0]6

MEM_MB_DQS_L[7..0]6

MEM_MB_DQS_H[7..0]6

MEM_MB_DM[7..0]6

D D

CPU1B

CPU1B

MEMORY INTERFACE A

MEM_MA0_CLK_H26,7
MEM_MA0_CLK_L26,7

MEM_MA0_CLK_H16,7
MEM_MA0_CLK_L16,7
MEM_MA0_CLK_H06,7
MEM_MA0_CLK_L06,7

MEM_MA0_CS_L16,7
MEM_MA0_CS_L06,7

MEM_MA0_ODT06,7

MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0

MEM_MA0_CS_L1
MEM_MA0_CS_L0

MEM_MA0_ODT0

AG21
AG20

G19
H19
U27
U26

AC25
AA24

AC28
AE20

AE19

G20
G21
V27
W27

AD27
AA25

AC27

C C

MEM_MA_CAS_L6,7
MEM_MA_WE_L6,7
MEM_MA_RAS_L6,7

MEM_MA_BANK26,7
MEM_MA_BANK16,7
MEM_MA_BANK06,7

MEM_MA_CKE06,7

MEM_MA_ADD[15..0]6,7

B B

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_CKE0

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0

AB25
AB27
AA26

N25
Y27

AA27

M25
M27

N24

AC26

N26
P25
Y25
N27
R24
P27
R25
R26
R27

U25
W24

AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28

D29
C29
C25
D25
E19

G15

AF15
AF19
AJ25
AH29

B29
E24
E18
H15

L27

T25
T27

F19
F15

MEMORY INTERFACE A

MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)

MA0_CS_L(1)
MA0_CS_L(0)

MA0_ODT(0)
MA1_CLK_H(2)

MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)

MA1_CS_L(1)
MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L
MA_WE_L
MA_RAS_L

MA_BANK(2)
MA_BANK(1)
MA_BANK(0)

MA_CKE(1)
MA_CKE(0)

MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)

MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)

MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)

MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)

MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)

MA_DQS_H(8)

MA_DQS_L(8)

MA_DM(8)

MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)

AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26

MEM_MA_DATA18

C26

MEM_MA_DATA17

G23

MEM_MA_DATA16

F23

MEM_MA_DATA15

E22

MEM_MA_DATA14

E21

MEM_MA_DATA13

F17

MEM_MA_DATA12

G17

MEM_MA_DATA11

G22

MEM_MA_DATA10

F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14

J28
J27

J25
K25

J26
G28
G27
L24
K27
H29
H27

MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19

MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0

MEM_MA_DATA[63..0] 6

MEM_MB0_CLK_H26,7
MEM_MB0_CLK_L26,7
MEM_MB0_CLK_H16,7
MEM_MB0_CLK_L16,7

MEM_MB0_CLK_H06,7
MEM_MB0_CLK_L06,7

MEM_MB0_CS_L16,7

MEM_MB0_CS_L06,7

MEM_MB0_ODT06,7

MEM_MB_CAS_L6,7
MEM_MB_WE_L6,7
MEM_MB_RAS_L6,7

MEM_MB_BANK26,7
MEM_MB_BANK16,7
MEM_MB_BANK06,7

MEM_MB_CKE06,7

MEM_MB_ADD[15..0]6,7

MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0

MEM_MB0_CS_L1
MEM_MB0_CS_L0

MEM_MB0_ODT0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_CKE0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0

AJ19
AK19

AE30

AC31
AD29

AL19
AL18

W29
W28

AE29
AB31

AD31

AC29
AC30
AB29

AA31
AA28

M31
M29

AE31

AA29

AA30
AK13

AJ13

AK17

AJ17

AK23

AL23
AL28
AL29

AJ14

AH17

AJ23

AK29

A18
A19
U31
U30

C19
D19

N31

N28
N29

N30
P29

P31
R29
R28
R31
R30
T31
T29
U29
U28

D31
C31
C24
C23
D17
C17
C14
C13

C30
A23
B17
B13

MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)

MB0_CS_L(1)
MB0_CS_L(0)

MB0_ODT(0)
MB1_CLK_H(2)

MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)

MB1_CS_L(1)
MB1_CS_L(0)

MB1_ODT(0)

MB_CAS_L
MB_WE_L
MB_RAS_L

MB_BANK(2)
MB_BANK(1)
MB_BANK(0)

MB_CKE(1)
MB_CKE(0)

MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)

MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)

MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)

CPU1C

CPU1C

MEMORY INTERFACE B

MEMORY INTERFACE B

MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)

MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)

MB_DQS_H(8)

MB_DQS_L(8)

MB_DM(8)

MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)

AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13

J31
J30

J29
K29

K31
G30
G29
L29
L28
H31
G31

MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20

MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10

MEM_MB_DATA9

MEM_MB_DATA8

MEM_MB_DATA7

MEM_MB_DATA6

MEM_MB_DATA5

MEM_MB_DATA4

MEM_MB_DATA3

MEM_MB_DATA2

MEM_MB_DATA1

MEM_MB_DATA0

MEM_MB_DATA[63..0] 6

A A

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

ATHLON64 DDR MEMORY I/F

ATHLON64 DDR MEMORY I/F

ATHLON64 DDR MEMORY I/F

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

5

4

3

2

http://www.msi.com.tw

MS-7307H1

MS-7307H1

MS-7307H1

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Wednesday, April 19, 2006

431

431

431

Rev

Rev

Rev

0A

0A

0A

of

of

of

5

4

3

2

1

VCCP

CPU1F

CPU1F

VDD1

VDD1

A4

VDD1

A6

VDD2

AA8

VDD3

D D

C C

B B

AA10
AA12
AA14
AA16
AA18

AB11

AC10

AE10

AB7
AB9

AC4
AC5
AC8

AD2
AD3
AD7
AD9

AF7
AF9
AG4
AG5
AG7
AH2
AH3

E10

F11

G10
G12

H11
H23

K11
K13
K15
K17
K19
K21
K23

Y17
Y19

VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27

B3

VDD28

B5

VDD29

B7

VDD30

C2

VDD31

C4

VDD32

C6

VDD33

C8

VDD34

D3

VDD35

D5

VDD36

D7

VDD37

D9

VDD38

E4

VDD39

E6

VDD40

E8

VDD41
VDD42

F5

VDD43

F7

VDD44

F9

VDD45
VDD46

G6

VDD47

G8

VDD48
VDD49
VDD50

H7

VDD51
VDD52
VDD53

J8

VDD54

J12

VDD55

J14

VDD56

J16

VDD57

J18

VDD58

J20

VDD59

J22

VDD60

J24

VDD61

K7

VDD62

K9

VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70

L4

VDD71

L5

VDD72

L8

VDD73

L10

VDD74

L12

VDD75
VDD150
VDD151

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

VSS240
VSS241

A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16

VCCP

M11
M13
M15
M17
M19

N10
N12
N14
N16
N18

P11
P13
P15
P17
P19

R10
R12
R14
R16
R18
R20

U10
U12
U14
U16
U18
U20

V11
V13
V15
V17
V19
V21

W10
W12
W14
W16
W18
W20

Y11
Y13
Y15
Y21

CPU1G

CPU1G

VDD2

L14
L16
L18

T11
T13
T15
T17
T19
T21

VDD2

VDD1
VDD2
VDD3

M2

VDD4

M3

VDD5

M7

VDD6

M9

VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

N8

VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

P7

VDD19

P9

VDD20
VDD21
VDD22
VDD23
VDD24
VDD25

R4

VDD26

R5

VDD27

R8

VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34

T2

VDD35

T3

VDD36

T7

VDD37

T9

VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44

U8

VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51

V9

VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58

W4

VDD59

W5

VDD60

W8

VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67

Y2

VDD68

Y3

VDD69

Y7

VDD70

Y9

VDD71
VDD72
VDD73
VDD74
VDD75

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75

AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18

VCCP

AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11

M21
M23
N20
N22

R22
U22
W22

CPU1H

CPU1H

VDD3

VDD3

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

L20

VDD19

L22

VDD20
VDD21
VDD22
VDD23
VDD24

P21

VDD25

P23

VDD26
VDD27

T23

VDD28
VDD29

V23

VDD30
VDD31

Y23

VDD32

5

GND

6

GND

7

GND

8

GND

1

GND

2

GND

3

GND

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22

VTT_DDR

VCC_DDR

VCCP

C476

C476
C0.22U16X/B

C0.22U16X/B

VCCP

C469

C469

X_C22U6.3X1206/B

X_C22U6.3X1206/B

VCC1_2HT

AJ4
AJ3
AJ2
AJ1

D12
C12
B12
A12

AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30

M24
M26
M28
M30
P24
P26
P28
P30

T24
T26
T28

T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29

C485

C485
C0.22U16X/B

C0.22U16X/B

C468

C468

X_C22U6.3X1206/B

X_C22U6.3X1206/B

VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4

VTT1
VTT2
VTT3
VTT4

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29

C481

C481
C0.22U16X/B

C0.22U16X/B

C472

C472

C22U6.3X1206/B

C22U6.3X1206/B

CPU1I

CPU1I

VDDIO

VDDIO

VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4

VTT5
VTT6
VTT7
VTT8
VTT9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28

C457

C457
C0.01U50X/B

C0.01U50X/B

VLDT_RUN_B

H6
H5
H2

VTT_DDR

H1
AK12

AJ12
AH12
AG12
AL12

K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15

C464

C464

C180P50N/4/B

C180P50N/4/B

C462

C462

X_C22U6.3X1206/B

X_C22U6.3X1206/B

C22U6.3X1206/B

C22U6.3X1206/B

C470

C470

C465

C465

C22U6.3X1206/B

C22U6.3X1206/B

C70

C70
C4.7U16Y1206

C4.7U16Y1206

C22U6.3X1206

C22U6.3X1206

C463

C463

C22U6.3X1206/B

C22U6.3X1206/B

C467

C467

C473

C473

X_C22U6.3X1206/B

X_C22U6.3X1206/B

C480

C480

C22U6.3X1206/B

C22U6.3X1206/B

C458

C458

C22U6.3X1206

C22U6.3X1206

C460

C460

C22U6.3X1206/B

C22U6.3X1206/B

C475

C475

X_C22U6.3X1206/B

X_C22U6.3X1206/B

C459

C459

X_C22U6.3X1206/B

X_C22U6.3X1206/B

C22U6.3X1206

C22U6.3X1206

C479

C479

VTT_DDR

C15

C14

C14

C53

C11

C11
C0.22U16X

C0.22U16X

A A

VTT_DDR

C158

C158
C0.22U16X

C0.22U16X

C53
C0.22U16X

C0.22U16X

C161

C161
C0.22U16X

C0.22U16X

5

C4.7U10Y0805

C4.7U10Y0805

C167

C167
C4.7U10Y0805

C4.7U10Y0805

C15
C4.7U10Y0805

C4.7U10Y0805

C169

C169
C4.7U10Y0805

C4.7U10Y0805

C44

C44
C10P16N

C10P16N

C164

C164
C10P16N

C10P16N

C16

C16
C10P16N

C10P16N

C135

C135
C10P16N

C10P16N

C60

C60
C1000P50X

C1000P50X

C128

C128
C1000P50X

C1000P50X

C47

C47
C1000P50X

C1000P50X

C152

C152
C1000P50X

C1000P50X

VCC_DDR VCC_DDR

C471

C471

C76

C0.22U16X/B

C0.22U16X/B

C76
C0.22U16X

C0.22U16X

C207

C207
C4.7U10Y0805

C4.7U10Y0805

C80

C80
C4.7U10Y0805

C4.7U10Y0805

3

C461

C461
C0.22U16X/B

C0.22U16X/B

4

C474

C474

X_C22U6.3X1206/B

X_C22U6.3X1206/B

C477

C477

C22U6.3X1206/B

C22U6.3X1206/B

C156

C156

C4.7U10Y0805

C4.7U10Y0805

C176

C176

C4.7U10Y0805

C4.7U10Y0805

2

C466

C466
C0.22U16X/B

C0.22U16X/B

C155

C155
C0.22U16X

C0.22U16X

C484

C484

C75

C75

C0.01U50X/B

C0.01U50X/B

C0.22U16X

C0.22U16X

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

ATHLON64 PWR & GND

ATHLON64 PWR & GND

ATHLON64 PWR & GND

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

C146

C146
C180P50N

C180P50N

MS-7307H1

MS-7307H1

MS-7307H1

1

Last Revision Date:

Last Revision Date:

Last Revision Date:

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Sheet

Sheet

Sheet

531

531

531

Rev

Rev

Rev

0A

0A

0A

of

of

of

5

MEM_MA_DQS_H[7..0]4
MEM_MA_DQS_L[7..0]4

69

VDD6

64

VDD753VDD859VDD9

170

VDD1067VDD11

VDDQ1

172

178

184

187

189

197

VDD1

VDD2

VDD3

VDD4

164

D D

C C

MEM_MA_ADD[15..0]4,7

B B

MEM_MA_DM[7..0]4

SMB_MEM_CLK12

SMB_MEM_DATA12
MEM_MA_BANK24,7
MEM_MA_BANK14,7
MEM_MA_BANK04,7

MEM_MA0_CLK_H04,7
MEM_MA0_CLK_L04,7
MEM_MA0_CLK_H14,7
MEM_MA0_CLK_L14,7
MEM_MA0_CLK_H24,7
MEM_MA0_CLK_L24,7

MEM_MA_CKE04,7
MEM_MA_RAS_L4,7

MEM_MA_CAS_L4,7
MEM_MA0_CS_L04,7

MEM_MA0_CS_L14,7

MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

R154 33RR154 33R
R151 33RR151 33R

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2

MEM_MA_CKE0

MEM_MA_RAS_L
MEM_MA_CAS_L

MEM_MA0_CS_L0
MEM_MA0_CS_L1

MEM_MA_DM7

MEM_MA_DM6

MEM_MA_DM5

MEM_MA_DM4

MEM_MA_DM3

MEM_MA_DM2

MEM_MA_DM1

MEM_MA_DM0

SMB_MEMCLK
SMB_MEMDATA

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

VDD5

4

VCC3VCC_DDR

175

181

191

194

72

78

238

DIMM1DIMM1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ651VDDQ756VDDQ862VDDQ9

VDDQ1075VDDQ11

VDDSPD

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

WE_L
VREF
TEST
ODT0

ODT1

ERR_OUT_L

PAR_IN

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

NC1

236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22

MEM_MA_DATA10

21
13
12
129
128
123
122
10
9
4
3

73
1
102
195

77
55

68
19

MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA18
MEM_MA_DATA17
MEM_MA_DATA16
MEM_MA_DATA15
MEM_MA_DATA14
MEM_MA_DATA13
MEM_MA_DATA12
MEM_MA_DATA11

MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0

MEM_MA_WE_L

VDDR_VREF

MEM_MA0_ODT0

MEM_MA_DATA[63..0] 4

MEM_MA_WE_L 4,7

MEM_MA0_ODT0 4,7

VDDR_VREF

C45

C45
C0.1U25Y

C0.1U25Y

3

MEM_MB_DQS_H[7..0]4
MEM_MB_DQS_L[7..0]4

164

MEM_MB_DM[7..0]4

VCC3

MEM_MB_BANK24,7
MEM_MB_BANK14,7
MEM_MB_BANK04,7

MEM_MB_ADD[15..0]4,7

MEM_MB0_CLK_H04,7
MEM_MB0_CLK_L04,7
MEM_MB0_CLK_H14,7
MEM_MB0_CLK_L14,7
MEM_MB0_CLK_H24,7
MEM_MB0_CLK_L24,7

MEM_MB_CKE04,7
MEM_MB_RAS_L4,7

MEM_MB_CAS_L4,7
MEM_MB0_CS_L04,7

MEM_MB0_CS_L14,7

MEM_MB_DM7

MEM_MB_DM6

MEM_MB_DM5

MEM_MB_DM4

MEM_MB_DM3

MEM_MB_DM2

MEM_MB_DM1

MEM_MB_DM0

MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

SMB_MEMCLK
SMB_MEMDATA
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2

MEM_MB_CKE0

MEM_MB_RAS_L
MEM_MB_CAS_L

MEM_MB0_CS_L0
MEM_MB0_CS_L1

165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126

46

45
114
113
105
104

93

92

84

83

37

36

28

27

16

15

101
240
239
120
119

54
190

71
173

174
196
176

57

70
177
179

58
180

60

61
182

63
183
188

168
167
162
161

49

48

43

42
185

186
137
138
220
221

18

52
171
192

74
193

76

7
6

VCC_DDR

DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L

SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0

CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L

RESET_L
CKE0

CKE1
RAS_L
CAS_L

S0_L
S1_L

2

1

VCC3

69

170

175

181

191

194

72

78

VDDQ651VDDQ756VDDQ862VDDQ9

VDDQ1075VDDQ11

238

VDDSPD

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

WE_L

VREF
TEST
ODT0

ODT1

ERR_OUT_L

PAR_IN

NC1

DIMM2DIMM2

236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3

73
1
102
195

77
55

68
19

MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0

MEM_MB_WE_L

VDDR_VREF

MEM_MB0_ODT0

MEM_MB_DATA[63..0] 4

MEM_MB_WE_L 4,7

VDDR_VREF

C54

C54
C0.1U25Y

C0.1U25Y

MEM_MB0_ODT0 4,7

172

178

184

187

189

197

64

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD753VDD859VDD9

VDD1067VDD11

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VCC_DDR

DIMM 1 DIMM 2

A A

5

ADDR=1010000B

4

R53

R53

56.2R1%

56.2R1%

R50

R50

56.2R1%

56.2R1%

C62

C62
C0.1U16X

C0.1U16X

VDDR_VREF

VDDR_VREF

C36

C36
C0.1U16X

C0.1U16X

3

C48

C48
C1000P50X

C1000P50X

2

ADDR=1010001B

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

FIRST LOGICAL DDR DIMM

FIRST LOGICAL DDR DIMM

FIRST LOGICAL DDR DIMM

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

MS-7307H1

MS-7307H1

MS-7307H1

Last Revision Date:

Last Revision Date:

Last Revision Date:
Sheet

Sheet

Sheet

1

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Wednesday, April 19, 2006

631

631

631

of

of

of

Rev

Rev

Rev

0A

0A

0A

5

4

3

2

1

MEM_MA_ADD[15..0]4,6

C171

C171

C0.1U16X

C0.1U16X

VCC_DDR

C103

C103

C0.1U16X

C0.1U16X

C117

C117

C0.1U16X

C0.1U16X

C109

C109

C0.1U16X

C0.1U16X

MEM_MA_ADD15

VTT_DDR

MEM_MA_BANK2

RN9 8P4R-47R0402RN9 8P4R-47R0402

1

MEM_MA_BANK24,6
MEM_MB_BANK24,6

D D

MEM_MA_BANK04,6
MEM_MA_RAS_L4,6
MEM_MB0_CS_L04,6
MEM_MA0_CS_L04,6

MEM_MB_BANK04,6
MEM_MB_RAS_L4,6
MEM_MA_BANK14,6

MEM_MB0_CS_L14,6

C C

MEM_MB_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MA_ADD12

RN10 8P4R-47R0402RN10 8P4R-47R0402

MEM_MA_ADD9
MEM_MB_ADD11
MEM_MB_ADD7
MEM_MB_ADD6

RN12 8P4R-47R0402RN12 8P4R-47R0402

MEM_MA_ADD6
MEM_MA_ADD5
MEM_MB_ADD5
MEM_MA_ADD1

RN15 8P4R-47R0402RN15 8P4R-47R0402

MEM_MA_ADD2
MEM_MB_ADD1
MEM_MB_ADD2

MEM_MA_BANK0

RN18 8P4R-47R0402RN18 8P4R-47R0402

MEM_MA_RAS_L
MEM_MB0_CS_L0
MEM_MA0_CS_L0

MEM_MB_BANK0

RN17 8P4R-47R0402RN17 8P4R-47R0402

MEM_MB_RAS_L
MEM_MA_BANK1
MEM_MA_ADD10

MEM_MB_ADD13
MEM_MB0_CS_L1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

R92 47R0402R92 47R0402
R94 47R0402R94 47R0402

MEM_MA0_CLK_H24,6

MEM_MA0_CLK_L24,6

MEM_MA0_CLK_H14,6

MEM_MA0_CLK_L14,6

MEM_MA0_CLK_H04,6

MEM_MA0_CLK_L04,6

MEM_MB0_CLK_H24,6

MEM_MB0_CLK_L24,6

MEM_MB0_CLK_H14,6

MEM_MB0_CLK_L14,6

MEM_MB0_CLK_H04,6

MEM_MB0_CLK_L04,6

MEM_MA0_CLK_H2

MEM_MA0_CLK_L2

MEM_MA0_CLK_H1

MEM_MA0_CLK_L1

MEM_MA0_CLK_H0

MEM_MA0_CLK_L0

MEM_MB0_CLK_H2

MEM_MB0_CLK_L2

MEM_MB0_CLK_H1

MEM_MB0_CLK_L1

MEM_MB0_CLK_H0

MEM_MB0_CLK_L0

C151

C151
C1.5P50N0402

C1.5P50N0402

C56

C56
C1.5P50N0402

C1.5P50N0402

C101

C101

C1.5P50N0402

C1.5P50N0402

C142

C142
C1.5P50N0402

C1.5P50N0402

C51

C51
C1.5P50N0402

C1.5P50N0402

C95

C95
C1.5P50N0402

C1.5P50N0402

C166

C166

C0.1U16X

C0.1U16X

VTT_DDR

C0.1U16X

C0.1U16X

MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

C94

C94

C145

C145

C0.1U16X

C0.1U16X

C482 C22P50N0402C482 C22P50N0402
C478 C22P50N0402C478 C22P50N0402
C504 C22P50N0402C504 C22P50N0402
C483 C22P50N0402C483 C22P50N0402 C96 C22P50N0402/BC96 C22P50N0402/B
C487 C22P50N0402C487 C22P50N0402
C500 C22P50N0402C500 C22P50N0402
C488 C22P50N0402C488 C22P50N0402
C489 C22P50N0402C489 C22P50N0402
C490 C22P50N0402C490 C22P50N0402
C492 C22P50N0402C492 C22P50N0402
C491 C22P50N0402C491 C22P50N0402
C494 C22P50N0402C494 C22P50N0402
C493 C22P50N0402C493 C22P50N0402
C495 C22P50N0402C495 C22P50N0402
C496 C22P50N0402C496 C22P50N0402
C498 C22P50N0402C498 C22P50N0402

C502 C22P50N0402C502 C22P50N0402
C503 C22P50N0402C503 C22P50N0402
C501 C22P50N0402C501 C22P50N0402

C486 C22P50N0402C486 C22P50N0402
C497 C22P50N0402C497 C22P50N0402
C499 C22P50N0402C499 C22P50N0402

Decoupling Between Processor and DIMMs

C136

C136

C153

C0.1U16X

C0.1U16X

C153

C0.1U16X

C0.1U16X

VCC_DDR

Layout: Spread out on VTT pour

C97

C97

C159

C159

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

C127

C127

C121

C121

C0.1U16X

C0.1U16X

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

C125

C125

C0.1U16X

C0.1U16X

C93 C22P50N0402/BC93 C22P50N0402/B
C89 C22P50N0402/BC89 C22P50N0402/B
C154 C22P50N0402/BC154 C22P50N0402/B

C102 C22P50N0402/BC102 C22P50N0402/B
C138 C22P50N0402/BC138 C22P50N0402/B
C105 C22P50N0402/BC105 C22P50N0402/B
C108 C22P50N0402/BC108 C22P50N0402/B
C111 C22P50N0402/BC111 C22P50N0402/B
C115 C22P50N0402/BC115 C22P50N0402/B
C112 C22P50N0402/BC112 C22P50N0402/B
C118 C22P50N0402/BC118 C22P50N0402/B
C116 C22P50N0402/BC116 C22P50N0402/B
C120 C22P50N0402/BC120 C22P50N0402/B
C123 C22P50N0402/BC123 C22P50N0402/B
C129 C22P50N0402/BC129 C22P50N0402/B

C144 C22P50N0402/BC144 C22P50N0402/B
C147 C22P50N0402/BC147 C22P50N0402/B
C140 C22P50N0402/BC140 C22P50N0402/B

C98 C22P50N0402/BC98 C22P50N0402/B
C126 C22P50N0402/BC126 C22P50N0402/B
C134 C22P50N0402/BC134 C22P50N0402/B

C173

C173

C139

C139

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

VCC_DDR

MEM_MB_ADD[15..0]4,6

RN8 8P4R-47R0402RN8 8P4R-47R0402

MEM_MA_CKE04,6

B B

MEM_MB_BANK14,6

MEM_MA_WE_L4,6
MEM_MA_CAS_L4,6
MEM_MB_WE_L4,6
MEM_MA0_ODT04,6

MEM_MB_CKE04,6

MEM_MB_CAS_L4,6
MEM_MA0_CS_L14,6

MEM_MB0_ODT04,6

A A

5

MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MB_ADD8
MEM_MA_ADD11
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD4
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MA_ADD3
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MA_ADD0
MEM_MB_ADD10

MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MB_WE_L
MEM_MA0_ODT0

MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14

MEM_MB_CAS_L
MEM_MA_ADD13
MEM_MA0_CS_L1
MEM_MB0_ODT0

1
3
5
7

RN11 8P4R-47R0402RN11 8P4R-47R0402

1
3
5
7

RN14 8P4R-47R0402RN14 8P4R-47R0402

1
3
5
7

RN16 8P4R-47R0402RN16 8P4R-47R0402

1
3
5
7

RN19 8P4R-47R0402RN19 8P4R-47R0402

1
3
5
7

RN7 8P4R-47R0402RN7 8P4R-47R0402

1
3
5
7

RN20 8P4R-47R0402RN20 8P4R-47R0402

1
3
5
7

VTT_DDR

2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

4

3

VTT_DDR

C174

C174

C0.1U16X

C0.1U16X

C90

C90

C0.1U16X

C0.1U16X

C20

C20

C0.1U16X

C0.1U16X

C78

C78

C0.1U16X

C0.1U16X

C21

C21

C0.1U16X

C0.1U16X

C74

C74

C0.1U16X

C0.1U16X

C124

C124

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

2

C83

C83

C113

C113

C0.1U16X

C0.1U16X

C143

C143

C0.1U16X

C0.1U16X

C162

C162

C107

C107

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

DDR Terminatior

DDR Terminatior

DDR Terminatior

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

http://www.msi.com.tw

C168

C168

C81

C81

C0.1U16X

C0.1U16X

MS-7307H1

MS-7307H1

MS-7307H1

C119

C119

C0.1U16X

C0.1U16X

C0.1U16X

C0.1U16X

Last Revision Date:

Last Revision Date:

Last Revision Date:

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Sheet

Sheet

Sheet

1

C22

C22

Rev

Rev

Rev

0A

0A

0A

731

731

731

of

of

of

5

D D

U8F

W24

W21

M17

W23

W20
W22

M23
M22

W19

Y23
V24

U22
R24
P24
P22
N22
Y21
V21

T21
R18
P16
N20

Y22
V23

U21
R23
P23
P21
N21
Y20

U20
R19
P17
N19
N18

T23
T22
R21
R20

Y19

N16

T13

U8F

HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P

HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N

HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N

HT_CPU_RXCTL_P
HT_CPU_RXCTL_N

HT_CPU_CAL_1P2V
HT_CPU_CAL_GND

+1.2V_PLLHTCPU

+1.2V_PLLHTMCP

1P2VPLL_PWR

HT_CADOUT_H[15..0]

HT_CADOUT_L[15..0]

HT_CLKOUT_H03

HT_CLKOUT_L03

HT_CLKOUT_H13

HT_CLKOUT_L13

HT_CTLOUT_H03
HT_CTLOUT_L03

VCC1_2HT

150R1%

150R1%

R102

R102

FB16 30L500m_200/BFB16 30L500m_200/B

HT_CADOUT_H0
HT_CADOUT_H1
HT_CADOUT_H2
HT_CADOUT_H3
HT_CADOUT_H4
HT_CADOUT_H5
HT_CADOUT_H6
HT_CADOUT_H7
HT_CADOUT_H8
HT_CADOUT_H9
HT_CADOUT_H10
HT_CADOUT_H11
HT_CADOUT_H12
HT_CADOUT_H13
HT_CADOUT_H14
HT_CADOUT_H15

HT_CADOUT_L0
HT_CADOUT_L1
HT_CADOUT_L2
HT_CADOUT_L3
HT_CADOUT_L4
HT_CADOUT_L5
HT_CADOUT_L6
HT_CADOUT_L7
HT_CADOUT_L8
HT_CADOUT_L9
HT_CADOUT_L10
HT_CADOUT_L11
HT_CADOUT_L12
HT_CADOUT_L13
HT_CADOUT_L14
HT_CADOUT_L15

HT_CTLOUT_H0
HT_CTLOUT_L0

R105 150R1%R105 150R1%

C513

C513

C1U10Y/B

C1U10Y/B

1P2VPLL_FILT

C511

C511

C0.1U25Y/B

C0.1U25Y/B

HT_CADOUT_H[15..0]3

HT_CADOUT_L[15..0]3

C C

B B

1P2VPLL_PWR9,10

C51

C51

SEC 1 OF 6

SEC 1 OF 6

4

HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P

HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P

HT_CPU_TXD0_N

HT_CPU_TXD1_N

HT_CPU_TXD2_N

HT_CPU_TXD3_N

HT_CPU_TXD4_N

HT_CPU_TXD5_N

HT_CPU_TXD6_N

HT_CPU_TXD7_N

HT_CPU_TXD8_N

HT_CPU_TXD9_N

HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N

HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N

HT_CPU_TXCTL_P
HT_CPU_TXCTL_N

CLKOUT_PRI_200MHZ_P

CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N

HT_CPU_REQ*

HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD

+2.5V_PLLHTCPU

C23
D23
E22
F23
H22
J21
K21
K23
D21
F19
F21
G20
J19
L17
L20
L18

C24
D24
E23
F24
H23
J22
K22
K24
D22
E20
E21
G19
J18
K17
K19
L19

G23
G24
G22
G21

L23
L24

B24
B23
A22
B21

F18
G18
D20
E19

L16

HT_CADIN_H0
HT_CADIN_H1
HT_CADIN_H2
HT_CADIN_H3
HT_CADIN_H4
HT_CADIN_H5
HT_CADIN_H6
HT_CADIN_H7
HT_CADIN_H8
HT_CADIN_H9
HT_CADIN_H10
HT_CADIN_H11
HT_CADIN_H12
HT_CADIN_H13
HT_CADIN_H14
HT_CADIN_H15

HT_CADIN_L0
HT_CADIN_L1
HT_CADIN_L2
HT_CADIN_L3
HT_CADIN_L4
HT_CADIN_L5
HT_CADIN_L6
HT_CADIN_L7
HT_CADIN_L8
HT_CADIN_L9
HT_CADIN_L10
HT_CADIN_L11
HT_CADIN_L12
HT_CADIN_L13
HT_CADIN_L14
HT_CADIN_L15

HT_CLKIN_H0
HT_CLKIN_L0
HT_CLKIN_H1
HT_CLKIN_L1

HT_CTLIN_H0
HT_CTLIN_L0

2P5V_PLL

HT_CADIN_H[15..0]

HT_CADIN_L[15..0]

HT_CLKIN_H0 3
HT_CLKIN_L0 3
HT_CLKIN_H1 3
HT_CLKIN_L1 3

HT_CTLIN_H0 3
HT_CTLIN_L0 3

CPU_CLK 3
CPU_CLK# 3

HT_STOP#
LDT_RST
CPU_PWRGD

3

HT_CADIN_H[15..0] 3

HT_CADIN_L[15..0] 3

HT_STOP# 3

LDT_RST 3
CPU_PWRGD 3

2

U8A

HTMCP_UP[7..0]11

HTMCP_UP#[7..0]11

HTMCP_UP[7..0]

HTMCP_UP#[7..0]

HTMCP_UPCLK011

HTMCP_UPCLK0#11

HTMCP_UPCNTL11

HTMCP_UPCNTL#11

HTMCP_REQ#11

HTMCP_STOP#11

HTMCP_RST#11

HTMCP_PWRGD11

MCPOUT_25MHZ11

MCPOUT_200MHZ11

MCPOUT_200MHZ#11

HTMCP_UP0
HTMCP_UP1
HTMCP_UP2
HTMCP_UP3
HTMCP_UP4
HTMCP_UP5
HTMCP_UP6
HTMCP_UP7

HTMCP_UP#0
HTMCP_UP#1
HTMCP_UP#2
HTMCP_UP#3
HTMCP_UP#4
HTMCP_UP#5
HTMCP_UP#6
HTMCP_UP#7

HTMCP_UPCLK0
HTMCP_UPCLK0#

HTMCP_UPCNTL
HTMCP_UPCNTL#

HTMCP_REQ#
HTMCP_STOP#
HTMCP_RST#
HTMCP_PWRGD

MCPOUT_25MHZ

MCPOUT_200MHZ
MCPOUT_200MHZ#

AD6
AC7
AA8

AA9
AD10
AD11
AC12
AC13

AA6

AA11

W12

AC6

AB7

AB8

AB9
AC10
AC11
AB12
AB13

AA7

W10

W11

AD9

AC9

U10

AD14
AC14

AB5

AA5

AC5

AD5

AC4

W7

Y8
V9

Y10
V11

Y6
Y7

W9
Y12
V13

T10

Y5

W5

HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P

HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N

HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N

HT_MCP_RXCTL_P
HT_MCP_RXCTL_N

HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD

CLKIN_25MHZ

CLKIN_200MHZ_P
CLKIN_200MHZ_N

U8A

C51

C51

SEC 2 OF 6

SEC 2 OF 6

SCLKIN_MCLKOUT_200MHZ_P
SCLKIN_MCLKOUT_200MHZ_N

HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P

HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P

HT_MCP_TXD0_N

HT_MCP_TXD1_N

HT_MCP_TXD2_N

HT_MCP_TXD3_N

HT_MCP_TXD4_N

HT_MCP_TXD5_N

HT_MCP_TXD6_N

HT_MCP_TXD7_N

HT_MCP_TXD8_N

HT_MCP_TXD9_N

HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N

HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N

HT_MCP_TXCTL_P
HT_MCP_TXCTL_N

CLKOUT_CTERM

HT_MCP_CAL_1P2V
HT_MCP_CAL_GND

AC24
AD23
AC22
AC20
AB18
AA17
AB16
AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13

AC23
AD22
AC21
AD20
AC18
AB17
AB15
AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13

AC19
AD19
Y17
W17

AC15
AD15

B22
A20

B20

AB23
AB24

HTMCP_DWN0
HTMCP_DWN1
HTMCP_DWN2
HTMCP_DWN3
HTMCP_DWN4
HTMCP_DWN5
HTMCP_DWN6
HTMCP_DWN7

HTMCP_DWN#0
HTMCP_DWN#1
HTMCP_DWN#2
HTMCP_DWN#3
HTMCP_DWN#4
HTMCP_DWN#5
HTMCP_DWN#6
HTMCP_DWN#7

1

HTMCP_DWN[7..0]

HTMCP_DWN#[7..0]

HTMCP_DWNCLK0
HTMCP_DWNCLK0#

HTMCP_DWNCNTL
HTMCP_DWNCNTL#

R112 2.37K/1R112 2.37K/1

2.37K Ohm

R103 150R1%R103 150R1%

R104 150R1%R104 150R1%

HTMCP_DWNCLK0 11
HTMCP_DWNCLK0# 11

HTMCP_DWNCNTL 11
HTMCP_DWNCNTL# 11

VCC1_2

HTMCP_DWN[7..0] 11

HTMCP_DWN#[7..0] 11

PLACE ON BACK SIDE

VCC2_5

C201

C201

C508

C4.7U10Y0805

A A

5

C4.7U10Y0805

C508

C0.1U25Y/B

C0.1U25Y/B

FB17 30L500m_200/BFB17 30L500m_200/B

C510

C510

C1U10Y/B

C1U10Y/B

PLACE ON BACK SIDE

4

C512

C512

C0.1U25Y/B

C0.1U25Y/B

2P5V_PLL 9

Micro Star Restricted Secret

Micro Star Restricted Secret

Micro Star Restricted Secret

Title

Title

Title

Document Number

Document Number

Document Number

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

Taipei Hsien, Taiwan

Taipei Hsien, Taiwan
http://www.msi.com.tw

http://www.msi.com.tw

3

2

http://www.msi.com.tw

C51PV-1/ HT CPU & MCP

C51PV-1/ HT CPU & MCP

C51PV-1/ HT CPU & MCP

MS-7307H1

MS-7307H1

MS-7307H1

Last Revision Date:

Last Revision Date:

Last Revision Date:

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Wednesday, April 19, 2006

Sheet

Sheet

Sheet

831

831

1

831

Rev

Rev

Rev

0A

0A

0A

of

of

of