MSI MS-7303 Schematics

5

4

3

2

1

MSI

MS-7303 Ver: 1 . 1

D D

CPU:

AMD M2 Athlon 64/Athlon 64 FX

Title Page

Cover Sheet 1
Block Diagram

2
3GPIO SPEC
4,5,6AMD M2 940

System Chipset:

NVIDIA C51PVG
NVIDIA MCP 51G / MCP 51

On Board Chipset:

LPC Super I/O -- F71882
LAN -- RTL8201CL(default) Dual-lay RTL8211BL
Audio Codec --ALC861(default) / ALC883
BIOS -DUAL SPI FLASH ROM 4M (default is single BIOS)
1394 Controller-VT6308(default) co-lay VT6307

System Memory

/ DDR Terminations
C51PVG 9,10,11
MCP51G 12,13,14,15
PCI Slot 1&2
PCI-Express X 16 & X1 PORT
LAN - RTL8201CL
Audio - ALC861

1394 Controller-VT6308

C C

B B

Main Memory:

DDR II * 2 (Max 2GB)

Expansion Slots:

PCI-E X 16 *1
PCI-E X 1 *1
PCI Slot X 2

PWM:

Controller--Intersil ISL6566CRZ 3 Phase

ACPI:

WINBOND / MS6 Ver: RBF

Other:

IDE(DMA133) *1
FDD *1
SATA(SATA2-300MB/S) *2

F71882 LPC I/O / BIOS
USB connectors
PWM - ISL6566CRZ
MS-6 ACPI Controller
MS-11 / VTT
KB/MS/LPT/COM
ATA 66/100/133 Connectors
ATX Connector / Front Panel

/FAN

VGA
POWER OK MAP
POWER MAP
RESET MAP
MANUAL PARTS

HISTORY

7,8

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

USB2.0 *8(Rear*4 Front*4)
COM PORT *1
LPT PORT *1

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

Cover Sheet

1

MS-7303

Last Revision Date:

Tuesday, July 18, 2006

Sheet

Rev

0A

of

134

5

4

3

2

1

BLOCK DIAGRAM

D D

POWER

SUPPLY

CONNECTOR

PCI-E X16, PCI-E X1

VRM
ISL6566CRZ
3-Phase PWM

PCI EXPRESS

AM2-940

HT 16X16 1GHZ

NFORCE

CRUSH 51G

400/533/667/800MHZ

VGA CONN

DDR II SDRAM CONN 0
240 PIN (Unbuffered)

DDR II SDRAM CONN 1
240 PIN (Unbuffered)

468 BGA

C C

PRIMARY IDE

X2 - SATA CONN

B B

PS2/KBRD CONN

PARALLEL CONN

SERIAL CONN

FAN Control

Vcore Control

ATA 133

INTEGRATED SATA 1/2

SIO

LPC SUPER I/O
F71882

LPC BUS 33MHZ

LPC Header

SPI Header

NFORCE
MCP 51G

508 BGA

HT 8X8 1GHZ

AZAILIA/AC97

X8 USB2

PCI BUS

PCI 33MHZ PCI SLOT 1

Realtek ALC 861/883 (8CH)

BACK PANEL CONN

USB2 PORTS 0-1
DOUBLE STACK

USB2 PORTS 2-3
X2/GBIT LAN

FRONT PANEL HDR

USB2 PORTS 4-5

USB2 PORTS 6-7

Realtek 8201CL/8211BL

1394 VT6308/6307
(Rear X1, Front X1)

PCI SLOT 2

SPI 4MB FLASH

SPI 4MB FLASH

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

Block Diagram

MS-7303

Last Revision Date:
Sheet

1

Monday, July 17, 2006

2

Rev

0A

34

of

5

4

3

2

1

C-51G GPIO FUNCTION

D D

NAME Function Description

GPIO_1

GPIO_2/CPU_SLP*

GPIO_3/CPU_CLKRUN*

GPIO_4/SUS_STAT* MII_phy reset

NC

NC

NC

SIO GPIO FUNCTION

NAME Function Description

GP0

GP1

GP2

GP3

GP4

C C

GP16

CPU FAN GPO

GP17

GP20

GP21

GP32

GP33

NC

NC

NC

NC

GP26/PSIN

B B

GP27/PSOUT#

PSIN#

PSOUT# (PWRBTN#)

GP31/PSON# PS_ON# (ATX_PWR_ON#)

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

GPIO SPEC

MS-7303

Last Revision Date:

Monday, July 17, 2006

Sheet

334

1

Rev

0A

of

5

4

3

2

1

VCC_DDR

R1087

R293
300/4

VCC_DDR

300/4

C590

102P/50V/X7R/4

R308
300/4

CPU_THRIP2# CPU_THRIP# CPU_THRIP#

For thermtrip
function-R1086, R1088
close SB; R1087 close
Q25.

VCC_DDR

TP4

TP11

TP12

R307

80.6R1%

TP15
TP17
TP18

TP21

X_224P/16v/6C577

CADIP[0..15]
CADIN[0..15]
CADOP[0..15]
CADON[0..15]

VCC1_2HT

C579 X_475P/1206

C578 475P/1206

CPU3A

HYPERTRANSPORT

L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)

475P/1206C580

224P/16v/6C581

L0_CLKOUT_H(1)

L0_CLKOUT_L(1)

L0_CLKOUT_H(0)

L0_CLKOUT_L(0)

L0_CTLOUT_H(1)

L0_CTLOUT_L(1)

L0_CTLOUT_H(0)

L0_CTLOUT_L(0)

L0_CADOUT_H(9)

L0_CADOUT_L(9)

L0_CADOUT_H(8)

L0_CADOUT_L(8)

L0_CADOUT_H(7)

L0_CADOUT_L(7)

L0_CADOUT_H(6)

L0_CADOUT_L(6)

L0_CADOUT_H(5)

L0_CADOUT_L(5)

L0_CADOUT_H(4)

L0_CADOUT_L(4)

L0_CADOUT_H(3)

L0_CADOUT_L(3)

L0_CADOUT_H(2)

L0_CADOUT_L(2)

L0_CADOUT_H(1)

L0_CADOUT_L(1)

L0_CADOUT_H(0)

L0_CADOUT_L(0)

X_224P/16v/6C582

AD5
AD4
AD1
AC1

Y6
W6
W2
W3

Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4

Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1

X_224P/16v/6C583

CADOP15
CADON15
CADOP14
CADON14
CADOP13
CADON13
CADOP12
CADON12
CADOP11
CADON11
CADOP10
CADON10
CADOP9
CADON9
CADOP8
CADON8

CADOP7
CADON7
CADOP6
CADON6
CADOP5
CADON5
CADOP4
CADON4
CADOP3
CADON3CADIN3
CADOP2
CADON2
CADOP1
CADON1
CADOP0
CADON0

CLKOP1 9
CLKON1 9
CLKOP0 9
CLKON0 9

CTLOP0 9
CTLON0 9

CPUCLKO_H9

Layout : Place R292
within 0.5 inch of CPU

TP1
TP9

SIO_THERM_SIC21
SIO_THERM_SID21

If SI is not used,the SID
pin cna be left unconnector
and SIC should have a 300
ohm pulldown to VSS

VDDA25VDDA_25

VDDA25

C584 C3900P25X

VCC_DDR

R300

39.2R1%

R304

39.2R1%

C588

C3900P25X

R301
300/4

MEMZN
MEMZP

CPUCLKO_L9

VCC_DDR

R292

169R1%

R294
300/4

SIO_THERM_SIC
SIO_THERM_SID

R299
X_300/4

475P/1206

CPUCLKIN_H

CPUCLKIN_L

X_102P/50V/X7R/6

COREFB_H23

COREFB_L23

CPU_M_VREF

THERMDC_CPU21
THERMDA_CPU21

C585

TP2
TP3
TP10
TP5

TP6

TP7

224P/16v/6

C589

CPU_TEST25_H

CPU_TEST25_L

R305 300/4
R306 300/4

TP13
TP14
TP16
TP20
TP19

C586

C587

3300P/50/X/4

LDT_PWRGD_L
LDT_STOP#_L
LDT_RST#_L

CPU_PRESENT_L

CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS

CPU_DBREQ_L
COREFB_H

COREFB_L

CPU_VTT_SENSE

AK6

AL10
AJ10

AH10

AH11

AJ11

AH9

AG9
AG8
AH7

C10
D10

A8
B8

C9
D8
C7

AL3

AL6

AL9

A5
G2

G1

E12

F12

A10
B10
F10

E9

AJ7

F6
D6

E7
F8
C5

E5

AJ5

AJ6

VDDA1
VDDA2

CLKIN_H
CLKIN_L

PWROK
LDTSTOP_L
RESET_L

CPU_PRESENT_L

SIC
SID

TDI
TRST_L
TCK
TMS

DBREQ_L
VDD_FB_H

VDD_FB_L
VTT_SENSE

M_VREF
M_ZN
M_ZP

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9

TEST17
TEST16
TEST15
TEST14
TEST12

TEST7
TEST6
TEST5
TEST4
TEST3
TEST2

CPU3D

MISC

THERMTRIP_L

PROCHOT_L

DBRDY

VDDIO_FB_H

VDDIO_FB_L

HTREF1
HTREF0

TEST29_H

TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)

TDO

PSI_L

TEST8

80S/0805

2 1

D2
D1
C1
E3
E2
E1

AK7
AL7

AK10

B6
AK11

AL11
F1

V8
V7

C11
D11

AK8
AH8
AJ9
AL8
AJ8

J10
H9
AK9
AK5
G7
D4

L10

VID4
VID3
VID2
VID1
VID0

CPU_THRIP2#

CPU_TDO

CPU_DBRDY

CPU_VDDIOFB_H
CPU_VDDIOFB_L

CPU_PSI_L

R309 300/4

TP8

VCC_DDR

CADIP[0..15]9

CADIN[0..15]9

CADOP[0..15]9

CADON[0..15]9

D D

VCC1_2HT

C C

B B

VCC1_2HT

CLKIP19

CLKIN19

CLKIP09

CLKIN09

R295 49.9/4/1
R296 51

CTLIP09

CTLIN09

CADIP15
CADIN15
CADIP14
CADIN14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8

CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3

CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0

224P/16v/6C574

224P/16v/6C575

X_224P/16v/6C576

N6

L0_CLKIN_H(1)

P6

L0_CLKIN_L(1)

N3

L0_CLKIN_H(0)

N2

L0_CLKIN_L(0)

V4

L0_CTLIN_H(1)

V5

L0_CTLIN_L(1)

U1

L0_CTLIN_H(0)

V1

L0_CTLIN_L(0)

U6

L0_CADIN_H(15)

V6

L0_CADIN_L(15)

T4

L0_CADIN_H(14)

T5

L0_CADIN_L(14)

R6

L0_CADIN_H(13)

T6

L0_CADIN_L(13)

P4

L0_CADIN_H(12)

P5

L0_CADIN_L(12)

M4

L0_CADIN_H(11)

M5

L0_CADIN_L(11)

L6

L0_CADIN_H(10)

M6

L0_CADIN_L(10)

K4

L0_CADIN_H(9)

K5

L0_CADIN_L(9)

J6

L0_CADIN_H(8)

K6

L0_CADIN_L(8)

U3

L0_CADIN_H(7)

U2

L0_CADIN_L(7)

R1

L0_CADIN_H(6)

T1

L0_CADIN_L(6)

R3

L0_CADIN_H(5)

R2

L0_CADIN_L(5)

N1

L0_CADIN_H(4)

P1

L0_CADIN_L(4)

L1

L0_CADIN_H(3)

M1

L0_CADIN_L(3)

L3

L0_CADIN_H(2)

L2

L0_CADIN_L(2)

J1

L0_CADIN_H(1)

K1

L0_CADIN_L(1)

J3

L0_CADIN_H(0)

J2

L0_CADIN_L(0)

VCC3 3VDUAL

R1086

4.7K/4

VID[0..4] 21

VCC_DDR

R297

4.7K/4

Q25 N-MMBT3904_SOT23

Layout : Place
with in 1 inch

R302 44.2RST
R303 44.2RST

C591

102P/50V/X7R/4

Layout :

1)Place R307 within

0.5 inch

2)FBCLKOUT are
differential signals
(8/5/20)

VCC_DDR

CPU_THRIP# 12

VCC1_2HT

R1088
X_4.7K/4

R298
300/4

VCC_DDR

R314

15/6/1

VCC_DDR

U17D

9 8

07_SOIC14

VCC_DDR

U17F

13 12

07_SOIC14

R310
15/6/1

0.1u/25V/4

147

147

For S3 issue(LDT RST can not still low)

VCC2_5

RN85

1

2
4
6
8

8P4R-330R

A A

-LDTSTOP9

ATX_PWR_OK13,21,24,28

3
5
7

-LDT_RST
CPU_GD

-LDTSTOP

-LDTSTOP

5

07_SOIC14

07_SOIC14

VCC_DDR

U17A

147

1 2

VCC_DDR

U17B

147

3 4

VCC_DDR

RN111

1
3
5
7

8P4R-330R

2
4
6
8

CPU_THRIP2#
LDT_RST#_L
LDT_PWRGD_L
LDT_STOP#_L

Use RN86 when 7407
Don't Stuff

-LDTSTOP
CPU_GD

-LDT_RST

ATX_PWR_OK13,21,24,28

-LDT_RST9

4

RN86

1

2

3

4

5

6

7

8

X_0/6/8P4R

VCC_DDR

U17C

5 6

07_SOIC14

VCC_DDR

U17E

11 10

07_SOIC14

LDT_STOP#_L
LDT_PWRGD_L
LDT_RST#_L

147

147

CPU_GD9

LDT_RST#_L-LDT_RSTLDT_STOP#_L

ATX_PWR_OK13,21,24,28

CPU_GD

3

C592

CPU_M_VREF

C593
102P/50V/X7R/6

LDT_PWRGD_L

2

CPU_PRESENT_L
CPU_TEST25_H

CPU_TEST25_L

R312 1K/4/1
R311 510R

R313 510R

VCC_DDR

Micro Star Restricted Secret

Title

ATHLON64 HT I/F CTRL & DEBUG

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7303

1

Last Revision Date:

Tuesday, July 25, 2006

Sheet

434

Rev

0A

of

5

D D

4

3

2

1

CPU3B

MEM_MA0_CLK_H27,8
MEM_MA0_CLK_L27,8

MEM_MA0_CLK_H17,8
MEM_MA0_CLK_L17,8
MEM_MA0_CLK_H07,8
MEM_MA0_CLK_L07,8

MEM_MA0_CS_L17,8
MEM_MA0_CS_L07,8

MEM_MA0_ODT07,8

MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0

MEM_MA0_CS_L1
MEM_MA0_CS_L0

MEM_MA0_ODT0

AG21
AG20

G19
H19
U27
U26

AC25
AA24

AC28
AE20

AE19

G20
G21
V27
W27

AD27
AA25

AC27

C C

MEM_MA_CAS_L7,8
MEM_MA_WE_L7,8
MEM_MA_RAS_L7,8

MEM_MA_BANK27,8
MEM_MA_BANK17,8
MEM_MA_BANK07,8

MEM_MA_CKE07,8

MEM_MA_ADD[15..0]7,8

MEM_MA_DQS_H77
MEM_MA_DQS_L77

B B

MEM_MA_DQS_H67
MEM_MA_DQS_L67
MEM_MA_DQS_H57
MEM_MA_DQS_L57
MEM_MA_DQS_H47
MEM_MA_DQS_L47
MEM_MA_DQS_H37
MEM_MA_DQS_L37
MEM_MA_DQS_H27
MEM_MA_DQS_L27
MEM_MA_DQS_H17
MEM_MA_DQS_L17
MEM_MA_DQS_H07
MEM_MA_DQS_L07

MEM_MA_DM77
MEM_MA_DM67
MEM_MA_DM57
MEM_MA_DM47
MEM_MA_DM37
MEM_MA_DM27
MEM_MA_DM17
MEM_MA_DM07

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_CKE0
MEM_MA_ADD15

MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0

AB25
AB27
AA26

N25
Y27

AA27

M25
M27

N24

AC26

N26
P25
Y25
N27
R24
P27
R25
R26
R27

U25
W24

AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28

D29
C29
C25
D25
E19

G15

AF15
AF19
AJ25
AH29

B29
E24
E18
H15

L27

T25
T27

F19
F15

MEMORY INTERFACE A

MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)

MA0_CS_L(1)
MA0_CS_L(0)

MA0_ODT(0)
MA1_CLK_H(2)

MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)

MA1_CS_L(1)
MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L
MA_WE_L
MA_RAS_L

MA_BANK(2)
MA_BANK(1)
MA_BANK(0)

MA_CKE(1)
MA_CKE(0)

MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)

MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)

MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)

MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)

MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)

MA_DQS_H(8)

MA_DQS_L(8)

MA_DM(8)

MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)

MEM_MA_DATA63

AE14

MEM_MA_DATA62

AG14

MEM_MA_DATA61

AG16

MEM_MA_DATA60

AD17

MEM_MA_DATA59

AD13

MEM_MA_DATA58

AE13

MEM_MA_DATA57

AG15

MEM_MA_DATA56

AE16

MEM_MA_DATA55

AG17

MEM_MA_DATA54

AE18

MEM_MA_DATA53

AD21

MEM_MA_DATA52

AG22

MEM_MA_DATA51

AE17

MEM_MA_DATA50

AF17

MEM_MA_DATA49

AF21

MEM_MA_DATA48

AE21

MEM_MA_DATA47

AF23

MEM_MA_DATA46

AE23

MEM_MA_DATA45

AJ26

MEM_MA_DATA44

AG26

MEM_MA_DATA43

AE22

MEM_MA_DATA42

AG23

MEM_MA_DATA41

AH25

MEM_MA_DATA40

AF25

MEM_MA_DATA39

AJ28

MEM_MA_DATA38

AJ29

MEM_MA_DATA37

AF29

MEM_MA_DATA36

AE26

MEM_MA_DATA35

AJ27

MEM_MA_DATA34

AH27

MEM_MA_DATA33

AG29

MEM_MA_DATA32

AF27

MEM_MA_DATA31

E29

MEM_MA_DATA30

E28

MEM_MA_DATA29

D27

MEM_MA_DATA28

C27

MEM_MA_DATA27

G26

MEM_MA_DATA26

F27

MEM_MA_DATA25

C28

MEM_MA_DATA24

E27

MEM_MA_DATA23

F25

MEM_MA_DATA22

E25

MEM_MA_DATA21

E23

MEM_MA_DATA20

D23

MEM_MA_DATA19

E26

MEM_MA_DATA18

C26

MEM_MA_DATA17

G23

MEM_MA_DATA16

F23

MEM_MA_DATA15

E22

MEM_MA_DATA14

E21

MEM_MA_DATA13

F17

MEM_MA_DATA12

G17

MEM_MA_DATA11

G22

MEM_MA_DATA10

F21

MEM_MA_DATA9

G18

MEM_MA_DATA8

E17

MEM_MA_DATA7

G16

MEM_MA_DATA6

E15

MEM_MA_DATA5

G13

MEM_MA_DATA4

H13

MEM_MA_DATA3

H17

MEM_MA_DATA2

E16

MEM_MA_DATA1

E14

MEM_MA_DATA0

G14
J28

J27
J25
K25

J26
G28
G27
L24
K27
H29
H27

MEM_MA_DATA[63..0] 7

MEM_MB0_CLK_H27,8
MEM_MB0_CLK_L27,8
MEM_MB0_CLK_H17,8
MEM_MB0_CLK_L17,8

MEM_MB0_CLK_H07,8
MEM_MB0_CLK_L07,8

MEM_MB0_CS_L17,8

MEM_MB0_CS_L07,8

MEM_MB0_ODT07,8

MEM_MB_CAS_L7,8
MEM_MB_WE_L7,8
MEM_MB_RAS_L7,8

MEM_MB_BANK27,8
MEM_MB_BANK17,8
MEM_MB_BANK07,8

MEM_MB_CKE07,8

MEM_MB_ADD[15..0]7,8

MEM_MB_DQS_H77
MEM_MB_DQS_L77
MEM_MB_DQS_H67
MEM_MB_DQS_L67
MEM_MB_DQS_H57
MEM_MB_DQS_L57
MEM_MB_DQS_H47
MEM_MB_DQS_L47
MEM_MB_DQS_H37
MEM_MB_DQS_L37
MEM_MB_DQS_H27
MEM_MB_DQS_L27
MEM_MB_DQS_H17
MEM_MB_DQS_L17
MEM_MB_DQS_H07
MEM_MB_DQS_L07

MEM_MB_DM77
MEM_MB_DM67
MEM_MB_DM57
MEM_MB_DM47
MEM_MB_DM37
MEM_MB_DM27
MEM_MB_DM17
MEM_MB_DM07

MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0

MEM_MB0_CS_L1
MEM_MB0_CS_L0

MEM_MB0_ODT0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_CKE0
MEM_MB_ADD15

MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0

AJ19

AK19

AE30
AC31

AD29

AL19
AL18

AE29
AB31

AD31

AC29
AC30
AB29

AA31
AA28

AE31

AA29

AA30
AK13

AJ13

AK17

AJ17

AK23

AL23
AL28
AL29

AJ14

AH17

AJ23

AK29

A18
A19
U31
U30

C19
D19
W29
W28

N31

M31
M29

N28
N29

N30
P29

P31
R29
R28
R31
R30

U29
U28

D31
C31
C24
C23
D17
C17
C14
C13

C30
A23
B17
B13

T31
T29

MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)

MB0_CS_L(1)
MB0_CS_L(0)

MB0_ODT(0)
MB1_CLK_H(2)

MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)

MB1_CS_L(1)
MB1_CS_L(0)

MB1_ODT(0)

MB_CAS_L
MB_WE_L
MB_RAS_L

MB_BANK(2)
MB_BANK(1)
MB_BANK(0)

MB_CKE(1)
MB_CKE(0)

MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)

MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)

MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)

CPU3C

MEMORY INTERFACE B

MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)

MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)

MB_DQS_H(8)

MB_DQS_L(8)

MB_DM(8)

MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)

AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13

J31
J30

J29
K29

K31
G30
G29
L29
L28
H31
G31

MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0

MEM_MB_DATA[63..0] 7

A A

Micro Star Restricted Secret

Title

ATHLON64 DDR MEMORY I/F

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

MS-7303

1

Last Revision Date:

Monday, July 17, 2006

Sheet

534

Rev

0A

of

5

4

3

2

1

VCORE

CPU3F

VDD1

A4

VDD1

A6

VDD2

AA8

VDD3

AA10

VDD4

AA12

VDD5

AA14

VDD6

AA16

VDD7

AA18

VDD8

AB7

VDD9

D D

C C

B B

AB11

AC4
AC5
AC8

AC10

AD2
AD3
AD7
AD9

AE10

AF7
AF9
AG4
AG5
AG7
AH2
AH3

G10
G12

H11
H23

AB9

VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27

B3

VDD28

B5

VDD29

B7

VDD30

C2

VDD31

C4

VDD32

C6

VDD33

C8

VDD34

D3

VDD35

D5

VDD36

D7

VDD37

D9

VDD38

E4

VDD39

E6

VDD40

E8

VDD41

E10

VDD42

F5

VDD43

F7

VDD44

F9

VDD45

F11

VDD46

G6

VDD47

G8

VDD48
VDD49
VDD50

H7

VDD51
VDD52
VDD53

J8

VDD54

J12

VDD55

J14

VDD56

J16

VDD57

J18

VDD58

J20

VDD59

J22

VDD60

J24

VDD61

K7

VDD62

K9

VDD63

K11

VDD64

K13

VDD65

K15

VDD66

K17

VDD67

K19

VDD68

K21

VDD69

K23

VDD70

L4

VDD71

L5

VDD72

L8

VDD73

L10

VDD74

L12

VDD75

Y17

VDD150

Y19

VDD151

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

VSS240
VSS241

A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16

SLOTOCC#_CPU 21

VCORE

M11
M13
M15
M17
M19

N10
N12
N14
N16
N18

P11
P13
P15
P17
P19

R10
R12
R14
R16
R18
R20

U10
U12
U14
U16
U18
U20

V11
V13
V15
V17
V19
V21

W10
W12
W14
W16
W18
W20

Y11
Y13
Y15
Y21

CPU3G

L14
L16
L18

T11
T13
T15
T17
T19
T21

VDD2

VDD1
VDD2
VDD3

M2

VDD4

M3

VDD5

M7

VDD6

M9

VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

N8

VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

P7

VDD19

P9

VDD20
VDD21
VDD22
VDD23
VDD24
VDD25

R4

VDD26

R5

VDD27

R8

VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34

T2

VDD35

T3

VDD36

T7

VDD37

T9

VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44

U8

VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51

V9

VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58

W4

VDD59

W5

VDD60

W8

VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67

Y2

VDD68

Y3

VDD69

Y7

VDD70

Y9

VDD71
VDD72
VDD73
VDD74
VDD75

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75

AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18

VCORE

AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11

M21
M23
N20
N22
P21
P23
R22

U22
V23
W22
Y23

L20
L22

T23

CPU3H

VDD3

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32

5

GND

6

GND

7

GND

8

GND

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22

VCC_DDR

VCC1_2HT

VTT_DDR

AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30

M24
M26
M28
M30
P24
P26
P28
P30

V25
V26
V28
V30
Y24
Y26
Y28
Y29

CPU3I

VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4

VTT1
VTT2
VTT3
VTT4

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29

VDDIO

VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4

VTT5
VTT6
VTT7
VTT8
VTT9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28

AJ4
AJ3
AJ2
AJ1

D12
C12
B12
A12

T24
T26
T28
T30

H6
H5
H2
H1

AK12
AJ12
AH12
AG12
AL12

K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15

VLDT_RUN_B

VTT_DDR

C594 4.7u/10/Y/8

X_0.01u/50V/6/X7RC595

X_0.01u/50V/6/X7RC596

X_0.01u/50V/6/X7RC597

VCORE

C602 X_180P

X_224P/16v/6C599

0.01u/50V/6/X7RC601

224P/16v/6C600

VCORE

C614 X_C22U6.3X1206/B

C603 X_C22U6.3X1206/BX_224P/16v/6C598

C604 X_C22U6.3X1206/B

C605 X_C22U6.3X1206/B

C606 C10U6.3X1206/B

C607 X_C22U6.3X1206/B

C608 X_C22U6.3X1206/B

C609 X_C22U6.3X1206/B

C610 C10U6.3X1206/B

C611 X_C22U6.3X1206/B

C612 C10U6.3X1206/B

C613 X_C22U6.3X1206

C615 C10U6.3X1206/B

C616 X_C22U6.3X1206/B

C617 X_C22U6.3X1206

VTT_DDR

C622 X_180P

C623 X_180P

C624 102P/50V/X7R/6

C625 102P/50V/X7R/6

C620 4.7u/10/Y/8

C621 X_4.7u/10Y/8

X_224P/16v/6C618

224P/16v/6C619

A A

5

VTT_DDR

224P/16v/6C640

224P/16v/6C641

C642 X_4.7u/10Y/8

C643 X_4.7u/10/Y/8

C644 X_180P

4

C645 180P

C646 X_102P/50V/X7R/6

C647 102P/50V/X7R/6

VTT_DDR

For EMI

C961 X_0.1u/16V/4

C960 X_0.1u/16V/4

C630 C4.7U6.3X0603

VCC_DDRVCC_DDR

C633 C4.7U6.3X0603

C632 X_C22U6.3X1206

+

C631 X_C22U6.3X1206/B

EC45 1000u/16V/8*20

224P/16v/6C635

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

C638 C22U6.3X1206/B

C639 180P

224P/16v/6C636

0.01u/50V/6/X7RC637

Micro Star Restricted Secret

ATHLON64 PWR & GND

MS-7303

Last Revision Date:

Friday, July 21, 2006

Sheet

1

Rev

0A

of

634

C964 X_0.1u/16V/4

C963 X_0.1u/16V/4

C962 X_0.1u/16V/4

C629 C4.7U6.3X0603

X_224P/16v/6C626

224P/16v/6C627

224P/16v/6C628

3

2

5

4

VCC3VCC_DDR

3

2

VCC3VCC_DDR

1

DIMM1

55

102

68

MEM_MA_DATA[63..0]5

D D

C C

B B

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

19

NC

3

RC118RC0

DQ0

4

DQ1

9

NC/TEST

DQ2

10

DQ3

122

DQ4

123

DQ5

128

DQ6

129

DQ7

12

DQ8

13

DQ9

21

DQ10

22

DQ11

131

DQ12

132

DQ13

140

DQ14

141

DQ15

24

DQ16

25

DQ17

30

DQ18

31

DQ19

143

DQ20

144

DQ21

149

DQ22

150

DQ23

33

DQ24

34

DQ25

39

DQ26

40

DQ27

152

DQ28

153

DQ29

158

DQ30

159

DQ31

80

DQ32

81

DQ33

86

DQ34

87

DQ35

199

DQ36

200

DQ37

205

DQ38

206

DQ39

89

DQ40

90

DQ41

95

DQ42

96

DQ43

208

DQ44

209

DQ45

214

DQ46

215

DQ47

98

DQ48

99

DQ49

107

DQ50

108

DQ51

217

DQ52

218

DQ53

226

DQ54

227

DQ55

110

DQ56

111

DQ57

116

DQ58

117

DQ59

229

DQ60

230

DQ61

235

DQ62

236

DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

50

VSS

65

VSS

66

VSS

79

VSS

82

VSS

85

VSS

88

VSS

91

VSS

94

VSS

97

VSS

VSS

VSS

VSS

VSS

100

103

106

109

112

NC

VDD051VDD156VDD262VDD372VDD478VDD5

VSS

VSS

VSS

VSS

115

118

121

124

191

194

181

175

75

170

197

172

187

184

189

67

178

VDD6

VDD7

VDD8

VDD3

VDDQ0

VDDQ153VDDQ259VDDQ364VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ469VDDQ7

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

127

130

133

136

139

142

145

148

151

154

157

160

163

166

169

198

201

204

207

VDDQ9

VSS

161

162

167

CB042CB143CB248CB349CB4

VSS

VSS

219

VSS

222

DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

CK1#(CK0#)

VSS

VSS

225

228

168

CB5

CB6

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

A10_AP

A11
A12
A13
A14
A15

A16/BA2

BA1
BA0

WE#
CAS#
RAS#

DM0/DQS9
NC/DQS9#

ODT0
ODT1

CKE0
CKE1

CS0#
CS1#

CK0(DU)
CK0#(DU)
CK1(CK0)

CK2(DU)
CK2#(DU)

SCL

SDA

VREF

SA0
SA1
SA2

VSS

VSS

VSS

DDRII-240_GREEN

231

234

237

CB7

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

MEM_MA_DQS_H0

7

MEM_MA_DQS_L0

6

MEM_MA_DQS_H1

16

MEM_MA_DQS_L1

15

MEM_MA_DQS_H2

28

MEM_MA_DQS_L2

27

MEM_MA_DQS_H3

37

MEM_MA_DQS_L3

36

MEM_MA_DQS_H4

84

MEM_MA_DQS_L4

83

MEM_MA_DQS_H5

93

MEM_MA_DQS_L5

92

MEM_MA_DQS_H6

105

MEM_MA_DQS_L6

104

MEM_MA_DQS_H7

114

MEM_MA_DQS_L7

113
46
45

MEM_MA_ADD0

188

MEM_MA_ADD1

183

MEM_MA_ADD2

63

MEM_MA_ADD3

182

MEM_MA_ADD4

61

MEM_MA_ADD5

60

MEM_MA_ADD6

180

MEM_MA_ADD7

58

MEM_MA_ADD8

179

MEM_MA_ADD9

177

MEM_MA_ADD10

70

MEM_MA_ADD11

57

MEM_MA_ADD12

176

MEM_MA_ADD13

196

MEM_MA_ADD14

174

MEM_MA_ADD15

173

MEM_MA_BANK2

54

MEM_MA_BANK1

190

MEM_MA_BANK0

71

MEM_MA_WE_L

73

MEM_MA_CAS_L

74

MEM_MA_RAS_L

192

MEM_MA_DM0

125
126

MEM_MA_DM1

134
135

MEM_MA_DM2

146
147

MEM_MA_DM3

155
156

MEM_MA_DM4

202
203

MEM_MA_DM5

211
212

MEM_MA_DM6

223
224

MEM_MA_DM7

232
233
164
165

MEM_MA0_ODT0

195
77

52
171

MEM_MA0_CS_L0

193

MEM_MA0_CS_L1

76

MEM_MA0_CLK_H0

185

MEM_MA0_CLK_L0

186

MEM_MA0_CLK_H1

137

MEM_MA0_CLK_L1

138

MEM_MA0_CLK_H2

220

MEM_MA0_CLK_L2

221

SMB_MEM_CLK

120

SMB_MEM_DATA

119
1

239
240
101

MEM_MA_DQS_H0 5
MEM_MA_DQS_L0 5
MEM_MA_DQS_H1 5
MEM_MA_DQS_L1 5
MEM_MA_DQS_H2 5
MEM_MA_DQS_L2 5
MEM_MA_DQS_H3 5
MEM_MA_DQS_L3 5
MEM_MA_DQS_H4 5
MEM_MA_DQS_L4 5
MEM_MA_DQS_H5 5
MEM_MA_DQS_L5 5
MEM_MA_DQS_H6 5
MEM_MA_DQS_L6 5
MEM_MA_DQS_H7 5
MEM_MA_DQS_L7 5

MEM_MA_ADD[15..0] 5,8

MEM_MA_BANK2 5,8
MEM_MA_BANK1 5,8
MEM_MA_BANK0 5,8

MEM_MA_WE_L 5,8
MEM_MA_CAS_L 5,8
MEM_MA_RAS_L 5,8

MEM_MA_DM[7..0] 5

MEM_MA0_ODT0 5,8

MEM_MA_CKE0 5,8

MEM_MA0_CS_L0 5,8
MEM_MA0_CS_L1 5,8

MEM_MA0_CLK_H0 5,8

MEM_MA0_CLK_L0 5,8

MEM_MA0_CLK_H1 5,8

MEM_MA0_CLK_L1 5,8

MEM_MA0_CLK_H2 5,8

MEM_MA0_CLK_L2 5,8

SMB_MEM_CLK 13

SMB_MEM_DATA 13

VDDR_VREF

C651

0.1u/25V/4

PLACE CLOSE TO DIMM PIN

MEM_MB_DATA[63..0]5

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

238

VDDSPD

VSS

VSS

210

213

216

ADDRESS: 000

R317

56.2R1%

R318

56.2R1%

VCC_DDR

C653

X_0.1u/25V/4

C654

0.1u/25V/4

VDDR_VREF

VDDR_VREF

C655
102P/50V/X7R/6

SMB_MEM_CLK SMB_MEM_DATA

3VDUAL 3VDUAL

2

3

D29
BAV99

1

3

MEM_MA_DQS_H[7..0]5

2

D30
BAV99

1

MEM_MA_DQS_L[7..0]5

MEM_MB_DQS_H[7..0]5
MEM_MB_DQS_L[7..0]5

DIMM2

122
123
128
129

131
132
140
141

143
144
149
150

152
153
158
159

199
200
205
206

208
209
214
215

107
108
217
218
226
227
110
111
116
117
229
230
235
236

161

162

167

CB042CB143CB248CB349CB4

VSS

VSS

219

VSS

222

DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#

CK1#(CK0#)

VSS

VSS

225

228

168

CB5

CB6

CB7

DQS0

DQS0#

DQS1

DQS1#

DQS2

DQS2#

DQS3

DQS3#

DQS4

DQS4#

DQS5

DQS5#

DQS6

DQS6#

DQS7

DQS7#

DQS8

DQS8#

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10_AP

A11
A12
A13
A14
A15

A16/BA2

BA1
BA0

WE#
CAS#
RAS#

DM0/DQS9
NC/DQS9#

ODT0
ODT1

CKE0
CKE1

CS0#
CS1#

CK0(DU)
CK0#(DU)
CK1(CK0)

CK2(DU)
CK2#(DU)

SCL

SDA

VREF

SA0
SA1
SA2

VSS

VSS

VSS

DDRII-240_ORANGE

231

234

237

MEM_MB_DQS_H0

7

MEM_MB_DQS_L0

6

MEM_MB_DQS_H1

16

MEM_MB_DQS_L1

15

MEM_MB_DQS_H2

28

MEM_MB_DQS_L2

27

MEM_MB_DQS_H3

37

MEM_MB_DQS_L3

36

MEM_MB_DQS_H4

84

MEM_MB_DQS_L4

83

MEM_MB_DQS_H5

93

MEM_MB_DQS_L5

92

MEM_MB_DQS_H6

105

MEM_MB_DQS_L6

104

MEM_MB_DQS_H7

114

MEM_MB_DQS_L7

113
46
45

MEM_MB_ADD0

188

MEM_MB_ADD1

183

MEM_MB_ADD2

63

MEM_MB_ADD3

182

MEM_MB_ADD4

61

MEM_MB_ADD5

60

MEM_MB_ADD6

180

MEM_MB_ADD7

58

MEM_MB_ADD8

179

MEM_MB_ADD9

177

MEM_MB_ADD10

70

MEM_MB_ADD11

57

MEM_MB_ADD12

176

MEM_MB_ADD13

196

MEM_MB_ADD14

174

MEM_MB_ADD15

173

MEM_MB_BANK2

54

MEM_MB_BANK1

190

MEM_MB_BANK0

71

MEM_MB_WE_L

73

MEM_MB_CAS_L

74

MEM_MB_RAS_L

192

MEM_MB_DM0

125
126

MEM_MB_DM1

134
135

MEM_MB_DM2

146
147

MEM_MB_DM3

155
156

MEM_MB_DM4

202
203

MEM_MB_DM5

211
212

MEM_MB_DM6

223
224

MEM_MB_DM7

232
233
164
165

MEM_MB0_ODT0

195
77

52
171

MEM_MB0_CS_L0

193

MEM_MB0_CS_L1

76

MEM_MB0_CLK_H0

185

MEM_MB0_CLK_L0

186

MEM_MB0_CLK_H1

137

MEM_MB0_CLK_L1

138

MEM_MB0_CLK_H2

220

MEM_MB0_CLK_L2

221

SMB_MEM_CLK

120

SMB_MEM_DATA

119

VDDR_VREFVDDR_VREF

1

VCC3

239
240
101

MEM_MB_DQS_H0 5
MEM_MB_DQS_L0 5
MEM_MB_DQS_H1 5
MEM_MB_DQS_L1 5
MEM_MB_DQS_H2 5
MEM_MB_DQS_L2 5
MEM_MB_DQS_H3 5
MEM_MB_DQS_L3 5
MEM_MB_DQS_H4 5
MEM_MB_DQS_L4 5
MEM_MB_DQS_H5 5
MEM_MB_DQS_L5 5
MEM_MB_DQS_H6 5
MEM_MB_DQS_L6 5
MEM_MB_DQS_H7 5
MEM_MB_DQS_L7 5

MEM_MB_ADD[15..0] 5,8

MEM_MB_BANK2 5,8
MEM_MB_BANK1 5,8
MEM_MB_BANK0 5,8

MEM_MB_WE_L 5,8
MEM_MB_CAS_L 5,8
MEM_MB_RAS_L 5,8

MEM_MB_DM[7..0] 5

MEM_MB0_ODT0 5,8

MEM_MB_CKE0 5,8

MEM_MB0_CS_L0 5,8
MEM_MB0_CS_L1 5,8

MEM_MB0_CLK_H0 5,8

MEM_MB0_CLK_L0 5,8

MEM_MB0_CLK_H1 5,8

MEM_MB0_CLK_L1 5,8

MEM_MB0_CLK_H2 5,8

MEM_MB0_CLK_L2 5,8

SMB_MEM_CLK 13

SMB_MEM_DATA 13

VDDR_VREF

C652

0.1u/25V/4

PLACE CLOSE TO DIMM PIN

55

102

68

19

NC

3

RC118RC0

DQ0

4

DQ1

9

NC/TEST

DQ2

10

DQ3
DQ4
DQ5
DQ6
DQ7

12

DQ8

13

DQ9

21

DQ10

22

DQ11
DQ12
DQ13
DQ14
DQ15

24

DQ16

25

DQ17

30

DQ18

31

DQ19
DQ20
DQ21
DQ22
DQ23

33

DQ24

34

DQ25

39

DQ26

40

DQ27
DQ28
DQ29
DQ30
DQ31

80

DQ32

81

DQ33

86

DQ34

87

DQ35
DQ36
DQ37
DQ38
DQ39

89

DQ40

90

DQ41

95

DQ42

96

DQ43
DQ44
DQ45
DQ46
DQ47

98

DQ48

99

DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

2

VSS

5

VSS

8

VSS

11

VSS

14

VSS

17

VSS

20

VSS

23

VSS

26

VSS

29

VSS

32

VSS

35

VSS

38

VSS

41

VSS

44

VSS

47

VSS

50

VSS

65

VSS

66

VSS

79

VSS

82

VSS

85

VSS

88

VSS

91

VSS

94

VSS

97

VSS

VSS

VSS

VSS

VSS

100

103

106

109

112

NC

VDD051VDD156VDD262VDD372VDD478VDD5

VSS

VSS

VSS

VSS

115

118

121

124

191

194

181

175

75

170

197

VDD6

VDD7

VDD8

VDD3

VDDQ0

VDDQ153VDDQ259VDDQ364VDDQ4

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

127

130

133

136

139

142

145

148

151

154

157

160

163

172

187

184

178

VDDQ5

VDDQ6

VDDQ7

VDDQ469VDDQ7

VSS

VSS

VSS

VSS

VSS

166

169

198

201

189

204

VDDQ8

VSS

67

207

VDDQ9

VSS

210

238

VDDSPD

VSS

VSS

213

216

ADDRESS: 001

A A

Micro Star Restricted Secret

Title

DDR II DIMM 1 & 2

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

MS-7303

1

Last Revision Date:

Thursday, July 20, 2006

Sheet

Rev

0A

of

734

5

MEM_MA_BANK25,7
MEM_MA_ADD145,7
MEM_MA_ADD155,7
MEM_MB_ADD95,7

MEM_MB_ADD115,7
MEM_MA_ADD125,7
MEM_MB_ADD75,7
MEM_MA_ADD115,7

D D

MEM_MA_ADD85,7
MEM_MA_ADD65,7
MEM_MA_ADD55,7
MEM_MB_ADD55,7

MEM_MB_ADD35,7
MEM_MA_ADD25,7
MEM_MB_ADD15,7
MEM_MB_ADD25,7

MEM_MA_ADD05,7
MEM_MA_ADD105,7
MEM_MA_BANK15,7

MEM_MB_RAS_L5,7

MEM_MA_WE_L5,7

MEM_MB_WE_L5,7

MEM_MA_CAS_L5,7
MEM_MA0_ODT05,7

MEM_MA_ADD135,7
MEM_MA0_CS_L15,7

C C

MEM_MA_BANK2
MEM_MA_ADD14
MEM_MA_ADD15
MEM_MB_ADD9

MEM_MB_ADD11
MEM_MA_ADD12
MEM_MB_ADD7
MEM_MA_ADD11

MEM_MA_ADD8
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MB_ADD5

MEM_MB_ADD3
MEM_MA_ADD2
MEM_MB_ADD1
MEM_MB_ADD2

MEM_MA_ADD0
MEM_MA_ADD10
MEM_MA_BANK1
MEM_MB_RAS_L

MEM_MA_WE_L
MEM_MB_WE_L
MEM_MA_CAS_L
MEM_MA0_ODT0

MEM_MA_ADD13
MEM_MA0_CS_L1

RN89 8P4R-47R0402

1
3
5
7

RN90 8P4R-47R0402

1
3
5
7

RN91 8P4R-47R0402

1
3
5
7

RN92 8P4R-47R0402

1
3
5
7

RN93 8P4R-47R0402

1
3
5
7

RN94 8P4R-47R0402

1
3
5
7

R320 47R0402
R319 47R0402

VTT_DDR

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

4

MEM_MA0_CLK_H25,7

MEM_MA0_CLK_L25,7

MEM_MA0_CLK_H15,7

MEM_MA0_CLK_L15,7

MEM_MA0_CLK_H05,7

MEM_MA0_CLK_L05,7

MEM_MB0_CLK_H25,7

MEM_MB0_CLK_L25,7

MEM_MB0_CLK_H15,7

MEM_MB0_CLK_L15,7

MEM_MB0_CLK_H05,7

MEM_MB0_CLK_L05,7

MEM_MA0_CLK_H2

MEM_MA0_CLK_L2

MEM_MA0_CLK_H1

MEM_MA0_CLK_L1

MEM_MA0_CLK_H0

MEM_MA0_CLK_L0

MEM_MB0_CLK_H2

MEM_MB0_CLK_L2

MEM_MB0_CLK_H1

MEM_MB0_CLK_L1

MEM_MB0_CLK_H0

MEM_MB0_CLK_L0

C664
C1.5P/4

C681
C1.5P/4

C696

C1.5P/4

C703
C1.5P/4

C704
C1.5P/4

C705
C1.5P/4

VTT_DDR

C708 0.1u/25V/4

3

VCC_DDR VCC_DDR

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

C22P50N0603C657
C22P50N0603C659
C22P50N0603C661
C22P50N0603C666
C22P50N0603C665
C22P50N0603C668
C22P50N0603C672
C22P50N0603C671
C22P50N0603C673
C22P50N0603C676 22p/50/N/4C678
C22P50N0603C677

C22P50N0603C682
C22P50N0603C684
C22P50N0603C687

C22P50N0603C690
C22P50N0603C691
C22P50N0603C693

C22P50N0603C697
C22P50N0603C698
C22P50N0603C700 22p/50/N/4C701

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

Decoupling Between Processor and DIMMs

Layout: Spread out on VTT pour

C713 0.1u/25V/4

C712 0.1u/25V/4

C711 X_0.1u/25V/4

C709 0.1u/25V/4

C710 0.1u/25V/4

C716 0.1u/25V/4

C715 0.1u/25V/4

C714 0.1u/25V/4

C717 0.1u/25V/4

C720 0.1u/25V/4

C719 0.1u/25V/4

C718 X_0.1u/25V/4

2

22p/50/N/4C658C22P50N0603C656
22p/50/N/4C660
22p/50/N/4C662
22p/50/N/4C663
22p/50/N/4C667
22p/50/N/4C669
22p/50/N/4C670
22p/50/N/4C675
22p/50/N/4C674
22p/50/N/4C679

22p/50/N/4C680
22p/50/N/4C686C22P50N0603C683
22p/50/N/4C685
22p/50/N/4C689
22p/50/N/4C688

22p/50/N/4C692
22p/50/N/4C695
22p/50/N/4C694

22p/50/N/4C699
22p/50/N/4C702

VTT_DDR VCC_DDR

C724 X_0.1u/25V/4

C721 0.1u/25V/4

C722 X_0.1u/25V/4

C723 X_0.1u/25V/4

1

C726 X_0.1u/25V/4

C727 0.1u/25V/4

C728 0.1u/25V/4

VTT_DDR

RN95 8P4R-47R0402

1

MEM_MB_CKE05,7

B B

MEM_MB_ADD155,7
MEM_MB_ADD145,7

MEM_MA_ADD95,7
MEM_MA_ADD75,7
MEM_MB_ADD85,7
MEM_MB_ADD65,7

MEM_MA_ADD45,7
MEM_MA_ADD35,7
MEM_MB_ADD45,7
MEM_MA_ADD15,7

MEM_MB_ADD05,7
MEM_MB_BANK15,7
MEM_MB_ADD105,7
MEM_MB_BANK05,7

MEM_MA_BANK05,7
MEM_MA_RAS_L5,7
MEM_MB0_CS_L05,7
MEM_MA0_CS_L05,7

MEM_MB_BANK25,7

A A

MEM_MB_ADD125,7
MEM_MA_CKE05,7

MEM_MB_CAS_L5,7

MEM_MB0_ODT05,7
MEM_MB_ADD135,7
MEM_MB0_CS_L15,7

MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14

MEM_MA_ADD9
MEM_MA_ADD7
MEM_MB_ADD8
MEM_MB_ADD6

MEM_MA_ADD4
MEM_MA_ADD3
MEM_MB_ADD4
MEM_MA_ADD1

MEM_MB_ADD0
MEM_MB_BANK1
MEM_MB_ADD10
MEM_MB_BANK0

MEM_MA_BANK0
MEM_MA_RAS_L
MEM_MB0_CS_L0
MEM_MA0_CS_L0

MEM_MB_BANK2
MEM_MB_ADD12
MEM_MA_CKE0

MEM_MB_CAS_L
MEM_MB0_ODT0
MEM_MB_ADD13
MEM_MB0_CS_L1

5

2

3

4

5

6

7

8

RN96 8P4R-47R0402

1

2

3

4

5

6

7

8

RN97 8P4R-47R0402

1

2

3

4

5

6

7

8

RN98 8P4R-47R0402

1

2

3

4

5

6

7

8

RN99 8P4R-47R0402

1

2

3

4

5

6

7

8

RN100 8P4R-47R0402

1

2

3

4

5

6

7

8

RN101 8P4R-47R0402

1

2

3

4

5

6

7

8

Micro Star Restricted Secret

Title

DDR Terminatior

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

4

3

2

http://www.msi.com.tw

MS-7303

1

Last Revision Date:

Monday, July 17, 2006

Sheet

834

Rev

0A

of

5

4

3

2

1

U7F

CADOP[0..15]4

D D

CADON[0..15]4

C C

B B

1P2VPLL_PWR10,11

1P2VPLL_PWR

CADOP[0..15]

CADON[0..15]

CLKOP04

CLKON04

CLKOP14

CLKON14

CTLOP04
CTLON04

VCC1_2HT

R111 150/6/1

R108 150/6/1

X_30ohm/6/500mA

FB20

CP25

COPPER

PLACE ON BACK SIDE

1P2VPLL_FILT

1u/10V/6

C514

CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15

CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15

CTLOP0
CTLON0

C516

0.1u/25V/6

Y23

W24

V24
U22
R24
P24
P22
N22
Y21
V21

W21

T21
R18
P16
N20

M17

Y22

W23

V23
U21
R23
P23
P21
N21

Y20
W20
W22

U20

R19

P17

N19

N18

T23

T22

R21

R20

M23
M22

W19

Y19

N16

T13

HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P

HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N

HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N

HT_CPU_RXCTL_P
HT_CPU_RXCTL_N

HT_CPU_CAL_1P2V
HT_CPU_CAL_GND

+1.2V_PLLHTCPU

+1.2V_PLLHTMCP

?

?

C51PVG

SEC 1 OF 6

HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P

HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P

HT_CPU_TXD0_N

HT_CPU_TXD1_N

HT_CPU_TXD2_N

HT_CPU_TXD3_N

HT_CPU_TXD4_N

HT_CPU_TXD5_N

HT_CPU_TXD6_N

HT_CPU_TXD7_N

HT_CPU_TXD8_N

HT_CPU_TXD9_N

HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N

HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N

HT_CPU_TXCTL_P
HT_CPU_TXCTL_N

CLKOUT_PRI_200MHZ_P

CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N

HT_CPU_REQ*

HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD

+2.5V_PLLHTCPU

VCC2_5

C23
D23
E22
F23
H22
J21
K21
K23
D21
F19
F21
G20
J19
L17
L20
L18

C24
D24
E23
F24
H23
J22
K22
K24
D22
E20
E21
G19
J18
K17
K19
L19

G23
G24
G22
G21

L23
L24

B24
B23
A22
B21

F18
G18
D20
E19

L16

C249

4.7u/10/Y/8

CADIP0
CADIP1
CADIP2
CADIP3
CADIP4
CADIP5
CADIP6
CADIP7
CADIP8
CADIP9
CADIP10
CADIP11
CADIP12
CADIP13
CADIP14
CADIP15

CADIN0
CADIN1
CADIN2
CADIN3
CADIN4
CADIN5
CADIN6
CADIN7
CADIN8
CADIN9
CADIN10
CADIN11
CADIN12
CADIN13
CADIN14
CADIN15

CLKIP0
CLKIN0
CLKIP1
CLKIN1

CTLIP0
CTLIN0

-LDTSTOP

-LDT_RST
CPU_GD

2P5V_PLL

C510

0.1u/25V/6

CADIP[0..15]

CADIN[0..15]

CPUCLKO_H 4
CPUCLKO_L 4

-LDTSTOP 4

COPPER

CP16

X_30ohm/6/500mA

CADIN[0..15] 4

CLKIP0 4
CLKIN0 4
CLKIP1 4
CLKIN1 4

CTLIP0 4
CTLIN0 4

-LDT_RST 4
CPU_GD 4

FB22

C513

1u/10V/6

CADIP[0..15] 4

2P5V_PLL

C512

0.1u/25V/6

HTMCP_UP[7..0]12

HTMCP_UP#[7..0]12

2P5V_PLL 10

HTMCP_UP[7..0]

HTMCP_UP#[7..0]

HTMCP_UPCLK012

HTMCP_UPCLK0#12

HTMCP_UPCNTL12

HTMCP_UPCNTL#12

HTMCP_REQ#12

HTMCP_STOP#12

HTCP_RST#12

HTMCP_PWRGD12

MCPOUT_25MHZ12

MCPOUT_200MHZ12

MCPOUT_200MHZ#12

HTMCP_UP0
HTMCP_UP1
HTMCP_UP2
HTMCP_UP3
HTMCP_UP4
HTMCP_UP5
HTMCP_UP6
HTMCP_UP7

HTMCP_UP#0
HTMCP_UP#1
HTMCP_UP#2
HTMCP_UP#3
HTMCP_UP#4
HTMCP_UP#5
HTMCP_UP#6
HTMCP_UP#7

HTMCP_UPCLK0
HTMCP_UPCLK0#

HTMCP_UPCNTL
HTMCP_UPCNTL#

HTMCP_REQ#
HTMCP_STOP#
HTCP_RST#
HTMCP_PWRGD

MCPOUT_25MHZ

MCPOUT_200MHZ
MCPOUT_200MHZ#

AD10
AD11
AC12
AC13

AC10
AC11

AD14
AC14

AA11

AB12
AB13

AD6
AC7

AA8
AA9

AA6

Y10
V11

W12

AC6

AB7
AB8
AB9

AA7

W10

Y12

W11

V13

AD9
AC9

U10
T10

AB5

AA5
AC5
AD5

AC4

W7

Y8
V9

Y6
Y7

W9

Y5

W5

U7A

?

HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P

HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N

HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N

HT_MCP_RXCTL_P
HT_MCP_RXCTL_N

HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD

CLKIN_25MHZ

CLKIN_200MHZ_P
CLKIN_200MHZ_N

?

C51PVG

SEC 2 OF 6

SCLKIN_MCLKOUT_200MHZ_P

SCLKIN_MCLKOUT_200MHZ_N

HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P

HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P

HT_MCP_TXD0_N

HT_MCP_TXD1_N

HT_MCP_TXD2_N

HT_MCP_TXD3_N

HT_MCP_TXD4_N

HT_MCP_TXD5_N

HT_MCP_TXD6_N

HT_MCP_TXD7_N

HT_MCP_TXD8_N

HT_MCP_TXD9_N

HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N

HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N

HT_MCP_TXCTL_P
HT_MCP_TXCTL_N

CLKOUT_CTERM

HT_MCP_CAL_1P2V
HT_MCP_CAL_GND

AC24
AD23
AC22
AC20
AB18
AA17
AB16
AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13

AC23
AD22
AC21
AD20
AC18
AB17
AB15
AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13

AC19
AD19
Y17
W17

AC15
AD15

B22
A20

B20

AB23
AB24

HTMCP_DWN0
HTMCP_DWN1
HTMCP_DWN2
HTMCP_DWN3
HTMCP_DWN4
HTMCP_DWN5
HTMCP_DWN6
HTMCP_DWN7

HTMCP_DWN#0
HTMCP_DWN#1
HTMCP_DWN#2
HTMCP_DWN#3
HTMCP_DWN#4
HTMCP_DWN#5
HTMCP_DWN#6
HTMCP_DWN#7

HTMCP_DWNCLK0
HTMCP_DWNCLK0#

HTMCP_DWNCNTL
HTMCP_DWNCNTL#

UNNAMED_21_C51_I164_CLKOUTCTERM

HTMCP_DWN[7..0]

HTMCP_DWN#[7..0]

R120 2.37K/6/1

VCC1_2

R109 150/6/1

R110 150/6/1

HTMCP_DWN[7..0] 12

HTMCP_DWN#[7..0] 12

HTMCP_DWNCLK0 12
HTMCP_DWNCLK0# 12

HTMCP_DWNCNTL 12
HTMCP_DWNCNTL# 12

A A

5

4

PLACE ON BACK SIDE

Micro Star Restricted Secret

Title

Document Number

3

2

C51G-1/ HT CPU & MCP

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7303

1

Last Revision Date:

Monday, July 17, 2006

Sheet

Rev

0A

934

of

5

U7B

?

J8

PED_RX017
PED_RX117
PED_RX217
PED_RX317
PED_RX417
PED_RX517
PED_RX617
PED_RX717

VCC3

VCC3

VCC3

PED_RX817
PED_RX917
PED_RX1017
PED_RX1117
PED_RX1217
PED_RX1317
PED_RX1417
PED_RX1517

PED_RX0*17
PED_RX1*17
PED_RX2*17
PED_RX3*17
PED_RX4*17
PED_RX5*17
PED_RX6*17
PED_RX7*17
PED_RX8*17
PED_RX9*17
PED_RX10*17
PED_RX11*17
PED_RX12*17
PED_RX13*17
PED_RX14*17
PED_RX15*17

PC0_PRSNT#17

R154 10K/4

PE1_RX17
PE1_RX*17

PC1_PRSNT#17

R155 10K/4

R156 10K/4

PE1_RX
PE1_RX*

D D

C C

CP18 COPPER

1P2VPLL_PWR9,11

1P2VPLL_PWR

FB21 X_30ohm/6/500mA

J6

K9

L6

L7
M9
N8
N6
R6
P3
R8
U6

T8
U7
V4
Y3

J7

J5

J9

L5

L8
M8

N7

N5

R5

P4

R7

U5

T9

U8

V3

AA3

D1

G6

H6

E2

J4

K3

E3

D3

E4

AC3
AB3

T11

C730

0.1u/25V/6

PE0_RX0_P
PE0_RX1_P
PE0_RX2_P
PE0_RX3_P
PE0_RX4_P
PE0_RX5_P
PE0_RX6_P
PE0_RX7_P
PE0_RX8_P
PE0_RX9_P
PE0_RX10_P
PE0_RX11_P
PE0_RX12_P
PE0_RX13_P
PE0_RX14_P
PE0_RX15_P

PE0_RX0_N
PE0_RX1_N
PE0_RX2_N
PE0_RX3_N
PE0_RX4_N
PE0_RX5_N
PE0_RX6_N
PE0_RX7_N
PE0_RX8_N
PE0_RX9_N
PE0_RX10_N
PE0_RX11_N
PE0_RX12_N
PE0_RX13_N
PE0_RX14_N
PE0_RX15_N

PE0_PRSNT*

PE1_RX_P
PE1_RX_N

PE1_PRSNT*

PE2_RX_P
PE2_RX_N

PE2_PRSNT*

PE1_CLKREQ*/CLK
PE2_CLKREQ*/DATA

PE_REFCLKIN_P
PE_REFCLKIN_N

+1.2V_PLLPE

?

SEC 3 OF 6

C51PVG

PE0_TX0_P
PE0_TX1_P
PE0_TX2_P
PE0_TX3_P
PE0_TX4_P
PE0_TX5_P
PE0_TX6_P
PE0_TX7_P
PE0_TX8_P

PE0_TX9_P
PE0_TX10_P
PE0_TX11_P
PE0_TX12_P
PE0_TX13_P
PE0_TX14_P
PE0_TX15_P

PE0_TX0_N

PE0_TX1_N

PE0_TX2_N

PE0_TX3_N

PE0_TX4_N

PE0_TX5_N

PE0_TX6_N

PE0_TX7_N

PE0_TX8_N

PE0_TX9_N
PE0_TX10_N
PE0_TX11_N
PE0_TX12_N
PE0_TX13_N
PE0_TX14_N
PE0_TX15_N

PE0_REFCLK_P
PE0_REFCLK_N

PE1_TX_P
PE1_TX_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_TX_P
PE2_TX_N

PE2_REFCLK_P
PE2_REFCLK_N

PE_TSTCLK_P
PE_TSTCLK_N

PE_RST*

PE_CTERM_GND

4

L1
L3
L4
M4
P1
R1
R3
R4
U4
V1
W1
W3
AA1
AB1
AC1
AD2

L2
M2
M3
N3
P2
R2
T2
T3
U3
V2
W2
Y2
AA2
AB2
AC2
AD3

K1
K2

G4
G5

G2
G3

H4
J3

H2
H3

F1
F2

G1

D2

PE0_CLK
PE0_CLK*

PE1_TX
PE1_TX*

PE1_CLK
PE1_CLK*

PE_RST*

PE_COMP

PED_TX0 17
PED_TX1 17
PED_TX2 17
PED_TX3 17
PED_TX4 17
PED_TX5 17
PED_TX6 17
PED_TX7 17
PED_TX8 17
PED_TX9 17
PED_TX10 17
PED_TX11 17
PED_TX12 17
PED_TX13 17
PED_TX14 17
PED_TX15 17

PED_TX0* 17
PED_TX1* 17
PED_TX2* 17
PED_TX3* 17
PED_TX4* 17
PED_TX5* 17
PED_TX6* 17
PED_TX7* 17
PED_TX8* 17
PED_TX9* 17
PED_TX10* 17
PED_TX11* 17
PED_TX12* 17
PED_TX13* 17
PED_TX14* 17
PED_TX15* 17

PE0_CLK 17
PE0_CLK* 17

PE1_TX 17
PE1_TX* 17

PE1_CLK 17
PE1_CLK* 17

R157 X_100/6

PE_RST* 17

R153 2.37K/6/1

R29
G29
B29

3

R
G
B

R145

R142

150/6/1

150/6/1

PLACE NEAR C51

TV-OUT remove

1P2VPLL_PWR9,11

R148
150/6/1

1P2VPLL_PWR

Width = 12 milsWidth = 7 mils

HSYNC#29
VSYNC#29

R146 124/6/1

2P5V_PLL9

C299

0.1u/16V/4

HSYNC#
VSYNC#

C276

0.01u/16V/4

2P5V_PLL

C298

0.1u/16V/4

3P3V_DAC

R1071
X_0/4

2

U7C

?

A5

DAC_RED

B6

DAC_GREEN

A6

DAC_BLUE

B7

DAC_HSYNC

C7

DAC_VSYNC

D8

DAC_RSET

D9

DAC_VREF

C8

DAC_IDUMP

A9

+3.3V_DAC

H13

+2.5V_PLLGPU

C9

XTAL_IN

B9

XTAL_OUT

R9

+1.2V_PLLGPU

P9

+1.2V_PLLCORE

H16

+1.2V_PLLIFP

?

C51PVG

SEC 4 OF 6

IFPA_TXC_P

IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD1_P
IFPA_TXD2_P
IFPA_TXD3_P

IFPA_TXD0_N
IFPA_TXD1_N
IFPA_TXD2_N
IFPA_TXD3_N

IFPB_TXC_P

IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD5_P
IFPB_TXD6_P
IFPB_TXD7_P

IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_N

IFPAB_PROBE

IFPAB_RSET

+2.5V_PLLIFP

+2.5V_PLLCORE

PKG_TEST

TEST_MODE_EN

JTAG_TCK

JTAG_TDI
JTAG_TDO
JTAG_TMS

JTAG_TRST*

C14
B13

A15
D15
A14

DVI remove

F14
B15

C15
B14
E14

A10
B10

B11
E13
D13
B12

A11
F13
C13
C12

IFPAB_PROBE

A16

IFPAB_RSET

F15

2P5V_PLL

E16

2P5V_PLL

H12

D17
C17

JTAG_TCK

C18

JTAG_TDI

B19
C19

JTAG_TMS

B18

JTAG_TRST*

A19

R129 1K/6

2P5V_PLL 9

R128 1K/6

R127 X_10K/4

R126 X_10K/4

X_0.1u/16V/4C261

R121 X_10K/4

1

R125 X_10K/4

VCC2_5

B B

A A

PLACE ON BACK SIDE

5

VCC3

4A ?

FB10 X_40S

COPPER

CP5

4

3

C272

4.7u/10/Y/8

3P3V_DAC

C273

0.1u/16V/4

2

Micro Star Restricted Secret

Title

Document Number

C51G-2 / PCI-E & DAC

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7303

1

Last Revision Date:

Monday, July 17, 2006

Sheet

10 34

Rev

0A

of

A

B

C

D

E

C51 DECOUPLING

PLACE ON BACK SIDE
CENTER OF C51

4 4

VCC1_2 VCC1_2

3 3

VCC1_2HT

VCC3

AB11
AA18

W16

E10
F10
F11
G11
H11

T15
U13
U11

U16
U15

K16
M16
R16
M21

T16
U17
C21
H17

D18
C10

U7E

C51PVG

B5

+1.2V_CORE

C6

+1.2V_CORE

D7

+1.2V_CORE

E8

+1.2V_CORE

E9

+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE

J11

+1.2V_CORE

J12

+1.2V_CORE

J13

+1.2V_CORE

J14

+1.2V_CORE

+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP

Y9

+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP

B4

+1.2V_PED

C5

+1.2V_PED

D6

+1.2V_PED

E7

+1.2V_PED

+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT

J20

+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT

+3.3V
+3.3V

?

SEC 5 OF 6

+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA

+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL

+2.5V_CORE
+2.5V_CORE

+2.5V_IFPA
+2.5V_IFPB

A3
B3
C4
D5
E6
F7
F8
F9

VCC1_2

FB11

X_30ohm_3000mA

A2
B2
C2
C3
D4
E5
F6
G7
G8
G9
H10
J10

VCC2_5

C16
B16

G15
H15

2_5_IFPA

C517

0.1u/25V/6

CP6
COPPER

1P2VPEA_PWR

1P2VPLL_PWR

C267

4.7u/10/Y/8
COPPER

1P2VPLL_PWR 9,10

VCC2_5

FB9

X_30ohm/6/500mA

CP4

1P2VPLL_PWR9,10

3.3V FOR TMDS

VCC1_2

VCC1_2

1P2VPEA_PWR

1u/10V/6C526 10u/10V/8C291

1u/10V/6C523

10u/10V/8C275

1P2VPLL_PWR

4.7u/10/Y/8C301

4.7u/10/Y/8C300

1u/10V/6C295

10u/10V/8C284

0.1u/25V/6C527

0.1u/16V/4C264

0.1u/25V/6C518

0.1u/25V/6C525

0.1u/25V/6C529

0.1u/16V/4C271

0.1u/25V/6C524

0.1u/25V/6C519 0.1u/16V/4C248

0.1u/25V/6C528

0.1u/16V/4C293

0.1u/25V/6C530

0.1u/16V/4C287

0.1u/25V/6C522

0.1u/16V/4C255 0.1u/16V/4C286

0.1u/25V/6C521

10u/10V/8C940

C563
X_0.1u/25V/6

VCC1_2

PLACE ON BACK SIDE
MCPHT CORE BALLS

0.1u/25V/6C515

0.1u/25V/6C509

VCC3 VCC2_5VDDA_25

C341

0.1u/16V/4

C568
X_33P/50V/6

2 2

VCC1_2HT

C567 X_0.1u/25V/6

B1

E11

L12

P14

N14

M14

P13

N13

M13

P12

N12

M12

P11

N11

M11

L11

AA24

AA23

A23

AA22

V22

R22

L22

F22

AB6

C22

H21

Y16

G13

U12

AB14

R17

C20

T14

V19

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

C51PVG

SEC 6 OF 6

?

U7D

1 1

GNDC1GND

AA21

GND

AA13

GND

GND

GND

GND

GND

E12

C11

U14

AA4

AB4

A

GND

GND

GND

GND

GND

GND

GND

F12

E15

E18

Y18

U18

D11

AB10

GND

GND

GND

GND

GND

GND

GND

J17

F16

E17

Y11

N17

U19

G17

GND

GND

GND

GND

GND

GND

GND

J16

L21

T12

F17

T17

H19

D19

GND

GND

GND

GND

GND

GND

GND

J15

L13

L14

T19

P19

H14

M19

B

V8

PE_GNDF4PE_GNDV6PE_GNDK8PE_GNDH8PE_GNDW8PE_GNDW6PE_GNDT6PE_GNDP6PE_GNDM6PE_GNDK6PE_GND

?

PE_GNDU9PE_GNDY4PE_GNDW4PE_GNDT4PE_GNDN4PE_GNDK4PE_GNDN9PE_GNDP8PE_GNDL9PE_GNDF3PE_GND

33P/50V/6C511

0.1u/25V/6C508

0.1u/16V/4C244

0.1u/16V/4C245

33P/50V/6C566

H9

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

C

D

http://www.msi.com.tw

C51G-3/PWR/GND

MS-7303

Last Revision Date:
Sheet

E

Monday, July 17, 2006

11 34

Rev

0A

of