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MS-7302
Schematic RS780
34 pgs1.36 Mb0

MSI MS-7302 Schematic RS780

5
4
3
2
1
MSI
D D
MS-7302 Ver:0A
CPU:
AMD M2 Athlon 64/Athlon 64 FX AM2R2
System Chipset:
AMD/ATI RS780 colay RS740 AMD/ATI SB700
On Board Chipset:
FINTEK Super I/O -- F71882 LAN -- RTL8111C(B)/RTL8101E HD Codec -- ALC888 BIOS -- SPI ROM 8M
C C
1394 -- JMB381
Main Memory:
DDR II X 2 (Max 4GB)
Expansion Slots:
PCI-E X 1 *1 PCI-E X 16 *1
PCI 2.2 Slot X 2
Clock Generator:
Controller--ICS9LPRS477
B B
PWM:
INTSIL6566 3 Phase+75125
Title Page
Cover Sheet 1
GPIO Configuration Clock Distribution 4 Power Deliver Chart INTSIL6566 3 Phase+75125 Clock-Gen ICS9LPRS477 AMD AMr2 940 FIRST LOGICAL DDR DIMM
DDR Terminatior
AMD/ATI RS780 COLAY RS740
AMD/ATI SB700 PCI EXPRESS X16 & X 1 SLOT PCI Slot 1,2 USB connectors VGA CONN / TVOUT LAN - Realtek 8111C(B)/8101E
Azalia Codec-ALC888 1394 Controller - JMB381 LPC-F71882 / FDD / COM / LPT IDE Conn / FAN VCC_DDR&VCC1_1 NB ACPI by UPI ATX/Front Panel/KB/EMI BOM - Option Parts POWER OK MAP RESET MAP History
2Block Diagram 3
5 6 7
8, 9,10
11 12
13, 14,15,16,17
18, 19,20,21,22
23 24 25 26 27
28 29 30 31 32
33 34 35 36 37 38
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Document Number
Document Number
Document Number
5
4
3
2
Cover Sheet
Cover Sheet
Cover Sheet
MS-7501
MS-7501
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
MS-7501
1
Last Revision Date:
Last Revision Date:
Last Revision Date: Sheet
Sheet
Sheet
Tuesday, October 23, 2007
Tuesday, October 23, 2007
Tuesday, October 23, 2007
138
138
138
Rev
Rev
Rev
0A
0A
0A
5
4
3
2
1
Project RS-780 BLOCK DIAGRAM
DDRII 400,533,667,800
D D
DVI CON
PCIE GFX x16
C C
4X1 PCIE INTERFACE
TMDS
22
PCIE x16
31
AMD AM2/AM2g2
AM2 SOCKET
OUT
ATI NB - RS780
HyperTransport LINK0 CPU I/F 1 16X PCIE VIDEO I/F 1 4X PCIE I/F WITH SB 2 1X PCIE I/F
7,8,9
16x16 2.6GHZ(HT3)HyperTransport LINK
IN
128bit
DDRII 400,533,667,800
128bit
UNBUFFERED DDRII DIMM1
UNBUFFERED DDRII DIMM2
DDRII FIRST LOGICAL DIMM DDRII SECOND LOGICAL DIMM
10
10
UNBUFFERED DDRII DIMM3
UNBUFFERED DDRII DIMM4
11
11
13,14,15,16
Realtek 8111C(B)/8101E
USB-4USB-5
30
USB-11 HDR
B B
30 30 30 30 30
USB-10 HDR
HDR HDR HDR HDR
USB-1USB-2USB-3
USB-7USB-8USB-9
PCIE x1 SLOT1
USB-0 REARREARREARREARREARREAR
USB-6
303030303030
3125
USB 2.0
A-LINK
4X PCIE
ATI SB - SB700
USB2.0 (12) SATA2 (4 PORTS) AC97 2.3 HD AUDIO 1.0 ACPI 1.1 SPI I/F PCI/PCI BRIDGE
AZALIA
SERIAL ATA 2.0
HD AUDIO HDR
AZALIA CODEC
SATA#0 SATA#1
29
29
24
24 24 24
SATA#2 SATA#3
PCI BUS
SPI Bus
ITE SIO
17,18,19,20,21
Fintek 71882
26
LPC BUS
TPM Pin Header
30
PCI SLOT 2
30
CPU CORE POWER
ACPI CONTROLLER
uPI
A A
27
NB CORE POWER Intersil ISL6323 Intersil ISL6612A
CPU VLDT Power
RS780 CORE POWER
PCIE & SB POWER
DDR2 DRAM POWER
6
27
27
PCI SLOT 1
SPI ROM 8M
33
19
ATX CON & DUAL POWER
5
27
4
FLOPPY
LPT
22
23
3
KBD MOUSE
22 23
SERIAL PORT
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK Diagram
BLOCK Diagram
BLOCK Diagram
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7501 0A
MS-7501 0A
MS-7501 0A
1
of
of
of
238Tuesday, October 23, 2007
238Tuesday, October 23, 2007
238Tuesday, October 23, 2007
5
D D
C C
4
3
2
1
B B
PCI Config.
DEVICE MCP1 INT Pin REQ#/GNT#
PCI Slot 1
PCI Slot 2
A A
5
4
PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTB# PCI_INTC# PCI_INTD# PCI_INTA#
PREQ#0 PGNT#0
PREQ#1 PGNT#1
IDSEL
AD16
AD17
3
CLOCK
PCICLK0
PCICLK1
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
MICRO-START INT'L CO.,LTD.
GPIO Configuration
GPIO Configuration
GPIO Configuration
MS-7501 0A
MS-7501 0A
MS-7501 0A
1
338Tuesday, October 23, 2007
338Tuesday, October 23, 2007
338Tuesday, October 23, 2007
5
4
3
2
1
D D
DIMM1 DIMM2
3 PAIR MEM CLK
3 PAIR MEM CLK
3 PAIR MEM CLK
3 PAIR MEM CLK
AM2/AM2g2 CPU AM2 SOCKET
C C
B B
1 PAIR CPU CLK
200MHZ
HT REFCLK
100MHz DIFF RS780
EXTERNAL CLK GEN.
NB-OSCIN
14.318MHZ
NB ALINK PCIE CLK
100MHZ
SB ALINK PCIE CLK
100MHZ
NB GFX PCIE CLK
100MHZ
NB GPP PCIE CLK
100MHZ
PCIE GFX CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
PCIE GPP CLK
100MHZ
USB CLK
48MHZ
SIO CLK
48MHZ
AMD/ATI NB RS780
(RX780)
PCIE GFX SLOT 1 - 16 LANES
PCIE GPP SLOT 1 - 1 LANE
PCIE GPP SLOT 2 - 4 LANES
PCIE GBE
25MHZ OSC INPUT
25MHz LAN
25MHz SATA
CPU_HT_CLK
NB_HT_CLK
25M_48M_66M_OSC
AMD/ATI SB
SB700
NB_DISP_CLK
GPP_CLK3
PCIE_RCLK/ NB_LNK_CLK
SLT_GFX_CLK
GPP_CLK0
GPP_CLK1
GPP_CLK2
USB_CLK
PCI CLK0
33MHZ
PCI CLK1
33MHZ
PCI CLK2
33MHZ
PCI CLK3
33MHZ
PCI CLK4
33MHZ
PCI CLK5
33MHZ
LPC_CLK0
33MHZ
LPC CLK1
33MHZ
SB_BITCLK
48MHZ
32.768KHz
PCI SLOT 0 33MHz
PCI SLOT 1 33MHz
IEEE1394 33MHz
SUPER IO IT8718F 33MHz
TPM 33MHz
LEO CHIP 33MHz
HD AUDIO ALC 662/883
25MHz
DIMM3 DIMM4
14.31818MHz
A A
5
External clock mode
Internal clock mode
4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Clock Distribution
Clock Distribution
Clock Distribution
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7501
MS-7501
MS-7501
438Tuesday, October 23, 2007
438Tuesday, October 23, 2007
438Tuesday, October 23, 2007
1
0A
0A
0A
of
of
of
5
Power Deliver Chart
4
3
2
1
2.5V Shunt Regulator
VRM SW REGUALTOR
D D
ATX P/S WITH 1A STBY CURRENT
5V
5VSB
+/-5%
+/-5%
3.3V +/-5%
12V +/-5%
-12V +/-5%
CPU PW 12V +/-5%
5VDIMM Linear REGULATOR
1.8V VDD SW REGULATOR
1.8V VCC Linear REGULATOR
VDDA25 (S0, S1)
VCCP (S0, S1) / VCC_NB (S0, S1)
0.9V VTT_DDR REGULATOR
1.1V VCC Linear REGULATOR
1.2V VCC Linear REGULATOR
VCC_DDR (S0, S1, S3) VTT_DDR (S0, S1, S3)
DDRII DIMMX4
VDD MEM
12A
VTT_DDR
2A
NB_VCC1P1 (S0, S1)
VCC_1V2 (S0, S1)
+1.8V_S0 (S0, S1)
C C
AMD AM2r2 CPU
VDDA 2.5V 0.2A VDDCORE
0.8-1.55V
DDR2 MEM I/F VDD MEM 1.8V VTT MEM 0.9V
VLDT 1.2V
NB RS780
VDDHT/RX 1.1V VDDHTTX 1.2V VDDPCIE 1.1V NB CORE VDDC
1.1V VDDA18PCIE 1.8V
PLLs 1.8V VDD18/VDD18_MEM
1.8V VDD_MEM 1.8V/1.5V
AVDD 3.3V
110A
10A 2A
0.5A
1.2A
0.5A 2A 7A
0.9A
0.1A
0.01A
0.5A
0.135A
SB700
VCC3_SB Linear REGULATOR
VCC3_SB (S0, S1, S3, S5)
1.2V_SB Linear REGULATOR
+1.2VSB (S0, S1) VCC3_SB (S0, S1, S3, S5)
VCC3 (S0, S1)
+5VA Linear
B B
5VDUAL Linear REGULATOR
REGULATOR
+5VA (S0, S1)
VCC3_SB (S0, S1, S3, S5)
X4 PCI-E
ATA I/O
ATA PLL
PCI-E PVDD
SB CORE
CLOCK
1.2V S5 PW
3.3V S5 PW
USB CORE I/O
3.3V I/O
+3.3VDUAL (S3)
+3.3V (S0, S1)
+5V (S0, S1)
AUDIO CODEC
3.3V CORE
5V ANALOG
SUPER I/O
0.8A
0.5A
0.01A 80mA
0.6A
0.22A
0.01A
0.2A
0.45A
0.1A
0.1A
0.01A
0.01A
0.1A
PCI Slot (per slot)
A A
5
5V
3.3V 12V
3.3VDual
-12V
5.0A
7.6A
0.5A
0.375A
0.1A
X1 PCIE per
3.3V 12V
3.3Vaux
3.0A
0.5A
0.1A
4
X16 PCIE per
3.3V 12V
3.3VDual
3.0A
5.5A
0.1A
USB X6 FR
VDD 5VDual
3.0A
USB X6 RL 2XPS/2
VDD 5VDual
3.0A
3
5VDual
0.5A
ENTHENET
3.3V (S3)
3.3V (S0, S1)
0.1A
0.5A
IEEE-1394 x1
3.3V (S0, S1)
0.1A
12V (S0, S1) 1.1A
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
C
C
C
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
MICRO-START INT'L CO.,LTD.
Power Deliver Chart
Power Deliver Chart
Power Deliver Chart
MS-7501 0A
MS-7501 0A
MS-7501 0A
1
538Tuesday, October 23, 2007
538Tuesday, October 23, 2007
538Tuesday, October 23, 2007
5
+12VIN
PWR1
PWR1
PWRCONN4P_CREAM-RH-1
PWRCONN4P_CREAM-RH-1
12V
12V
4
3
C229
C229
X_C0.01u25X0402
D D
X_C0.01u25X0402
2
12V
12V
GNDGND
GNDGND
1
X_C0.01u25X0402
X_C0.01u25X0402
5
+12VIN
CHOKE6
CHOKE6
1 2
C231
C231
CH-1.2u18A3m-RH
CH-1.2u18A3m-RH
CD1000u16EL20-RH-3
CD1000u16EL20-RH-3
VCCPVCC5_SBVCC3
R61
R61
4.7KR0402
4.7KR0402
R33 X_0R0402R33 X_0R0402
652 1 3 4
Q10
Q10
NN-CMKT3904_SOT363-6-RH
NN-CMKT3904_SOT363-6-RH
VCORE_VLD33
C C
VR_EN
VRM_EN
C25
C25
C0.1u25Y
C0.1u25Y
R19
R19
5.1KR1%0402
5.1KR1%0402
C14 C220p50N0402C14 C220p50N0402
R29 1KR0402R29 1KR0402
R36
R36
VCCP
51R0402
51R0402
COREFB_L8
B B
R32
R32
51R0402
51R0402
VCC5
R14 130KR1%0402-RHR14 130KR1%0402-RH
COREFB+
C26
C26
X_C0.01u25X0402
X_C0.01u25X0402
X_C0.01u25X0402
X_C0.01u25X0402
R30
R30
X_63.4KR1%0402
X_63.4KR1%0402
C10
C10
C680p50X0402
C680p50X0402
C19
C19
R39 1.5KR1%0402R39 1.5KR1%0402
A A
5
C29 C0.047u16Y0402C29 C0.047u16Y0402 R47 9.1KR1%0402R47 9.1KR1%0402
R78
R78
10KR0402
10KR0402
R62
R62
4.7KR0402
4.7KR0402
VRM_GD
C15
C15
C4700p16X0402
C4700p16X0402
R28
R28
750R1%0402
750R1%0402
C24
C24
X_C0.01u25X0402
X_C0.01u25X0402
R43 120KR1%0402R43 120KR1%0402
R53
R53
1KR0402
1KR0402
VRM_GD
C37
C37
C0.1u25Y
C0.1u25Y
U4
U4
VRVID4 VRVID3 VRVID2 VRVID1 VRVID0
COMP
COMP
FB
VDIFF
COREFB-
OFS
FS REF
C16
C16
C0.01u25X0402
C0.01u25X0402
VCCP
R38 12KR0402R38 12KR0402 R45 12KR0402R45 12KR0402 R52 12KR0402R52 12KR0402
38
VID4
39
VID3
40
VID2
1
VID1
2
VID0
3
VID12.5
35
PGOOD
37
ENLL
8
COMP
9
FB
10
VDIFF
12
VSEN
11
RGND
6
OFS
36
FS
5
REF
4
VRM10
13
OCSET
14
ICOMP
15
ISUM
16
IREF
C34
C34
C0.01u25X0402
C0.01u25X0402
4
CD1000u16EL20-RH-3
CD1000u16EL20-RH-3
+
+
+
+
12
12
EC13
EC13
EC22
EC22
CD1000u16EL20-RH-3
CD1000u16EL20-RH-3
VCC5
D3
D3
S-SM5817A[SN]_DO214AC
S-SM5817A[SN]_DO214AC
PWM_VCC5
7
VCC
GND
ISL6566CRZ_QFN40
ISL6566CRZ_QFN40
41
BOTTOM PAD CONNECT TO GND THROUGH 10 vias
PHASE1 PHASE2 PHASE3
4
PVCC1 BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
PVCC2 BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PVCC3 BOOT3
UGATE3
PHASE3
ISEN3
LGATE3
+
+
12
EC16
EC16
VCORE_EN#33
+
+
12
CD1000u16EL20-RH-3
CD1000u16EL20-RH-3
C11
C11
C1u16Y0805
C1u16Y0805
12VP1
33
BOOT1
30
U_G1
31
PHASE1
29
IS1
32
L_G1
34
12VP2
24
BOOT2
26
U_G2
27
PHASE2
28
IS2
25
L_G2
23
12VP3
18
BOOT3
21
U_G3
20
PHASE3
22
IS3
19
L_G3
17
EC7
EC7
10KR0402
10KR0402
R77
R77
2.2R0805
2.2R0805
R68
R68
2.8KR1%0402
2.8KR1%0402
R76
R76
2.2R0805
2.2R0805
R72
R72
2.8KR1%0402
2.8KR1%0402
R74
R74
2.2R0805
2.2R0805
R65
R65
VIN
C213
C213
C0.1u16Y0402
C0.1u16Y0402
VCC5_SB
R20
R20
2.8KR1%0402
2.8KR1%0402
C55
C55
C0.1u25Y
C0.1u25Y
C54
C54
C0.1u25Y
C0.1u25Y
C53
C53
C0.1u25Y
C0.1u25Y
R21
R21
10KR0402
10KR0402
+12VIN
VCORE_EN#R
+12VIN
+12VIN
R51
R51
2.2R0805
2.2R0805
C39
C39
C1u16Y0805
C1u16Y0805
R75
R75
2.2R0805
2.2R0805
C56
C56
C1u16Y0805
C1u16Y0805
R66
R66
2.2R0805
2.2R0805
C38
C38
C1u16Y0805
C1u16Y0805
VRM_EN
B
U_G3
L_G3
R14810KR0402R14810KR0402
R130X_10KR0402R130X_10KR0402
VCCP
3
U_G1
R107
R107
PHASE1
+12VIN
R7 10KR1%0402R710KR1%0402
C9 C0.1u16X0402-2C9 C0.1u16X0402-2 R10 3.6KR1%R10 3.6KR1%
CE
Q1
Q1 N-2N3904_SOT23
N-2N3904_SOT23
R149 1R0805R149 1R0805
PHASE3
EC20
EC20
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC8
EC8
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC9
EC9
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC19
EC19
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC14
EC14
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC15
EC15
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC6
EC6
+
+
1 2
CD1800u6.3EL20-RH-3
CD1800u6.3EL20-RH-3
EC5
EC5
+
+
1 2
X_CD1800u6.3EL20-RH-3
X_CD1800u6.3EL20-RH-3
3
10KR0402
10KR0402
L_G1
R91
R91
X_10KR0402
X_10KR0402
R108
R108
UG3
1R0805
1R0805
Q27
Q27
D
D
G
G
S
S
N-P0903BD_TO252
N-P0903BD_TO252
GND
G
G
GND
UG1
Q29
Q29
D
D
S
S
N-P0903BD_TO252
N-P0903BD_TO252
Q14
Q14
D
D
G
G
S
S
N-P0903BD_TO252
N-P0903BD_TO252
GND
G
G
GND GND
Q31N-P0903BD_TO252
Q31N-P0903BD_TO252
D
D
G
G
S
S
GND
G
G
Q18
Q18
D
D
S
S
N-P0903BD_TO252
N-P0903BD_TO252
C190
C190
C1u16Y
C1u16Y
CHOKE5
CHOKE5
1 2
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
R131
R131
2.2R0805
2.2R0805
C165
C165
C1000p50X0402
C1000p50X0402
Q22
Q22
D
D
S
S
N-P0903BD_TO252
N-P0903BD_TO252
R92
R92
2.2R0805
2.2R0805
C81
C81
C1000p50X0402
C1000p50X0402
VIN
C182
C182
X_C10u16Y1206
X_C10u16Y1206
VCCP
GND
LDT_PWRGD8,18
VIN
C86
C86
C1u16Y
C1u16Y
GND
VCCA_1V2
CPUVID[0..4]8
SCL07,11,20
SDA07,11,20
CPU_CORE_TYPE8
SLOTOCC#
VRVID4
VRVID0 VRVID1 VRVID2 VRVID3
X_8P4R-680R0402-RH
X_8P4R-680R0402-RH
CPUVID3 CPUVID2 CPUVID1
2
C85
C85
X_C10u16Y1206
X_C10u16Y1206
CHOKE2
CHOKE2
1 2
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
3VDUAL
R27 X_4.7KR0402R27 X_4.7KR0402
R40 X_4.7KR0402R40 X_4.7KR0402
B
B
C21
C21
X_C0.1u25Y
X_C0.1u25Y
VCC3
R9
X_4.7KR0402R9X_4.7KR0402
B
B
Q3X_N-MMBT3904_NL_SOT23
Q3X_N-MMBT3904_NL_SOT23
C
C
E
E
R15 0RR15 0R
R35 X_4.7KR0402R35 X_4.7KR0402
SLOTOCC#10
R49 0R0402R49 0R0402 R56 0R0402R56 0R0402
CPUVID1
R44 X_4.7KR0402R44 X_4.7KR0402
R16 X_680R0402-RHR16 X_680R0402-RH
RN1
RN1
1
2
3
4
5
6
7
8
VCC_DDR
RN3
RN3
1
2
3
4
5
6
7
8
8P4R-330R0402
8P4R-330R0402
2
VCCP
R31
R31
47.5R1%
47.5R1%
GND
Q5
Q5
C
C
E
E
X_N-MMBT3904_NL_SOT23
X_N-MMBT3904_NL_SOT23
CPUVID4 CPUVID3 CPUVID2CPUVID2 CPUVID1 CPUVID0
VR_DIS_IN
R42 0RR42 0R
R24 0R0402R24 0R0402
R18 X_300R0402R18 X_300R0402
3VDUAL
VCC3
U_G2
R119 1R0805R119 1R0805
R11810KR0402 R11810KR0402
PHASE2
L_G2
R112 X_10KR0402R112 X_10KR0402
SLP_S3#20,30,33
U3
U3
10
VID_IN[4]
11
VID_IN[3]/SVC
12
VID_IN[2]/SVD
13
VID_IN[1]
14
VID_IN[0]
22
VR_DIS_IN
21
CPU_PG_IN
7
VFIXEN
23
SLOTOCC#
24
SCL
25
SDA
9
CORE_TYPE
1
CPU_VDD_RUN
VIN
C121
C121
C1u16Y
C1u16Y
Q26
Q26
D
UG2
D
D
G
G
S
S
GND
D
D
G
G
S
S
R12
R12
X_0R0402
X_0R0402
VID_OUT[4] VID_OUT[3] VID_OUT[2] VID_OUT[1] VID_OUT[0]
VREF_NB
VCC_DDR
COREFB_H8
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
D
N-P0903BD_TO252
N-P0903BD_TO252
G
G
S
S
Q23
Q23
N-P0903BD_TO252
N-P0903BD_TO252
D
D
G
G
S
S
GND
VR_DIS_IN
Q6
Q6
X_N-2N7002_SOT23
X_N-2N7002_SOT23
VR_EN
NB_EN#
VSI_1
VSO_1
VSI_2
VSO_2
3VSB VDDA
GND
X_F75125RG-RH
X_F75125RG-RH
Q25
Q25
N-P0903BD_TO252
N-P0903BD_TO252
GND
VRVID4 VRVID3 VRVID2 VRVID1 VRVID0
19 18 17 16 15
VR_EN
20
5 3
1
R54 X_0R0402R54 X_0R0402
2
28 27
4 8 6 26
C30
C30
X_C0.1u25Y
X_C0.1u25Y
R113
R113
2.2R0805
2.2R0805
C1000p50X0402
C1000p50X0402
C104
C104
VRVID4 VRVID3 VRVID2 VRVID1 VRVID0
R59 X_0R0402R59 X_0R0402
COREFB_H
COREFB+
C18
C18
X_C0.1u25Y
X_C0.1u25Y
R57 0R0402R57 0R0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
STL6740 3+1PHASE
STL6740 3+1PHASE
STL6740 3+1PHASE
MS-7509 0A
MS-7509 0A
MS-7509 0A
1
GND
R17 0R0402R17 0R0402 RN2
RN2
1 3 5 7
8P4R-0R0402
8P4R-0R0402
C27
C27
X_C0.1u25Y
X_C0.1u25Y
1 2
2 4 6 8
3VDUAL VCC_DDR VDDA25
C114
C114
X_C10u16Y1206
X_C10u16Y1206
CHOKE4
CHOKE4
CH-0.25u40A0.65m-RH
CH-0.25u40A0.65m-RH
CPUVID4 CPUVID3 CPUVID2 CPUVID1 CPUVID0
COREFB+COREFB_H
638Wednesday, November 07, 2007
638Wednesday, November 07, 2007
638Wednesday, November 07, 2007
of
of
of
VCCP
VCC3
X_Copper
X_Copper
5
CLK_VDD
CP9
CP9
4
3
2
1
L20 X_30L3A-15_0805-RHL20 X_30L3A-15_0805-RH
D D
C C
CLK_VDD
FP_RST#20,30,33,34
SCL06,11,20
SDA06,11,20
CLK_VDD
B B
RS740
3.3V 33R serial
1.8V 75R/100R
RX780
RS780
NB_OSC_14M15
R234
R234
75R1%0402
75R1%0402
C10u10Y0805
C10u10Y0805
VCC3
CLK_VDD
VCC3
NB_OSC_14MNB
1.1V 150R/75R
C384
C384
CP6 X_CopperCP6 X_Copper
L18
L18
X_30L3A-15_0805-RH
X_30L3A-15_0805-RH
C314
C314
C22p50N
C22p50N
C346
C346
C22p50N
C22p50N
X_10KR0402
X_10KR0402
C332
C332
X_C10p50N0402
X_C10p50N0402
Reserved for EMI 0906
REF0/SEL_HTT66 HTT CLOCK
0
A A
1
100.00 DIFFERENTIAL
66.66 SINGLE END
5
C343
C343 C0.1u16X0402-2
C0.1u16X0402-2
CP3 X_CopperCP3 X_Copper
L15
L15
X_30L3A-15_0805-RH
X_30L3A-15_0805-RH
C368
C368
C1u6.3Y0402-RH
C1u6.3Y0402-RH
14.318MHZ16P_D-RH
14.318MHZ16P_D-RH
Y2
Y2
1 2
R213 X_4.7KR0402R213 X_4.7KR0402 R212 0R0402R212 0R0402 R282 0R0402R282 0R0402 R283 0R0402R283 0R0402
R216 1KR0402R216 1KR0402
R245
R245
R259
R259
X_10KR0402
X_10KR0402
R249
R249
150R1%0402
150R1%0402
R268
R268
10KR0402
10KR0402
C377
C378
C378 X_C0.1u16X0402-2
X_C0.1u16X0402-2
1- PLACE ALL THE SERIES TERMINATION RESISTORS AS CLOSE AS U41 AS POSSIBLE
C377 C0.1u16X0402-2
C0.1u16X0402-2
2- ROUTE ALL CPUCLK/#, NBSRCCLK/#, GPPCLK/# AS DIFFERENT PAIR RULE 3- PUT DECOUPLING CAPS CLOSE TO U41
POWER PIN
CLK_VDDA
C312
C312
C309
C309
C0.1u16X0402-2
R252
R252 X_10KR0402
X_10KR0402
SEL_HTT66
SEL_SATA
SEL_OC_MODE
R257
R257 10KR0402
10KR0402
C0.1u16X0402-2
TXC1 TXC2
RST#_CLK
PD#
X_C10u10Y0805
X_C10u10Y0805
VDD48
R226
R226 X_1MR
X_1MR
CLK_VDD
EXT CLK FREQUENCY SELECT TABLE(MHZ)
FS2
0 0 0 0 0 1
0 1 0 0 1 1 1 0 0 1 0 1 1 1 1
CPUFS1
Hi-Z X
180.00
220.00
100.00
133.33
200.00
4
SRCCLK
C310
C310 X_C0.1u16X0402-2
X_C0.1u16X0402-2
U18A
U18A
44
VDDA
43
GNDA
60
VDDREF
61
GNDREF
39
VDDSATA
42
GNDSATA
64
VDD48
3
GND48
48
VDDCPU
47
GNDCPU
56
VDDHTT
53
GNDHTT
34
VDDATIG
11
VDDSRC
16
VDDSRC
25
VDDSB_SRC
28
GNDATIG
33
GNDATIG
10
GNDSRC
17
GNDSRC
24
GNDSB_SRC
62
X1
63
X2
52
RESTORE#
4
SMBCLK
5
SMBDAT
51
PD#
59
REF0/SEL_HTT66
58
REF1/SEL_SATA
57
REF2/SEL_OC_MODE**
[2:1]
CPUKG1T_LPRS/SRC7T_LPRS
CPUKG1C_LPRS/SRC7C_LPRS
ICS9LPRS477BKLFT_MLF64-RH
ICS9LPRS477BKLFT_MLF64-RH
HTTFS0 PCI
Hi-Z Hi-Z100.00 Reserved
100.00
100.00
100.00
36.56 73.12
100.00
66.66 33.33
100.00
66.66 33.33
100.00
66.66 33.33 Normal HAMMER operation
C313
C313 X_C0.1u16X0402-2
X_C0.1u16X0402-2
CPUKG0T_LPRS CPUKG0C_LPRS
ATIG0T_LPRS ATIG0C_LPRS ATIG1T_LPRS ATIG1C_LPRS ATIG2T_LPRS ATIG2C_LPRS ATIG3T_LPRS ATIG3C_LPRS
SB_SRC0T_LPRS SB_SRC0C_LPRS SB_SRC1T_LPRS SB_SRC1C_LPRS
SRC0T_LPRS
SRC0C_LPRS
SRC1T_LPRS
SRC1C_LPRS
SRC2T_LPRS
SRC2C_LPRS
SRC3T_LPRS
SRC3C_LPRS
SRC4T_LPRS
SRC4C_LPRS **DOC_1/SRC5T_LPRS **DOC_0/SRC5C_LPRS
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
HTT0T_LPRS/66M
HTT0C_LPRS/66M
**SEL_CPU1#/48MHz_0
**SEL_DOC/48MHz_1
USB
48.00
48.00
X/6X/3
30.0060.00
48.00
48.00
48.00
48.00
48.00
50 49 46 45
38 37 36 35 32 31 30 29
27 26 23 22
21 20 19 18 15 14 13 12 9 8 7 6 41 40
55 54
2 1
COMMENT
Reserved Reserved Reserved Reserved Reserved
C311
C311 X_C0.1u16X0402-2
X_C0.1u16X0402-2
CPU_CLK_R CPU_CLK#_R
NBGFX_SRCCLK_R NBGFX_SRCCLK#_R GFX_CLKP_R GFX_CLKN_R
GPPCLK0_R GPPCLK0#_R 1394CLK2_R 1394CLK2#_R LANCLK1_R LANCLK1#_R NBLINKCLK_R NBLINKCLK#_R DOC1# DOC0# SBSRCCLK_R SBSRCCLK#_R
HTREFCLK_R HTREFCLK#_R
SIO_CLK_R USBCLK_EXT_R
3
C341
C341 X_C0.1u16X0402-2
X_C0.1u16X0402-2
Reserved for EMI 0906
R208 0R0402R208 0R0402 R201 0R0402R201 0R0402
RN22
RN22
1
2
3
4
5
6
7
8
8P4R-0R0402
8P4R-0R0402
RN23 8P4R-0R0402RN23 8P4R-0R0402
1
2
3
4
5
6
7
8
RN24 8P4R-0R0402RN24 8P4R-0R0402
1
2
3
4
5
6
7
8
R293 0R0402R293 0R0402 R292 0R0402R292 0R0402
R194 0R0402R194 0R0402 R195 0R0402R195 0R0402
R232 0R0402R232 0R0402 R224 0R0402R224 0R0402
R281 0R0402R281 0R0402 R280 0R0402R280 0R0402
C382
C382
X_C10p50N0402
X_C10p50N0402
CPU_CLK 8 CPU_CLK# 8
NBGFX_SRCCLK 15 NBGFX_SRCCLK# 15
GFX_CLKP 23 GFX_CLKN 23
GPPCLK0 23 GPPCLK0# 23 CK_PE_100M_1394P 29 CK_PE_100M_1394N 29
CK_PE_100M_LAN 27 CK_PE_100M_LAN# 27 NBLINKCLK 15 NBLINKCLK# 15
SBSRCCLK 18 SBSRCCLK# 18
HTREFCLK 15 HTREFCLK# 15
SIO_CLK 30 USBCLK_EXT 20
C383
C383 X_C10p50N0402
X_C10p50N0402
2
CLK_VDD
DOC
VCC3
R291
R291
4.7KR0402
4.7KR0402
R284 X_4.7KR0402R284 X_4.7KR0402
R279
R279 10KR0402
10KR0402
USBCLK_EXT_R
DOC0#
DOC1#
Title
Title
Title
Clock-Gen ICS9LPRS477
Clock-Gen ICS9LPRS477
Clock-Gen ICS9LPRS477
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
65
U18B
U18B
THERMPAD
ICS9LPRS477BKLFT_MLF64-RH
ICS9LPRS477BKLFT_MLF64-RH
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
MS-7501
MS-7501
MS-7501
Last Revision Date:
Last Revision Date:
Last Revision Date: Sheet
Sheet
Sheet
1
Rev
Rev
Rev
0A
0A
0A
Tuesday, November 06, 2007
Tuesday, November 06, 2007
Tuesday, November 06, 2007
738
738
738
of
of
of
5
4
3
2
1
L0_CLKIN_H(1) L0_CLKIN_L(1) L0_CLKIN_H(0) L0_CLKIN_L(0)
L0_CTLIN_H(1) L0_CTLIN_L(1) L0_CTLIN_H(0) L0_CTLIN_L(0)
L0_CADIN_H(15) L0_CADIN_L(15) L0_CADIN_H(14) L0_CADIN_L(14) L0_CADIN_H(13) L0_CADIN_L(13) L0_CADIN_H(12) L0_CADIN_L(12) L0_CADIN_H(11) L0_CADIN_L(11) L0_CADIN_H(10) L0_CADIN_L(10) L0_CADIN_H(9) L0_CADIN_L(9) L0_CADIN_H(8) L0_CADIN_L(8)
L0_CADIN_H(7) L0_CADIN_L(7) L0_CADIN_H(6) L0_CADIN_L(6) L0_CADIN_H(5) L0_CADIN_L(5) L0_CADIN_H(4) L0_CADIN_L(4) L0_CADIN_H(3) L0_CADIN_L(3) L0_CADIN_H(2) L0_CADIN_L(2) L0_CADIN_H(1) L0_CADIN_L(1) L0_CADIN_H(0) L0_CADIN_L(0)
M2_1
M2_1
HT_CADIN_H[15..0] HT_CADIN_L[15..0] HT_CADOUT_H[15..0] HT_CADOUT_L[15..0]
C256
C256
C4.7u16Y1206
C4.7u16Y1206
X_C4.7u16Y1206
X_C4.7u16Y1206
CPU1A
CPU1A
HYPERTRANSPORT
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0) L0_CTLOUT_H(1)
L0_CTLOUT_L(1) L0_CTLOUT_H(0) L0_CTLOUT_L(0)
L0_CADOUT_H(15) L0_CADOUT_L(15) L0_CADOUT_H(14) L0_CADOUT_L(14) L0_CADOUT_H(13) L0_CADOUT_L(13) L0_CADOUT_H(12) L0_CADOUT_L(12) L0_CADOUT_H(11) L0_CADOUT_L(11) L0_CADOUT_H(10) L0_CADOUT_L(10)
L0_CADOUT_H(9) L0_CADOUT_L(9) L0_CADOUT_H(8) L0_CADOUT_L(8)
L0_CADOUT_H(7) L0_CADOUT_L(7) L0_CADOUT_H(6) L0_CADOUT_L(6) L0_CADOUT_H(5) L0_CADOUT_L(5) L0_CADOUT_H(4) L0_CADOUT_L(4) L0_CADOUT_H(3) L0_CADOUT_L(3) L0_CADOUT_H(2) L0_CADOUT_L(2) L0_CADOUT_H(1) L0_CADOUT_L(1) L0_CADOUT_H(0) L0_CADOUT_L(0)
C207
C207
VDDA25VDDA_25
L1
L1
80L2A-100_0805-RH
80L2A-100_0805-RH
C3300p50X0402
C3300p50X0402
LDT_PWRGD LDT_STOP#
CPU_PRESENT_L
CPU_TDI CPU_TRST_L CPU_TCK CPU_TMS
CPU_DBREQ_L
TP10TP10
CPU_VTT_SENSE
CPU_M_VREF
CPU_TEST25_H CPU_TEST25_L
C80
C80
VDDA25
AL10 AJ10 AH10
AH11 AJ11
C10 D10
A8 B8
C9 D8 C7
AL3 AL6
AK6
AL4
AK4
AL9
A5 G2
G1
E12 F12
A10 B10 F10
E9
AJ7
F6 D6
E7 F8 C5
AH9
E5
AJ5
AH7
AJ6
CPU1D
CPU1D
MISC
MISC
VDDA1 VDDA2
CLKIN_H
PLATFORM_TYPE
CLKIN_L PWROK
LDTSTOP_L RESET_L
CPU_PRESENT_L SIC
SID ALERT_L SA0
TDI TRST_L TCK TMS
DBREQ_L VDD_FB_H
VDD_FB_L
VTT_SENSE M_VREF
M_ZN M_ZP
TEST25_H TEST25_L TEST19 TEST18 TEST13 TEST9
TEST17 TEST16 TEST15 TEST14 TEST12
TEST7 TEST6
TEST3 TEST2
KEY/VSS1 KEY/VSS2
CORE_TYPE
VID(5)
VID(4) SVC/VID(3) SVD/VID(2)
PVIEN/VID(1)
VID(0)
THERMDC THERMDA
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H VDDIO_FB_L
VDDNB_FB_H
VDDNB_FB_L
PSI_L
HTREF1 HTREF0
TEST29_H TEST29_L
TEST24 TEST23 TEST22 TEST21 TEST20
TEST28_H TEST28_L
TEST27 TEST26 TEST10
TEST8
TDO
H22 AE9
CPU_PLATFORM_TYPE
F2
CPU_CORE_TYPE
G5 D2
CPUVID4
D1
CPUVID3LDT_RST#
C1
CPUVID2
E3
CPUVID1
E2
CPUVID0
E1 AG9
AG8 AK7
CPU_HOT
AL7
CPU_TDO
AK10
CPU_DBRDY
B6 AK11
AL11 G4 G3
CPU_PSI_L
F1
HTREF1
V8
HTREF0
V7
TEST29_H
C11
TEST29_L
D11
AK8 AH8 AJ9 AL8 AJ8
J10 H9 AK9
R136 300R0402R136 300R0402
AK5 G7 D4
TP23TP23
X_0.22u/16v/X7/6
C200
C200
HT_CLKOUT_H1 13 HT_CLKOUT_L1 13 HT_CLKOUT_H0 13 HT_CLKOUT_L0 13
HT_CTLOUT_H1 13 HT_CTLOUT_L1 13 HT_CTLOUT_H0 13 HT_CTLOUT_L0 13
HT_CADOUT_H15 HT_CADOUT_L15 HT_CADOUT_H14 HT_CADOUT_L14 HT_CADOUT_H13 HT_CADOUT_L13 HT_CADOUT_H12 HT_CADOUT_L12 HT_CADOUT_H11 HT_CADOUT_L11 HT_CADOUT_H10 HT_CADOUT_L10 HT_CADOUT_H9 HT_CADOUT_L9 HT_CADOUT_H8 HT_CADOUT_L8
HT_CADOUT_H7 HT_CADOUT_L7 HT_CADOUT_H6 HT_CADOUT_L6 HT_CADOUT_H5 HT_CADOUT_L5 HT_CADOUT_H4 HT_CADOUT_L4 HT_CADOUT_H3 HT_CADOUT_L3HT_CADIN_L3 HT_CADOUT_H2 HT_CADOUT_L2 HT_CADOUT_H1 HT_CADOUT_L1 HT_CADOUT_H0 HT_CADOUT_L0
X_0.22u/16v/X7/6
C88
C88
X_C0.22u16X
X_C0.22u16X
C76
C73
390R0402
390R0402
VCC_DDR
C73
C3900p50X
C3900p50X
C72
C72
VCC_DDR
R137
R137
R147
R147
39.2R1%
39.2R1%
CPU_STRAP_HI_E11 CPU_STRAP_LO_F11
R145
R145
39.2R1%
39.2R1%
C3900p50X
C3900p50X
R138
R138 390R0402
390R0402
THERM_SIC THERM_SID
R90
R90 169R1%
169R1%
C4.7u16Y1206
C4.7u16Y1206
LDT_PWRGD6,18
LDT_STOP#15,18
COREFB_H6
COREFB_L6
CPU_CLK7
CPU_CLK#7
C63
C63
LDT_RST#15,18
X_C1000p50X
X_C1000p50X
TP20TP20 TP17TP17
TP5TP5
C76
C0.22u16X
C0.22u16X
CPUCLKIN CPUCLKIN#
C69
C69
ALERT_L CPU_SA0
TP16TP16 TP24TP24
R87 300R0402R87 300R0402 R88 300R0402R88 300R0402
TP9TP9 TP12TP12 TP11TP11 TP7TP7 TP15TP15
C179
C179
C0.22u16X
C0.22u16X
AD5 AD4 AD1 AC1
Y6 W6 W2 W3
Y5 Y4 AB6 AA6 AB5 AB4 AD6 AC6 AF6 AE6 AF5 AF4 AH6 AG6 AH5 AH4
Y1 W1 AA2 AA3 AB1 AA1 AC2 AC3 AE2 AE3 AF1 AE1 AG2 AG3 AH1 AG1
VCC_DDR
TP8TP8
THERMDC_CPU 30 THERMDA_CPU 30
TP21TP21
VCC_DDR
TP6TP6
TP1TP1
R89
R89
80.6R1%
80.6R1%
TP22TP22 TP14TP14 TP18TP18
TP19TP19
VCC_DDR
CPU_CORE_TYPE6
R105
R105 300R0402
300R0402
CPUVID[0..4]6
TP13TP13
C1000p50X0402
C1000p50X0402
VCC_DDR
C171
C171
R142
R142 300R0402
300R0402
CPU_CORE_TYPE
CPU_HOT
VCC_DDR
R143
R143 300R0402
300R0402
R144 44.2R1%R144 44.2R1% R141 44.2R1%R141 44.2R1%
VCC_DDR
R82
R82 15R1%
15R1%
R81
R81 15R1%
15R1%
VCC_DDR
CPU_SA0
CPU_HOT 18
VCC_DDR
300R0402
300R0402
R146
R146
4.7KR0402
4.7KR0402
B
Q30
Q30 N-2N3904_SOT23
N-2N3904_SOT23
CE
C178
C178
C1000p50X0402
C1000p50X0402
CPU_M_VREF
C78
C78
C0.1u25Y0402-RH
C0.1u25Y0402-RH
RN5
RN5
1
2
3
4
5
6
7
8
8P4R-300R-RH
8P4R-300R-RH
R140 0RR140 0R
R139
R139
CPU_THRIP# 20
TALERT# 19,30
VCCA_1V2
C70
C70 C1000p50X
C1000p50X
LDT_PWRGD LDT_RST# LDT_STOP#
HT_CADIN_H[15..0]13 HT_CADIN_L[15..0]13
HT_CADOUT_H[15..0]13
HT_CADOUT_L[15..0]13
D D
C C
B B
VCCA_1V2 VCCA_1V2
X_C0.22u16X
X_C0.22u16X
C681
C0.22u16X
C0.22u16X
C680
C680
X_C0.22u16X
X_C0.22u16X
X_49.9R1%0402
X_49.9R1%0402
HT_CLKIN_H113
HT_CLKIN_L113
HT_CLKIN_H013
HT_CLKIN_L013
HT_CTLIN_H113
HT_CTLIN_L113
HT_CTLIN_H013
HT_CTLIN_L013
HT_CADIN_H15 HT_CADIN_L15 HT_CADIN_H14 HT_CADIN_L14 HT_CADIN_H13 HT_CADIN_L13 HT_CADIN_H12 HT_CADIN_L12 HT_CADIN_H11 HT_CADIN_L11 HT_CADIN_H10 HT_CADIN_L10 HT_CADIN_H9 HT_CADIN_L9 HT_CADIN_H8 HT_CADIN_L8
HT_CADIN_H7 HT_CADIN_L7 HT_CADIN_H6 HT_CADIN_L6 HT_CADIN_H5 HT_CADIN_L5 HT_CADIN_H4 HT_CADIN_L4 HT_CADIN_H3
HT_CADIN_H2 HT_CADIN_L2 HT_CADIN_H1 HT_CADIN_L1 HT_CADIN_H0 HT_CADIN_L0
C681
R486
R486
C201
C201
VCCA_1V2
C252
C252
X_C0.22u16X
X_C0.22u16X
X_49.9R1%0402
X_49.9R1%0402
R485
R485
N6 P6 N3 N2
V4 V5 U1 V1
U6 V6 T4 T5 R6 T6 P4 P5 M4 M5 L6 M6 K4 K5 J6 K6
U3 U2 R1 T1 R3 R2 N1 P1 L1 M1 L3 L2 J1 K1 J3 J2
ALERT_L CPU_PRESENT_L CPU_TEST25_H
A A
5
4
3
2
CPU_TEST25_L
Title
Title
Title
K9 M2 HT I/F,CTRL&DEBUG
K9 M2 HT I/F,CTRL&DEBUG
K9 M2 HT I/F,CTRL&DEBUG
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
R135 X_4.7KR0402R135 X_4.7KR0402 R134 1KR0402R134 1KR0402 R86 510RR86 510R
R85 510RR85 510R
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
MS-7501
MS-7501
MS-7501
Last Revision Date:
Last Revision Date:
Last Revision Date: Sheet
Sheet
Sheet
1
VCC_DDR
Tuesday, November 06, 2007
Tuesday, November 06, 2007
Tuesday, November 06, 2007
838
838
838
of
of
of
Rev
Rev
Rev
0A
0A
0A
5
4
3
2
1
AG21 AG20
AC25 AA24
AC28 AE20
AE19
W27
AD27 AA25
AC27
AB25 AB27 AA26
AA27
AC26
W24
AD15 AE15 AG18 AG19 AG24 AG25 AG27 AG28
AF15 AF19
AJ25
AH29
G19 H19 U27 U26
G20 G21 V27
N25 Y27
L27
M25 M27
N24 N26
P25 Y25 N27 R24 P27 R25 R26 R27 T25 U25 T27
D29 C29 C25 D25 E19 F19 F15 G15
B29 E24 E18 H15
MEM_MA_DQS_L[7..0] MEM_MA_DQS_H[7..0] MEM_MA_DM[7..0] MEM_MA_ADD[15..0] MEM_MA_DATA[63..0]
MEMORY INTERFACE A
MEMORY INTERFACE A
MA0_CLK_H(2) MA0_CLK_L(2) MA0_CLK_H(1) MA0_CLK_L(1) MA0_CLK_H(0) MA0_CLK_L(0)
MA0_CS_L(1) MA0_CS_L(0)
MA0_ODT(0) MA1_CLK_H(2)
MA1_CLK_L(2) MA1_CLK_H(1) MA1_CLK_L(1) MA1_CLK_H(0) MA1_CLK_L(0)
MA1_CS_L(1) MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L MA_WE_L MA_RAS_L
MA_BANK(2) MA_BANK(1) MA_BANK(0)
MA_CKE(1) MA_CKE(0)
MA_ADD(15) MA_ADD(14) MA_ADD(13) MA_ADD(12) MA_ADD(11) MA_ADD(10) MA_ADD(9) MA_ADD(8) MA_ADD(7) MA_ADD(6) MA_ADD(5) MA_ADD(4) MA_ADD(3) MA_ADD(2) MA_ADD(1) MA_ADD(0)
MA_DQS_H(7) MA_DQS_L(7) MA_DQS_H(6) MA_DQS_L(6) MA_DQS_H(5) MA_DQS_L(5) MA_DQS_H(4) MA_DQS_L(4) MA_DQS_H(3) MA_DQS_L(3) MA_DQS_H(2) MA_DQS_L(2) MA_DQS_H(1) MA_DQS_L(1) MA_DQS_H(0) MA_DQS_L(0)
MA_DM(7) MA_DM(6) MA_DM(5) MA_DM(4) MA_DM(3) MA_DM(2) MA_DM(1) MA_DM(0)
CPU1B
CPU1B
MA_DATA(63) MA_DATA(62) MA_DATA(61) MA_DATA(60) MA_DATA(59) MA_DATA(58) MA_DATA(57) MA_DATA(56) MA_DATA(55) MA_DATA(54) MA_DATA(53) MA_DATA(52) MA_DATA(51) MA_DATA(50) MA_DATA(49) MA_DATA(48) MA_DATA(47) MA_DATA(46) MA_DATA(45) MA_DATA(44) MA_DATA(43) MA_DATA(42) MA_DATA(41) MA_DATA(40) MA_DATA(39) MA_DATA(38) MA_DATA(37) MA_DATA(36) MA_DATA(35) MA_DATA(34) MA_DATA(33) MA_DATA(32) MA_DATA(31) MA_DATA(30) MA_DATA(29) MA_DATA(28) MA_DATA(27) MA_DATA(26) MA_DATA(25) MA_DATA(24) MA_DATA(23) MA_DATA(22) MA_DATA(21) MA_DATA(20) MA_DATA(19) MA_DATA(18) MA_DATA(17) MA_DATA(16) MA_DATA(15) MA_DATA(14) MA_DATA(13) MA_DATA(12) MA_DATA(11) MA_DATA(10)
MA_DATA(9) MA_DATA(8) MA_DATA(7) MA_DATA(6) MA_DATA(5) MA_DATA(4) MA_DATA(3) MA_DATA(2) MA_DATA(1) MA_DATA(0)
MA_DQS_H(8) MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7) MA_CHECK(6) MA_CHECK(5) MA_CHECK(4) MA_CHECK(3) MA_CHECK(2) MA_CHECK(1) MA_CHECK(0)
AE14 AG14 AG16 AD17 AD13 AE13 AG15 AE16 AG17 AE18 AD21 AG22 AE17 AF17 AF21 AE21 AF23 AE23 AJ26 AG26 AE22 AG23 AH25 AF25 AJ28 AJ29 AF29 AE26 AJ27 AH27 AG29 AF27 E29 E28 D27 C27 G26 F27 C28 E27 F25 E25 E23 D23 E26 C26 G23 F23 E22 E21 F17 G17 G22 F21 G18 E17 G16 E15 G13 H13 H17 E16 E14 G14
J28 J27
J25 K25
J26 G28 G27 L24 K27 H29 H27
MEM_MA_DATA63 MEM_MA_DATA62 MEM_MA_DATA61 MEM_MA_DATA60 MEM_MA_DATA59 MEM_MA_DATA58 MEM_MA_DATA57 MEM_MA_DATA56 MEM_MA_DATA55 MEM_MA_DATA54 MEM_MA_DATA53 MEM_MA_DATA52 MEM_MA_DATA51 MEM_MA_DATA50 MEM_MA_DATA49 MEM_MA_DATA48 MEM_MA_DATA47 MEM_MA_DATA46 MEM_MA_DATA45 MEM_MA_DATA44 MEM_MA_DATA43 MEM_MA_DATA42 MEM_MA_DATA41 MEM_MA_DATA40 MEM_MA_DATA39 MEM_MA_DATA38 MEM_MA_DATA37 MEM_MA_DATA36 MEM_MA_DATA35 MEM_MA_DATA34 MEM_MA_DATA33 MEM_MA_DATA32 MEM_MA_DATA31 MEM_MA_DATA30 MEM_MA_DATA29 MEM_MA_DATA28 MEM_MA_DATA27 MEM_MA_DATA26 MEM_MA_DATA25 MEM_MA_DATA24 MEM_MA_DATA23 MEM_MA_DATA22 MEM_MA_DATA21 MEM_MA_DATA20
MEM_MA_DATA19 MEM_MA_DATA18 MEM_MA_DATA17 MEM_MA_DATA16 MEM_MA_DATA15 MEM_MA_DATA14 MEM_MA_DATA13 MEM_MA_DATA12 MEM_MA_DATA11 MEM_MA_DATA10
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
AK19
AE30 AC31
AD29 AL19
AL18
AE29 AB31
AD31
AC29 AC30 AB29
AA31 AA28
AE31
AA29
AA30 AK13 AK17 AK23
AL23 AL28 AL29
AH17 AK29
AJ19
A18 A19 U31 U30
C19
D19 W29 W28
N31
M31
M29
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AJ13 AJ17
D31
C31
C24
C23
D17
C17
C14
C13 AJ14 AJ23
C30
A23
B17
B13
MEM_MB_DQS_L[7..0] MEM_MB_DQS_H[7..0] MEM_MB_DM[7..0] MEM_MB_ADD[15..0] MEM_MB_DATA[63..0]
MEMORY INTERFACE B
MEMORY INTERFACE B
MB0_CLK_H(2) MB0_CLK_L(2) MB0_CLK_H(1) MB0_CLK_L(1) MB0_CLK_H(0) MB0_CLK_L(0)
MB0_CS_L(1) MB0_CS_L(0)
MB0_ODT(0) MB1_CLK_H(2)
MB1_CLK_L(2) MB1_CLK_H(1) MB1_CLK_L(1) MB1_CLK_H(0) MB1_CLK_L(0)
MB1_CS_L(1) MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L MB_WE_L MB_RAS_L
MB_BANK(2) MB_BANK(1) MB_BANK(0)
MB_CKE(1) MB_CKE(0)
MB_ADD(15) MB_ADD(14) MB_ADD(13) MB_ADD(12) MB_ADD(11) MB_ADD(10) MB_ADD(9) MB_ADD(8) MB_ADD(7) MB_ADD(6) MB_ADD(5) MB_ADD(4) MB_ADD(3) MB_ADD(2) MB_ADD(1) MB_ADD(0)
MB_DQS_H(7) MB_DQS_L(7) MB_DQS_H(6) MB_DQS_L(6) MB_DQS_H(5) MB_DQS_L(5) MB_DQS_H(4) MB_DQS_L(4) MB_DQS_H(3) MB_DQS_L(3) MB_DQS_H(2) MB_DQS_L(2) MB_DQS_H(1) MB_DQS_L(1) MB_DQS_H(0) MB_DQS_L(0)
MB_DM(7) MB_DM(6) MB_DM(5) MB_DM(4) MB_DM(3) MB_DM(2) MB_DM(1) MB_DM(0)
CPU1C
CPU1C
MB_DATA(63) MB_DATA(62) MB_DATA(61) MB_DATA(60) MB_DATA(59) MB_DATA(58) MB_DATA(57) MB_DATA(56) MB_DATA(55) MB_DATA(54) MB_DATA(53) MB_DATA(52) MB_DATA(51) MB_DATA(50) MB_DATA(49) MB_DATA(48) MB_DATA(47) MB_DATA(46) MB_DATA(45) MB_DATA(44) MB_DATA(43) MB_DATA(42) MB_DATA(41) MB_DATA(40) MB_DATA(39) MB_DATA(38) MB_DATA(37) MB_DATA(36) MB_DATA(35) MB_DATA(34) MB_DATA(33) MB_DATA(32) MB_DATA(31) MB_DATA(30) MB_DATA(29) MB_DATA(28) MB_DATA(27) MB_DATA(26) MB_DATA(25) MB_DATA(24) MB_DATA(23) MB_DATA(22) MB_DATA(21) MB_DATA(20) MB_DATA(19) MB_DATA(18) MB_DATA(17) MB_DATA(16) MB_DATA(15) MB_DATA(14) MB_DATA(13) MB_DATA(12) MB_DATA(11) MB_DATA(10)
MB_DATA(9) MB_DATA(8) MB_DATA(7) MB_DATA(6) MB_DATA(5) MB_DATA(4) MB_DATA(3) MB_DATA(2) MB_DATA(1) MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7) MB_CHECK(6) MB_CHECK(5) MB_CHECK(4) MB_CHECK(3) MB_CHECK(2) MB_CHECK(1) MB_CHECK(0)
AH13 AL13 AL15 AJ15 AF13 AG13 AL14 AK15 AL16 AL17 AK21 AL21 AH15 AJ16 AH19 AL20 AJ22 AL22 AL24 AK25 AJ21 AH21 AH23 AJ24 AL27 AK27 AH31 AG30 AL25 AL26 AJ30 AJ31 E31 E30 B27 A27 F29 F31 A29 A28 A25 A24 C22 D21 A26 B25 B23 A22 B21 A20 C16 D15 C21 A21 A17 A16 B15 A14 E13 F13 C15 A15 A13 D13
J31 J30
J29 K29
K31 G30 G29 L29 L28 H31 G31
MEM_MB_DATA63 MEM_MB_DATA62 MEM_MB_DATA61 MEM_MB_DATA60 MEM_MB_DATA59 MEM_MB_DATA58 MEM_MB_DATA57 MEM_MB_DATA56 MEM_MB_DATA55 MEM_MB_DATA54 MEM_MB_DATA53 MEM_MB_DATA52 MEM_MB_DATA51 MEM_MB_DATA50 MEM_MB_DATA49 MEM_MB_DATA48 MEM_MB_DATA47 MEM_MB_DATA46 MEM_MB_DATA45 MEM_MB_DATA44 MEM_MB_DATA43 MEM_MB_DATA42 MEM_MB_DATA41 MEM_MB_DATA40 MEM_MB_DATA39 MEM_MB_DATA38 MEM_MB_DATA37 MEM_MB_DATA36 MEM_MB_DATA35 MEM_MB_DATA34 MEM_MB_DATA33 MEM_MB_DATA32 MEM_MB_DATA31 MEM_MB_DATA30 MEM_MB_DATA29 MEM_MB_DATA28 MEM_MB_DATA27 MEM_MB_DATA26 MEM_MB_DATA25 MEM_MB_DATA24 MEM_MB_DATA23 MEM_MB_DATA22 MEM_MB_DATA21 MEM_MB_DATA20
MEM_MB_DATA19 MEM_MB_DATA18 MEM_MB_DATA17 MEM_MB_DATA16 MEM_MB_DATA15 MEM_MB_DATA14 MEM_MB_DATA13 MEM_MB_DATA12 MEM_MB_DATA11 MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DQS_L[7..0]11 MEM_MB_DQS_H[7..0]11
MEM_MB_DM[7..0]11 MEM_MB_ADD[15..0]11,12 MEM_MB_DATA[63..0]11
MEM_MB0_CLK_H211,12 MEM_MB0_CLK_L211,12 MEM_MB0_CLK_H111,12 MEM_MB0_CLK_L111,12 MEM_MB0_CLK_H011,12 MEM_MB0_CLK_L011,12
MEM_MB0_CS_L111,12 MEM_MB0_CS_L011,12
MEM_MB0_ODT011,12
MEM_MB_CAS_L11,12 MEM_MB_WE_L11,12 MEM_MB_RAS_L11,12
MEM_MB_BANK211,12 MEM_MB_BANK111,12 MEM_MB_BANK011,12
MEM_MB_CKE112 MEM_MB_CKE011,12
MEM_MB0_CLK_H2 MEM_MB0_CLK_L2 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H0 MEM_MB0_CLK_L0
MEM_MB0_CS_L1 MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB_CAS_L MEM_MB_WE_L MEM_MB_RAS_L
MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_CKE1 MEM_MB_CKE0
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0
MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0
MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0
MEM_MA_DQS_L[7..0]11 MEM_MA_DQS_H[7..0]11
MEM_MA_DM[7..0]11
MEM_MA_ADD[15..0]11,12
D D
MEM_MA0_CLK_H211,12 MEM_MA0_CLK_L211,12 MEM_MA0_CLK_H111,12 MEM_MA0_CLK_L111,12 MEM_MA0_CLK_H011,12 MEM_MA0_CLK_L011,12
MEM_MA0_CS_L111,12 MEM_MA0_CS_L011,12
MEM_MA0_ODT011,12
C C
B B
MEM_MA_CAS_L11,12 MEM_MA_WE_L11,12 MEM_MA_RAS_L11,12
MEM_MA_BANK211,12 MEM_MA_BANK111,12 MEM_MA_BANK011,12
MEM_MA_CKE112 MEM_MA_CKE011,12
MEM_MA_DATA[63..0]11
MEM_MA0_CLK_H2 MEM_MA0_CLK_L2 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H0 MEM_MA0_CLK_L0
MEM_MA0_CS_L1 MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA_CAS_L MEM_MA_WE_L MEM_MA_RAS_L
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
MEM_MA_CKE1 MEM_MA_CKE0
MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0
MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0
MEM_MA_DM7 MEM_MA_DM6 MEM_MA_DM5 MEM_MA_DM4 MEM_MA_DM3 MEM_MA_DM2 MEM_MA_DM1 MEM_MA_DM0
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
K9 M2 DDR MEMORY I/F
K9 M2 DDR MEMORY I/F
K9 M2 DDR MEMORY I/F
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
MS-7501
MS-7501
MS-7501
1
Last Revision Date:
Last Revision Date:
Last Revision Date: Sheet
Sheet
Sheet
Tuesday, November 06, 2007
Tuesday, November 06, 2007
Tuesday, November 06, 2007
Rev
Rev
Rev
0A
0A
0A
938
938
938
of
of
of
5
VCCP
D D
VCCP
AA10 AA12 AA14 AA16 AA18
AB11
AC10
AE10
C C
B B
VTT_DDR
C64
C64 C0.22u16X
C0.22u16X
A A
VTT_DDR VCC_DDR
C187
C187 X_C0.22u16X
X_C0.22u16X
A4 A6 B5 B7 C6 C8 D7 D9 E8
E10
F9 F11 G10 G12
AA8
AB7 AB9
AC4 AC5 AC8
AD2 AD3 AD7 AD9
AF7 AF9
AG4 AG5 AG7 AH2 AH3
B3
C2
C4
D3
D5
E4
E6
F5
F7
G6 G8
H7 H11 H23
J8
J12 J14 J16 J18 J20 J22 J24
K7
K9 K11 K13 K15 K17 K19 K21 K23
L4
L5
L8
L10
L12 Y17 Y19
VDD1
VDD1
VDDNB1 VDDNB2 VDDNB3 VDDNB4 VDDNB5 VDDNB6 VDDNB7 VDDNB8 VDDNB9 VDDNB10 VDDNB11 VDDNB12 VDDNB13 VDDNB14
VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18 VDD19 VDD20 VDD21 VDD22 VDD23 VDD24 VDD25 VDD26 VDD27 VDD28 VDD31 VDD32 VDD35 VDD36 VDD39 VDD40 VDD43 VDD44 VDD47 VDD48 VDD51 VDD52 VDD53 VDD54 VDD55 VDD56 VDD57 VDD58 VDD59 VDD60 VDD61 VDD62 VDD63 VDD64 VDD65 VDD66 VDD67 VDD68 VDD69 VDD70 VDD71 VDD72 VDD73 VDD74 VDD75 VDD150 VDD151
C195
C195 X_C0.22u16X
X_C0.22u16X
C224
C224
X_C0.01u16X0402
X_C0.01u16X0402
C59
C59 X_C0.22u16X
X_C0.22u16X
CPU1F
CPU1F
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44
VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74
VSS240 VSS241
C60
C60
X_C4.7u10Y0805
X_C4.7u10Y0805
VCC3VCC_DDR
C191
C191
C4.7u10Y0805
C4.7u10Y0805
5
A3 A7 A9 A11 AA4 AA5 AA7 AA9 AA11 AA13 AA15 AA17 AA19 AA21 AA23 AB2 AB3 AB8 AB10 AB12 AB14 AB16 AB18 AB20 AB22 AC7 AC9 AC11 AC13 AC15 AC17 AC19 AC21 AC23 AD8 AD10 AD12 AD14 AD16 AD20 AD22 AD24 AE4 AE5
AE11 AF2 AF3 AF8 AF10 AF12 AF14 AF16 AF18 AF20 AF22 AF24 AF26 AF28 AG10 AG11 AH14 AH16 AH18 AH20 AH22 AH24 AH26 AH28 AH30 AK2 AK14 AK16 AK18 Y14 Y16
X_C4.7u10Y0805
X_C4.7u10Y0805
C4.7u10Y0805
C4.7u10Y0805
C184
C184
C180p50N0402
C180p50N0402
C65
C65
C180p50N0402
C180p50N0402
SLOTOCC# 6
C170
C170
C68
C68
X_C180p50N0402
X_C180p50N0402
C79
C79
C173
C173
X_C180p50N0402
X_C180p50N0402
VCCP
C74
C74
X_C1000p50X
X_C1000p50X
C177
C177
C1000p50X
C1000p50X
L14
VDD1
L16
VDD2
L18
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
M11
VDD8
M13
VDD9
M15
VDD10
M17
VDD11
M19
VDD12
N8
VDD13
N10
VDD14
N12
VDD15
N14
VDD16
N16
VDD17
N18
VDD18
P7
VDD19
P9
VDD20
P11
VDD21
P13
VDD22
P15
VDD23
P17
VDD24
P19
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
R10
VDD29
R12
VDD30
R14
VDD31
R16
VDD32
R18
VDD33
R20
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
T11
VDD39
T13
VDD40
T15
VDD41
T17
VDD42
T19
VDD43
T21
VDD44
U8
VDD45
U10
VDD46
U12
VDD47
U14
VDD48
U16
VDD49
U18
VDD50
U20
VDD51
V9
VDD52
V11
VDD53
V13
VDD54
V15
VDD55
V17
VDD56
V19
VDD57
V21
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
W10
VDD62
W12
VDD63
W14
VDD64
W16
VDD65
W18
VDD66
W20
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
Y11
VDD72
Y13
VDD73
Y15
VDD74
Y21
VDD75
VDD2
VDD2
C67
C67
C1000p50X
C1000p50X
C180
C180
C0.22u16X
C0.22u16X
X_C1000p50X
X_C1000p50X
CPU1G
CPU1G
C642
C642
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48
VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75
VCCP
4
AK20 AK22 AK24 AK26 AK28 AK30 AL5 B4 B9 B11 B14 B16 B18 B20 B22 B24 B26 B28 B30 C3 D14 D16 D18 D20 D22 D24 D26 D28 D30 E11 F4 F14 F16 F18 F20 F22 F24 F26 F28 F30 G9 G11 H8 H10 H12 H14 H16 H18
H24 H26 H28 H30 J4 J5 J7 J9 J11 J13 J15 J17 J19 J21 J23 K2 K3 K8 K10 K12 K14 K16 K18 K20 K22 Y18
VCCP
AA20 AA22 AB13 AB15 AB17 AB19 AB21 AB23 AC12 AC14 AC16 AC18 AC20 AC22 AD11 AD23 AE12 AF11
VCC_DDR VCCP
C209
C209 X_C0.22u16X
X_C0.22u16X
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD7 VDD8 VDD9 VDD10 VDD11 VDD12 VDD13 VDD14 VDD15 VDD16 VDD17 VDD18
L20
VDD19
L22
VDD20
M21
VDD21
M23
VDD22
N20
VDD23
N22
VDD24
P21
VDD25
P23
VDD26
R22
VDD27
T23
VDD28
U22
VDD29
V23
VDD30
W22
VDD31
Y23
VDD32
5
5
6
6
7
7
8
8
1
1
2
2
3
3
BOTTOM
C663
C663 X_C2.2u6.3X5
X_C2.2u6.3X5
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C188
C188
CPU1H
CPU1H
VDD3
VDD3
VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65
C658
C658 X_C2.2u6.3X5
X_C2.2u6.3X5
C193
C193
BOTTOM
C639
C639
X_C0.22u16X
X_C0.22u16X
4
C648
C648
X_C0.22u16X
X_C0.22u16X
C649
C649 X_C0.01u50X
X_C0.01u50X
X_C180p50N0402
X_C180p50N0402
N17
VSS1
N19
VSS2
N21
VSS3
N23
VSS4
P2
VSS5
P3
VSS6
P8
VSS7
P10
VSS8
P12
VSS9
P14 P16 P18 P20 P22 R7 R9 R11 R13 R15 R17 R19 R21 R23 T8 T10 T12 T14 T16 T18 T20 T22 U4 U5 U7 U9 U11 U13 U15 U17 U19 U21 U23 V2 V3 V10 V12 V14 V16 V18 V20 V22 W9 W11 W13 W15 W17 W19 W21 W23 Y8 Y10 Y12 W7 Y20 Y22
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH C106
C106
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C62
C62
3
BOTTOM
C643
C643 C4.7u10Y0805
C4.7u10Y0805
C103
C103
C113
C113
C0.1u25Y0402-RH
C0.1u25Y0402-RH
3
VCC_DDR
For EMI
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C0.1u25Y0402-RH
C0.1u25Y0402-RH
VCCA_1V2
VTT_DDR
C660
C660
X_C0.22u16X
X_C0.22u16X
X_C10u10X1206
X_C10u10X1206
C647
C647 X_C4.7u10Y0805
X_C4.7u10Y0805
C208
C208
VCCP
C655
C655
VCCP
C644
C644
C22u6.3X1206
C22u6.3X1206
VCCP
C635
C635
+
+
12
EC11
EC11 X_CD1800u6.3EL20-RH-2
X_CD1800u6.3EL20-RH-2
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C205
C205
C176
C176
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
AJ4 AJ3 AJ2 AJ1
D12 C12 B12 A12
AB24 AB26 AB28 AB30 AC24 AD26 AD28 AD30 AF30
M24 M26 M28 M30 P24 P26 P28 P30
T24 T26 T28
T30 V25 V26 V28 V30 Y24 Y26 Y28 Y29
C654
C654
C0.22u16X
C0.22u16X
X_C0.22u16X
X_C0.22u16X
C630
C630
X_C22u6.3X1206
X_C22u6.3X1206
X_C22u6.3X1206
X_C22u6.3X1206
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C99
C99
C0.1u25Y0402-RH
C0.1u25Y0402-RH
VLDT_A1 VLDT_A2 VLDT_A3 VLDT_A4
VTT1 VTT2 VTT3 VTT4
VDDIO1 VDDIO2 VDDIO3 VDDIO4 VDDIO5 VDDIO6 VDDIO7 VDDIO8 VDDIO9 VDDIO10 VDDIO11 VDDIO12 VDDIO13 VDDIO14 VDDIO15 VDDIO16 VDDIO17 VDDIO18 VDDIO19 VDDIO20 VDDIO21 VDDIO22 VDDIO23 VDDIO24 VDDIO25 VDDIO26 VDDIO27 VDDIO28 VDDIO29
X_C10u6.3X51206
X_C10u6.3X51206
C633
C633
C10u10X1206
C10u10X1206
X_C10u10X1206
X_C10u10X1206
C98
C98
CPU1I
CPU1I
VDDIO
VDDIO
VLDT_B1 VLDT_B2 VLDT_B3 VLDT_B4
C91
C91
C631
C631
X_C22u6.3X1206
X_C22u6.3X1206
VCC_DDRVCC_DDR
C632
C632
X_C10u10X1206
X_C10u10X1206
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C204
C204
C101
C101
C0.1u25Y0402-RH
C0.1u25Y0402-RH
2
VTT5 VTT6 VTT7 VTT8 VTT9
VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8
VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28
C634
C634 C0.01u50X
C0.01u50X
C637
C637
C10u6.3X51206
C10u6.3X51206
C629
C629
C640
C640
C181
C181
C0.1u25Y0402-RH
C0.1u25Y0402-RH
2
H6 H5 H2 H1
AK12 AJ12 AH12 AG12 AL12
K24 K26 K28 K30 L7 L9 L11 L13 L15 L17 L19 L21 L23 M8 M10 M12 M14 M16 M18 M20 M22 N4 N5 N7 N9 N11 N13 N15
C638
C638
C10u10X1206
C10u10X1206
X_C0.1u25Y0402-RH
X_C0.1u25Y0402-RH
C120
C120
VTT_DDR
X_C22u6.3X1206
X_C22u6.3X1206
C653
C653
C4.7u10Y0805
C4.7u10Y0805
C102
C102
VLDT_RUN_B
C646
C646
X_C0.22u16X
X_C0.22u16X
C4.7u10Y0805
C4.7u10Y0805
BOTTOM
C628
C628
X_C10u10X1206
X_C10u10X1206
C203
C203
X_C0.22u16X
X_C0.22u16X
C174
C174 C0.01u50X
C0.01u50X
C96
C96
X_C0.01u50Y5
X_C0.01u50Y5
C93
C93
C94
C94
X_C0.01u50Y5
X_C0.01u50Y5
C652
C652
C10u6.3X51206
C10u6.3X51206
X_C10u6.3X51206
X_C10u6.3X51206
C97
C97
C119
C119
X_C0.01u50X
X_C0.01u50X
C10u6.3X51206
C10u6.3X51206
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
K9 M2 PWR & GND
K9 M2 PWR & GND
K9 M2 PWR & GND
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
C645
C645
C636
C636
C95
C95 C0.01u50Y5
C0.01u50Y5
C10u10X1206
C10u10X1206
C135
C135
X_C180p50N0402
X_C180p50N0402
MS-7501
MS-7501
MS-7501
1
1
C659
C659
C641
C641
X_C10u6.3X51206
X_C10u6.3X51206
Last Revision Date:
Last Revision Date:
Last Revision Date:
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Wednesday, November 07, 2007
Sheet
Sheet
Sheet
10 38
10 38
10 38
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
MEM_MA_DQS_H[7..0]9 MEM_MA_DQS_L[7..0]9
MEM_MA_DM[7..0]9 MEM_MA_ADD[15..0]9,12 MEM_MA_DATA[63..0]9
D D
C C
MEM_MA_BANK29,12 MEM_MA_BANK19,12 MEM_MA_BANK09,12
B B
MEM_MA0_CLK_H09,12 MEM_MA0_CLK_L09,12 MEM_MA0_CLK_H19,12 MEM_MA0_CLK_L19,12 MEM_MA0_CLK_H29,12 MEM_MA0_CLK_L29,12
MEM_MA_CKE09,12 MEM_MA_RAS_L9,12
MEM_MA_CAS_L9,12
A A
MEM_MA0_CS_L09,12 MEM_MA0_CS_L19,12
MEM_MA_DQS_H[7..0] MEM_MA_DQS_L[7..0] MEM_MA_DM[7..0] MEM_MA_ADD[15..0] MEM_MA_DATA[63..0]
VCC_DDR
69
172
178
184
187
189
197
64
170
175
181
191
194
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
164
DQS17_H
165
DQS17_L
MEM_MA_DM7
232
DQS16_H
233
DQS16_L
MEM_MA_DM6
223
DQS15_H
224
DQS15_L
MEM_MA_DM5
211
DQS14_H
212
DQS14_L
MEM_MA_DM4
202
DQS13_H
203
DQS13_L
MEM_MA_DM3
155
DQS12_H
156
DQS12_L
MEM_MA_DM2
146
DQS11_H
147
DQS11_L
MEM_MA_DM1
134
DQS10_H
135
DQS10_L
MEM_MA_DM0
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
MEM_MA_DQS_H7 MEM_MA_DQS_L7 MEM_MA_DQS_H6 MEM_MA_DQS_L6 MEM_MA_DQS_H5 MEM_MA_DQS_L5 MEM_MA_DQS_H4 MEM_MA_DQS_L4 MEM_MA_DQS_H3 MEM_MA_DQS_L3 MEM_MA_DQS_H2 MEM_MA_DQS_L2 MEM_MA_DQS_H1 MEM_MA_DQS_L1 MEM_MA_DQS_H0 MEM_MA_DQS_L0
SCL06,7,20
SDA06,7,20
MEM_MA_BANK2 MEM_MA_BANK1 MEM_MA_BANK0
MEM_MA_ADD15 MEM_MA_ADD14 MEM_MA_ADD13 MEM_MA_ADD12 MEM_MA_ADD11 MEM_MA_ADD10 MEM_MA_ADD9 MEM_MA_ADD8 MEM_MA_ADD7 MEM_MA_ADD6 MEM_MA_ADD5 MEM_MA_ADD4 MEM_MA_ADD3 MEM_MA_ADD2 MEM_MA_ADD1 MEM_MA_ADD0
MEM_MA0_CLK_H0 MEM_MA0_CLK_L0 MEM_MA0_CLK_H1 MEM_MA0_CLK_L1 MEM_MA0_CLK_H2 MEM_MA0_CLK_L2
MEM_MA_CKE0 MEM_MA_RAS_L
MEM_MA_CAS_L MEM_MA0_CS_L0
MEM_MA0_CS_L1
5
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
SCL0
120
SCL
SDA0
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DDRII-240_GREEN-RH
DDRII-240_GREEN-RH
VDDQ651VDDQ756VDDQ862VDDQ9
4
VCC3
238
78
72
DIMM1
DIMM1
VDDQ1075VDDQ11
VDDSPD
MEM_MA_DATA63
236
DQ63
MEM_MA_DATA62
235
DQ62
MEM_MA_DATA61
230
DQ61
MEM_MA_DATA60
229
DQ60
MEM_MA_DATA59
117
DQ59
MEM_MA_DATA58
116
DQ58
MEM_MA_DATA57
111
DQ57
MEM_MA_DATA56
110
DQ56
MEM_MA_DATA55
227
DQ55
MEM_MA_DATA54
226
DQ54
MEM_MA_DATA53
218
DQ53
MEM_MA_DATA52
217
DQ52
MEM_MA_DATA51
108
DQ51
MEM_MA_DATA50
107
DQ50
MEM_MA_DATA49
99
DQ49
MEM_MA_DATA48
98
DQ48
MEM_MA_DATA47
215
DQ47
MEM_MA_DATA46
214
DQ46
MEM_MA_DATA45
209
DQ45
MEM_MA_DATA44
208
DQ44
MEM_MA_DATA43
96
DQ43
MEM_MA_DATA42
95
DQ42
MEM_MA_DATA41
90
DQ41
MEM_MA_DATA40
89
DQ40
MEM_MA_DATA39
206
DQ39
MEM_MA_DATA38
205
DQ38
MEM_MA_DATA37
200
DQ37
MEM_MA_DATA36
199
DQ36
MEM_MA_DATA35
87
DQ35
MEM_MA_DATA34
86
DQ34
MEM_MA_DATA33
81
DQ33
MEM_MA_DATA32
80
DQ32
MEM_MA_DATA31
159
DQ31
MEM_MA_DATA30
158
DQ30
MEM_MA_DATA29
153
DQ29
MEM_MA_DATA28
152
DQ28
MEM_MA_DATA27
40
DQ27
MEM_MA_DATA26
39
DQ26
MEM_MA_DATA25
34
DQ25
MEM_MA_DATA24
33
DQ24
MEM_MA_DATA23
ERR_OUT_L
PAR_IN
150
DQ23
MEM_MA_DATA22
149
DQ22
MEM_MA_DATA21
144
DQ21
MEM_MA_DATA20
143
DQ20
MEM_MA_DATA19
31
DQ19
MEM_MA_DATA18
30
DQ18
MEM_MA_DATA17
25
DQ17
MEM_MA_DATA16
24
DQ16
MEM_MA_DATA15
141
DQ15
MEM_MA_DATA14
140
DQ14
MEM_MA_DATA13
132
DQ13
MEM_MA_DATA12
131
DQ12
MEM_MA_DATA11
22
DQ11
MEM_MA_DATA10
21
DQ10
MEM_MA_DATA9
13
DQ9
MEM_MA_DATA8
12
DQ8
MEM_MA_DATA7
129
DQ7
MEM_MA_DATA6
128
DQ6
MEM_MA_DATA5
123
DQ5
MEM_MA_DATA4
122
DQ4
MEM_MA_DATA3
10
DQ3
MEM_MA_DATA2
9
DQ2
MEM_MA_DATA1
4
DQ1
MEM_MA_DATA0
3
DQ0
MEM_MA_WE_L
73
WE_L
1
VREF
102
TEST
195
ODT0
77
ODT1
55 68
19
NC1
4
VDDR_VREF
MEM_MA0_ODT0
MEM_MA_WE_L 9,12
MEM_MA0_ODT0 9,12
C48
C48
C0.1u25Y0402-RH
C0.1u25Y0402-RH
VDDR_VREF
MEM_MB_BANK29,12 MEM_MB_BANK19,12 MEM_MB_BANK09,12
MEM_MB0_CLK_H09,12 MEM_MB0_CLK_L09,12 MEM_MB0_CLK_H19,12 MEM_MB0_CLK_L19,12 MEM_MB0_CLK_H29,12 MEM_MB0_CLK_L29,12
3
MEM_MB_DQS_H[7..0]9 MEM_MB_DQS_L[7..0]9
MEM_MB_DM[7..0]9
MEM_MB_ADD[15..0]9,12
MEM_MB_DATA[63..0]9
MEM_MB_CKE09,12 MEM_MB_RAS_L9,12
MEM_MB_CAS_L9,12 MEM_MB0_CS_L09,12
MEM_MB0_CS_L19,12
MEM_MB_DQS_H[7..0] MEM_MB_DQS_L[7..0] MEM_MB_DM[7..0] MEM_MB_ADD[15..0] MEM_MB_DATA[63..0]
MEM_MB_DM7 MEM_MB_DM6 MEM_MB_DM5 MEM_MB_DM4 MEM_MB_DM3 MEM_MB_DM2 MEM_MB_DM1 MEM_MB_DM0
MEM_MB_DQS_H7 MEM_MB_DQS_L7 MEM_MB_DQS_H6 MEM_MB_DQS_L6 MEM_MB_DQS_H5 MEM_MB_DQS_L5 MEM_MB_DQS_H4 MEM_MB_DQS_L4 MEM_MB_DQS_H3 MEM_MB_DQS_L3 MEM_MB_DQS_H2 MEM_MB_DQS_L2 MEM_MB_DQS_H1 MEM_MB_DQS_L1 MEM_MB_DQS_H0 MEM_MB_DQS_L0
VCC3
SCL0 SDA0 MEM_MB_BANK2 MEM_MB_BANK1 MEM_MB_BANK0
MEM_MB_ADD15 MEM_MB_ADD14 MEM_MB_ADD13 MEM_MB_ADD12 MEM_MB_ADD11 MEM_MB_ADD10 MEM_MB_ADD9 MEM_MB_ADD8 MEM_MB_ADD7 MEM_MB_ADD6 MEM_MB_ADD5 MEM_MB_ADD4 MEM_MB_ADD3 MEM_MB_ADD2 MEM_MB_ADD1 MEM_MB_ADD0
MEM_MB0_CLK_H0 MEM_MB0_CLK_L0 MEM_MB0_CLK_H1 MEM_MB0_CLK_L1 MEM_MB0_CLK_H2 MEM_MB0_CLK_L2
MEM_MB_CKE0 MEM_MB_RAS_L
MEM_MB_CAS_L MEM_MB0_CS_L0
MEM_MB0_CS_L1
3
VCC_DDR
164
DQS17_H
165
DQS17_L
232
DQS16_H
233
DQS16_L
223
DQS15_H
224
DQS15_L
211
DQS14_H
212
DQS14_L
202
DQS13_H
203
DQS13_L
155
DQS12_H
156
DQS12_L
146
DQS11_H
147
DQS11_L
134
DQS10_H
135
DQS10_L
125
DQS9_H
126
DQS9_L
46
DQS8_H
45
DQS8_L
114
DQS7_H
113
DQS7_L
105
DQS6_H
104
DQS6_L
93
DQS5_H
92
DQS5_L
84
DQS4_H
83
DQS4_L
37
DQS3_H
36
DQS3_L
28
DQS2_H
27
DQS2_L
16
DQS1_H
15
DQS1_L
7
DQS0_H
6
DQS0_L
101
SA2
240
SA1
239
SA0
120
SCL
119
SDA
54
BA2
190
BA1
71
BA0
173
A15
174
A14
196
A13
176
A12
57
A11
70
A10
177
A9
179
A8
58
A7
180
A6
60
A5
61
A4
182
A3
63
A2
183
A1
188
A0
168
CB7
167
CB6
162
CB5
161
CB4
49
CB3
48
CB2
43
CB1
42
CB0
185
CK0_H
186
CK0_L
137
CK1_H
138
CK1_L
220
CK2_H
221
CK2_L
18
RESET_L
52
CKE0
171
CKE1
192
RAS_L
74
CAS_L
193
S0_L
76
S1_L
DDRII-240_ORANGE-RH
DDRII-240_ORANGE-RH
69
172
178
184
187
189
197
64
170
175
181
191
194
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
2
VCC3
238
78
72
DIMM2
DIMM2
VDDQ1075VDDQ11
VDDSPD
MEM_MB_DATA63
236
DQ63
MEM_MB_DATA62
235
DQ62
MEM_MB_DATA61
230
DQ61
MEM_MB_DATA60
229
DQ60
MEM_MB_DATA59
117
DQ59
MEM_MB_DATA58
116
DQ58
MEM_MB_DATA57
111
DQ57
MEM_MB_DATA56
110
DQ56
MEM_MB_DATA55
227
DQ55
MEM_MB_DATA54
226
DQ54
MEM_MB_DATA53
218
DQ53
MEM_MB_DATA52
217
DQ52
MEM_MB_DATA51
108
DQ51
MEM_MB_DATA50
107
DQ50
MEM_MB_DATA49
99
DQ49
MEM_MB_DATA48
98
DQ48
MEM_MB_DATA47
215
DQ47
MEM_MB_DATA46
214
DQ46
MEM_MB_DATA45
209
DQ45
MEM_MB_DATA44
208
DQ44
MEM_MB_DATA43
96
DQ43
MEM_MB_DATA42
95
DQ42
MEM_MB_DATA41
90
DQ41
MEM_MB_DATA40
89
DQ40
MEM_MB_DATA39
206
DQ39
MEM_MB_DATA38
205
DQ38
MEM_MB_DATA37
200
DQ37
MEM_MB_DATA36
199
DQ36
MEM_MB_DATA35
87
DQ35
MEM_MB_DATA34
86
DQ34
MEM_MB_DATA33
81
DQ33
MEM_MB_DATA32
80
DQ32
MEM_MB_DATA31
159
DQ31
MEM_MB_DATA30
158
DQ30
MEM_MB_DATA29
153
DQ29
MEM_MB_DATA28
152
DQ28
MEM_MB_DATA27
40
DQ27
MEM_MB_DATA26
39
DQ26
MEM_MB_DATA25
34
DQ25
MEM_MB_DATA24
33
DQ24
MEM_MB_DATA23
150
DQ23
MEM_MB_DATA22
149
DQ22
MEM_MB_DATA21
144
ERR_OUT_L
PAR_IN
DQ21
MEM_MB_DATA20
143
DQ20
MEM_MB_DATA19
31
DQ19
MEM_MB_DATA18
30
DQ18
MEM_MB_DATA17
25
DQ17
MEM_MB_DATA16
24
DQ16
MEM_MB_DATA15
141
DQ15
MEM_MB_DATA14
140
DQ14
MEM_MB_DATA13
132
DQ13
MEM_MB_DATA12
131
DQ12
MEM_MB_DATA11
22
DQ11
MEM_MB_DATA10
21
DQ10
MEM_MB_DATA9
13
DQ9
MEM_MB_DATA8
12
DQ8
MEM_MB_DATA7
129
DQ7
MEM_MB_DATA6
128
DQ6
MEM_MB_DATA5
123
DQ5
MEM_MB_DATA4
122
DQ4
MEM_MB_DATA3
10
DQ3
MEM_MB_DATA2
9
DQ2
MEM_MB_DATA1
4
DQ1
MEM_MB_DATA0
3
DQ0
MEM_MB_WE_L
73
WE_L
1
VREF
102
TEST
195
ODT0
77
ODT1
55 68
19
NC1
2
VDDR_VREF
MEM_MB0_ODT0
MEM_MB_WE_L 9,12
MEM_MB0_ODT0 9,12
VDDR_VREF
R60
R60
15R1%0402-RH
15R1%0402-RH
R71
R71
15R1%0402-RH
15R1%0402-RH
C47
C47 C0.1u25Y0402-RH
C0.1u25Y0402-RH
VCC_DDR
1
SCL0
Z
SDA0
Z
VDDR_VREF
C40
C40
VDDR_VREF
C0.1u25Y0402-RH
C0.1u25Y0402-RH
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
1
VCC3
VCC3
Y
X
Y
X
MS-7501
MS-7501
MS-7501
D21
D21 X_1PS226_SOT23
X_1PS226_SOT23
D22
D22 X_1PS226_SOT23
X_1PS226_SOT23
C49
C49 C0.1u25Y0402-RH
C0.1u25Y0402-RH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Tuesday, November 06, 2007
Tuesday, November 06, 2007
Tuesday, November 06, 2007
Sheet
Sheet
Sheet
11 38
11 38
11 38
of
of
of
Rev
Rev
Rev
0A
0A
0A
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