5
4
3
2
1
MSI
MS-7297 Ver:0B
D D
C C
B B
CPU:
AMD K8 AM2 Athlon 64/Athlon 64 FX
System Chipset:
ATI RS485
ATI SB600
On Board Chipset:
Winbond Super I/O -- W83627EHG Ver.H
LAN -- RTL8100C/RTL8110SC
HD Codec --ALC861
BIOS --LPC FLASH ROM 4M
Main Memory:
DDR2 * 2 (Max 4GB)
Expansion Slots:
PCI-E X 1 *1
PCI-E X 16 *1
PCI 2.3 Slot X 2
PWM:
Controller--Intersil ISL6566CR 3 Phase
Clock Generator:
Controller--ICS 951464AGLF
Title Page
Cover Sheet 1
Block Diagram
AMD K8 AM2 940
System Memory
DDR Terminations
2
3,4,5
6
7
ATI RS485 8-11
CLOCK GENERATOR ICS951464AGLF 12
ATI SB600 13-17
PCI Slot 1,2
PCI-Express X 16 ,X1
I/O W83627EHG Ver.H / FDD
LAN RTL8100C/RTL8110SC
HD Audio - ALC861
USB connectors
PWM - ISL6566CRZ 3 phase,TPD=89W
MS-6 ACPI Co ntr oller & MS-6+
IDE / SATA / FAN / LPT
ATX Connector / Front Panel / KB / CON
MANUAL PARTS
TV-OUT & VGA Connector
GPIO SPEC
POWER MAP
POWER OK MAP
History
RESET MAP
18
19
20
21
22
23
24
25-26
27
28
29
30
31
32
33
34
35
A A
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
Cover Sheet
MS-7297 0B
1
13 5 Thursday, June 29, 2006
of
5
4
3
2
1
BLOCK DIAGRAM
D D
POWER
SUPPLY
CONNECTOR
VREG
SOCKET AM2 940
DDR2 CONN1
DDR2 CONN2
PEX X16
C C
PRIMARY IDE
X4 - SATA CONN
B B
FLOPPY CONN
PS2/KBRD CONN
PARALLEL CONN
ATA 133
INTEGRATED SATA 1/2
Winbond W83627EHG
PEX X1
SIO
PCI EXPRESS
PCI EXPRESS
LPC BUS 33MHZ
LPC HDR
4MB FLASH
ATI
RS485
465 BGA
ATI
SB600
564 BGA
AZAILIA/AC97
X8 USB2.0 (S B 600)
VGA CONN
PCI 33MHZ
BACK PANEL CONN
USB2 PORTS 0-1
DOUBLE STACK
USB2 PORTS 2-3
X2/GBIT LAN
FRONT PANEL HDR
USB2 PORTS 4-5
USB2 PORTS 6-7
Realtek, AL C 861, 2channels rev.D
LAN-RTL8100C/8110S
PCI SLOT 1
PCI SLOT 2
A A
Title
Block Diagram
Size Document Number R ev
Custom
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7297 0B
1
of
23 5 Friday, June 30, 2006
5
4
3
2
1
C166
HT_CADIN_H [15..0]
HT_CADIN_L[15..0]
HT_CADO UT_H[15..0]
HT_CADOUT_L[15..0]
C4.7U10Y0805
CPU1A
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
CPU_SIC [13]
CPU_SID [13]
VCCA_1V2 VDDA25
C0.22U16X
C191
X_C4.7U16Y1206
C167
C4.7U10Y0805
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
C201
C180
HT_CLKOUT_H1 [8]
HT_CLKOUT_L1 [8]
HT_CLKOUT_H0 [8]
HT_CLKOUT_L0 [8]
HT_CTLOUT_H0 [8]
HT_CTLOUT_L0 [8]
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3 HT_CAD IN_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
C196
X_C0.22U16X
TP15
TP14
X_C0.22U16X
CPU_CLK [12]
CPU_CLK# [12]
VCC_DDR
X_300R0402
VCC_DDR
C3900P50X
C3900P50X
R109
R112
39.2R1%
CPU_STRAP_HI_E11
CPU_STRAP_LO_F11
R113
39.2R1%
C56
C55
THERM_SIC
THERM_SID
R280
300R0402
R73
169R1%
HT_CADIN_H [15..0] [8]
HT_CADIN_L[15..0] [8]
HT_CADO UT_H[15..0] [8]
HT_CADO U T _L[15..0] [8]
D D
VCCA_1V2
X_C0.22U16X
C175
C186
C0.22U16X
C0.22U16X
HT_CLKIN_H1 [8]
HT_CLKIN_L1 [8]
VCCA_1V2
C C
B B
HT_CLKIN_H0 [8]
HT_CLKIN_L0 [8]
R116 51R0402
R117 51R0402
HT_CTLIN_H0 [8]
HT_CTLIN_L0 [8]
HT_CADIN_H15
HT_CAD IN_L15
HT_CADIN_H14
HT_CAD IN_L14
HT_CADIN_H13
HT_CAD IN_L13
HT_CADIN_H12
HT_CAD IN_L12
HT_CADIN_H11
HT_CAD IN_L11
HT_CADIN_H10
HT_CAD IN_L10
HT_CADIN_H9
HT_CAD IN_L9
HT_CADIN_H8
HT_CAD IN_L8
HT_CADIN_H7
HT_CAD IN_L7
HT_CADIN_H6
HT_CAD IN_L6
HT_CADIN_H5
HT_CAD IN_L5
HT_CADIN_H4
HT_CAD IN_L4
HT_CADIN_H3
HT_CADIN_H2
HT_CAD IN_L2
HT_CADIN_H1
HT_CAD IN_L1
HT_CADIN_H0
HT_CAD IN_L0
C179
C199
X_C0.22U16X
N6
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
N3
L0_CLKIN_H(0)
N2
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
U1
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
U6
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
R6
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
M4
L0_CADIN_H(11)
M5
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
M6
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
U3
L0_CADIN_H(7)
U2
L0_CADIN_L(7)
R1
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
R3
L0_CADIN_H(5)
R2
L0_CADIN_L(5)
N1
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
M1
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
C4.7U16Y1206
CPUCLKIN
CPUCLKIN#
COREFB+ [24]
COREFB- [24]
TP1
CPU_M_VREF
THERMDC_CPU [20]
THERMDA_CPU [20]
Option to SB600
R512 X_0R0402
R514 X_0R0402
C64
C50
C0.22U16X
LDT_PWRGD
LDT_STOP#
LDT_RST#
C45
X_C1000P50X
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB+
COREFB-
CPU_VTT_SENSE
CPU_TEST25_H
CPU_TEST25_L
R43 300R0402
R42 300R0402
TP10
TP11
TP13
TP8
TP18
C3300P50X0402 C58
CPU_PRESENT_L
THERM_SIC
THERM_SID
C10
D10
A8
B8
C9
D8
C7
AL3
AL6
AK6
AL10
AJ10
AH10
AL9
A5
G2
G1
E12
F12
AH11
AJ11
A10
B10
F10
E9
AJ7
F6
D6
E7
F8
C5
AH9
E5
AJ5
AG9
AG8
AH7
AJ6
CPU1D
MISC
VDDA1
VDDA2
CLKIN_H
CLKIN_L
PWROK
LDTSTOP_L
RESET_L
CPU_PRESENT_L
THERMTRIP_L
SIC
SID
TDI
TRST_L
TCK
TMS
DBREQ_L
VDD_FB_H
VDD_FB_L
VTT_SENSE
M_VREF
M_ZN
M_ZP
TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9
TEST17
TEST16
TEST15
TEST14
TEST12
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
PSI_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
80S/0805
2 1
TDO
L4
D2
VID4
D1
VID3
C1
VID2
E3
VID1
E2
VID0
E1
CPU_THRIP#_L
AK7
AL7
CPU_TDO
AK10
CPU_DBRDY
B6
CPU_VDDIOFB_H
AK11
CPU_VDDIOFB_L
AL11
CPU_PSI_L
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
VDDA25 VDDA_25
TP9
VCC_DDR
R108 300R0402
VCC_DDR
TP12
R52
80.6R1%
TP21
TP17
TP20
TP19
R18
300R0402
VCC_DDR
C160
X_C1000P50X0402
R106
300R0402
VID[0..4] [24]
VCC_DDR VCC_DDR
R510
300R0402
R511
4.7KR0402
Q45 N-MMBT3904_NL_SOT23
R111 44.2R1%
R114 44.2R1%
C161
X_C1000P50X0402
VCC_DDR
CPU_THRIP# [25]
VCCA_1V2
R105
300R0402
VCC_DDR
33 5 Friday, June 30, 2006
VCC_DDR
of
VCC3
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
MICRO-START INT'L CO.,LTD.
ATHLON64 HT I / F C TRL & DEBUG
MS-7297 0B
Q2
R617
X_4.7KR0402
2
4
6
8
10
12
14
16
18
20
22
24
26
LDT_RST# LDT_RST_L
LDT_RST_L
LDT_STOP# [10,13]
LDT_PWRGD [13]
LDT_RST# [13]
LDT_STOP#
LDT_PWRGD
LDT_RST#
LDT_STOP#
LDT_PWRGD
LDT_RST#
For SB600
RN58
1
3
5
7
8P4R-10KR
VCC_DDR
C65
CPU_M_VREF
C59
C1000P16X
R54
15/6/1
2
4
6
8
15/6/1
R57
C0.1U25Y0402-RH
Title
Size Document Number Re v
Custom
4
3
2
Date: Sheet
R618
X_1KR0402
SW1 X_SW-TACT4PS
1
2
R3
3
4
X_100R
X_N-PMBS3904_SOT23-RH
VCC_DDR
1
3
CPU_DBREQ_L
CPU_DBRDY
CPU_TCK
CPU_TMS
A A
CPU_TDI
CPU_TRST_L
CPU_TDO
5
7
9
11
13
15
17
19
21
23
J1
KEY
X__H2X13[25]_black
5
R118 1KR1%0402
R67 510R
R72 510R
1
5
4
3
2
1
MEM_MA_DQS_L[7..0] [6]
MEM_MA_DQS_H[7..0] [6]
MEM_MA_DM[7..0] [6]
MEM_MB_DQS_L[7..0] [6]
MEM_MB_DQS_H[7..0] [6]
MEM_MB_DM[7..0] [6]
D D
CPU1B
MEM_MA0_CLK_H2 [6,7]
MEM_MA0_CLK_L2 [6,7]
MEM_MA0_CLK_H1 [6,7]
MEM_MA0_CLK_L1 [6,7]
MEM_MA0_CLK_H0 [6,7]
MEM_MA0_CLK_L0 [6,7]
MEM_MA0_CS_L1 [6,7]
MEM_MA0_CS_L0 [6,7]
MEM_MA0_ODT0 [6,7]
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
AG21
AG20
G19
H19
U27
U26
AC25
AA24
AC28
AE20
AE19
G20
G21
V27
W27
AD27
AA25
AC27
C C
MEM_MA_CAS_L [6,7]
MEM_MA_WE_L [6,7]
MEM_MA_RAS_L [6,7]
MEM_MA_BANK2 [6,7]
MEM_MA_BANK1 [6,7]
MEM_MA_BANK0 [6,7]
MEM_MA_CKE0 [6,7]
MEM_MA_ADD[15..0] [6,7]
B B
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AB25
AB27
AA26
N25
Y27
AA27
M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
F19
F15
G15
AF15
AF19
AJ25
AH29
B29
E24
E18
H15
L27
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
MEM_MA_DATA18
C26
MEM_MA_DATA17
G23
MEM_MA_DATA16
F23
MEM_MA_DATA15
E22
MEM_MA_DATA14
E21
MEM_MA_DATA13
F17
MEM_MA_DATA12
G17
MEM_MA_DATA11
G22
MEM_MA_DATA10
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
J28
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DATA[63..0] [6]
MEM_MB0_CLK_H2 [6,7]
MEM_MB0_CLK_L2 [6,7]
MEM_MB0_CLK_H1 [6,7]
MEM_MB0_CLK_L1 [6,7]
MEM_MB0_CLK_H0 [6,7]
MEM_MB0_CLK_L0 [6,7]
MEM_MB0_CS_L1 [6,7]
MEM_MB0_CS_L0 [6,7]
MEM_MB0_ODT0 [6,7]
MEM_MB_CAS_L [6,7]
MEM_MB_WE_L [6,7]
MEM_MB_RAS_L [6,7]
MEM_MB_BANK2 [6,7]
MEM_MB_BANK1 [6,7]
MEM_MB_BANK0 [6,7]
MEM_MB_CKE0 [6,7]
MEM_MB_ADD[15..0] [6,7]
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AJ19
AK19
AE30
AC31
AD29
AL19
AL18
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
AA31
AA28
M31
M29
AE31
AA29
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
AJ14
AH17
AJ23
AK29
A18
A19
U31
U30
C19
D19
N31
N28
N29
N30
P29
P31
R29
R28
R31
R30
T31
T29
U29
U28
D31
C31
C24
C23
D17
C17
C14
C13
C30
A23
B17
B13
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
CPU1C
MEMORY INTERFACE B
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DATA[63..0] [6]
A A
Title
ATHLON64 DDR MEMORY I/F
Size Document Number Re v
Custom
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7297 0B
1
of
43 5 Thursday, June 29, 2006
5
4
3
2
1
VCCP
CPU1F
VDD1
A4
VDD1
A6
VDD2
AA8
VDD3
AA10
VDD4
AA12
VDD5
AA14
VDD6
AA16
VDD7
AA18
VDD8
AB7
VDD9
D D
C C
B B
AB11
AC10
AE10
AB9
AC4
AC5
AC8
AD2
AD3
AD7
AD9
AF7
AF9
AG4
AG5
AG7
AH2
AH3
E10
F11
G10
G12
H11
H23
K11
K13
K15
K17
K19
K21
K23
Y17
Y19
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
B3
VDD28
B5
VDD29
B7
VDD30
C2
VDD31
C4
VDD32
C6
VDD33
C8
VDD34
D3
VDD35
D5
VDD36
D7
VDD37
D9
VDD38
E4
VDD39
E6
VDD40
E8
VDD41
VDD42
F5
VDD43
F7
VDD44
F9
VDD45
VDD46
G6
VDD47
G8
VDD48
VDD49
VDD50
H7
VDD51
VDD52
VDD53
J8
VDD54
J12
VDD55
J14
VDD56
J16
VDD57
J18
VDD58
J20
VDD59
J22
VDD60
J24
VDD61
K7
VDD62
K9
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
L4
VDD71
L5
VDD72
L8
VDD73
L10
VDD74
L12
VDD75
VDD150
VDD151
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
VCCP
M11
M13
M15
M17
M19
N10
N12
N14
N16
N18
P11
P13
P15
P17
P19
R10
R12
R14
R16
R18
R20
U10
U12
U14
U16
U18
U20
V11
V13
V15
V17
V19
V21
W10
W12
W14
W16
W18
W20
Y11
Y13
Y15
Y21
CPU1G
L14
L16
L18
T11
T13
T15
T17
T19
T21
VDD2
VDD1
VDD2
VDD3
M2
VDD4
M3
VDD5
M7
VDD6
M9
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
N8
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
P7
VDD19
P9
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
R4
VDD26
R5
VDD27
R8
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
U8
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
V9
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
W4
VDD59
W5
VDD60
W8
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
Y2
VDD68
Y3
VDD69
Y7
VDD70
Y9
VDD71
VDD72
VDD73
VDD74
VDD75
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
VCCP
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
M21
M23
W22
L20
L22
N20
N22
P21
P23
R22
T23
U22
V23
Y23
CPU1H
VDD3
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
5
GND
6
GND
7
GND
8
GND
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
VCCP
VCC_DDR
VCCA_1V2
VTT_DDR
VCCP
C645
X_C0.22U16X
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
C648
X_C0.22U16X
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
C647
CPU1I
VDDIO
C0.22U16X
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
C649
C0.01U50X
H6
H5
H2
VTT_DDR
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
C670
X_C180P50N0402
VLDT_RUN_B
C84
C4.7U10Y0805
X_C0.01U50Y5
C73
C75
X_C0.01U50Y5
X_C0.01U50Y5
C77
C640
C635
X_C22U6.3X1206
X_C22U6.3X1206
C633
C22U6.3X1206
C22U6.3X1206
VTT_DDR
C157
C0.22U16X
A A
VTT_DDR
C238
C0.22U16X
C274
C0.22U16X
C34
C0.22U16X
C207
C4.7U10Y0805
C213
X_C4.7U10Y0805
5
C202
X_C4.7U10Y0805
C291
C4.7U10Y0805
C194
X_C180P50N0402
C187
X_C180P50N0402
C184
X_C180P50N0402
C226
C180P50N0402
C62
C1000P50X
C237
C1000P50X
C229
C1000P50X
C51
C1000P50X
C634
X_C0.22U16X
C638
C0.22U16X
C204
C0.22U16X
C263
C4.7U10Y0805
VCC_DDR VCC3
C671 C0.01U16X0402
4
3
C642
C189
C4.7U10Y0805
C627
C22U6.3X1206
X_C22U6.3X1206
EC22
+
.CD1000U6.3EL11.5-RH
C636
C22U6.3X1206
VCC_DDR VCC_DDR
C641
X_C22U6.3X1206
C646
C632
C22U6.3X1206
C133
X_C22U6.3X1206
2
C628
C22U6.3X1206
C22
C4.7U10Y0805
C639
C630
X_C22U6.3X1206
C22U6.3X1206
C631
C195
C4.7U10Y0805
C0.22U16X
Title
Size Document Number Re v
Custom
Date: Sheet
X_C22U6.3X1206
C220
C0.22U16X
ATHLON64 PWR & GND
MS-7297 0B
C629
C643
X_C22U6.3X1206
C197
C0.01U50X
C644
C22U6.3X1206
C669
C180P50N0402
MICRO-START INT'L CO.,LTD.
of
1
53 5 Thursday, June 29, 2006
5
4
3
2
1
MEM_MA_DQS_H[7..0] [4]
MEM_MA_DQS_L[7..0] [4]
D D
MEM_MA_DM[7..0] [4]
C C
MEM_MA_BANK2 [4,7]
MEM_MA_BANK1 [4,7]
MEM_MA_BANK0 [4,7]
MEM_MA_ADD[15..0] [4,7]
B B
MEM_MA0_CLK_H0 [4,7]
MEM_MA0_CLK_L0 [4,7]
MEM_MA0_CLK_H1 [4,7]
MEM_MA0_CLK_L1 [4,7]
MEM_MA0_CLK_H2 [4,7]
MEM_MA0_CLK_L2 [4,7]
MEM_MA_CKE0 [4,7]
MEM_MA_RAS_L [4,7]
MEM_MA_CAS_L [4,7]
A A
MEM_MA0_CS_L0 [4,7]
MEM_MA0_CS_L1 [4,7]
SCL CLK
SDA DATA
5
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA_CKE0
MEM_MA_RAS_L
MEM_MA_CAS_L
MEM_MA0_CS_L0
MEM_MA0_CS_L1
VCC_DDR
69
170
197
64
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
DIMM 1
ADDR=1010000B
175
VDDQ2
172
178
184
187
189
VDD1
VDD2
VDD3
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
VDD4
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
181
VDDQ3
191
194
VDDQ4
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VCC3
78
238
72
DIMM1
VDDQ1075VDDQ11
VDDSPD
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
WE_L
VREF
ODT0
ODT1
ERR_OUT_L
PAR_IN
MEM_MA_DATA63
236
MEM_MA_DATA62
235
MEM_MA_DATA61
230
MEM_MA_DATA60
229
MEM_MA_DATA59
117
MEM_MA_DATA58
116
MEM_MA_DATA57
111
MEM_MA_DATA56
110
MEM_MA_DATA55
227
MEM_MA_DATA54
226
MEM_MA_DATA53
218
MEM_MA_DATA52
217
MEM_MA_DATA51
108
MEM_MA_DATA50
107
MEM_MA_DATA49
99
MEM_MA_DATA48
98
MEM_MA_DATA47
215
MEM_MA_DATA46
214
MEM_MA_DATA45
209
MEM_MA_DATA44
208
MEM_MA_DATA43
96
MEM_MA_DATA42
95
MEM_MA_DATA41
90
MEM_MA_DATA40
89
MEM_MA_DATA39
206
MEM_MA_DATA38
205
MEM_MA_DATA37
200
MEM_MA_DATA36
199
MEM_MA_DATA35
87
MEM_MA_DATA34
86
MEM_MA_DATA33
81
MEM_MA_DATA32
80
MEM_MA_DATA31
159
MEM_MA_DATA30
158
MEM_MA_DATA29
153
MEM_MA_DATA28
152
MEM_MA_DATA27
40
MEM_MA_DATA26
39
MEM_MA_DATA25
34
MEM_MA_DATA24
33
MEM_MA_DATA23
150
MEM_MA_DATA22
149
MEM_MA_DATA21
144
MEM_MA_DATA20
143
MEM_MA_DATA19
31
MEM_MA_DATA18
30
MEM_MA_DATA17
25
MEM_MA_DATA16
24
MEM_MA_DATA15
141
MEM_MA_DATA14
140
MEM_MA_DATA13
132
MEM_MA_DATA12
131
MEM_MA_DATA11
22
MEM_MA_DATA10
21
MEM_MA_DATA9
13
DQ9
MEM_MA_DATA8
12
DQ8
MEM_MA_DATA7
129
DQ7
MEM_MA_DATA6
128
DQ6
MEM_MA_DATA5
123
DQ5
MEM_MA_DATA4
122
DQ4
MEM_MA_DATA3
10
DQ3
MEM_MA_DATA2
9
DQ2
MEM_MA_DATA1
4
DQ1
MEM_MA_DATA0
3
DQ0
MEM_MA_WE_L
73
VDDR_VREF
1
102
TEST
MEM_MA0_ODT0
195
77
55
68
19
NC1
4
MEM_MA_DATA[63..0] [4]
MEM_MA_WE_L [4,7]
MEM_MA0_ODT0 [4,7]
VDDR_VREF
C618
C0.1U16X
MEM_MB_DQS_H[7..0] [4]
MEM_MB_DQS_L[7..0] [4]
MEM_MB_DM[7..0] [4]
VCC3
MEM_MB_BANK2 [4,7]
MEM_MB_BANK1 [4,7]
MEM_MB_BANK0 [4,7]
MEM_MB_ADD[15..0] [4,7]
MEM_MB0_CLK_H0 [4,7]
MEM_MB0_CLK_L0 [4,7]
MEM_MB0_CLK_H1 [4,7]
MEM_MB0_CLK_L1 [4,7]
MEM_MB0_CLK_H2 [4,7]
MEM_MB0_CLK_L2 [4,7]
MEM_MB_CKE0 [4,7]
MEM_MB_RAS_L [4,7]
MEM_MB_CAS_L [4,7]
MEM_MB0_CS_L0 [4,7]
MEM_MB0_CS_L1 [4,7]
SCL CLK
SDA DATA
MEM_MB_DM1
3
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB_CKE0
MEM_MB_RAS_L
MEM_MB_CAS_L
MEM_MB0_CS_L0
MEM_MB0_CS_L1
VCC_DDR
69
170
172
178
184
187
189
VDD1
VDD2
VDD3
DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L
SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L
RESET_L
CKE0
CKE1
RAS_L
CAS_L
S0_L
S1_L
VDD4
164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126
46
45
114
113
105
104
93
92
84
83
37
36
28
27
16
15
7
6
101
240
239
120
119
54
190
71
173
174
196
176
57
70
177
179
58
180
60
61
182
63
183
188
168
167
162
161
49
48
43
42
185
186
137
138
220
221
18
52
171
192
74
193
76
175
197
64
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
DIMM 2
ADDR=1010001B
181
VDDQ3
191
VDDQ4
194
VDDQ5
72
VDDQ651VDDQ756VDDQ862VDDQ9
VCC3
78
VDDQ1075VDDQ11
238
VDDSPD
WE_L
VREF
ODT0
ODT1
ERR_OUT_L
PAR_IN
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
TEST
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
NC1
DIMM2
2
236
235
230
229
117
116
111
110
227
226
218
217
108
107
99
98
215
214
209
208
96
95
90
89
206
205
200
199
87
86
81
80
159
158
153
152
40
39
34
33
150
149
144
143
31
30
25
24
141
140
132
131
22
21
13
12
129
128
123
122
10
9
4
3
73
1
102
195
77
55
68
19
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_WE_L
VDDR_VREF
MEM_MB0_ODT0
MEM_MB_DATA[63..0] [4]
MEM_MB_WE_L [4,7]
VDDR_VREF
C619
C0.1U16X
MEM_MB0_ODT0 [4,7]
SCL
SCL [12,14,20,21,25]
SDA [12,14,20,21,25]
R145 33R
SDA
R154 33R
SCL CLK
SDA DATA
VCC_DDR
R24
56.2R1%
X_C0.1U25Y0402-RH
R22
56.2R1%
Title
FIRST LOGIC AL DDR DIMM
Size Document Number Rev
Custom
Date: Sheet
VDDR_VREF
C19
VDDR_VREF
C620
C1000P50X
MICRO-START INT'L CO.,LTD.
MS-7297 0B
1
63 5 Thursday, June 29, 2006
of
5
4
3
2
1
VTT_DDR
MEM_MB_BANK2
RN15 8P4R-47R0402
1
MEM_MB_BANK2 [4,6]
MEM_MA_BANK2 [4,6]
MEM_MB_ADD12 [4,6]
MEM_MB_ADD9 [4,6]
MEM_MA_ADD9 [4,6]
MEM_MB_ADD11 [4,6]
D D
C C
MEM_MB_ADD7 [4,6]
MEM_MB_ADD8 [4,6]
MEM_MB_ADD3 [4,6]
MEM_MA_ADD1 [4,6]
MEM_MB_ADD1 [4,6]
MEM_MB_ADD2 [4,6]
MEM_MA_ADD5 [4,6]
MEM_MA_ADD4 [4,6]
MEM_MA_ADD3 [4,6]
MEM_MA_ADD2 [4,6]
MEM_MB_RAS_L [4,6]
MEM_MA_RAS_L [4,6]
MEM_MB0_CS_L0 [4,6]
MEM_MB_WE_L [4,6]
MEM_MA_BANK0 [4,6]
MEM_MB_BANK1 [4,6]
MEM_MB_ADD10 [4,6]
MEM_MB_BANK0 [4,6]
MEM_MA0_ODT0 [4,6]
MEM_MA_ADD13 [4,6]
MEM_MA0_CS_L1 [4,6]
MEM_MA_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MA_ADD9
MEM_MB_ADD11
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD3
MEM_MA_ADD1
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MB_RAS_L
MEM_MA_RAS_L
MEM_MB0_CS_L0
MEM_MB_WE_L
MEM_MA_BANK0
MEM_MB_BANK1
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MA0_ODT0
MEM_MA_ADD13
MEM_MA0_CS_L1
RN16 8P4R-47R0402
RN18 8P4R-47R0402
RN20 8P4R-47R0402
RN23 8P4R-47R0402
RN22 8P4R-47R0402
RN26 8P4R-47R0402
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
MEM_MA0_CLK_H2 [4,6]
MEM_MA0_CLK_L2 [4,6]
MEM_MA0_CLK_H1 [4,6]
MEM_MA0_CLK_L1 [4,6]
MEM_MA0_CLK_H0 [4,6]
MEM_MA0_CLK_L0 [4,6]
MEM_MB0_CLK_H2 [4,6]
MEM_MB0_CLK_L2 [4,6]
MEM_MB0_CLK_H1 [4,6]
MEM_MB0_CLK_L1 [4,6]
MEM_MB0_CLK_H0 [4,6]
MEM_MB0_CLK_L0 [4,6]
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
C182
C1.5P50N0402
C63
C1.5P50N0402
C107
C1.5P50N0402
C173
C1.5P50N0402
C47
C1.5P50N0402
C113
C1.5P50N0402
C0.1U25Y0402-RH
VTT_DDR
C224
C0.1U25Y0402-RH
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
C0.1U25Y0402-RH
C165
C22P50N0402 C93
C22P50N0402 C90
C22P50N0402 C185
C22P50N0402 C99
C22P50N0402 C100
C22P50N0402 C141
C22P50N0402 C106
C22P50N0402 C110
C22P50N0402 C105
C22P50N0402 C115
C22P50N0402 C108
C22P50N0402 C114
C22P50N0402 C120
C22P50N0402 C126
C22P50N0402 C131
C22P50N0402 C143
C22P50N0402 C154
C22P50N0402 C162
C22P50N0402 C145
C22P50N0402 C96
C22P50N0402 C146
C22P50N0402 C151
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
Decoupling Between Processor and DIMMs
Layout: Spread out on VTT pour
C0.1U25Y0402-RH
C147
C221
C0.1U25Y0402-RH
C0.1U25Y0402-RH
C188
C232
C0.1U25Y0402-RH
C223
C0.1U25Y0402-RH
C0.1U25Y0402-RH
C192
C305
C88
X_C0.1U25Y0402-RH
C0.1U25Y0402-RH
C102
X_C0.1U25Y0402-RH
C216
C0.1U25Y0402-RH
C22P50N0402 C101
C22P50N0402 C98
C22P50N0402 C190
C22P50N0402 C109
C22P50N0402 C111
C22P50N0402 C163
C22P50N0402 C117
C22P50N0402 C124
C22P50N0402 C116
C22P50N0402 C129
C22P50N0402 C121
C22P50N0402 C128
X_C22P50N0402 C132
C22P50N0402 C135
C22P50N0402 C138
C22P50N0402 C150
C22P50N0402 C170
C22P50N0402 C176
C22P50N0402 C168
C22P50N0402 C104
C22P50N0402 C153
C22P50N0402 C159
C85
C123
C0.1U25Y0402-RH
VCC_DDR VCC_DDR
C0.1U25Y0402-RH
C144
C119
C0.1U25Y0402-RH
VTT_DDR
VTT_DDR
MEM_MA_ADD14
RN14 8P4R-47R0402
1
MEM_MA_ADD14 [4,6]
MEM_MB_ADD15 [4,6]
MEM_MA_ADD15 [4,6]
MEM_MB_ADD14 [4,6]
MEM_MA_ADD8 [4,6]
MEM_MB_ADD6 [4,6]
MEM_MB_ADD5 [4,6]
MEM_MB_ADD4 [4,6]
B B
A A
MEM_MA_ADD12 [4,6]
MEM_MA_ADD11 [4,6]
MEM_MA_ADD7 [4,6]
MEM_MA_ADD6 [4,6]
MEM_MA_ADD0 [4,6]
MEM_MA_ADD10 [4,6]
MEM_MB_ADD0 [4,6]
MEM_MA_BANK1 [4,6]
MEM_MB0_ODT0 [4,6]
MEM_MB_ADD13 [4,6]
MEM_MB0_CS_L1 [4,6]
MEM_MA_CKE0 [4,6]
MEM_MB_CKE0 [4,6]
MEM_MA0_CS_L0 [4,6]
MEM_MB_CAS_L [4,6]
MEM_MA_WE_L [4,6]
MEM_MA_CAS_L [4,6]
MEM_MB_ADD15
MEM_MA_ADD15
MEM_MB_ADD14
MEM_MA_ADD8
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD0
MEM_MA_ADD10
MEM_MB_ADD0
MEM_MA_BANK1
MEM_MB0_ODT0
MEM_MB_ADD13
MEM_MB0_CS_L1
MEM_MA_CKE0
MEM_MB_CKE0
MEM_MA0_CS_L0
MEM_MB_CAS_L
MEM_MA_WE_L
MEM_MA_CAS_L
RN17 8P4R-47R0402
RN19 8P4R-47R0402
RN21 8P4R-47R0402
RN24 8P4R-47R0402
RN13 8P4R-47R0402
RN25 8P4R-47R0402
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
C0.1U25Y0402-RH
C94
C92
C0.1U25Y0402-RH
VCC_DDR
C0.1U25Y0402-RH
C67
C66
C0.1U25Y0402-RH
C0.1U25Y0402-RH
C721
C0.1U25Y0402-RH
C767
C180P50N0402
C768
C180P50N0402
C769
C180P50N0402
C770
C180P50N0402
C771
C180P50N0402
C772
C180P50N0402
C773
C180P50N0402
C774
C180P50N0402
C775
C180P50N0402
C722
C0.1U25Y0402-RH
C273
C723
C0.1U25Y0402-RH
C724
C0.1U25Y0402-RH
For EMI solution
C0.1U25Y0402-RH
C725
C97
C0.1U25Y0402-RH
C0.1U25Y0402-RH
C726
C140
C0.1U25Y0402-RH
C0.1U25Y0402-RH
C155
VCC_DDR
Title
DDR Terminatior
Size Document Number R ev
Custom
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7297 0B
73 5 Thursday, June 29, 2006
1
of
5
4
3
2
1
D D
C C
B B
VDDHT_PKG
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
HT_CLKOUT_H1 [3]
HT_CLKOUT_L1 [3]
HT_CLKOUT_H0 [3]
HT_CLKOUT_L0 [3]
HT_CTLOUT_H0 [3]
HT_CTLOUT_L0 [3]
49.9R1%0402
R152 49.9R1%0402
R137
HT_RXCALN
HT_RXCALP
R19
R18
R21
R22
U22
U21
U18
U19
W19
W20
AC21
AB22
AB20
AA20
AA19
Y19
T24
R25
U25
U24
V23
U23
V24
V25
AA25
AA24
AB23
AA23
AB24
AB25
AC24
AC25
W21
W22
Y24
W25
P24
P25
A24
C24
U12A
HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N
HT_RXCLK1P
HT_RXCLK1N
HT_RXCLK0P
HT_RXCLK0N
HT_RXCTLP
HT_RXCTLN
HT_RXCALP
HT_RXCALN
PART 1 OF 5
HYPER TRANSPORT I/F
HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N
HT_TXCLK1P
HT_TXCLK1N
HT_TXCLK0P
HT_TXCLK0N
HT_TXCTLP
HT_TXCTLN
HT_TXCALP
HT_TXCALN
P21
P22
P18
P19
M22
M21
M18
M19
L18
L19
G22
G21
J20
J21
F21
F22
N24
N25
L25
M24
K25
K24
J23
K23
G25
H24
F25
F24
E23
F23
E24
E25
L21
L22
J24
J25
N23
P23
C25
D24
HT_TXCALP
HT_TXCALN
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
HT_CLKIN_H1 [3]
HT_CLKIN_L1 [3]
HT_CLKIN_H0 [3]
HT_CLKIN_L0 [3]
HT_CTLIN_H0 [3]
HT_CTLIN_L0 [3]
R138 100R1%0402
ATI-RS485MC-216MCA4ALA12FG-A12
HT_CADIN_H[15..0] [3]
HT_CADIN_L[15..0] [3]
HT_CADOUT_ H[1 5..0 ] [3]
HT_CADOUT_L[15..0] [3]
A A
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOU T_H [15 ..0]
HT_CADOUT_L[15..0]
MICRO-START INT'L CO.,LTD.
Title
RS485 HT LINK I/F
Size Docu me nt Number Rev
Custom
5
4
3
Date: Sheet
MS-7297 0B
2
83 5 Thursday, June 29, 2006
1
of
A
W11
W12
AA11
AB11
W14
W15
AA12
AB12
AA14
AB14
AB7
AB6
AA7
AB9
AA9
G5
G4
J8
J7
J4
J5
L8
L7
L4
L5
M8
M7
M4
M5
P8
P7
P4
P5
R4
R5
R7
R8
U4
U5
W4
W5
Y4
Y5
V9
W9
Y7
PED_RX0 [19]
PED_RX0* [19]
PED_RX1 [19]
PED_RX1* [19]
PED_RX2 [19]
PED_RX2* [19]
4 4
3 3
2 2
A_RX2P [13]
A_RX2N [13]
A_RX3P [13]
A_RX3N [13]
PE0_RX [19]
PE0_RX* [19]
A_RX0P [13]
A_RX0N [13]
A_RX1P [13]
A_RX1N [13]
PED_RX3 [19]
PED_RX3* [19]
PED_RX4 [19]
PED_RX4* [19]
PED_RX5 [19]
PED_RX5* [19]
PED_RX6 [19]
PED_RX6* [19]
PED_RX7 [19]
PED_RX7* [19]
PED_RX8 [19]
PED_RX8* [19]
PED_RX9 [19]
PED_RX9* [19]
PED_RX10 [19]
PED_RX10* [19]
PED_RX11 [19]
PED_RX11* [19]
PED_RX12 [19]
PED_RX12* [19]
PED_RX13 [19]
PED_RX13* [19]
PED_RX14 [19]
PED_RX14* [19]
PED_RX15 [19]
PED_RX15* [19]
A_RX2P
A_RX2N
A_RX3P
A_RX3N
PE0_RX
PE0_RX*
R184 10KR0402
*
R189 8.25KR1%
*
U12B
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
PCEH_ISET
PCEH_TXISET
B
PART 2 OF 5
PCIE GFX I/F
PCIE I/F GPP
PCIE I/F SB
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
PCEH_PCAL
PCEH_NCAL
J1
H2
K2
K1
K3
L3
L1
L2
N2
N1
P2
P1
P3
R3
R1
R2
T2
U1
V2
V1
V3
W3
W1
W2
Y2
AA1
AA2
AB2
AB1
AC1
AE3
AE4
A_TX2P0
AD8
A_TX2N0
AE8
A_TX3P0
AD7
A_TX3N0
AE7
AD4
AE5
AD5
AD6
A_TX0P_C
AE9
A_TX0N_C
AD10
A_TX1P_C
AC8
A_TX1N_C
AD9
R191 150R1%0402
AD11
R195 100R1%0402
AE11
PE0_TX
PE0_TX*
PED_TX0 [19]
PED_TX0* [19]
PED_TX1 [19]
PED_TX1* [19]
PED_TX2 [19]
PED_TX2* [19]
PED_TX3 [19]
PED_TX3* [19]
PED_TX4 [19]
PED_TX4* [19]
PED_TX5 [19]
PED_TX5* [19]
PED_TX6 [19]
PED_TX6* [19]
PED_TX7 [19]
PED_TX7* [19]
PED_TX8 [19]
PED_TX8* [19]
PED_TX9 [19]
PED_TX9* [19]
PED_TX10 [19]
PED_TX10* [19]
PED_TX11 [19]
PED_TX11* [19]
PED_TX12 [19]
PED_TX12* [19]
PED_TX13 [19]
PED_TX13* [19]
PED_TX14 [19]
PED_TX14* [19]
PED_TX15 [19]
PED_TX15* [19]
C347 C0.1U16Y0402
C345 C0.1U16Y0402
C354 C0.1U16Y0402
C350 C0.1U16Y0402
*
*
C
C322 C0.1U16Y0402
C316 C0.1U16Y0402
C341 C0.1U16Y0402
C338 C0.1U16Y0402
VDDA12_PKG2
A_TX2P [13]
A_TX2N [13]
A_TX3P [13]
A_TX3N [13]
PE0_TX [19]
PE0_TX* [19]
A_TX0P [13]
A_TX0N [13]
A_TX1P [13]
A_TX1N [13]
D
E
ATI-RS485MC-216MCA4ALA12FG-A12
AVIOD STUB
RS690/485 2/4-LANE ALINK CONFIGURATION
AVIOD STUB
RS690/485 2/4-LANE ALINK CONFIGURATION
RS690/RS485 CHANGE TABLE
1 1
RS690
RS485
R189 NB/DIFF
DNI
8.25K
A
R184
10K
R195 R191
2K 562R 1.47K
150R 82.5R
Title
RS485 PCIE I/F
Size Document Number R ev
Custom
B
C
D
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7297 0B
93 5 Thursday, June 29, 2006
E
of