MSI MS-7278 Schematics
5
1
Cover Sheet
2 System Block Diagram
Intel LGA775 CPU - Signals
D D
C C
B B
A A
3
Intel LGA775 CPU - Power
4
Intel LGA775 CPU - GND
5
6
Intel Broadwater - CPU Signal
Intel Broadwater - Memory
7
Intel Broadwater - PCI Express
8
9
Intel Broadwater - GND
Intel ICH8 DH - 1
10
11
Intel ICH8 DH - 2
12
Intel ICH8 DH - 3
13
Clock Gen. - ICS9LPRS512
Super I/O - Winbond W83627EHG ver:H
14
15
Azalia Codec - ALC883/882
16
Lan - Intel Intel Neneveh / Ekron
17
DDRII DIMM 1 & 2
18
DDRII DIMM 3 & 4
19
DDRII Termination
20
PCI - Express x16
21
LPT / COM / KB / MS
22
USB / SATA Connectors
23
BTX Connector & Front Panel
24
ACPI Controller - MS7
25
Power Regulator - MS11
26
VRM 11 - Intersil 6312 / 6322
27
FAN Controller
28
D-Sub Connector
29
IEEE 1394 - VIA 6307 / 6308
30
EMI Solution
31
Manual Parts
32
GPIO & Jumper Setting
33
Syatem Power OK Map
34
Syatem Power Delivery
35
Syatem Reset Diagram
36
System Clock Diagram
37 Project History
5
4
MS-7278
CPU :
Intel Conroe Family Processor
Intel Pentium D Processor 900 and 800 Sequence
Intel Pentium 4 Processor 600 Sequence
System Chipset :
Intel G965 - GMCH (North Bridge)
Intel ICH8 DH (South Bridge)
On Board Chipset :
Clock Gen. -- ICS9LPRS512
Azalia Codec - ALC883 / 882
LAN -- Intel Neneveh / Ekron
VRM 11 - Intersil 6312 / 6322
ACPI Controller -- MS7
IEEE 1394 -- VIA 6307 / 6308
Super I/O -- Winbond W83627EHG ver:H / W83627DHG
SPI Flash 8Mb / 16Mb
Main Memory :
2 Channel DDR II * 4 (Max 8GB)
Expansion Slot :
PCI Express x16 Slot * 1
Intel G965 + ICH8 DH + Intel 82566DC + ALC883 + VIA6307 + W83627 EHG ver:HCfg-7278-017278-01S
Cfg-7278-02 Intel G965 + ICH8 DH + Intel 82562V + ALC883 + VIA6307 + W83627 DHG L7278-02S
4
3
2
1
pico BTX Platform
Version : 100
PlatForm or OptionConfig ItemERP No.
3
Option Select
STD
2
Title
Size Document Number Rev
Date: Sheet
MICRO-START INT'L CO.,LTD.
Cover Sheet
MS-7278
1
of
137Friday, August 18, 2006
100
5
4
3
2
1
VRD 11 / 775_VR_Config_05A
Intersil 6312 / 6322 3 Phase PWM
D D
Intel LGA775 Processor
FSB 533/800/1066MHz
PCI Express x16
Graphics Slot
PCI Express x16
Intel Broadwater
GMCH (G965)
D-Sub Connector
C C
Channel A
Channel B
DDR2DDR2
DDR2DDR2
533/667/800 MHz
DMI Interface Controller Link
SMBus 2.0 / I2C
SATA1
SATA2
SATA3
SATA4
4 port SATA 2.0
PCI Express x1
MS11 Power Regulator
MS7 ACPI Controller
Intel ICH8 DH
Intel Neneveh / Ekron
PCI Bus
GPIO
VIA IEEE 1394
B B
AC Link
Azalia Codec
10 port USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
SPI Flash
LPC Interface
PS2
Mouse / KeyBoard
Winbond Super I/O
COM Port
W83627 EHG ver:H
Fan Controller
A A
5
4
W83627DHG
3
Parallel Port
2
Title
Size Document Number Rev
Date: Sheet
MICRO-START INT'L CO.,LTD.
System Block Diagram
MS-7278
1
of
237Wednesday, August 16, 2006
100
5
Intel LGA775 CPU - Signals
H_A#[3..35]6
H_A#31
H_A#30
H_A#28
H_A#29
H_A#27
H_A#32
H_A#33
H_A#34
D53#
B15
C14
H_D#53
H_D#52
D52#
D51#
C15
H_D#51
D50#
A14
D17
H_D#50
H_D#49
H_A#35
AJ6
A35#
D49#
D48#
D20
H_D#48
AJ5
AH5
A34#
D47#
D22
G22
H_D#47
H_D#46
AH4
A33#
A32#
D46#
D45#
E22
H_D#45
AG5
AG4
A31#
D44#
F21
G21
H_D#44
H_D#43
AG6
A30#
A29#
D43#
D42#
E21
H_D#42
AF4
A28#
D41#
F20
H_D#41
H_D#40
D D
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
U19A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
H_DBI#[0..3]6
CPU_GTLREF24
H_IERR#4
H_FERR#4,10
H_STPCLK#10
H_INIT#10
H_DBSY#6
H_DRDY#6
H_TRDY#6
H_ADS#6
H_LOCK#6
H_BNR#6
H_HIT#6
H_HITM#6
H_BPRI#6
C C
B B
H_DEFER#6
TRMTRIP#4,10
H_PROCHOT#4
H_IGNNE#10
ICH_H_SMI#10
H_A20M#10
VTT_OUT_LEFT4,5
VTT_OUT_LEFT4,5
CPU_GTLREF34
H_SLP#10
H_D#[0..63]6
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
THERMDACPU
THERMDCCPU
R552 51R0402
BPM#1
R551 51R0402
CPU_BSEL013
CPU_BSEL113
CPU_BSEL213
H_PWRGD4,11
H_CPURST#4,6
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
AF5
A27#
D40#
E19
H_A#25
H_A#26
AB4
AC5
A26#
D39#
F18
E18
H_D#39
H_D#38
H_A#24
AB5
A25#
A24#
D38#
D37#
F17
H_D#37
H_A#22
H_A#23
AA5
AD6
A23#
D36#
G17
G18
H_D#35
H_D#36
4
H_A#21
AA4
A22#
A21#
D35#
D34#
E16
H_D#34
H_A#19
H_A#20
H_A#18
A20#Y4A19#Y6A18#W6A17#
D33#
D32#
D31#
E15
G16
G15
H_D#31
H_D#32
H_D#33
H_A#17
H_A#16
H_A#15
H_A#14
H_A#13
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D30#
D29#
D28#
D27#
D26#
F15
F14
E13
G14
G13
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_A#12
H_A#11
D25#
F12
D13
H_D#24
H_D#25
H_A#10
U6
D24#
F11
H_D#23
H_A#8
H_A#6
H_A#5
H_A#7
H_A#9
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_A#4
H_A#3
L5
H_D#16
H_D#17
AC2
D11
C12
H_D#14
H_D#15
DBR#
D14#
D13#
B12
H_D#13
CPU_VSS_VRM_SENSE
AJ3
AN4
AN3
AN6
AN5
ITP_CLK1
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D12#D8D11#
D10#
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
B10
A11
A10
C11
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
3
R137 X_1KR1%0402
EC1
X_C10U6.3X51206
VID0
VID1
VID3
VID5
VID2
VID4
VID7
VID6
AM7
AM5
AL4
AK4
AL6
AM3
AL5
VID6#
VID5#
VID_SELECT
GTLREF_SEL
H_D#1
H_D#2
H_D#3
AM2
VID4#
VID3#
VID2#
VID1#
VID0#
GTLREF0
GTLREF1
GTLREF2
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
RSVD#G6
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
ZIF-SOCK775-15u-in
B4
H_D#0
AK3
ITP_CLK0
H_D#5
H_D#6
RSVD#AM7
H_D#4
R1 0R0402
R6 0R0402
VID[0..7] 26
VTT_OUT_RIGHT
R7
680R0402
AN7
CPU_GTLREF0
H1
CPU_GTLREF1
H2
H29
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
H_TESTHI09
G4
H_TESTHI08
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
RSVD_AK6
AK6
RSVD_G6
G6
G28
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
U3
U2
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
FP_RST# 11,13,23
VCC_VRM_SENSE 26
VSS_VRM_SENSE 26
VRD_VIDSEL 26
CPU_GTLREF0 4
CPU_GTLREF1 4
CPU_MCH_GTLREF 6
R534 X_0R0402
R535 X_0R0402
R536 X_0R0402
R538 X_0R0402
PECI 10,14
H_REQ#[0..4] 6
RN5 8P4R-51R0402
R611 51R0402
R9 51R0402
R10 51R0402
R11 51R0402
R13 X_130R1%0402
R12 X_62R0402
CK_H_CPU# 13
CK_H_CPU 13
H_RS#[0..2] 6
TP21
TP20
R16 49.9R1%0402
R17 49.9R1%0402
R19 49.9R1%0402
R18 49.9R1%0402
R20 49.9R1%0402
R21 49.9R1%0402
TP18
TP22
TP19
TP23
H_ADSTB#1 6
H_ADSTB#0 6
H_DSTBP#3 6
H_DSTBP#2 6
H_DSTBP#1 6
H_DSTBP#0 6
H_DSTBN#3 6
H_DSTBN#2 6
H_DSTBN#1 6
H_DSTBN#0 6
H_NMI 10
H_INTR 10
H_TESTHI08
H_TESTHI09
BPM#1
H_TESTHI12 5
1
2
3
4
5
6
7
8
TP24
BPM#0 5
C3
C0.1U16Y0402
2
VTT_OUT_LEFT
V_FSB_VTT
VTT_OUT_RIGHT 4,5
VTT_OUT_LEFT 4,5
H_BR#0 4,6
VTT_OUT_LEFT 4,5
1
THERMDACPUCPU_VCC_VRM_SENSE
THERMDCCPU
VTT_OUT_RIGHT
VTT_OUT_RIGHT
R3 0R0402
R5 0R0402
VID7
1
2
VID3
3
4
VID6
5
6
VID1
7
8
RN1 8P4R-680R
VID2
1
2
VID0
3
4
VID5
5
6
VID4
7
8
RN2 8P4R-680R
R139 51R0402
R149 51R0402
R596 X_62R0402
R272 62R0402
VTT_OUT_RIGHT
C1
C0.1U16Y0402
RN3
8P4R-51R0402
1
2
3
4
5
6
7
8
RN4 8P4R-62R0402
1
2
3
4
5
6
7
8
PLACE BPM TERMINATION NEAR CPU
THERMDA_CPU 14
THERMDC_CPU 14
C2
C0.1U16Y0402
H_BPM#2
H_BPM#3
H_BPM#0
H_BPM#1
H_BPM#4
H_BPM#5
H_TDO
H_TMS
H_TDI
H_TRST#
H_TCK
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
Intel LGA775 CPU - Signals
MS-7278
1
of
337Wednesday, August 16, 2006
100
5
VCCP
AF9
AF8
AF22
AF21
U19B
VCCP
D D
C C
AF19
AF18
AF15
AF14
AF12
AF11
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
VCCP
AE9
AB8
AA8
VCC#AF19
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8
VCC#AF22
VCC#AF21
VCC#Y30
VCC#Y8
Y8
Y29
Y30
VCC#AF9
VCC#AF8
VCC#Y28
VCC#Y29
Y28
AG14
AG12
AG11
VCC#AG14
VCC#AG12
VCC#AG11
VCC#Y25
VCC#Y26
VCC#Y27
Y25
Y26
Y27
AG19
AG18
AG15
VCC#AG19
VCC#AG18
VCC#AG15
VCC#W8W8VCC#Y23
VCC#Y24
Y23
Y24
AG21
VCC#AG21
VCC#W30
W30
AG26
AG25
AG22
VCC#AG25
VCC#AG22
VCC#W28
VCC#W29
W27
W28
W29
AG29
AG28
AG27
VCC#AG28
VCC#AG27
VCC#AG26
VCC#W25
VCC#W26
VCC#W27
W24
W25
W26
AG30
AG9
AG8
VCC#AG8
VCC#AG30
VCC#AG29
VCC#V8
VCC#W23
VCC#W24
V8
U8
W23
AH12
AH11
VCC#AG9
VCC#AH12
VCC#AH11
VCC#U29
VCC#U30
VCC#U8
U29
U30
AH18
AH15
AH14
VCC#AH18
VCC#AH15
VCC#AH14
VCC#U26
VCC#U27
VCC#U28
U26
U27
U28
AH22
AH21
AH19
VCC#AH22
VCC#AH21
VCC#AH19
VCC#U23
VCC#U24
VCC#U25
U23
U24
U25
AH27
AH26
AH25
VCC#AH27
VCC#AH26
VCC#AH25
VCC#T29
VCC#T30
VCC#T8
T8
T29
T30
AH28
AH29
AH30
VCC#AH28
VCC#AH29
VCC#AH30
VCC#T26
VCC#T27
VCC#T28
T26
T27
T28
AH8
AH9
AJ11
VCC#AH8
VCC#AH9
VCC#T24
VCC#T25
T23
T24
T25
4
AJ12
AJ14
VCC#AJ11
VCC#AJ12
VCC#AJ14
VCC#P8
VCC#R8
VCC#T23
P8
R8
AJ15
AJ18
VCC#AJ15
VCC#N8
N8
N30
AJ19
AJ21
VCC#AJ18
VCC#AJ19
VCC#AJ21
VCC#N28
VCC#N29
VCC#N30
N28
N29
AJ22
AJ25
VCC#AJ22
VCC#AJ25
VCC#N26
VCC#N27
N26
N27
AJ8
AJ26
VCC#AJ8
VCC#AJ26
VCC#N24
VCC#N25
N24
N25
AJ9
AK11
VCC#AJ9
VCC#AK11
VCC#M8
VCC#N23
M8
N23
AK12
AK14
AK15
VCC#AK12
VCC#AK14
VCC#AK15
VCC#M28
VCC#M29
VCC#M30
M28
M29
M30
AK18
AK19
AK21
VCC#AK18
VCC#AK19
VCC#AK21
VCC#M25
VCC#M26
VCC#M27
M25
M26
M27
AK22
AK25
AK26
VCC#AK22
VCC#AK25
VCC#AK26
VCC#L8
VCC#M23
VCC#M24
L8
M23
M24
AK8
AK9
VCC#AK8
VCC#AK9
VCC#K30
VCC#K8
K8
K30
AL11
AL12
AL14
VCC#AL11
VCC#AL12
VCC#K28
VCC#K29
K27
K28
K29
AL15
AL18
AL19
VCC#AL14
VCC#AL15
VCC#AL18
VCC#K25
VCC#K26
VCC#K27
K24
K25
K26
AL21
AL22
AL25
VCC#AL19
VCC#AL21
VCC#AL22
VCC#J9
VCC#K23
VCC#K24
J8
J9
K23
AL26
AL29
AL30
VCC#AL25
VCC#AL26
VCC#AL29
VCC#J29
VCC#J30
VCC#J8
J28
J29
J30
3
AL8
AL9
AM11
VCC#AL8
VCC#AL9
VCC#AL30
VCC#J26
VCC#J27
VCC#J28
J25
J26
J27
AM12
AM14
AM15
VCC#AM11
VCC#AM12
VCC#AM14
VCC#AM15
VCC#J22
VCC#J23
VCC#J24
VCC#J25
J22
J23
J24
AM18
AM19
AM21
VCC#AM18
VCC#AM19
VCC#AM21
VCC#J19
VCC#J20
VCC#J21
J19
J20
J21
AM22
AM25
AM26
VCC#AM22
VCC#AM25
VCC#AM26
VCC#J14
VCC#J15
VCC#J18
J14
J15
J18
AM8
AM29
AM30
VCC#AM8
VCC#AM29
VCC#AM30
VCC#J11
VCC#J12
VCC#J13
J11
J12
J13
AM9
AN11
AN12
VCC#AM9
VCC#AN11
VCC#AN9
VCC#J10
J10
AN8
AN9
AN14
AN15
AN18
VCC#AN12
VCC#AN14
VCC#AN15
VCC#AN18
VTT_OUT_RIGHT
VCC#AN26
VCC#AN29
VCC#AN30
VCC#AN8
AN26
AN29
AN30
AN19
AN21
AN22
VCCA
VSSA
VCC#AN19
VCC#AN21
VCC#AN22
VCCPLL
VCC-IOPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTTPWRGD
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC#AN25
1122334
AN25
A23
B23
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
ZIF-SOCK775-15u-in
4
2
H_VCCA
H_VSSA
H_VCCPLL
H_VCCIOPLL
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
C4
C10U10Y0805
C5
X_C22U6.3X1206
CAPS FOR FSB GENERIC
VTT_SEL 24
C6
C10U10Y0805
1
GTLREF Voltage Should Be 0.63 * VTT = 0.756V
VTT_OUT_RIGHT
B B
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
A A
R22 124R1%0402
R28 124R1%0402
R546 X_124R1%0402
R545 X_124R1%0402
R24
210R1%0402
R30
210R1%0402
R548
X_210R1%0402
R549
X_210R1%0402
R23 10R1%0402
C7
C1U10X
R29 10R1%0402
C12
C1U10X
R543 X_10R1%0402
C629
X_C1U10X
R544 X_10R1%0402
C630
X_C1U10X
CPU_GTLREF0 3
C8
C220P50N0402
CPU_GTLREF1 3
C13
C220P50N0402
C617
X_C220P50N0402
C616
X_C220P50N0402
CPU_GTLREF2 3
R537
X_0R0402
For Cost-Down Reserved
CPU_GTLREF3 3
For Qusd-Core CPU GTL-REF circuit reserved
5
4
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
L1 10U155m_0806
V_FSB_VTT
L2 10U155m_0806
V_1P5_ICH
VID_GD#24
L40 X_10U155m_0806
CP18 X_COPPER
VTT_OUT_LEFT
VCC5_SB
R39
1KR1%0402
R42 1KR1%0402
R25
0R0402
C9
C10U10Y0805
B
3
R38
680R0402
CE
Q3
N-SST3904_SOT23
C10
C10U10Y0805
C14
C1U16Y
1.25V VTT_PWRGOOD
C16
X_C1U16Y
H_VCCIOPLL
H_VCCA
C11
C1U16Y
H_VSSA
H_VCCPLL
C15
C1U16Y
H_PROCHOT#3
VTT_PWG 26
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
R31 10KR0402
2
VTT_OUT_RIGHT3,5
VTT_OUT_LEFT3,5
V_FSB_VTT
R32 X_0R0402
PLACE AT CPU END OF ROUTE
R33 X_130R1%0402
R34 62R0402
R35 X_100R0402
R37 62R0402
R36 62R0402
H_PROCHOT# 3
H_IERR# 3
H_PWRGD 3,11
H_BR#0 3,6
H_CPURST# 3,6
PLACE AT ICH END OF ROUTE
R40 62R0402
R41 62R0402
VCC3
R26
10KR0402
Q1
N-SST3904_SOT23
Title
Size Document Number Rev
Date: Sheet
Q2
N-SST3904_SOT23
MICRO-START INT'L CO.,LTD.
Intel LGA775 CPU - Power
MS-7278
TRMTRIP# 3,10
H_FERR# 3,10
Pull high in RN7
1
THERM# 10,11,14
100
of
437Monday, August 21, 2006
5
VTT_OUT_RIGHT3,4
4
3
2
1
V26
V25
VSS#V26
VSS#V25
VSS#AH6
VSS#AH7
AH6
AH7
V24
V23
VSS#V24
VSS#V23
VSS#AJ10
VSS#AJ13
AJ10
AJ13
AJ16
R587 0R0402
R618 X_1KR1%0402
R30
R29
R28
T3
U1
R5
VSS#T7T7VSS#T6T6VSS#T3
VSS#U7U7VSS#U1
VSS#R7R7VSS#R5
VSS#R30
VSS#R29
VSS#AJ16
VSS#AJ17
VSS#AJ20
VSS#AJ23
VSS#AJ24
VSS#AJ27
VSS#AJ28
VSS#AJ29
VSS#AJ30
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AJ17
AJ20
R27
R26
VSS#R28
VSS#R27
VSS#R26
VSS#AJ4
VSS#AJ7
VSS#AK10
AJ7
AK10
R25
R24
R23
VSS#R25
VSS#R24
VSS#AK13
VSS#AK16
AK13
AK16
AK17
H_TESTHI12 3
P4
P30
R2
VSS#P7P7VSS#P4
VSS#R2
VSS#R23
VSS#AK17
VSS#AK2
VSS#AK20
VSS#AK23
AK2
AK20
AK23
AK24
P29
P28
P27
VSS#P30
VSS#P29
VSS#P28
VSS#AK24
VSS#AK27
VSS#AK28
AK27
AK28
AK29
P26
P25
P24
VSS#P27
VSS#P26
VSS#P25
VSS#AK29
VSS#AK30
VSS#AK5
AK5
AK7
AK30
P23
VSS#N7N7VSS#N6N6VSS#N3
VSS#P24
VSS#P23
VSS#AK7
VSS#AL10
VSS#AL13
AL10
AL13
N3
VSS#AL16
VSS#AL17
AL16
AL17
AL20
M1
L6
VSS#L7L7VSS#L6
VSS#M7M7VSS#M1
VSS#AL20
VSS#AL23
VSS#AL24
AL23
AL24
AL27
L30
L29
L3
VSS#L3
VSS#L30
VSS#AL27
VSS#AL28
VSS#AL3
AL3
AL7
AL28
L28
L27
VSS#L29
VSS#L28
VSS#L27
VSS#AL7
VSS#AM1
VSS#AM10
AM1
AM10
L26
L25
L24
VSS#L26
VSS#L25
VSS#L24
VSS#AM13
VSS#AM16
VSS#AM17
AM13
AM16
AM17
K5
L23
VSS#K7K7VSS#K5
VSS#L23
VSS#AM20
VSS#AM23
VSS#AM24
AM20
AM23
AM24
K2
J7
VSS#J4J4VSS#J7
VSS#K2
VSS#AM27
VSS#AM28
VSS#AM4
AM4
AM27
AM28
H8
H9
VSS#H9
AN1
H6
H7
VSS#H6
VSS#H7
VSS#H8
VSS#AN1
VSS#AN10
VSS#AN13
AN10
AN13
H28
H3
VSS#H3
VSS#AN16
VSS#AN17
AN2
AN16
AN17
H26
H27
VSS#H26
VSS#H27
VSS#H28
VSS#AN2
VSS#AN20
VSS#AN23
AN20
AN23
H23
H24
H25
VSS#H24
VSS#H25
VSS#AN24
VSS#AN27
AN24
AN27
AN28
H20
H21
H22
VSS#H21
VSS#H22
VSS#H23
VSS#AN28
VSS#B1B1VSS#B11
B11
H17
H18
H19
VSS#H14
VSS#H13
VSS#H17
VSS#H18
VSS#H19
VSS#H20
VSS#H12
VSS#H11
VSS#H10
VSS#G1
VSS#F7
VSS#F4
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10
VSS#E8
VSS#E29
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20
VSS#E2
VSS#E17
VSS#E14
VSS#E11
VSS#D9
VSS#D6
VSS#D5
VSS#D3
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#C7
VSS#C4
VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10
VSS#B8
VSS#B5
VSS#B24
VSS#B20
VSS#B17
VSS#B14
ZIF-SOCK775-15u-in
B14
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R586 51R0402
TP17
BPM#0 3
VTT_OUT_LEFT 3,4
D D
R43 49.9R1%0402
R44 49.9R1%0402
H_COMP7
H_COMP6
AE3
D1
AE4
COMP6Y3COMP7
VSS#AE29
VSS#AE30
AE5
AE29
AE30
RSVD#D1
RSVD#AE4
VSS#AE5
VSS#AE7
VSS#AF10
AE7
AF10
D14
AF13
U19C
A12
VSS#A12
A15
VSS#A15
A18
VSS#A18
A2
VSS#A2
A21
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
A24
A6
A9
VSS#A21
VSS#A24
VSS#A6
VSS#A9
VSS#AA23
VSS#AA24
VSS#AA25
VSS#AA26
VSS#AA27
VSS#AA28
VSS#AA29
VSS#AA3
VSS#AA30
VSS#AA6
VSS#AA7
VSS#AB1
VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30
VSS#AB7
VSS#AC3
VSS#AC6
VSS#AC7
VSS#AD4
VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17
VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
R547 X_1KR1%0402
C C
B B
E23
RSVD#E23
RSVD#D14
VSS#AF13
VSS#AF16
VSS#AF17
AF16
AF17
AF20
R45 51R0402
F23
F6
E7
IMPSEL#
RSVD#E5E5RSVD#E6E6RSVD#E7
RSVD#F23
VSS#AF20
VSS#AF23
VSS#AF24
VSS#AF25
VSS#AF26
AF23
AF24
AF25
AF26
R46 24.9R1%0402
H_COMP8
B13
RSVD#B13
VSS#AF27
VSS#AF28
AF27
AF28
AF29
J3
N4
P5
RSVD#J3
RSVD#N4
VSS#AF29
VSS#AF3
VSS#AF30
AF3
AF6
AF30
R48 51R0402
R47 51R0402
MSID[1]V1MSID[0]
RSVD#P5
VSS#AF6
VSS#AF7
VSS#AG10
AF7
AG10
AC4
W1
RSVD#AC4
VSS#AG13
VSS#AG16
VSS#AG17
AG13
AG16
AG17
VSS#Y7Y7VSS#Y5Y5VSS#Y2
VSS#AG20
VSS#AG23
VSS#AG24
AG20
AG23
AG24
Y2
VSS#W7W7VSS#W4
VSS#AG7
VSS#AH1
AH1
AG7
V6
W4
VSS#V7V7VSS#V6
VSS#AH10
VSS#AH13
AH10
AH13
AH16
V3
V30
V29
VSS#V3
VSS#V30
VSS#AH16
VSS#AH17
VSS#AH20
AH17
AH20
AH23
V28
V27
VSS#V29
VSS#V28
VSS#V27
VSS#AH23
VSS#AH24
VSS#AH3
AH3
AH24
TP11
MSID1 MSID0
2005 Perf FMB 0 0
2005 Value FMB 0 NC
A A
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
2006 65W FMB 0 NC
MICRO-START INT'L CO.,LTD.
Intel LGA775 CPU - GND
MS-7278
1
537Wednesday, August 16, 2006
100
5
4
3
2
1
V_FSB_VTT
AG19
AG18
AG17
P29
P27
P26
P24
P23
N29
N26
N24
N23
M29
M24
M23
L24
L23
K24
K23
J24
J23
H24
H23
G26
G24
G23
F26
F24
F23
E29
E27
E26
E23
D29
D28
D27
C30
C29
C27
B30
B29
B28
B27
A30
A28
R27
VTT_38
VTT_39
VCC_37
VCC_38
AC6
AB24
AC13
HXSWING
VTT_40
VTT_41
VCC_39
VCC_40
AB22
AB20
R26
VTT_42
VTT_43
VCC_41
VCC_42
AA25
AA23
VTT_44
VCC_43
U20A
J42
HA3#
L39
HA4#
J40
L37
L36
K42
N32
N34
M38
N37
M36
R34
N35
N38
U37
N39
R37
P42
R39
V36
R38
U36
U33
R35
V33
V35
Y34
V42
V38
Y36
Y38
Y39
AA37
M34
U34
F40
L35
L38
G43
J37
W40
Y40
W41
T43
Y43
U42
V41
AA42
W42
G39
U40
U41
AA41
U39
R32
U32
AM17
C31
AM18
J13
D23
C25
D25
B25
D24
B24
V_1P25_CORE
R50 49.9R1%0402 C19
R51 49.9R1%0402
5
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HA32#
HA33#
HA34#
HA35#
HADSTB0#
HADSTB1#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HADS#
HTRDY#
HDRDY#
HDEFER#
HITM#
HHIT#
HLOCK#
HBREQ0#
HBNR#
HBPRI#
HDBSY#
HRS0#
HRS1#
HRS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSCOMP#
HSWING
HDVREF
HAVREF
VTT_1
VTT_2
VTT_3
VCC_1
VCC_2
AJ12
AJ11
AJ10
C20
X_C2.7P25N0402
C21
X_C2.7P25N0402
VTT_4
VTT_5
VTT_6
VCC_3
VCC_4
VCC_5
AJ9
AJ8
AJ7
HXSCOMP
HXSCOMPB
VTT_7
VTT_8
VCC_6
VCC_7
AJ6
VTT_9
VCC_8
AJ5
VTT_10
VCC_9
AJ4
AJ3
VTT_11
VTT_12
VCC_10
VCC_11
AJ2
AH4
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VTT_26
VTT_27
VTT_28
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VTT_34
VTT_35
VTT_36
VTT_37
VCC_12
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_80
VCC_34
VCC_35
VCC_36
AH2
AH1
AG9
AG8
AG7
AG6
AG5
AG4
AG3
AG2
AF13
AF12
AF11
AD24
AD22
AD20
AC25
AC23
AC21
AG13
AG12
AG11
AG10
V_FSB_VTT V_FSB_VTT
R52
300R1%0402
R294 49.9R1%0402
R55
100R1%0402
C22
C0.1U16Y0402
4
AC19
PWRGD11,24
PLTRST#10,24
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
HXRCOMP
HXSCOMP
HXSCOMPB
HXSWING
MCH_GTLREF
V_FSB_VTT
V_FSB_VTT
H_A#[3..35]3
D D
H_ADSTB#03
C C
B B
16.5R1%0402-RH
A A
H_ADSTB#13
H_REQ#[0..4]3
H_ADS#3
H_TRDY#3
H_DRDY#3
H_DEFER#3
H_HITM#3
H_HIT#3
H_LOCK#3
H_BR#03,4
H_BNR#3
H_BPRI#3
H_DBSY#3
H_RS#[0..2]3
CK_H_MCH13
CK_H_MCH#13
H_CPURST#3,4
ICH_SYNC#11
R49
R24
R23
VTT_45
VCC_44
AA21
AA19
VTT_46
VCC_45
VCC_46
AA3
AA13
VCC_84
VCC_85
VCC_47
VCC_48
Y24
Y22
AG15
VCC_86
VCC_87
VCC_49
VCC_50
Y20
V_1P25_CORE
AG14
AF26
AF25
AF24
AF22
AF20
AF18
AF17
AF15
AF14
AE27
AE26
AE25
AE23
AE21
AE19
VCC_88
VCC_89
VCC_90
VCC_91
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_100
VCC_101
VCC_102
VCC_103
VCC_51
VCC_52Y6VCC_53
VCC_54
VCC_55
VCC_56V9VCC_57
VCC_58
VCC_59U9VCC_60U6VCC_61U3VCC_62
VCC_63
VCC_64N9VCC_65N8VCC_66N6VCC_67N3VCC_68L6VCC_69J6VCC_70J3VCC_71J2VCC_72G2VCC_73
Y13
V13
V12
V10
U13
U10
N12
N11
GTLREF VOLTAGE SHOULD BE 0.67*VTT=0.8VHXSWING S/B 1/4*VTT +/- 2%
100 OHM OVER 210 RESISTORS
R53
124R1%0402
R56
210R1%0402
CPU_MCH_GTLREF
R54 51R0402
C23
C0.1U16Y0402
3
AE17
AD27
VCC_104
VCC_105
VCC_106
AD26
AD18
VCC_107
VCC_108
AD17
AD15
AD14
VCC_109
VCC_110
F11
C24
X_C2200P50X
AC27
AC26
AC17
VCC_111
VCC_112
VCC_113
VCC_114
VCC_74F9VCC_75D4VCC_76
C13
MCH_GTLREF
AC15
AC14
AB27
VCC_115
VCC_116
VCC_77C9VCC_78
P20
Y11
AB26
VCC_117
VCC_79
AG25
AB18
AB17
AA27
AA26
HD0
HD1
HD2
HD3
VCC_118
VCC_119
VCC_120
VCC_121
VCC_122
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDSTBP0#
HDSTBN0#
HDSTBP1#
HDSTBN1#
HDSTBP2#
HDSTBN2#
HDSTBP3#
HDSTBN3#
VCC_81
VCC_82
VCC_83
[INTEL-LE82G965-C2[QN08]-RH]
AG21
AG20
CPU_MCH_GTLREF 3
R40
P41
R41
N40
R42
M39
N41
N42
L41
J39
L42
J41
K41
G40
F41
F42
C42
D41
F38
G37
E42
E39
E37
C39
B39
G33
A37
F33
E35
K32
H32
B34
J31
F32
M31
E31
K31
G31
K29
F31
J29
F29
L27
K27
H26
L26
J26
M26
C33
C35
E41
B41
D42
C40
D35
B40
C38
D37
B33
D33
C34
B35
A32
D32
M40
J33
G29
E33
L40
M43
G35
H33
G27
H27
B38
D38
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 3
H_DSTBN#0 3
H_DSTBP#1 3
H_DSTBN#1 3
H_DSTBP#2 3
H_DSTBN#2 3
H_DSTBP#3 3
H_DSTBN#3 3
C17
C0.1U16Y0402
2
V_FSB_VTT
C18
C0.1U16Y0402
H_D#[0..63] 3
H_DBI#[0..3] 3
C0.1U16Y0402
Title
Size Document Number Rev
Date: Sheet
MICRO-START INT'L CO.,LTD.
Broadwater - CPU Signal
MS-7278
1
of
637Monday, August 21, 2006
100
5
4
3
2
1
DATA_B39
DATA_B40
AN35
AR37
SDQ_B38
SDQ_B39
SDQ_A38
SDQ_A39
AP41
AR42
DATA_B42
DATA_B41
AM35
AM38
SDQ_B40
SDQ_B41
SDQ_A40
SDQ_A41
AN41
AM39
DATA_B44
DATA_B43
AJ34
AL38
SDQ_B42
SDQ_B43
SDQ_A42
SDQ_A43
AK42
AK41
SCKE_B[0..3]18,19
DATA_B45
DATA_B46
AR39
AM34
SDQ_B44
SDQ_B45
SDQ_A44
SDQ_A45
AN40
AN42
DATA_B47
DATA_B48
AL37
AL32
SDQ_B46
SDQ_B47
SDQ_A46
SDQ_A47
AL42
AL39
DATA_B50
DATA_B49
AG38
AJ38
SDQ_B48
SDQ_B49
SDQ_A48
SDQ_A49
AJ40
AH43
DATA_B51
AF35
AF33
SDQ_B50
SDQ_B51
SDQ_A50
SDQ_A51
AF39
AE40
DATA_B[0..63]18
DATA_B0
DATA_B2
DATA_B3
DATA_B4
DATA_B1
DATA_B6
DATA_B9
DATA_B5
DATA_B7
DATA_B8
DATA_B13
DATA_B14
DATA_B11
DATA_B10
AN9
AU7
SDQ_B5
SDQ_B6
SDQ_A5
SDQ_A6
AV4
AU1
AT11
AU11
SDQ_B7
SDQ_B8
SDQ_A7
SDQ_A8
AY2
AY3
AP13
AR13
SDQ_B9
SDQ_B10
SDQ_A9
SDQ_A10
BB5
AY6
DATA_B12
AR11
AU9
SDQ_B11
SDQ_B12
SDQ_B13
SDQ_A11
SDQ_A12
SDQ_A13
AW2
AW3
AV12
BA5
D D
AN7
AN8
AW5
AW7
AN5
SDQ_B0
SDQ_A0
AR5
AR4
SDQ_B1
SDQ_B2
SDQ_A1
SDQ_A2
AV3
AV2
AN6
SDQ_B3
SDQ_B4
SDQ_A3
SDQ_A4
AP3
AP2
SCS_A#[0..3]17,19
RAS_A#17,19
CAS_A#17,19
WE_A#17,19
MAA_A[0..14]17,19
C C
B B
VCC_DDR
C0.1U16Y0402
ODT_A[0..3]17,19
SBS_A[0..2]17,19
DQS_A017
DQS_A#017
DQS_A117
DQS_A#117
DQS_A217
DQS_A#217
DQS_A317
DQS_A#317
DQS_A417
DQS_A#417
DQS_A517
DQS_A#517
DQS_A617
DQS_A#617
DQS_A717
DQS_A#717
P_DDR0_A17
N_DDR0_A17
P_DDR1_A17
N_DDR1_A17
P_DDR2_A17
N_DDR2_A17
P_DDR3_A17
N_DDR3_A17
P_DDR4_A17
N_DDR4_A17
P_DDR5_A17
N_DDR5_A17
R57 20R1%0402
R59 20R1%0402
R58 20R1%0402
C26
R60 20R1%0402
Place CAPs close to RCOMPXPU
and VOH/VOL resistors
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
AW35
BA35
BA34
BB38
BB33
AY35
BB34
BA31
BB25
BA26
BA25
AY25
BA23
AY24
AY23
BB23
BA22
AY33
BB22
AW21
AY38
BA21
AY37
BA38
BB35
BA39
BA33
AW32
BB21
AU4
AR3
AT20
AU18
AR41
AR40
AL41
AL40
AG42
AG41
AC42
AC41
AU31
AR31
AP27
AN27
AV33
AW33
AP29
AP31
AM26
AM27
AT33
AU33
AN2
AN3
BB40
BA40
BB3
BA4
BB9
BA9
U20B
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SRAS_A#
SCAS_A#
SWE_A#
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_A14
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SBS_A0
SBS_A1
SBS_A2
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
DATA_B16
DATA_B17
DATA_B15
AU12
AU15
SDQ_B14
SDQ_B15
SDQ_B16
SDQ_A14
SDQ_A15
SDQ_A16
BB4
AY7
DATA_B18
DATA_B19
AV13
AU17
SDQ_B17
SDQ_B18
SDQ_A17
SDQ_A18
BC7
AW11
DATA_B21
DATA_B20
AT17
AU13
SDQ_B19
SDQ_B20
SDQ_A19
SDQ_A20
BB6
AY11
DATA_B22
DATA_B23
AM13
AV15
SDQ_B21
SDQ_B22
SDQ_A21
SDQ_A22
BA6
BA10
DATA_B25
DATA_B24
AW17
AV24
SDQ_B23
SDQ_B24
SDQ_A23
SDQ_A24
AT18
BB10
DATA_B27
DATA_B26
AT23
AT26
SDQ_B25
SDQ_B26
SDQ_A25
SDQ_A26
AR18
AU21
DATA_B28
DATA_B29
AP26
AU23
SDQ_B27
SDQ_B28
SDQ_A27
SDQ_A28
AT21
AP17
DATA_B30
DATA_B31
AW23
AR24
SDQ_B29
SDQ_B30
SDQ_A29
SDQ_A30
AP20
AN17
DATA_B32
DATA_B33
AN26
AW37
SDQ_B31
SDQ_B32
SDQ_A31
SDQ_A32
AV20
AV42
DATA_B34
DATA_B35
AV38
AN36
SDQ_B33
SDQ_B34
SDQ_A33
SDQ_A34
AP42
AU40
DATA_B36
DATA_B37
AN37
AU35
SDQ_B35
SDQ_B36
SDQ_A35
SDQ_A36
AV40
AN39
DATA_B38
AR35
SDQ_B37
SDQ_A37
AV41
DATA_B52
DATA_B53
AJ37
AJ35
SDQ_B52
SDQ_B53
SDQ_A52
SDQ_A53
AJ42
AJ41
DATA_B54
DATA_B55
AG33
AF34
SDQ_B54
SDQ_B55
SDQ_A54
SDQ_A55
AF41
AF42
DATA_B56
DATA_B57
AD36
AC33
SDQ_B56
SDQ_A56
AD40
AD43
DQM_B[0..7]18
DATA_B58
DATA_B59
AA34
AA36
SDQ_B57
SDQ_B58
SDQ_B59
SDQ_A57
SDQ_A58
SDQ_A59
AB41
AA40
DATA_B61
DATA_B60
AD34
AF38
SDQ_B60
SDQ_B61
SDQ_A60
SDQ_A61
AE42
AE41
DATA_B63
DATA_B62
AC34
AA33
SDQ_B62
SDQ_B63
SDQ_A62
SDQ_A63
AB42
AC39
SCKE_B1
SCKE_B0
AY12
AW12
SCKE_B0
SCKE_B1
SCKE_A0
SCKE_A1
AY20
BC20
SCKE_B3
SCKE_B2
BB11
BA11
SCKE_B2
SCKE_B3
SCKE_A2
SCKE_A3
AY21
BA19
DQM_B0
DQM_B1
AR7
AW9
SDM_B0
SDM_A0
BA2
AR2
DQM_B3
DQM_B2
AW13
AP23
SDM_B1
SDM_B2
SDM_A1
SDM_A2
AY9
AN18
DQM_B4
DQM_B5
AU37
AM37
SDM_B3
SDM_B4
SDM_A3
SDM_A4
AU43
AM43
DQM_B6
DQM_B7
AG39
AD38
SCS_B0#
SCS_B1#
SCS_B2#
SDM_B5
SDM_B6
SDM_B7
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SMA_B14
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SBS_B0
SBS_B1
SBS_B2
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SVREF
SMRCOMPVOL
SMRCOMPVOH
SDM_A5
SDM_A6
SDM_A7
[INTEL-LE82G965-C2[QN08]-RH]
AC40
AG40
BB27
BB30
AY27
AY31
AW26
AW29
BA27
BB17
AY17
BA17
BC16
AW15
BA15
BB15
BA14
AY15
BB14
AW18
BB13
BA13
AY29
AY13
BA29
BA30
BB29
BB31
AY19
BA18
BC12
AV6
AU5
AR12
AP12
AP15
AR15
AT24
AU26
AW39
AU39
AL35
AL34
AG35
AG36
AC36
AC37
AV31
AW31
AU27
AT27
AV32
AT32
AU29
AR29
AV29
AW27
AN33
AP32
AM6
AM8
AM10
SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3
RAS_B#
CAS_B#
WE_B#
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
MAA_B14
ODT_B0
ODT_B1
ODT_B2
ODT_B3
SBS_B0
SBS_B1
SBS_B2
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
P_DDR3_B
N_DDR3_B
P_DDR4_B
N_DDR4_B
P_DDR5_B
N_DDR5_B
MCH_VREF_A
SCS_B#[0..3] 18,19
RAS_B# 18,19
CAS_B# 18,19
WE_B# 18,19
MAA_B[0..14] 18,19
ODT_B[0..3] 18,19
SBS_B[0..2] 18,19
DQS_B0 18
DQS_B#0 18
DQS_B1 18
DQS_B#1 18
DQS_B2 18
DQS_B#2 18
DQS_B3 18
DQS_B#3 18
DQS_B4 18
DQS_B#4 18
DQS_B5 18
DQS_B#5 18
DQS_B6 18
DQS_B#6 18
DQS_B7 18
DQS_B#7 18
P_DDR0_B 18
N_DDR0_B 18
P_DDR1_B 18
N_DDR1_B 18
P_DDR2_B 18
N_DDR2_B 18
P_DDR3_B 18
N_DDR3_B 18
P_DDR4_B 18
N_DDR4_B 18
P_DDR5_B 18
N_DDR5_B 18
DDR_RCOMPVOL
DDR_RCOMPVOH
C25 C0.1U16Y0402
R61 1KR1%0402
R62
3.01KR1%0402
R63 1KR1%0402
C27
C0.1U16Y0402
DDR_RCOMPVOL = 0.2 * VCC_DDR
DDR_RCOMPVOH = 0.8 * VCC_DDR
VCC_DDR
C28
C0.1U16Y0402
SCKE_A1
SCKE_A0
SCKE_A3
SCKE_A2
DQM_A1
DQM_A2
DQM_A0
DQM_A3
DQM_A4
DQM_A5
DQM_A6
DATA_A1
DATA_A3
DATA_A2
DATA_A[0..63]17
A A
DATA_A0
DATA_A9
DATA_A8
DATA_A7
DATA_A10
DATA_A6
DATA_A4
DATA_A5
DATA_A11
DATA_A14
DATA_A15
DATA_A13
DATA_A12
DATA_A16
DATA_A19
DATA_A17
DATA_A18
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A29
DATA_A27
DATA_A25
DATA_A24
DATA_A26
DATA_A28
DATA_A35
DATA_A34
DATA_A30
DATA_A32
DATA_A33
DATA_A31
DATA_A37
DATA_A38
DATA_A36
DATA_A45
DATA_A46
DATA_A40
DATA_A39
DATA_A47
DATA_A43
DATA_A44
DATA_A42
DATA_A41
DATA_A52
DATA_A55
DATA_A51
DATA_A49
DATA_A54
DATA_A50
DATA_A53
DATA_A48
DATA_A56
SCKE_A[0..3]17,19
DATA_A63
DATA_A62
DATA_A57
DATA_A60
DATA_A59
DATA_A58
DATA_A61
DQM_A[0..7]17
DQM_A7
VCC_DDR
R64 1KR1%0402
R65
1KR1%0402
MCH_VREF_A
C29
C0.1U16Y0402
PLACE 0.1UF CAP CLOSE TO MCH
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
Intel Broadwater - Memory
MS-7278
1
of
737Wednesday, August 16, 2006
100
5
V_1P25_CORE
U20C
F15
EXP_RXP0
G15
EXP_RXN0
K15
EXP_RXP1
J15
EXP_RXN1
F12
EXP_RXP2
E12
EXP_RXN2
J12
EXP_RXP3
H12
EXP_RXN3
J11
EXP_RXP4
H11
EXP_RXN4
F7
EXP_RXP5
E7
EXP_RXN5
E5
EXP_RXP6
F6
EXP_RXN6
C2
EXP_RXP7
D2
EXP_RXN7
G6
EXP_RXP8
G5
EXP_RXN8
L9
EXP_RXP9
L8
EXP_RXN9
M8
EXP_RXP10
M9
EXP_RXN10
M4
EXP_RXP11
L4
EXP_RXN11
M5
EXP_RXP12
M6
EXP_RXN12
R9
EXP_RXP13
R10
EXP_RXN13
T4
EXP_RXP14
R4
EXP_RXN14
R6
EXP_RXP15
R7
EXP_RXN15
W2
DMI_RXP0
V1
DMI_RXN0
Y8
DMI_RXP1
Y9
DMI_RXN1
AA7
DMI_RXP2
AA6
DMI_RXN2
AB3
DMI_RXP3
AA4
DMI_RXN3
B12
GCLKP
B13
GCLKN
G17
SDV0_CTRLDATA
E17
SDVO_CTRLCLK
G20
BSEL0
J20
BSEL1
J18
BSEL2
G18
MTYPE
E18
EXP_SLR
J17
EXP_EN
Y32
VCC_CL_PLL
C23
VCCA_HPLL
A24
VCCA_MPLL
A22
VCCA_DPLLA
C22
VCCA_DPLLB
B15
VCCA_EXPPLL
C17
VCCA_DAC_17
B16
VCCA_DAC_18
A16
VCCA_EXP_19
C21
VCCD_CRT_20
B21
VCCDQ_CRT_21
D16
VSS_1
B17
VCC33
[INTEL-LE82G965-C2[QN08]-RH]
V_1P25_CORE
C51
C52
C56
C66
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
H_BSL013
H_BSL113
H_BSL213
MTYPE
EXP_SLR
EXP_EN
VCC_CL_PLL
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
VCCD_CRT
VCCDQ_CRT
VCC3
C53
C1U16Y
VCCA_MPLL
C60
C0.1U16Y0402
VCCA_HPLL
C67
C0.1U16Y0402
EXP_A_RXP_020
EXP_A_RXN_020
EXP_A_RXP_120
D D
C C
Pull High for ATX Platform
Pull Low for BTX Platform
V_1P25_CORE
B B
V_1P5_ICH
V_1P25_CORE V_1P25_CORE
A A
V_1P25_CORE
R657 X_1KR1%0402
R648 1KR1%0402
EXP_PRSNT_N20
V_1P25_CORE
Power to this pin should be sourced
from VCC_CL if supporting iAMT,if not
power can be sourced from the 1.25V
Core rail.
C50
C0.1U16Y0402
L4 X_10U100m_0805
EXP_A_RXN_120
EXP_A_RXP_220
EXP_A_RXN_220
EXP_A_RXP_320
EXP_A_RXN_320
EXP_A_RXP_420
EXP_A_RXN_420
EXP_A_RXP_520
EXP_A_RXN_520
EXP_A_RXP_620
EXP_A_RXN_620
EXP_A_RXP_720
EXP_A_RXN_720
EXP_A_RXP_820
EXP_A_RXN_820
EXP_A_RXP_920
EXP_A_RXN_920
EXP_A_RXP_1020
EXP_A_RXN_1020
EXP_A_RXP_1120
EXP_A_RXN_1120
EXP_A_RXP_1220
EXP_A_RXN_1220
EXP_A_RXP_1320
EXP_A_RXN_1320
EXP_A_RXP_1420
EXP_A_RXN_1420
EXP_A_RXP_1520
EXP_A_RXN_1520
DMI_TXP010
DMI_TXN010
DMI_TXP110
DMI_TXN110
DMI_TXP210
DMI_TXN210
DMI_TXP310
DMI_TXN310
CK_PE_100M_MCH13
CK_PE_100M_MCH#13
SDVO_CTRL_DATA20
SDVO_CTRL_CLK20
R68 1KR1%0402
R67 0R
R69 0R
V_3P3_DAC_FILTERED
R72 0R
R71 0R
X_C0.022U25X0402
C0.1U16Y0402
CP8
X_COPPER
X_C0.22U16Y
CP11
X_COPPER
L7 X_10U100m_0805
X_C10U10Y0805
5
AL26
VCC_CL_1
VCC_EXP_1
VCC_EXP_2
AD11
AD10
4
AL24
AL23
AL21
AL20
AL18
AL17
AL15
VCC_CL_2
VCC_CL_3
VCC_CL_4
VCC_CL_5
VCC_CL_6
VCC_CL_7
VCC_CL_8
VCC_EXP_3
VCC_EXP_4
VCC_EXP_5
VCC_EXP_6
VCC_EXP_7
VCC_EXP_8
VCC_EXP_9
AD9
AD8
AD7
AD6
AD5
AD4
AD2
CP9
X_COPPER
L5 X_10U100m_0805
X_C10U10Y0805
CP10
X_COPPER
L6 X_10U100m_0805
X_C10U10Y0805
4
AK29
AK27
AJ31
AK30
VCC_CL_9
VCC_CL_10
VCC_CL_11
VCC_CL_12
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
VCC_EXP_13
AD1
AC4
AC3
AC2
VCC_DDR
C61
C64
AG31
AF31
AD32
AC32
VCC_CL_13
VCC_CL_14
VCC_CL_15
VCC_CL_16
VCC_EXP_14
VCC_EXP_15
VCC_EXP_16
AE4
AE3
AE2
AA32
AJ30
AJ29
AJ27
VCC_CL_17
VCC_CL_18
VCC_CL_19
VCC_CL_20
VCCSM_1
VCCSM_2
VCCSM_3
VCCSM_4
BC39
BC34
BC30
BC26
VCCA_DPLLA
VCCA_DPLLA
C62
C0.1U16Y0402
VCCA_DPLLB
C65
C0.1U16Y0402
AG30
AG29
AG27
VCC_CL_21
VCC_CL_22
VCC_CL_23
VCCSM_5
VCCSM_6
VCCSM_7
BC22
BC18
BC14
AG26
AF30
AF29
VCC_CL_24
VCC_CL_25
VCC_CL_26
VCCSM_8
VCCSM_9
VCCSM_10
BB39
BB37
BB32
AF27
AD30
AD29
VCC_CL_27
VCC_CL_28
VCC_CL_29
VCCSM_11
VCCSM_12
VCCSM_13
BB28
BB26
BB24
V_1P25_CORE
AC30
AC29
AL12
VCC_CL_30
VCC_CL_31
VCC_CL_32
VCCSM_14
VCCSM_15
VCCSM_16
BB20
BB18
BB16
AL11
AL10
AL9
VCC_CL_33
VCC_CL_34
VCC_CL_35
VCCSM_17
VCCSM_18
VCCSM_19
BB12
AY32
AW24
AL8
AL7
AL6
AL5
AL4
AL3
VCC_CL_36
VCC_CL_37
VCC_CL_38
VCC_CL_39
VCC_CL_40
VCC_CL_41
VCCSM_20
VCCSM_21
VCCSM_22
VCC_SMCLK_1
AV26
AV18
BB41
AW20
C54
C1U16Y
L8 10U100m_0805
3
AL2
AK26
AK24
AK23
AK21
VCC_CL_42
VCC_CL_43
VCC_CL_44
VCC_CL_45
VCC_SMCLK_5
VCC_SMCLK_4
VCC_SMCLK_3
VCC_SMCLK_2
BA43
BB42
AY42
BA42
V_CKDDR
R73 1R1%
R75 1R1%
CP12
X_COPPER
X_C10U10Y0805
3
VCC_CL_46
AK20
AK18
AK17
AK15
AK3
AK2
AK1
AJ13
AD31
AC31
VCC_CL_47
VCC_CL_48
VCC_CL_49
VCC_CL_50
VCC_CL_51
VCC_CL_52
VCC_CL_53
VCC_CL_54
VCC_CL_55
VCC_CL_56
RESERVED_2
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
RESERVED_8
RESERVED_9
RESERVED_3
RESERVED_1
H18
BB2
AF32
BB19
AN21
AN32
AG32
AM31
AW42
L3 600L350m_450
C55 C10U10Y0805
VCCA_GPLL
C68
C69
C0.1U16Y0402
AA31
Y31
AJ26
AJ24
AJ23
VCC_CL_57
VCC_CL_58
VCC_CL_59
VCC_CL_60
RESERVED_10
RESERVED_11
RESERVED_12
RESERVED_13
AA9
AJ32
AL31
AA10
AM21
VCC_DDR
AJ21
AJ20
AJ18
AJ17
AJ15
VCC_CL_61
VCC_CL_62
VCC_CL_63
VCC_CL_64
VCC_CL_65
RESERVED_14
RESERVED_15
RESERVED_16
RESERVED_17
RESERVED_18
Y12
U30
U31
R29
AA11
V_1P25_CORE
CP13 X_COPPER
VCC3V_1P25_CORE
AJ14
AA30
AA29
Y30
Y29
V30
V29
VCC_CL_66
VCC_CL_67
VCC_CL_68
VCC_CL_69
VCC_CL_70
VCC_CL_71
VCC_CL_72
RESERVED_25
RESERVED_19
RESERVED_20
RESERVED_21
RESERVED_22
RESERVED_23
RESERVED_24
F13
R30
U12
U11
R12
R13
AP21
L9 0.1U400m
C10U10Y0805
2
U29
U27
AL13
AK14
AL29
AL27
VCC_CL_73
VCC_CL_74
VCC_CL_75
VCC_CL_76
VCC_CL_77
VCC_CL_78
VCC_CL_79
EXP_COMPO
TEST2
TEST1
RESERVED_28
RESERVED_27
RESERVED_26
V31
BC1
AA39
BC43
C58 C10U6.3X50603
C63 X_C10U6.3X50603
C70
2
D11
EXP_TXP0
D12
EXP_TXN0
B11
EXP_TXP1
A10
EXP_TXN1
C10
EXP_TXP2
D9
EXP_TXN2
B9
EXP_TXP3
B7
EXP_TXN3
D7
EXP_TXP4
D6
EXP_TXN4
B5
EXP_TXP5
B6
EXP_TXN5
B3
EXP_TXP6
B4
EXP_TXN6
F2
EXP_TXP7
E2
EXP_TXN7
F4
EXP_TXP8
G4
EXP_TXN8
J4
EXP_TXP9
K3
EXP_TXN9
L2
EXP_TXP10
K1
EXP_TXN10
N2
EXP_TXP11
M2
EXP_TXN11
P3
EXP_TXP12
N4
EXP_TXN12
R2
EXP_TXP13
P1
EXP_TXN13
U2
EXP_TXP14
T2
EXP_TXN14
V3
EXP_TXP15
U4
EXP_TXN15
V7
DMI_TXP0
V6
DMI_TXN0
W4
DMI_TXP1
Y4
DMI_TXN1
AC8
DMI_TXP2
AC9
DMI_TXN2
Y2
DMI_TXP3
AA2
DMI_TXN3
AC11
AC12
EXP_COMPI
C15
HSYNC
D15
VSYNC
B18
RED
C19
GREEN
B20
BLUE
C18
RED#
D19
GREEN#
D20
BLUE#
L13
DDC_DATA
M13
DDC_CLK
C14
DREFCLKP
D13
DREFCLKN
A20
REFSET
AM15
CL_PWROK
AA12
CL_RST#
AM5
CL_VERF
AD13
CL_CLK
AD12
CL_DATA
K20
ALLZTEST
F20
XORTEST
A14
TESTIN#
TEST0
A43
V_3P3_DAC_FILTERED
C71
X_C10U10Y0805
EXP_A_TXP_0
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_RXP0
DMI_RXN0
DMI_RXP1
DMI_RXN1
DMI_RXP2
DMI_RXN2
DMI_RXP3
DMI_RXN3
GRCOMP
HSYNC
VSYNC
VGA_RED
VGA_GREEN
VGA_BLUE
MCH_DDC_DATA
MCH_DDC_CLK
CK_96M_DREF
CK_96M_DREF#
DACREFSET
CL_VREF_MCH
C72
C0.01U25X0402
1
Place close to GMCH
EXP_A_TXP_0 20
EXP_A_TXN_0 20
EXP_A_TXP_1 20
EXP_A_TXN_1 20
EXP_A_TXP_2 20
EXP_A_TXN_2 20
EXP_A_TXP_3 20
EXP_A_TXN_3 20
EXP_A_TXP_4 20
EXP_A_TXN_4 20
EXP_A_TXP_5 20
EXP_A_TXN_5 20
EXP_A_TXP_6 20
EXP_A_TXN_6 20
EXP_A_TXP_7 20
EXP_A_TXN_7 20
EXP_A_TXP_8 20
EXP_A_TXN_8 20
EXP_A_TXP_9 20
EXP_A_TXN_9 20
EXP_A_TXP_10 20
EXP_A_TXN_10 20
EXP_A_TXP_11 20
EXP_A_TXN_11 20
EXP_A_TXP_12 20
EXP_A_TXN_12 20
EXP_A_TXP_13 20
EXP_A_TXN_13 20
EXP_A_TXP_14 20
EXP_A_TXN_14 20
EXP_A_TXP_15 20
EXP_A_TXN_15 20
DMI_RXP0 10
DMI_RXN0 10
DMI_RXP1 10
DMI_RXN1 10
DMI_RXP2 10
DMI_RXN2 10
DMI_RXP3 10
DMI_RXN3 10
R66
24.9R1%0402
R70 1.3KR1%0402
Title
Size Document Number Rev
Date: Sheet
V_1P25_CORE
HSYNC 28
VSYNC 28
VGA_RED 28
VGA_GREEN 28
VGA_BLUE 28
MCH_DDC_DATA 28
MCH_DDC_CLK 28
CK_96M_DREF 13
CK_96M_DREF# 13
CL_PWROK 11
CL_RST 11
CL_N_CLK 11
CL_N_DATA 11
V_1P25_CORE
R74
1KR1%0402
R76
392R1%0402
MICRO-START INT'L CO.,LTD.
Broadwater - PCI Express
MS-7278
VCC_DDR
C30
C2.2U6.3Y
C31
C2.2U6.3Y
C32
C2.2U6.3Y
C33
C2.2U6.3Y
C34
C2.2U6.3Y
C35
C2.2U6.3Y
MCH MEMORY DECOUPLING
V_1P25_CORE
C36
X_C10U6.3X50603
C37
X_C10U6.3X50603
C38
X_C10U6.3X50603
C39
C10U10Y0805
C40
X_C10U10Y0805
C41
X_C10U10Y0805
C42
X_C10U10Y0805
C43
X_C10U6.3X50603
C44
X_C10U6.3X50603
C45
X_C10U6.3X50603
C46
C0.1U16Y0402
C47
C0.1U16Y0402
C48
C0.1U16Y0402
C49
C0.1U16Y0402
MCH CORE DECOUPLING
CL_VREF_MCH = 0.349V
CL_VREF_MCH
C59
C0.1U16Y0402
of
1
837Monday, August 21, 2006
100
5
4
3
2
1
V_1P25_CORE
N20
BC42
BC2
BB43
BB1
B43
B42
NC_3
NC_4
NC_5
NC_6
NC_7
A42
NC_8B2NC_9
AA17
AA15
AA14
Y27
Y26
Y18
Y17
Y15
Y14
W27
W26
W25
W23
W21
W19
W18
W17
V27
V26
V25
V24
V23
V22
V21
V20
V19
V18
V17
V15
V14
U26
U25
U24
U23
U22
U21
U20
U19
U18
U17
U15
U14
R20
R18
R17
R15
R14
P15
P14
AG24
AG23
VCC_168
VCC_169
VCC_170
VCC_171
VCC_172
VCC_173
AG22
VCC_174
U20D
BC37
VSS_1
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
VCC_138
VCC_139
VCC_140
VCC_141
VCC_142
VCC_143
VCC_144
VCC_145
VCC_146
VCC_147
VCC_148
VCC_149
VCC_150
VCC_151
VCC_152
VCC_153
VCC_154
VCC_155
VCC_156
VCC_157
VCC_158
VCC_159
VCC_160
VCC_161
VCC_162
VCC_163
VCC_164
VCC_165
VCC_166
D D
C C
B B
BC32
BC28
BC24
BC10
AY41
AW43
AW41
AW1
AV37
AV35
AV27
AV23
AV21
AV17
AV11
AU42
AU38
AU32
AU24
AU20
AT31
AT29
AT15
AT13
AT12
AR38
AR33
AR32
AR27
AR26
AR23
AR21
AR20
AR17
AP43
AP24
AP18
AN38
AN31
AN29
AN24
AN23
AN20
AN15
AN13
AN12
AN11
AM42
AM40
AM36
AM33
AM29
AM24
AM23
AM20
AM11
AM9
AM7
AM4
AM2
AM1
AL36
AL33
AK43
BC5
BB7
AY4
AV9
AV7
AU6
AU2
AR9
AR6
AP1
AN4
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VCC_167
M20
L17
N17
N18
N15
RESERVED_29
RESERVED_30
RESERVED_31
RESERVED_32
L15
L18
M18
F17
K17
RESERVED_33
RESERVED_34
RESERVED_35
RESERVED_36
RESERVED_37
NC_1
NC_2
RESERVED_38
A41
C43
R21
W20
W22
W24
AA18
AC18
AE18
AE20
AE22
AE24
AF19
AF21
AF23
VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
AY40
VSS_274
M11
L12
VSS
VCC
VSS_293A3VSS_292A5VSS_291
VSS_290C1VSS_289
VSS_288E1VSS_287
VSS_286
VSS_285
VSS_284
VSS_283
VSS_282
VSS_281
BA1
BC3
VSS_273
VSS_272
BC41
M33
VSS_271
VSS_270
M35
M37
VSS_269
VSS_268
M42
VSS_267
VSS_266N5VSS_265N7VSS_264
N10
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_195
VSS_194
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_188
N13
N21
N27
N31
N33
N36
P2
P17
P18
P21
P30
P43
R3
R5
R8
R11
R31
R33
R36
T1
T42
U5
U7
U8
U35
U38
V2
V5
V8
V11
V32
V34
V37
V39
V43
W3
Y1
Y5
Y7
Y10
Y19
Y21
Y23
Y25
Y33
Y35
Y37
Y42
AA5
AA8
AA20
AA22
AA24
AA35
AA38
AB1
AB2
AB19
AB21
AB23
AB25
AB43
AC5
AC7
AC10
AC20
AC22
AC24
AC35
AC38
AD19
AD21
AD23
AD25
AD33
AD35
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96M7VSS_97M1VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105L7VSS_106L5VSS_107L3VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114K2VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120J9VSS_121J7VSS_122J5VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137G9VSS_138G7VSS_139G1VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145F3VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154E9VSS_155E3VSS_156
VSS_157
VSS_158
VSS_159
VSS_160D3VSS_161
VSS_162
VSS_163C6VSS_164C5VSS_165C4VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180A7VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
J38
J35
J32
J27
L33
L32
L31
L29
L21
L20
L11
K43
K26
K21
K18
AF9
AF8
AF7
AF6
M27
M21
M17
M15
AJ39
AJ36
AJ33
AF43
AF37
AF36
AF10
AH42
AG37
AG34
A A
5
M10
K13
4
J21
K12
H31
H29
H21
H20
H17
H15
H13
G42
G38
G32
G21
F37
F35
F27
F21
F18
E43
E32
E24
E21
E20
E15
E13
E11
D40
D31
D21
G13
G12
G11
3
D17
B37
B32
B31
B26
B23
B22
B19
B14
B10
A39
A34
A26
A18
C26
C11
A12
AF5
AF3
AF2
AF1
AD42
AD39
AD37
2
[INTEL-LE82G965-C2[QN08]-RH]
Title
Size Document Number Rev
Date: Sheet
MICRO-START INT'L CO.,LTD.
Broadwater - GND
MS-7278
1
of
937Wednesday, August 16, 2006
100
5
AD0
AD[31..0]29
D D
C_BE#[3..0]29
C C
PCIRST_ICH8#24
B B
SPI_MOSI_F
SPI_CS0_F# SPI_CS0#
SPI_CLK_F
VCC3_SB
Reserve
A A
DEVSEL#29
FRAME#29
IRDY#29
TRDY#29
STOP#29
PAR29
LOCK#29
SERR#29
PERR#29
PME#29
ICH_PCLK13
R85 10R1%0402
PREQ#029
PREQ#129
PREQ#229
PREQ#329
PGNT#129
PGNT#329
PIRQ#A29
PIRQ#B29
PIRQ#C29
PIRQ#D29
PIRQ#E29
PIRQ#F29
PIRQ#G29
PIRQ#H29
SERIRQ14
R87 15R0402
R88 15R0402
R89 15R0402
RN46
1
2
3
4
5
6
7
8
X_8P4R-10KR0402
SPI_CS0#
SPI_MISO
SPI_CS1#
SPI_MOSI
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C_BE#0
C_BE#1
C_BE#2
C_BE#3
PGNT#0
PGNT#1
PGNT#2
PGNT#3
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS1#
E18
A16
A14
A17
B13
E17
C17
A13
C14
E14
C13
E15
A11
D10
C11
E13
E12
D13
E11
G16
A10
C12
A12
B12
E16
D15
D11
B10
C16
B16
C15
D17
G11
AG9
D21
B19
C21
A19
A18
F18
F16
F14
D8
D7
C7
F13
B7
C6
B5
F12
F8
E7
B6
A7
D9
E6
C9
D3
E3
E8
A9
A4
B9
C4
C5
A3
A8
D5
F10
F9
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C/BE0#
C/BE1#
C/BE2#
C/BE3#
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PLOCK#
SERR#
PERR#
PME#
PCICLK
PCIRST#
REQ0#
REQ1#/GPIO50
REQ2#/GPIO52
REQ3#/GPIO54
GNT0#
GNT1#/GPIO51
GNT2#/GPIO53
GNT3#/GPIO55
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
SERIRQ
SPI_MOSI
SPI_MISO
SPI_CS0#
SPI_CLK
SPI_CS1#
VSS_001
A5
A24
VSS_004
VSS_003
VSS_002
B2
A28
PCI INTERFACE INTERRUPT
PART 1/3
SPI
VSS_012
VSS_011
VSS_010
VSS_009
VSS_008
VSS_007
VSS_006
VSS_005
B8
B24
B20
B17
B14
B11
C27
C22
VSS_013
C28
4
ICH 8
VSS_021
VSS_020
VSS_019
VSS_018
VSS_017
VSS_016
VSS_015
VSS_014
D6
D4
D2
D25
D22
D19
D16
D12
VSS_023
VSS_022
E9
D26
PCI EXPRESS
VSS_029
VSS_028
VSS_027
VSS_026
VSS_025
VSS_024
F7
F2
F15
E28
E27
E24
E21
A20M#
CPUSLP#
FERR#
IGNNE#
INIT#
INIT3_3V#
INTR
NMI
SMI#
STPCLK#
RCIN#
A20GATE
CPU
THRMTRIP#
PECI
PLTRST#
PERN_1
PERP_1
PETN_1
PETP_1
PERN_2
PERP_2
PETN_2
PETP_2
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
PERN_6/GLAN_RXN
PERP_6/GLAN_RXP
PETN_6/GLAN_TXN
PETP_6/GLAN_TXP
DMI_0RXN
DMI_0RXP
DMI_0TXN
DMI_0TXP
DMI_1RXN
DMI_1RXP
DMI_1TXN
DMI_1TXP
DMI_2RXN
DMI_2RXP
DMI_2TXN
DMI_2TXP
DMI_3RXN
DMI_3RXP
DMI_3TXN
DMI_3TXP
DMI_CLKN
VSS_032
VSS_033
VSS_034
F25
F26
DMI_IRCOMP
LAN_RSTSYNC
VSS_037
VSS_036
VSS_035
G6
G4
G1
G10
DMI_CLKP
DMICOMPI
GLAN_CLK
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
VSS_040
VSS_039
VSS_038
G18
G13
DIRECT MEDIA
LAN
VSS_031
VSS_030
F24
F22
U17A
AD23
AC24
AB22
AC22
AB19
AC12
AH28
AC23
AB20
AB23
AF10
AG10
AG28
R621 X_0R0402
R622 0R0402
AF26
PLTRST_L
AF23
N25
N26
M28
M27
L25
L26
K28
K27
J26
J25
H28
H27
G26
G25
F28
F27
E26
E25
D28
D27
GLAN_RXN
C26
GLAN_RXP
C25
GLAN_TXN_C
B28
GLAN_TXP_C
B27
U26
U25
T28
T27
W26
W25
V28
V27
AA25
AA24
Y28
Y27
AC26
AC25
AB28
AB27
R25
R24
DMI_BIAS
AD27
AD28
E22
E20
LAN_PWROK
AF17
ELAN_RXD0
E19
ELAN_RXD1
C19
ELAN_RXD2
D20
ELAN_TXD0
C20
ELAN_TXD1
C18
ELAN_TXD2
D18
[INTEL-NH82801HH-B1[QM36]-RH]
LAN_PWROK
3
R77 10R1%0402
For low speed device reset
C73 C0.1U16Y0402
C74 C0.1U16Y0402
R86 24.9R1%0402
<200mils
C618
X_C0.1U16Y0402
H_A20M# 3
H_SLP# 3
H_FERR# 3,4
H_IGNNE# 3
H_INIT# 3
TP16
H_INTR 3
H_NMI 3
ICH_H_SMI# 3
H_STPCLK# 3
KBRST# 14
A20GATE 14
TRMTRIP# 3,4
PECI_SIO 14
PECI 3,14
For intel phy lan
Stuff for NINEVEH
Empty for EKRON
DMI_RXN0 8
DMI_RXP0 8
DMI_TXN0 8
DMI_TXP0 8
DMI_RXN1 8
DMI_RXP1 8
DMI_TXN1 8
DMI_TXP1 8
DMI_RXN2 8
DMI_RXP2 8
DMI_TXN2 8
DMI_TXP2 8
DMI_RXN3 8
DMI_RXP3 8
DMI_TXN3 8
DMI_TXP3 8
CK_PE_100M_ICH# 13
CK_PE_100M_ICH 13
ELAN_CLK 16
ELAN_SYNC 16
ELAN_TXD[0..2] 16
ELAN_RXD[0..2] 16
R57310KR0402
R595X_0R0402
PLTRST# 6,24
GLAN_RXN 16
GLAN_RXP 16
GLAN_TXN 16
GLAN_TXP 16
V_1P5_ICH
VCC3_SB
RSMRST# 11,24
For SIO 83627EHG Ver:H
Add R622 ; Del R621
For SIO 83627DHG
Add R621 ; Del R622
SPI FLASH
SPI_CS0_F#
SPI_MISO
SPI_WP#11
From SB GPIO32
2
From SB GPIO33
R94 15R0402
SIGNAL
SPKR
GNT3
INTVRMEN/LAN100_SLP
SATALED
HDA_SDOUT
GNT2
ACSDOUT11
ACSYNC11
SPKR11,23
JBAT2
1
2
N31-1030151+N33-1020271-RH
SPI_HOLD#11
VCC3_SB
3
Reserved for BIOS control used
R594 X_0R0402
R91
1KR1%0402
U4
1
CE#
2
SO
HOLD#
3
WP#
4
VSS
SST25VF016B-50-4C-S2AF-RH
ICH8 H/W STRAPS
PGNT#2
PGNT#3
VCC3_SB
PGNT#0
VCC3
VDD
SCK
SI
L DES.
H
DIS REBOOT
EN
EN
EN
DIS
NORM
REVERSE
N/A
DFX/PCIE
N/AHDA_SYNC
SET
BIT
SET
N/A
BIT
R78 X_1KR1%0402
R79 X_1KR1%0402
R81 X_1KR1%0402
R80 X_1KR1%0402
R82 X_1KR1%0402
R96
1KR1%0402
R84 X_1KR1%0402
R83
1KR1%0402
RN7
2
4
6
8
8P4R-10KR0402
SPI_MISO
SPI_CS0_F#
HOLD#
HOLD#
8
R95 1KR1%0402
7
SPI_CLK_F
6
SPI_MOSI_F
5
Please Close to SB
1
A16 OVERIDEDIS
INTERNAL VRM
VCCSUS1_05,1_5, VCCCL1_5
VCCLAN1_05,VCC, VCCCL1_05)
PCIE 0-3 ORDER
XOR MODE/PCIE
PORT CONFIG BIT 1
PCIE PORT CONFIG
BIT 0 (1-4)
PCIE PORT CONFIG 2
BIT 0 (5-6)
VCC3_SB
VCC3
BOOT SELECT STRAPS
BOOT DEVICE GNT0 SPI_CS1#
FWH 1 1
SPI 0 X
PCI 1 0
SPI_CS1#
SERIRQ
1
A20GATE
3
KBRST#
5
THERM#
7
THERM# 4,11,14
SPI Debug Port
VCC3_SBVCC3_SB
JSPI1
1 2
3 4
6
5
7 8
9
_H2X5(10)_black-1
VCC3_SB
C76
C0.1U16Y0402
SPI_MOSI_F
SPI_CLK_F
C75
C0.1U16Y0402
For non-AMT function with Intel Lan (82566/82562)
Stuff R573
Empty R595 , C618
5
4
3
2
Title
Size Document Number Rev
Date: Sheet
MICRO-START INT'L CO.,LTD.
Intel ICH8 DH - 1
MS-7278
1
of
10 37Wednesday, August 16, 2006
100
5
4
3
2
1
BATTERY
U17B
USB0-22
USB0+22
USB1-22
USB1+22
USB2-22
USB2+22
USB3-22
USB3+22
USB4-22
USB4+22
USB5-22
USB5+22
USB6-22
USB6+22
USB7-22
USB7+22
USB8-22
USB8+22
USB9-22
USB9+22
PWRGD6,24
FP_RST#3,13,23
SLP_S3#14,24,25
SLP_S4#13,24
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ#0
LDRQ_1#
LPC_FRAME#
AC_BITCLK_ICH
ACRST#
ACSDIN0
ACSDOUT
ACSYNC
C612C0.1U16Y0402
C613C0.1U16Y0402
C614C0.1U16Y0402
USB_BIAS
SMB_ALERT#
SM_LINK0
SM_LINK1
LINK_ALERT#
VRM_PWRGD
LAN100_SLP
INTRUDER#
BATLOW#
R124 0R
ICH_14M13
USB_4813
5
LPC_AD014
LPC_AD114
LPC_AD214
LPC_AD314
D D
C C
B B
VCC5_SB
A A
LPC_DRQ#014
LPC_FRAME#14
OC#022
OC#222
OC#122
Please close to ICH8 DH
ICH_SYNC#6
VCC3
R277
4.7KR0402
R628
10KR0402
ACSDOUT10
ACSYNC10
R102 22.6R1%
SMBCLK_MAIN13,14,17,18,20,24,26
SMBDATA_MAIN13,14,17,18,20,24,26
RSMRST#10,24
PWRBTN#14
H_PWRGD3,4
CK_PWRGD13
LPC_PD#
WAKE#20
RI#21
THERM#4,10,14
SPKR10,23
R126 X_10KR0402
RSMRST#
C639
X_C1U16Y
F6
LAD0
F5
LAD1
G9
LAD2
E5
LAD3
G8
LDRQ_0#
C3
LDRQ_1#/GPIO23
B3
LFRAME#
AF12
ACZ_BCLK
AF13
ACZ_RST#
AE13
ACZ_SDIN_0
AC14
ACZ_SDIN_1
AH12
ACZ_SDIN_2
AD13
ACZ_SDIN_3
AH11
ACZ_SDOUT
AH10
ACZ_SYNC
G2
USBP_0N
G3
USBP_0P
H5
USBP_1N
H4
USBP_1P
H1
USBP_2N
H2
USBP_2P
J3
USBP_3N
J2
USBP_3P
K5
USBP_4N
K4
USBP_4P
K1
USBP_5N
K2
USBP_5P
L3
USBP_6N
L2
USBP_6P
M5
USBP_7N
M4
USBP_7P
M2
USBP_8N
M1
USBP_8P
N2
USBP_9N
N3
USBP_9P
AF15
OC0#
AH14
OC1#/GPIO40
AG14
OC2#/GPIO41
AG15
OC3#/GPIO42
AH15
OC4#/GPIO43
AE15
OC5#/GPIO29
AG13
OC6#/GPIO30
AF14
OC7#/GPIO31
AD14
OC8#
AG16
OC9#
E1
USBRBIASN
E2
USBRBIASP
AD19
SMBCLK
AB18
SMBDATA
AF21
SMBALERT#/GPIO11
AE19
SMLINK0
AG21
SMLINK1
AH21
SMLALERT#
AD22
RSMRST#
A1
PWRBTN#
AE24
PWROK
AC16
VRMPWRGD_VGATE
AF25
CPUPWRGD/GPIO49
F1
CK_PWRGD
AF16
SYS_RESET#
AF22
SLP_S3#
AH23
SLP_S4#
AC17
SLP_S5#
AG22
SLP_M#
AG24
LAN100_SLP
G7
SUS_STAT#/LPCPD#
E4
SUSCLK
AF24
INTRUDER#
AH18
WAKE#
AG17
RI#
AH9
THRM#
AE22
BATLOW#
AE10
MCH_SYNC#
AF6
SPKR
AE25
DPRSTP#
AD24
DPSLP#
AD16
DFXTESTB
AG6
CLK14
B1
CLK48
VSS_042
VSS_041
G27
G24
VSS_044
VSS_043
H3
G28
VSS_046
VSS_045
H7
H6
VSS_048
VSS_047
H24
H23
VSS_050
VSS_049
H26
H25
AC-LINKLPC
ICH 8
PART 2/3
MISCPOWER MGNTSM BUSUSB
VSS_059
VSS_058
VSS_057
VSS_056
VSS_055
VSS_054
VSS_053
VSS_052
VSS_051
J5
J4
J1
K7
K6
K3
J28
J27
K25
VSS_061
VSS_060
L1
K26
4
VSS_063
VSS_062
L5
L4
VSS_065
VSS_064
L15
L13
VSS_067
VSS_066
L28
L27
VSS_069
VSS_068
M3
M12
VSS_071
VSS_070
M14
M13
GPIO
VSS_074
VSS_073
VSS_072
M22
M17
M16
M15
VSS_075
M25
SATA_0RXN
SATA_0RXP
SATA_0TXN
SATA_0TXP
SATA_1RXN
SATA_1RXP
SATA_1TXN
SATA_1TXP
SATA_2RXN
SATA_2RXP
SATA_2TXN
SATA_2TXP
SATA_3RXN
SATA_3RXP
SATA_3TXN
SATA_3TXP
SATA_4RXN
SATA_4RXP
SATA_4TXN
SATA_4TXP
SATA_5RXN
S-ATA
BMBUSY#/PMSYNC#/GPIO0
SATA_5RXP
SATA_5TXN
SATA_5TXP
SATA_CLKN
SATA_CLKP
SATARBIASN
SATABIASP
SATALED#
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA2GP/GPIO36
SATA3GP/GPIO37
SATA4GP
SATA5GP
GLGP1O3/GPIO9
GLGPIO1/GPIO10
CLGPIO2/GPIO14
CLGPIO0/GPIO24
S4_STATE#/GPIO26
QRT_STATE0/GPIO27
QRT_STATE1/GPIO28
SATACLKREQ#/GPIO35
SCLOCK/GPIO22
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
INTVRMEN
RTCRST#
RTC
GLAN_COMPO
GLAN_COMPI
CL_CLK0
CL_CLK1
CL_DATA0
CL_DATA1
VSS_080
VSS_079
VSS_078
N5
N4
TACH0/GPIO17
TACH1/GPIO1
TACH2/GPIO6
TACH3/GPIO7
VSS_083
VSS_082
VSS_081
N13
N12
N11
CL_VREF0
CL_VREF1
CL_PWROK
CL_RST#
FAN_PWM0
FAN_PWM1
FAN_PWM2
VSS_085
VSS_084
N15
N14
AMT
AFSC
VSS_077
VSS_076
N1
M26
AC5
AC4
AE4
AE3
AF1
AF2
AH2
AH1
W5
W4
AA3
AA4
AB1
AB2
AD2
AD1
Y1
Y2
U3
U4
T1
T2
V2
V1
AG3
AG4
SATA_BIAS
SATA_BIAS
R2
R1
AB10
AB11
AD8
AF8
AD9
R111 10KR0402
AD10
R112 10KR0402
AE9
GPIO_0
AF9
AE16
GPIO8
GP12
GPIO13
GPIO15
GPIO16
GPIO18
GPIO20
GPIO25
GPIO32
GPIO33
GPIO34
VCCRTC
RTCX1
RTCX2
SSTCTL
[INTEL-NH82801HH-B1[QM36]-RH]
AG18
AF20
AC19
AF18
AH24
AE21
AE11
AC11
AG8
AG23
AH17
AH25
AD20
AD15
AH7
AG7
AG12
AD12
AE7
AH6
AC10
AF7
AG26
AA22
AD21
AH26
AH27
C24
D24
F21
AH20
G21
AE18
B21
AG20
C2
AG19
AB6
AD6
AB8
AC7
AF5
AE6
AC8
AD17
WOL
GPIO_10
GPIO_12
GPIO_13
GPIO_14
CLEAR_PASSWORD
GPIO22
GPIO38
GPIO39
GPIO48
INTVRMEN
RTC_RST#
RTCX1
RTCX2
< 200mils
R122 24.9R1%0402
CL_VREF_ICH
CL_VREF1
ICH_FAN_PWM0
ICH_FAN_PWM1
TACH0
R591 X_0R0402
TACH1
R590 X_0R0402
GPIO_6
GPIO_7
Open Drain Ouput
ICH_FAN_PWM0
ICH_FAN_PWM1
3
SATA_RX#0 22
SATA_RX0 22
SATA_TX#0 22
SATA_TX0 22
SATA_RX#1 22
SATA_RX1 22
SATA_TX#1 22
SATA_TX1 22
SATA_RX#2 22
SATA_RX2 22
SATA_TX#2 22
SATA_TX2 22
SATA_RX#3 22
SATA_RX3 22
SATA_TX#3 22
SATA_TX3 22
CK_ICHSATA# 13
CK_ICHSATA 13
R107 24.9R1%0402
SATALED# 23
RN11 8P4R-10KR0402
SPI_WP# 10
SPI_HOLD# 10
RN12 8P4R-10KR0402
2
4
6
8
SSTCTL 14
1
2
3
4
5
6
7
8
LPC_PME# 14
PHY_DIS# 16
R119 4.7KR0402
1
3
5
7
C79C0.1U16Y0402
VBAT
CL_N_CLK 8
CL_N_DATA 8
R597 0R0402
R593 X_0R0402
R592 X_0R0402
AFSC_CPUFAN_IN 14,27
AFSC_SYSFAN_IN 14,27
R599 X_10KR0402
R598 X_10KR0402
V_1P5_ICH
CL_PWROK 8
CL_RST 8
Unused SATAxGP pins must be
terminated using 8.2k ohm to 10k
ohm pull-up resistors to
VCC3.(For device hot swap)
VCC3
VCC3
VCC3
Enable internal 2.5V VRM
RTCX1
RTCX2
PWRGD
AFSC_CPUFAN_PWM 27
AFSC_SYSFAN_PWM 27
VCC5
R123
10MR
VCC3_SB
1 2
R128
_3.24KR1%0402
1 2
R131
453R1%
CMOS CLEAR
JBAT1 (1-2)
N31-1030151+N33-1020271-RH
C80
C10P50N
4
Y1
3
32.768KHZ12.5P_D-RH
C83
C10P50N
CL_VREF_ICH = 0.405V
CL_VREF_ICH
C85
C0.01U25X0402
2
JBAT1
CLEARNORMAL
(2-3)
VCC3_SB
2
R116
100R0402
1
2
3
VBAT
D1
S-BAT54C_SOT23-RH
3
1
VBAT_DZ
R115 20KR1%0402
C78
C1U16Y
R113 1KR1%0402
RTC_RST#
C77
C1U16Y
BAT1
Close to Pin AA2 of ICH6.
ICH8 PULL-UP RESISTORS
ALL COMPONENTS CLOSE TO ICH8
Trace length is less than 3inchs to ICH8.
GPIO_12
SMB_ALERT#
SM_LINK1
GPIO_14
LPC_PME#
RI#
GPIO_13
BATLOW#
LPC_PD#
SM_LINK0
GPIO_10
LINK_ALERT#
GPIO_6
GPIO_7
SATALED#
LDRQ_1#
RN14 8P4R-10KR0402
SMBCLK_MAIN
SMBDATA_MAIN
GPIO_0
CL_PWROK
INTVRMEN
LAN100_SLP
INTRUDER#
PWRGD
CL_VREF1
FP_RST#
WAKE#
CLEAR_PASSWORD
R114 10KR0402
VCC3
R117 0R0402
VRM_GD24,26
R118 100KR0402
SM_LINK0
R627 0R0402
R626 0R0402
WOL
AC_BITCLK15
AC_RST#15
AC_SDOUT15
AC_SYNC15
AC_SDIN015
Title
Size Document Number Rev
Date: Sheet
AC_BITCLK
AC_SDOUT
AC_SYNC
C82
X_C20P50N0402
MICRO-START INT'L CO.,LTD.
Intel ICH8 DH - 2
MS-7278
1
2
3
4
5
6
7
8
RN8 8P4R-10KR0402
1
2
3
4
5
6
7
8
RN9 8P4R-10KR0402
1
2
3
4
5
6
7
8
RN10 8P4R-10KR0402
1
2
3
4
5
6
7
8
R106 X_4.7KR0402
R100 X_4.7KR0402
R110 1KR1%0402
R636 X_4.7KR0402
R125 390KR0402
R121 390KR0402
R99 1MR0402
R98 10KR0402
R649 1KR1%0402
R108 8.2KR0402
R109 1KR1%0402
R101 1KR1%0402
R61010KR0402
R129100KR0402
R602 33R0402
R603 33R0402
R605 33R0402
R604 33R0402
R601 33R0402
C81
X_C10P50N0402
Please close to SB
1
VRM_PWRGD
SMBCLK_MAIN
SMBDATA_MAINSM_LINK1
AC_BITCLK_ICH
ACRST#AC_RST#
ACSDOUT
ACSYNC
ACSDIN0AC_SDIN0
11 37Wednesday, August 16, 2006
12
BAT1
BAT-2P-RH-1
VCC3_SB
VCC3
VCC3
VBAT
VCC3_SB
VCC3_SB
of
100
5
4
3
2
1
5VREF & 5VREF_SUS Sequencing Circuit
N16
N17
N18
N27
N28
P12
P13
P14
P15
P16
P17
P22
P27
R11
R12
R13
R14
R15
R16
R17
R18
T12
T13
T14
T15
T16
T17
T22
T25
T26
U12
U13
U14
U15
U16
U17
U27
U28
VSS_125
VSS_126
VSS_177
VSS_178
AH4
AH13
VSS_127
VSS_128
VSS_179
VSS_180
AH16
AH19
VSS_129
VSS_130V7VSS_131
VSS_181
VSS
G5
AH22
2
V13
VCC3
R132 10R1%0402
VCC5
D D
VCC3_SB
VCC5_SB
C C
V_1P5_ICH
V_1P5_ICH
B B
V_1P5_ICH
A A
R133 10R1%0402
CP14 X_COPPER
1 2
L11
X_10U100m_0805-LF
CP15 X_COPPER
1 2
L12
X__1U500m_0805-RH
CP16 X_COPPER
1 2
L13
X_10U100m_0805-LF
5
B
N-SST3904_SOT23
C87
C0.1U16Y0402
CE
Q6
N-SST3904_SOT23
5VREF_SUS
C95
C0.1U16Y0402
C100
C10U10Y0805
C109
C10U10Y0805
C114
C10U10Y0805
5VREF
VCCSATAPLL
C101
C0.1U16Y0402
GLAN_PLL
C110
C0.1U16Y0402
VCCDMIPLL
C115
C0.1U16Y0402
V_1P5_ICH
C0.1U16Y0402
L10
21
80L4_40_1206-RH
V_1P25_CORE
C10U10Y0805
Close to ICH8DH
C89
C98 C0.1U16Y0402
C102 C0.1U16Y0402
C104 C0.01U25X0402
C106 C10U10Y0805
C333
C116 C0.1U16Y0402
C117 C0.1U16Y0402
C118 C0.01U25X0402
C120 C10U10Y0805
CE
Q5
B
V_1P5_ICH
VCC_CL_1_5
VCC3_SB
VCC3
C332
C10U10Y0805
V_1P5_ICH
VCCSATAPLL
VCCDMIPLL
GLAN_PLL
VCC3_SB
VCC3_SB
C0.1U16Y0402
V_1P5_FILTER
12
+
EC14
CD470U16EL11.5-RH
V_1P5_ICH
4
5VREF
5VREF_SUS
C93
G12
G15
AB9
AB13
AB14
AC13
AB7
AD7
AE12
AF11
AH5
G20
M23
M24
W22
W23
W24
AA26
AA27
AA28
AE27
AE28
AA5
AA6
AB3
AB4
AB5
AC1
AC2
AC3
A15
Y22
A21
P28
A25
F20
B26
B25
A27
A26
J22
J23
J24
K22
K23
K24
L22
L23
L24
N22
N23
N24
P23
P24
P25
P26
R22
R23
R26
R27
R28
T23
T24
U22
U23
U24
V23
V24
Y23
Y24
Y25
Y26
A2
C1
F3
T7
U5
U6
V3
V4
V5
W1
W2
W3
U7
V6
W6
Y6
V5REF
V5REF_SUS
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC_CL_1_5
VCCSUSHDA
VCCHDA
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCUSBPLL
VCCSATAPLL
VCCDMIPLL
VCCGLANPLL
VCCSUS3_3
VCCCL3_3
VCCCL3_3
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCCGLAN1_5
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCC1_5_B
VCCDMI
VCCDMI
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VSS_134
VSS_135
V25
V26
VSS_086
VSS_136
VSS_137
VSS_138Y3VSS_139Y4VSS_140Y5VSS_141
W27
W28
VSS_087
VSS_088
VSS_089
AA1
VSS_090
VSS_091
VSS_142
VSS_143
AA2
AA23
VSS_092
VSS_093
VSS_144
VSS_145
AB12
AB24
VSS_094
VSS_095
VSS_146
VSS_147
AB25
AB26
3
VSS_096
VSS_097
VSS_098
VSS_099
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
ICH 8
PART 3/3
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
AC6
AC9
AD3
AD4
AC15
AC18
AC21
AC27
AC28
VSS_105
VSS_106
VSS_107T3VSS_108T4VSS_109T5VSS_110T6VSS_111
VSS_157
VSS_158
VSS_159
VSS_160
AE1
AD5
AD11
AD26
VSS_161
VSS_162
AE2
AE5
VSS_112
VSS_163
VSS_164
AE8
AE14
VSS_113
VSS_114
VSS_165
VSS_166
AE17
AE20
VSS_115
VSS_116
VSS_167
VSS_168
AF3
AE23
VSS_117
VSS_118
VSS_169
VSS_170
AF4
AG1
VSS_119
VSS_120U1VSS_121U2VSS_122
VSS_171
VSS_172
VSS_173
AG2
AG5
AG11
VSS_123
VSS_174
VSS_175
AG25
AG27
VSS_124
VSS_176
AH3
U17C [INTEL-NH82801HH-B1[QM36]-RH]
V15
V22
VCCLAN1_05
VSS_133
VSSKUMBG
VSSAUBGP4VSSASATABG
VSSA3GBG
F4
B22
VCCLAN1_05
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
VCC1_05
V_CPU_IO
V_CPU_IO
VCC3_3
VCC3_3
VCCGLAN3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCC3_3
VCCLAN3_3
VCCLAN3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS3_3
VCCSUS1_05
VCCSUS1_05
VCCCL1_05
VCCSUS1_5
VCCSUS1_5
VSS_132
VSS_ICHDET
AH8
AF27
F17
G17
D1
L6
L7
M6
M7
W7
Y7
AA7
A23
B23
C23
D23
E23
F23
G22
G23
H22
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
AD25
AE26
AF28
P5
A22
A6
B4
B15
B18
C8
C10
D14
E10
F11
G14
F19
G19
N6
N7
P1
P2
P3
P6
P7
R3
R4
R5
R6
R7
AB16
AB21
AC20
AD18
AF19
J6
AB17
A20
AB15
J7
Title
Size Document Number Rev
Date: Sheet
C86 C0.1U16Y0402
C94 C0.1U16Y0402
C88 C0.1U16Y0402
C90 C2.2U6.3Y
C91 C2.2U6.3Y
C96 C0.1U25Y
C92 C0.1U25Y
V_FSB_VTT
VCC3
C97 C1U16Y
C99 C0.1U16Y0402
C103 C0.1U16Y0402
C105 C0.1U16Y0402
C107 C0.1U16Y0402
VCC3_SB
C111 C0.1U16Y0402
C112 C0.022U25X0402
C113 C0.022U25X0402
VCCSUS_1_5-1
VCCSUS_1_5-2
V_1P05EP_INT
V_1P5_SB_INT
V_1P5_SB_INT
C124
C4.7U10Y0805
Intel ICH8 DH - 3
V_1P5_ICH
V_1P05_ICH
Botton Compoment
VCC3_SB
C108
C0.1U16Y0402
C119 X_C0.01U25X0402
C121 X_C0.01U25X0402
C123
C0.1U16Y0402
C125
C1U16Y
C122
C10U10Y0805
MICRO-START INT'L CO.,LTD.
MS-7278
1
12 37Monday, August 21, 2006
100
of
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