![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg1.png)
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2
3
4
5
MS-7274
Title
A A
COVER SHEET
BLOCK DIAGRAM
Intel LGA775
nVIDIA C19
DDR II DIMM 1 & 2 Channel A
DDR II DIMM 3 & 4 Channel B
DDR II Termination
PCI-Express X16 & X1 Slot
Version 0A
Page
1
2
3 , 4 , 5
6 , 7 , 8 , 9 ,10
11
12
13
14
MCP04 15 , 16 , 17 , 18
B B
LPC ROM ,IDE & SATA
LPC SIO - W83627EHG-H & FDD
KB/MS , LPT & FAN
Audio Codec -ALC850
Audio Jacks
USB CONNECTORS
LAN PHY RTL8201CL
PCI Slot 1,2
IEEE1394 -VT6307 /6308P
ACPI controller -MS7
C C
Regulators 1
Regulators 2
VRM10 PWM -Intsill ISL6316
ATX & Front Panel
Misc
History
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
Intel LGA775 Processor
NVIDIA C19 & MCP04
CPU:
Intel - up to 3.8G(Single core) & 3.2G(Dual core)
System Chipset:
NVIDIA Crush19 - North Bridge
NVIDIA MCP04 - South Bridge
On Board Chipset:
BIOS -- LPC EEPROM- 4M
REALTAK ALC850 AC97 Audio ( 7.1 Channel)
LPC Super I/O -- W83627EHG-H
LAN--PHY RTL8201CL
1394 -- VIA- VT6307/8 with PHY
CLOCK -- Integrate to System Chipset
Main Memory:
DDR II * 4 (Max 4GB)
Expansion Slots:
PCI EXPRESS X16 SLOT * 1
PCI EXPRESS X1 SLOT * 1
PCI 1,2 SLOT * 2
SATA *4
PCI Routing Table
PCI Device
D D
PCI Slot 1
PCI Slot 2
(Add MEDION SPEC)
IEEE1394
1
AD21
AD22
AD23
AD25 4 X
0
1
3
INTERRUPTIDSEL REQ/GNT
X
Y
Z2
WAD24
2
PCI CLK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK1394
Intersil PWM:
3
Controller: Intsill ISL6316 4 Phase
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
Cover Sheet
Cover Sheet
Cover Sheet
0A
0A
134Monday, January 16, 2006
134Monday, January 16, 2006
134Monday, January 16, 2006
5
0A
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg2.png)
1
Block Diagram
2
3
4
5
A A
VRD 10.1
MS-10
4-Phase
Intel LGA775 Processor
PWM
FSB
133/200/266 MHz
PCI EXPRESS
PCI EXPRESS
X16 Slot
PCIE X1
Slot
B B
X16
PCI EXPRESS
X1
UltraDMA
33/66/100
NVIDIA
CRUSH19
Channel A
200/266/333/400 MHz
Channel B
200/266/333/400 MHz
HyperTransport
DDR II
DIMM
Modules
1, 2
DDR II
DIMM
Modules
3, 4
IEEE 1394
VIA6308
IDE x1
SATA II
C C
SATA II x4
USB 2.0
NVIDIA
MCP04
PCI
USB Port x 8
PCI Slot 1 Add
MEDION spec
AC97 5.1 Ch
AC'97
LPC Bus
PCI Slot x2
ALC850
MII
RTL8201CL
RGMII
LPC Super I/O
Winbond
W83627EHF
D D
FloopyLPC ROM
ParallelKeyboard
Serial
Mouse
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
1
2
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
<Doc> 0A
<Doc> 0A
<Doc> 0A
234Monday, January 16, 2006
234Monday, January 16, 2006
234Monday, January 16, 2006
5
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg3.png)
1
2
3
4
5
Reserved for Daul Core CPU
VCC_VRM_SENSE 31
VSS_VRM_SENSE 31
X_10KR0402
GTLREF_SEL
C73
C73
VTT_OUT_RIGHT
C68
C68
C0.1U16Y0402
C0.1U16Y0402
X_10KR0402
VTT_OUT_RIGHT 4,5,6
H_FORCEPH 31
H_A#[3..35]6
H_A#7
H_A#4
H_A#31
H_A#30
H_A#28
H_A#24
AG6
E21
AF4
A29#
D42#
F20
H_D#41
H_A#27
AF5
A28#
D41#
E19
H_D#40
H_A#26
AB4
A27#
D40#
E18
H_D#39
H_A#25
AC5
A26#
D39#
F18
H_D#38
AB5
A25#
D38#
F17
H_D#37
H_A#23
A24#
D37#
H_D#36
H_A#32
H_A#33
H_A#29
H_A#34
A A
U8A
U8A
H_DBI#[0..3]6
H_EDRDY#6
H_FERR#6
H_STPCLK#6
H_INIT#6
H_DBSY#6 H_PCREQ# 6
H_DRDY#6
H_TRDY#6
H_ADS#6
H_LOCK#6
H_BNR#6
H_HIT#6
B B
C C
D D
H_HITM#6
H_DEFER#6
CPU_TMPA20
VTIN_GND20
TRMTRIP#6
H_PROCHOT#6,31
H_SLP6
VTT_OUT_RIGHT
H_FSBSEL04,6
H_FSBSEL14,6
H_FSBSEL24,6
H_CPURST#6
H_D#[0..63]6
H_BPRI#6
H_IGNNE#6
H_SMI#6
H_A20M#6
H_PWRGD6
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_IERR
H_TDI
H_TMS
H_TRST#
H_TCK
R120
R120
X_0R0402
X_0R0402
R97 62R0402R97 62R0402
H_PWRGD
H_CPURST#
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
TESTI_13
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
H_A#35
AJ6
AJ5
AH5
AH4
AG5
AG4
A35#
A34#
A33#
A32#
A31#
A30#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
B15
A14
C14
C15
D17
H_D#50
H_D#51
H_D#49
H_D#53
H_D#52
F21
E22
D20
D22
G22
G21
H_D#48
H_D#43
H_D#47
H_D#42
H_D#44
H_D#46
H_D#45
AA5
G17
H_A#22
AD6
A23#
D36#
G18
H_D#35
H_A#21
AA4
A22#
D35#
E16
H_D#34
H_A#20
H_A#19
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
E15
G16
H_D#32
H_D#33
H_A#18
D32#
G15
H_D#31
H_A#17
AB6
D31#
F15
H_D#30
H_A#16
D30#
H_D#29
H_A#15
H_A#12
H_A#11
H_A#13
H_A#14
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D29#
D28#
D27#
D26#
D25#
D24#
F14
F12
E13
D13
G14
G13
H_D#24
H_D#25
H_D#28
H_D#26
H_D#27
H_A#10
U6
F11
H_D#23
H_A#9
D23#
H_D#22
H_A#6
H_A#8
H_A#5
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
H_D#21
H_D#20
H_D#18
H_D#19
H_A#3
L5
AN4
AC2
AN3
DBR#
VSS_SENSE
VCC_SENSE
D14#
D13#
D12#D8D11#
B12
D11
C12
C11
H_D#17
H_D#14
H_D#16
H_D#11
H_D#12
H_D#15
H_D#13
VCC_VRM_SENSE
VSS_VRM_SENSE
AN6
AN5
VCC_MB_REGULATION
D10#
B10
A11
H_D#9
H_D#10
VSS_MB_REGULATION
D9#
AJ3
D8#
A10
H_D#7
H_D#8
TP1TP1
1
VID5
VID4
VID3
AM7
AM5
AL4
AK4
AK3
ITP_CLK1
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
H_D#6
AL6
VID6#
VID5#
VID4#
VID_SELECT
ITP_CLK0
RSVD#AM7
GTLREF_SEL
FORCEPH
LINT1/NMI
LINT0/INTR
B4
H_D#0
H_D#5
H_D#4
H_D#2
H_D#1
H_D#3
VID[0..5] 31
VID1
VID2
VID0
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
AN7
H1
GTLREF0
H2
GTLREF1
H29
E24
GTLREF2
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
TESTHI12
P1
TESTHI11
H5
TESTHI10
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
G6
RSVD#G6
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
ADSTB1#
R6
ADSTB0#
C17
DSTBP3#
G19
DSTBP2#
E12
DSTBP1#
B9
DSTBP0#
A16
DSTBN3#
G20
DSTBN2#
G12
DSTBN1#
C8
DSTBN0#
L1
K1
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
R50 62R0402R50 62R0402
GTLREF_SEL
C19_GTLREF_CPU
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
H_FORCEPH
RSVD_G6
H_RS#2
H_RS#1
H_RS#0
H_BR#0
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
1
1
1
1
CPU_GTLREF0 4
C19_GTLREF_CPU 6
Underneath CPU
C55
C55
C220P16X0402
C220P16X0402
H_REQ#[0..4] 6
RN108P4R-62R0402RN108P4R-62R0402
H_TESTHI1
H_BR#0
R136 62R0402R136 62R0402
R163 60.4R1%0402R163 60.4R1%0402
R82 X_130R1%0402R82 X_130R1%0402
R113 X_60.4R1%0402R113 X_60.4R1%0402
CK_H_CPU# 6
CK_H_CPU 6
H_RS#[0..2] 6
1
TP2TP2
1
TP3TP3
R109 60.4R1%0402R109 60.4R1%0402
R115 60.4R1%0402R115 60.4R1%0402
R111 60.4R1%0402R111 60.4R1%0402
R123 60.4R1%0402R123 60.4R1%0402
R110 60.4R1%0402R110 60.4R1%0402 C79
R139 60.4R1%0402R139 60.4R1%0402
TP4TP4
TP5TP5
TP6TP6
TP7TP7
H_ADSTB#1 6
H_ADSTB#0 6
H_DSTBP#3 6
H_DSTBP#2 6
H_DSTBP#1 6
H_DSTBP#0 6
H_DSTBN#3 6
H_DSTBN#2 6
H_DSTBN#1 6
H_DSTBN#0 6
H_NMI 6
H_INTR 6
1
3
5
7
1
3
5
7
RN128P4R-62R0402RN128P4R-62R0402
V_FSB_VTT
If stuff Dual Core circuit
remove this R480
2
4
6
8
2
4
6
8
C79
X_C0.1U16Y0402
X_C0.1U16Y0402
VTT_OUT_LEFT
C0.1U16Y0402
C0.1U16Y0402
VTT_OUT_RIGHT
H_BR#0 6
VTT_OUT_LEFT 4,6
+12V
R153
R153
G
C74
C74
C0.1U16Y0402
C0.1U16Y0402
VID2
VID3
VID4
VID0
VID5
TESTI_13
V_FSB_VTT
C69
C69
C0.1U16Y0402
C0.1U16Y0402
VCC3
R165
R165
02
FSB FREQUENCY
VCC3
R166
R166
X_110R1%0402
X_110R1%0402
TABLE
R160
R160
X_249R1%0402
X_249R1%0402
DS
Q26
Q26
X_N-2N7002_SOT23
X_N-2N7002_SOT23
H_TESTHI0
X_60.4R1%0402
X_60.4R1%0402
BSEL
1
267 MHZ (1067)000
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
RN4
RN4
8P4R-680R
8P4R-680R
1
2
3
4
5
6
7
8
R84 680R0402R84 680R0402
R86 680R0402R86 680R0402
R118 150R0402R118 150R0402
R107 X_150R0402R107 X_150R0402
R173 62R0402R173 62R0402
RN5
RN5
1
2
3
4
5
6
7
8
8P4R-62R0402
8P4R-62R0402
RN6
RN6
1
2
3
4
5
6
7
8
8P4R-62R0402
8P4R-62R0402
RN8
RN8
7
8
5
6
3
4
1
2
8P4R-62R0402
8P4R-62R0402
PLACE BPM TERMINATION NEAR CPU
C155
C155
X_C0.1U16Y0402
X_C0.1U16Y0402
VTT_OUT_RIGHTVID1
VTT_OUT_LEFTH_PWRGD
H_CPURST#
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TCK
H_BPM#2
H_BPM#4
H_TRST#
H_TDI
H_IERR
H_TMS
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
1
2
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
<Doc> 0A
<Doc> 0A
<Doc> 0A
334Monday, January 16, 2006
334Monday, January 16, 2006
334Monday, January 16, 2006
5
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg4.png)
1
VCCP
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF22
AF21
AF9
VCC#AF19
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8
AF8
VCC#AF9
VCC#AF8
VCC#AF22
VCC#AF21
VCC#Y8
Y8
VCC#AG14
VCC#AG12
VCC#AG11
VCC#Y25
VCC#Y26
VCC#Y27
VCC#Y28
VCC#Y29
VCC#Y30
Y25
Y26
Y27
Y28
Y29
Y30
VCC#AG25
VCC#AG22
VCC#AG21
VCC#AG19
VCC#AG18
VCC#AG15
VCC#W28
VCC#W29
VCC#W30
VCC#W8
VCC#Y23
VCC#Y24
W8
Y23
Y24
W30
W29
W28
W27
U8B
U8B
VCCP
A A
B B
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
VCC#AG28
VCC#AG27
VCC#AG26
VCC#W25
VCC#W26
VCC#W27
W25
W26
VCC#AG30
VCC#AG29
VCC#W24
W23
W24
AG8
VCC#AG8
VCC#V8V8VCC#W23
AG9
VCC#AG9
VCC#U8
U8
VCC#AH12
VCC#AH11
VCC#U29
VCC#U30
U29
U30
VCC#AH15
VCC#AH14
VCC#U27
VCC#U28
U27
U28
VCC#AH19
VCC#AH18
VCC#U25
VCC#U26
U25
U26
VCC#AH21
VCC#U24
U24
AH22
U23
2
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
VCC#AJ15
VCC#N8
N8
N30
VCC#AJ18
VCC#AJ19
VCC#N29
VCC#N30
N28
N29
VCC#AJ21
VCC#AJ22
VCC#N27
VCC#N28
N26
N27
AJ26
AJ8
VCC#AJ25
VCC#AJ26
VCC#N25
VCC#N26
N24
N25
AJ9
VCC#AJ8
VCC#AJ9
VCC#N24
N23
VCC#AK11
VCC#M8M8VCC#N23
M30
VCC#AK12
VCC#AK14
VCC#M29
VCC#M30
M28
M29
AH27
AH26
AH25
AH28
AH29
AH30
AH8
AH9
VCC#AH8
VCC#AH9
VCC#AJ11
VCC#AJ12
VCC#AH27
VCC#AH26
VCC#AH25
VCC#AH22
VCC#AH28
VCC#AH29
VCC#T27
VCC#T28
VCC#T29
VCC#T30
VCC#T8T8VCC#U23
T27
T28
T29
T30
VCC#AJ14
VCC#AH30
VCC#P8P8VCC#R8
VCC#T23
VCC#T24
VCC#T25
VCC#T26
R8
T23
T24
T25
T26
AK26
AK8
AK9
VCC#AK8
M25
VCC#AK9
VCC#AK21
VCC#AK22
VCC#AK25
VCC#AK26
VCC#K30
VCC#K8K8VCC#L8L8VCC#M23
VCC#M24
VCC#M25
K30
M23
M24
VCC#AK15
VCC#AK18
VCC#AK19
VCC#M26
VCC#M27
VCC#M28
M26
M27
3
AM8
AM9
AN11
AN12
AN14
AN15
VCC#AM8
VCC#AM9
VCC#J10
VCC#J11
J10
AN9
VCC#AN11
VCC#AN12
VCC#AN14
VCC#AN30
VCC#AN8
VCC#AN9
AN8
AN30
AN18
VCC#AN15
VTT_OUT_RIGHT
VCC#AN29
AN26
AN29
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
VCC#AL8
VCC#AL11
VCC#AL12
VCC#AL14
VCC#AL15
VCC#AL18
VCC#AL19
VCC#AL21
VCC#AL22
VCC#K24
VCC#K25
VCC#K26
VCC#K27
VCC#K28
VCC#K29
K23
K24
K25
K26
K27
K28
K29
VCC#AL25
VCC#J8J8VCC#J9J9VCC#K23
J30
VCC#AL26
VCC#AL29
VCC#J29
VCC#J30
J28
J29
VCC#AL30
VCC#J27
VCC#J28
J26
J27
VCC#AL9
VCC#AM11
VCC#J25
VCC#J26
J24
J25
VCC#AM12
VCC#AM14
VCC#J23
VCC#J24
J22
J23
VCC#AM15
VCC#AM18
VCC#J21
VCC#J22
J20
J21
VCC#AM19
VCC#AM21
VCC#J19
VCC#J20
J18
J19
VCC#AM22
VCC#AM25
VCC#J15
VCC#J18
J14
J15
VCC#AM26
VCC#AM29
VCC#J13
VCC#J14
J12
J13
VCC#AM30
VCC#J12
J11
AN19
AN21
AN22
VCCA
VSSA
VCC#AN18
VCC#AN19
VCC#AN21
VCC#AN22
VCCPLL
VCC-IOPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTTPWRGD
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC#AN25
VCC#AN26
1122334
AN25
4
A23
B23
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
4
H_VCCA
H_VSSA
H_VCCA
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
1
TP10TP10
V_FSB_VTT
5
V_FSB_VTT
C145 C0.1U16X0402C145 C0.1U16X0402
C144 C0.1U16X0402C144 C0.1U16X0402
V_FSB_VTT
C137 X_C10U6.3X50805C137 X_C10U6.3X50805
C141 X_C10U6.3X50805C141 X_C10U6.3X50805
C130 C10U6.3X50805C130 C10U6.3X50805
CAPS FOR FSB GENERIC
CPU DECOUPLING CAPACITORS
Place these caps within socket cavity
VTT_OUT_LEFT
C C
D D
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
L3 X_10U100m_0805L3 X_10U100m_0805
CP3
CP3
1 2
X_COPPER
X_COPPER
VTT_OUT_RIGHT3,5,6
1
VID_GD#28,31
R117 124R1%0402R117 124R1%0402
R114
R114
210R1%0402
210R1%0402
VTT_OUT_RIGHT
VCC5_SB
R104
R104
1KR0402
1KR0402
R103
R103
10KR0402
10KR0402
C117
C117
C1U16X5
C1U16X5
R121 10R0402R121 10R0402
C86
C86
C1U16Y
C1U16Y
R80
R80
680R0402
680R0402
B
C93
C93
C220P16X0402
C220P16X0402
C122
C122
C10U6.3X50805
C10U6.3X50805
VTT_PWG
CE
Q12
Q12
N-MMBT3904_SOT23
N-MMBT3904_SOT23
C119
C119
C10U6.3X50805
C10U6.3X50805
2
CPU_GTLREF0 3VTT_OUT_LEFT3,6
C64
C64
X_C1U16Y
X_C1U16Y
H_VCCA
H_VSSA
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
CPU DECOUPLING CAPACITORS
Place these caps within socket Solder Side
VCCP
12
+
RN27
RN27
2
4
6
8
8P4R-1KR0402
8P4R-1KR0402
+
EC54
EC54
X_C100U2SP-LF
X_C100U2SP-LF
12
+
12
+
+
EC53
EC53
X_C100U2SP-LF
X_C100U2SP-LF
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
3
+
V_FSB_VTT
EC52
EC52
X_C100U2SP-LF
X_C100U2SP-LF
1
3
5
7
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
VCCP
H_FSBSEL1 3,6
H_FSBSEL0 3,6
H_FSBSEL2 3,6
4
12
+
+
EC15
EC15
C100U2SP-LF
C100U2SP-LF
VCCP
C94
C94
C91
C91
C87
C96
C96
X_C10U6.3X51206
X_C10U6.3X51206
C10U6.3X51206
C10U6.3X51206
VCCP
C95
C98
C98
C10U6.3X51206
C10U6.3X51206
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
C95
C92
C92
X_C10U6.3X51206
X_C10U6.3X51206
X_C10U6.3X51206
X_C10U6.3X51206
MS-7274
MS-7274
MS-7274
Intel LGA775 - Power 0A
Intel LGA775 - Power 0A
Intel LGA775 - Power 0A
C87
X_C10U6.3X51206
X_C10U6.3X51206
C10U6.3X51206
C10U6.3X51206
C97
C97
C84
C84
C10U6.3X51206
C10U6.3X51206
C10U6.3X51206
C10U6.3X51206
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
5
C99
C99
C10U6.3X51206
C10U6.3X51206
C88
C88
X_C10U6.3X51206
X_C10U6.3X51206
C83
C83
C10U6.3X51206
C10U6.3X51206
434Monday, January 16, 2006
434Monday, January 16, 2006
434Monday, January 16, 2006
of
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg5.png)
1
2
3
4
5
V26
V25
V24
VSS#V27
VSS#V26
VSS#V25
VSS#AH3
VSS#AH6
VSS#AH7
AH6
AH7
AJ10
MSID1 MSID0
T3
V23
U1
VSS#T7T7VSS#T6T6VSS#T3
VSS#U7U7VSS#U1
VSS#V24
VSS#V23
VSS#AJ10
VSS#AJ13
VSS#AJ16
VSS#AJ17
VSS#AJ20
VSS#AJ23
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
P30
P29
P28
P27
P26
P25
P24
P23
VSS#P24
VSS#AK7
M1
L30
L29
L28
L27
N3
L6
VSS#L7L7VSS#L6
VSS#N7N7VSS#N6N6VSS#N3
VSS#M7M7VSS#M1
VSS#P23
VSS#AL10
VSS#AL13
VSS#AL16
VSS#AL17
VSS#AL20
VSS#AL23
VSS#AL24
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
L26
L3
VSS#L3
VSS#L30
VSS#L29
VSS#L28
VSS#L27
VSS#AL27
VSS#AL28
VSS#AL3
VSS#AL7
VSS#AM1
VSS#AM10
AL3
AL7
AM1
AL28
AM10
AM13
VSS#L26
VSS#AM13
L25
AM16
VSS#L25
VSS#AM16
L24
AM17
VSS#L24
VSS#AM17
L23
AM20
VSS#L23
VSS#AM20
AM23
VSS#K7K7VSS#K5
VSS#AM23
K2
K5
J7
H9
VSS#J4J4VSS#J7
VSS#K2
VSS#AM24
VSS#AM27
VSS#AM28
AM24
AM27
AM28
AM4
VSS#AM4
VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9
VSS#AN1
VSS#AN10
VSS#AN13
VSS#AN16
AN1
AN10
AN13
AN16
AN17
R30
R29
R28
R27
R26
R25
R24
R23
R5
VSS#R7R7VSS#R5
VSS#R30
VSS#R29
VSS#R28
VSS#R27
VSS#AJ24
VSS#AJ27
VSS#AJ28
VSS#AJ29
VSS#AJ30
VSS#AJ4
VSS#AJ7
AJ4
AJ7
AJ27
AJ28
AJ29
AJ30
AK10
P4
R2
VSS#P7P7VSS#P4
VSS#R2
VSS#P30
VSS#P29
VSS#P28
VSS#P27
VSS#P26
VSS#R26
VSS#R25
VSS#R24
VSS#R23
VSS#AK10
VSS#AK13
VSS#AK16
VSS#AK17
VSS#AK2
VSS#AK20
AK2
AK13
AK16
AK17
AK20
AK23
VSS#P25
VSS#AK23
VSS#AK24
VSS#AK27
VSS#AK28
VSS#AK29
VSS#AK30
VSS#AK5
AK5
AK24
AK7
AK27
AK28
AK29
AK30
H23
H24
H25
H26
H27
H28
VSS#H24
VSS#H25
VSS#H26
VSS#H27
VSS#H28
VSS#AN17
VSS#AN2
VSS#AN20
VSS#AN23
VSS#AN24
VSS#AN27
AN2
AN20
AN23
AN24
AN27
AN28
H22
VSS#H22
VSS#H23
VSS#AN28
H21
H19
H20
VSS#H19
VSS#H20
VSS#H21
VSS#B1B1VSS#B11
VSS#B14
B11
B14
H17
H18
H14
VSS#H14
H13
VSS#H13
VSS#H17
VSS#H18
H12
VSS#H12
H11
VSS#H11
H10
VSS#H10
G1
VSS#G1
F7
VSS#F7
F4
VSS#F4
F22
VSS#F22
F19
VSS#F19
F16
VSS#F16
F13
VSS#F13
F10
VSS#F10
E8
VSS#E8
E29
VSS#E29
E28
VSS#E28
E27
VSS#E27
E26
VSS#E26
E25
VSS#E25
E20
VSS#E20
E2
VSS#E2
E17
VSS#E17
E14
VSS#E14
E11
VSS#E11
D9
VSS#D9
D6
VSS#D6
D5
VSS#D5
D3
VSS#D3
D24
VSS#D24
D21
VSS#D21
D18
VSS#D18
D15
VSS#D15
D12
VSS#D12
C7
VSS#C7
C4
VSS#C4
C24
VSS#C24
C22
VSS#C22
C19
VSS#C19
C16
VSS#C16
C13
VSS#C13
C10
VSS#C10
B8
VSS#B8
B5
VSS#B5
B24
VSS#B24
B20
VSS#B20
B17
VSS#B17
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
VTT_OUT_RIGHT3,4,6
R119
R85
R85
R99
R99
60.4R1%0402
VSS#A12
VSS#A15
VSS#A18
VSS#A2
VSS#A21
VSS#A24
VSS#A6
VSS#A9
VSS#AA23
VSS#AA24
VSS#AA25
VSS#AA26
VSS#AA27
VSS#AA28
VSS#AA29
VSS#AA3
VSS#AA30
VSS#AA6
VSS#AA7
VSS#AB1
VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30
VSS#AB7
VSS#AC3
VSS#AC6
VSS#AC7
VSS#AD4
VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17
VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
AE29
H_COMP6
COMP6Y3COMP7
VSS#AE29
VSS#AE30
AE30
H_COMP7
60.4R1%0402
TP11TP11
D14
AE3
D1
AE4
RSVD#D1
RSVD#AE4
VSS#AE5
VSS#AE7
VSS#AF10
AE5
AE7
AF10
AF13
1
E23
RSVD#D14
VSS#AF13
AF16
RSVD#E23
VSS#AF16
AF17
60.4R1%0402
A A
B B
C C
60.4R1%0402
U8C
U8C
A12
A15
A18
A2
A21
A24
A6
A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
R119
X_100R1%0402
X_100R1%0402
TP8TP8
TP9TP9
R122
R122
R108
R108
62R0402
62R0402
1
X_100R1%0402
X_100R1%0402
1
B13
E7
RSVD#E5E5RSVD#E6E6RSVD#E7
VSS#AF17
VSS#AF20
VSS#AF23
AF20
AF23
AF24
J3
RSVD#F23
VSS#AF25
N4
F6
IMPSEL#
RSVD#J3
RSVD#B13
VSS#AF26
VSS#AF27
VSS#AF28
VSS#AF29
VSS#AF3
AF3
AF26
AF27
AF28
AF29
AF30
F23
VSS#AF24
AF25
R100
R100
X_22R0402
X_22R0402
R101
R101
62R0402
62R0402
P5
W1
AC4
MSID[1]V1MSID[0]
RSVD#P5
RSVD#N4
RSVD#AC4
VSS#AF30
VSS#AF6
VSS#AF7
VSS#AG10
VSS#AG13
VSS#AG16
AF6
AF7
AG10
AG13
AG16
AG17
2005 Perf FMB 0 0
2005 Value FMB 0 1
V30
V29
V28
VSS#V7V7VSS#V6
VSS#AH13
V27
V6
V3
VSS#V3
VSS#V30
VSS#V29
VSS#V28
VSS#AH16
VSS#AH17
VSS#AH20
VSS#AH23
VSS#AH24
AH3
AH16
AH17
AH20
AH23
AH24
Y2
W4
VSS#Y7Y7VSS#Y5Y5VSS#Y2
VSS#W7W7VSS#W4
VSS#AG17
VSS#AG20
VSS#AG23
VSS#AG24
VSS#AG7
VSS#AH1
VSS#AH10
AH1
AG7
AH10
AG20
AH13
AG23
AG24
D D
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
1
2
3
4
Date: Sheet
MICRO-START INT'L CO.,LTD.
Intel LGA775 - GND 0A
Intel LGA775 - GND 0A
Intel LGA775 - GND 0A
5
of
534Monday, January 16, 2006
534Monday, January 16, 2006
534Monday, January 16, 2006
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg6.png)
1
A A
R144
R144
100R1%0402
100R1%0402
1 2
H_DBI#[0..3]
R140
R140
0R0402
0R0402
C126
C126
C0.1U16Y0402
C0.1U16Y0402
H_DBI#[0..3]3
B B
C C
1
VTT_OUT_RIGHT
VTT_OUT_LEFT
100R1%0402
100R1%0402
84.5R1%0402-LF
84.5R1%0402-LF
R142
R142
R141
R141
VTT_OUT_RIGHT3,4,5
VTT_OUT_LEFT3,4
D D
GTLREF VOLTAGE SHOULD BE
0.63*VTT
2
H_DSTBP#03
H_DSTBN#03
H_DSTBP#13
H_DSTBN#13
H_DSTBP#23
H_DSTBN#23
H_DSTBP#33
H_DSTBN#33
H_A#[3..35]3
H_REQ#[0..4]3
H_RS#[0..2]3
C132
C132
C0.1U16Y0402
C0.1U16Y0402
2
H_ADSTB#03
H_ADSTB#13
H_ADS#3
H_BNR#3
H_BR#03
H_DBSY#3
H_DRDY#3
H_HIT#3
H_HITM#3
H_LOCK#3
H_TRDY#3
H_PROCHOT#3,31
TRMTRIP#3
H_FERR#3
H_FSBSEL23,4
H_FSBSEL13,4
R147 60.4R1%0402R147 60.4R1%0402
R145 60.4R1%0402R145 60.4R1%0402
C133
C133
C220P16X0402
C220P16X0402
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_PROCHOT#
TRMTRIP#
H_FERR#
H_FSBSEL2
H_FSBSEL1
H_FSBSEL0
H_RS#0
H_RS#1
H_RS#2
R146
R146
511R1%0402
511R1%0402
C19_GTLREF_CPU 3
CAPS SHOULD
BE PLACED
NEAR C19 AND
CPU PIN
U12A
U12A
P4
CPU_DSTBP0*
P2
CPU_DSTBN0*
N3
CPU_DBI0*
W5
CPU_DSTBP1*
W7
CPU_DSTBN1*
T10
CPU_DBI1*
AD5
CPU_DSTBP2*
AE7
CPU_DSTBN2*
AC9
CPU_DBI2*
AA5
CPU_DSTBP3*
Y3
CPU_DSTBN3*
AC3
CPU_DBI3*
N8
CPU_A3*
L7
CPU_A4*
L10
CPU_A5*
N7
CPU_A6*
N6
CPU_A7*
L5
CPU_A8*
J4
CPU_A9*
J8
CPU_A10*
L9
CPU_A11*
J7
CPU_A12*
H8
CPU_A13*
J6
CPU_A14*
H7
CPU_A15*
H5
CPU_A16*
E5
CPU_A17*
H6
CPU_A18*
G6
CPU_A19*
G5
CPU_A20*
F5
CPU_A21*
F8
CPU_A22*
F6
CPU_A23*
G8
CPU_A24*
F7
CPU_A25*
E6
CPU_A26*
E8
CPU_A27*
D8
CPU_A28*
A3
CPU_A29*
C4
CPU_A30*
B3
CPU_A31*
A5
CPU_A32*
A4
CPU_A33*
C5
CPU_A34*
B4
CPU_A35*
L6
CPU_ADSTB0*
E7
CPU_ADSTB1*
N4
CPU_REQ0*
R5
CPU_REQ1*
L8
CPU_REQ2*
N9
CPU_REQ3*
M10
CPU_REQ4*
H3
CPU_ADS*
J5
CPU_BNR*
F3
CPU_BR0*
H1
CPU_DBSY*
H2
CPU_DRDY*
R6
CPU_HIT*
G3
CPU_HITM*
K2
CPU_LOCK*
H4
CPU_TRDY*
A8
CPU_PROCHOT*
D3
CPU_THERMTRIP*
D4
CPU_FERR*
AG4
CPU_BSEL2
AG3
CPU_BSEL1
AF3
CPU_BSEL0
J3
CPU_RS0*
M3
CPU_RS1*
J2
CPU_RS2*
C6
CPU_DRV0_VTT
B6
CPU_DRV1_GND
E4
GTL_VREF1
F2
GTL_VREF2
D5
CPU_CTERM_GND
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
C19
C19
1 OF 8
1 OF 8
CPU I/F
CPU I/F
PLACE DIVIDER RESISTOR NEAR VTT
3
CPU_D0*
CPU_D1*
CPU_D2*
CPU_D3*
CPU_D4*
CPU_D5*
CPU_D6*
CPU_D7*
CPU_D8*
CPU_D9*
CPU_D10*
CPU_D11*
CPU_D12*
CPU_D13*
CPU_D14*
CPU_D15*
CPU_D16*
CPU_D17*
CPU_D18*
CPU_D19*
CPU_D20*
CPU_D21*
CPU_D22*
CPU_D23*
CPU_D24*
CPU_D25*
CPU_D26*
CPU_D27*
CPU_D28*
CPU_D29*
CPU_D30*
CPU_D31*
CPU_D32*
CPU_D33*
CPU_D34*
CPU_D35*
CPU_D36*
CPU_D37*
CPU_D38*
CPU_D39*
CPU_D40*
CPU_D41*
CPU_D42*
CPU_D43*
CPU_D44*
CPU_D45*
CPU_D46*
CPU_D47*
CPU_D48*
CPU_D49*
CPU_D50*
CPU_D51*
CPU_D52*
CPU_D53*
CPU_D54*
CPU_D55*
CPU_D56*
CPU_D57*
CPU_D58*
CPU_D59*
CPU_D60*
CPU_D61*
CPU_D62*
CPU_D63*
CPU_PWRGD
CPU_RST*
CPU_ITP_CLK0
CPU_ITP_CLK1
CPU_BCLK0
CPU_BCLK1
CPU_ERDY*
CPU_PC_REQ*
CPU_BPRI*
CPU_DEFER*
CPU_A20M*
CPU_IGNNE*
CPU_INIT*
CPU_INTR
CPU_NMI
CPU_SMI*
CPU_SLP
CPU_STPCLK*
3
K4
M4
K3
M1
L3
M2
N2
N5
T4
T2
T3
T1
P3
U2
U3
U5
U8
P10
U7
U6
R8
U9
R3
U4
W6
W8
W9
V10
Y5
AA6
AA7
AA8
AA4
V4
AA9
AC8
AC5
Y10
AC7
AC6
AB10
AE6
AE8
AE4
AF5
AE9
AE2
AD10
AD4
AA2
V2
Y4
V3
W3
AB2
Y2
Y1
AA3
AD2
AD3
AB4
AB3
AD1
AE5
C2
AE10
B8
C7
AE3
AF2
F4
R7
T5
R9
E3
C1
C3
E1
D1
B2
D2
M5
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
CK_H_CPU_R
CK_H_CPU_R#
H_EDRDY#
H_PCREQ#
H_BPRI#
H_DEFER#
H_A20M#
H_IGNNE#
H_INIT#
H_INTR
H_NMI
H_SMI#
H_SLP
H_STPCLK#
H_D#[0..63] 3
H_PWRGD 3
H_CPURST# 3
R177 33R0402R177 33R0402
R179 33R0402R179 33R0402
H_EDRDY# 3
H_PCREQ# 3H_FSBSEL03,4
H_BPRI# 3
H_DEFER# 3
H_A20M# 3
H_IGNNE# 3
H_INIT# 3
H_INTR 3
H_NMI 3
H_SMI# 3
H_SLP 3
H_STPCLK# 3
4
R176
R176
60.4R1%0402
60.4R1%0402
4
R178
R178
60.4R1%0402
60.4R1%0402
Place near C19
V_FSB_VTT
C181
C181
C180
C180
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
Place underneath C19
V_FSB_VTT
C512
C512
Solder side footprint
C0603MS_BOT
TERMINATION CLOSE TO C19
C170
C170
C174
C174
X_C15P50N0402
X_C15P50N0402
C38、C39、C40、C41
H_PROCHOT#
H_NMI
H_INTR
TRMTRIP#
CK_H_CPU 3
CK_H_CPU# 3
X_C15P50N0402
X_C15P50N0402
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
5
C177
C177
C173
C173
X_C0.1U16Y0402
X_C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C514
C514
C515
C515
C0.1U25Y
C0.1U25Y
C0.1U25Y
C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
RN18
RN18
2
4
6
8
8P4R-150R0402
8P4R-150R0402
nVIDIA C19 - CPU Signals 0A
nVIDIA C19 - CPU Signals 0A
nVIDIA C19 - CPU Signals 0A
VTT_OUT_RIGHT
1
3
5
7
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
5
C90
C90
C0.1U16Y0402
C0.1U16Y0402
634Monday, January 16, 2006
634Monday, January 16, 2006
634Monday, January 16, 2006
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg7.png)
1
U12C
U12C
C19
AH25
C190
C190
C19_CLK#17
C19_CLK17
HT_RXCTL
AM25
HT_RXD7
AK25
HT_RXD6
AK24
HT_RXD5
AJ23
HT_RXD4
AM23
HT_RXD3
AN21
HT_RXD2
AJ21
HT_RXD1
AM20
HT_RXD0
AG25
HT_RXCTL*
AN25
HT_RXD7*
AL25
HT_RXD6*
AM24
HT_RXD5*
AH23
HT_RXD4*
AN23
HT_RXD3*
AM21
HT_RXD2*
AK21
HT_RXD1*
AL21
HT_RXD0*
AL23
HT_RX_CLK
AK23
HT_RX_CLK*
AG19
HT_PWRGD
AH19
HT_RESET*
AJ19
HT_STOP*
AG10
TMS
AJ5
TDI
AJ6
TDO
AJ3
TCK
AJ4
TRST*
AH26
HT_RX_COMP_GND
AG26
HT_TX_COMP_GND
AM4
TEST
R184
R184
10KR0402
10KR0402
VCC3
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
RN30
RN30
1
3
5
7
8P4R-10KR0402
8P4R-10KR0402
R217
R217
150R1%0402
150R1%0402
HT_UP7
HT_UP6
HT_UP5
HT_UP4
HT_UP3
HT_UP2
HT_UP1
HT_UP#8
HT_UP#7
HT_UP#6
HT_UP#5
HT_UP#4
HT_UP#3
HT_UP#2
HT_UP#1
HT_UP#0
HT_PWRGD
HT_RESET#
HT_STOP#
2
4
6
8
R218
R218
C0.1U16Y0402
C0.1U16Y0402
HT_UP[0..8]15
A A
HT_UP#[0..8]15 HT_DWN#[0..8] 15
HT_UP_CLK15
HT_UP_CLK#15 HT_DWN_CLK# 15
HT_PWRGD15
HT_RESET#15
HT_STOP#15
C19_VDD_PEX
Change from
VCC1_4 for
Layout.
B B
49.9R1%0402
49.9R1%0402
RN39
RN39
HT_STOP#
7
8
HT_REQ#
5
6
VCC3
C C
4
2
8P4R-1KR0402
8P4R-1KR0402
HT_PWRGD
3
HT_RESET#
1
C19
3 OF 8
3 OF 8
HT I/F
HT I/F
U11
U11
LT1087S_SOT89
LT1087S_SOT89
VIN3VOUT
ADJ
1
2
HT_TXCTL
HT_TXD7
HT_TXD6
HT_TXD5
HT_TXD4
HT_TXD3
HT_TXD2
HT_TXD1
HT_TXD0
HT_TXCTL*
HT_TXD7*
HT_TXD6*
HT_TXD5*
HT_TXD4*
HT_TXD3*
HT_TXD2*
HT_TXD1*
HT_TXD0*
HT_TX_CLK
HT_TX_CLK*
HT_REQ*
NC1
NC2
25MHZ_IN
CLKIN
CLKIN*
C271 C3900P50XC271 C3900P50X
R213
R213
49.9R1%0402
49.9R1%0402
R212
R212
49.9R1%0402
49.9R1%0402
C270
C270
C3900P50X
C3900P50X
PLACE CLOSE TO C19
2
R182
R182
158R1%0402
158R1%0402
AR20
AT21
AP21
AP22
AP23
AT24
AR25
AR26
AN26
AT20
AR21
AR22
AN22
AN24
AT25
AP25
AP26
AP27
AP24
AR24
AK19
AL3
D7
AL4
AR30
AP30
HT_DWN8HT_UP8
HT_DWN7
HT_DWN6
HT_DWN5
HT_DWN4
HT_DWN3
HT_DWN2
HT_DWN1
HT_DWN0HT_UP0
HT_DWN#8
HT_DWN#7
HT_DWN#6
HT_DWN#5
HT_DWN#4
HT_DWN#3
HT_DWN#2
HT_DWN#1
HT_DWN#0
HT_REQ#
C19_CLK_RC#
C266
C266
C0.01U16X0402
C0.01U16X0402
1 2
VDD_PE_PLL
C189
C189
C0.1U16Y0402
C0.1U16Y0402
VCC3
R219
R219
1.54KR1%0402
1.54KR1%0402
R216
R216
511R1%0402
511R1%0402
HT_DWN_CLK 15
HT_REQ# 15
C19_25MHZ_IN 17
C19_CLK_RC
HT_DWN[0..8] 15
VCC3
C19_VDD_PEX
X_C10U6.3X50805
X_C10U6.3X50805
CP4
CP4
1 2
X_COPPER
X_COPPER
C267
C267
C10U6.3X50805
C10U6.3X50805
C175
C175
3
PE_B_CLK#14
PE_CLKIN
PE_CLKIN#
C265
C265
C1U16X5
C1U16X5
L4
L4
X_30L500m_200
X_30L500m_200
C182
C182
C10U16Y1206
C10U16Y1206
PE_B_TXP14
PE_B_TXN14
PE_B_RXP14
PE_B_RXN14
PE_B_CLK14
R183
R183
100R1%0402
100R1%0402
C194
C194
C0.01U16X0402
C0.01U16X0402
1 2
1 2
C196
C196
C0.01U16X0402
C0.01U16X0402
C19_VDD_PLL
C260
C260
C0.1U16X0402
C0.1U16X0402
VDD_PE_PLL
C183
C183
C188
C188
C1U16X5
C1U16X5
PE_B_TXP
PE_B_TXN
PE_B_RXP
PE_B_RXN
PE_B_CLK
PE_B_CLK#
PE_C_CLK
PE_C_CLK#
PE_CLK_TEST
PE_CLK_TEST#
PE_CLKIN
PE_CLKIN#
X_C0.1U16X0402
X_C0.1U16X0402
R181
R181
2.43KR1%0402
2.43KR1%0402
AN6
AR6
AR5
AN1
AR4
AR3
AR2
AN2
AM8
AN7
AN4
AM1
AM6
AM7
AR8
AM2
AN3
AM5
AP29
AT29
AP6
AP5
AT5
AT4
AT3
AP2
AK8
AL8
AP4
AL6
AL7
AP8
AL5
AJ8
AJ7
AK2
AK5
AK3
4
U12B
U12B
PE1_TX0
PE1_TX0*
PE1_RX0
PE1_RX0*
PE1_REFCLK
PE1_REFCLK*
PE1_PRSNT*
PE2_TX0
PE2_TX0*
PE2_RX0
PE2_RX0*
PE2_REFCLK
PE2_REFCLK*
PE2_PRSNT*
PCI EXP I/F
PCI EXP I/F
PE3_TX0
PE3_TX0*
PE3_RX0
PE3_RX0*
PE3_REFCLK
PE3_REFCLK*
PE3_PRSNT*
PE4_TX0
PE4_TX0*
PE4_RX0
PE4_RX0*
PE4_REFCLK
PE4_REFCLK*
PE4_PRSNT*
PE0_PRSNT*
PE_CLK_TEST
PE_CLK_TEST*
VDD_PLL1_3P3
VDD_PLL2_3P3
PE_CLKIN
PE_CLKIN*
VDD_PE_PLL
PE_CTERM_GND
GND_PE_PLL
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
C19
C19
2 OF 8
2 OF 8
PE0_TX15
PE0_TX14
PE0_TX13
PE0_TX12
PE0_TX11
PE0_TX10
PE0_TX9
PE0_TX8
PE0_TX7
PE0_TX6
PE0_TX5
PE0_TX4
PE0_TX3
PE0_TX2
PE0_TX1
PE0_TX0
PE0_TX15*
PE0_TX14*
PE0_TX13*
PE0_TX12*
PE0_TX11*
PE0_TX10*
PE0_TX9*
PE0_TX8*
PE0_TX7*
PE0_TX6*
PE0_TX5*
PE0_TX4*
PE0_TX3*
PE0_TX2*
PE0_TX1*
PE0_TX0*
PE0_RX15
PE0_RX14
PE0_RX13
PE0_RX12
PE0_RX11
PE0_RX10
PE0_RX9
PE0_RX8
PE0_RX7
PE0_RX6
PE0_RX5
PE0_RX4
PE0_RX3
PE0_RX2
PE0_RX1
PE0_RX0
PE0_RX15*
PE0_RX14*
PE0_RX13*
PE0_RX12*
PE0_RX11*
PE0_RX10*
PE0_RX9*
PE0_RX8*
PE0_RX7*
PE0_RX6*
PE0_RX5*
PE0_RX4*
PE0_RX3*
PE0_RX2*
PE0_RX1*
PE0_RX0*
PE0_REFCLK
PE0_REFCLK*
PE_RESET*
AN20
AN18
AR18
AR17
AT16
AP16
AP15
AP14
AP13
AT13
AT12
AN12
AN10
AR10
AR9
AT8
AP20
AP19
AP18
AP17
AT17
AR16
AN16
AN14
AR14
AR13
AR12
AP12
AP11
AP10
AP9
AT9
AM19
AN17
AK17
AJ17
AK16
AM15
AJ15
AM13
AK13
AJ13
AK12
AN11
AJ11
AN9
AK9
AJ9
AN19
AM17
AL17
AH17
AM16
AN15
AH15
AM14
AL13
AH13
AM12
AM11
AH11
AM9
AL9
AH9
AP7
AN8
AP1
PE_A_TXP15
PE_A_TXP14
PE_A_TXP13
PE_A_TXP12
PE_A_TXP11
PE_A_TXP10
PE_A_TXP9
PE_A_TXP8
PE_A_TXP7
PE_A_TXP6
PE_A_TXP5
PE_A_TXP4
PE_A_TXP3
PE_A_TXP2
PE_A_TXP1
PE_A_TXP0
PE_A_TXN15
PE_A_TXN14
PE_A_TXN13
PE_A_TXN12
PE_A_TXN11
PE_A_TXN10
PE_A_TXN9
PE_A_TXN8
PE_A_TXN7
PE_A_TXN6
PE_A_TXN5
PE_A_TXN4
PE_A_TXN3
PE_A_TXN2
PE_A_TXN1
PE_A_TXN0
PE_A_RXP15
PE_A_RXP14
PE_A_RXP13
PE_A_RXP12
PE_A_RXP11
PE_A_RXP10
PE_A_RXP9
PE_A_RXP8
PE_A_RXP7
PE_A_RXP6
PE_A_RXP5
PE_A_RXP4
PE_A_RXP3
PE_A_RXP2
PE_A_RXP1
PE_A_RXP0
PE_A_RXN15
PE_A_RXN14
PE_A_RXN13
PE_A_RXN12
PE_A_RXN11
PE_A_RXN10
PE_A_RXN9
PE_A_RXN8
PE_A_RXN7
PE_A_RXN6
PE_A_RXN5
PE_A_RXN4
PE_A_RXN3
PE_A_RXN2
PE_A_RXN1
PE_A_RXN0
5
PE_A_TXP[0..15] 14
PE_A_TXN[0..15] 14
PE_A_RXP[0..15] 14
PE_A_RXN[0..15] 14
PE_A_CLK 14
PE_A_CLK# 14
PE_RESET# 14
R185
D D
1
R185
39.2R1%0402
39.2R1%0402
2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
nVIDIA C19 - PCI-Express 0A
nVIDIA C19 - PCI-Express 0A
nVIDIA C19 - PCI-Express 0A
734Monday, January 16, 2006
734Monday, January 16, 2006
734Monday, January 16, 2006
5
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg8.png)
1
U12D
U12D
MBA_A0
A A
DQM_B[0..7]12
DQS_B[0..7]12
B B
DQS_B#[0..7]12
MBA_B[0..2]12,13
CSB_A#[0..1]12,13
RASB_A#12,13
C C
CASB_A#12,13
WEB_A#12,13
CKEB_A[0..1]12,13
ODTB_A[0..1]12,13
MBA_A1
MBA_A2
MBA_A3
MBA_A4
MBA_A5
MBA_A6
MBA_A7
MBA_A8
MBA_A9
MBA_A10
MBA_A11
MBA_A12
MBA_A13
MBA_A14
DQM_B0
DQM_B1
DQM_B2
DQM_B3
DQM_B4
DQM_B5
DQM_B6
DQM_B7
DQS_B0
DQS_B1
DQS_B2
DQS_B3
DQS_B4
DQS_B5
DQS_B6
DQS_B7
DQS_B#0
DQS_B#1
DQS_B#2
DQS_B#3
DQS_B#4
DQS_B#5
DQS_B#6
DQS_B#7
MBA_B0
MBA_B1
MBA_B2
CSB_A#0
CSB_A#1
MCLK6
MCLK612
MCLK7
MCLK712
MCLK8
MCLK812
MCLK#6
MCLK#612
MCLK#7
MCLK#712
MCLK#8
MCLK#812
RASB_A#
CASB_A#
WEB_A#
CKEB_A0
CKEB_A1
ODTB_A0
ODTB_A1
N29
A34
B34
D33
E33
E31
E32
F30
F31
E28
M27
F29
E29
U30
D29
H13
F17
H21
F25
W29
AC31
AG30
AM32
K12
H17
K20
H25
V27
AC29
AG29
AL30
G17
G25
W28
AC30
AF28
AM31
N33
N28
R30
U31
AF30
K16
AG31
R32
R28
R29
H27
G27
T32
U28
J13
J21
J27
L29
J17
L28
MA1A_0
MA1A_1
MA1A_2
MA1A_3
MA1A_4
MA1A_5
MA1A_6
MA1A_7
MA1A_8
MA1A_9
MA1A_10
MA1A_11
MA1A_12
MA1A_13
MA1A_14
MDQM1_0
MDQM1_1
MDQM1_2
MDQM1_3
MDQM1_4
MDQM1_5
MDQM1_6
MDQM1_7
MDQS1_0
MDQS1_1
MDQS1_2
MDQS1_3
MDQS1_4
MDQS1_5
MDQS1_6
MDQS1_7
MDQS1_0*
MDQS1_1*
MDQS1_2*
MDQS1_3*
MDQS1_4*
MDQS1_5*
MDQS1_6*
MDQS1_7*
MBA1A_0
MBA1A_1
MBA1A_2
MCS1A_0*
MCS1A_1*
MCLK1A_0
MCLK1A_1
MCLK1A_2
MCLK1A_0*
MCLK1A_1*
MCLK1A_2*
MRAS_1A*
MCAS_1A*
MWE_1A*
MCKE1A_0
MCKE1A_1
MODT1A_0
MODT1A_1
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
2
C19
C19
4 OF 8
4 OF 8
MEM I/F
MEM I/F
CHANNEL B ( BANK 0 )
CHANNEL B ( BANK 0 )
MDQ1_0
MDQ1_1
MDQ1_2
MDQ1_3
MDQ1_4
MDQ1_5
MDQ1_6
MDQ1_7
MDQ1_8
MDQ1_9
MDQ1_10
MDQ1_11
MDQ1_12
MDQ1_13
MDQ1_14
MDQ1_15
MDQ1_16
MDQ1_17
MDQ1_18
MDQ1_19
MDQ1_20
MDQ1_21
MDQ1_22
MDQ1_23
MDQ1_24
MDQ1_25
MDQ1_26
MDQ1_27
MDQ1_28
MDQ1_29
MDQ1_30
MDQ1_31
MDQ1_32
MDQ1_33
MDQ1_34
MDQ1_35
MDQ1_36
MDQ1_37
MDQ1_38
MDQ1_39
MDQ1_40
MDQ1_41
MDQ1_42
MDQ1_43
MDQ1_44
MDQ1_45
MDQ1_46
MDQ1_47
MDQ1_48
MDQ1_49
MDQ1_50
MDQ1_51
MDQ1_52
MDQ1_53
MDQ1_54
MDQ1_55
MDQ1_56
MDQ1_57
MDQ1_58
MDQ1_59
MDQ1_60
MDQ1_61
MDQ1_62
MDQ1_63
F13
G13
F15
G15
J11
E12
D13
E15
K14
E16
H19
J19
H15
J15
D18
G19
F21
G21
F23
G23
K18
E20
D21
E23
K22
E24
J25
E27
H23
J23
D25
K24
W32
W30
AA30
AA29
T27
W31
Y32
AA31
Y27
AC32
AD32
AE31
AA28
AA33
AC28
AB27
AE33
AD27
AJ32
AJ31
AE29
AE28
AG28
AJ30
AL32
AK30
AK29
AN30
AK32
AK31
AJ29
AL29
DATA_B0
DATA_B1
DATA_B2
DATA_B3
DATA_B4
DATA_B5
DATA_B6
DATA_B7
DATA_B8
DATA_B9
DATA_B10
DATA_B11
DATA_B12
DATA_B13
DATA_B14
DATA_B15
DATA_B16
DATA_B17
DATA_B18
DATA_B19
DATA_B20
DATA_B21
DATA_B22
DATA_B23
DATA_B24
DATA_B25
DATA_B26
DATA_B27
DATA_B28
DATA_B29
DATA_B30
DATA_B31
DATA_B32
DATA_B33
DATA_B34
DATA_B35
DATA_B36
DATA_B37
DATA_B38
DATA_B39
DATA_B40
DATA_B41
DATA_B42
DATA_B43
DATA_B44
DATA_B45
DATA_B46
DATA_B47
DATA_B48
DATA_B49
DATA_B50
DATA_B51
DATA_B52
DATA_B53
DATA_B54
DATA_B55
DATA_B56
DATA_B57
DATA_B58
DATA_B59
DATA_B60
DATA_B61
DATA_B62
DATA_B63
3
DATA_B[0..63] 12MBA_A[0..14]12,13
VCC_DDR
MAA_A0
MAA_A[0..14]11,13
MAA_B[0..2]11,13
RASA_A#11,13
CASA_A#11,13
WEA_A#11,13
CKEA_A[0..1]11,13
ODTA_A[0..1]11,13
CSA_A#[0..1]11,13
MCLK#011
MCLK#111
MCLK#211
MCLK011
MCLK111
MCLK211
R162 39R1%R162 39R1%
R161 39R1%R161 39R1%
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
MAA_B0
MAA_B1
MAA_B2
RASA_A#
CASA_A#
WEA_A#
CKEA_A0
CKEA_A1
ODTA_A0
ODTA_A1
CSA_A#0
CSA_A#1
MCLK#0
MCLK#1
MCLK#2
MCLK0
MCLK1
MCLK2
T34
A33
B33
B32
A32
D32
C32
D31
C31
B30
T36
C30
E30
Y34
B29
U32
T35
C29
U35
V33
V34
B28
C28
Y33
Y36
V35
Y35
P33
A16
AM33
P34
B16
AL34
E10
E11
4
U12F
U12F
MA0A_0
MA0A_1
MA0A_2
MA0A_3
MA0A_4
MA0A_5
MA0A_6
MA0A_7
MA0A_8
MA0A_9
MA0A_10
MA0A_11
MA0A_12
MA0A_13
MA0A_14
MBA0A_0
MBA0A_1
MBA0A_2
MRAS_0A*
MCAS_0A*
MWE_0A*
MCKE0A_0
MCKE0A_1
MODT0A_0
MODT0A_1
MCS0A_0*
MCS0A_1*
MCLK0A_0*
MCLK0A_1*
MCLK0A_2*
MCLK0A_0
MCLK0A_1
MCLK0A_2
MEM_DRV0_1P8V
MEM_DRV1_GND
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
C19
C19
6 OF 8
6 OF 8
MEM I/F
MEM I/F
MCKE1B_0
MCKE1B_1
MODT1B_0
MODT1B_1
CHANNEL A ( BANK 0 )
CHANNEL A ( BANK 0 )
CHANNEL B ( BANK 1 )
CHANNEL B ( BANK 1 )
MCLK1B_0*
MCLK1B_1*
MCLK1B_2*
MEM_TERM_GND
MA1B_0
MA1B_1
MA1B_2
MA1B_3
MA1B_4
MA1B_5
MA1B_6
MA1B_7
MA1B_8
MA1B_9
MA1B_10
MA1B_11
MA1B_12
MA1B_13
MA1B_14
MBA1B_0
MBA1B_1
MBA1B_2
MRAS_1B*
MCAS_1B*
MWE_1B*
MCS1B_0*
MCS1B_1*
MCLK1B_0
MCLK1B_1
MCLK1B_2
F35
G31
E36
G32
F32
E34
F34
D35
D36
D34
H32
C36
C35
H29
B35
G34
F33
C34
H31
G29
H30
K26
F27
P27
U33
R31
U29
N30
F19
AH32
N31
E19
AG32
F11
CKEB_B0
CKEB_B1
ODTB_B0
ODTB_B1
CSB_B#0
CSB_B#1
MCLK#9
MCLK#10
MCLK#11
MCLK9
MCLK10
MCLK11
5
CKEB_B[0..1] 12,13
ODTB_B[0..1] 12,13
CSB_B#[0..1] 12,13
MCLK#9 12
MCLK#10 12
MCLK#11 12
MCLK9 12
MCLK10 12
MCLK11 12
R155
R155
150R1%0402
150R1%0402
Solder side footprint C0603MS_BOT
C59、C60、C61、C62、C63、C64、C65、C66、C67、C68
VCC_DDR
C516
C516
C520
D D
1
C520
C0.1U25Y
C0.1U25Y
C0.1U25Y
C0.1U25Y
2
Place underneath C19
C517
C513
C513
C0.1U25Y
C0.1U25Y
C519
C519
C0.1U25Y
C0.1U25Y
C510
C510
C0.1U25Y
C0.1U25Y
C517
C0.1U25Y
C0.1U25Y
C511
C511
C0.1U25Y
C0.1U25Y
C524
C524
C0.1U25Y
C0.1U25Y
C508
C508
C0.1U25Y
C0.1U25Y
C521
C521
C10U6.3X50805
C10U6.3X50805
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
nVIDIA C19 - Memory 1 & 2 0A
nVIDIA C19 - Memory 1 & 2 0A
nVIDIA C19 - Memory 1 & 2 0A
834Monday, January 16, 2006
834Monday, January 16, 2006
834Monday, January 16, 2006
5
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bg9.png)
1
A A
DQM_A[0..7]11
B B
C C
PCIRST_STR#15
DQS_A[0..7]11
DQS_A#[0..7]11
CSA_B#[0..1]11,13
CKEA_B[0..1]11,13
ODTA_B[0..1]11,13
R209
R209
10KR0402
10KR0402
MCLK311
MCLK411
MCLK511
MCLK#311
MCLK#411
MCLK#511
PCIRST_STREN#
DQM_A0
DQM_A1
DQM_A2
DQM_A3
DQM_A4
DQM_A5
DQM_A6
DQM_A7
DQS_A0
DQS_A1
DQS_A2
DQS_A3
DQS_A4
DQS_A5
DQS_A6
DQS_A7
DQS_A#0
DQS_A#1
DQS_A#2
DQS_A#3
DQS_A#4
DQS_A#5
DQS_A#6
DQS_A#7
CSA_B#0
CSA_B#1
MCLK3
MCLK4
MCLK5
MCLK#3
MCLK#4
MCLK#5
CKEA_B0
CKEA_B1
ODTA_B0
ODTA_B1
2
L31
M34
M35
M33
L34
K33
L32
K34
K32
K35
M32
J33
J34
P35
J35
D12
E17
E21
E25
AC34
AG34
AM36
AT33
B12
C16
C21
C25
AD34
AH34
AN35
AT32
C12
D16
B21
B25
AD33
AH33
AN36
AR33
N32
L30
H36
U34
AA32
R34
B17
AM34
T33
C17
AM35
M36
N34
N35
A28
D28
W34
AA35
AN31
R208
R208
12KR0402
12KR0402
U12E
U12E
MA0B_0
MA0B_1
MA0B_2
MA0B_3
MA0B_4
MA0B_5
MA0B_6
MA0B_7
MA0B_8
MEM I/F
MEM I/F
MA0B_9
MA0B_10
MA0B_11
MA0B_12
MA0B_13
MA0B_14
MDQM0_0
MDQM0_1
MDQM0_2
MDQM0_3
MDQM0_4
MDQM0_5
MDQM0_6
MDQM0_7
MDQS0_0
MDQS0_1
MDQS0_2
MDQS0_3
MDQS0_4
MDQS0_5
MDQS0_6
MDQS0_7
MDQS0_0*
MDQS0_1*
MDQS0_2*
MDQS0_3*
MDQS0_4*
MDQS0_5*
MDQS0_6*
MDQS0_7*
MBA0B_0
MBA0B_1
MBA0B_2
MCS0B_0*
MCS0B_1*
MCLK0B_0
MCLK0B_1
MCLK0B_2
MCLK0B_0*
MCLK0B_1*
MCLK0B_2*
MRAS_0B*
MCAS_0B*
MWE_0B*
MCKE0B_0
MCKE0B_1
MODT0B_0
MODT0B_1
STR_EN*
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
C19
C19
5 OF 8
5 OF 8
CHANNEL A ( BANK 1 )
CHANNEL A ( BANK 1 )
MEM_VREF
MEM_VREF2
MDQ0_0
MDQ0_1
MDQ0_2
MDQ0_3
MDQ0_4
MDQ0_5
MDQ0_6
MDQ0_7
MDQ0_8
MDQ0_9
MDQ0_10
MDQ0_11
MDQ0_12
MDQ0_13
MDQ0_14
MDQ0_15
MDQ0_16
MDQ0_17
MDQ0_18
MDQ0_19
MDQ0_20
MDQ0_21
MDQ0_22
MDQ0_23
MDQ0_24
MDQ0_25
MDQ0_26
MDQ0_27
MDQ0_28
MDQ0_29
MDQ0_30
MDQ0_31
MDQ0_32
MDQ0_33
MDQ0_34
MDQ0_35
MDQ0_36
MDQ0_37
MDQ0_38
MDQ0_39
MDQ0_40
MDQ0_41
MDQ0_42
MDQ0_43
MDQ0_44
MDQ0_45
MDQ0_46
MDQ0_47
MDQ0_48
MDQ0_49
MDQ0_50
MDQ0_51
MDQ0_52
MDQ0_53
MDQ0_54
MDQ0_55
MDQ0_56
MDQ0_57
MDQ0_58
MDQ0_59
MDQ0_60
MDQ0_61
MDQ0_62
MDQ0_63
D10
C11
B13
C13
B10
C10
A12
E13
D14
C15
C18
C19
B14
C14
B18
D17
B20
A20
D22
C23
D20
C20
B22
C22
B24
A24
C26
C27
D24
C24
B26
D26
AB35
AB33
AE32
AE35
AA34
AB34
AD35
AD36
AF34
AF33
AJ33
AJ35
AE34
AF35
AH35
AH36
AK34
AL33
AN34
AR35
AJ34
AK35
AP36
AP35
AT34
AP33
AN32
AP31
AP34
AR34
AR32
AP32
H11
G11
3
DATA_A0
DATA_A1
DATA_A2
DATA_A3
DATA_A4
DATA_A5
DATA_A6
DATA_A7
DATA_A8
DATA_A9
DATA_A10
DATA_A11
DATA_A12
DATA_A13
DATA_A14
DATA_A15
DATA_A16
DATA_A17
DATA_A18
DATA_A19
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A24
DATA_A25
DATA_A26
DATA_A27
DATA_A28
DATA_A29
DATA_A30
DATA_A31
DATA_A32
DATA_A33
DATA_A34
DATA_A35
DATA_A36
DATA_A37
DATA_A38
DATA_A39
DATA_A40
DATA_A41
DATA_A42
DATA_A43
DATA_A44
DATA_A45
DATA_A46
DATA_A47
DATA_A48
DATA_A49
DATA_A50
DATA_A51
DATA_A52
DATA_A53
DATA_A54
DATA_A55
DATA_A56
DATA_A57
DATA_A58
DATA_A59
DATA_A60
DATA_A61
DATA_A62
DATA_A63
DATA_A[0..63] 11
PLACE CAP CLOSE TO C19
C148
C148
C0.1U16Y0402
C0.1U16Y0402
VCC_DDR
R159
R159
100R1%0402
100R1%0402
R156
R156
100R1%0402
100R1%0402
4
5
D D
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
1
2
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
nVIDIA C19 - Memory 3 0A
nVIDIA C19 - Memory 3 0A
nVIDIA C19 - Memory 3 0A
934Monday, January 16, 2006
934Monday, January 16, 2006
934Monday, January 16, 2006
5
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bga.png)
1
A13
GND1
A17
GND2
A2
GND3
A21
GND4
A25
GND5
A29
GND6
A35
GND7
AA1
GND8
AA10
GND9
AA16
GND10
AA17
GND11
AA18
GND12
AA19
A A
B B
C C
D D
GND13
AA20
GND14
AA21
GND15
AA27
GND16
AA36
GND17
AB28
GND18
AB30
GND19
AB32
GND20
AB5
GND21
AB7
GND22
AB9
GND23
AC10
GND24
AC27
GND25
AC33
GND26
AC4
GND27
AD28
GND28
AD30
GND29
AD9
GND30
AE1
GND31
AN28
GND32
AE27
GND33
AE36
GND34
D6
GND35
AE30
GND36
AF32
GND37
AF7
GND38
AK20
GND39
AG13
GND40
AG15
GND41
AG17
GND42
AG11
GND43
AG21
GND44
AG23
GND45
AG12
GND46
AG33
GND47
AH10
GND48
AH12
GND49
AH14
GND50
AH16
GND51
AH18
GND52
AH20
GND53
AH22
GND54
AH24
GND55
AN5
GND56
AH28
GND57
AH30
GND58
D30
GND59
AJ36
GND60
AG14
GND61
AK10
GND62
AK14
GND63
AK18
GND64
AK22
GND65
AK33
GND66
AK6
GND67
AM10
GND68
AG16
GND69
AM18
GND70
AL31
GND71
AM22
GND72
AM26
GND73
AM30
GND74
AG18
GND75
AN13
GND76
AG20
GND77
AG22
GND78
AG24
GND79
AH21
GND80
AN33
GND81
AK7
GND82
AP3
GND83
AR1
GND84
AR29
GND85
AR36
GND86
AL11
GND87
AL15
GND88
AT2
GND89
AH7
GND90
AJ25
GND91
AT35
GND92
AK11
GND93
AL19
GND94
B1
GND95
B36
GND96
B5
GND97
C33
GND98
D11
GND99
D15
GND100
D19
GND101
D23
GND102
D27
GND103
AM3
GND104
E14
GND105
E18
GND106
E2
GND107
E22
GND108
E26
GND109
AK4
GND110
E35
GND111
U12H NVIDIA-C19-C1-RH
U12H NVIDIA-C19-C1-RH
1
C19
C19
8 OF 8
8 OF 8
GND
GND
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130
GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160
GND161
GND162
GND163
GND164
GND165
GND166
GND167
GND168
GND169
GND170
GND171
GND172
GND173
GND174
GND175
GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188
GND189
GND190
GND191
GND192
GND193
GND194
GND195
GND196
GND197
GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207
GND208
GND209
GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219
GND220
GND221
GND222
G10
G12
G14
G16
G18
G20
G22
G24
G26
G28
G30
G33
G4
J1
J12
J14
J16
J18
J20
J22
J24
J26
J36
K13
K15
K17
K19
K21
K23
K25
Y9
K30
K5
K7
C8
AK15
L33
L4
M28
M30
M9
N1
N10
N27
N36
P28
P30
P32
P5
P7
P9
R10
R27
R33
R4
T16
T17
T18
T19
T20
T21
T28
T30
T9
U1
U10
U16
U17
U18
U19
U20
U21
U27
U36
V16
V17
V18
V19
V20
V21
V28
V30
V32
V5
V7
V9
W10
W16
W17
W18
W19
W20
W21
W27
W33
W4
Y16
Y17
Y18
Y19
Y20
Y21
Y28
Y30
AK26
G7
AD7
Y7
M7
T7
AF4
2
VCC_DDR
12
+
+
EC30
EC30
CD1800U6.3EL20-1
CD1800U6.3EL20-1
2
VCC_DDR
V_FSB_VTT
VCC3
M22
R23
H33
H34
H35
R24
M23
N14
N15
N16
N17
N18
N19
N20
N21
M24
P14
P15
P16
P17
P18
P19
P20
P21
M25
R14
N22
T14
N23
R25
T23
N24
N25
M14
M15
M16
M17
M18
M19
M20
M21
P22
P23
P24
P25
T25
AA13
AD13
AB13
V13
AC13
U12
U14
U13
AF10
V12
W12
AF9
Y12
AH5
AG5
AG6
AG7
AG8
AG9
AH2
AH3
W13
W14
Y13
Y14
AA12
AB12
AC12
AD12
AE12
V14
AH1
AH4
AJ2
AJ1
AN29
AM29
AM28
L27
K27
K28
J28
J29
J30
J31
T24
J32
U12G
U12G
VDD_MEM1
VDD_MEM2
VDD_MEM3
VDD_MEM4
VDD_MEM5
VDD_MEM6
VDD_MEM7
VDD_MEM8
VDD_MEM9
VDD_MEM10
VDD_MEM11
VDD_MEM12
VDD_MEM13
VDD_MEM14
VDD_MEM15
VDD_MEM16
VDD_MEM17
VDD_MEM18
VDD_MEM19
VDD_MEM20
VDD_MEM21
VDD_MEM22
VDD_MEM23
VDD_MEM24
VDD_MEM25
VDD_MEM26
VDD_MEM27
VDD_MEM28
VDD_MEM29
VDD_MEM30
VDD_MEM31
VDD_MEM32
VDD_MEM33
VDD_MEM34
VDD_MEM35
VDD_MEM36
VDD_MEM37
VDD_MEM38
VDD_MEM39
VDD_MEM40
VDD_MEM41
VDD_MEM42
VDD_MEM43
VDD_MEM44
VDD_MEM45
VDD_MEM46
VDD_MEM47
VDD_MEM48
VDD_MEM49
VDD_MEM50
VDD_MEM51
VDD_MEM52
VDD_MEM53
VDD_MEM54
VDD_MEM55
VTT_CPU1
VTT_CPU2
VTT_CPU3
VTT_CPU4
VTT_CPU5
VTT_CPU6
VTT_CPU7
VTT_CPU8
VTT_CPU9
VTT_CPU10
VTT_CPU11
VTT_CPU12
VTT_CPU13
VTT_CPU14
VTT_CPU15
VTT_CPU16
VTT_CPU17
VTT_CPU18
VTT_CPU19
VTT_CPU20
VTT_CPU21
VTT_CPU22
VTT_CPU23
VTT_CPU24
VTT_CPU25
VTT_CPU26
VTT_CPU27
VTT_CPU28
VTT_CPU29
VTT_CPU30
VTT_CPU31
VTT_CPU32
VTT_CPU33
VTT_CPU34
VTT_CPU35
VDD_3P3_1
VDD_3P3_2
VDD_3P3_3
NVIDIA-C19-C1-RH
NVIDIA-C19-C1-RH
C19
C19
7 OF 8
7 OF 8
POWER
POWER
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD_LDT1
VDD_LDT2
VDD_LDT3
VDD_LDT4
VDD_PE1
VDD_PE2
VDD_PE3
VDD_PE4
VDD_PE5
VDDIO_PE1
VDDIO_PE2
VDDIO_PE3
VDDIO_PE4
VDDIO_PE5
VDDA1_1P2
VDDA2_1P2
VTT_MEM1
VTT_MEM2
VTT_MEM3
VTT_MEM4
VTT_MEM5
VTT_MEM6
VTT_MEM7
VTT_MEM8
VTT_MEM9
VTT_MEM10
VTT_MEM11
VTT_MEM12
VTT_MEM13
VTT_MEM14
VTT_MEM15
VTT_MEM16
VTT_MEM17
VTT_MEM18
VTT_MEM19
VTT_MEM20
VTT_MEM21
VTT_MEM22
VTT_MEM23
3
VCC1_4
AA23
AA24
AB23
AB24
AD16
AD17
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AD20
AD21
AD22
AD23
AD24
AF27
AK27
AG27
AH27
AK28
AM27
AP28
AL27
AN27
AR28
AT28
AD18
AD19
AE16
V25
U23
U24
V23
V24
W24
Y24
AA25
AB25
AC25
AD25
W25
Y25
AJ27
AE23
AE24
AE25
AE17
AE18
U25
AE19
AE20
AE21
AE22
AD15
AC15
AE15
AC16
AE14
AE13
AB14
AC14
AA14
AD14
W23
Y23
K9
K10
K11
J9
J10
A9
B9
C9
D9
E9
M12
M13
N12
N13
P12
P13
R13
R12
T12
T13
F9
G9
H9
3
C19_VDD_PEX
C507
C507
C10U6.3X50805
C10U6.3X50805
C523
C523
C10U6.3X50805
C10U6.3X50805 C282 C0.1U16X0402C282 C0.1U16X0402
C526
C526
C0.01U16X
C0.01U16X
Underneath C19
C98 footprint C0603MS_BOT
VTT_DDR
12
EC16
EC16
+
+
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
Place underneath C19
C506
C506
C0.1U16X
C0.1U16X
Solder side footprint C0603MS_BOT
C73、C74、C75、C76、C77、C78、C79、C80
C81、C82、C83、C84、C85、C86、C87
C518
C518
C0.1U16X
C0.1U16X
Underneath C19
CP19
CP19
1 2
X_COPPER
X_COPPER
C522
C522
C1U16Y
C1U16Y
4
C509
C509
X_C0.1U16X
X_C0.1U16X
CP18 X_COPPERCP18 X_COPPER
1 2
L20 X_40L3_25_0805L20 X_40L3_25_0805
VCC1_4
HS5
HS5
HeatSink
HeatSink
4
C505
C505
X_C0.1U16X
X_C0.1U16X
VCC1_4
5
VCC1_4 VCC1_4VTT_DDR
C528
C528
C0.1U16X
C0.1U16X
C529
C529
C0.1U16X
C0.1U16X
C531
C531
C0.1U16X
C0.1U16X
VCC1_4
VCC3
VTT_DDR
C138
C138
X_C0.1U16X0402
X_C0.1U16X0402
C286 C1U16YC286 C1U16Y
C283 C0.1U16X0402C283 C0.1U16X0402
C527
C527
C0.1U16X
C0.1U16X
C525
C525
C0.1U16X
C0.1U16X
C530
C530
C10U6.3X50805
C10U6.3X50805
C258 C10U6.3X50805C258 C10U6.3X50805
C261 C0.1U16X0402C261 C0.1U16X0402
C259 C0.1U16X0402C259 C0.1U16X0402
C153
C153
C0.1U16X0402
C0.1U16X0402
VCC1_4
EC35
EC35
.CD1000U6.3EL11.5
.CD1000U6.3EL11.5
1 2
+
+
PLACE CLOSE TO C19
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
MS-7274
MS-7274
MS-7274
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet
MICRO-START INT'L CO.,LTD.
nVIDIA C19 - Power & GND 0A
nVIDIA C19 - Power & GND 0A
nVIDIA C19 - Power & GND 0A
10 34Monday, January 16, 2006
10 34Monday, January 16, 2006
10 34Monday, January 16, 2006
5
of
![](/html/bc/bce7/bce7493bd7e93a59ad862d1d508635255846083e15e9154f1db4a6cf58b9582a/bgb.png)
1
2
3
4
5
A A
DIMM1
DATA_A[0..63]9
B B
C C
DATA_A0
DATA_A1
DATA_A2
DATA_A3
DATA_A4
DATA_A5
DATA_A6
DATA_A7
DATA_A8
DATA_A9
DATA_A10
DATA_A11
DATA_A12
DATA_A13
DATA_A14
DATA_A15
DATA_A16
DATA_A17
DATA_A18
DATA_A19
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A24
DATA_A25
DATA_A26
DATA_A27
DATA_A28
DATA_A29
DATA_A30
DATA_A31
DATA_A32
DATA_A33
DATA_A34
DATA_A35
DATA_A36
DATA_A37
DATA_A38
DATA_A39
DATA_A40
DATA_A41
DATA_A42
DATA_A43
DATA_A44
DATA_A45
DATA_A46
DATA_A47
DATA_A48
DATA_A49
DATA_A50
DATA_A51
DATA_A52
DATA_A53
DATA_A54
DATA_A55
DATA_A56
DATA_A57
DATA_A58
DATA_A59
DATA_A60
DATA_A61
DATA_A62
DATA_A63
DIMM1
55
102
19
68
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS#5
VSS#8
VSS#11
VSS#14
VSS#17
VSS#20
VSS#23
VSS#26
VSS#29
VSS#32
VSS#35
VSS#38
VSS#41
VSS#44
VSS#47
VSS#50
VSS#65
VSS#66
VSS#79
VSS#82
VSS#85
VSS#88
VSS#91
VSS#94
VSS#97
VSS#100
100
RC118RC0
VSS#103
103
106
NC#19
NC/TEST
VSS#106
VSS#109
109
112
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS#112
VSS#115
VSS#118
VSS#121
115
118
121
3
4
9
10
122
123
128
129
12
13
21
22
131
132
140
141
24
25
30
31
143
144
149
150
33
34
39
40
152
153
158
159
80
81
86
87
199
200
205
206
89
90
95
96
208
209
214
215
98
99
107
108
217
218
226
227
110
111
116
117
229
230
235
236
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
VSS#124
124
127
75
VDD3#75
VSS#127
VSS#130
130
191
VSS#133
133
136
194
VDD6
VSS#136
VSS#139
139
181
175
VDD7
VSS#142
142
145
170
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#145
VSS#148
VSS#151
148
151
VSS#154
154
VSS#157
157
VCC3VCC_DDR VCC3
DIMM2
197
VSS#160
160
69
172
VDDQ5
VDDQ4#69
VSS#163
VSS#166
163
166
187
184
VDDQ6
VSS#169
169
198
178
189
VDDQ7
VDDQ7#178
VSS#198
VSS#201
201
204
67
VDDQ8
VDDQ9
VSS#204
VSS#207
207
210
238
VDDSPD
VSS#210
VSS#213
213
216
CB042CB143CB248CB349CB4
VSS#216
VSS#219
VSS#222
219
222
225
161
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2#(DU)
VSS#225
VSS#228
VSS#231
228
231
162
CB5
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
DQS8#
A10_AP
A16/BA2
CK0(DU)
CK2(DU)
VSS#234
234
167
CB6
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
BA1
BA0
WE#
CAS#
RAS#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
SCL
SDA
VREF
SA0
SA1
SA2
VSS#237
237
168
CB7
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
X3
X3
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
57
A11
176
A12
196
A13
174
A14
173
A15
54
190
71
73
74
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
119
X1
X1
1
X2
X2
239
240
101
DDRII-240_green
DDRII-240_green
ADDRESS: 000
0xA0
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
MAA_B2
MAA_B1
MAA_B0
WEA_A#
CASA_A#
RASA_A#
DQM_A0
DQM_A1
DQM_A2
DQM_A3
DQM_A4
DQM_A5
DQM_A6
DQM_A7
ODTA_A0
ODTA_A1
CKEA_A0
CKEA_A1
CSA_A#0
CSA_A#1
MCLK0
MCLK#0
MCLK1
MCLK#1
MCLK2
MCLK#2
SMBCLK_DDR
SMBDATA_DDR
DIMM_VREF
DQS_A0 9
DQS_A#0 9
DQS_A1 9
DQS_A#1 9
DQS_A2 9
DQS_A#2 9
DQS_A3 9
DQS_A#3 9
DQS_A4 9
DQS_A#4 9
DQS_A5 9
DQS_A#5 9
DQS_A6 9
DQS_A#6 9
DQS_A7 9
DQS_A#7 9
MAA_A[0..14] 8,13
MAA_B[0..2] 8,13
WEA_A# 8,13
CASA_A# 8,13
RASA_A# 8,13
DQM_A[0..7] 9
ODTA_A[0..1] 8,13
CKEA_A[0..1] 8,13
CSA_A#[0..1] 8,13
MCLK0 8
MCLK#0 8
MCLK1 8
MCLK#1 8
MCLK2 8
MCLK#2 8
C76
C76
C0.1U16Y0402
C0.1U16Y0402
PLACE CLOSE TO DIMM PIN PLACE CLOSE TO DIMM PIN
VCC3_SB
DATA_A0
DATA_A1
DATA_A2
DATA_A3
DATA_A4
DATA_A5
DATA_A6
DATA_A7
DATA_A8
DATA_A9
DATA_A10
DATA_A11
DATA_A12
DATA_A13
DATA_A14
DATA_A15
DATA_A16
DATA_A17
DATA_A18
DATA_A19
DATA_A20
DATA_A21
DATA_A22
DATA_A23
DATA_A24
DATA_A25
DATA_A26
DATA_A27
DATA_A28
DATA_A29
DATA_A30
DATA_A31
DATA_A32
DATA_A33
DATA_A34
DATA_A35
DATA_A36
DATA_A37
DATA_A38
DATA_A39
DATA_A40
DATA_A41
DATA_A42
DATA_A43
DATA_A44
DATA_A45
DATA_A46
DATA_A47
DATA_A48
DATA_A49
DATA_A50
DATA_A51
DATA_A52
DATA_A53
DATA_A54
DATA_A55
DATA_A56
DATA_A57
DATA_A58
DATA_A59
DATA_A60
DATA_A61
DATA_A62
DATA_A63
DIMM2
55
19
3
RC118RC0
DQ0
4
DQ1
9
DQ2
10
DQ3
122
DQ4
123
DQ5
128
DQ6
129
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
131
DQ12
132
DQ13
140
DQ14
141
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
143
DQ20
144
DQ21
149
DQ22
150
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
152
DQ28
153
DQ29
158
DQ30
159
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
199
DQ36
200
DQ37
205
DQ38
206
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
208
DQ44
209
DQ45
214
DQ46
215
DQ47
98
DQ48
99
DQ49
107
DQ50
108
DQ51
217
DQ52
218
DQ53
226
DQ54
227
DQ55
110
DQ56
111
DQ57
116
DQ58
117
DQ59
229
DQ60
230
DQ61
235
DQ62
236
DQ63
2
VSS
5
VSS#5
8
VSS#8
11
VSS#11
14
VSS#14
17
VSS#17
20
VSS#20
23
VSS#23
26
VSS#26
29
VSS#29
32
VSS#32
35
VSS#35
38
VSS#38
41
VSS#41
44
VSS#44
47
VSS#47
50
VSS#50
65
VSS#65
66
VSS#66
79
VSS#79
82
VSS#82
85
VSS#85
88
VSS#88
91
VSS#91
94
VSS#94
97
VSS#97
VSS#100
VSS#103
100
103
106
DDR2 DIMM1
102
NC#19
NC/TEST
VSS#106
VSS#109
109
68
NC
VSS#112
112
VCC_DDR
VDD051VDD156VDD262VDD372VDD478VDD5
VSS#115
VSS#118
VSS#121
VSS#124
VSS#127
115
118
121
124
127
DDR2 DIMM2
170
75
191
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VDD3#75
VSS#130
VSS#133
VSS#136
VSS#139
VSS#142
VSS#145
VSS#148
130
133
136
139
142
145
148
197
VDDQ153VDDQ259VDDQ364VDDQ4
VSS#151
VSS#154
VSS#157
151
154
157
160
69
172
VDDQ4#69
VSS#160
VSS#163
163
166
187
VDDQ5
VDDQ6
VSS#166
VSS#169
169
178
184
VDDQ7
VSS#198
198
201
189
67
VDDQ8
VDDQ9
VDDQ7#178
VSS#201
VSS#204
VSS#207
204
207
210
238
VDDSPD
VSS#210
VSS#213
213
CB042CB143CB248CB349CB4
VSS#216
VSS#219
VSS#222
216
219
222
VSS#225
225
228
161
162
167
CB5
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A16/BA2
CAS#
RAS#
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
ODT0
ODT1
CKE0
CKE1
CS0#
CS1#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
VREF
VSS#228
VSS#231
VSS#234
231
234
237
168
CB6
CB7
7
6
16
15
28
27
37
36
84
83
93
92
105
104
114
113
46
45
X3
X3
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
57
A11
176
A12
196
A13
174
A14
173
A15
54
190
BA1
71
BA0
73
WE#
74
192
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
77
52
171
193
76
185
186
137
138
220
221
120
SCL
119
SDA
X1
X1
1
X2
X2
239
SA0
240
SA1
101
SA2
VSS#237
DDRII-240_orange
DDRII-240_orange
ADDRESS: 010
0xA4
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
MAA_B2
MAA_B1
MAA_B0
WEA_A#
CASA_A#
RASA_A#
DQM_A0
DQM_A1
DQM_A2
DQM_A3
DQM_A4
DQM_A5
DQM_A6
DQM_A7
ODTA_B0
ODTA_B1
CKEA_B0
CKEA_B1
CSA_B#0
CSA_B#1
MCLK3
MCLK#3
MCLK4
MCLK#4
MCLK5
MCLK#5
SMBCLK_DDR
SMBDATA_DDR
DIMM_VREF
VCC3
ODTA_B[0..1] 9,13
CKEA_B[0..1] 9,13
CSA_B#[0..1] 9,13
MCLK3 9
MCLK#3 9
MCLK4 9
MCLK#4 9
MCLK5 9
MCLK#5 9
R232 10R0402R232 10R0402
R231 10R0402R231 10R0402
C78
C78
C0.1U16Y0402
C0.1U16Y0402
DIMM_VREF 12,29
SMBCLK_MEM 16
SMBDATA_MEM 16
2
SMBDATA_DDR
3
D13
D13
BAV99-7-F_SOT23-LF
BAV99-7-F_SOT23-LF
1
VCC3_SB
D D
2
SMBCLK_DDR
3
D14
D14
BAV99-7-F_SOT23-LF
BAV99-7-F_SOT23-LF
1
SMBDATA_DDR 12
SMBCLK_DDR 12
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A2
A2
A2
Date: Sheet
Date: Sheet of
1
2
3
4
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7274
MS-7274
MS-7274
DDR II DIMM 1 & 2
DDR II DIMM 1 & 2
DDR II DIMM 1 & 2
5
0A
0A
0A
of
11 34Monday, January 16, 2006
11 34Monday, January 16, 2006
11 34Monday, January 16, 2006