MSI MS-7259 Schematics
A
B
C
D
E
CHIPSET P4M800_CE + VT8237_Pro
TITLE
4 4
3 3
2 2
COVER SHEET
BLOCK DIAGRAM
PWR And CLOCK Map
PROCESSOR ( Intel LGA775)
NORTH BRIDGE P4M800_Pro
DIMMII 1&2
DIMM1&2 Terminations
VGA Connector
DVI VT1632
S&AV-VIDEO VIA VT1623
SOUTH BRIDGE (VT8237R Plus)
MS7 ACPI Controller
VRM 1.1 - Intersil 6566
Clock Generator ICS950952
IDE SATA Connectors , KB/MS
ATX & F_Panel
PCI Slot 1 & 2
AC97 VIA VT1617A
FWH, Fan control
USB Connectors
LAN VIA VT6103L(10/100)
1394 VIA VT6307/6308
Super I/O W83627EHG-H-RH & FAN
Manual Part
GPIO/MEMORY/PCI/HW STRPPING
CHANGE NOTE
SHEET
1
2
3
4,5,6
7,8,9,10
11
12
13
14
15
16,17,18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
MS-7259 / 6415
CPU:
Intel 2005 Main-Stream (TDP=130W)
Prescott LGA775
System Chipset:
North Bridge : VIA P4M800 Ver:Pro
South Bridge : VIA VT8237R Plus
On Board Chipset:
BIOS -- FWH FLASH 4Mb
AC97 AUDIO Codec -- VIA VT1617A
LPC Super I/O -- W83627EHG-H-RH
LAN - VIA VT6103L(10/100)
Clock Generator - ICS950952
1394--VIA VT6307/6308
Main Memory:
DDR II * 2 (Max 2GB)
Expansion Slots:
PCI 2.2 SLOT * 2
Intersil PWM:
Controller:
INTERSIL 6566 3PHASE
Version 0A
34
35
1 1
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
A
B
C
D
Date: Sheet
MICRO-START INT'L CO.,LTD.
COVER SHEET
COVER SHEET
COVER SHEET
MS-7259 0A
MS-7259 0A
MS-7259 0A
E
134Friday, December 09, 2005
134Friday, December 09, 2005
134Friday, December 09, 2005
of
of
of
VRM 10.1
Intersil 6566
3Phase
1
Block Diagram
Intel Prescott Processor-LGA775
FSB
performance
TDP=130W
Iccmax=125A
Icctdc=115A
TV-OUT
VIA VT1623MS-VEDIO &
DVI OUT
VIA VT1632A
Analog
Video Out
IDE Primary
A A
USB Port 0
USB Port 1
USB Port 2
FPD1
DVP1
RGB
UltraDMA 33/66/100
USB
P4M800_Pro
VCORE= +1.5VNB
VDIMM= +1.8VDIMM
VDDQ= +1.5VAGP
VLINK= +2.5V
VT8237_PLUS
VCC25= +2.5V
VCC33= +3.3V
V-Link/8bits/S533M
64bit DDR
PCI
MII
2 DDR II
DIMM
Modules
PCI
1394
CO-LAYOUT
VT 6307/6308
VIA
LAN
VIA
VT 6103L
RISER CARD
PCI Slot 2
PCI Slot 1
USB Port 3
USB Port 4
USB Port 5
LPC Bus
LPC SIO
Winbond
USB Port 6
W83627EHG-H-RH
USB Port 7
VIA VT1617A
AC'97 Link
SATA prot1 and
port2
KEYBOARD
MOUSE
1
LPC FLASH
ROM
Serial
X2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7259 0A
MS-7259 0A
MS-7259 0A
of
of
of
234Friday, December 09, 2005
234Friday, December 09, 2005
234Friday, December 09, 2005
8
7
6
5
4
3
2
1
CLOCK MAP
CPUCLKT0
LGA775
D D
CPUCLKT1
GCLK 66MHz
VIA
P4M800_Pro
GUICK14MHz
ICS950952
VCLK 66MHz
Clock
Generator
C C
APIC
USB48MHz
SB14MHz
SPCLK 33MHz
SXI 25MHz
DCLKA
VIA
VT8237R_PLUS
DDRII
32.768MHz
DIMM1/2
AC97XIN
24MHz
SIO_PCLK
B B
33MHz
AC97
VIA VT1617A
W83627EHF
LPC IO
1394_PCLK
24MHz
LAN_PCLK
25MHz
FWH_CLK
VT6307
1394
LAN 10/100
VIA VT 6103L
FWH
33MHz
A A
PCI CLK 1~2
33MHz
8
7
6
5
PCI Slot 1~2
4
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
3
Date: Sheet
MICRO-START INT'L CO.,LTD.
PWR And CLOCK Map
PWR And CLOCK Map
PWR And CLOCK Map
MS-7259 0A
MS-7259 0A
MS-7259 0A
2
334Friday, December 09, 2005
334Friday, December 09, 2005
334Friday, December 09, 2005
of
of
of
1
8
D D
C C
VTT_OUT_RIGHT
VTT_OUT_RIGHT
VTT_OUT_RIGHT
B B
A A
THERM#{17,30}
THERM# PROCHOT#
8
don't support willameter
VCCP
R322
R322
X_4.7KR0402
X_4.7KR0402
B
C E
Q40 X_N-SST3904_SOT23Q40 X_N-SST3904_SOT23
7
HDBI#[0..3]{7}
TP15TP15
IERR#{5}
FERR#{18}
STPCLK#{18}
HINIT#{18}
HDBSY#{7}
HDRDY#{7}
HTRDY#{7}
HADS#{7}
HLOCK#{7}
HBNR#{7}
HIT#{7}
HITM#{7}
HBPRI#{7}
HDEFER#{7}
RN39B 8P4R-51RRN39B 8P4R-51R
3 4
RN40A 8P4R-51RRN40A 8P4R-51R
1 2
RN39A 8P4R-51RRN39A 8P4R-51R
1 2
RN40C 8P4R-51RRN40C 8P4R-51R
5 6
RN39D 8P4R-51RRN39D 8P4R-51R
7 8
CPU_TMPA{26}
VTIN_GND{26}
THERMTRIP#{5}
CPUMISS{17}
PROCHOT#{5}
IGNNE#{18}
SMI#{18}
SLP#{18}
C240 X_C0.1U16Y0402C240 X_C0.1U16Y0402
R305 X_1KR0402-1R305 X_1KR0402-1
H_BSL0{5,21}
H_BSL1{5,21}
H_BSL2{5}
CPU_GD{5,19}
CPURST#{5,7}
HD#[0..63]{7}
B
7
HDBI#0
HDBI#1
HDBI#2
HDBI#3
-EDRDY
IERR#
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
CPU_BOOT
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
HA#[3..33]{7}
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
6
U7A
U7A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
HD#53
6
D53#
C14
HD#52
D52#
C15
HD#51
D51#
A14
HD#50
D50#
D17
HD#49
CPU SIGNAL BLOCK
HA#30
HA#31
HA#29
HA#27
HA#32
HA#33
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
F21
F20
E22
E21
D20
D22
G22
G21
HD#42
HD#41 HA#28
HD#43
HD#48
HD#47
HD#44
HD#40
HD#45
HD#46
AF5
E19
HA#26
AB4
A27#
D40#
E18
HD#39
HA#25
AC5
A26#
D39#
F18
HD#38
HA#24
AB5
A25#
D38#
F17
HD#37
HA#23
AA5
A24#
D37#
G17
HD#36
HA#22
AD6
A23#
D36#
G18
HD#35
HA#21
AA4
A22#
D35#
E16
HD#34
HA#20
A21#
D34#
E15
HD#33
5
HA#19
HA#17
HA#18
AB6
A20#Y4A19#Y6A18#W6A17#
D33#
D32#
D31#
D30#
F15
G16
G15
HD#32
HD#30
HD#31
5
HA#16
HA#14
HA#12
HA#11
HA#13
HA#15
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D29#
D28#
D27#
D26#
D25#
D24#
F14
F12
E13
D13
G14
G13
HD#28
HD#25
HD#26
HD#27
HD#24
HD#29
HA#6
HA#8
HA#10
HA#7
HA#9
U6
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
F11
E10
D10
HD#23
HD#20
HD#21
HD#19
HD#22
HA#4
HA#5
HD#17
HD#18
HA#3
L5
HD#16
HD#15
D11
R297
R297
X_0R0402
X_0R0402
AC2
DBR#
D14#
B12
C12
HD#13
HD#14
AN3
D13#
HD#12
AN4
RSVD
RSVD
D12#D8D11#
C11
HD#10
HD#11
4
AN5
B10
4
AJ3
AK3
AN6
ITP_CLK1
VSS_SENSE
VCC_SENSE
D10#
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A11
A10
HD#8
HD#9
HD#7
HD#6
TP4TP4
AM7
VID7#
ITP_CLK0
HD#3
HD#4
HD#5
VID5
VID4
AM5
AL4
AK4
VID6#
VID5#
VID_SELECT
GTLREF_SEL
HD#2
HD#1
VID4#
LINT0/INTR
FP_RST# {19,23}
C252
C252
C22U10Y1206
C22U10Y1206
VID0
VID3
VID2
VID1
AL6
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
GTLREF0
GTLREF1
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
RSVD
RSVD
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B4
HD#0
3
VCC_VRM_SENSE {20}
VSS_VRM_SENSE {20}
VID[0..5] {20}
R303 62R0402R303 62R0402
AN7
CPU_GTLREF0
H1
CPU_GTLREF1
H2
GTLREF_SEL
H29
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
G5
HREQ#4
J6
HREQ#3
K6
HREQ#2
M6
HREQ#1
J5
HREQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
H_TESTHI9
G4
H_TESTHI8
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
RSVD_AK6
AK6
RSVD_G6
G6
G28
F28
HRS#2
A3
HRS#1
F5
HRS#0
B3
-HAP1
U3
-HAP0
U2
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
TP7TP7
TP8TP8
TP5TP5
TP6TP6
3
RN41ARN41A
RN40B 8P4R-51RRN40B 8P4R-51R
RN40D 8P4R-51RRN40D 8P4R-51R
RN39C 8P4R-51RRN39C 8P4R-51R
RN41B 8P4R-51RRN41B 8P4R-51R
RN41C 8P4R-51RRN41C 8P4R-51R
R271 62R0402R271 62R0402
-HAP1 {7}
-HAP0 {7}
R289 60.4R1%0402R289 60.4R1%0402
R262 60.4R1%0402R262 60.4R1%0402
R287 60.4R1%0402R287 60.4R1%0402
R285 60.4R1%0402R285 60.4R1%0402
R288 60.4R1%0402R288 60.4R1%0402
R170 60.4R1%0402R170 60.4R1%0402
PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE
12
34
78
56
34
56
TP10TP10
HREQ#[0..4] {7}
R286 62R0402R286 62R0402
R301 62R0402R301 62R0402
R282 62R0402R282 62R0402
R283 62R0402R283 62R0402
R113 62R0402R113 62R0402
R270 62R0402R270 62R0402
R112 62R0402R112 62R0402
R276 X_62R0402R276 X_62R0402
R278 X_62R0402R278 X_62R0402
CPUCLK# {21}
CPUCLK {21}A20M#{18}
HRS#[0..2] {7}
HADSTB#1 {7}
HADSTB#0 {7}
HDSTBP#3 {7}
HDSTBP#2 {7}
HDSTBP#1 {7}
HDSTBP#0 {7}
HDSTBN#3 {7}
HDSTBN#2 {7}
HDSTBN#1 {7}
HDSTBN#0 {7}
NMI_SB {18}
INTR {18}
2
CPU_GTLREF0 {5}
CPU_GTLREF1 {5}
TP9TP9
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
VTT_OUT_RIGHT
HBR#0 {5,7}
VTT_OUT_LEFT
C242
C242
X_C0.1U16Y0402
X_C0.1U16Y0402
VTT_OUT_LEFT
SMI#
HINIT#
IGNNE#
STPCLK#
NMI_SB
SLP#
A20M#
INTR
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
R268 62R0402R268 62R0402
R267 62R0402R267 62R0402
R266 62R0402R266 62R0402
R265 62R0402R265 62R0402
R291 62R0402R291 62R0402
R264 62R0402R264 62R0402
R290 62R0402R290 62R0402
R263 62R0402R263 62R0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
INTEL LGA775 - SIGNALS
INTEL LGA775 - SIGNALS
INTEL LGA775 - SIGNALS
MS-7259 0A
MS-7259 0A
MS-7259 0A
2
1
100
of
of
of
434Tuesday, December 20, 2005
434Tuesday, December 20, 2005
434Tuesday, December 20, 2005
1
8
D D
C C
VCCP
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
U7B
U7B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
7
VCCP
AF21
VCC
VCC
Y8
AF22
Y30
VCC
VCC
6
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCU8VCCV8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y23
Y24
Y25
Y26
Y27
Y28
Y29
W30
W29
W28
W27
W26
W25
W24
W23
U26
U27
U28
U29
U30
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCT8VCC
VCC
VCC
T23
T24
T25
T26
T27
T28
T29
T30
U23
U24
U25
VCC
AJ15
VCC
VCCN8VCCP8VCCR8VCC
AJ18
N30
VCC
VCC
AJ19
N29
VCC
VCC
AJ21
N28
VCC
VCC
AJ22
N27
VCC
VCC
AJ25
N26
VCC
VCC
5
AJ26
N25
VCC
VCC
4
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
K25
K26
K27
K28
K29
N23
N24
M27
M28
M29
M30
K30
M23
M24
M25
M26
AM26
VCC
VCC
J14
AM29
VCC
VCC
J13
AM30
VCC
VCC
J12
AM8
J11
VCC
VCC
AM9
J10
VCC
VCC
AN11
VCC
VCC
AN9
3
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC-IOPLL
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD/VTT_PKGSENSE
VCC
VCC
VCC
VCC
VCC
HS11HS22HS33HS4
AN8
AN25
AN26
AN29
AN30
VCCA
VSSA
RSVD
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
4
H_VCCA
A23
H_VSSA
B23
D23
H_VCCIOPLL
C23
V_FSB_VTT
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
F27
F29
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
2
C121 X_C0.1U16Y0402C121 X_C0.1U16Y0402
C129 X_C10U10Y0805C129 X_C10U10Y0805
V_FSB_VTT
C130 C10U10Y0805C130 C10U10Y0805
CAPS FOR FSB GENERIC
B
B
VTT_OUT_RIGHT
VTT_OUT_LEFT
1
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
VTT_OUT_RIGHT
B B
Cedar Mill
VTT_OUT_LEFT
VTT_OUT_LEFT CPU_GTLREF1
R312 49.9R1%0402R312 49.9R1%0402
R310 49.9R1%0402R310 49.9R1%0402
R300
R300
100R1%0402
100R1%0402
R311
R311
100R1%0402
100R1%0402
R279 10R0402R279 10R0402
C251
C251
_C1U6.3Y50402/80-20%
_C1U6.3Y50402/80-20%
R299 10R0402R299 10R0402
C250
C250
_C1U6.3Y50402/80-20%
_C1U6.3Y50402/80-20%
CPU_GTLREF0VTT_OUT_RIGHT
C241
C241
C220P50N0402
C220P50N0402
C246
C246
C220P50N0402
C220P50N0402
CPU_GTLREF0 {4}
CPU_GTLREF1 {4}
PLACE AT CPU END OF ROUTE
VTT_OUT_RIGHT
VTT_OUT_LEFT
A A
8
VTT_OUT_RIGHT
VTT_OUT_LEFT
7
R275 62R0402R275 62R0402
R284 120R0402R284 120R0402
R293 100R0402R293 100R0402
R259 62R0402R259 62R0402 R324
R296 62R0402R296 62R0402
R292 62R0402R292 62R0402
CPURST#
PROCHOT#
CPU_GD
HBR#0
IERR#VTT_OUT_RIGHT
THERMTRIP#
6
CPURST# {4,7}
PROCHOT# {4}
CPU_GD {4,19}
HBR#0 {4,7}
THERMTRIP# {4}
5
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
L13 X_10U100m_0805L13 X_10U100m_0805
V_FSB_VTT
12
C141
C141
C1U16Y
C1U16Y
CP15CP15
L12
L12
X_10U100m_0805
X_10U100m_0805
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
CP14CP14
12
VID_GD#{19,20}IERR# {4}
4
C140
C140
C1U16Y
C1U16Y
B
VCC5_SB
R324
1KR0402-1
1KR0402-1
R323
R323
5.6KR0402-LF
5.6KR0402-LF
RN15 8P4R-470RRN15 8P4R-470R
1
2
3
4
5
6
7
8
VTT_OUT_LEFT
H_VCCIOPLL
H_VSSA
H_VCCA
R298
R298
_680R0402-1
_680R0402-1
Q41
Q41
N-SST3904_SOT23
N-SST3904_SOT23
H_BSL2 {4}
H_BSL1 {4,21}
H_BSL0 {4,21}
B
B
1.25V VTT_PWRGOOD
VTT_PWG
3
R302
R302
0R0402
VCCP
R315
R315
2.2KR0402
2.2KR0402
THERMTRIP#{4}
Title
Title
Title
INTEL LGA775 - POWER
INTEL LGA775 - POWER
INTEL LGA775 - POWER
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
THRDOWN
CE
Q38
Q38
B
N-SST3904_SOT23
C249
C249
C0.1U16Y0402
C0.1U16Y0402
N-SST3904_SOT23
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MS-7259 0A
MS-7259 0A
MS-7259 0A
0R0402
RSMRST# {18,19}
534Tuesday, March 14, 2006
534Tuesday, March 14, 2006
534Tuesday, March 14, 2006
1
of
of
of
1
VTT_OUT_RIGHT
VTT_OUT_RIGHT
GTLVREF_NB {7}
R273
R273
62R0402
62R0402
A A
TP11TP11
TP12TP12
TP14TP14
VSS
E23
E24
RSVD
VSS
AF16
AF17
RSVD
RSVDE5RSVDE6RSVDE7RSVD
VSS
VSS
VSS
AF20
AF23
TP13TP13
F23
B13
RSVDF6RSVD
VSS
VSS
VSS
VSS
VSS
AF24
AF25
AF26
AF27
AF28
H_COMP7
AC4
AE3
AE4
U7C
U7C
A12
VSS
A15
VSS
A18
VSS
A2
VSS
A21
VSS
A24
VSS
A6
VSS
A9
VSS
AA23
VSS
AA24
VSS
AA25
VSS
AA26
B B
C C
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D14
RSVD
RSVD
RSVD
RSVDD1RSVD
VSS
VSS
VSS
VSS
VSS
AE5
AE7
AF10
AF13
AE29
AE30
R269
R269
62R0402
62R0402
MSID1
RSVDJ3RSVDN4RSVDP5RSVDV1RSVDW1RSVD
VSS
VSS
VSS
VSS
VSS
AF3
AF6
AF7
AF29
AF30
2
MSID0
H_COMP6
VSS
VSS
AG10
AG13
R295
R295
62R0402
62R0402
Y3
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
AG16
AG17
AG20
AG23
AG24
VSS
R294
R294
VSS
AG7
3
4
5
MSID1 MSID0
VSS
0
0
R30
R29
R28
R27
R26
R25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AJ28
AJ29
AJ30
AK10
AK13
05 Per FMB
R272
R272
62R0402
62R0402
X_62R0402
X_62R0402
V30
VSS
VSS
VSS
VSS
AH1
AH10
AH13
AH16
AH17
VSS
AH20
V29
VSSV3VSS
VSS
VSS
AH23
05 Value FMB
V28
V27
V26
V25
V24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH3
AH6
AH7
AJ10
AH24
V23
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
AJ27
VSS
VSS
R24
VSS
VSS
AK16
R23
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
AK2
AK17
AK20
VSS
0
1
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSB1VSS
VSS
B11
AN1
AN2
AN10
AN13
AN16
AN17
AN20
AN23
AN24
B14
AN27
AN28
H14
VSS
H13
VSS
H12
VSS
H11
VSS
H10
VSS
G1
VSS
F7
VSS
F4
VSS
F22
VSS
F19
VSS
F16
VSS
F13
VSS
F10
VSS
E8
VSS
E29
VSS
E28
VSS
E27
VSS
E26
VSS
E25
VSS
E20
VSS
E2
VSS
E17
VSS
E14
VSS
E11
VSS
D9
VSS
D6
VSS
D5
VSS
D3
VSS
D24
VSS
D21
VSS
D18
VSS
D15
VSS
D12
VSS
C7
VSS
C4
VSS
C24
VSS
C22
VSS
C19
VSS
C16
VSS
C13
VSS
C10
VSS
B8
VSS
B5
VSS
B24
VSS
B20
VSS
B17
VSS
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
VSS
VSS
K2
L25
L24
L23
K5
VSS
VSS
VSS
VSSK7VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM16
AM17
AM4
AM20
AM23
AM24
AM27
AM28
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK5
AK7
AL10
AL13
AK23
AK24
AK27
AK28
AK29
AL16
AK30
VSS
L30
L29
L28
L27
L26
VSSL3VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL3
AL7
AL17
AL20
AL23
AM1
AL24
AL27
AL28
AM10
AM13
D D
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
INTEL LGA775 - GND
INTEL LGA775 - GND
INTEL LGA775 - GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet
Date: Sheet
1
2
3
4
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7259 0A
MS-7259 0A
MS-7259 0A
5
of
of
of
634Tuesday, December 20, 2005
634Tuesday, December 20, 2005
634Tuesday, December 20, 2005
4
3
2
1
VIA confirmed
V_FSB_VTT
D D
U9A
HA#[3..33]{4}
C C
HADSTB#0{4}
HADSTB#1{4}
HADS#{4}
HBNR#{4}
HBPRI#{4}
HBR#0{4,5}
HDBSY#{4}
HDEFER#{4}
HDRDY#{4}
HIT#{4}
HITM#{4}
HLOCK#{4}
HTRDY#{4}
C139
C139
near NB
HREQ#[0..4]{4}
HRS#[0..2]{4}
HDBI#[0..3]{4}
near NB
C143
C143
C0.01U50X
C0.01U50X
X_C0.01U50X
X_C0.01U50X
CPURST#{4,5}
NBHCLK{21}
NBHCLK#{21}
GTLVREF_NB
C133
C133
GTLVREF_NB1
C396
C396
-HAP0{4}
-HAP1{4}
C153
C153
C0.01U16X0402
C0.01U16X0402
B B
C0.01U16X0402
C0.01U16X0402
C0.01U50X
C0.01U50X
C0.01U50X
C0.01U50X
C0.1U16Y0402
C0.1U16Y0402
A A
C0.01U16X0402
C0.01U16X0402
C391
C391
C142
C142
-HAP0
-HAP1
HRCOMP
HCOMPVREF
TP16TP16
4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#32
HA#33
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
HDBI#0
HDBI#1
HDBI#2
HDBI#3
C392
C392
-DPRW
1
U9A
Y29
HA3
V27
HA4
AA29
HA5
Y27
HA6
Y26
HA7
AC27
HA8
AA28
HA9
AB27
HA10
AA27
HA11
AC29
HA12
AB29
HA13
AB28
HA14
AC26
HA15
AD29
HA16
T28
HA17
R28
HA18
N29
HA19
N28
HA20
P29
HA21
P27
HA22
R27
HA23
N26
HA24
T26
HA25
P26
HA26
R25
HA27
N27
HA28
N25
HA29
R29
HA30
T27
HA31
U26
HA32
T25
HA33
W28
HADSTB0
R26
HADSTB1
M29
ADS
M28
BNR
T29
BPRI
K26
BREQ
M25
DBSY
U27
DEFER
M26
DRDY
L27
HIT
U29
HITM
L29
HLOCK
M24
HTRDY
W27
HREQ0
V28
HREQ1
V26
HREQ2
W29
HREQ3
V29
HREQ4
L26
RS0
M27
RS1
K25
RS2
C29
HDBI0
H27
HDBI1
B21
HDBI2
A21
HDBI3
D14
CPURST
Y23
HCLK+
W23
HCLK-
R24
HAVREF0
V24
HAVREF1
F22
HDVREF0
G24
HDVREF1
F19
HDVREF2
F16
HDVREF3
L24
GTLVREF
N24
HAP0
W26
HAP1
G25
HRCOMP
G26
HCOMPVREF
K24
DPWR
VIA-P4M800Pro-CD
VIA-P4M800Pro-CD
A16
GND
A19
GND
B22
GND
B25
GND
U19
T19
R19
P19
N19
M19
L19
L18
L17
L16
L15
V18
GND
U18
GND
HDSTB0P
HDSTB0N
HDSTB1P
HDSTB1N
HDSTB2P
HDSTB2N
HDSTB3P
HDSTB3N
GND
T18
AC28
GND
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
L25
L28
E29
E26
E25
E22
B28
D16
D15
D19
H26
H29
GND
GND
GND
GND
GND
P25
P28
Y25
Y28
P18
U28
U25
N18
R18
M18
3
D27
D26
A29
C26
C28
D28
A27
B29
A26
B26
D25
E24
A25
A28
D24
C25
K28
K29
J28
K27
J26
J29
J25
J27
F28
G29
G27
D29
E27
F27
E28
F29
E23
B24
C24
A24
A23
B23
A22
C23
F21
C22
E21
C21
D20
D21
F20
E20
B19
C19
B20
B18
C20
A20
C18
B17
B16
A17
C14
C15
A18
B15
B14
A15
B27
C27
H28
G28
D23
D22
C17
C16
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HDSTBP#0 {4}
HDSTBN#0 {4}
HDSTBP#1 {4}
HDSTBN#1 {4}
HDSTBP#2 {4}
HDSTBN#2 {4}
HDSTBP#3 {4}
HDSTBN#3 {4}
HD#[0..63] {4}
V_FSB_VTT
V_FSB_VTT V_FSB_VTT
Component Side
R111
VCCP
2
R111
X_0R
X_0R
CP7CP7
12
CB9
CB9
C10U10Y0805
C10U10Y0805
CB7
CB7
C10U10Y0805
C10U10Y0805
CB12
CB12
X_C0.1U16Y0402
X_C0.1U16Y0402
CB13
CB13
C1U16Y
C1U16Y
CB23
CB23
C1U16Y
C1U16Y
CB70
CB70
C10U10Y0805
C10U10Y0805
CB11
CB11
X_C0.1U16Y0402
X_C0.1U16Y0402
CB73
CB73
C1U16Y
C1U16Y
Solder Side
R115 49.9R1%0402R115 49.9R1%0402
R116 49.9R1%0402R116 49.9R1%0402
R114 100R1%0402R114 100R1%0402
C146
C146
C0.1U16Y0402
C0.1U16Y0402
R137 20.5R1%0402R137 20.5R1%0402
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
GTLVREF_NB1
R119
R119
100R1%0402
100R1%0402
GTLVREF_NB
R117
R117
100R1%0402
100R1%0402
HCOMPVREF
R121
R121
49.9R1%0402
49.9R1%0402
HRCOMP
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
P4M800-CPU
P4M800-CPU
P4M800-CPU
MS-7259 0A
MS-7259 0A
MS-7259 0A
GTLVREF_NB {6}
1
734Tuesday, December 20, 2005
734Tuesday, December 20, 2005
734Tuesday, December 20, 2005
of
of
of
BY PASS CAP
4
VCC_DDR
W12
W13
W14
W15
W16
V11
U9B
AD28
AE27
AF27
AG28
AD27
AE29
AG27
AG29
AH29
AJ29
AG25
AJ25
AJ28
AH27
AH26
AJ26
AJ24
AG24
AJ22
AG21
AH24
AG23
AG22
AJ21
AH21
AJ20
AG18
AH18
AG20
AH19
AJ18
AG17
AJ12
AG12
AJ10
AH12
AJ11
AG10
AG8
AH6
AG9
AG5
AH4
AH1
AG4
AG3
AG1
AD3
AD1
AG2
AE1
AD2
AF21
AF23
AE22
AF24
AF28
AJ27
AJ23
AJ19
AG11
AH7
AJ9
AH9
AJ7
AJ6
AJ8
AJ5
AJ4
AJ2
AF4
AJ1
AF2
AF3
AJ3
AF1
U9B
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
CKE0
CKE1
CKE2
CKE3
DQM0
DQM1
DQM2
DQM3
DQM4
DQM5
DQM6
DQM7
-DQM0
-DQM1
-DQM2
-DQM3
-DQM4
-DQM5
-DQM6
-DQM7
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
CKEA0
CKEA1
CKEA2
CKEA3
D D
C C
B B
MD[0:63]{11}
CKEA0{11,12}
CKEA1{11,12}
CKEA2{11,12}
CKEA3{11,12}
-DQM[0:7]{11}
W11
VCC18MEM
W17
VCC18MEM
VCC18MEM
VCC18MEM
VCC18MEM
VCC18MEM
VCC18MEM
VCC18MEM
W18
3
W19
V19
MA0
MA1
MA2
MA3
VCC18MEM
VCC18MEM
VCC18MEM
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
BA0
BA1
DMCOMP
MEMDET
ODT0
ODT1
ODT2
ODT3
SRAS
SCAS
SWE
CS0
CS1
CS2
CS3
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
MCLKIA
MCLKO-
MCLKO+
MEMVREF1
MEMVREF2
MEMVREF3
MEMVREF4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AF13
AD15
AJ15
AJ16
AJ17
AF16
AG15
AE18
AF17
AE19
AJ14
AF20
AE21
AD7
AF12
AJ13
AE5
AE24
AE9
AE10
AF6
AD6
AE12
AF9
AF11
AD9
AF8
AG7
AF7
AF29
AG26
AH22
AG19
AH10
AG6
AH3
AE3
AD26
AE26
AF26
AD23
AD17
AD11
AD8
M16
N16
P16
R16
T16
U16
V16
M15
N15
P15
-CS0
-CS1
-CS2
-CS3
-DQS0
-DQS1
-DQS2
-DQS3
-DQS4
-DQS5
-DQS6
-DQS7
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
BA0 {11,12}
BA1 {11,12}
R216 _301R1%0402-1R216 _301R1%0402-1
MEMDET
ODT0 {11,12}
ODT1 {11,12}
ODT2 {11,12}
ODT3 {11,12}
-SRASA {11,12}
-SCASA {11,12}
-SWEA {11,12}
-CS0 {11,12}
-CS1 {11,12}
-CS2 {11,12}
-CS3 {11,12}
DCLKI
MCLKOÂMCLKO+
DCLKI {21}
DCLKO as short as passable
DCLKI = DCLKx + 2 "
MVREF_NB
MAA[0:13] {11,12}
-DQS[0:7] {11}
2
-CS[0..3]{11,12}
ODT[0..3]{11,12}
BA[0..1]{11,12}
CKEA[0..3]{11,12}
R719 _22R-LFR719 _22R-LF
R720 _22R-LFR720 _22R-LF
Test Point
(Place near their respective balls of NB)
DCLKO- {21}
DCLKO+ {21}
DCLKI
MCLKO+
MCLKO-
VCC_DDR
R214
R214
100R1%0402
100R1%0402
MVREF_NB
R211
R211
100R1%0402
100R1%0402
VCC_DDR
Component Side
TP17TP17
1
TP2TP2
1
TP3TP3
1
VCC_DDR
MVREF_NB = 0.5* VCCDDR
C397
C207
C207
C1000P50X0402
C1000P50X0402
C397
C1000P50X
C1000P50X
VCC_DDR
CB25
CB25
C10U10Y0805
C10U10Y0805
CB24
CB24
X_C10U10Y0805
X_C10U10Y0805
CB22
CB22
X_C1U16Y
X_C1U16Y
Solder Side
R239 1KR1%0402R239 1KR1%0402
R230 X_1KR1%R230 X_1KR1%
MEMDET
1
C403
C403
C0.01U50X
C0.01U50X
CB72
CB72
C10U10Y0805
C10U10Y0805
CB79
CB79
C0.1U16Y
C0.1U16Y
CB77
CB77
X_C1U16Y
X_C1U16Y
CB74
CB74
C1U16Y
C1U16Y
CB67
CB67
X_C10U10Y0805
X_C10U10Y0805
CB85
CB85
X_C1U16Y
X_C1U16Y
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AE2
GND
AE8
AE11
AH11
AH14
AH17
AH8
AH5
AH2
AE28
AE25
AE23
AE20
AE17
AE16
AE14
A A
4
VIA-P4M800Pro-CD
VIA-P4M800Pro-CD
AH20
GND
AH23
GND
AH25
GND
GND
GND
GND
GND
GND
GND
N17
GND
GND
GND
GND
GND
T17
U17
T15
V17
V15
U15
R15
P17
R17
DCLKI
Near to NB chip
2
C393 X_C5P50NC393 X_C5P50N
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
P4M800-DDR
P4M800-DDR
P4M800-DDR
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7259 0A
MS-7259 0A
MS-7259 0A
1
834Tuesday, December 20, 2005
834Tuesday, December 20, 2005
834Tuesday, December 20, 2005
of
of
of
GND
GND
AF5
M17
AH28
3
4
VCC_AGP
M11
N11
P11
R11
GND
P14
GND
R12
VCC15AGP
GND
R13
VCC15AGP
GND
R14
VCC15AGP
GND
T12
VCC15AGP
GND
T11
VCC15AGP
GND
GND
GND
T14
T13
U12
U9C
VLAD[0:7]{18}
D D
UPSTB{18}
-UPSTB{18}
UPCMD{18}
C C
+1.5VNB
B B
A A
VSUS15
VSUS15
-SUSST{17}
PCIRST#2{15,19,29,30}
-PWROK_NB{17}
VCC_DDR
R228 4.7KR0402R228 4.7KR0402
Strapping For NB_TEST Mode
TESTIN BISTIN RBF WBF
1 1 x x Disable all TEST mode
VBE0{18}
DNSTB{18}
-DNSTB{18}
DNCMD{18}
TESTIN_NB
4
VLAD0
VLAD1
VLAD2
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7
LVREF_NB
LCOMPP
TESTIN_NB
AVDD1
AVDD2
U9C
V1
VD0
U2
VD1
Y2
VD2
Y3
VD3
T2
VD4
T3
VD5
AA2
VD6
AA1
VD7
U3
VBE
W2
UPSTB+
W1
UPSTB-
V2
DNSTB+
V3
DNSTB-
AA3
UPCMD
W3
DNCMD
V4
VLVREF
T4
VLCOMPP
U11
VCC15VL
U10
VCC15VL
V10
VCC15VL
K10
VCC15
K11
VCC15
K12
VCC15
K13
VCC15
K15
VCC15
K17
VCC15
K19
VCC15
K20
VCC15
Y10
VCC15
Y12
VCC15
Y14
VCC15
Y16
VCC15
Y18
VCC15
Y20
VCC15
L10
VCC15
N10
VCC15
R10
VCC15
W10
VCC15
M20
VCC15
P20
VCC15
T20
VCC15
V20
VCC15
AC25
VSUS15
AB1
VSUS15
AB3
SUSST
AF25
TESTIN
AC1
RESET
AB2
PWROK
AA25
VCCA33HCK
AD25
VCCA33MCK
AA26
GNDAHCK
AD24
GNDAMCK
VIA-P4M800Pro-CD
VIA-P4M800Pro-CD
M12
GND
M13
GND
M14
GND
N12
GND
N13
GND
N14
GND
GND
P13
P12
3
GD24/GDVP1D09
GD26/GDVP1D10
GD27/GDVP1D04
GD28/GDVP1D07
GD29/GDVP1D06
GD30/GDVP1D08
GD31/GDVP1DET
GC#BE0/FPD03
GC#BE1/SBPLDAT
GC#BE2/FPD19
GC#BE3/GDVP1D11
GFRAME/FPHS
GIRDY/SBPLCLK
GDEVSEL/FPVS
GSTOP/FP1CLK
GREQ/SBDDCCLK
GGNT/SBDDCDAT
GSERR/FP1DE
GST0/ENAVEE
GST1/ENAVDD
GST2/ENABLT
GSBSTBF/GDVP1D01
GSBSTBS/GDVP1D02
GADSTBF0/FPD04
GADSTBS0/FPD02
GADSTBF1/FPD12
GADSTBS1/FPDET
GSBA0/GDVP1VS
GSBA1/GDVP1DE
GSBA2/GDVP1D00
GSBA3/GDVP1HS
GSBA4/GDVP1D05
GSBA5/GDVP1D03
GSBA6/GDVP1CLK
GSBA7/GDVP1CLK
GND
GND
GND
GND
GND
V12
V13
V14
U13
U14
3
GD0/FPD10
GD1/FPD11
GD2/FP1CLK
GD3/FPD09
GD4/FPD08
GD5/FPD07
GD6/FPD06
GD7FPD05
GD8/FP1DET
GD9/FP1HS
GD10/FPD01
GD11/FPD23
GD12/FPD00
GD13/FPD22
GD14/FPD21
GD15/FPD20
GD16/FPD18
GD17/FPD17
GD18/FPD16
GD19/FPDE
GD20/FPD14
GD21/FPCLK
GD22/FPD13
GD23/FPD15
GD25
GTRDY
GPAR/FP1VS
GDBIH
GRBF
GWBF/FPCLK
GDBIL
AGP8XDET
AGPVREF1
AGPVREF2
GCLK
AGPCOMPN
AGPCOMPP
AGPBUSY
LCOMPP
P3
P4
R3
R4
R1
N2
P1
R2
M3
M1
N4
L3
L1
N5
K2
R6
J2
H3
H1
K4
G1
R164 33R0402-2R164 33R0402-2
G2
K5
G3
D9
J6
K6
D10
J4
D4
F2
D7
J5
D6
F3
D8
H4
E1
M2
K1
J1
D11
L6
L4
M5
K3
J3
M4
P6
G5
F4
B3
D5
C4
M6
H6
C5
E4
E3
F5
D1
C1
D2
C2
N1
N3
G4
F1
VS
A1
DE
A2
D0
B1
HS
C3
D5
D1
D3
D4
DVPCLK
D2
DVPCLK_N
D3
N6
G6
R5
AGPCOMPN
A4
AGPCOMPP
A3
T1
AGPCOMPN
AGPCOMPP
R127 60.4R1%0402R127 60.4R1%0402
R194 _402R1%0402-1R194 _402R1%0402-1
DVO11 {15}
DVO10 {15}
DVO9 {15}
DVO8 {15}
DVO6 {15}
DVO5 {15}
DVO4 {15}
TVDE {15}
DVO2 {15}
TVCLK {15}
DVO1 {15}
DVO3 {15}
DVP1DET {14}
SBDAT1 {14,15}
DVO7 {15}
TVHS {15}
SBCLK1 {14,15}
TVVS {15}
DE
HS
VS
D2
2
D0
4
D3
6
D1
8
D5
2
D6
4
D4
6
D7
8
D8
2
D9
4
D10
6
D11
8
DVO0 {15}
TVCLKR {15}
GCLK_NB {21}
AGPBZ {18}
R125 60.4R1%0402R125 60.4R1%0402
R14322R0402 R14322R0402
R14622R0402 R14622R0402
R14722R0402 R14722R0402
RN24_8P4R-22R-LF RN24_8P4R-22R-LF
1
3
5
7
1
3
5
7
1
3
5
7
RN26_8P4R-22R-LF RN26_8P4R-22R-LF
RN28_8P4R-22R-LF RN28_8P4R-22R-LF
C189
C189
C0.1U16Y0402
C0.1U16Y0402
VCC_AGP
DP1DE {14}
DP1HS {14}
DP1VS {14}
DP1D02 {14}
DP1D00 {14}
DP1D03 {14}
DP1D01 {14}
DP1D05 {14}
DP1D06 {14}
DP1D04 {14}
DP1D07 {14}
DP1D08 {14}
DP1D09 {14}
DP1D10 {14}
DP1D11 {14}
VCC_AGP
R721
R721
1KR
1KR
R180
R180
1KR0402-1
1KR0402-1
DVPCLK
DVPCLK_N
2
VCC VSUS15 Regulator
VCC3_SB VSUS15
U12
U12
LT1087S_SOT89
LT1087S_SOT89
C213
C213
X_C10U10Y1206
X_C10U10Y1206
VIN3VOUT
C210
C210
C0.1U16Y0402
C0.1U16Y0402
ADJ
1
2
R210
R210
422R1%0402
422R1%0402
R203
R203
100R1%0402
100R1%0402
C10U10Y1206
C10U10Y1206
+1.5VNB
Solder Side
FB10
FB10
X_220L2_50
X_220L2_50
AVDD2
X_C1000P50X0402
X_C1000P50X0402
VCC3
FB9
FB9
X_220L2_50
X_220L2_50
AVDD1
VCC_AGP
CB76
CB76
C10U10Y0805
C10U10Y0805
CB83
CB83
C1U16Y
C1U16Y
CB82
CB82
X_C1U16Y
X_C1U16Y
trace width 100-mil
C218
C218
CM9
CM9
C0.1U16Y0402
C0.1U16Y0402
+1.5VNB
C209
C209
C0.1U16Y0402
C0.1U16Y0402
CM8
CM8
Title
Title
Title
P4M800-VLINK&GRAPHIC
P4M800-VLINK&GRAPHIC
P4M800-VLINK&GRAPHIC
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
MS-7259 0A
MS-7259 0A
MS-7259 0A
R136
R136
1KR1%0402
1KR1%0402
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Component Side
VCC_AGP
X_COPPER
X_COPPER
R154 22R0402R154 22R0402
R151 22R0402R151 22R0402
2
CP19
CP19
CP18
CP18
X_COPPER
X_COPPER
CB14
CB14
C0.1U16Y0402
C0.1U16Y0402
CB16
CB16
C0.1U16Y0402
C0.1U16Y0402
CB15
CB15
C0.1U16Y0402
C0.1U16Y0402
VCC3
12
C215
C215
C1U16Y
C1U16Y
12
C211
C211
C1U16Y
C1U16Y
X_C1000P50X0402
X_C1000P50X0402
CLK {14}
CLK_N {14}
1
C206
C206
C204
C204
X_C10U10Y1206
X_C10U10Y1206
C401
C401
C0.01U50X
C0.01U50X
C394
C394
X_C0.1U16Y
X_C0.1U16Y
C395
C395
C10U10Y0805
C10U10Y0805
C404
C404
C0.1U16Y
C0.1U16Y
C402
C402
C0.1U16Y
C0.1U16Y
C400
C400
C1U16Y
C1U16Y
CB68
CB68
C10U10Y0805
C10U10Y0805
VCC_AGP +1.5VNB
R135
R135
1.4KR1%0402
1.4KR1%0402
LVREF_NB
C182
C182
C152
C152
C0.1U16Y
C0.1U16Y
C0.1U16Y0402
C0.1U16Y0402
LVREF_NB => VDD/4=0.625
934Friday, December 16, 2005
934Friday, December 16, 2005
934Friday, December 16, 2005
of
of
1
of
4
U9D
U9D
D D
FPD4
FPD5
RN21
RN21
8P4R-4.7KR
8P4R-4.7KR
1 2
3 4
5 6
7 8
C C
FPD8
C13
B13
A13
D13
E13
D12
C12
A12
B12
E12
B11
A11
E11
C11
A10
B10
E10
C10
D11
B9
DVP0D00/TVD00
DVP0D01/TVD01
DVP0D02/TVD02
DVP0D03/TVD03
DVP0D04/TVD04
DVP0D05/TVD05
DVP0D06/TVD06
DVP0D07/TVD07
DVP0D08/TVD08
DVP0D09/TVD09
DVP0D10/TVD10
DVP0D11/TVD11
GPO0
GPOUT
TVCLKR
DVP0DE/TVDE
DVP0HS/TVHS
DVP0VS/TVVS
DVP0CLK/TVCLK
DVP0DET
VCCPLL1
VCCPLL2
C7
D7
VCCA33PLL1D8VCCA33PLL2
VCCA33DAC1E7VCCA33DAC2
GNDB4GNDE2GNDE5GNDH2GNDH5GNDL2GNDL5GNDP2GNDP5GNDU1GNDU4GND
GNDB2GND
A14
VCCDAC1
VCCDAC2
VCC3 VCC3
L13
L12
L14
AR
AG
AB
VCC33GFX
VCC33GFX
VCC33GFX
RSET
HSYNC
VSYNC
XIN
INTA
SPCLK1
SPCLK2
SPD1
SPD2
DISPCLKI
DISPCLKO
GNDAPLL1
GNDAPLL2
GNDADAC2
GNDADAC1
Y1
B6
A5
B5
A6
B8
A8
A7
A9
D9
E9
D10
E8
C8
C9
B7
C6
D6
E6
RSET
3
AR {13}
AG {13}
AB {13}
R120
R120
80.6R1%0402
80.6R1%0402
HSYNC {13}
VSYNC {13}
GUICK {21}
PIRQ#A {16,24,29}
SPDCLK2 {13}
SPD2 {13}
R144
R144
22R0402
22R0402
VCC3
CB78
CB78
2
CP11
CP11
X_COPPER
X_COPPER
CP8
CP8
X_COPPER
X_COPPER
C1U16Y
C1U16Y
CB5
CB5
C0.1U16Y0402
C0.1U16Y0402
C98
C98
X_C0.1U16Y0402
X_C0.1U16Y0402
12
FB7
FB7
X_220L2_50
X_220L2_50
VCCPLL1
CM7
FB4
FB4
X_220L2_50
X_220L2_50
VCCPLL2
CM7
X_C1000P50X0402
X_C1000P50X0402
CM5
CM5
X_C1000P50X0402
X_C1000P50X0402
C137
C137
C1U16Y
C1U16Y
VCC3 VCC3
12
C136
C136
C1U16Y
C1U16Y
CP10
CP10
X_COPPER
X_COPPER
CP9
CP9
X_COPPER
X_COPPER
VCC3
12
C135
C135
C1U16Y
C1U16Y
12
C145
C145
X_C1000P50X0402
X_C1000P50X0402
1
FB6
FB6
X_220L2_50
X_220L2_50
VCCDAC1
FB5
FB5
X_220L2_50
X_220L2_50
VCCDAC2
CM6
CM6
X_C1000P50X0402
X_C1000P50X0402
CM4
CM4
C1U16Y
C1U16Y
R129
R129
10KR0402
10KR0402
R139
R139
X_10KR0402
X_10KR0402
VCC3
R131
R131
X_10KR0402
X_10KR0402
R141
R141
10KR0402
10KR0402
R130
R130
X_10KR0402
X_10KR0402
R140
R140
10KR0402
10KR0402
3
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
P4M800-VGA
P4M800-VGA
P4M800-VGA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
2
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7259 0A
MS-7259 0A
MS-7259 0A
1
10 34Friday, December 16, 2005
10 34Friday, December 16, 2005
10 34Friday, December 16, 2005
of
of
of
GFX power up strapping setting:
TVD4/DVP0D4 =>AGP Port Muxing
TVD5/DVP0D5 =>Dedicated DVI Port Configuration
TVD6/DVP0D6 =>Dedicated DVI Port Selection
TVD8/DVP0D8 =>External AGP Function Enable
TVD9/DVP0D9 =>PCI Signal Test Output Enable
B B
TVD10/DVP0D10 =>CPUCK/MCK Clock Select
TVD7/DVP0D7 =>GFX Clock Select(VCK/LCDCK/ECK)
A A
0: Two 12-bit DVI interface
1: One 24-bit Panel interface
0: TMDS
1: TV Encoder
0: Disable
1: Enable
0: External
1: Internal
0: Disable
1: Enable
0: From NB
1: From External
0: Refer Internal PLL
1: From External
VIA-P4M800Pro-CD
VIA-P4M800Pro-CD
4
FPD8
FPD4
FPD5
8
DIMM1
MD[0:63]{8} MD[0:63]{8}
D D
C C
B B
A A
8
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DIMM1
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
3
4
9
10
12
13
21
22
24
25
30
31
33
34
39
40
80
81
86
87
89
90
95
96
98
99
2
5
8
11
14
17
20
23
26
29
32
35
38
41
44
47
50
65
66
79
82
85
88
91
94
97
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC_DDR
55
100
VSS
19
NC
RC118RC0
VSS
VSS
103
106
102
NC/TEST
VSS
109
R437
R437
1KR1%0402
1KR1%0402
7
VCC_DDR VCC3 VCC_DDR VCC3
170
197
172
187
184
189
67
68
NC
VDD051VDD156VDD262VDD372VDD478VDD5
VSS
VSS
VSS
112
115
118
121
VSS
VSS
124
191
75
VDD3
VSS
VSS
VSS
127
130
133
136
DIMM_VREF_A
R438
R438
1KR1%0402
1KR1%0402
7
194
181
175
VDD6
VDD7
VDD8
VDDQ0
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
VSS
VSS
VSS
VSS
VSS
139
142
145
148
151
154
178
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
157
160
163
166
169
198
201
204
207
238
VDDQ9
VDDSPD
VSS
VSS
VSS
VSS
210
213
216
219
SMBCLK_DDR
SMBDATA_DDR
6
CB042CB143CB248CB349CB4
VSS
VSS
VSS
222
225
6
161
162
167
CB5
DQS0
DQS0#
DQS1
DQS1#
DQS2
DQS2#
DQS3
DQS3#
DQS4
DQS4#
DQS5
DQS5#
DQS6
DQS6#
DQS7
DQS7#
DQS8
DQS8#
A10_AP
A16/BA2
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
ODT0
ODT1
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
VREF
VSS
VSS
VSS
DDRII-240_blue-RH
DDRII-240_blue-RH
228
231
234
237
CB6
WE#
CAS#
RAS#
CKE0
CKE1
CS0#
CS1#
VSS
168
CB7
-DQS0
7
6
-DQS1
16
15
-DQS2
28
27
-DQS3
37
36
-DQS4
84
83
-DQS5
93
92
-DQS6
105
104
-DQS7
114
113
46
45
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
57
A11
176
A12
196
A13
174
A14
173
A15
54
BA1
190
BA1
BA0
71
BA0
-SWEA
73
-SCASA
74
-SRASA
192
-DQM0
125
126
-DQM1
134
135
-DQM2
146
147
-DQM3
155
156
-DQM4
202
203
-DQM5
211
212
-DQM6
223
224
-DQM7
232
233
164
165
ODT0
195
ODT1
77
CKEA0
52
CKEA1
171
-CS0
193
-CS1
76
MDCLKA0
185
MDCLKA#0
186
MDCLKA1
137
MDCLKA#1
138
MDCLKA2
220
MDCLKA#2
221
SMBCLK_DDR
120
SCL
SMBDATA_DDR
119
SDA
DIMM_VREF_A
1
239
SA0
240
SA1
101
SA2
R434 33R0402-2R434 33R0402-2
R435 33R0402-2R435 33R0402-2
VCC3
C375
C375
C0.1U16Y0402
C0.1U16Y0402
-DQS0 {8}
-DQS1 {8}
-DQS2 {8}
-DQS3 {8}
-DQS4 {8}
-DQS5 {8}
-DQS6 {8}
-DQS7 {8}
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
BA1 {8,12}
BA0 {8,12}
-SWEA {8,12}
-SCASA {8,12}
-SRASA {8,12}
-DQM[0:7] {8}
ODT0 {8,12}
ODT1 {8,12}
CKEA0 {8,12}
CKEA1 {8,12}
-CS0 {8,12}
-CS1 {8,12}
MDCLKA0 {21}
MDCLKA#0 {21}
MDCLKA1 {21}
MDCLKA#1 {21}
MDCLKA2 {21}
MDCLKA#2 {21}
C311
C311
C0.1U16Y0402
C0.1U16Y0402
PLACE CLOSE TO DIMM PIN
ADDRESS: 000
0xA0
DDR2 DIMM1
SMBCLK_ISO {17,19,21,26,30}
SMBDATA_ISO {17,19,21,26,30}
5
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD8
MD9
MD10
MD11
MD12
MD13
MD14
MD15
MD16
MD17
MD18
MD19
MD20
MD21
MD22
MD23
MD24
MD25
MD26
MD27
MD28
MD29
MD30
MD31
MD32
MD33
MD34
MD35
MD36
MD37
MD38
MD39
MD40
MD41
MD42
MD43
MD44
MD45
MD46
MD47
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
ODT[0..3]{8,12}
CKEA[0..3]{8,12}
BA[0..1]{8,12}
5
DIMM2
DIMM2
122
123
128
129
131
132
140
141
143
144
149
150
152
153
158
159
199
200
205
206
208
209
214
215
107
108
217
218
226
227
110
111
116
117
229
230
235
236
-DQS[0:7]{8}
4
68
19
55
102
NC
NC
3
RC118RC0
DQ0
4
DQ1
9
DQ2
10
DQ3
DQ4
DQ5
DQ6
DQ7
12
DQ8
13
DQ9
21
DQ10
22
DQ11
DQ12
DQ13
DQ14
DQ15
24
DQ16
25
DQ17
30
DQ18
31
DQ19
DQ20
DQ21
DQ22
DQ23
33
DQ24
34
DQ25
39
DQ26
40
DQ27
DQ28
DQ29
DQ30
DQ31
80
DQ32
81
DQ33
86
DQ34
87
DQ35
DQ36
DQ37
DQ38
DQ39
89
DQ40
90
DQ41
95
DQ42
96
DQ43
DQ44
DQ45
DQ46
DQ47
98
DQ48
99
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
2
VSS
5
VSS
8
VSS
11
VSS
14
VSS
17
VSS
20
VSS
23
VSS
26
VSS
29
VSS
32
VSS
35
VSS
38
VSS
41
VSS
44
VSS
47
VSS
50
VSS
65
VSS
66
VSS
79
VSS
82
VSS
85
VSS
88
VSS
91
VSS
94
VSS
97
VSS
VDD051VDD156VDD262VDD372VDD478VDD5
NC/TEST
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
100
103
106
109
112
115
118
121
124
127
4
170
191
194
181
175
75
VDD6
VDD7
VDD8
VDD3
VDDQ0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
130
133
136
139
142
145
148
VDDQ153VDDQ259VDDQ364VDDQ4
VSS
151
154
3
197
172
187
184
189
178
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ469VDDQ7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
157
160
163
166
169
198
201
204
3
2
67
238
161
162
167
168
CB042CB143CB248CB349CB4
CB5
CB6
CB7
-DQS0
7
VDDQ9
VDDSPD
VSS
VSS
VSS
207
210
213
216
DQS0
6
DQS0#
-DQS1
16
DQS1
15
DQS1#
-DQS2
28
DQS2
27
DQS2#
-DQS3
37
DQS3
36
DQS3#
-DQS4
84
DQS4
83
DQS4#
-DQS5
93
DQS5
92
DQS5#
-DQS6
105
DQS6
104
DQS6#
-DQS7
114
DQS7
113
DQS7#
46
DQS8
45
DQS8#
188
A0
183
A1
63
A2
182
A3
61
A4
60
A5
180
A6
58
A7
179
A8
177
A9
70
A10_AP
57
A11
176
A12
196
A13
174
A14
173
A15
54
A16/BA2
DM0/DQS9
NC/DQS9#
DM1/DQS10
NC/DQS10#
DM2/DQS11
NC/DQS11#
DM3/DQS12
NC/DQS12#
DM4/DQS13
NC/DQS13#
DM5/DQS14
NC/DQS14#
DM6/DQS15
NC/DQS15#
DM7/DQS16
NC/DQS16#
DM8/DQS17
NC/DQS17#
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
VSS
VSS
VSS
VSS
VSS
VSS
219
222
225
228
231
234
190
BA1
71
BA0
73
WE#
74
CAS#
192
RAS#
125
126
134
135
146
147
155
156
202
203
211
212
223
224
232
233
164
165
195
ODT0
77
ODT1
52
CKE0
171
CKE1
193
CS0#
76
CS1#
185
186
137
138
220
221
120
SCL
119
SDA
1
VREF
VCC_DDR
239
SA0
240
SA1
101
SA2
VSS
VSS
DDRII-240_blue-RH
DDRII-240_blue-RH
237
BA1
BA0
-SWEA
-SCASA
-SRASA
-DQM0
-DQM1
-DQM2
-DQM3
-DQM4
-DQM5
-DQM6
-DQM7
ODT2
ODT3
CKEA2
CKEA3
-CS2
-CS3
MDCLKA3
MDCLKA#3
MDCLKA4
MDCLKA#4
MDCLKA5
MDCLKA#5
SMBCLK_DDR
SMBDATA_DDR
DIMM_VREF_A
-DQS0 {8}
-DQS1 {8}
-DQS2 {8}
-DQS3 {8}
-DQS4 {8}
-DQS5 {8}
-DQS6 {8}
-DQS7 {8}
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
PLACE CLOSE TO DIMM PIN
ADDRESS: 001
0xA2
BA1 {8,12}
BA0 {8,12}
-SWEA {8,12}
-SCASA {8,12}
-SRASA {8,12}
ODT2 {8,12}
ODT3 {8,12}
CKEA2 {8,12}
CKEA3 {8,12}
-CS2 {8,12}
-CS3 {8,12}
MDCLKA3 {21}
MDCLKA#3 {21}
MDCLKA4 {21}
MDCLKA#4 {21}
MDCLKA5 {21}
MDCLKA#5 {21}
C378
C378
C0.1U16Y0402
C0.1U16Y0402
MAA[0:13] {8,12}MAA[0:13] {8,12}
VCC_DDR
-DQM[0:7] {8}
DDR2 DIMM2
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
DDR II DIMM 1 & 2
DDR II DIMM 1 & 2
DDR II DIMM 1 & 2
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet
Date: Sheet
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7259 0A
MS-7259 0A
MS-7259 0A
VCC_DDR
VCC_DDR
+
+
.CD1000U6.3EL15
.CD1000U6.3EL15
1
C313
C313
C1U16Y
C1U16Y
C314
C314
X_C1U16Y
X_C1U16Y
C315
C315
C1U16Y
C1U16Y
C316
C316
X_C1U16Y
X_C1U16Y
C317
C317
C1U16Y
C1U16Y
C318
C318
X_C1U16Y
X_C1U16Y
C319
C319
C1U16Y
C1U16Y
C320
C320
X_C1U16Y
X_C1U16Y
11 34Thursday, December 15, 2005
11 34Thursday, December 15, 2005
11 34Thursday, December 15, 2005
1
C321
C321
C1U16Y
C1U16Y
C322
C322
X_C1U16Y
X_C1U16Y
C323
C323
C1U16Y
C1U16Y
C324
C324
X_C1U16Y
X_C1U16Y
C325
C325
C1U16Y
C1U16Y
C326
C326
X_C1U16Y
X_C1U16Y
C327
C327
C1U16Y
C1U16Y
C328
C328
X_C1U16Y
X_C1U16Y
EC34
EC34
of
of
of
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