MSI MS-7252 Schematics
5
4
3
2
1
MSI
MS-7252 Ver:100
CPU:
D D
AMD 940 Athlon 64/Athlon 64 FX
System Chipset:
Title Page
Cover Sheet 1
Block Diagram
AMD AM2 940
System Memory
DDR Terminations
2
3,4,5
6,7
8
NVIDIA C51PV / C51PVG
C51PV 9-11
NVIDIA MCP51 / MCP51G
MCP51 12-15
On Board Chipset:
LPC Super I/O -- W83627EHF / DHF
LAN -- RTL8201CL
IEEE1394 - VT6307 / VT6308
PCI Slot 1,2
PCI-E X16 , X1 Slot
LPC -W83627EHF / FDD / BIOS
16
17
18
AC97 Codec --ALC883
BIOS --LPC FLASH ROM 4M
LAN VSC8201 / RTL8201CL
Azalia CODEC & Interanl SPK
C C
Main Memory:
1394 Controller-VT6307
19
20
21
DDR * 4 (Max 4GB)
22
23
24
25
26
Expansion Slots:
PCI-E X1 *1
PCI-E X 16 *1
PCI 2.2 Slot * 2
USB connectors
MS-6 ACPI Controller & MS-6+
PWM - ISL6566CR
IDE &FDD & FAN
ATX Connector / Front Panel
27KB/MS/LPT/COM/TPM/EMI
PWM:
Controller--Intersil ISL6566CR 3 Phase
TV-OUT
VGA / DVI
MANUAL PARTS
B B
GPIO SPEC
POWER OK MAP
POWER MAP
RESET MAP
History
A A
28
29
30
31
32
33
34
35
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
Cover Sheet
Cover Sheet
Cover Sheet
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
1
Friday, March 10, 2006
Friday, March 10, 2006
Friday, March 10, 2006
1 35
1 35
1 35
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
4
3
2
1
BLOCK DIAGRAM
D D
POWER
SUPPLY
CONNECTOR
PEX X16, PEX X1
VREG
PCI EXPRESS
SOCKET 940
K9
HT 16X16 1GHZ
NFORCE
CRUSH 51
128-BIT 400/533MHZ
DDR SDRAM CONN 0
DDR SDRAM CONN 2
DDR SDRAM CONN 1
DDR SDRAM CONN3
VGA CONN
468 BGA
C C
HT 8X8 1GHZ
PCI 33MHZ
ATA 133
PRIMARY IDE
SECONDARY IDE
NFORCE
MCP 51
508 BGA
AZAILIA/AC97
Realtek ALC 883 (Azalia, 7.1Channel)
X8 USB2
1394-VT6307
PCI SLOT 1
PCI SLOT 2
PCI Extender
X4 - SATA CONN
FLOPPY CONN
B B
A A
PS2/KBRD CONN
PARALLEL CONN
SERIAL CONN
SERIAL HDR
INTEGRATED SATA 1/2
SIO
LPC SUPER I/O
47M997
LPC BUS 33MHZ
LPC HDR
4MB FLASH
Realtek 8201CL
BACK PANEL CONN
USB2 PORTS 0-1
DOUBLE STACK
USB2 PORTS 2-3
X2/GBIT LAN
FRONT PANEL HDR
USB2 PORTS 4-5
USB2 PORTS 6-7
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
Block Diagram
Block Diagram
Block Diagram
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
1
Friday, March 10, 2006
Friday, March 10, 2006
Friday, March 10, 2006
2
2
2
Rev
Rev
Rev
0A
0A
0A
35
35
35
of
of
of
5
4
3
2
1
VDDA_25 VDDA25
L1 80L3_100_0805L1 80L3_100_0805
2 1
C57
C4.7U16Y1206
C4.7U16Y1206
VCC_DDR
COREFB+24
COREFB-24
TP1TP1
TP8TP8
TP10TP10
TP11TP11
TP7TP7
TP17TP17
C57
LDT_RST_L
TP2TP2
CPU1A
CPU1A
HYPERTRANSPORT
D D
VCC1_2HT
C C
HT_CLKIN_H19
HT_CLKIN_L19
HT_CLKIN_H09
HT_CLKIN_L09
R107 51R1%0402-LFR107 51R1%0402-LF
R106 51R1%0402-LFR106 51R1%0402-LF
HT_CTLIN_H09
HT_CTLIN_L09
HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0
N6
L0_CLKIN_H(1)
P6
L0_CLKIN_L(1)
N3
L0_CLKIN_H(0)
N2
L0_CLKIN_L(0)
V4
L0_CTLIN_H(1)
V5
L0_CTLIN_L(1)
U1
L0_CTLIN_H(0)
V1
L0_CTLIN_L(0)
U6
L0_CADIN_H(15)
V6
L0_CADIN_L(15)
T4
L0_CADIN_H(14)
T5
L0_CADIN_L(14)
R6
L0_CADIN_H(13)
T6
L0_CADIN_L(13)
P4
L0_CADIN_H(12)
P5
L0_CADIN_L(12)
M4
L0_CADIN_H(11)
M5
L0_CADIN_L(11)
L6
L0_CADIN_H(10)
M6
L0_CADIN_L(10)
K4
L0_CADIN_H(9)
K5
L0_CADIN_L(9)
J6
L0_CADIN_H(8)
K6
L0_CADIN_L(8)
U3
L0_CADIN_H(7)
U2
L0_CADIN_L(7)
R1
L0_CADIN_H(6)
T1
L0_CADIN_L(6)
R3
L0_CADIN_H(5)
R2
L0_CADIN_L(5)
N1
L0_CADIN_H(4)
P1
L0_CADIN_L(4)
L1
L0_CADIN_H(3)
M1
L0_CADIN_L(3)
L3
L0_CADIN_H(2)
L2
L0_CADIN_L(2)
J1
L0_CADIN_H(1)
K1
L0_CADIN_L(1)
J3
L0_CADIN_H(0)
J2
L0_CADIN_L(0)
HYPERTRANSPORT
L0_CLKOUT_H(1)
L0_CLKOUT_L(1)
L0_CLKOUT_H(0)
L0_CLKOUT_L(0)
L0_CTLOUT_H(1)
L0_CTLOUT_L(1)
L0_CTLOUT_H(0)
L0_CTLOUT_L(0)
L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)
L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)
L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)
AD5
AD4
AD1
AC1
Y6
W6
W2
W3
Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4
Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1
HT_CLKOUT_H1 9
HT_CLKOUT_L1 9
HT_CLKOUT_H0 9
HT_CLKOUT_L0 9
HT_CTLOUT_H0 9
HT_CTLOUT_L0 9
HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8
HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0
TP15TP15
TP14TP14
CPU_CLK9
CPU_CLK#9
C66 C3900P50XC66 C3900P50X
_169R1%-1
_169R1%-1
C65 C3900P50XC65 C3900P50X
VCC_DDR
R104
R104
39.2R1%
39.2R1%
R103
R103
39.2R1%
39.2R1%
R68
R68
C38
C38
X_C1000P50X0402
X_C1000P50X0402
CPU_STRAP_HI_E11
CPU_STRAP_LO_F11
CPU_M_VREF
TP3TP3
R56 300RR56 300R
R53 300RR53 300R
TP4TP4
SM_THERMDC18,25
SM_THERMDA18,25
CPU_SIC18
CPU_SID18
TP26TP26
TP27TP27
TP28TP28
TP30TP30
TP24TP24
C73
C73
C0.22U16X
C0.22U16X
R94 300R1%R94 300R1%
R102 300R1%R102 300R1%
TP13TP13
VDDA25
C69
C69
C3300P50X
C3300P50X
CPUCLKIN
CPUCLKIN#
CPU_PWRGD_L
HT_STOP_L
CPU_PRESENT_L
CPU_SIC
CPU_SID
CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS
CPU_DBREQ_L
COREFB+
COREFBCPU_VTT_SENSE
CPU_TEST25_H
CPU_TEST25_L
C10
VDDA1
D10
VDDA2
A8
CLKIN_H
B8
CLKIN_L
C9
PWROK
D8
LDTSTOP_L
C7
RESET_L
AL3
CPU_PRESENT_L
AL6
SIC
AK6
SID
AL10
TDI
AJ10
TRST_L
AH10
TCK
AL9
TMS
A5
DBREQ_L
G2
VDD_FB_H
G1
VDD_FB_L
E12
VTT_SENSE
F12
M_VREF
AH11
M_ZN
AJ11
M_ZP
A10
TEST25_H
B10
TEST25_L
F10
TEST19
E9
TEST18
AJ7
TEST13
F6
TEST9
D6
TEST17
E7
TEST16
F8
TEST15
C5
TEST14
AH9
TEST12
E5
TEST7
AJ5
TEST6
AG9
TEST5
AG8
TEST4
AH7
TEST3
AJ6
TEST2
CPU1D
CPU1D
MISC
MISC
THERMTRIP_L
PROCHOT_L
DBRDY
VDDIO_FB_H
VDDIO_FB_L
HTREF1
HTREF0
TEST29_H
TEST29_L
TEST24
TEST23
TEST22
TEST21
TEST20
TEST28_H
TEST28_L
TEST27
TEST26
TEST10
TEST8
VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)
TDO
PSI_L
D2
D1
C1
E3
E2
E1
AK7
AL7
AK10
B6
AK11
AL11
F1
V8
V7
C11
D11
AK8
AH8
AJ9
AL8
AJ8
J10
H9
AK9
AK5
G7
D4
VID4
VID3
VID2
VID1
VID0
CPU_THRIP_L
CPU_TDO
CPU_DBRDY
VDDIO_FB_H
CPU_PSI_L
R101 300RR101 300R
TP9TP9
R95 300RR95 300R
TP25TP25
TP29TP29
VDDIO_FB_H 23
TP12TP12
R61 80.6R1%R61 80.6R1%
VCC_DDR
VCC_DDR
C1000P50X0402
C1000P50X0402
TP20TP20
TP18TP18
TP19TP19
TP16TP16
R19
R19
300R
300R
C163
C163
VCC_DDR
R96
R96
300R
300R
C164
C164
C1000P50X0402
C1000P50X0402
R99 44.2R1%R99 44.2R1%
R100 44.2R1%R100 44.2R1%
VID[0..4] 18,24
VCC1_2HT
B B
A A
HT_CADIN_H[15..0]9
HT_CADIN_L[15..0]9
HT_CADOUT_H[15..0]9
HT_CADOUT_L[15..0]9
CPU_PRESENT_L
CPU_TEST25_H
CPU_TEST25_L
VCC_DDR
_15R1%0805-1
_15R1%0805-1
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
R109 1KR0402R109 1KR0402
R65 510RR65 510R
R67 510RR67 510R
R62
R62
_15R1%0805-1
_15R1%0805-1
C75
C75
R63
R63
C0.1U16Y0402
C0.1U16Y0402
5
CPU_M_VREF
VCC_DDR
C70
C70
C1000P50X0402
C1000P50X0402
TP31TP31
AMD RECOMMAND
VCC1_2HT
C165
C165
C4.7U10Y0805
C4.7U10Y0805
X_C4.7U10Y0805
X_C4.7U10Y0805
HDT_LDT_RST#
C213
C213
X_C4.7U10Y0805
X_C4.7U10Y0805
4
VCC3
R585
R585
X_300R
X_300R
Q60
Q60
X_N-2N7002_SOT23
X_N-2N7002_SOT23
C166
C166
C0.22U16X
C0.22U16X
VDDA25
C183
C183
X_C0.22U16X
X_C0.22U16X
LDT_RST_L
C221
C221
C219
C219
X_C10P25N0402/0.25
X_C10P25N0402/0.25
X_C10P25N0402/0.25
X_C10P25N0402/0.25
C188
C188
VCC_DDR
52
V
HT_STOP#9
LDT_RST9
CPU_PWRGD9
3
HT_STOP#
LDT_RST
CPU_PWRGD
CPU_THRIP_L
V
1 6
G
G
VCC_DDR
52
V
V
3 4
G
G
VCC_DDR
52
V
V
1 6
G
G
VCC_DDR
52
V
V
3 4
G
G
HT_STOP_L
U30A
U30A
NC7WZ07_SC70-6
NC7WZ07_SC70-6
LDT_RST_L
U30B
U30B
NC7WZ07_SC70-6
NC7WZ07_SC70-6
CPU_PWRGD_L
U31A
U31A
NC7WZ07_SC70-6
NC7WZ07_SC70-6
CPU_THRIP#
U31B
U31B
NC7WZ07_SC70-6
NC7WZ07_SC70-6
2
CPU_THRIP# 12
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
HT Bus Level shift
VDDA25
VCC_DDR
LDT_RST_L
CPU_PWRGD_L
CPU_THRIP_L
HT_STOP_L
X_8P4R-0R
X_8P4R-0R
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
ATHLON64 HT I/F CTRL & DEBUG
ATHLON64 HT I/F CTRL & DEBUG
ATHLON64 HT I/F CTRL & DEBUG
RN8
RN8
1
2
3
4
5
6
7
8
8P4R-1KR
8P4R-1KR
RN48
RN48
1
2
3
4
5
6
7
8
8P4R-300R
8P4R-300R
RN2
RN2
1
2
3
4
5
6
7
8
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
1
LDT_RST
CPU_PWRGD
CPU_THRIP#
HT_STOP#
HT_STOP_L
CPU_THRIP_L
CPU_PWRGD_L
LDT_RST_L
LDT_RST
CPU_PWRGD
CPU_THRIP#
HT_STOP#
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
of
3 35
of
3 35
of
3 35
Rev
Rev
Rev
0A
0A
0A
5
MEM_MA_DQS_L[7..0]6,7
MEM_MA_DQS_H[7..0]6,7
MEM_MA_DM[7..0]6,7
D D
MEMORY INTERFACE A
MEM_MA0_CLK_H26,8
MEM_MA0_CLK_L26,8
MEM_MA0_CLK_H16,8
MEM_MA0_CLK_L16,8
MEM_MA0_CLK_H06,8
MEM_MA0_CLK_L06,8
MEM_MA0_CS_L16,8
MEM_MA0_CS_L06,8
MEM_MA0_ODT06,8
MEM_MA1_CLK_H27,8
MEM_MA1_CLK_L27,8
MEM_MA1_CLK_H17,8
MEM_MA1_CLK_L17,8
MEM_MA1_CLK_H07,8
MEM_MA1_CLK_L07,8
MEM_MA1_CS_L17,8
MEM_MA1_CS_L07,8
MEM_MA1_ODT07,8
C C
MEM_MA_ADD[15..0]6,7,8
B B
MEM_MA_CAS_L6,7,8
MEM_MA_WE_L6,7,8
MEM_MA_RAS_L6,7,8
MEM_MA_BANK26,7,8
MEM_MA_BANK16,7,8
MEM_MA_BANK06,7,8
MEM_MA_CKE17,8
MEM_MA_CKE06,8
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CS_L1
MEM_MA0_CS_L0
MEM_MA0_ODT0
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_CS_L1
MEM_MA1_CS_L0
MEM_MA1_ODT0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0
MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0
AG21
AG20
G19
H19
U27
U26
AC25
AA24
AC28
AE20
AE19
G20
G21
V27
W27
AD27
AA25
AC27
AB25
AB27
AA26
N25
Y27
AA27
L27
M25
M27
N24
AC26
N26
P25
Y25
N27
R24
P27
R25
R26
R27
T25
U25
T27
W24
AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28
D29
C29
C25
D25
E19
F19
F15
G15
AF15
AF19
AJ25
AH29
B29
E24
E18
H15
MEMORY INTERFACE A
MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)
MA0_CS_L(1)
MA0_CS_L(0)
MA0_ODT(0)
MA1_CLK_H(2)
MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)
MA1_CS_L(1)
MA1_CS_L(0)
MA1_ODT(0)
MA_CAS_L
MA_WE_L
MA_RAS_L
MA_BANK(2)
MA_BANK(1)
MA_BANK(0)
MA_CKE(1)
MA_CKE(0)
MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)
MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)
MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)
CPU1B
CPU1B
4
MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)
MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)
MA_DQS_H(8)
MA_DQS_L(8)
MA_DM(8)
MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)
AE14
AG14
AG16
AD17
AD13
AE13
AG15
AE16
AG17
AE18
AD21
AG22
AE17
AF17
AF21
AE21
AF23
AE23
AJ26
AG26
AE22
AG23
AH25
AF25
AJ28
AJ29
AF29
AE26
AJ27
AH27
AG29
AF27
E29
E28
D27
C27
G26
F27
C28
E27
F25
E25
E23
D23
E26
MEM_MA_DATA18
C26
MEM_MA_DATA17
G23
MEM_MA_DATA16
F23
MEM_MA_DATA15
E22
MEM_MA_DATA14
E21
MEM_MA_DATA13
F17
MEM_MA_DATA12
G17
MEM_MA_DATA11
G22
MEM_MA_DATA10
F21
G18
E17
G16
E15
G13
H13
H17
E16
E14
G14
MEM_MA_DQS_H8
J28
MEM_MA_DQS_L8
J27
J25
K25
J26
G28
G27
L24
K27
H29
H27
MEM_MA_DATA63
MEM_MA_DATA62
MEM_MA_DATA61
MEM_MA_DATA60
MEM_MA_DATA59
MEM_MA_DATA58
MEM_MA_DATA57
MEM_MA_DATA56
MEM_MA_DATA55
MEM_MA_DATA54
MEM_MA_DATA53
MEM_MA_DATA52
MEM_MA_DATA51
MEM_MA_DATA50
MEM_MA_DATA49
MEM_MA_DATA48
MEM_MA_DATA47
MEM_MA_DATA46
MEM_MA_DATA45
MEM_MA_DATA44
MEM_MA_DATA43
MEM_MA_DATA42
MEM_MA_DATA41
MEM_MA_DATA40
MEM_MA_DATA39
MEM_MA_DATA38
MEM_MA_DATA37
MEM_MA_DATA36
MEM_MA_DATA35
MEM_MA_DATA34
MEM_MA_DATA33
MEM_MA_DATA32
MEM_MA_DATA31
MEM_MA_DATA30
MEM_MA_DATA29
MEM_MA_DATA28
MEM_MA_DATA27
MEM_MA_DATA26
MEM_MA_DATA25
MEM_MA_DATA24
MEM_MA_DATA23
MEM_MA_DATA22
MEM_MA_DATA21
MEM_MA_DATA20
MEM_MA_DATA19
MEM_MA_DATA9
MEM_MA_DATA8
MEM_MA_DATA7
MEM_MA_DATA6
MEM_MA_DATA5
MEM_MA_DATA4
MEM_MA_DATA3
MEM_MA_DATA2
MEM_MA_DATA1
MEM_MA_DATA0
MEM_MA_DM8
MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0
MEM_MA_DATA[63..0] 6,7
MEM_MA_DQS_H8 6,7
MEM_MA_DQS_L8 6,7
MEM_MA_DM8 6,7
3
MEM_MB_DQS_L[7..0]6,7
MEM_MB_DQS_H[7..0]6,7
MEM_MB_DM[7..0]6,7
MEM_MB0_CLK_H26,8
MEM_MB0_CLK_L26,8
MEM_MB0_CLK_H16,8
MEM_MB0_CLK_L16,8
MEM_MB0_CLK_H06,8
MEM_MB0_CLK_L06,8
MEM_MB0_CS_L16,8
MEM_MB0_CS_L06,8
MEM_MB0_ODT06,8
MEM_MB1_CLK_H27,8
MEM_MB1_CLK_L27,8
MEM_MB1_CLK_H17,8
MEM_MB1_CLK_L17,8
MEM_MB1_CLK_H07,8
MEM_MB1_CLK_L07,8
MEM_MB1_CS_L17,8
MEM_MB1_CS_L07,8
MEM_MB1_ODT07,8
MEM_MB_CAS_L6,7,8
MEM_MB_WE_L6,7,8
MEM_MB_RAS_L6,7,8
MEM_MB_BANK26,7,8
MEM_MB_BANK16,7,8
MEM_MB_BANK06,7,8
MEM_MB_CKE17,8
MEM_MB_CKE06,8
MEM_MB_ADD[15..0]6,7,8
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CS_L1
MEM_MB0_CS_L0
MEM_MB0_ODT0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CS_L1
MEM_MB1_CS_L0
MEM_MB1_ODT0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0
MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0
AJ19
AK19
A18
A19
U31
U30
AE30
AC31
AD29
AL19
AL18
C19
D19
W29
W28
AE29
AB31
AD31
AC29
AC30
AB29
N31
AA31
AA28
M31
M29
N28
N29
AE31
N30
P29
AA29
P31
R29
R28
R31
R30
T31
T29
U29
U28
AA30
AK13
AJ13
AK17
AJ17
AK23
AL23
AL28
AL29
D31
C31
C24
C23
D17
C17
C14
C13
AJ14
AH17
AJ23
AK29
C30
A23
B17
B13
2
MEMORY INTERFACE B
MEMORY INTERFACE B
MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)
MB0_CS_L(1)
MB0_CS_L(0)
MB0_ODT(0)
MB1_CLK_H(2)
MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)
MB1_CS_L(1)
MB1_CS_L(0)
MB1_ODT(0)
MB_CAS_L
MB_WE_L
MB_RAS_L
MB_BANK(2)
MB_BANK(1)
MB_BANK(0)
MB_CKE(1)
MB_CKE(0)
MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)
MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)
MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)
CPU1C
CPU1C
MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)
MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)
MB_DQS_H(8)
MB_DQS_L(8)
MB_DM(8)
MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)
AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13
J31
J30
J29
K29
K31
G30
G29
L29
L28
H31
G31
MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20
MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10
MEM_MB_DATA9
MEM_MB_DATA8
MEM_MB_DATA7
MEM_MB_DATA6
MEM_MB_DATA5
MEM_MB_DATA4
MEM_MB_DATA3
MEM_MB_DATA2
MEM_MB_DATA1
MEM_MB_DATA0
MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DM8
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
1
MEM_MB_DQS_H8 6,7
MEM_MB_DQS_L8 6,7
MEM_MB_DM8 6,7
MEM_MB_DATA[63..0] 6,7
MEM_MA_CHECK[7..0] 6,7
A A
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
5
4
3
2
http://www.msi.com.tw
ATHLON64 DDR MEMORY I/F
ATHLON64 DDR MEMORY I/F
ATHLON64 DDR MEMORY I/F
MEM_MB_CHECK[7..0] 6,7
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Sheet
Sheet
Sheet
1
of
4 35
of
4 35
of
4 35
Rev
Rev
Rev
0A
0A
0A
5
VCCP
CPU1F
CPU1F
VDD1
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD37
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD150
VDD151
VDD1
A4
A6
AA8
VTT_DDR
AA10
AA12
AA14
AA16
AA18
AB7
AB9
AB11
AC4
AC5
AC8
AC10
AD2
AD3
AD7
AD9
AE10
AF7
AF9
AG4
AG5
AG7
AH2
AH3
B3
B5
B7
C2
C4
C6
C8
D3
D5
D7
D9
E4
E6
E8
E10
F5
F7
F9
F11
G6
G8
G10
G12
H7
H11
H23
J12
J14
J16
J18
J20
J22
J24
K7
K9
K11
K13
K15
K17
K19
K21
K23
L4
L5
L8
L10
L12
Y17
Y19
J8
D D
C C
B B
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS240
VSS241
A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16
VCCP
L14
L16
L18
M2
M3
M7
M9
M11
M13
M15
M17
M19
N8
N10
N12
N14
N16
N18
P7
P9
P11
P13
P15
P17
P19
R4
R5
R8
R10
R12
R14
R16
R18
R20
T11
T13
T15
T17
T19
T21
U8
U10
U12
U14
U16
U18
U20
V9
V11
V13
V15
V17
V19
V21
W4
W5
W8
W10
W12
W14
W16
W18
W20
Y2
Y3
Y7
Y9
Y11
Y13
Y15
Y21
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
T2
VDD35
T3
VDD36
T7
VDD37
T9
VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
4
CPU1G
CPU1G
VDD2
VDD2
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18
VCC_DDR
VCCP
AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11
L20
L22
M21
M23
N20
N22
P21
P23
R22
T23
U22
V23
W22
Y23
5
6
7
8
1
2
3
4
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
GND
GND
GND
GND
GND
GND
GND
GND
CPU1H
CPU1H
VDD3
VDD3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22
3
VCC_DDR
VCCP
VCC1_2HT
VTT_DDR
AJ4
AJ3
AJ2
AJ1
D12
C12
B12
A12
AB24
AB26
AB28
AB30
AC24
AD26
AD28
AD30
AF30
M24
M26
M28
M30
P24
P26
P28
P30
T24
T26
T28
T30
V25
V26
V28
V30
Y24
Y26
Y28
Y29
VLDT_A1
VLDT_A2
VLDT_A3
VLDT_A4
VTT1
VTT2
VTT3
VTT4
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
CPU1I
CPU1I
VDDIO
VDDIO
0603
C564
C564
C0.22U16X
C0.22U16X
C575
C575
C0.22U16X
C0.22U16X
C571
C571
C0.22U16X
C0.22U16X
2
VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4
VTT5
VTT6
VTT7
VTT8
VTT9
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
C547
C547
C0.01U25X0402
VLDT_RUN_B
H6
H5
H2
VTT_DDR
H1
AK12
AJ12
AH12
AG12
AL12
K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15
0603
C548
C548
X_C10P25N0402/0.25
X_C10P25N0402/0.25
C94
C94
C4.7U16Y1206
C4.7U16Y1206
GND 3,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
VCC1_2HT
C784
C784
C180P50N0402
C180P50N0402
VCCP
C777
C777
C180P50N
C180P50N
VCC_DDR
C781
C22U6.3X1206
C22U6.3X1206
C558
C558
C60
C60
X_10U/1206
X_10U/1206
C781
C180P50N0402
C180P50N0402
VCC_DDR
C780
C780
C180P50N0402
C180P50N0402
C180P50N0402
C180P50N0402
VTT_DDR
C785
C785
C180P50N0402
C180P50N0402
C180P50N0402
C180P50N0402
AMD RECOMMAND
for EMI containment.
C561
C561
X_10U/1206
X_10U/1206
C789
C789
C180P50N0402
C180P50N0402
C787
C787
C180P50N0402
C180P50N0402
C783
C783
C180P50N0402
C180P50N0402
X_10U/1206
X_10U/1206C0.01U25X0402
1
C782
C782
C180P50N0402
C180P50N0402
C788
C788
C786
C786
C90
C90
C778
C778
C180P50N0402
C180P50N0402
C779
C779
C180P50N0402
C180P50N0402
C563
C563
X_10U/1206
X_10U/1206
10U/1206
10U/1206
C136
C136
C259
C34
C68
C42
C42
C0.22U16X
C0.22U16X
A A
VTT_DDR
C189
C189
C0.22U16X
C0.22U16X
C68
C0.22U16X
C0.22U16X
C192
C192
C0.22U16X
C0.22U16X
C34
C4.7U10Y0805
C4.7U10Y0805
X_C4.7U10Y0805
X_C4.7U10Y0805
C201
C201
C4.7U10Y0805
C4.7U10Y0805
5
C36
C36
X_C10P50N0402
X_C10P50N0402
C203
C203
X_C10P50N0402
X_C4.7U10Y0805
X_C4.7U10Y0805
X_C10P50N0402 C0.22U16X
C50
C50
X_C10P50N0402
X_C10P50N0402
C194
C194
X_C10P50N0402
X_C10P50N0402
C39
C39
C169
C169
X_C1000P50X0402
X_C1000P50X0402
C74
C74
X_C1000P50X0402
X_C1000P50X0402
X_C1000P50X0402
X_C1000P50X0402
C160
C160
X_C1000P50X0402
X_C1000P50X0402 C0.22U16X
C53
C53
C187
C187
4
C551
C551
C0.22U16X
C0.22U16X
VCC_DDR
C562
C562
X_C22U6.3X1206
X_C22U6.3X1206
C0.22U16X
C0.22U16X
10U/1206
10U/1206
C559
C559
C0.22U16X
C0.22U16X
C567
C567
C4.7U10Y0805
C4.7U10Y0805
C224
C224
C102
C102
C4.7U10Y0805
C4.7U10Y0805
C259
C4.7U10Y0805
C4.7U10Y0805
C87
C87
C76
C76
C4.7U10Y0805
C4.7U10Y0805
C555
C555
C0.22U16X
C179
C179
C0.22U16X
C97
C97
C0.22U16X
C0.22U16X
3
C0.01U25X0402
C0.01U25X0402
VCCP
C557
C557
X_10U/1206
X_10U/1206
C574
C574
X_C10P25N0402/0.25
X_C10P25N0402/0.25
C269
C269
C556
C556
X_10U/1206
X_10U/1206
C560
C560
X_10U/1206
X_10U/1206
C552
C552
X_10U/1206
X_10U/1206
2
C554
C554
10U/1206
10U/1206
C553
C553
10U/1206
10U/1206
C570
C570
10U/1206
10U/1206
10U/1206
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
10U/1206
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
ATHLON64 PWR & GND
ATHLON64 PWR & GND
ATHLON64 PWR & GND
C550
C550
MS-7252H1
MS-7252H1
MS-7252H1
1
C549
C549
X_10U/1206
X_10U/1206
Last Revision Date:
Last Revision Date:
Last Revision Date:
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Sheet
Sheet
Sheet
5 35
5 35
5 35
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
4
3
2
1
MEM_MA_DQS_H[7..0]4,7
MEM_MA_DQS_L[7..0]4,7
D D
MEM_MA_DM84,7
MEM_MA_DM[7..0]4,7
MEM_MA_DQS_H84,7
MEM_MA_DQS_L84,7
C C
SMB_MEMCLK
SMB_MEM_CLK13
SMB_MEM_DATA13
MEM_MA_BANK24,7,8
MEM_MA_BANK14,7,8
MEM_MA_BANK04,7,8
MEM_MA_ADD[15..0]4,7,8
R192 33RR192 33R
R187 33RR187 33R
SMB_MEMDATA
VCC_DDR
172
VDD1
178
184
VDD2
187
VDD3
VDD4
189
197
VDD5
VDD6
64
VDD753VDD859VDD9
69
170
VDD1067VDD11
175
181
VDDQ1
VDDQ2
191
194
VDDQ3
VDDQ4
72
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VCC3
78
238
VDDQ1075VDDQ11
VDDSPD
DIMM1DIMM1
MEM_MA_DATA[63..0] 4,7
MEM_MB_DQS_H[7..0]4,7
MEM_MB_DQS_L[7..0]4,7
MEM_MB_DM84,7
MEM_MB_DM[7..0]4,7
MEM_MB_DQS_H84,7
MEM_MB_DQS_L84,7
VCC3
MEM_MB_BANK24,7,8
MEM_MB_BANK14,7,8
MEM_MB_BANK04,7,8
MEM_MB_ADD[15..0]4,7,8
VCC_DDR
172
VDD1
178
184
VDD2
VDD3
187
189
VDD4
197
VDD5
VDD6
64
VDD753VDD859VDD9
VDD1067VDD11
VCC3
69
170
175
181
191
194
72
78
238
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VDDQ1075VDDQ11
VDDSPD
MEM_MB_DATA[63..0] 4,7
SMB_MEMCLK
SMB_MEMDATA
SMB_MEM_CLK
SMB_MEMCLK 7
SMB_MEMDATA 7
3VDUAL
21
D18
D18
X_1PS226_SOT23
X_1PS226_SOT23
3VDUAL
SMB_MEM_DATA
B B
MEM_MA_CHECK[7..0]4,7
VDDR_VREF
MEM_MA0_CLK_H04,8
MEM_MA0_CLK_L04,8
MEM_MA0_CLK_H14,8
MEM_MA0_CLK_L14,8
MEM_MA0_CLK_H24,8
MEM_MA0_CLK_L24,8
MEM_MA_CKE04,8
MEM_MA_RAS_L4,7,8
MEM_MA_CAS_L4,7,8
A A
MEM_MA0_CS_L04,8
MEM_MA0_CS_L14,8
MEM_MA_WE_L 4,7,8
MEM_MA0_ODT0 4,8
VDDR_VREF
C52
C52
C0.1U16Y0402
C0.1U16Y0402
MEM_MB_CHECK[7..0]4,7
MEM_MB0_CLK_H04,8
MEM_MB0_CLK_L04,8
MEM_MB0_CLK_H14,8
MEM_MB0_CLK_L14,8
MEM_MB0_CLK_H24,8
MEM_MB0_CLK_L24,8
MEM_MB_CKE04,8
MEM_MB_RAS_L4,7,8
MEM_MB_CAS_L4,7,8
MEM_MB0_CS_L04,8
MEM_MB0_CS_L14,8
DIMM 3
ADDR=1010000B
5
4
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3 VDDR_VREF
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
DIMM 1
ADDR=1010001B
3
2
MEM_MB_WE_L 4,7,8
MEM_MB0_ODT0 4,8
VDDR_VREF
C63
C63
C0.1U16Y0402
C0.1U16Y0402
VCC_DDR VDDR_VREF
R55
R55
56.2R1%
56.2R1%
R66
R66
56.2R1%
56.2R1%
C0.1U16Y0402
C0.1U16Y0402
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
FIRST LOGICAL DDR DIMM
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
1
21
C43
C43
C0.1U16Y0402
C0.1U16Y0402
VDDR_VREF
C59
C59
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
D17
D17
X_1PS226_SOT23
X_1PS226_SOT23
C56
C56
C1000P50X0402
C1000P50X0402
Rev
Rev
Rev
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
of
6 35
of
6 35
of
6 35
0A
0A
0A
5
4
3
2
1
MEM_MA_DQS_H[7..0]4,6
MEM_MA_DQS_L[7..0]4,6
D D
MEM_MA_DM84,6
MEM_MA_DM[7..0]4,6
MEM_MA_DQS_H84,6
C C
MEM_MA_DQS_L84,6
VCC3
SMB_MEMCLK6
SMB_MEMDATA6
MEM_MA_BANK24,6,8
MEM_MA_BANK14,6,8
MEM_MA_BANK04,6,8
MEM_MA_ADD[15..0]4,6,8
VCC_DDR
172
VDD1
178
184
VDD2
187
VDD3
VDD4
189
197
VDD5
VDD6
VDD753VDD859VDD9
64
69
170
VDD1067VDD11
175
181
VDDQ1
VDDQ2
191
194
VDDQ3
VDDQ4
72
VDDQ5
VDDQ651VDDQ756VDDQ862VDDQ9
VCC3
78
238
VDDQ1075VDDQ11
VDDSPD
MEM_MA_DATA[63..0] 4,6
MEM_MB_DM[7..0]4,6
MEM_MB_DQS_L[7..0]4,6
MEM_MB_DQS_H[7..0]4,6
VCC_DDR
172
178
184
187
189
197
64
69
170
175
181
191
194
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD753VDD859VDD9
VDD1067VDD11
VDDQ1
VDDQ2
VDDQ3
VDDQ4
MEM_MB_DM84,6
MEM_MB_DQS_H84,6
MEM_MB_DQS_L84,6
VCC3
SMB_MEMCLK6
SMB_MEMDATA6
MEM_MB_BANK24,6,8
MEM_MB_BANK14,6,8
MEM_MB_BANK04,6,8
MEM_MB_ADD[15..0]4,6,8
VDDQ5
72
78
VDDQ651VDDQ756VDDQ862VDDQ9
VDDQ1075VDDQ11
VCC3
238
MEM_MB_DATA[63..0] 4,6
VDDSPD
B B
MEM_MA_CHECK[7..0]4,6
MEM_MA_WE_L 4,6,8
MEM_MA1_CLK_H04,8
MEM_MA1_CLK_L04,8
MEM_MA1_CLK_H14,8
MEM_MA1_CLK_L14,8
MEM_MA1_CLK_H24,8
MEM_MA1_CLK_L24,8
MEM_MA_CKE14,8
A A
MEM_MA_RAS_L4,6,8
MEM_MA_CAS_L4,6,8
MEM_MA1_CS_L04,8
MEM_MA1_CS_L14,8
MEM_MA1_ODT0 4,8
VDDR_VREF
C54
C54
C0.1U16Y0402
C0.1U16Y0402
DIMM 4
ADDR=1010010B
5
4
3
MEM_MB_CHECK[7..0]4,6
MEM_MB1_CLK_H04,8
MEM_MB1_CLK_L04,8
MEM_MB1_CLK_H14,8
MEM_MB1_CLK_L14,8
MEM_MB1_CLK_H24,8
MEM_MB1_CLK_L24,8
MEM_MB_CKE14,8
MEM_MB_RAS_L4,6,8
MEM_MB_CAS_L4,6,8
MEM_MB1_CS_L04,8
MEM_MB1_CS_L14,8
MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0
DIMM 2
ADDR=1010011B
2
MEM_MB_WE_L 4,6,8
MEM_MB1_ODT0 4,8
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
SECOND LOGICAL DDR DIMM
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
1
VDDR_VREF
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
C46
C46
C0.1U16Y0402
C0.1U16Y0402
Rev
Rev
Rev
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
of
7 35
of
7 35
of
7 35
0A
0A
0A
5
4
3
2
1
VTT_DDR
MEM_MA0_CLK_H24,6
MEM_MA_ADD[15..0]4,6,7
MEM_MB_ADD154,6,7
D D
C C
MEM_MB_ADD144,6,7
MEM_MB_BANK24,6,7
MEM_MA_ADD94,6,7
MEM_MA_ADD114,6,7
MEM_MB_ADD124,6,7
MEM_MB_ADD94,6,7
MEM_MA_ADD74,6,7
MEM_MA_ADD64,6,7
MEM_MB_ADD64,6,7
MEM_MB_ADD54,6,7
MEM_MA_ADD54,6,7
MEM_MB_ADD14,6,7
MEM_MB_ADD24,6,7
MEM_MA_ADD14,6,7
MEM_MA_ADD24,6,7
MEM_MB_ADD104,6,7
MEM_MB_BANK04,6,7
MEM_MB_RAS_L4,6,7
MEM_MB0_CS_L04,6
MEM_MA_BANK04,6,7
MEM_MB_BANK14,6,7
MEM_MA_RAS_L4,6,7
MEM_MA0_CS_L04,6
MEM_MA_ADD134,6,7
MEM_MB1_CS_L14,7
MEM_MA0_CS_L14,6
MEM_MA1_CS_L14,7
MEM_MB1_CS_L04,7
MEM_MB1_ODT04,7
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_BANK2
MEM_MA_ADD9
MEM_MA_ADD11
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MA_ADD5
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MB_ADD10
MEM_MB_BANK0
MEM_MB_RAS_L
MEM_MB0_CS_L0
MEM_MA_BANK0
MEM_MB_BANK1
MEM_MA_RAS_L
MEM_MA0_CS_L0
MEM_MA_ADD13
MEM_MB1_CS_L1
MEM_MA0_CS_L1
MEM_MA1_CS_L1
MEM_MB1_CS_L0
MEM_MB1_ODT0
RN15 8P4R-47R0402RN15 8P4R-47R0402
1
2
3
4
5
6
7
RN16 8P4R-47R0402RN16 8P4R-47R0402
RN18 8P4R-47R0402RN18 8P4R-47R0402
RN20 8P4R-47R0402RN20 8P4R-47R0402
RN24 8P4R-47R0402RN24 8P4R-47R0402
RN22 8P4R-47R0402RN22 8P4R-47R0402
RN28 8P4R-47R0402RN28 8P4R-47R0402
R108 47R0402R108 47R0402
R113 47R0402R113 47R0402
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
MEM_MA0_CLK_L24,6
MEM_MA0_CLK_H14,6
MEM_MA0_CLK_L14,6
MEM_MA0_CLK_H04,6
MEM_MA0_CLK_L04,6
MEM_MB0_CLK_H24,6
MEM_MB0_CLK_L24,6
MEM_MB0_CLK_H14,6
MEM_MB0_CLK_L14,6
MEM_MB0_CLK_H04,6
MEM_MB0_CLK_L04,6
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
C185
C185
C1.5P50N0402
C1.5P50N0402
C72
C72
C1.5P50N0402
C1.5P50N0402
C124
C124
C1.5P50N0402
C1.5P50N0402
C176
C176
C1.5P50N0402
C1.5P50N0402
C71
C71
C1.5P50N0402
C1.5P50N0402
C122
C122
C1.5P50N0402
C1.5P50N0402
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3 MEM_MB_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0
MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0
C565 C22P50N0402C565 C22P50N0402
C566 C22P50N0402C566 C22P50N0402
C590 C22P50N0402C590 C22P50N0402
C568 C22P50N0402C568 C22P50N0402
C573 C22P50N0402C573 C22P50N0402
C587 C22P50N0402C587 C22P50N0402
C572 C22P50N0402C572 C22P50N0402
C577 C22P50N0402C577 C22P50N0402
C576 C22P50N0402C576 C22P50N0402
C578 C22P50N0402C578 C22P50N0402
C580 C22P50N0402C580 C22P50N0402
C583 C22P50N0402C583 C22P50N0402
C579 C22P50N0402C579 C22P50N0402
C585 C22P50N0402C585 C22P50N0402
C581 C22P50N0402C581 C22P50N0402
C588 C22P50N0402C588 C22P50N0402
C589 C22P50N0402C589 C22P50N0402
C586 C22P50N0402C586 C22P50N0402
C584 C22P50N0402C584 C22P50N0402
C569 C22P50N0402C569 C22P50N0402
C591 C22P50N0402C591 C22P50N0402
C582 C22P50N0402C582 C22P50N0402
Decoupling Between Processor and DIMMs
VTT_DDR
C199
C199
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C193
C193
C0.1U16Y0402
C0.1U16Y0402
C173
C173
C0.1U16Y0402
C0.1U16Y0402
C156
C156
X_C0.1U16Y0402
X_C0.1U16Y0402
Layout: Spread out on VTT pour
C181
C181
C0.1U16Y0402
C0.1U16Y0402
C111
C111
C190
C190
X_C0.1U16Y0402
X_C0.1U16Y0402
C150
C150
X_C0.1U16Y0402
X_C0.1U16Y0402
MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7MEM_MA_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0
MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0
C130
C130
X_C0.1U16Y0402
X_C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C109 C22P50N0402C109 C22P50N0402
C110 C22P50N0402C110 C22P50N0402
C171 C22P50N0402C171 C22P50N0402
C116 C22P50N0402C116 C22P50N0402
C118 C22P50N0402C118 C22P50N0402
C161 C22P50N0402C161 C22P50N0402
C119 C22P50N0402C119 C22P50N0402
C132 C22P50N0402C132 C22P50N0402
C128 C22P50N0402C128 C22P50N0402
C133 C22P50N0402C133 C22P50N0402
C141 C22P50N0402C141 C22P50N0402
C148 C22P50N0402C148 C22P50N0402
C140 C22P50N0402C140 C22P50N0402
C152 C22P50N0402C152 C22P50N0402
C145 C22P50N0402C145 C22P50N0402
C162 C22P50N0402C162 C22P50N0402
C167 C22P50N0402C167 C22P50N0402
C158 C22P50N0402C158 C22P50N0402
C151 C22P50N0402C151 C22P50N0402
C115 C22P50N0402C115 C22P50N0402
C172 C22P50N0402C172 C22P50N0402
C147 C22P50N0402C147 C22P50N0402
C202
C202
C137
C137
C0.1U16Y0402
C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C159
C159
C0.1U16Y0402
C0.1U16Y0402
VCC_DDRVCC_DDR
C121
C121
C95
C95
X_C0.1U16Y0402
X_C0.1U16Y0402
C125
C125
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C112
C112
VTT_DDR
VCC_DDR
C108
C28
C28
C0.1U16Y0402
C0.1U16Y0402
C86
C0.1U16Y0402
C0.1U16Y0402
C77
C77
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
VTT_DDR
X_C10P50N0402
X_C10P50N0402
VCC_DDR
X_C10P50N0402
X_C10P50N0402
C241
C241
C0.1U16Y0402
C0.1U16Y0402
C223
C223
X_C10P50N0402
X_C10P50N0402
C242
C242
X_C10P50N0402
X_C10P50N0402
2
C250
C250
C0.1U16Y0402
C0.1U16Y0402
For EMI
C227
C227
X_C10P50N0402
X_C10P50N0402
C58
C58
X_C10P50N0402
X_C10P50N0402
C105
C105
C103
C103
C0.1U16Y0402
C0.1U16Y0402
MEM_MB_ADD[15..0]4,6,7
MEM_MB_CKE14,7
MEM_MB_CKE04,6
MEM_MA_BANK24,6,7
B B
A A
MEM_MA_ADD124,6,7
MEM_MA_ADD84,6,7
MEM_MB_ADD114,6,7
MEM_MB_ADD74,6,7
MEM_MB_ADD84,6,7
MEM_MB_ADD44,6,7
MEM_MB_ADD34,6,7
MEM_MA_ADD44,6,7
MEM_MA_ADD34,6,7
MEM_MA_ADD04,6,7
MEM_MA_ADD104,6,7
MEM_MB_ADD04,6,7
MEM_MA_BANK14,6,7
MEM_MB_WE_L4,6,7
MEM_MB_CAS_L4,6,7
MEM_MA_WE_L4,6,7
MEM_MA_CAS_L4,6,7
MEM_MA_CKE14,7
MEM_MA_CKE04,6
MEM_MA_ADD154,6,7
MEM_MA_ADD144,6,7
MEM_MA0_ODT04,6
MEM_MB0_ODT04,6
MEM_MB_ADD134,6,7
MEM_MB0_CS_L14,6
MEM_MA1_CS_L04,7
MEM_MA1_ODT04,7
MEM_MB_CKE1
MEM_MB_CKE0
MEM_MA_BANK2
MEM_MA_ADD12
MEM_MA_ADD8
MEM_MB_ADD11
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD0
MEM_MA_ADD10
MEM_MB_ADD0
MEM_MA_BANK1
MEM_MB_WE_L
MEM_MB_CAS_L
MEM_MA_WE_L
MEM_MA_CAS_L
MEM_MA_CKE1
MEM_MA_CKE0
MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA0_ODT0
MEM_MB0_ODT0
MEM_MB_ADD13
MEM_MB0_CS_L1
MEM_MA1_CS_L0
MEM_MA1_ODT0
RN14 8P4R-47R0402RN14 8P4R-47R0402
1
2
3
4
5
6
7
RN17 8P4R-47R0402RN17 8P4R-47R0402
RN19 8P4R-47R0402RN19 8P4R-47R0402
RN21 8P4R-47R0402RN21 8P4R-47R0402
RN26 8P4R-47R0402RN26 8P4R-47R0402
RN13 8P4R-47R0402RN13 8P4R-47R0402
RN27 8P4R-47R0402RN27 8P4R-47R0402
R105 47R0402R105 47R0402
R117 47R0402R117 47R0402
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
VTT_DDR
MEM_MA1_CLK_L24,7
MEM_MA1_CLK_H14,7
MEM_MA1_CLK_L14,7
MEM_MA1_CLK_H04,7
MEM_MA1_CLK_L04,7
MEM_MB1_CLK_H24,7
MEM_MB1_CLK_L24,7
MEM_MB1_CLK_H14,7
MEM_MB1_CLK_L14,7
MEM_MB1_CLK_H04,7
MEM_MB1_CLK_L04,7
MEM_MA1_CLK_H24,7
5
4
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
C186
C186
C1.5P50N0402
C1.5P50N0402
C61
C61
C1.5P50N0402
C1.5P50N0402
C129
C129
C1.5P50N0402
C1.5P50N0402
C180
C180
C1.5P50N0402
C1.5P50N0402
C67
C67
C1.5P50N0402
C1.5P50N0402
C127
C127
C1.5P50N0402
C1.5P50N0402
C0.1U16Y0402
3
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C29
C29
C86
C231
C231
C0.1U16Y0402
C0.1U16Y0402
C256
C256
X_C10P50N0402
X_C10P50N0402
C200
C200
C108
C0.1U16Y0402
C0.1U16Y0402
C26
C26
X_C10P50N0402
X_C10P50N0402
C254
C254
C262
C222
C222
C0.1U16Y0402
C0.1U16Y0402
C22
C22
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
C262
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
DDR Terminatior
DDR Terminatior
DDR Terminatior
C123
C123
C131
C131
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
1
C30
C30
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
of
8 35
of
8 35
of
8 35
Rev
Rev
Rev
0A
0A
0A
5
U13F
U13F
?
?
HT_CADOUT_H[15..0]3
D D
HT_CADOUT_L[15..0]3
C C
HT_CADOUT_H[15..0]
HT_CADOUT_L[15..0]
HT_CLKOUT_H03
HT_CLKOUT_L03
HT_CLKOUT_H13
HT_CLKOUT_L13
HT_CTLOUT_H03
HT_CTLOUT_L03
HT_CADOUT_H0
HT_CADOUT_H1
HT_CADOUT_H2
HT_CADOUT_H3
HT_CADOUT_H4
HT_CADOUT_H5
HT_CADOUT_H6
HT_CADOUT_H7
HT_CADOUT_H8
HT_CADOUT_H9
HT_CADOUT_H10
HT_CADOUT_H11
HT_CADOUT_H12
HT_CADOUT_H13
HT_CADOUT_H14
HT_CADOUT_H15
HT_CADOUT_L0
HT_CADOUT_L1
HT_CADOUT_L2
HT_CADOUT_L3
HT_CADOUT_L4
HT_CADOUT_L5
HT_CADOUT_L6
HT_CADOUT_L7
HT_CADOUT_L8
HT_CADOUT_L9
HT_CADOUT_L10
HT_CADOUT_L11
HT_CADOUT_L12
HT_CADOUT_L13
HT_CADOUT_L14
HT_CADOUT_L15
HT_CTLOUT_H0
HT_CTLOUT_L0
HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P
HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N
HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N
HT_CPU_RXCTL_P
HT_CPU_RXCTL_N
C51
C51
VCC1_2HT
R147 150R1%R147 150R1%
B B
1P2VPLL_PWR10,11
1P2VPLL_PWR
FB19 X_0RFB19 X_0R
R150 150R1%R150 150R1%
CP23
CP23
X_COPPER
X_COPPER
C1U10Y
C1U10Y
PLACE ON BACK SIDE
C598
C598
1P2VPLL_FILT
C600
C600
C0.1U16Y0402
C0.1U16Y0402
HT_CPU_CAL_1P2V
HT_CPU_CAL_GND
+1.2V_PLLHTCPU
+1.2V_PLLHTMCP
?
?
NVIDIA-C51-G-A1
NVIDIA-C51-G-A1
SEC 1 OF 6
SEC 1 OF 6
4
HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P
HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P
HT_CPU_TXD0_N
HT_CPU_TXD1_N
HT_CPU_TXD2_N
HT_CPU_TXD3_N
HT_CPU_TXD4_N
HT_CPU_TXD5_N
HT_CPU_TXD6_N
HT_CPU_TXD7_N
HT_CPU_TXD8_N
HT_CPU_TXD9_N
HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N
HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N
HT_CPU_TXCTL_P
HT_CPU_TXCTL_N
CLKOUT_PRI_200MHZ_P
CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N
HT_CPU_REQ*
HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD
+2.5V_PLLHTCPU
VCC2_5
HT_CADIN_H0
HT_CADIN_H1
HT_CADIN_H2
HT_CADIN_H3
HT_CADIN_H4
HT_CADIN_H5
HT_CADIN_H6
HT_CADIN_H7
HT_CADIN_H8
HT_CADIN_H9
HT_CADIN_H10
HT_CADIN_H11
HT_CADIN_H12
HT_CADIN_H13
HT_CADIN_H14
HT_CADIN_H15
HT_CADIN_L0
HT_CADIN_L1
HT_CADIN_L2
HT_CADIN_L3
HT_CADIN_L4
HT_CADIN_L5
HT_CADIN_L6
HT_CADIN_L7
HT_CADIN_L8
HT_CADIN_L9
HT_CADIN_L10
HT_CADIN_L11
HT_CADIN_L12
HT_CADIN_L13
HT_CADIN_L14
HT_CADIN_L15
HT_CLKIN_H0
HT_CLKIN_L0
HT_CLKIN_H1
HT_CLKIN_L1
HT_CTLIN_H0
HT_CTLIN_L0
2P5V_PLL
C244
HT_CADIN_H[15..0]
HT_CADIN_L[15..0]
HT_STOP#
LDT_RST
CPU_PWRGD
FB20 X_0RFB20 X_0R
C595
C595C244
CP24
CP24
X_COPPER
X_COPPER
HT_CADIN_H[15..0] 3
HT_CADIN_L[15..0] 3
HT_CLKIN_H0 3
HT_CLKIN_L0 3
HT_CLKIN_H1 3
HT_CLKIN_L1 3
HT_CTLIN_H0 3
HT_CTLIN_L0 3
CPU_CLK 3
CPU_CLK# 3
C597
C597
C1U10Y
C1U10Y
HT_STOP# 3
LDT_RST 3
CPU_PWRGD 3
2P5V_PLL
C599
C599
C0.1U16Y0402
C0.1U16Y0402
3
2P5V_PLL 10
2
U13A
U13A
?
?
HTMCP_UP[7..0]12
HTMCP_UP#[7..0]12
HTMCP_UPCNTL#12
MCPOUT_200MHZ#12
HTMCP_UP[7..0]
HTMCP_UP#[7..0]
HTMCP_UPCLK012
HTMCP_UPCLK0#12
HTMCP_UPCNTL12
HTMCP_REQ#12
HTMCP_STOP#12
HTMCP_RST#12
HTMCP_PWRGD12
MCPOUT_25MHZ12
MCPOUT_200MHZ12
HTMCP_UP0
HTMCP_UP1
HTMCP_UP2
HTMCP_UP3
HTMCP_UP4
HTMCP_UP5
HTMCP_UP6
HTMCP_UP7
HTMCP_UPCLK0
HTMCP_UPCLK0#
HTMCP_UPCNTL
HTMCP_UPCNTL#
HTMCP_REQ#
HTMCP_STOP#
HTMCP_RST#
HTMCP_PWRGD
MCPOUT_25MHZ
MCPOUT_200MHZ
MCPOUT_200MHZ#
HTMCP_UP#0
HTMCP_UP#1
HTMCP_UP#2
HTMCP_UP#3
HTMCP_UP#4
HTMCP_UP#5
HTMCP_UP#6
HTMCP_UP#7
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N
HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD
CLKIN_25MHZ
CLKIN_200MHZ_P
CLKIN_200MHZ_N
?
?
C51
C51
SEC 2 OF 6
SEC 2 OF 6
SCLKIN_MCLKOUT_200MHZ_P
SCLKIN_MCLKOUT_200MHZ_N
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P
HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TXD8_N
HT_MCP_TXD9_N
HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
CLKOUT_CTERM
HT_MCP_CAL_1P2V
HT_MCP_CAL_GND
HTMCP_DWN0
HTMCP_DWN1
HTMCP_DWN2
HTMCP_DWN3
HTMCP_DWN4
HTMCP_DWN5
HTMCP_DWN6
HTMCP_DWN7
HTMCP_DWN#0
HTMCP_DWN#1
HTMCP_DWN#2
HTMCP_DWN#3
HTMCP_DWN#4
HTMCP_DWN#5
HTMCP_DWN#6
HTMCP_DWN#7
HTMCP_DWNCLK0
HTMCP_DWNCLK0#
HTMCP_DWNCNTL
HTMCP_DWNCNTL#
R155 2.37K/1R155 2.37K/1
2.37K Ohm
R148 150R1%R148 150R1%
R149 150R1%R149 150R1%
1
HTMCP_DWN[7..0]
HTMCP_DWN#[7..0]
VCC1_2
HTMCP_DWN[7..0] 12
HTMCP_DWN#[7..0] 12
HTMCP_DWNCLK0 12
HTMCP_DWNCLK0# 12
HTMCP_DWNCNTL 12
HTMCP_DWNCNTL# 12
X_C4.7U10Y0805
A A
5
4
X_C4.7U10Y0805
X_C0.1U16Y0402
X_C0.1U16Y0402
PLACE ON BACK SIDE
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
3
2
http://www.msi.com.tw
C51PV-1/ HT CPU & MCP
C51PV-1/ HT CPU & MCP
C51PV-1/ HT CPU & MCP
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Friday, March 17, 2006
Friday, March 17, 2006
Friday, March 17, 2006
Sheet
Sheet
Sheet
9 35
9 35
1
9 35
Title
Micro Star Restricted Secret
Title
Rev
Rev
Rev
0A
0A
0A
of
of
of
5
U13B
U13B
?
?
J8
AA3
AC3
AB3
T11
J6
K9
L6
L7
M9
N8
N6
R6
P3
R8
U6
T8
U7
V4
Y3
J7
J5
J9
L5
L8
M8
N7
N5
R5
P4
R7
U5
T9
U8
V3
D1
G6
H6
E2
J4
K3
E3
D3
E4
PE0_RX0_P
PE0_RX1_P
PE0_RX2_P
PE0_RX3_P
PE0_RX4_P
PE0_RX5_P
PE0_RX6_P
PE0_RX7_P
PE0_RX8_P
PE0_RX9_P
PE0_RX10_P
PE0_RX11_P
PE0_RX12_P
PE0_RX13_P
PE0_RX14_P
PE0_RX15_P
PE0_RX0_N
PE0_RX1_N
PE0_RX2_N
PE0_RX3_N
PE0_RX4_N
PE0_RX5_N
PE0_RX6_N
PE0_RX7_N
PE0_RX8_N
PE0_RX9_N
PE0_RX10_N
PE0_RX11_N
PE0_RX12_N
PE0_RX13_N
PE0_RX14_N
PE0_RX15_N
PE0_PRSNT*
PE1_RX_P
PE1_RX_N
PE1_PRSNT*
PE2_RX_P
PE2_RX_N
PE2_PRSNT*
PE1_CLKREQ*/CLK
PE2_CLKREQ*/DATA
PE_REFCLKIN_P
PE_REFCLKIN_N
+1.2V_PLLPE
?
?
PED_RX017
PED_RX117
PED_RX217
PED_RX317
PED_RX417
PED_RX517
PED_RX617
PED_RX717
D D
PC0_PRSNT#17
C C
PC1_PRSNT#17
1P2VPLL_PWR9,11
1P2VPLL_PWR
PED_RX817
PED_RX917
PED_RX1017
PED_RX1117
PED_RX1217
PED_RX1317
PED_RX1417
PED_RX1517
PED_RX0*17
PED_RX1*17
PED_RX2*17
PED_RX3*17
PED_RX4*17
PED_RX5*17
PED_RX6*17
PED_RX7*17
PED_RX8*17
PED_RX9*17
PED_RX10*17
PED_RX11*17
PED_RX12*17
PED_RX13*17
PED_RX14*17
PED_RX15*17
R229 10KR0402R229 10KR0402
VCC3
PE1_RX17
PE1_RX*17
VCC3
VCC3
PE1_RX*
R230 10KR0402R230 10KR0402
R231 10KR0402R231 10KR0402
FB21 X_0RFB21 X_0R
CP10
CP10
X_COPPER
X_COPPER
C0.1U16Y0402
C0.1U16Y0402
C603
C603
C51
C51
SEC 3 OF 6
SEC 3 OF 6
PE0_REFCLK_P
PE0_REFCLK_N
PE1_REFCLK_P
PE1_REFCLK_N
PE2_REFCLK_P
PE2_REFCLK_N
PE_TSTCLK_P
PE_TSTCLK_N
PE_CTERM_GND
PE0_TX0_P
PE0_TX1_P
PE0_TX2_P
PE0_TX3_P
PE0_TX4_P
PE0_TX5_P
PE0_TX6_P
PE0_TX7_P
PE0_TX8_P
PE0_TX9_P
PE0_TX10_P
PE0_TX11_P
PE0_TX12_P
PE0_TX13_P
PE0_TX14_P
PE0_TX15_P
PE0_TX0_N
PE0_TX1_N
PE0_TX2_N
PE0_TX3_N
PE0_TX4_N
PE0_TX5_N
PE0_TX6_N
PE0_TX7_N
PE0_TX8_N
PE0_TX9_N
PE0_TX10_N
PE0_TX11_N
PE0_TX12_N
PE0_TX13_N
PE0_TX14_N
PE0_TX15_N
PE1_TX_P
PE1_TX_N
PE2_TX_P
PE2_TX_N
PE_RST*
4
L1
L3
L4
M4
P1
R1
R3
R4
U4
V1
W1
W3
AA1
AB1
AC1
AD2
L2
M2
M3
N3
P2
R2
T2
T3
U3
V2
W2
Y2
AA2
AB2
AC2
AD3
K1
K2
G4
G5
G2
G3
H4
J3
H2
H3
F1
F2
G1
D2
PE1_TXPE1_RX
PE1_TX*
PE1_CLK
PE1_CLK*
PE_COMP
PED_TX0 17
PED_TX1 17
PED_TX2 17
PED_TX3 17
PED_TX4 17
PED_TX5 17
PED_TX6 17
PED_TX7 17
PED_TX8 17
PED_TX9 17
PED_TX10 17
PED_TX11 17
PED_TX12 17
PED_TX13 17
PED_TX14 17
PED_TX15 17
PED_TX0* 17
PED_TX1* 17
PED_TX2* 17
PED_TX3* 17
PED_TX4* 17
PED_TX5* 17
PED_TX6* 17
PED_TX7* 17
PED_TX8* 17
PED_TX9* 17
PED_TX10* 17
PED_TX11* 17
PED_TX12* 17
PED_TX13* 17
PED_TX14* 17
PED_TX15* 17
PE0_CLK
PE0_CLK*
R232 X_100RR232 X_100R
PE_RST*
R228 2.37KR1%R228 2.37KR1%
PE1_TX 17
PE1_TX* 17
PE1_CLK 17
PE1_CLK* 17
PE_RST* 17
PE0_CLK 17
PE0_CLK* 17
R
R28
G
G28
B
B28
PLACE NEAR C51
3
10 mil7.5 mil
R206
R206
R200
R200
R211
150R1%
150R1%
1P2VPLL_PWR9,11
R211
150R1%
150R1% R212 115R1%R212 115R1%
150R1%
150R1%
1P2VPLL_PWR
C327
C327
C0.1U16Y0402
C0.1U16Y0402
HSYNC#29
VSYNC#29
2P5V_PLL9
HSYNC#
VSYNC#
C279 C0.01U16X0402C279 C0.01U16X0402
3P3V_DAC
2P5V_PLL
Y2 27MHZ20P_DY2 27MHZ20P_D
C268
C268
C20P50N
C20P50N
C326
C326
C0.1U16Y0402
C0.1U16Y0402
C277
C277
C20P50N
C20P50N
H13
H16
A5
B6
A6
B7
C7
D8
D9
C8
A9
C9
B9
R9
P9
U13C
U13C
?
?
DAC_RED
DAC_GREEN
DAC_BLUE
DAC_HSYNC
DAC_VSYNC
DAC_RSET
DAC_VREF
DAC_IDUMP
+3.3V_DAC
+2.5V_PLLGPU
XTAL_IN
XTAL_OUT
+1.2V_PLLGPU
+1.2V_PLLCORE
+1.2V_PLLIFP
?
?
2
C51
C51
SEC 4 OF 6
SEC 4 OF 6
IFPA_TXC_P
IFPA_TXC_N
IFPA_TXD0_P
IFPA_TXD1_P
IFPA_TXD2_P
IFPA_TXD3_P
IFPA_TXD0_N
IFPA_TXD1_N
IFPA_TXD2_N
IFPA_TXD3_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD4_P
IFPB_TXD5_P
IFPB_TXD6_P
IFPB_TXD7_P
IFPB_TXD4_N
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_N
IFPAB_PROBE
IFPAB_RSET
+2.5V_PLLIFP
+2.5V_PLLCORE
PKG_TEST
TEST_MODE_EN
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
C14
B13
A15
D15
A14
F14
B15
C15
B14
E14
A10
B10
B11
E13
D13
B12
A11
F13
C13
C12
A16
F15
E16
H12
D17
C17
C18
B19
C19
B18
A19
TXC+
TXC-
TX0+
TX1+
TX2+
TX0TX1TX2-
IFPAB_PROBE
IFPAB_RSET
2P5V_PLL
2P5V_PLL
R177 1KR0402R177 1KR0402
R172 X_10KR0402R172 X_10KR0402
R169 X_10KR0402R169 X_10KR0402
JTAG_TMS
R163 X_10KR0402R163 X_10KR0402
R168 X_10KR0402R168 X_10KR0402
TXC+ 29
TXC- 29
TX0+ 29
TX1+ 29
TX2+ 29
TX0- 29
TX1- 29
TX2- 29
C0.1U16Y0402C258 C0.1U16Y0402C258
R182 1KR0402R182 1KR0402
3.3V FOR TMDS
2P5V_PLL 9
44.9 ohm
TXC+
TXCTX0+
TX0TX1+
TX1TX2+
TX2-
1
R561
R561
49.9/4
49.9/4
VCC2_5
R562
R562
49.9/4
49.9/4
R563
R563
49.9/4
49.9/4
3P3V_IFPA
R564
R564
49.9/4
49.9/4
R565
R565
49.9/4
49.9/4
R566
R566
49.9/4
49.9/4
R567
R567
49.9/4
49.9/4
R568
R568
49.9/4
49.9/4
B B
PLACE ON BACK SIDE
FB9 X_0R0805FB9 X_0R0805
CP17
CP17
X_COPPER
X_COPPER
X_C4.7U10Y0805
X_C4.7U10Y0805
4A ?
C266
C266
3P3V_DAC
C267
C267
C0.1U16Y0402
C0.1U16Y0402
VCC3
VCC3
PMOS
Q46
_P-CMT2301GM233_SOT23-3-RH
_P-CMT2301GM233_SOT23-3-RH
DS
Q47
Q47
N-2N7002_SOT23
N-2N7002_SOT23
ATX_PWR_OK123,26
G
Q46
R296 10KR0402R296 10KR0402
S
S
G
G
G
D S
R511 X_0/0805R511 X_0/0805
D
D
3P3V_IFPA
For C51G No DVI
3P3V_IFPA 11
15~20 mil width
A A
TMDS Backdrive Prevention Circuit
Title
Title
Title
Document Number
Document Number
Document Number
5
4
3
2
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
C51PV-2 / PCI-E & DAC
C51PV-2 / PCI-E & DAC
C51PV-2 / PCI-E & DAC
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
1
Monday, March 20, 2006
Monday, March 20, 2006
Monday, March 20, 2006
of
10 35
of
10 35
of
10 35
Rev
Rev
Rev
0A
0A
0A
A
B
C
D
E
C51 DECOUPLING
PLACE ON BACK SIDE
VCC1_2
4 4
U13E
B5
C6
D7
E8
E9
E10
F10
F11
G11
H11
J11
J12
J13
J14
T15
U13
U11
Y9
W16
U16
U15
B4
C5
D6
E7
K16
M16
R16
M21
J20
T16
U17
C21
H17
D18
C10
U13E
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_CORE
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_HTMCP
+1.2V_PED
+1.2V_PED
+1.2V_PED
+1.2V_PED
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+1.2V_HT
+3.3V
+3.3V
?
?
C51
C51
SEC 5 OF 6
SEC 5 OF 6
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PEA
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+1.2V_PLL
+2.5V_CORE
+2.5V_CORE
+2.5V_IFPA
+2.5V_IFPB
VCC1_2
AB11
AA18
3 3
VCC1_2HT
VCC3
FB11
FB11
X_30L3_15_0805
X_30L3_15_0805
A3
B3
C4
D5
E6
F7
F8
F9
X_30L3_15_0805
X_30L3_15_0805
A2
B2
C2
C3
D4
E5
F6
G7
G8
G9
H10
J10
C16
B16
G15
H15
VCC2_5
CP5
CP5
X_COPPER
X_COPPER
1P2VPEA_PWR
VCC1_2
FB12
3P3_IFPA_L
C667
C667
0.1u/25V/6
0.1u/25V/6
CP7
CP7
X_COPPER
X_COPPER
1P2VPLL_PWR
C228
C228
4.7u/10V/8
4.7u/10V/8
1P2VPLL_PWR 9,10
FB31 X_0RFB31 X_0R
CP25
CP25
X_COPPER
X_COPPER
3P3V_IFPA 10
3.3V FOR TMDS
VCC1_2
C1U10Y
C1U10Y
VCC1_2
X_C10U10Y0805
X_C10U10Y0805
C4.7U10Y0805
C4.7U10Y0805
C10U10Y0805
C10U10Y0805
VCC1_2HT
PLACE ON BACK SIDE
CENTER OF C51
C608
C608
C606
C606
C0.1U16Y0402
C0.1U16Y0402
C1U10Y
C1U10Y
C288
C288
C278
C278FB12
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C10U10Y0805
X_C10U10Y0805
1P2VPLL_PWR
C329
C329
C328
C328
C0.1U16Y0402
C0.1U16Y0402
C4.7U10Y0805
C4.7U10Y0805
1P2VPEA_PWR
*
C308
C308
C309
C309
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C4.7U10Y0805
X_C4.7U10Y0805
C609
C609
X_C0.1U16Y0402
X_C0.1U16Y0402
C264
C264
C271
C271
X_C0.1U16Y0402
X_C0.1U16Y0402
C602
C602
C607
C607
C0.1U16Y0402
C0.1U16Y0402
*
C324
C324
C1U10Y
C1U10Y
C283
C283
C610
C610
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C287
C287
X_C0.1U16Y0402
X_C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C611
C611
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C321
C321
C323
C323
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C605
C605
* *
C260
C260
C281
C281
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
*
C330
C330
C604
C604
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C322
C322
C0.1U16Y0402
C0.1U16Y0402
C282
C282
*
C331
C331
C325
C325
C0.1U16Y0402
C0.1U16Y0402
C298
C298
VCC1_2
C0.1U16Y0402
C0.1U16Y0402
MCPHT CORE BALLS
C594
C594
C0.1U16Y0402
C0.1U16Y0402
C383
C383
C0.1U16Y0402
C0.1U16Y0402
C596
C596
VCC3
*
C251
C251
C0.1U16Y0402
C0.1U16Y0402
C211
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
C245
C245
C593
C593
C592
C592
C0.1U16Y0402
C0.1U16Y0402
2 2
V8
F4
V6
K8
H8
W8
W6
T6
P6
M6
B1
E11
L12
P14
N14
M14
P13
N13
M13
P12
N12
M12
P11
N11
M11
L11
AA24
AA23
A23
AA22
V22
R22
L22
F22
AB6
C22
H21
Y16
G13
U12
AB14
R17
C20
T14
V19
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
C51
C51
SEC 6 OF 6
SEC 6 OF 6
?
?
U13D
U13D
1 1
GND
GNDC1GND
AA13
AA21
GND
U14
A
GND
E12
GND
C11
GND
AB4
GND
AA4
GND
F12
GND
D11
GND
AB10
GND
Y18
GND
E18
GND
U18
GND
E15
GND
Y11
GND
U19
GND
N17
GND
F16
GND
J17
GND
E17
GND
G17
GND
T17
GND
F17
GND
T12
GND
J16
GND
D19
GND
H19
GND
L21
GND
M19
GND
P19
GND
T19
GND
L14
GND
L13
GND
H14
GND
J15
K6
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
?
?
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
PE_GND
L9
F3
B
T4
H9
U9
Y4
N4
K4
N9
P8
W4
C
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
C0.1U16Y0402
*
C220
C220
C211
C178
C178
C177
C177
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
X_C0.1U16Y0402
D
**
*
C182
C182
C215
C215
X_C0.1U16Y0402
X_C0.1U16Y0402
Micro Star Restricted Secret
Micro Star Restricted Secret
Micro Star Restricted Secret
Title
Title
Title
Document Number
Document Number
Document Number
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
Taipei Hsien, Taiwan
http://www.msi.com.tw
http://www.msi.com.tw
http://www.msi.com.tw
C51PV-3/PWR/GND
C51PV-3/PWR/GND
C51PV-3/PWR/GND
MS-7252CH
MS-7252CH
MS-7252CH
Last Revision Date:
Last Revision Date:
Last Revision Date:
Sheet
Sheet
Sheet
E
Rev
Rev
Rev
0A
0A
0A
Wednesday, March 15, 2006
Wednesday, March 15, 2006
Wednesday, March 15, 2006
of
11 35
of
11 35
of
11 35
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