5
4
3
2
1
Cover Sheet, Block diagram
Intel LGA775 CPU - Signals
D D
Intel LGA775 CPU - Power
Intel LGA775 CPU- GND
Intel Broadwater - CPU
Intel Broadwater - Memory
Intel Broadwater - PCI Express
Intel Broadwater - GND
ICH8
C C
Clock Generator - ICS 9LPRS510
LPC I/O - Winbond W83627EHF & KB/MS
HD Audio ALC883 15
LAN - Realtek 8110SC/8100C
DDRII DIMM1,2
DDRII DIMM 3 , 4 & Termination & MCH1.8V
PCI - Express x16 & x1 port 1 & 2
PCI SLOT 1
B B
USB Connectors
ATX & Front Panel & VGA Connector
MS7 ACPI Controller
VRD 11 - RT8802AM+RT9607+RT9619
FAN Controller & SATA
JMB361
Manual Parts 28
POWER/PWROK/RESET MAP
A A
Revision History
1-2
3
4
5
6
7
8
9
10-12
13
14
16
17
18-19
20
21
22
23
24
25
26
27
29 - 31
32
MS-7235
CPU
Pentium 4
Pentium D
Celeron D
System Chipset:
On Board Chipset:
Main Memory:
Expansion Slots:
Realteak PWM:
Generation
Prescott (5 series)
Cedar Mill (6 series)
P4 Extreme Edition X 1066 2MB
Smithfield (8 series)
PD Extreme Edition V 800
Presler (9 series)
Prescott (3 series)
Cedar Mill (TBD series) X TBD 512KB X V X
Intel Broadwater P- GMCH (North Bridge)
Intel ICH8/ICH8R (South Bridge)
BIOS -- SPI Flash 8Mb
AC97 AUDIO -- HD Audio /ALC883
LPC Super I/O -- Winbond W83627EHG ver. H
LAN -- Realtek 8110SC/8100C
CLOCK -- ICS 9LPRS510
2 CHANNEL DDR II * 4 (Max 8GB)
PCIE x16 SLOT * 1
PCIE x1 SLOT * 2
PCI SLOT * 3
Controller:Realteak RT8802AM+RT9607+RT9619
Version 0A
DUAL CORE EIST
X
X
V
533/800
800
800
1MB
2MB
2 x 1MB
2 x 1MB
V
X
800
533
2 x 2MB
256KB
HTL2 CacheFSB EM64T
"1" in last
V
code
VV
V
VV
V
X
VV
V
X
VV
X
XX
X
>=830V
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
COVER SHEET
MS-7235
1
132Monday, December 26, 2005
0A
of
5
4
3
2
1
Block Diagram
D D
VRM 11
Realteck RT8802
Intel LGA775 Processor
4-Phase PWM
200/266
MHz
FSB
4 DDR II
PCI EXPRESS
X16
Connector
C C
PCI EXPRESS X1 1&2
SATA 0~6
PCI EXPRESS X16
Broadwater
GMCH
DMI
PCI EXPRESS X1
SATA2
ICH8
USB
DDRII
up to 800
MHz
PCI EXPRESS X2
PCI
DIMM
Modules
JMB361
IDE
SATA7
PCI Slot 1 2 3 4
USB Port 0~9
B B
HD Audio
ALC883
AC'97
PCI
Realtek 8110SC
LPC Bus
LPC SIO
Winbond
SPI
SPI
W83627EHG
SPI Flash
IrDA Parallel COM1,2
A A
5
4
Floopy
3
Keyboard
Mouse
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
2
Date: Sheet
Block Diagram
MS-7235
1
0A
of
232Monday, December 26, 2005
5
4
3
2
1
CPU SIGNAL BLOCK
H_A#[3..35]6
D D
U6A
H_DBI#[0..3]6
H_IERR#4
H_FERR#4,10
H_STPCLK#10
H_INIT#10
H_DBSY#6
H_DRDY#6
H_TRDY#6
H_ADS#6
H_LOCK#6
THERMDA_CPU14
THERMDC_GND14
R91
51R0402
H_SLP#
H_D#[0..63]6
H_BNR#6
H_HIT#6
H_HITM#6
H_BPRI#6
H_DEFER#6
TRMTRIP#4,10
H_PROCHOT#4,11,25
H_IGNNE#10
ICH_H_SMI#10
H_A20M#10
CPU_BSEL013
CPU_BSEL113
CPU_BSEL213
H_PWRGD4,11
H_CPURST#4,6
5
C C
VTT_OUT_LEFT
B B
A A
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
THERMDA_CPU
THERMDC_GND
H_SLP#
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD#AH2
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
D52#
B15
C14
H_D#53
H_D#52
D51#
C15
H_D#51
H_D#50
D50#
A14
H_D#49
H_A#35
D49#
D17
H_D#48
H_A#34
AJ6
A35#
D48#
D20
H_D#47
H_A#33
AJ5
A34#
D47#
G22
H_D#46
H_A#32
AH5
A33#
D46#
D22
H_D#45
H_A#31
AH4
A32#
D45#
E22
H_D#44
H_A#30
AG5
A31#
D44#
G21
H_D#43
H_A#29
AG4
A30#
D43#
F21
H_D#42
AG6
A29#
D42#
E21
H_A#28
H_A#27
AF4
AF5
A28#
A27#
D41#
D40#
F20
E19
H_D#41
H_D#40
4
H_A#25
H_A#26
AB4
AC5
A26#
D39#
F18
E18
H_D#39
H_D#38
H_A#24
AB5
A25#
A24#
D38#
D37#
F17
H_D#37
H_A#22
H_A#23
AA5
AD6
A23#
A22#
D36#
D35#
G17
G18
H_D#35
H_D#36
H_A#21
H_A#20
AA4
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
E16
E15
H_D#33
H_D#34
H_A#19
H_A#18
D32#
D31#
G16
G15
H_D#31
H_D#32
H_A#17
AB6
F15
H_D#30
H_A#16
H_A#15
H_A#14
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D30#
D29#
D28#
F14
G14
H_D#27
H_D#28
H_D#29
H_A#13
D27#
G13
H_D#26
H_A#12
D26#
E13
H_D#25
H_A#11
D25#
D13
H_D#24
D24#
F12
H_A#8
H_A#10
H_A#7
H_A#9
U6
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
F11
E10
D10
H_D#20
H_D#21
H_D#22
H_D#23
H_A#6
H_A#5
H_A#4
H_A#3
L5
AC2
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
D11
C12
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
DBR#
D14#
D13#
B12
H_D#12
H_D#13
AN4
AN3
VCC_SENSE
D12#D8D11#
C11
H_D#11
VSS_SENSE
3
AN5
AN6
VSS_MB_REGULATION
VCC_MB_REGULATION
D10#
D9#
B10
A11
H_D#9
H_D#10
AJ3
D8#
A10
H_D#7
H_D#8
AK3
ITP_CLK1
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
H_D#6
ITP_CLK0
H_D#5
VID7
VID6
AM7
AM5
RSVD#AM7
H_D#3
H_D#4
VID6#
VCC_VRM_SENSE
VSS_VRM_SENSE
VID3
VID5
VID2
VID4
AL4
AK4
AL6
AM3
VID5#
VID4#
VID3#
VID2#
VID_SELECT
GTLREF0
GTLREF1
GTLREF_SEL
GTLREF2
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
RSVD#G6
BCLK1#
BCLK0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
ZIF-SOCK775-15u-in
B4
H_D#0
H_D#1
H_D#2
VID1
AL5
VID0
VID1#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
DP3#
DP2#
DP1#
DP0#
AM2
VID0#
VID[0..7] 25
VTT_OUT_RIGHT
R57
1KR0402
AN7
CPU_GTLREF0
H1
CPU_GTLREF1
H2
GTLREF_SEL
H29
CPU_MCH_GTLREF
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
H_SST
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
G4
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
H_FORCEPR#
AK6
RSVD_G6
G6
G28
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
TEST-U3
U3
TEST-U2
U2
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
TEST-J17
J17
TEST-H16
H16
TEST-H15
H15
TEST-J16
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
VCC_VRM_SENSE 25
VSS_VRM_SENSE 25
R59
X_1KR0402
VIDSEL 25
CPU_GTLREF0 4
CPU_GTLREF1 4
CPU_MCH_GTLREF 6
H_SST 10
H_REQ#[0..4] 6
RN8 8P4R-51R0402
1
2
3
4
5
6
7
8
R99 51R0402
R110 51R0402
R83 51R0402
R109 51R0402
R70 X_130R1%0402
R90 X_62R
CK_H_CPU# 13
CK_H_CPU 13
H_RS#[0..2] 6
T4
T3
R85 49.9R1%0402
R93 49.9R1%0402
R87 49.9R1%0402
R100 49.9R1%0402
R86 49.9R1%0402
R112 49.9R1%0402
T7
T6
T8
T5
H_ADSTB#1 6
H_ADSTB#0 6
H_DSTBP#3 6
H_DSTBP#2 6
H_DSTBP#1 6
H_DSTBP#0 6
H_DSTBN#3 6
H_DSTBN#2 6
H_DSTBN#1 6
H_DSTBN#0 6
H_NMI 10
H_INTR 10
2
RN2
VID7
VID3
VID6
VID1
VID5
VID2
VID0
VID4
8P4R-680R
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN4
8P4R-680R
VTT_OUT_RIGHT H_TMS
T9
VTT_OUT_RIGHT H_BPM#3
VTT_OUT_RIGHT H_BPM#2
VTT_OUT_LEFT
V_FSB_VTT 4,6,11,12,13,24,25
VTT_OUT_RIGHT 4,5
H_BR#0 4,6
VTT_OUT_LEFT 4
C42
X_C0.1U25Y
MSI
Title
Size Document Number Rev
Date: Sheet
VTT_OUT_RIGHT
C43
C0.1U16Y0402
C40
C0.1U16Y0402
RN6
8P4R-62R0402
1
2
3
4
5
6
7
8
R7162R0402
RN3
1
2
3
4
5
6
7
8
8P4R-51R0402
R75 51R0402
R74 51R0402
H_TDI
H_TCK
H_TDO
H_TRST#
H_BPM#5
H_BPM#1
H_BPM#0
H_BPM#4
H_FORCEPR# 25
MICRO-STAR INt'L CO., LTD.
Intel LGA775 CPU - Signals
MS-7235
332Monday, December 26, 2005
1
0A
of
5
4
3
2
1
VCCP
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AH8
AF21
AF9
VCC#AF19
VCC#AF18
VCC#AF15
VCC#AF14
VCC#AF12
VCC#AF11
VCC#AE9
VCC#AE23
VCC#AE22
VCC#AE21
VCC#AE19
VCC#AE18
VCC#AE15
VCC#AE14
VCC#AE12
VCC#AE11
VCC#AD8
VCC#AD30
VCC#AD29
VCC#AD28
VCC#AD27
VCC#AD26
VCC#AD25
VCC#AD24
VCC#AD23
VCC#AC8
VCC#AC30
VCC#AC29
VCC#AC28
VCC#AC27
VCC#AC26
VCC#AC25
VCC#AC24
VCC#AC23
VCC#AB8
VCC#AA8
AF8
VCC#AF9
VCC#AF8
VCC#AF22
VCC#AF21
VCC#Y8
Y8
VCC#AG14
VCC#AG12
VCC#AG11
VCC#Y25
VCC#Y26
VCC#Y27
VCC#Y28
VCC#Y29
VCC#Y30
Y25
Y26
Y27
Y28
Y29
Y30
VCC#AG25
VCC#AG22
VCC#AG21
VCC#AG19
VCC#AG18
VCC#AG15
VCC#W28
VCC#W29
VCC#W30
VCC#W8
VCC#Y23
VCC#Y24
W8
Y23
Y24
W30
W29
W28
W27
U6B
D D
C C
VCCP
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
VCC#AG28
VCC#AG27
VCC#AG26
VCC#W25
VCC#W26
VCC#W27
W25
W26
VCC#AG30
VCC#AG29
VCC#W24
W23
W24
AG8
VCC#AG8
VCC#V8V8VCC#W23
AG9
VCC#AG9
VCC#U8
U8
AH12
AH11
VCC#AH12
VCC#AH11
VCC#U29
VCC#U30
U29
U30
AH15
AH14
VCC#AH15
VCC#AH14
VCC#U27
VCC#U28
U27
U28
AH19
AH18
VCC#AH19
VCC#AH18
VCC#U25
VCC#U26
U25
U26
AH22
AH21
VCC#AH22
VCC#AH21
VCC#U24
U23
U24
AH25
VCC#AH25
VCC#T8T8VCC#U23
AH26
T30
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF22
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AH27
AH28
AH29
AH30
VCC#AH8
VCC#AH9
VCC#AH27
VCC#AH26
VCC#AH28
VCC#AH29
VCC#AH30
VCC#T24
VCC#T25
VCC#T26
VCC#T27
VCC#T28
VCC#T29
VCC#T30
T23
T24
T25
T26
T27
T28
T29
AJ21
VCC#AJ11
VCC#AJ12
VCC#AJ14
VCC#AJ15
VCC#AJ18
VCC#AJ19
VCC#N29
VCC#N30
VCC#N8
VCC#P8P8VCC#R8
VCC#T23
N8
R8
N28
N29
N30
AJ22
AJ25
VCC#AJ21
VCC#AJ22
VCC#N27
VCC#N28
N26
N27
AJ26
AJ8
VCC#AJ25
VCC#AJ26
VCC#N25
VCC#N26
N24
N25
AK11
AJ9
VCC#AJ8
VCC#AJ9
VCC#N24
N23
AK12
VCC#AK11
VCC#M8M8VCC#N23
M30
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
VCC#AK8
VCC#AK9
VCC#AL11
VCC#AL12
VCC#AL14
VCC#AL15
VCC#AK12
VCC#AK14
VCC#AK15
VCC#AK18
VCC#AK19
VCC#AK21
VCC#AK22
VCC#AK25
VCC#AK26
VCC#K8K8VCC#L8L8VCC#M23
VCC#M24
VCC#M25
VCC#M26
VCC#M27
VCC#M28
VCC#M29
VCC#M30
M23
M24
M25
M26
M27
M28
M29
VCC#AL18
VCC#K25
VCC#K26
VCC#K27
VCC#K28
VCC#K29
VCC#K30
K24
K25
K26
K27
K28
K29
K30
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
H_VCCA
A23
VCCA
VCC#AL8
VCC#AL25
VCC#J8J8VCC#J9J9VCC#K23
J30
VCC#AL26
VCC#AL29
VCC#J29
VCC#J30
J28
J29
VCC#AL30
VCC#J27
VCC#J28
J26
J27
VCC#AL9
VCC#AM11
VCC#J25
VCC#J26
J24
J25
VCC#AM12
VCC#AM14
VCC#J23
VCC#J24
J22
J23
VCC#AM15
VCC#AM18
VCC#J21
VCC#J22
J20
J21
VCC#AM19
VCC#AM21
VCC#J19
VCC#J20
J19
VCC#AL19
VCC#AL21
VCC#AL22
VCC#K24
K23
VCC#AM22
VCC#J18
J15
J18
VCC#AM25
VCC#AM26
VCC#J14
VCC#J15
J13
J14
VCC#AM29
VCC#AM30
VCC#J12
VCC#J13
J11
J12
VCC#AM8
VCC#AM9
VCC#J10
VCC#J11
J10
AN9
VCC#AN11
VCC#AN12
VCC#AN14
VCC#AN30
VCC#AN8
VCC#AN9
AN8
AN29
AN30
VCC#AN15
VCC#AN18
VCC#AN19
VCC#AN21
VCC#AN22
VCCPLL
VCC-IOPLL
VTT#A25
VTT#A26
VTT#A27
VTT#A28
VTT#A29
VTT#A30
VTT#B25
VTT#B26
VTT#B27
VTT#B28
VTT#B29
VTT#B30
VTT#C25
VTT#C26
VTT#C27
VTT#C28
VTT#C29
VTT#C30
VTT#D25
VTT#D26
VTT#D27
VTT#D28
VTT#D29
VTT#D30
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD#F29
VCC#AN25
VCC#AN26
VCC#AN29
1122334
AN25
AN26
VSSA
4
H_VSSA
B23
H_VCCPLL
D23
H_VCCA
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
F27
F29
ZIF-SOCK775-15u-in
V_FSB_VTT
CAPS FOR FSB GENERIC
V_FSB_VTT
C83
C2.2U6.3Y
C82
C2.2U6.3Y
C76
C2.2U6.3Y
C74
C2.2U6.3Y
VTT_OUT_RIGHT
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
B B
VTT_OUT_RIGHT
R92 124R1%
R94 124R1%
R89
210R1%
R96
210R1%
R98 49.9R1%0402
C47
C1U16Y
R97 49.9R1%0402
C49
C1U16Y
C50
X_C220P16X0402
C48
X_C220P16X0402
CPU_GTLREF0 3
CPU_GTLREF1 3
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
V_1P5_ICH
L1
X_10U100m_0805
CP7
X_COPPER
CP8
X_COPPER
C78
X_C1U16Y
H_VCCPLL
C86
C0.01U25X0402
C75
X_C10U10Y0805
C89
X_C10U10Y0805
C70
C10U10Y0805
H_VCCA
H_VSSA
PLACE AT CPU END OF ROUTE
VTT_OUT_RIGHT3,5
A A
VTT_OUT_LEFT3
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
5
R68 X_130R1%0402
R80 62R0402
R65 62R0402
R88 X_100R0402
R102 62R0402
H_PROCHOT#
H_IERR#
H_CPURST#
H_PWRGD
H_BR#0
PLACE AT ICH END OF ROUTE
R291 62R0402
R289 62R0402
TRMTRIP#
H_FERR#
H_PROCHOT# 3,11,25
H_IERR# 3
H_CPURST# 3,6
H_PWRGD 3,11
H_BR#0 3,6
TRMTRIP# 3,10V_FSB_VTT3,6,11,12,13,24,25
H_FERR# 3,10
4
VTT_OUT_LEFT
VCC5_SB
R62
1KR0402
VID_GD#24,25
3
R63 1KR0402
R60
680R0402
CE
Q6
B
N-PMBS3904_SOT23-RH
1.25V VTT_PWRGOOD
VTT_PWG
2
Title
Size Document Number Rev
Date: Sheet
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
MICRO-STAR INt'L CO., LTD.
MSI
Intel LGA775 CPU - Power
MS-7235
432Monday, December 26, 2005
1
0A
of
5
VTT_OUT_RIGHT3,4
R79
R81
VSS#A12
VSS#A15
VSS#A18
VSS#A2
VSS#A21
VSS#A24
VSS#A6
VSS#A9
VSS#AA23
VSS#AA24
VSS#AA25
VSS#AA26
VSS#AA27
VSS#AA28
VSS#AA29
VSS#AA3
VSS#AA30
VSS#AA6
VSS#AA7
VSS#AB1
VSS#AB23
VSS#AB24
VSS#AB25
VSS#AB26
VSS#AB27
VSS#AB28
VSS#AB29
VSS#AB30
VSS#AB7
VSS#AC3
VSS#AC6
VSS#AC7
VSS#AD4
VSS#AD7
VSS#AE10
VSS#AE13
VSS#AE16
VSS#AE17
VSS#AE2
VSS#AE20
VSS#AE24
VSS#AE25
VSS#AE26
VSS#AE27
VSS#AE28
VSS#AE29
AE29
49.9R1%0402
H_COMP7
H_COMP6
AE3
AE4
COMP6Y3COMP7
VSS#AE30
VSS#AE5
AE5
AE7
AE30
T12
D14
D1
RSVD#D1
RSVD#D14
RSVD#AE4
VSS#AE7
VSS#AF10
VSS#AF13
AF10
AF13
E23
AF16
RSVD#E23
VSS#AF16
AF17
51R0402
T11
RSVD#E5E5RSVD#E6E6RSVD#E7
VSS#AF17
VSS#AF20
AF20
AF23
R95
R115
24.9R1%0402
H_COMP8
B13
IMPSEL#
RSVD#B13
VSS#AF26
VSS#AF27
AF27
47R0402
VSS#AF28
AF28
AF29
R84
J3
P5
N4
RSVD#J3
RSVD#P5
RSVD#N4
VSS#AF29
VSS#AF3
VSS#AF30
VSS#AF6
AF3
AF6
AF7
AF30
T10
E7
F23
F6
RSVD#F23
VSS#AF23
VSS#AF24
VSS#AF25
AF24
AF25
AF26
49.9R1%0402
D D
U6C
A12
A15
A18
A2
A21
A24
A6
A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
C C
B B
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
W1
MSID[1]V1MSID[0]
VSS#AF7
VSS#AG10
VSS#AG13
AG10
AG13
R82
47R0402
AC4
RSVD#AC4
VSS#AG16
VSS#AG17
VSS#AG20
AG16
AG17
AG20
4
Y2
VSS#Y7Y7VSS#Y5Y5VSS#Y2
VSS#W7W7VSS#W4
VSS#AG23
VSS#AG24
VSS#AG7
VSS#AH1
AH1
AG7
AG23
AG24
W4
VSS#V7V7VSS#V6
VSS#AH10
VSS#AH13
AH10
AH13
V6
VSS#AH16
AH16
V30
V3
VSS#V3
VSS#V30
VSS#AH17
VSS#AH20
AH17
AH20
V29
V28
VSS#V29
VSS#V28
VSS#AH23
VSS#AH24
AH23
AH24
V27
V26
VSS#V27
VSS#V26
VSS#AH3
VSS#AH6
AH3
AH6
V25
V24
VSS#V25
VSS#V24
VSS#AH7
VSS#AJ10
AH7
AJ10
V23
U1
VSS#U7U7VSS#U1
VSS#V23
VSS#AJ13
VSS#AJ16
AJ13
AJ16
AJ17
3
L6
T3
R30
R29
R28
R27
R26
R5
VSS#T7T7VSS#T6T6VSS#T3
VSS#R7R7VSS#R5
VSS#AJ17
VSS#AJ20
VSS#AJ23
VSS#AJ24
VSS#AJ27
AJ20
AJ23
AJ24
AJ27
AJ28
R25
VSS#R30
VSS#R29
VSS#R28
VSS#R27
VSS#R26
VSS#R25
VSS#AJ28
VSS#AJ29
VSS#AJ30
VSS#AJ4
VSS#AJ7
VSS#AK10
VSS#AK13
AJ4
AJ7
AJ29
AJ30
AK10
AK13
R24
R23
R2
VSS#R24
VSS#R23
VSS#AK16
VSS#AK17
AK2
AK16
AK17
P30
P4
VSS#P7P7VSS#P4
VSS#R2
VSS#AK2
VSS#AK20
VSS#AK23
AK20
AK23
AK24
P29
P28
P27
VSS#P30
VSS#P29
VSS#P28
VSS#AK24
VSS#AK27
VSS#AK28
AK27
AK28
AK29
P26
P25
P24
VSS#P27
VSS#P26
VSS#P25
VSS#AK29
VSS#AK30
VSS#AK5
AK5
AK7
AK30
P23
VSS#N7N7VSS#N6N6VSS#N3
VSS#P24
VSS#P23
VSS#AK7
VSS#AL10
VSS#AL13
AL10
AL13
N3
VSS#AL16
AL16
AL17
M1
VSS#M7M7VSS#M1
VSS#AL17
VSS#AL20
VSS#AL23
AL20
AL23
AL24
L3
L30
VSS#L7L7VSS#L6
VSS#L30
VSS#AL24
VSS#AL27
VSS#AL28
AL3
AL27
AL28
L29
VSS#L3
VSS#L29
VSS#AL3
VSS#AL7
AL7
L28
L27
VSS#L28
VSS#L27
VSS#AM1
VSS#AM10
AM1
AM10
L26
L25
VSS#L26
VSS#L25
VSS#AM13
VSS#AM16
AM13
AM16
2
L24
L23
VSS#L24
VSS#L23
VSS#AM17
VSS#AM20
AM17
AM20
K2
K5
VSS#K2
VSS#K7K7VSS#K5
VSS#AM23
VSS#AM24
VSS#AM27
AM23
AM24
AM27
1
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
J7
H9
VSS#J4J4VSS#J7
VSS#AM28
VSS#AM4
AM4
AM28
H28
H14
VSS#H3H3VSS#H6H6VSS#H7H7VSS#H8H8VSS#H9
VSS#AN1
VSS#AN10
VSS#AN13
VSS#AN16
AN1
AN10
AN13
AN16
VSS#H24
VSS#H25
VSS#H26
VSS#H27
VSS#H28
VSS#AN17
VSS#AN2
VSS#AN20
VSS#AN23
VSS#AN24
VSS#AN27
AN2
AN17
AN20
AN23
AN24
AN27
AN28
VSS#H22
VSS#H23
VSS#AN28
VSS#H14
VSS#H13
VSS#H18
VSS#H19
VSS#H20
VSS#H21
VSS#H12
VSS#H11
VSS#H10
VSS#F22
VSS#F19
VSS#F16
VSS#F13
VSS#F10
VSS#E29
VSS#E28
VSS#E27
VSS#E26
VSS#E25
VSS#E20
VSS#E17
VSS#E14
VSS#E11
VSS#D24
VSS#D21
VSS#D18
VSS#D15
VSS#D12
VSS#C24
VSS#C22
VSS#C19
VSS#C16
VSS#C13
VSS#C10
VSS#B24
VSS#B20
VSS#B17
VSS#B1B1VSS#B11
VSS#B14
B11
B14
H13
VSS#H17
H12
H11
H10
G1
VSS#G1
F7
VSS#F7
F4
VSS#F4
F22
F19
F16
F13
F10
E8
VSS#E8
E29
E28
E27
E26
E25
E20
E2
VSS#E2
E17
E14
E11
D9
VSS#D9
D6
VSS#D6
D5
VSS#D5
D3
VSS#D3
D24
D21
D18
D15
D12
C7
VSS#C7
C4
VSS#C4
C24
C22
C19
C16
C13
C10
B8
VSS#B8
B5
VSS#B5
B24
B20
B17
ZIF-SOCK775-15u-in
R66
X_0R
CPU DECOUPLING CAPACITORS
VCCP VCCP VCCP VCCP
EC19
EC41
C10U6.3X51206
EC5
A A
C10U6.3X51206
C10U6.3X51206
EC11
C10U6.3X51206
EC10
C10U6.3X51206
EC22
C10U6.3X51206
EC4
C10U6.3X51206
C10U10Y1206 10u/10V/Y5V,1206,80/-20%
Place these caps within socket cavity
5
4
EC12
C10U6.3X51206
EC16
C10U6.3X51206
EC43
C10U6.3X51206
MSI
MICRO-STAR INt'L CO., LTD.
Title
Size Document Number Rev
3
2
Date: Sheet
Intel LGA775 CPU - GND
MS-7235
532Monday, December 26, 2005
1
0A
of
5
V_FSB_VTT3,4,11,12,13,24,25
P29
P27
P26
P24
P23
N29
N26
N24
N23
M29
M24
VTT_6
VCC_5
AJ8
VTT_7
VCC_6
AJ7
VTT_8
VCC_7
AJ6
VTT_9
VCC_8
AJ5
VTT_10
VCC_9
AJ4
AJ3
M23
VTT_11
VTT_12
VCC_10
VCC_11
AJ2
U8A
J42
HA3#
L39
HA4#
J40
HA5#
L37
HA6#
L36
HA7#
K42
HA8#
N32
HA9#
N34
HA10#
M38
HA11#
N37
HA12#
M36
HA13#
R34
HA14#
N35
HA15#
N38
HA16#
U37
HA17#
N39
HA18#
R37
HA19#
P42
HA20#
R39
HA21#
V36
HA22#
R38
HA23#
U36
HA24#
U33
HA25#
R35
HA26#
V33
HA27#
V35
HA28#
Y34
HA29#
V42
HA30#
V38
HA31#
Y36
HA32#
Y38
HA33#
Y39
HA34#
AA37
HA35#
M34
HADSTB0#
U34
HADSTB1#
F40
HREQ0#
L35
HREQ1#
L38
HREQ2#
G43
HREQ3#
J37
HREQ4#
W40
HADS#
Y40
HTRDY#
W41
HDRDY#
T43
HDEFER#
Y43
HITM#
U42
HHIT#
V41
HLOCK#
AA42
HBREQ0#
W42
HBNR#
G39
HBPRI#
U40
HDBSY#
U41
HRS0#
AA41
HRS1#
U39
HRS2#
R32
HCLKP
U32
HCLKN
AM17
PWROK
C31
HCPURST#
AM18
RSTIN#
J13
ICH_SYNC#
D23
HRCOMP
C25
HSCOMP
D25
HSCOMP#
B25
HSWING
D24
HDVREF
B24
HAVREF
V_1P25_CORE
R135 49.9R1%0402
R132 49.9R1%0402
VTT_1
VTT_2
VCC_1
AJ12
VTT_3
VTT_4
VTT_5
VCC_2
VCC_3
VCC_4
AJ9
AJ11
AJ10
HXSCOMP
C131
X_C2.2P50N
HXSCOMPB
C130
X_C2.2P50N
PWRGD8,11,24
V_FSB_VTT
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
HXRCOMP
HXSCOMP
HXSCOMPB
HXSWING
MCH_GTLREF
5
H_A#[3..35]3
D D
C C
B B
A A
H_ADSTB#03
H_ADSTB#13
H_REQ#[0..4]3
H_ADS#3
H_LOCK#3
H_BR#03,4
H_BNR#3
H_BPRI#3
H_RS#[0..2]3
R141 16.9R1%
H_TRDY#3
H_DRDY#3
H_DEFER#3
H_HITM#3
H_HIT#3
H_DBSY#3
CK_H_MCH13
CK_H_MCH#13
H_CPURST#3,4
PLTRST#10
ICH_SYNC#11
V_FSB_VTT3,4,11,12,13,24,25
L24
L23
VTT_13
VCC_12
AH4
AH2
4
K24
K23
J24
J23
H24
H23
G26
G24
G23
F26
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
AH1
AG9
AG8
AG7
AG6
AG11
AG10
AG5
AG13
AG12
HXSWING S/B 1/4*VTT +/- 2%
V_FSB_VTT
R138
100R1%0402
4
F24
VTT_24
VTT_25
VCC_23
VCC_24
AG4
F23
E29
E27
VTT_26
VTT_27
VTT_28
VCC_25
VCC_26
VCC_27
AG3
AG2
AF13
R134
300R1%0402
E26
E23
D29
D28
D27
VTT_29
VTT_30
VTT_31
VTT_32
VTT_33
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
AF12
AF11
AD24
AD22
AD20
R139
49.9R1%0402
C135
C0.01U25X0402
C30
C29
C27
VTT_34
VTT_35
VCC_80
VCC_34
AC25
AC23
AC21
HXSWING
B30
B29
VTT_36
VTT_37
VCC_35
VCC_36
AC19
AC13
B28
B27
VTT_38
VTT_39
VCC_37
VCC_38
AC6
AB24
A30
VTT_40
VTT_41
VCC_39
VCC_40
AB22
A28
R27
VTT_42
VCC_41
AB20
AA25
R26
R24
VTT_43
VTT_44
VCC_42
VCC_43
AA23
AA21
V_FSB_VTT
3
V_1P25_CORE
R23
AG19
AG18
AG17
AG15
AG14
AF26
AF25
AF24
AF22
AF20
AF18
AF17
AF15
AF14
AE27
AE26
VTT_45
VTT_46
VCC_84
VCC_85
VCC_86
VCC_87
VCC_88
VCC_89
VCC_90
VCC_91
VCC_93
VCC_94
VCC_95
VCC_96
VCC_97
VCC_98
VCC_99
VCC_44
VCC_45
VCC_46
VCC_47
VCC_48
VCC_49
VCC_50
VCC_51
VCC_52Y6VCC_53
VCC_54
VCC_55
VCC_56V9VCC_57
VCC_58
VCC_59U9VCC_60U6VCC_61U3VCC_62
Y24
Y22
Y20
Y13
V13
V12
V10
U13
U10
R137
210R1%
N12
AA3
AA19
AA13
GTLREF VOLTAGE SHOULD BE 0.67*VTT=0.8V
100 OHM OVER 210 RESISTORS
R133 124R1%
3
AE25
AE23
AE21
AE19
AE17
AD27
AD26
VCC_100
VCC_101
VCC_102
VCC_103
VCC_104
VCC_105
VCC_106
VCC_63
VCC_64N9VCC_65N8VCC_66N6VCC_67N3VCC_68L6VCC_69J6VCC_70J3VCC_71J2VCC_72G2VCC_73
N11
CPU_MCH_GTLREF
R140 51R0402
C137
C1U16Y
VCC_107
AD18
VCC_108
AD17
VCC_109
AD15
AD14
AC27
AC26
VCC_110
VCC_111
VCC_112
VCC_74F9VCC_75D4VCC_76
F11
C136
X_C220P10X
2
AC17
AC15
AC14
AB27
VCC_113
VCC_114
VCC_115
VCC_116
VCC_117
VCC_77C9VCC_78
VCC_79
P20
Y11
C13
CPU_MCH_GTLREF 3
MCH_GTLREF
2
AB26
VCC_118
VCC_81
AG25
AB18
VCC_119
VCC_82
AG21
AB17
AG20
AA27
AA26
VCC_120
VCC_121
VCC_122
HD10
HD11
HD12
HD13
HD14
HD15
HD16
HD17
HD18
HD19
HD20
HD21
HD22
HD23
HD24
HD25
HD26
HD27
HD28
HD29
HD30
HD31
HD32
HD33
HD34
HD35
HD36
HD37
HD38
HD39
HD40
HD41
HD42
HD43
HD44
HD45
HD46
HD47
HD48
HD49
HD50
HD51
HD52
HD53
HD54
HD55
HD56
HD57
HD58
HD59
HD60
HD61
HD62
HD63
HDINV#0
HDINV#1
HDINV#2
HDINV#3
HDSTBP0#
HDSTBN0#
HDSTBP1#
HDSTBN1#
HDSTBP2#
HDSTBN2#
HDSTBP3#
HDSTBN3#
VCC_83
Broadwater-P
1
H_D#0
R40
HD0
H_D#1
P41
HD1
H_D#2
R41
HD2
H_D#3
N40
HD3
H_D#4
R42
HD4
H_D#5
M39
HD5
H_D#6
N41
HD6
H_D#7
N42
HD7
H_D#8
L41
HD8
H_D#9
J39
HD9
H_D#10
L42
H_D#11
J41
H_D#12
K41
H_D#13
G40
H_D#14
F41
H_D#15
F42
H_D#16
C42
H_D#17
D41
H_D#18
F38
H_D#19
G37
H_D#20
E42
H_D#21
E39
H_D#22
E37
H_D#23
C39
H_D#24
B39
H_D#25
G33
H_D#26
A37
H_D#27
F33
H_D#28
E35
H_D#29
K32
H_D#30
H32
H_D#31
B34
H_D#32
J31
H_D#33
F32
H_D#34
M31
H_D#35
E31
H_D#36
K31
H_D#37
G31
H_D#38
K29
H_D#39
F31
H_D#40
J29
H_D#41
F29
H_D#42
L27
H_D#43
K27
H_D#44
H26
H_D#45
L26
H_D#46
J26
H_D#47
M26
H_D#48
C33
H_D#49
C35
H_D#50
E41
H_D#51
B41
H_D#52
D42
H_D#53
C40
H_D#54
D35
H_D#55
B40
H_D#56
C38
H_D#57
D37
H_D#58
B33
H_D#59
D33
H_D#60
C34
H_D#61
B35
H_D#62
A32
H_D#63
D32
H_DBI#0
M40
H_DBI#1
J33
H_DBI#2
G29
H_DBI#3
E33
L40
M43
G35
H33
G27
H27
B38
D38
C122
4.7u/10V/8
MSI
Title
Size Document Number Rev
Date: Sheet
H_DSTBP#0 3
H_DSTBN#0 3
H_DSTBP#1 3
H_DSTBN#1 3
H_DSTBP#2 3
H_DSTBN#2 3
H_DSTBP#3 3
H_DSTBN#3 3
C127
C0.1U16Y0402
MICRO-STAR INt'L CO., LTD.
Intel Broadwater - CPU Signals
H_D#[0..63] 3
MS-7235
H_DBI#[0..3] 3
V_FSB_VTT
C126
C0.1U16Y0402
1
632Monday, December 26, 2005
0A
of
5
4
3
2
1
DATA_B39
DATA_B38
AN35
AR37
SDQ_B38
SDQ_A38
AP41
AR42
DATA_A38
DATA_A39
DATA_B41
DATA_B40
DATA_B42
AM35
AM38
SDQ_B39
SDQ_B40
SDQ_B41
SDQ_A39
SDQ_A40
SDQ_A41
AN41
AM39
DATA_A42
DATA_A40
DATA_A41
DATA_B43
AJ34
AL38
SDQ_B42
SDQ_B43
SDQ_A42
SDQ_A43
AK42
AK41
DATA_A43
SCKE_B[0..3]18,19
DATA_B45
DATA_B44
AR39
AM34
SDQ_B44
SDQ_B45
SDQ_A44
SDQ_A45
AN40
AN42
DATA_A44
DATA_A45
DATA_B46
DATA_B47
AL37
AL32
SDQ_B46
SDQ_B47
SDQ_A46
SDQ_A47
AL42
AL39
DATA_A46
DATA_A47
DATA_B48
DATA_B49
AG38
AJ38
SDQ_B48
SDQ_A48
AJ40
AH43
DATA_A48
DATA_A49
DATA_B52
DATA_B51
DATA_B50
AF35
AF33
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_A49
SDQ_A50
SDQ_A51
AF39
AE40
DATA_A52
DATA_A50
DATA_A51
DATA_B[0..63]18
DATA_B7
DATA_B8
AU7
AT11
SDQ_B6
SDQ_B7
SDQ_A6
SDQ_A7
AV4
AY2
DATA_A8
DATA_A7
DATA_B10
DATA_B9
AP13
AU11
SDQ_B8
SDQ_B9
SDQ_B10
SDQ_A8
SDQ_A9
SDQ_A10
AY3
BB5
DATA_A9
DATA_A10
DATA_B11
DATA_B12
AR13
AR11
SDQ_B11
SDQ_A11
AY6
AW2
DATA_A11
DATA_A12
DATA_B13
DATA_B15
DATA_B14
AU9
AV12
SDQ_B12
SDQ_B13
SDQ_B14
SDQ_A12
SDQ_A13
SDQ_A14
BA5
AW3
DATA_A14
DATA_A13
DATA_A15
DATA_B16
DATA_B17
AU12
AU15
AV13
SDQ_B15
SDQ_B16
SDQ_A15
SDQ_A16
BB4
AY7
BC7
DATA_A16
DATA_A17
DATA_B18
DATA_B19
AU17
AT17
SDQ_B17
SDQ_B18
SDQ_B19
SDQ_A17
SDQ_A18
SDQ_A19
AY11
AW11
DATA_A19
DATA_A18
DATA_B21
DATA_B20
AU13
AM13
SDQ_B20
SDQ_B21
SDQ_A20
SDQ_A21
BB6
BA6
DATA_A21
DATA_A20
DATA_B23
DATA_B22
AV15
AW17
SDQ_B22
SDQ_B23
SDQ_A22
SDQ_A23
BA10
BB10
DATA_A23
DATA_A22
DATA_B25
DATA_B24
AV24
AT23
SDQ_B24
SDQ_B25
SDQ_A24
SDQ_A25
AT18
AR18
DATA_A24
DATA_A25
DATA_B27
DATA_B26
AT26
AP26
SDQ_B26
SDQ_B27
SDQ_A26
SDQ_A27
AT21
AU21
DATA_A26
DATA_A27
DATA_B29
DATA_B28
AU23
AW23
SDQ_B28
SDQ_B29
SDQ_A28
SDQ_A29
AP17
AN17
DATA_A29
DATA_A28
DATA_B30
DATA_B31
AR24
AN26
SDQ_B30
SDQ_A30
AP20
AV20
DATA_A31
DATA_A30
DATA_B32
DATA_B33
AW37
AV38
SDQ_B31
SDQ_B32
SDQ_B33
SDQ_A31
SDQ_A32
SDQ_A33
AV42
AU40
DATA_A32
DATA_A33
DATA_B34
DATA_B35
AN36
AN37
SDQ_B34
SDQ_B35
SDQ_A34
SDQ_A35
AP42
AN39
DATA_A34
DATA_A35
DATA_B37
DATA_B36
AU35
AR35
SDQ_B36
SDQ_B37
SDQ_A36
SDQ_A37
AV40
AV41
DATA_A36
DATA_A37
DATA_B5
DATA_B0
DATA_B3
DATA_B4
DATA_B2
DATA_B6
U8B
SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#
SRAS_A#
SCAS_A#
SWE_A#
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
SMA_A13
SMA_A14
SODT_A0
SODT_A1
SODT_A2
SODT_A3
SBS_A0
SBS_A1
SBS_A2
SDQS_A0
SDQS_A0#
SDQS_A1
SDQS_A1#
SDQS_A2
SDQS_A2#
SDQS_A3
SDQS_A3#
SDQS_A4
SDQS_A4#
SDQS_A5
SDQS_A5#
SDQS_A6
SDQS_A6#
SDQS_A7
SDQS_A7#
SCLK_A0
SCLK_A0#
SCLK_A1
SCLK_A1#
SCLK_A2
SCLK_A2#
SCLK_A3
SCLK_A3#
SCLK_A4
SCLK_A4#
SCLK_A5
SCLK_A5#
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
DATA_B1
AN7
AN8
SDQ_B0
SDQ_A0
AR5
AR4
DATA_A1
DATA_A0
AW5
AW7
SDQ_B1
SDQ_B2
SDQ_A1
SDQ_A2
AV3
AV2
DATA_A3
DATA_A2
AN5
AN6
SDQ_B3
SDQ_B4
SDQ_A3
SDQ_A4
AP3
AP2
DATA_A4
DATA_A5
AN9
SDQ_B5
SDQ_A5
AU1
DATA_A6
D D
SCS_A#[0..3]17,19
RAS_A#17,19
CAS_A#17,19
WE_A#17,19
MAA_A[0..14]17,19
C192
ODT_A[0..3]17,19
SBS_A[0..2]17,19
DQS_A017
DQS_A#017
DQS_A117
DQS_A#117
DQS_A217
DQS_A#217
DQS_A317
DQS_A#317
DQS_A417
DQS_A#417
DQS_A517
DQS_A#517
DQS_A617
DQS_A#617
DQS_A717
DQS_A#717
P_DDR0_A17
N_DDR0_A17
P_DDR1_A17
N_DDR1_A17
P_DDR2_A17
N_DDR2_A17
P_DDR3_A17
N_DDR3_A17
P_DDR4_A17
N_DDR4_A17
P_DDR5_A17
N_DDR5_A17
R173 20R1%0402
R172 20R1%0402
R125 20R1%0402
R124 20R1%0402
C C
B B
VCC_DDR
C0.1U16Y0402
A A
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
MAA_A13
MAA_A14
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SRCOMP0
SRCOMP1
SRCOMP2
SRCOMP3
AW35
BA35
BA34
BB38
BB33
AY35
BB34
BA31
BB25
BA26
BA25
AY25
BA23
AY24
AY23
BB23
BA22
AY33
BB22
AW21
AY38
BA21
AY37
BA38
BB35
BA39
BA33
AW32
BB21
AU4
AR3
BB3
BA4
BB9
BA9
AT20
AU18
AR41
AR40
AL41
AL40
AG42
AG41
AC42
AC41
AU31
AR31
AP27
AN27
AV33
AW33
AP29
AP31
AM26
AM27
AT33
AU33
AN2
AN3
BB40
BA40
DATA_A[0..63]17
DATA_B54
DATA_B53
AJ37
AJ35
SDQ_B52
SDQ_B53
SDQ_A52
SDQ_A53
AJ42
AJ41
DATA_A54
DATA_A53
SCKE_A[0..3]17,19
DATA_B56
DATA_B55
AG33
AF34
SDQ_B54
SDQ_B55
SDQ_A54
SDQ_A55
AF41
AF42
DATA_A56
DATA_A55
DATA_B58
DATA_B57
AD36
AC33
SDQ_B56
SDQ_B57
SDQ_A56
SDQ_A57
AD40
AD43
DATA_A58
DATA_A57
DQM_A[0..7]17
DQM_B[0..7]18
DATA_B60
DATA_B59
AA34
AA36
SDQ_B58
SDQ_B59
SDQ_A58
SDQ_A59
AB41
AA40
DATA_A59
DATA_A60
DATA_B61
DATA_B62
AD34
AF38
SDQ_B60
SDQ_B61
SDQ_A60
SDQ_A61
AE42
AE41
DATA_A62
DATA_A61
DATA_B63
AC34
AA33
SDQ_B62
SDQ_B63
SDQ_A62
SDQ_A63
AB42
AC39
DATA_A63
SCKE_B1
SCKE_B0
SCKE_B2
AY12
AW12
BB11
SCKE_B0
SCKE_B1
SCKE_A0
SCKE_A1
AY20
AY21
BC20
SCKE_A1
SCKE_A0
SCKE_A2
SCKE_B3
DQM_B0
BA11
SCKE_B2
SCKE_B3
SCKE_A2
SCKE_A3
BA19
SCKE_A3
DQM_A0
DQM_B1
AR7
AW9
SDM_B0
SDM_A0
BA2
AR2
DQM_A1
DQM_B3
DQM_B2
AW13
AP23
SDM_B1
SDM_B2
SDM_A1
SDM_A2
AY9
AN18
DQM_A2
DQM_A3
DQM_B4
DQM_B5
AU37
AM37
SDM_B3
SDM_B4
SDM_A3
SDM_A4
AU43
AM43
DQM_A4
DQM_A5
DQM_B6
DQM_B7
AG39
AD38
SDM_B5
SDM_B6
SDM_B7
SMRCOMPVOL
SMRCOMPVOH
SDM_A5
SDM_A6
SDM_A7
AC40
AG40
DQM_A6
DQM_A7
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMA_B0
SMA_B1
SMA_B2
SMA_B3
SMA_B4
SMA_B5
SMA_B6
SMA_B7
SMA_B8
SMA_B9
SMA_B10
SMA_B11
SMA_B12
SMA_B13
SMA_B14
SODT_B0
SODT_B1
SODT_B2
SODT_B3
SBS_B0
SBS_B1
SBS_B2
SDQS_B0
SDQS_B0#
SDQS_B1
SDQS_B1#
SDQS_B2
SDQS_B2#
SDQS_B3
SDQS_B3#
SDQS_B4
SDQS_B4#
SDQS_B5
SDQS_B5#
SDQS_B6
SDQS_B6#
SDQS_B7
SDQS_B7#
SCLK_B0
SCLK_B0#
SCLK_B1
SCLK_B1#
SCLK_B2
SCLK_B2#
SCLK_B3
SCLK_B3#
SCLK_B4
SCLK_B4#
SCLK_B5
SCLK_B5#
SVREF
Broadwater-P
BB27
BB30
AY27
AY31
AW26
AW29
BA27
BB17
AY17
BA17
BC16
AW15
BA15
BB15
BA14
AY15
BB14
AW18
BB13
BA13
AY29
AY13
BA29
BA30
BB29
BB31
AY19
BA18
BC12
AV6
AU5
AR12
AP12
AP15
AR15
AT24
AU26
AW39
AU39
AL35
AL34
AG35
AG36
AC36
AC37
AV31
AW31
AU27
AT27
AV32
AT32
AU29
AR29
AV29
AW27
AN33
AP32
AM6
AM8
AM10
VCC_DDR
SCS_B#0
SCS_B#1
SCS_B#2
SCS_B#3
RAS_B#
CAS_B#
WE_B#
MAA_B0
MAA_B1
MAA_B2
MAA_B3
MAA_B4
MAA_B5
MAA_B6
MAA_B7
MAA_B8
MAA_B9
MAA_B10
MAA_B11
MAA_B12
MAA_B13
MAA_B14
ODT_B0
ODT_B1
ODT_B2
ODT_B3
SBS_B0
SBS_B1
SBS_B2
DQS_B0
DQS_B#0
DQS_B1
DQS_B#1
DQS_B2
DQS_B#2
DQS_B3
DQS_B#3
DQS_B4
DQS_B#4
DQS_B5
DQS_B#5
DQS_B6
DQS_B#6
DQS_B7
DQS_B#7
P_DDR0_B
N_DDR0_B
P_DDR1_B
N_DDR1_B
P_DDR2_B
N_DDR2_B
P_DDR3_B
N_DDR3_B
P_DDR4_B
N_DDR4_B
P_DDR5_B
N_DDR5_B
MCH_VREF_A
DDR_RCOMPVOL
DDR_RCOMPVOH
R186 1KR1%0402
SCS_B#[0..3] 18,19
RAS_B# 18,19
CAS_B# 18,19
WE_B# 18,19
MAA_B[0..14] 18,19
ODT_B[0..3] 18,19
SBS_B[0..2] 18,19
DQS_B0 18
DQS_B#0 18
DQS_B1 18
DQS_B#1 18
DQS_B2 18
DQS_B#2 18
DQS_B3 18
DQS_B#3 18
DQS_B4 18
DQS_B#4 18
DQS_B5 18
DQS_B#5 18
DQS_B6 18
DQS_B#6 18
DQS_B7 18
DQS_B#7 18
P_DDR0_B 18
N_DDR0_B 18
P_DDR1_B 18
N_DDR1_B 18
P_DDR2_B 18
N_DDR2_B 18
P_DDR3_B 18
N_DDR3_B 18
P_DDR4_B 18
N_DDR4_B 18
P_DDR5_B 18
N_DDR5_B 18
C193
C0.01U25X0402
C198
C0.01U25X0402
R185
1KR1%0402
R178 1KR1%0402
R177
3.01KR1%0402
R184 1KR1%0402
MCH_VREF_A
C199
C0.1U16Y0402
PLACE 0.1UF CAP CLOSE TO MCH
VCC_DDR
DDR_RCOMPVOH = 0.2 * VCC_DDR
DDR_RCOMPVOH = 0.8 * VCC_DDR
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Broadwater - Memory Signals
MS-7235
1
732Monday, December 26, 2005
of
0A
5
V_1P25_CL
V_1P25_CL
AL26
VCC_CL_1
VCC_EXP_1
VCC_EXP_2
AD11
AD10
EXP_A_RXP_020
EXP_A_RXN_020
EXP_A_RXP_120
D D
C C
0:GMCH's PCI Express lane numbers
are reversed(BTX Platforms)
1:Normal operation(ATX Platforms)
V_1P25_CORE
EXP_PRSNT_N20
B B
V_1P25_CL
A A
V_1P25_CORE
EXP_A_RXN_120
EXP_A_RXP_220
EXP_A_RXN_220
EXP_A_RXP_320
EXP_A_RXN_320
EXP_A_RXP_420
EXP_A_RXN_420
EXP_A_RXP_520
EXP_A_RXN_520
EXP_A_RXP_620
EXP_A_RXN_620
EXP_A_RXP_720
EXP_A_RXN_720
EXP_A_RXP_820
EXP_A_RXN_820
EXP_A_RXP_920
EXP_A_RXN_920
EXP_A_RXP_1020
EXP_A_RXN_1020
EXP_A_RXP_1120
EXP_A_RXN_1120
EXP_A_RXP_1220
EXP_A_RXN_1220
EXP_A_RXP_1320
EXP_A_RXN_1320
EXP_A_RXP_1420
EXP_A_RXN_1420
EXP_A_RXP_1520
EXP_A_RXN_1520
DMI_ITP_MRP_010
DMI_ITN_MRN_010
DMI_ITP_MRP_110
DMI_ITN_MRN_110
DMI_ITP_MRP_210
DMI_ITN_MRN_210
DMI_ITP_MRP_310
DMI_ITN_MRN_310
CK_PE_100M_MCH13
CK_PE_100M_MCH#13
SDVO_CTRL_DATA20
SDVO_CTRL_CLK20
R148 1KR1%0402
R149 X_1KR1%0402
CP13
X_COPPER
CP15
X_COPPER
X_.CD220U10EL7
5
R145 X_0R
EC53
V_1P25_CL
L8 X_10U100m_0805
L11 X_10U100m_0805
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
H_BSL0
H_BSL013
H_BSL1
H_BSL113
H_BSL2
H_BSL213
R164 0R
VCC_CL_PLL
VCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
V_3P3_DAC_FILTERED
VCC3
VCCA_MPLL
C140
C10U10Y0805
VCCA_DPLLB
+
12
C154
C0.1U16Y0402
EXP_SLR
EXP_EN
U8C
F15
EXP_RXP0
G15
EXP_RXN0
K15
EXP_RXP1
J15
EXP_RXN1
F12
EXP_RXP2
E12
EXP_RXN2
J12
EXP_RXP3
H12
EXP_RXN3
J11
EXP_RXP4
H11
EXP_RXN4
F7
EXP_RXP5
E7
EXP_RXN5
E5
EXP_RXP6
F6
EXP_RXN6
C2
EXP_RXP7
D2
EXP_RXN7
G6
EXP_RXP8
G5
EXP_RXN8
L9
EXP_RXP9
L8
EXP_RXN9
M8
EXP_RXP10
M9
EXP_RXN10
M4
EXP_RXP11
L4
EXP_RXN11
M5
EXP_RXP12
M6
EXP_RXN12
R9
EXP_RXP13
R10
EXP_RXN13
T4
EXP_RXP14
R4
EXP_RXN14
R6
EXP_RXP15
R7
EXP_RXN15
W2
DMI_RXP0
V1
DMI_RXN0
Y8
DMI_RXP1
Y9
DMI_RXN1
AA7
DMI_RXP2
AA6
DMI_RXN2
AB3
DMI_RXP3
AA4
DMI_RXN3
B12
GCLKP
B13
GCLKN
G17
SDV0_CTRLDATA
E17
SDVO_CTRLCLK
G20
BSEL0
J20
BSEL1
J18
BSEL2
G18
MTYPE
E18
EXP_SLR
J17
EXP_EN
Y32
VCC_CL_PLL
C23
VCCA_HPLL
A24
VCCA_MPLL
A22
VCCA_DPLLA
C22
VCCA_DPLLB
B15
VCCA_EXPPLL
C17
VCCA_DAC_17
B16
VCCA_DAC_18
A16
VCCA_EXP_19
C21
VCCD_CRT_20
B21
VCCDQ_CRT_21
D16
VSS_1
B17
VCC33
Broadwater-P
V_1P25_CORE
V_1P25_CORE
C141
C0.1U16Y0402
AL24
AL23
AL21
AL20
AL18
VCC_CL_2
VCC_CL_3
VCC_CL_4
VCC_CL_5
VCC_CL_6
VCC_EXP_3
VCC_EXP_4
VCC_EXP_5
VCC_EXP_6
VCC_EXP_7
AD9
AD8
AD7
AD6
AD5
L9 X_10U100m_0805
L7 X_10U100m_0805
4
AK29
AK27
AL17
AL15
AK30
VCC_CL_7
VCC_CL_8
VCC_CL_9
VCC_CL_10
VCC_CL_11
VCC_EXP_8
VCC_EXP_9
VCC_EXP_10
VCC_EXP_11
VCC_EXP_12
AD4
AD2
AD1
AC4
AC3
VCC_DDR
CP14
X_COPPER
X_.CD220U10EL7
CP12
X_COPPER
X_C10U10Y0805
4
AJ31
AG31
AF31
AD32
VCC_CL_12
VCC_CL_13
VCC_CL_14
VCC_EXP_13
VCC_EXP_14
VCC_EXP_15
AE4
AE3
AE2
AC2
EC52
C144
AC32
AA32
AJ30
AJ29
VCC_CL_15
VCC_CL_16
VCC_CL_17
VCC_CL_18
VCC_CL_19
VCC_EXP_16
VCCSM_1
VCCSM_2
VCCSM_3
BC39
BC34
BC30
VCCA_DPLLA
+
12
VCCA_HPLL
AJ27
AG30
AG29
VCC_CL_20
VCC_CL_21
VCC_CL_22
VCCSM_4
VCCSM_5
VCCSM_6
BC26
BC22
BC18
C151
C0.1U16Y0402
C145
C0.1U16Y0402
AG27
AG26
AF30
AF29
VCC_CL_23
VCC_CL_24
VCC_CL_25
VCCSM_7
VCCSM_8
VCCSM_9
BB39
BB37
BB32
BC14
AF27
AD30
AD29
AC30
VCC_CL_26
VCC_CL_27
VCC_CL_28
VCC_CL_29
VCCSM_10
VCCSM_11
VCCSM_12
VCCSM_13
BB28
BB26
BB24
BB20
V_1P25_CORE
AC29
AL12
AL11
VCC_CL_30
VCC_CL_31
VCC_CL_32
VCC_CL_33
VCCSM_14
VCCSM_15
VCCSM_16
VCCSM_17
BB18
BB16
BB12
AL10
AL9
AL8
AL7
AL6
VCC_CL_34
VCC_CL_35
VCC_CL_36
VCC_CL_37
VCCSM_18
VCCSM_19
VCCSM_20
VCCSM_21
AY32
AV26
AV18
AW24
AW20
C107
C0.1U16Y0402
CP16
X_COPPER
L12
X_10U100m_0805
V_1P25_CORE
AL5
AL4
AL3
VCC_CL_38
VCC_CL_39
VCC_CL_40
VCC_CL_41
VCCSM_22
VCC_SMCLK_1
BB41
3
AL2
AK26
AK24
AK23
AK21
VCC_CL_42
VCC_CL_43
VCC_CL_44
VCC_CL_45
VCC_SMCLK_5
VCC_SMCLK_4
VCC_SMCLK_3
VCC_SMCLK_2
BA43
BB42
AY42
BA42
R162 0R
R161 0R
X_C10U10Y0805
3
AK20
AK18
AK17
AK15
VCC_CL_46
VCC_CL_47
VCC_CL_48
VCC_CL_49
VCC_CL_50
RESERVED_2
RESERVED_3
RESERVED_1
H18
BB19
AN21
V_CKDDR
L6 X_10U100m_0805
R122 1R1%
R123 1R1%
C165
AK3
AK2
AK1
AJ13
VCC_CL_51
VCC_CL_52
VCC_CL_53
VCC_CL_54
RESERVED_4
RESERVED_5
RESERVED_6
RESERVED_7
BB2
AN32
AM31
AW42
CP11
X_COPPER
VCCA_GPLL
C171
C10U10Y0805
C189
X_C10U10Y0805
AD31
AC31
AA31
Y31
VCC_CL_55
VCC_CL_56
VCC_CL_57
VCC_CL_58
RESERVED_8
RESERVED_9
RESERVED_10
RESERVED_11
AL31
AF32
AG32
AM21
C163
C0.1U16Y0402
AJ26
AJ24
AJ23
AJ21
AJ20
VCC_CL_59
VCC_CL_60
VCC_CL_61
VCC_CL_62
RESERVED_12
RESERVED_13
RESERVED_14
RESERVED_15
Y12
AA9
AJ32
AA10
AA11
C102
C10U10Y0805
AJ18
AJ17
AJ15
AJ14
AA30
VCC_CL_63
VCC_CL_64
VCC_CL_65
VCC_CL_66
VCC_CL_67
RESERVED_16
RESERVED_17
RESERVED_18
RESERVED_19
RESERVED_20
U30
U31
R29
R30
U12
VCC_DDR
VCC3
AA29
Y30
Y29
V30
V29
VCC_CL_68
VCC_CL_69
VCC_CL_70
VCC_CL_71
VCC_CL_72
RESERVED_25
RESERVED_21
RESERVED_22
RESERVED_23
RESERVED_24
F13
U11
R12
R13
AP21
L10 0.1U50m
C10U10Y0805
U29
U27
AL13
AK14
AL29
VCC_CL_73
VCC_CL_74
VCC_CL_75
VCC_CL_76
VCC_CL_77
RESERVED_28
RESERVED_27
RESERVED_26
V31
AA39
BC43
T13T2
C161
2
AL27
EXP_TXP0
EXP_TXN0
EXP_TXP1
EXP_TXN1
VCC_CL_78
VCC_CL_79
EXP_TXP2
EXP_TXN2
EXP_TXP3
EXP_TXN3
EXP_TXP4
EXP_TXN4
EXP_TXP5
EXP_TXN5
EXP_TXP6
EXP_TXN6
EXP_TXP7
EXP_TXN7
EXP_TXP8
EXP_TXN8
EXP_TXP9
EXP_TXN9
EXP_TXP10
EXP_TXN10
EXP_TXP11
EXP_TXN11
EXP_TXP12
EXP_TXN12
EXP_TXP13
EXP_TXN13
EXP_TXP14
EXP_TXN14
EXP_TXP15
EXP_TXN15
DMI_TXP0
DMI_TXN0
DMI_TXP1
DMI_TXN1
DMI_TXP2
DMI_TXN2
DMI_TXP3
DMI_TXN3
EXP_COMPO
EXP_COMPI
HSYNC
VSYNC
GREEN
GREEN#
BLUE#
DDC_DATA
DDC_CLK
DREFCLKP
DREFCLKN
REFSET
CL_PWROK
CL_RST#
CL_VERF
CL_CLK
CL_DATA
ALLZTEST
XORTEST
TESTIN#
TEST2
TEST1
TEST0
A43
BC1
T14
V_3P3_DAC_FILTERED
C160
C0.1U16Y0402
2
RED
BLUE
RED#
D11
D12
B11
A10
C10
D9
B9
B7
D7
D6
B5
B6
B3
B4
F2
E2
F4
G4
J4
K3
L2
K1
N2
M2
P3
N4
R2
P1
U2
T2
V3
U4
V7
V6
W4
Y4
AC8
AC9
Y2
AA2
AC11
AC12
C15
D15
B18
C19
B20
C18
D19
D20
L13
M13
C14
D13
A20
AM15
AA12
AM5
AD13
AD12
K20
F20
A14
EXP_A_TXP_0
EXP_A_TXN_0
EXP_A_TXP_1
EXP_A_TXN_1
EXP_A_TXP_2
EXP_A_TXN_2
EXP_A_TXP_3
EXP_A_TXN_3
EXP_A_TXP_4
EXP_A_TXN_4
EXP_A_TXP_5
EXP_A_TXN_5
EXP_A_TXP_6
EXP_A_TXN_6
EXP_A_TXP_7
EXP_A_TXN_7
EXP_A_TXP_8
EXP_A_TXN_8
EXP_A_TXP_9
EXP_A_TXN_9
EXP_A_TXP_10
EXP_A_TXN_10
EXP_A_TXP_11
EXP_A_TXN_11
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_MTP_IRP_0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3
GRCOMP
R155
10KR0402
R160 10KR0402
PWRGD
CL_VREF_MCH
T1
C157
C0.01U25X0402
1
Place close to GMCH
EXP_A_TXP_0 20
EXP_A_TXN_0 20
EXP_A_TXP_1 20
EXP_A_TXN_1 20
EXP_A_TXP_2 20
EXP_A_TXN_2 20
EXP_A_TXP_3 20
EXP_A_TXN_3 20
EXP_A_TXP_4 20
EXP_A_TXN_4 20
EXP_A_TXP_5 20
EXP_A_TXN_5 20
EXP_A_TXP_6 20
EXP_A_TXN_6 20
EXP_A_TXP_7 20
EXP_A_TXN_7 20
EXP_A_TXP_8 20
EXP_A_TXN_8 20
EXP_A_TXP_9 20
EXP_A_TXN_9 20
EXP_A_TXP_10 20
EXP_A_TXN_10 20
EXP_A_TXP_11 20
EXP_A_TXN_11 20
EXP_A_TXP_12 20
EXP_A_TXN_12 20
EXP_A_TXP_13 20
EXP_A_TXN_13 20
EXP_A_TXP_14 20
EXP_A_TXN_14 20
EXP_A_TXP_15 20
EXP_A_TXN_15 20
DMI_MTP_IRP_0 10
DMI_MTN_IRN_0 10
DMI_MTP_IRP_1 10
DMI_MTN_IRN_1 10
DMI_MTP_IRP_2 10
DMI_MTN_IRN_2 10
DMI_MTP_IRP_3 10
DMI_MTN_IRN_3 10
R168
24.9R1%0402
VCC3 VCC3
R156
X_10KR0402
V_1P25_CORE
PWRGD 6,11,24
CL_RST 11
CL_N_CLK 11
CL_N_DATA 11
V_1P25_CORE
R150
10KR0402
R151
X_10KR0402
BSEL
2
0
0
0
MICRO-STAR INt'L CO., LTD.
MSI
Title
Intel Broadwater PCI-Express & RBG Signals
Size Document Number Rev
Date: Sheet
VCC_DDR
C155
C2.2U6.3Y
C147
C2.2U6.3Y
C138
C2.2U6.3Y
C128
C2.2U6.3Y
C119
C2.2U6.3Y
C112
C2.2U6.3Y
MCH MEMORY DECOUPLING
V_1P25_CL
C177
C10U10Y0805
C187
C10U10Y0805
MCH CL DECOUPLING
V_1P25_CORE
C185
C10U10Y0805
C173
C10U10Y0805
C184
C10U10Y0805
C186
C10U10Y0805
C183
C10U10Y0805
C201
C10U10Y0805
C295
C10U10Y0805
C344
C10U10Y0805
C190
C10U10Y0805
C169
C1U16Y
C181
C1U16Y
C188
C1U16Y
C182
C1U16Y
MCH CORE DECOUPLING
CL_VREF_MCH = 0.352V (FOR NOW)
V_1P25_CL
R171
1KR1%0402
CL_VREF_MCH
R180
392R1%0402
1 2
TABLE
PSB FREQUENCY
0
1
266 MHz (1066)
0
0
133 MHZ (533)
0
1
200 MHZ (800)
1
0
MS-7235
1
832Monday, December 26, 2005
of
C194
C0.01U25X0402
0A
5
V_1P25_CORE
AA17
AA15
AA14
Y27
Y26
Y18
Y17
Y15
Y14
W27
W26
W25
W23
W21
W19
W18
W17
V27
V26
V25
V24
VCC_138
VCC_139
VCC_140
VCC_141
V23
VCC_142
VCC_143
U8D
D D
C C
B B
BC37
BC32
BC28
BC24
BC10
BC5
BB7
AY41
AY4
AW43
AW41
AW1
AV37
AV35
AV27
AV23
AV21
AV17
AV11
AV9
AV7
AU42
AU38
AU32
AU24
AU20
AU6
AU2
AT31
AT29
AT15
AT13
AT12
AR38
AR33
AR32
AR27
AR26
AR23
AR21
AR20
AR17
AR9
AR6
AP43
AP24
AP18
AP1
AN38
AN31
AN29
AN24
AN23
AN20
AN15
AN13
AN12
AN11
AN4
AM42
AM40
AM36
AM33
AM29
AM24
AM23
AM20
AM11
AM9
AM7
AM4
AM2
AM1
AL36
AL33
AK43
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VCC_123
VCC_124
VCC_125
VCC_126
VCC_127
VCC_128
VCC_129
VCC_130
VCC_131
VCC_132
VCC_133
VCC_134
VCC_135
VCC_136
VCC_137
V22
V21
VCC_144
VCC_145
V20
V19
VCC_146
VCC_147
4
V18
V17
VCC_148
VCC_149
V15
V14
VCC_150
VCC_151
U26
U25
VCC_152
VCC_153
U24
U23
VCC_154
VCC_155
U22
U21
VCC_156
VCC_157
U20
U19
VCC_158
VCC_159
U18
U17
VCC_160
VCC_161
U15
U14
VCC_162
VCC_163
R20
R18
VCC_164
VCC_165
R17
R15
VCC_166
VCC_167
R14
P15
VCC_168
VCC_169
P14
AG24
VCC_170
VCC_171
AG23
AG22
VCC_172
VCC_173
VCC_174
3
M20
L15
L18
M18
F17
L17
N17
N18
N15
RESERVED_29
RESERVED_30
RESERVED_31
K17
N20
BC42
BC2
BB43
BB1
B43
B42
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
RESERVED_33
RESERVED_34
RESERVED_35
RESERVED_36
RESERVED_37
RESERVED_32
RESERVED_38
NC_7
A42
NC_8B2NC_9
M11
L12
VSS
VCC
VSS_293A3VSS_292A5VSS_291
A41
C43
VSS_290C1VSS_289
R21
VSS_288E1VSS_287
2
W20
VSS_286
W22
VSS_285
W24
VSS_284
AA18
VSS_283
1
M42
VSS_270
M35
VSS_269
M37
VSS_268
VSS_267
VSS_266N5VSS_265N7VSS_264
N10
VSS_263
VSS_262
VSS_261
VSS_260
VSS_259
VSS_258
VSS_257
VSS_256
VSS_255
VSS_254
VSS_253
VSS_252
VSS_251
VSS_250
VSS_249
VSS_248
VSS_247
VSS_246
VSS_245
VSS_244
VSS_243
VSS_242
VSS_241
VSS_240
VSS_239
VSS_238
VSS_237
VSS_236
VSS_235
VSS_234
VSS_233
VSS_232
VSS_231
VSS_230
VSS_229
VSS_228
VSS_227
VSS_226
VSS_225
VSS_224
VSS_223
VSS_222
VSS_221
VSS_220
VSS_219
VSS_218
VSS_217
VSS_216
VSS_215
VSS_214
VSS_213
VSS_212
VSS_211
VSS_210
VSS_209
VSS_208
VSS_207
VSS_206
VSS_205
VSS_204
VSS_203
VSS_202
VSS_201
VSS_200
VSS_199
VSS_198
VSS_197
VSS_196
VSS_195
VSS_194
VSS_193
VSS_192
VSS_191
VSS_190
VSS_189
VSS_188
N13
N21
N27
N31
N33
N36
P2
P17
P18
P21
P30
P43
R3
R5
R8
R11
R31
R33
R36
T1
T42
U5
U7
U8
U35
U38
V2
V5
V8
V11
V32
V34
V37
V39
V43
W3
Y1
Y5
Y7
Y10
Y19
Y21
Y23
Y25
Y33
Y35
Y37
Y42
AA5
AA8
AA20
AA22
AA24
AA35
AA38
AB1
AB2
AB19
AB21
AB23
AB25
AB43
AC5
AC7
AC10
AC20
AC22
AC24
AC35
AC38
AD19
AD21
AD23
AD25
AD33
AD35
AC18
AE18
AE20
AE22
AE24
AF19
AF21
AF23
AY40
BA1
BC3
BC41
M33
VSS_282
VSS_281
VSS_280
VSS_279
VSS_278
VSS_277
VSS_276
VSS_275
VSS_274
VSS_273
VSS_272
VSS_271
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96M7VSS_97M1VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105L7VSS_106L5VSS_107L3VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114K2VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120J9VSS_121J7VSS_122J5VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137G9VSS_138G7VSS_139G1VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145F3VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154E9VSS_155E3VSS_156
VSS_157
VSS_158
VSS_159
VSS_160D3VSS_161
VSS_162
VSS_163C6VSS_164C5VSS_165C4VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180A7VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
J38
J35
J32
J27
L33
L32
L31
L29
L21
L20
L11
K43
K26
K21
K18
K13
AF9
AF8
AF7
AF6
M27
M21
M17
M15
AJ39
AJ36
AJ33
AF43
AF37
AF36
A A
5
AH42
AF10
AG37
AG34
M10
4
K12
J21
H31
H29
H21
H20
H17
H15
H13
G42
G38
G32
G21
G13
F37
F35
F27
F21
F18
E43
E32
E24
E21
E20
E15
E13
E11
D40
D31
D21
G12
G11
3
D17
C26
C11
B37
B32
B31
B26
B23
B22
B19
B14
B10
A39
A34
A26
A18
A12
AF5
AF3
AF2
MSI
Title
Size Document Number Rev
2
Date: Sheet
Broadwater-P
AF1
AD42
AD39
AD37
MICRO-STAR INt'L CO., LTD.
Intel Broadwater - GND
MS-7235
932Monday, December 26, 2005
1
of
0A
5
AD0
AD[31..0]16,21
D D
C C
PCIRST_ICH8#24
B B
SPI_MOSI_F
SPI_CS0_F# SPI_CS0#
SPI_CLK_F
V_3P3_CL
SPI FLASH
A A
C_BE#[3..0]16,21
R332 15/4
R328 15/4
R340 15/4
R333 10K/4
R336 10K/4
R324 10K/4
SPI_CS0_F#
SPI_MISO
DEVSEL#16,21
FRAME#16,21
IRDY#16,21
TRDY#16,21
STOP#16,21
PAR16,21
LOCK#21
SERR#16,21
PERR#16,21
PCI_PME#16,21
ICH_PCLK13
R386 10/4
PREQ#021
PREQ#121
PREQ#221
PREQ#316,21
PGNT#021
PGNT#121
PGNT#221
PGNT#316
PIRQ#A21
PIRQ#B21
PIRQ#C21
PIRQ#D21
PIRQ#E21
PIRQ#F16,21
PIRQ#G21
PIRQ#H21
SERIRQ14
V_3P3_CL
R379 15/4
R380 X_2.2K/4
5
SPI_MOSI
SPI_MISO
SPI_CLK
SPI_CS1#
SPI_MOSI
SPI_MISO
SPI_CS0#
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C_BE#0
C_BE#1
C_BE#2
C_BE#3
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PGNT#0
PGNT#1
PGNT#2
PGNT#3
SERIRQ
R378
2.2K/4
E18
AD0
A16
AD1
A14
AD2
A17
AD3
B13
AD4
F18
AD5
E17
AD6
C17
AD7
A13
AD8
C14
AD9
E14
AD10
C13
AD11
E15
AD12
F16
AD13
A11
AD14
D10
AD15
C11
AD16
E13
AD17
E12
AD18
D13
AD19
F14
AD20
E11
AD21
D8
AD22
D7
AD23
C7
AD24
F13
AD25
B7
AD26
C6
AD27
B5
AD28
F12
AD29
F8
AD30
E7
AD31
G16
C/BE0#
A10
C/BE1#
C12
C/BE2#
A12
C/BE3#
B12
DEVSEL#
E16
FRAME#
B6
IRDY#
A7
TRDY#
D15
STOP#
D9
PAR
D11
PLOCK#
E6
SERR#
C9
PERR#
D3
PME#
B10
PCICLK
E3
PCIRST#
E8
REQ0#
C16
REQ1#/GPIO50
B16
REQ2#/GPIO52
A9
REQ3#/GPIO54
A4
GNT0#
C15
GNT1#/GPIO51
D17
GNT2#/GPIO53
B9
GNT3#/GPIO55
C4
PIRQA#
C5
PIRQB#
A3
PIRQC#
A8
PIRQD#
D5
PIRQE#/GPIO2
F10
PIRQF#/GPIO3
G11
PIRQG#/GPIO4
F9
PIRQH#/GPIO5
AG9
SERIRQ
D21
SPI_MOSI
B19
SPI_MISO
C21
SPI_CS0#
A19
SPI_CLK
A18
SPI_CS1#
VSS_002
VSS_001
A5
A24
U20
1
CE#
2
SO
3
WP#
4
VSS
SST25LF080A-33-4C-S2AE-LF
VDD
HOLD#
SCK
8
7
6
5
SI
VSS_006
VSS_005B8VSS_004B2VSS_003
B11
A28
C465 0.1u/16V/4
SPI_HOLD#
B14
4
PCI INTERFACE INTERRUPT
ICH 8
PART 1/3
SPI
VSS_017
VSS_016D6VSS_015D4VSS_014D2VSS_013
VSS_012
VSS_011
VSS_010
VSS_009
VSS_008
VSS_007
B24
B20
B17
C22
R357 2.2K/4
D12
C28
C27
V_3P3_CL
SPI_CLK_F
SPI_MOSI_F
Closer to SB.
4
D16
VSS_018
D19
VSS_019
D22
VSS_020
D25
VSS_021
D26
3
U19A
AD23
A20M#
AC24
CPUSLP#
AB22
FERR#
AC22
IGNNE#
AB19
INIT#
AC12
INIT3_3V#
AH28
INTR
AC23
NMI
AB20
SMI#
AB23
STPCLK#
AF10
RCIN#
AG10
A20GATE
PECI
PLTRST#
PERN_1
PERP_1
PETN_1
PETP_1
PERN_2
PERP_2
PETN_2
PETP_2
PERN_3
PERP_3
PETN_3
PETP_3
PERN_4
PERP_4
PETN_4
PETP_4
PERN_5
PERP_5
PETN_5
PETP_5
DMI_0RXN
DMI_0RXP
DMI_0TXN
DMI_0TXP
DMI_1RXN
DMI_1RXP
DMI_1TXN
DMI_1TXP
DMI_2RXN
DMI_2RXP
DMI_2TXN
DMI_2TXP
DMI_3RXN
DMI_3RXP
DMI_3TXN
DMI_3TXP
DMI_CLKN
DMI_CLKP
DMICOMPI
GLAN_CLK
LAN_RST#
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
VSS_040
VSS_039
G18
G13
AG28
H_SST
AF26
PLTRST_L PLTRST#
FOR JMB361
PE_TXN2_C
PE_TXP2_C
PE_TXN1_C
PE_TXP1_C
PE_TXN3_C
PE_TXP3_C
DMI_BIAS
<200mils
V_3P3_CL
2
SPI_MOSI_F
SPI_CLK_F
6
10
R323 10/4
RSMRST#
AF23
N25
N26
M28
M27
L25
L26
K28
K27
J26
J25
H28
H27
G26
G25
F28
F27
E26
E25
D28
D27
C26
C25
B28
B27
U26
U25
T28
T27
W26
W25
V28
V27
AA25
AA24
Y28
Y27
AC26
AC25
AB28
AB27
R25
R24
AD27
AD28
E22
E20
AF17
E19
C19
D20
C20
C18
D18
ICH8_0818
JSPI1
3 4
5
7 8
9
H2X5(1)_black-RH
3
CPU
THRMTRIP#
PCI EXPRESS
PERN_6/GLAN_RXN
PERP_6/GLAN_RXP
PETN_6/GLAN_TXN
PETP_6/GLAN_TXP
DIRECT MEDIA
DMI_IRCOMP
LAN_RSTSYNC
LAN
VSS_032
VSS_031
VSS_030
VSS_029F7VSS_028F2VSS_027
VSS_026
VSS_025
VSS_024
VSS_023E9VSS_022
E28
E27
E24
E21
VSS_033
VSS_038
VSS_037G6VSS_036G4VSS_035G1VSS_034
F24
F22
F15
F25
F26
G10
SPI_MISO
SPI_CS0_F#
SPI_HOLD#
H_A20M# 3
H_FERR# 3,4
H_IGNNE# 3
H_INIT# 3
H_INTR 3
H_NMI 3
ICH_H_SMI# 3
H_STPCLK# 3
KBRST# 14
A20GATE 14
TRMTRIP# 3,4
H_SST 3
PE_RXN2
PE_RXP2
C383 0.1u/16V/4
C382 0.1u/16V/4
PE_RXN1
PE_RXP1
C381 0.1u/16V/4
C378 0.1u/16V/4
PE_RXN3
PE_RXP3
C379 C0.1U16Y0402
C380 C0.1U16Y0402
DMI_MTN_IRN_0 8
DMI_MTP_IRP_0 8
DMI_ITN_MRN_0 8
DMI_ITP_MRP_0 8
DMI_MTN_IRN_1 8
DMI_MTP_IRP_1 8
DMI_ITN_MRN_1 8
DMI_ITP_MRP_1 8
DMI_MTN_IRN_2 8
DMI_MTP_IRP_2 8
DMI_ITN_MRN_2 8
DMI_ITP_MRP_2 8
DMI_MTN_IRN_3 8
DMI_MTP_IRP_3 8
DMI_ITN_MRN_3 8
DMI_ITP_MRP_3 8
CK_PE_100M_ICH# 13
CK_PE_100M_ICH 13
R299 24.9/4/1
RSMRST# 11,24
2
PLTRST# 6
PE_RXN2 27
PE_RXP2 27
PE_TXN2 27
PE_TXP2 27
PE_RXN1 20
PE_RXP1 20
PE_TXN1 20
PE_TXP1 20
PE_RXN3 20
PE_RXP3 20
PE_TXN3 20
PE_TXP3 20
V_1P5_ICH
2
1
ICH8 H/W STRAPS
REVERSE
RN33
2
4
6
8
10K/4/8P4R
L DES.
EN
EN
A16 OVERIDEDIS
DIS
INT VRM
PCIE 0-3 ORDERSATALED
XOR MODE/PCIE
N/A
PORT CONFIG BIT 1
PCIE PORT CONFIG
N/AHDA_SYNC
BIT 0 (1-4)
SET
PCIE PORT CONFIG 2
BIT
BIT 0 (5-6)
R369 X_1K/6
A20GATE
1
SERIRQ
3
KBRST#
5
7
VCC3
SIGNAL
SPKR
GNT3
INTVRMEN
HDA_SDOUT
GNT2
SPKR11,23
VCC3
H
DIS REBOOT
EN
NORM
DFX/
PCIE
SET
BIT
N/A
BOOT SELECT STRAPS
BOOT DEVICE GNT0 SPI_CS1# JBOOT1
FWH 1 1 1-2(no use)
SPI 0 X 2-3(Default)
PCI 1 0 1-2 & R886
PH1*3/BLACK
PGNT#0
R371 1K/4
R342 1K/6
MSI
Title
Size Document Number Rev
Date: Sheet
1
2
3
JBOOT1
N41-1030141-H06
SPI_CS1#
MICRO-STAR INt'L CO., LTD.
Intel ICH8 - PCI & DMI & CPU & IRQ
MS-7235
10 32Monday, December 26, 2005
1
0A
of
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