5
4
3
2
1
MSI
MS-7228 Ver:0A
D D
CPU:
AMD 754 Sempron/Sempron-64
Title Page
Cover Sheet 1
Block Diagram
2
3GPIO SPEC
4,5,6AMD 754
System Chipset:
NVIDIA C51G
NVIDIA MCP 51G
On Board Chipset:
LPC Super I/O -- W83627EHF REV:C
LAN -- RTL8201CL
Audio Codec --ALC655
BIOS --LPC FLASH ROM 4M
System Memory
/ DDR Terminations
C51G 10,11,12
MCP51G 13,14,15,16
PCI Slot 1&2
PCI-Express X 16 & X1 PORT
W627EHF LPC I/O / BIOS
LAN - RTL8201CL
Audio - ALC655
C C
Main Memory:
DDR * 2 (Max 2GB)
Expansion Slots:
PCI-E X 16 *1
PCI-E X 1 *1
PCI 2.2 Slot X 2
PWM:
Controller--Intersil ISL6568CR 2 Phase
USB connectors
K8 PWM ISL6568CR
MS-6 ACPI Controller & MS-6+
KB/MS/LPT/COM
ATA 66/100/133 Connectors
ATX Connector / Front Panel
VGA
/FAN
POWER OK MAP
POWER MAP
RESET MAP
B B
MANUAL PARTS
HISTORY
7,8,9
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Cover Sheet
1
MS-7228
Last Revision Date:
Tuesday, October 04, 2005
Sheet
Rev
0A
of
133
5
4
3
2
1
BLOCK DIAGRAM
D D
POWER
SUPPLY
CONNECTOR
PEX X16, PEX X1
VREG
PCI EXPRESS
SOCKET 754
K8
NFORCE
CRUSH 51
HT 16X16 1GHZ
200/266/333/400MHZ
DDR SDRAM CONN 0
DDR SDRAM CONN 2
VGA CONN
468 BGA
C C
PRIMARY IDE
SECONDARY IDE
X2 - SATA CONN
B B
FLOPPY CONN
PS2/KBRD CONN
PARALLEL CONN
SERIAL CONN
SERIAL HDR
ATA 133
INTEGRATED SATA 1/2
SIO
LPC SUPER I/O
W83627EHF
LPC BUS 33MHZ
LPC HDR
4MB FLASH
NFORCE
MCP 51
508 BGA
HT 8X8 1GHZ
AZAILIA/AC97
X8 USB2
PCI 33MHZ
Realtek 8201CL
Realtek ALC 655
BACK PANEL CONN
USB2 PORTS 0-1
DOUBLE STACK
USB2 PORTS 2-3
X2/GBIT LAN
FRONT PANEL HDR
USB2 PORTS 4-5
USB2 PORTS 6-7
PCI SLOT 1
PCI SLOT 2
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Block Diagram
MS-7228
Last Revision Date:
Sheet
1
Tuesday, October 04, 2005
2
Rev
0A
33
of
5
4
3
2
1
C-51G GPIO FUNCTION
D D
NAME Function Description
GPIO_1
GPIO_2/CPU_SLP*
GPIO_3/CPU_CLKRUN*
GPIO_4/SUS_STAT* MII_phy reset
C C
NC
NC
BIOS WRITE PROTECT
SIO GPIO FUNCTION
NAME Function Description
GPSA1
GPSB1
GPSB2
GP13
GP14
FOR BIOS
FOR BIOS
GP16
GP17
GP32
GP33
GP44
GP45
NC
NC
NC
NC
NC
GP57/PSOUT#
B B
GP56/PSIN
PSOUT# (PWRBTN#)
PSIN (FP_RST#)
GP53/PSON# PS_ON# (ATX_PWR_ON#)
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
GPIO SPEC
MS-7228
Last Revision Date:
Tuesday, October 04, 2005
Sheet
333
1
Rev
0A
of
5
4
3
2
1
VCC1_2HT
C0.22U16Y
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
MCKE0 7,8
MCKE1 7,8
MEMCLK_H7 7,8
MEMCLK_L7 7,8
MEMCLK_H6 7,8
MEMCLK_L6 7,8
MEMCLK_H5 7,8
MEMCLK_L5 7,8
MEMCLK_H4 7,8
MEMCLK_L4 7,8
MEMCLK_H1 7,8
MEMCLK_L1 7,8
MEMCLK_H0 7,8
MEMCLK_L0 7,8
-MCS3 7,8
-MCS2 7,8
-MCS1 7,8
-MCS0 7,8
-MSRASA 7,8
-MSCASA 7,8
-MSWEA 7,8
MEMBANKA1 7,8
MEMBANKA0 7,8
MAA[13..0] 7,8
-MSRASB 7,8
-MSCASB 7,8
-MSWEB 7,8
MEMBAKB1 7,8
MEMBAKB0 7,8
MAB[13..0] 7,8
CADIP[0..15]10
CADIN[0..15]10
CADIP[0..15]
CADIN[0..15]
CLKIP110
CLKIN110
CLKIP010
CLKIN010
VLDT0
R41 49.9R1%
CTLIP010
CTLIN010
R46 49.9R1%
VREF routed as 40~50
mils trace wide ,
Space>25 mils
D D
C C
B B
DDR_VREF7
VCC_DDR
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
MD[63..0]9
DM[7..0]9
A A
-MDQS[7..0]9
C38 X_C1000P50N
C51 C1000P50X
R85 15R1%
R86 15R1%
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
AE13
AG12
AG3
AE2
AH3
AH9
AG5
AH5
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
AA1
AG1
AH7
AH13
AB1
AJ13
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AJ4
AF1
AJ3
AJ5
AJ6
AJ7
AJ9
A13
A14
AJ2
AJ8
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
RSVD_MEMADDA15
MEMDATA28
RSVD_MEMADDA14
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
RSVD_MEMADDB15
MEMDATA4
RSVD_MEMADDB14
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
U3B
X_C0.22U16Y
VCC1_2HT
C157
CADIP15
CADIN15
CADIP14
CADIN14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
CTLIP1
CTLIN1
C196
C0.22U16Y
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
W25
C171
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
T27
T28
V29
U29
V27
V28
Y29
Y25
Y27
Y28
R27
R26
T29
R29
X_C0.22U16Y
C156
U3A
N12-7540031-L06
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
HYPER TRANSPORT - LINK0
C181
C0.22U16Y
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
C237
C0.22U16Y
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
C173
C0.22U16Y
CADON15
CADON14
CADON13
CADON12
CADON11
CADON10
CADON9
CADON8
CADON7
CADON6
CADON5
CADON4
CADON3
CADON2
CADON1
CADON0
CLKOP1
CLKON1
CLKOP0
CLKON0
CTLOP0
CTLON0
CADOP15
CADOP14
CADOP13
CADOP12
CADOP11
CADOP10
CADOP9
CADOP8
CADOP7
CADOP6
CADOP5
CADOP4
CADOP3
CADOP2
CADOP1
CADOP0
VLDT0
CLKOP1 10
CLKON1 10
CLKOP0 10
CLKON0 10
CTLOP0 10
CTLON0 10
CADOP[0..15]
CADON[0..15]
VLDT0 5
C58
C4.7U10Y0805
CADOP[0..15] 10
CADON[0..15] 10
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
K8 DDR & HT
MS-7228
Last Revision Date:
Sheet
1
Tuesday, October 04, 2005
433
Rev
0A
of
5
4
3
2
1
VDDA_25
D D
VLDT04
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
C C
VCC2_5
HDT Test Port Signal .
B B
VDDA_25
DBREQ_L
DBRDY
TCK
TMS
TDI
TRST_L
R31 X_1KR
R32 X_1KR
1 2
3 4
5 6
7 8
RN37 X_8P4R-1KR
C198
C4.7U10Y0805
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
traces to exit ball field) and 500 mils long.
C62
C1000P50X
-LDTRST
-LDTSTOP
CPU_GD
CPU_THRIP#
CPU_VDDA_25
C33
X_C1000P50N
C61
C1000P50X
CPUCLKO_H10
CPUCLKO_L10
C4.7U10Y0805
-LDTRST10
-LDTSTOP10
Differential , "10:10:5:10:10" .
C239
5p/50V/6
1 2
C242
5p/50V/6
1 2
Near NB
COREFB_H23
COREFB_L23
Near CPU in 0.5" .
FB5 300L700m_250_0805
CPU_GD10
VLDT0
R40 44.2R1%
R39 44.2R1%
RN5
1 2
3 4
5 6
7 8
8P4R-680R
C59
C36 X_C1000P50N
C46 C392p
C45 C392p
VCC_DDR
C42
C0.22U16Y
-LDTRST
CPU_GD
-LDTSTOP
L0_REF1
L0_REF0
R30 820R
R47 820R
R43
C57
C1000P50X
VDDIO_SENSE
169R1%
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
VTT_DDR_SUS
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
AH25
AJ25
AF20
AE18
AJ27
AF27
AE26
A23
A24
B23
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
C16
AG15
AH17
C15
E20
E17
B21
A21
C18
A19
A28
AJ28
AE23
AF23
AF22
AF21
AA2
AG2
B18
AH1
AE21
C20
AG4
AG6
AE9
AG9
C1
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
J3
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
U3C
THERMTRIP_L
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
A20
A26
A27
AG13
AF14
AG14
AF15
AE15
AG18
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
FB6
X_120S/0603
CPU_THRIP#
THERMDA_CPU
THERMDC_CPU
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
FBCLKOUT_H
R49
80.6R1%
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
VCC_DDR
THERMDC_CPU
CPU_THRIP# 13
THERMDA_CPU 19
THERMDC_CPU 19
VID4 23
VID3 23
VID2 23
VID1 23
VID0 23
LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )
RN8
NC_AH18
A A
NC_AJ18
NC_AG18
NC_AG17
NC_D18
NC_B19
NC_C19
NC_D20
5
8P4R-1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
8P4R-1KR
RN36
VDDA_25 VCC_DDR
NC_C18
1 2
NC_A19
3 4
NC_C21
5 6
TDO
7 8
4
8P4R-1KR
RN39
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
3
2
http://www.msi.com.tw
K8 HDT & MISC
MS-7228
Last Revision Date:
Wednesday, October 05, 2005
Sheet
1
533
Rev
0A
of
5
4
3
2
1
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
D D
C C
B B
A A
D2
VSS10
AF2
VSS11
W6
VSS12
Y7
VSS13
AA8
VSS14
AB9
VSS15
AA10
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
AE16
VSS20
J18
VSS21
G20
VSS22
R20
VSS23
U20
VSS24
W20
VSS25
AA20
VSS26
AC20
VSS27
AE20
VSS28
AG20
VSS29
AJ20
VSS30
D21
VSS31
F21
VSS32
H21
VSS33
K21
VSS34
M21
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
AD21
VSS40
AG21
VSS41
B22
VSS42
E22
VSS43
G22
VSS44
J22
VSS45
L22
VSS46
N22
VSS47
R22
VSS48
U22
VSS49
AG29
VSS50
AA22
VSS51
AC22
VSS52
AG22
VSS53
AH22
VSS54
AJ22
VSS55
D23
VSS56
F23
VSS57
H23
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
AB23
VSS64
AD23
VSS65
AG23
VSS66
E24
VSS67
G24
VSS68
J24
VSS69
N24
VSS70
R24
VSS71
U24
VSS72
W24
VSS73
AA24
VSS74
AC24
VSS75
AG24
VSS76
AJ24
VSS77
B25
VSS78
C25
VSS79
B26
VSS80
D26
VSS81
H26
VSS82
M26
VSS83
T26
VSS84
Y26
VSS85
AD26
VSS86
AF26
VSS87
AH26
VSS88
C27
VSS89
B28
VSS90
D28
VSS91
G28
VSS92
F15
VSS187
H15
VSS188
AB17
VSS206
AD17
VSS207
B16
VSS208
G18
VSS209
AA18
VSS210
AC18
VSS211
D19
VSS212
F19
VSS213
H19
VSS214
K19
VSS215
Y19
VSS216
AB19
VSS217
AD19
VSS218
AF19
VSS219
J20
VSS220
L20
VSS221
N20
VSS222
GND GND
GROUND
5
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
U3E
VCORE
AC15
G13
AB14
G15
AA15
AB16
G17
AA17
AC17
AE17
AB18
AD18
AG19
G19
AC19
AA19
M20
AB20
AD20
G21
W21
AA21
AC21
M22
AB22
AD22
G23
W23
AA23
AC23
M24
AB24
AD24
AH24
AE25
VCC_DDR
L7
VDD1
VDD2
H18
VDD3
B20
VDD4
E21
VDD5
H22
VDD6
J23
VDD7
H24
VDD8
F26
VDD9
N7
VDD10
L9
VDD11
V10
VDD12
VDD13
K14
VDD14
Y14
VDD15
VDD16
VDD17
J15
VDD18
VDD19
H16
VDD20
K16
VDD21
Y16
VDD22
VDD23
VDD24
J17
VDD25
VDD26
VDD27
VDD28
F18
VDD29
K18
VDD30
Y18
VDD31
VDD32
VDD33
VDD34
E19
VDD35
VDD36
VDD39
VDD38
J19
VDD37
F20
VDD40
H20
VDD41
K20
VDD42
VDD43
P20
VDD44
T20
VDD45
V20
VDD46
Y20
VDD47
VDD48
VDD49
VDD50
J21
VDD51
L21
VDD52
N21
VDD53
R21
VDD54
U21
VDD55
VDD56
VDD57
VDD58
F22
VDD59
K22
VDD60
VDD61
P22
VDD62
T22
VDD63
V22
VDD64
Y22
VDD65
VDD66
VDD67
E23
VDD68
VDD69
L23
VDD70
N23
VDD71
R23
VDD72
U23
VDD73
VDD74
VDD75
VDD76
B24
VDD77
D24
VDD78
F24
VDD79
K24
VDD80
VDD81
P24
VDD82
T24
VDD83
V24
VDD84
Y24
VDD85
VDD86
VDD87
VDD88
VDD89
K26
VDD90
P26
VDD91
V26
VDD92
POWER
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
U3D
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
C550
X_33P/50V/6
VCORE
4
Bottom Side of CPU
VTT_DDR_SUS
C551
X_C0.1U25Y
X_C0.1U25Y
Bottom Side of CPU
VCC_DDR
C89
C133
<nopop>
C4.7U10Y0805
C1U6.3Y_0402
CPU SOCKET Inside
VCORE
VCC_DDR
C501
GND
C186
X_C0.1U25Y
C552
X_C0.1U25Y
C0.1U25Y
C504
C506
33P/50V/6
BACK
C502
33P/50V/6
GND
LAYOUT: Place beside processor.
C66
C210
C165
<nopop>
C1U16Y
C4.7U10Y0805
C79
C4.7U10Y0805
C94
X_C0.22U16Y
C231
C1000P50X
C107
C0.22U16Y
C1U16Y0805
C250
X_C1U16Y0805
C164
X_C1U16Y0805
C201
C0.22U16Y
In CPU.
100P
<nopop>
3
C110
C8.2P50N
C105
C0.22U16Y
C503
4.7u/6
<nopop>
X_C0.22U16Y
C115
C111
C8.2P50N
C507
X_C1U16Y
100P
C55
104P
C119
C116
C0.22U16Y
C500
X_C6.8P50N
C122
C0.22U16Y
C118
X_C0.22U16Y
GND
C103
C0.22U16Y
C123
C8.2P50N
C56
104P
C556
104P
C100
C106
C0.22U16Y
C180P50N
C101
C112
C180P50N
C180P50N
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,
2 in middle of HT link, and 12 along bottom left side of
Claw-hammer.
VCORE
C505
C256
C557
104P
C1U6.3Y_0402
C139
GND
C558
2
C0.22U16Y
104P
C559
104P
VCORE
C560
C553
104P
104P
VTT_DDR_SUSVCC_DDR
C127
X_100P_0402
VCC_DDR
Place between DIMN1 & 2
C152
C125
C0.1U10X_0402
C0.1U10X_0402
C555
C554
104P
104P
VCC_DDR
C561
104P
Title
Document Number
C148
C179
C0.1U10X_0402
C0.1U10X_0402
C131
GND
Micro Star Restricted Secret
K8 Power & GND
MS-7228
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C0.1U10X_0402
Last Revision Date:
Sheet
1
Tuesday, October 04, 2005
633
of
Rev
0A
5
4
3
2
1
VCC_DDR VCC_DDR
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
D D
C C
B B
DR_MD[63..0]8,9
VCC_DDR
R144 4.7KR
-MSWEA4,8
DDR_VREF
VREF routed as 40~50
mils trace wide ,
Space>25 mils
C0.1U25Y
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
C29
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VDD8
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
104
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
DDR DIMM
Place 104p and 1000p Cap. near the DIMM
Place near the DIMM
VCC_DDR
R23
A A
1KR1%
R22
1KR1%
C27
X_C0.1U25Y
DDR_VREF
C28
C1U10Y
VREF routed as 40~50 mils trace wide ,
Space>25 mils
DDR_VREF 4
5
DIMM1 SLAVE ADDRESS
= (1010000X)B = A0
SYSTEM MEMORY
172
180
VDDQ13
VDDQ14
PIN
VSS19
VSS20
152
160
15
82
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
NC(RESET#)
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
DDR1
DIMM-184_green
176
N13-1840061-K06
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
BA0
BA1
BA2
SCL
SA0
SA1
SA2
157
158
71
163
5
14
25
36
56
67
78
86
47
103
48
43
41
130
37
32
125
29
122
27
141
118
115
167
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13
SMB_MEM_CLK
SMB_MEM_DATA
MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7
MCKE0
MCKE1
-MSCASA
-MSRASA
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
143
156
164
112
128
136
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
184
SOCKET
VSS14
VSS15
VSS16
VSS17
VSS18
100
116
124
132
139
145
4
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
MAA[13..0]
-MCS0 4,8
-MCS1 4,8
-DR_MDQS0 8,9
-DR_MDQS1 8,9
-DR_MDQS2 8,9
-DR_MDQS3 8,9
-DR_MDQS4 8,9
-DR_MDQS5 8,9
-DR_MDQS6 8,9
-DR_MDQS7 8,9
MAA[13..0] 4,8
MEMBANKA0 4,8
MEMBANKA1 4,8
SMB_MEM_CLK 14
SMB_MEM_DATA 14
MEMCLK_H5 4,8
MEMCLK_L5 4,8
MEMCLK_H0 4,8
MEMCLK_L0 4,8
MEMCLK_H7 4,8
MEMCLK_L7 4,8
MCKE0 4,8
MCKE1 4,8
-MSCASA 4,8
-MSRASA 4,8
DR_DM[7..0]
VCC_DDR
DR_DM[7..0] 8,9
-MSWEB4,8
3
R147 4.7KR
DDR_VREF
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
101
102
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
1
VREF
9
NC2
NC3
NC4
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
DIMM2 SLAVE ADDRESS
= (1010001X)B = A2
143
156
164
172
180
15
VDDQ11
VDDQ12
VDDQ13
184
VSS17
VSS18
VSS19
139
145
152
VDDQ14
VDDQ15
PIN
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
160
176
82
VDDID
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
CK0(DU)
CK2(DU)
CKE0
CKE1
CAS#
RAS#
104
112
128
136
VDDQ7
VDDQ8
VDDQ9
VDDQ10
DDR DIMM
SOCKET
VSS14
VSS15
VSS16
100
116
124
132
2
CS0#
CS1#
CS2#
CS3#
SCL
SDA
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
A11
A12
A13
BA0
BA1
BA2
SA0
SA1
SA2
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
-MCS2
157
-MCS3
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
103
MAB0
48
MAB1
43
MAB2
41
MAB3
130
MAB4
37
MAB5
32
MAB6
125
MAB7
29
MAB8
122
MAB9
27
MAB10
141
MAB11
118
MAB12
115
MAB13
167
MEMBAKB0
59
MEMBAKB1
52
113
SMB_MEM_CLK
92
SMB_MEM_DATA
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
MCKE0
21
MCKE1
111
-MSCASB
65
-MSRASB
154
97
107
119
129
149
159
169
177
140
DDR2
DIMM-184_green
N13-1840061-K06
-MCS2 4,8
-MCS3 4,8
MAB[13..0] 4,8
MEMBAKB0 4,8
MEMBAKB1 4,8
VCC_DDR
MEMCLK_H4 4,8
MEMCLK_L4 4,8
MEMCLK_H1 4,8
MEMCLK_L1 4,8
MEMCLK_H6 4,8
MEMCLK_L6 4,8
-MSCASB 4,8
-MSRASB 4,8
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
DDR DIMM 1 & 2
MS-7228
Last Revision Date:
Wednesday, October 05, 2005
Sheet
1
Rev
0A
733
of
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS
DR_MD44
DR_MD35
DR_MD40
D D
DR_MD59
DR_MD63
DR_MD62
DR_MD58
-DR_MDQS7
DR_DM7
DR_MD57
DR_MD61
DR_MD60
DR_MD56
DR_MD51
DR_MD55
C C
B B
-MSCASA4,7
-MSRASB4,7
-MSRASA4,7
MEMBAKB04,7
MEMBANKA04,7
DR_MD54
-DR_MDQS6
DR_DM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD48
DR_MD49
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_DM5
DR_MD41
-MCS1
-MCS14,7
-MCS0
-MCS04,7
-DR_MDQS5
-MSCASA
-MSWEB
-MSWEB4,7
DR_MD45
-MSRASB
-MSRASA
DR_MD37
DR_MD33
RN62 8P4R-47R0402
7 8
5 6
3 4
1 2
RN60 8P4R-47R0402
7 8
5 6
3 4
1 2
RN58 8P4R-47R0402
7 8
5 6
3 4
1 2
RN55 8P4R-47R0402
7 8
5 6
3 4
1 2
RN53 8P4R-47R0402
7 8
5 6
3 4
1 2
RN52 8P4R-47R0402
7 8
5 6
3 4
1 2
RN50 8P4R-47R0402
7 8
5 6
3 4
1 2
RN47 8P4R-47R0402
7 8
5 6
3 4
1 2
RN46 8P4R-47R0402
7 8
5 6
3 4
1 2
RN40 8P4R-47R0402
7 8
5 6
3 4
1 2
MEMBAKB14,7
MEMBANKA14,7
DR_MD39
DR_MD38
DR_MD34
DR_DM4
-DR_MDQS4
DR_MD36
DR_MD32
MAB0
MAB10
MAA10
MAA0
MAA2
MAB2
DR_MD30DR_MD50
MAA3
MAA4
MAA6
MAB6
MAB5
DR_MD26
DR_DM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
MAB3
MAB4
MAA5
MAA8
DR_MD24
DR_MD19
VTT_DDR_SUS
RN45 8P4R-47R0402
7 8
5 6
3 4
1 2
RN42 8P4R-47R0402
7 8
5 6
3 4
1 2
RN38 8P4R-47R0402
7 8
5 6
3 4
1 2
RN35 8P4R-47R0402
7 8
5 6
3 4
1 2
RN33 8P4R-47R0402
7 8
5 6
3 4
1 2
RN28 8P4R-47R0402
7 8
5 6
3 4
1 2
RN31 8P4R-47R0402
7 8
5 6
3 4
1 2
RN30 8P4R-47R0402
7 8
5 6
3 4
1 2
RN25 8P4R-47R0402
7 8
5 6
3 4
1 2
VTT_DDR_SUS
DR_MD23
MAB8
MAB7
DR_MD22
MAA11
MAB11
MAB9
DR_MD21
DR_MD18
MAA7
MAA9
DR_DM2
-DR_MDQS2
DR_MD17
MAA12
MAB12
DR_MD16
DR_MD11
MCKE04,7
MCKE14,7
DR_MD20
DR_MD10
DR_MD15
DR_MD14
DR_DM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD6
DR_MD7
DR_MD2
DR_DM0
-DR_MDQS0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
DR_MD27
DR_MD31
MAB1
MAA1
RN23 8P4R-47R0402
7 8
5 6
3 4
1 2
RN19 8P4R-47R0402
7 8
5 6
3 4
1 2
RN21 8P4R-47R0402
7 8
5 6
3 4
1 2
RN17 8P4R-47R0402
7 8
5 6
3 4
1 2
RN15 8P4R-47R0402
7 8
5 6
3 4
1 2
RN13 8P4R-47R0402
7 8
5 6
3 4
1 2
RN12 8P4R-47R0402
7 8
5 6
3 4
1 2
RN9 8P4R-47R0402
7 8
5 6
3 4
1 2
RN6 8P4R-47R0402
7 8
5 6
3 4
1 2
RN3 8P4R-47R0402
7 8
5 6
3 4
1 2
RN34 8P4R-47R0402
7 8
5 6
3 4
1 2
VTT_DDR_SUS
-MCS3
-MCS34,7
-MCS2
-MCS24,7
-MSCASB4,7
-MSCASB
-MSWEA
-MSWEA4,7
RN49 8P4R-47R0402
7 8
5 6
3 4
1 2
DR_DM[7..0]7,9
For DIMM2 Clock
A A
MEMCLK_H44,7 MEMCLK_L5 4,7
MEMCLK_H14,7
MEMCLK_H64,7
MEMCLK_H4
MEMCLK_H1
MEMCLK_H6
5
C64 X_C10P50N
C113 X_C10P50N
C166 X_C10P50N
MEMCLK_L4
MEMCLK_L1
MEMCLK_L6
MEMCLK_L4 4,7
MEMCLK_L1 4,7
MEMCLK_L6 4,7
For DIMM1 Clock
MEMCLK_H54,7
MEMCLK_H74,7
4
MEMCLK_H7
MEMCLK_H0
C65 X_C10P50N
C167 X_C10P50N
C121 X_C10P50N
MEMCLK_L5MEMCLK_H5
MEMCLK_L7
MEMCLK_L0
MEMCLK_L7 4,7
MEMCLK_L0 4,7MEMCLK_H04,7
3
-DR_MDQS[7..0]7,9
DR_MD[63..0]7,9
MAB[13..0]4,7
MAA[13..0]4,7
DR_DM[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
DDR Treminations Part1
MS-7228
Last Revision Date:
Tuesday, October 04, 2005
Sheet
1
833
Rev
0A
of
5
4
3
2
1
DDR Terminations
MD38
R93 10R0402
RN41 8P4R-10R0402
1 2
MD32
3 4
MD36
5 6
MD33
7 8
D D
C C
B B
A A
-MDQS0 -DR_MDQS0
R34 10R0402
MD0
MD4
MD5
MD1
DM0
MD2
MD7
MD6
MD3
MD8
MD9
MD12
MD15
RN11 8P4R-10R0402
-MDQS1
MD13
DM1
MD14
MD17
-MDQS2
MD21
DM2
MD18
RN14 8P4R-10R0402
MD10
MD20
MD11
MD16
MD22
MD23
MD19
MD24
MD28
MD29
MD25
-MDQS3
RN32 8P4R-10R0402
MD26
MD30
MD31
MD27
-MDQS[7..0]4
-DR_MDQS[7..0]7,8
DR_MD[63..0]7,8
MD[63..0]4
DR_DM[7..0]7,8
DM[7..0]4
RN4 8P4R-10R0402
1 2
3 4
5 6
7 8
RN7 8P4R-10R0402
1 2
3 4
5 6
7 8
RN10 8P4R-10R0402
1 2
3 4
5 6
7 8
R65 10R0402
1 2
3 4
5 6
7 8
RN18 8P4R-10R0402
1 2
3 4
5 6
7 8
R67 10R0402
1 2
3 4
5 6
7 8
RN24 8P4R-10R0402
1 2
3 4
5 6
7 8
RN27 8P4R-10R0402
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
5
DR_MD0
DR_MD4
DR_MD5
DR_MD1
DR_DM0
DR_MD2
DR_MD7
DR_MD6
DR_MD3
DR_MD8
DR_MD9
DR_MD12
-DR_MDQS1
DR_MD13
DR_DM1
DR_MD14
DR_MD17
-DR_MDQS2
DR_MD21
DR_DM2
DR_MD10
DR_MD20
DR_MD11
DR_MD16
DR_MD22
DR_MD23
DR_MD19
DR_MD24
DR_MD28
DR_MD29
DR_MD25
-DR_MDQS3
DR_MD26
DR_MD30
DR_MD31
DR_MD27
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
DR_DM[7..0]
DM[7..0]
DR_MD15
DR_MD18
RN43 8P4R-10R0402
MD37
1 2
-MDQS4
3 4
DM4
5 6
MD34
7 8
MD42
R102 10R0402
RN44 8P4R-10R0402
MD39
1 2
MD40
3 4
MD35 DR_MD35
5 6
MD44
7 8
RN48 8P4R-10R0402
MD45
1 2
-MDQS5
3 4
MD41
5 6
DM5
7 8
RN51 8P4R-10R0402
MD43
1 2
MD46 DR_MD46
3 4
MD47
5 6
MD49
7 8
RN54 8P4R-10R0402
MD48
1 2
MD52
3 4
MD53
5 6
DM6
7 8
MD51
R124 10R0402
RN57 8P4R-10R0402
-MDQS6
1 2
MD54
3 4
MD50
5 6
MD55
7 8
RN59 8P4R-10R0402
MD56
1 2
MD60
3 4
MD61
5 6
MD57
7 8
RN61 8P4R-10R0402
DM7
1 2
-MDQS7
3 4
MD58
5 6
MD62
7 8
MD59
R141 10R0402
MD63
R139 10R0402
DM3
R71 10R0402
4
DR_MD32
DR_MD36
DR_MD33
DR_MD37
-DR_MDQS4
DR_DM4
DR_MD34
DR_MD39
DR_MD40
DR_MD44
DR_MD45
-DR_MDQS5
DR_MD41
DR_DM5
DR_MD43
DR_MD47
DR_MD49
DR_MD48
DR_MD52
DR_MD53
DR_DM6
-DR_MDQS6
DR_MD54
DR_MD50
DR_MD55
DR_MD56
DR_MD60
DR_MD61
DR_MD57
DR_DM7
-DR_MDQS7
DR_MD58
DR_MD62
DR_MD59
DR_MD63
DR_DM3
DR_MD38
DR_MD42
DR_MD51
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.
VTT_DDR_SUS
VTT_DDR_SUS
VTT_DDR_SUS
VTT_DDR_SUS
LAYOUT: Place on backside,
evenly spaced around VTT fill.
VTT_DDR_SUS
C88
X_68P_0402
C147
X_100P_0402
C26
X_C0.1U25Y
C251
X_C0.1U25Y
C206
C1U25Y
C274
X_C0.1U25Y
C226
X_C0.1U25Y
C91
X_C1U10Y
C132
C0.22U16Y
C3
X_C1000P50NC158
C1U10Y
C1
C151
C137
C1U16Y0805
C80
X_C1000P50X
C17
C1U10Y
C48
X_C0.1U25Y
C39
X_C0.22U16Y
C24
X_C4.7U10Y0805
3
X_C0.1U25Y
C1U25Y
C11
VTT_DDR_SUS
VCC_DDR
C193
C1000P50X
<nopop>
C43
X_C0.22U16Y
<nopop>
C241
X_C0.22U16Y
<nopop>
X_C0.22U16Y
<nopop>
C233
X_C0.1U25Y
C240
C1U25Y
C177
X_68P_0402
C85
X_C0.1U25Y
C50
X_C0.1U25Y
C258
X_C0.1U25Y
C87
C73
C129
X_C0.1U25Y
C99
C109
X_C0.1U25Y
LAYOUT: Locate close to
Clawhammer socket.
C1U16Y0805
C214
X_C4.7U10Y0805
C37
X_C0.1U25Y
C1U25Y
C52
X_C4.7U10Y0805
X_C1000P50X
C1U10Y
C63
X_C1U10Y
C1000P50X
C47
GND
C296
C1U16Y0805
C144
C159
C230
C117
C153
X_C100P50N
C1000P50X
C1U10Y
X_C1U10Y
C266
C235
C70
C0.22U16Y
C170
GND
C270
X_C0.1U25Y
C187
X_C0.1U25Y
C211
C1U25Y
C162
C1U25Y
C136
X_68P_0402
C140
C1U25Y
C95
C1U25Y
C243
X_C0.1U25Y
C124
X_C0.1U25Y
C1U16Y0805
C223
X_C0.1U25Y
C221
C1U25Y
LAYOUT: Locate close
to Clawhammer
socket.
VTT_DDR_SUS
EC17
CE470U10VD25A400RO
GND
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS
VCC_DDRVCC_DDR VCC_DDR VCC_DDR
C102
X_100P_0402
C282
C0.1U25Y
C68
C1U25Y
C120
X_68P_0402
C202
X_C0.1U25Y
C217
X_C0.1U25Y
C34
X_C0.1U25Y
C203
C1U10Y
2
C265
C1U25Y
C208
X_C1U10Y
C168
X_C0.1U25Y
C254
C1U25Y
C268
X_C0.1U25Y
C209
X_C0.1U25Y
C180
C1U10Y
C215
X_C0.1U25Y
VCC_DDR
C74
VCC_DDR
VCC_DDR
C236
C197
C192
C1U10Y
X_C0.1U25Y
GND
C281
C216
C0.1U25Y
X_C1U10Y
GND
LAYOUT: Locate close to
Dimm2 socket.
C84
C54
C0.1U25Y
C0.1U25Y
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
VCC3
C294
X_C0.1U25Y
C86
X_C0.1U25Y
VCC5
C19
X_C0.1U25Y
C20
100P
C195
X_C0.1U25Y
C220
X_C0.1U25Y
C204
100P
C108
C0.1U25Y
C160
C0.1U25Y
C259
100P
100P
C161
C0.1U25Y
C219
X_C0.1U25Y
C277
100P
GND
C1U25Y
C0.1U25Y
100P
C174
C0.1U25Y
GND
Micro Star Restricted Secret
DDR Terminitions Part2
GND
VCC_DDR
VCC_DDR
MS-7228
1
C77
X_C0.1U25Y
C92
X_C0.1U25Y
C176
X_C0.1U25Y
C93
X_C0.1U25Y
C130
X_C0.1U25Y
C142
X_C0.1U25Y
C188
X_C0.1U25Y
C175
X_C0.1U25Y
GND
C76
X_C0.1U25Y
C44
X_C0.1U25Y
C90
X_C0.1U25Y
C178
X_C0.1U25Y
C149
X_C0.1U25Y
GND
Last Revision Date:
Tuesday, October 04, 2005
Sheet
933
Rev
0A
of
5
4
3
2
1
U7F
CADOP[0..15]4
D D
CADON[0..15]4
C C
CADOP[0..15]
CADON[0..15]
CLKOP04
CLKON04
CLKOP14
CLKON14
CTLOP04
CTLON04
CTLOP0
CTLON0
CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15
CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15
Y23
W24
V24
U22
R24
P24
P22
N22
Y21
V21
W21
T21
R18
P16
N20
M17
Y22
W23
V23
U21
R23
P23
P21
N21
Y20
W20
W22
U20
R19
P17
N19
N18
T23
T22
R21
R20
M23
M22
HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P
HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N
HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N
HT_CPU_RXCTL_P
HT_CPU_RXCTL_N
VCC1_2HT
W19
HT_CPU_CAL_1P2V
Y19
?
1P2VPLL_PWR
R111 150/6/1
FB20 X_30S
CP17
COPPER
PLACE ON BACK SIDE
R108 150/6/1
1P2VPLL_FILT
1u/10V/6
C514
C516
0.1u/25V/6
B B
1P2VPLL_PWR11,12
N16
T13
HT_CPU_CAL_GND
+1.2V_PLLHTCPU
+1.2V_PLLHTMCP
?
C51
SEC 1 OF 6
HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P
HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P
HT_CPU_TXD0_N
HT_CPU_TXD1_N
HT_CPU_TXD2_N
HT_CPU_TXD3_N
HT_CPU_TXD4_N
HT_CPU_TXD5_N
HT_CPU_TXD6_N
HT_CPU_TXD7_N
HT_CPU_TXD8_N
HT_CPU_TXD9_N
HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N
HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N
HT_CPU_TXCTL_P
HT_CPU_TXCTL_N
CLKOUT_PRI_200MHZ_P
CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N
HT_CPU_REQ*
HT_CPU_STOP*
HT_CPU_RESET*
HT_CPU_PWRGD
+2.5V_PLLHTCPU
VCC2_5
C23
D23
E22
F23
H22
J21
K21
K23
D21
F19
F21
G20
J19
L17
L20
L18
C24
D24
E23
F24
H23
J22
K22
K24
D22
E20
E21
G19
J18
K17
K19
L19
G23
G24
G22
G21
L23
L24
B24
B23
A22
B21
F18
G18
D20
E19
L16
C249
4.7u/10V/8
CADIP0
CADIP1
CADIP2
CADIP3
CADIP4
CADIP5
CADIP6
CADIP7
CADIP8
CADIP9
CADIP10
CADIP11
CADIP12
CADIP13
CADIP14
CADIP15
CADIN0
CADIN1
CADIN2
CADIN3
CADIN4
CADIN5
CADIN6
CADIN7
CADIN8
CADIN9
CADIN10
CADIN11
CADIN12
CADIN13
CADIN14
CADIN15
CLKIN0
CLKIP1
CLKIN1
CTLIN0
CLKIP0
CTLIP0
2P5V_PLL
C510
0.1u/25V/6
CADIP[0..15]
CADIN[0..15]
-LDTSTOP
-LDTRST
CPU_GD
CP16
X_30S
CLKIP0 4
CLKIN0 4
CLKIP1 4
CLKIN1 4
CTLIP0 4
CTLIN0 4
CPUCLKO_H 5
CPUCLKO_L 5
COPPER
FB19
C513
1u/16V/6
CADIP[0..15] 4
CADIN[0..15] 4
-LDTSTOP 5
-LDTRST 5
CPU_GD 5
2P5V_PLL
C512
0.1u/25V/6
2P5V_PLL 11
HTMCP_UP[7..0]13
HTMCP_UP#[7..0]13
HTMCP_UP[7..0]
HTMCP_UP#[7..0]
HTMCP_UPCLK013
HTMCP_UPCLK0#13
HTMCP_UPCNTL13
HTMCP_UPCNTL#13
HTMCP_REQ#13
HTMCP_STOP#13
HTMCP_RST#13
HTMCP_PWRGD13
MCPOUT_25MHZ13
MCPOUT_200MHZ13
MCPOUT_200MHZ#13
HTMCP_UPCLK0
HTMCP_UPCLK0#
HTMCP_UPCNTL
HTMCP_UPCNTL#
HTMCP_REQ#
HTMCP_STOP#
HTMCP_RST#
HTMCP_PWRGD
MCPOUT_25MHZ
MCPOUT_200MHZ
MCPOUT_200MHZ#
HTMCP_UP0
HTMCP_UP1
HTMCP_UP2
HTMCP_UP3
HTMCP_UP4
HTMCP_UP5
HTMCP_UP6
HTMCP_UP7
HTMCP_UP#0
HTMCP_UP#1
HTMCP_UP#2
HTMCP_UP#3
HTMCP_UP#4
HTMCP_UP#5
HTMCP_UP#6
HTMCP_UP#7
AD10
AD11
AC12
AC13
AA11
AC10
AC11
AB12
AB13
AD14
AC14
AD6
AC7
AA8
AA9
AA6
Y10
V11
W12
AC6
AB7
AB8
AB9
AA7
W10
Y12
W11
V13
AD9
AC9
U10
T10
AB5
AA5
AC5
AD5
AC4
W7
Y8
V9
Y6
Y7
W9
Y5
W5
U7A
?
HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P
HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N
HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N
HT_MCP_RXCTL_P
HT_MCP_RXCTL_N
HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD
CLKIN_25MHZ
CLKIN_200MHZ_P
CLKIN_200MHZ_N
?
C51
SEC 2 OF 6
SCLKIN_MCLKOUT_200MHZ_P
SCLKIN_MCLKOUT_200MHZ_N
HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P
HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P
HT_MCP_TXD0_N
HT_MCP_TXD1_N
HT_MCP_TXD2_N
HT_MCP_TXD3_N
HT_MCP_TXD4_N
HT_MCP_TXD5_N
HT_MCP_TXD6_N
HT_MCP_TXD7_N
HT_MCP_TXD8_N
HT_MCP_TXD9_N
HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N
HT_MCP_TX_CLK0_P
HT_MCP_TX_CLK0_N
HT_MCP_TX_CLK1_P
HT_MCP_TX_CLK1_N
HT_MCP_TXCTL_P
HT_MCP_TXCTL_N
CLKOUT_CTERM
HT_MCP_CAL_1P2V
HT_MCP_CAL_GND
HTMCP_DWN0
AC24
HTMCP_DWN1
AD23
HTMCP_DWN2
AC22
HTMCP_DWN3
AC20
HTMCP_DWN4
AB18
HTMCP_DWN5
AA17
HTMCP_DWN6
AB16
HTMCP_DWN7
AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13
HTMCP_DWN#0
AC23
HTMCP_DWN#1
AD22
HTMCP_DWN#2
AC21
HTMCP_DWN#3
AD20
HTMCP_DWN#4
AC18
HTMCP_DWN#5
AB17
HTMCP_DWN#6
AB15
HTMCP_DWN#7
AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13
AC19
AD19
Y17
W17
AC15
AD15
B22
A20
B20
AB23
AB24
HTMCP_DWN[7..0]
HTMCP_DWNCLK0
HTMCP_DWNCLK0#
HTMCP_DWNCNTL
HTMCP_DWNCNTL#
UNNAMED_21_C51_I164_CLKOUTCTERM
R110 150/6/1
HTMCP_DWN#[7..0]
R120 2.37K/6/1
VCC1_2
R109 150/6/1
HTMCP_DWN[7..0] 13
HTMCP_DWN#[7..0] 13
HTMCP_DWNCLK0 13
HTMCP_DWNCLK0# 13
HTMCP_DWNCNTL 13
HTMCP_DWNCNTL# 13
A A
5
4
PLACE ON BACK SIDE
Micro Star Restricted Secret
Title
Document Number
3
2
C51G-1/ HT CPU & MCP
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
MS-7228
1
Last Revision Date:
Wednesday, October 05, 2005
Sheet
10 33
of
Rev
0A
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