MSI MS-7225 Schematics 0A

5

4

3

2

1

MSI

MS-7225 Ver:0A

D D

C C

B B

CPU:

AMD 940 Athlon 64/Athlon 64 FX

System Chipset:

NVIDIA C51PV / C51G
NVIDIA MCP 51

On Board Chipset:

LPC Super I/O -- SMSC 47M997
LAN -- RTL8201CL

AC97 Codec --ALC883

BIOS --LPC FLASH ROM 4M

Main Memory:

DDR * 4 (Max 4GB)

Expansion Slots:

PCI-E X 16 *1
PCI-E X1 *1

PCI 2.2 Slot * 2
PCI Extender

PWM:

Controller--Intersil ISL6566CR 3 Phase

Title Page

Cover Sheet 1
Block Diagram
AMD M2 940
System Memory
DDR Terminations

2
3,4,5
6,7

8
C51PV 9-11
MCP51 12-15
PCI Slot 1,2 & PCI Extender
PCI-Express X 16 , X1 Slot & MDC
SIO-LPC47M997 / BIOS
LAN - RTL8201CL

Azalia CODEC & Interanl SPK

1394 Controller-VT6307
USB connectors
MS-6 ACPI Co ntr oller & MS-6+
PWM - ISL6566CR
IDE &FDD & FAN
ATX Connector / Front Panel
TV-OUT & VGA Connector
MANUAL PARTS
GPIO SPEC
POWER OK MAP
POWER MAP
RESET MAP
History

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li - D e S t , Jung- He City,
Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

Cover Sheet

MS-7225H1

1

Last Revision Date:

Monday, September 12, 2005

Sheet

Rev

0A

133

of

5

4

3

2

1

BLOCK DIAGRAM

D D

POWER

SUPPLY

CONNECTOR

PEX X16, PEX X1

VREG

PCI EXPRESS

SOCKET 940

K9

NFORCE

CRUSH 51

HT 16X16 1GHZ

128-BIT 400/533MHZ

DDR SDRAM CONN 0

DDR SDRAM CONN 2

DDR SDRAM CONN 1

DDR SDRAM CONN3

VGA CONN

468 BGA

C C

PRIMARY IDE

SECONDARY IDE

X4 - SATA CONN

B B

FLOPPY CONN

PS2/KBRD CONN

PARALLEL CONN

SERIAL CONN

SERIAL HDR

ATA 133

INTEGRATED SATA 1/2

SIO

LPC SUPER I/O
47M997

LPC BUS 33MHZ

LPC HDR

4MB FLASH

NFORCE
MCP 51

508 BGA

HT 8X8 1GHZ

AZAILIA/AC97

X8 USB2

PCI 33MHZ

Realtek 8201CL

Realtek AL C 8 83 (Azalia, 7.1Channel)

BACK PANEL CONN

USB2 PORTS 0-1
DOUBLE STACK

USB2 PORTS 2-3
X2/GBIT LAN

FRONT PANEL HDR

USB2 PORTS 4-5

USB2 PORTS 6-7

1394-VT6307

PCI SLOT 1

PCI SLOT 2

PCI Extender

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR I NT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsi en , Taiwan

5

4

3

2

http://www.msi.com.tw

Block Diagram

MS-7225H1

Last Revision Date:
Sheet

1

Monday, Sep te mb er 12 , 2005

2

Rev

0A

33

of

5

4

3

2

1

VID(5)
VID(4)
VID(3)
VID(2)
VID(1)
VID(0)

THERMTRIP_L

PROCHOT_L

TDO

DBRDY

VDDIO_FB_H

VDDIO_FB_L

PSI_L

HTREF1
HTREF0

TEST29_H

TEST29_L

TEST24
TEST23
TEST22
TEST21
TEST20

TEST28_H

TEST28_L

TEST27
TEST26
TEST10

TEST8

VCC_DDR

D2
D1
C1
E3
E2
E1

AK7
AL7

AK10

B6
AK11

AL11
F1

V8
V7

C11
D11

AK8
AH8
AJ9
AL8
AJ8

J10
H9
AK9
AK5
G7
D4

RN8

1
3
5
7

TP9

VID4
VID3
VID2
VID1
VID0

CPU_THRIP#

CPU_TDO

CPU_DBRDY

CPU_VDDIOFB_H
CPU_VDDIOFB_L

CPU_PSI_L

R101 300R

2
4
6
8

8P4R-330R

LDT_RST
CPU_PWRGD
HT_STOP#
CPU_THRIP#

VCC_DDR

CPU_THRIP# 12

VCC_DDR

TP12

TP20
TP18
TP19

TP16

VCC_DDR

R19
X_300R

R96
300R

TP5

TP6

C163
C1000P50X

R61

80.6R1%

C164
C1000P50X

R99 44.2R1%
R100 44.2R1%

VID[0..4] 24

VCC_DDR

R95
300R

VCC1_2HT

HT_CADIN_H [15..0]9

HT_CADIN_L[15..0]9

HT_CADO UT_H[15..0]9

HT_CADO U T _L[15..0]9

D D

VCC1_2HT

C165
C4.7U10Y0805

VCC1_2HT

C C

B B

HT_CADIN_H [15..0]
HT_CADIN_L[15..0]
HT_CADO UT_H[15..0]
HT_CADOUT_L[15..0]

C213
C4.7U10Y0805

HT_CLKIN_H19

HT_CLKIN_L19

HT_CLKIN_H09

HT_CLKIN_L09

R107 47.5R1%0402
R106 47.5R1%0402

HT_CTLIN_H09

HT_CTLIN_L09

HT_CADIN_H15
HT_CAD IN_L15
HT_CADIN_H14
HT_CAD IN_L14
HT_CADIN_H13
HT_CAD IN_L13
HT_CADIN_H12
HT_CAD IN_L12
HT_CADIN_H11
HT_CAD IN_L11
HT_CADIN_H10
HT_CAD IN_L10
HT_CADIN_H9
HT_CAD IN_L9
HT_CADIN_H8
HT_CAD IN_L8

HT_CADIN_H7
HT_CAD IN_L7
HT_CADIN_H6
HT_CAD IN_L6
HT_CADIN_H5
HT_CAD IN_L5
HT_CADIN_H4
HT_CAD IN_L4
HT_CADIN_H3
HT_CAD IN_L3
HT_CADIN_H2
HT_CAD IN_L2
HT_CADIN_H1
HT_CAD IN_L1
HT_CADIN_H0
HT_CAD IN_L0

C166

C4.7U10Y0805

N6

L0_CLKIN_H(1)

P6

L0_CLKIN_L(1)

N3

L0_CLKIN_H(0)

N2

L0_CLKIN_L(0)

V4

L0_CTLIN_H(1)

V5

L0_CTLIN_L(1)

U1

L0_CTLIN_H(0)

V1

L0_CTLIN_L(0)

U6

L0_CADIN_H(15)

V6

L0_CADIN_L(15)

T4

L0_CADIN_H(14)

T5

L0_CADIN_L(14)

R6

L0_CADIN_H(13)

T6

L0_CADIN_L(13)

P4

L0_CADIN_H(12)

P5

L0_CADIN_L(12)

M4

L0_CADIN_H(11)

M5

L0_CADIN_L(11)

L6

L0_CADIN_H(10)

M6

L0_CADIN_L(10)

K4

L0_CADIN_H(9)

K5

L0_CADIN_L(9)

J6

L0_CADIN_H(8)

K6

L0_CADIN_L(8)

U3

L0_CADIN_H(7)

U2

L0_CADIN_L(7)

R1

L0_CADIN_H(6)

T1

L0_CADIN_L(6)

R3

L0_CADIN_H(5)

R2

L0_CADIN_L(5)

N1

L0_CADIN_H(4)

P1

L0_CADIN_L(4)

L1

L0_CADIN_H(3)

M1

L0_CADIN_L(3)

L3

L0_CADIN_H(2)

L2

L0_CADIN_L(2)

J1

L0_CADIN_H(1)

K1

L0_CADIN_L(1)

J3

L0_CADIN_H(0)

J2

L0_CADIN_L(0)

C183
C0.22U16X

HYPERTRANSPORT

C221
C0.22U16X

CPU1A

L0_CLKOUT_H(1)

L0_CLKOUT_L(1)

L0_CLKOUT_H(0)

L0_CLKOUT_L(0)

L0_CTLOUT_H(1)

L0_CTLOUT_L(1)

L0_CTLOUT_H(0)

L0_CTLOUT_L(0)

L0_CADOUT_H(15)
L0_CADOUT_L(15)
L0_CADOUT_H(14)
L0_CADOUT_L(14)
L0_CADOUT_H(13)
L0_CADOUT_L(13)
L0_CADOUT_H(12)
L0_CADOUT_L(12)
L0_CADOUT_H(11)
L0_CADOUT_L(11)
L0_CADOUT_H(10)
L0_CADOUT_L(10)

L0_CADOUT_H(9)
L0_CADOUT_L(9)
L0_CADOUT_H(8)
L0_CADOUT_L(8)

L0_CADOUT_H(7)
L0_CADOUT_L(7)
L0_CADOUT_H(6)
L0_CADOUT_L(6)
L0_CADOUT_H(5)
L0_CADOUT_L(5)
L0_CADOUT_H(4)
L0_CADOUT_L(4)
L0_CADOUT_H(3)
L0_CADOUT_L(3)
L0_CADOUT_H(2)
L0_CADOUT_L(2)
L0_CADOUT_H(1)
L0_CADOUT_L(1)
L0_CADOUT_H(0)
L0_CADOUT_L(0)

C219
_C10P25N0402/0.25

AD5
AD4
AD1
AC1

Y6
W6
W2
W3

Y5
Y4
AB6
AA6
AB5
AB4
AD6
AC6
AF6
AE6
AF5
AF4
AH6
AG6
AH5
AH4

Y1
W1
AA2
AA3
AB1
AA1
AC2
AC3
AE2
AE3
AF1
AE1
AG2
AG3
AH1
AG1

C188
_C10P25N0402/0.25

HT_CLKOUT_H1 9
HT_CLKOUT_L1 9
HT_CLKOUT_H0 9
HT_CLKOUT_L0 9

HT_CTLOUT_H0 9
HT_CTLOUT_L0 9

HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8

HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0

VDDA_25

80L3_40_0805

2 1

VDDA25

L1

VDDA25

CPU_CLK9

CPU_CLK#9

C66

C3900P50X

C65

C3900P50X

R68

_169R1%-1

VCC_DDR

TP15
TP14

R94 300R 1%
R102 300R1%

VCC_DDR

R104

39.2R1%

CPU_STRAP_HI_E11
CPU_STRAP_LO_F11

R103

39.2R1%

TP3

R56 300R
R53 300R

TP4

THERMDC_CPU18
THERMDA_CPU18

CPUCLKIN
CPUCLKIN#

C38
X_C1000P50X

TP13

CPU_M_VREF

TP8
TP10
TP11
TP7
TP17

C57

C4.7U16Y1206

CPU_PWRGD
HT_STOP#
LDT_RST

CPU_PRESENT_L

CPU_TDI
CPU_TRST_L
CPU_TCK
CPU_TMS

CPU_DBREQ_L

COREFB+24

COREFB-24

TP2
TP1

C73

C69

C0.22U16X

C3300P50X

COREFB+
COREFB-

CPU_VTT_SENSE

CPU_TEST25_H
CPU_TEST25_L

C10
D10

AK6

AL10
AJ10

AH10

AH11

AJ11

AH9

AG9
AG8

AH7

A8
B8

C9
D8
C7

AL3

AL6

AL9

A5
G2

G1

E12

F12

A10
B10
F10

E9

AJ7

F6
D6

E7
F8
C5

E5

AJ5

AJ6

CPU1D

MISC

VDDA1
VDDA2

CLKIN_H
CLKIN_L

PWROK
LDTSTOP_L
RESET_L

CPU_PRESENT_L

SIC
SID

TDI
TRST_L
TCK
TMS

DBREQ_L
VDD_FB_H

VDD_FB_L
VTT_SENSE

M_VREF
M_ZN
M_ZP

TEST25_H
TEST25_L
TEST19
TEST18
TEST13
TEST9

TEST17
TEST16
TEST15
TEST14
TEST12

TEST7
TEST6
TEST5
TEST4
TEST3
TEST2

VCC_DDR

SW1 X_SW-TACT4PS

1

3

2

4

R44 X_100R

LDT_RST

R62
_15R1%0805-1

CPU_M_VREF

VCC_DDR

R63
_15R1%0805-1

VCC_DDR

1
3

CPU_DBREQ_L
CPU_DBRDY
CPU_TCK
CPU_TMS

A A

CPU_TDI
CPU_TRST_L
CPU_TDO

5
7

9
11
13
15
17
19
21
23

X_hdr_k8_hdt/B

5

J1

KEY

2
4
6
8
10
12
14
16
18
20
22

LDT_RST

24
26

CPU_PWRGD9

LDT_RST9

HT_STOP#9

4

CPU_PWRGD

LDT_RST

HT_STOP#

3

C0.1U16X

C70
C1000P50X

CPU_PRESENT_L
CPU_TEST25_H

CPU_TEST25_L

2

R109 1KR
R65 510RC75

R67 510R

GND 5,6,7,8,9 ,10,11,12,13,14, 15, 16, 17,18,19,20,21,22,23,24,25,26,27,28

Micro Star Restricted Secret

Title

ATHLON64 HT I/F CTRL & DEBUG

Document Number

MICRO-STAR INT ' L C O.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hs i e n, Taiwan
http://www.msi.com.tw

MS-7225H1

Last Revision Date:
Sheet

1

Monday, September 12, 2005

333

Rev

0A

of

5

4

3

2

1

MEM_MA_DQS_L[7..0]6,7

MEM_MA_DQS_H[7..0]6,7

MEM_MA_DM[7..0]6,7

MEM_MB_DQS_L[7..0]6,7

MEM_MB_DQS_H[7..0]6,7

MEM_MB_DM[7..0]6,7

D D

CPU1B

MEM_MA0_CLK_H26,8
MEM_MA0_CLK_L26,8

MEM_MA0_CLK_H16,8
MEM_MA0_CLK_L16,8
MEM_MA0_CLK_H06,8
MEM_MA0_CLK_L06,8

MEM_MA0_CS_L16,8
MEM_MA0_CS_L06,8

MEM_MA0_ODT06,8

MEM_MA1_CLK_H27,8

MEM_MA1_CLK_L27,8

MEM_MA1_CLK_H17,8

MEM_MA1_CLK_L17,8

MEM_MA1_CLK_H07,8

MEM_MA1_CLK_L07,8

MEM_MA1_CS_L17,8

MEM_MA1_CS_L07,8

MEM_MA1_ODT07,8

C C

MEM_MA_CAS_L6,7,8
MEM_MA_WE_L6,7,8
MEM_MA_RAS_L6,7,8

MEM_MA_BANK26,7,8
MEM_MA_BANK16,7,8
MEM_MA_BANK06,7,8

MEM_MA_CKE17,8
MEM_MA_CKE06,8

MEM_MA_ADD[15..0]6,7,8

B B

MEM_MA0_CLK_H2
MEM_MA0_CLK_L2
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H0
MEM_MA0_CLK_L0

MEM_MA0_CS_L1
MEM_MA0_CS_L0

MEM_MA0_ODT0

MEM_MA1_CLK_H2
MEM_MA1_CLK_L2
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H0
MEM_MA1_CLK_L0

MEM_MA1_CS_L1
MEM_MA1_CS_L0

MEM_MA1_ODT0

MEM_MA_CAS_L
MEM_MA_WE_L
MEM_MA_RAS_L

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_CKE1
MEM_MA_CKE0

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

MEM_MA_DM7
MEM_MA_DM6
MEM_MA_DM5
MEM_MA_DM4
MEM_MA_DM3
MEM_MA_DM2
MEM_MA_DM1
MEM_MA_DM0

AG21
AG20

G19
H19
U27
U26

AC25
AA24

AC28
AE20

AE19

G20
G21
V27
W27

AD27
AA25

AC27

AB25
AB27
AA26

N25
Y27

AA27

M25
M27

N24

AC26

N26
P25
Y25
N27
R24
P27
R25
R26
R27

U25
W24

AD15
AE15
AG18
AG19
AG24
AG25
AG27
AG28

D29
C29
C25
D25
E19

G15

AF15
AF19
AJ25
AH29

B29
E24
E18
H15

L27

T25
T27

F19
F15

MEMORY INTERFACE A

MA0_CLK_H(2)
MA0_CLK_L(2)
MA0_CLK_H(1)
MA0_CLK_L(1)
MA0_CLK_H(0)
MA0_CLK_L(0)

MA0_CS_L(1)
MA0_CS_L(0)

MA0_ODT(0)
MA1_CLK_H(2)

MA1_CLK_L(2)
MA1_CLK_H(1)
MA1_CLK_L(1)
MA1_CLK_H(0)
MA1_CLK_L(0)

MA1_CS_L(1)
MA1_CS_L(0)

MA1_ODT(0)

MA_CAS_L
MA_WE_L
MA_RAS_L

MA_BANK(2)
MA_BANK(1)
MA_BANK(0)

MA_CKE(1)
MA_CKE(0)

MA_ADD(15)
MA_ADD(14)
MA_ADD(13)
MA_ADD(12)
MA_ADD(11)
MA_ADD(10)
MA_ADD(9)
MA_ADD(8)
MA_ADD(7)
MA_ADD(6)
MA_ADD(5)
MA_ADD(4)
MA_ADD(3)
MA_ADD(2)
MA_ADD(1)
MA_ADD(0)

MA_DQS_H(7)
MA_DQS_L(7)
MA_DQS_H(6)
MA_DQS_L(6)
MA_DQS_H(5)
MA_DQS_L(5)
MA_DQS_H(4)
MA_DQS_L(4)
MA_DQS_H(3)
MA_DQS_L(3)
MA_DQS_H(2)
MA_DQS_L(2)
MA_DQS_H(1)
MA_DQS_L(1)
MA_DQS_H(0)
MA_DQS_L(0)

MA_DM(7)
MA_DM(6)
MA_DM(5)
MA_DM(4)
MA_DM(3)
MA_DM(2)
MA_DM(1)
MA_DM(0)

MA_DATA(63)
MA_DATA(62)
MA_DATA(61)
MA_DATA(60)
MA_DATA(59)
MA_DATA(58)
MA_DATA(57)
MA_DATA(56)
MA_DATA(55)
MA_DATA(54)
MA_DATA(53)
MA_DATA(52)
MA_DATA(51)
MA_DATA(50)
MA_DATA(49)
MA_DATA(48)
MA_DATA(47)
MA_DATA(46)
MA_DATA(45)
MA_DATA(44)
MA_DATA(43)
MA_DATA(42)
MA_DATA(41)
MA_DATA(40)
MA_DATA(39)
MA_DATA(38)
MA_DATA(37)
MA_DATA(36)
MA_DATA(35)
MA_DATA(34)
MA_DATA(33)
MA_DATA(32)
MA_DATA(31)
MA_DATA(30)
MA_DATA(29)
MA_DATA(28)
MA_DATA(27)
MA_DATA(26)
MA_DATA(25)
MA_DATA(24)
MA_DATA(23)
MA_DATA(22)
MA_DATA(21)
MA_DATA(20)
MA_DATA(19)
MA_DATA(18)
MA_DATA(17)
MA_DATA(16)
MA_DATA(15)
MA_DATA(14)
MA_DATA(13)
MA_DATA(12)
MA_DATA(11)
MA_DATA(10)

MA_DATA(9)
MA_DATA(8)
MA_DATA(7)
MA_DATA(6)
MA_DATA(5)
MA_DATA(4)
MA_DATA(3)
MA_DATA(2)
MA_DATA(1)
MA_DATA(0)

MA_DQS_H(8)

MA_DQS_L(8)

MA_DM(8)

MA_CHECK(7)
MA_CHECK(6)
MA_CHECK(5)
MA_CHECK(4)
MA_CHECK(3)
MA_CHECK(2)
MA_CHECK(1)
MA_CHECK(0)

MEM_MA_DATA63

AE14

MEM_MA_DATA62

AG14

MEM_MA_DATA61

AG16

MEM_MA_DATA60

AD17

MEM_MA_DATA59

AD13

MEM_MA_DATA58

AE13

MEM_MA_DATA57

AG15

MEM_MA_DATA56

AE16

MEM_MA_DATA55

AG17

MEM_MA_DATA54

AE18

MEM_MA_DATA53

AD21

MEM_MA_DATA52

AG22

MEM_MA_DATA51

AE17

MEM_MA_DATA50

AF17

MEM_MA_DATA49

AF21

MEM_MA_DATA48

AE21

MEM_MA_DATA47

AF23

MEM_MA_DATA46

AE23

MEM_MA_DATA45

AJ26

MEM_MA_DATA44

AG26

MEM_MA_DATA43

AE22

MEM_MA_DATA42

AG23

MEM_MA_DATA41

AH25

MEM_MA_DATA40

AF25

MEM_MA_DATA39

AJ28

MEM_MA_DATA38

AJ29

MEM_MA_DATA37

AF29

MEM_MA_DATA36

AE26

MEM_MA_DATA35

AJ27

MEM_MA_DATA34

AH27

MEM_MA_DATA33

AG29

MEM_MA_DATA32

AF27

MEM_MA_DATA31

E29

MEM_MA_DATA30

E28

MEM_MA_DATA29

D27

MEM_MA_DATA28

C27

MEM_MA_DATA27

G26

MEM_MA_DATA26

F27

MEM_MA_DATA25

C28

MEM_MA_DATA24

E27

MEM_MA_DATA23

F25

MEM_MA_DATA22

E25

MEM_MA_DATA21

E23

MEM_MA_DATA20

D23

MEM_MA_DATA19

E26

MEM_MA_DATA18

C26

MEM_MA_DATA17

G23

MEM_MA_DATA16

F23

MEM_MA_DATA15

E22

MEM_MA_DATA14

E21

MEM_MA_DATA13

F17

MEM_MA_DATA12

G17

MEM_MA_DATA11

G22

MEM_MA_DATA10

F21

MEM_MA_DATA9

G18

MEM_MA_DATA8

E17

MEM_MA_DATA7

G16

MEM_MA_DATA6

E15

MEM_MA_DATA5

G13

MEM_MA_DATA4

H13

MEM_MA_DATA3

H17

MEM_MA_DATA2

E16

MEM_MA_DATA1

E14

MEM_MA_DATA0

G14

MEM_MA_DQS_H8

J28

MEM_MA_DQS_L8

J27

MEM_MA_DM8

J25

MEM_MA_CHECK7

K25

MEM_MA_CHECK6

J26

MEM_MA_CHECK5

G28

MEM_MA_CHECK4

G27

MEM_MA_CHECK3

L24

MEM_MA_CHECK2

K27

MEM_MA_CHECK1

H29

MEM_MA_CHECK0

H27

MEM_MA_DATA[63..0] 6,7

MEM_MA_DQS_H8 6,7
MEM_MA_DQS_L8 6,7

MEM_MA_DM8 6,7

MEM_MB0_CLK_H26,8
MEM_MB0_CLK_L26,8
MEM_MB0_CLK_H16,8
MEM_MB0_CLK_L16,8

MEM_MB0_CLK_H06,8
MEM_MB0_CLK_L06,8

MEM_MB0_CS_L16,8

MEM_MB0_CS_L06,8

MEM_MB0_ODT06,8

MEM_MB1_CLK_H27,8
MEM_MB1_CLK_L27,8

MEM_MB1_CLK_H17,8

MEM_MB1_CLK_L17,8
MEM_MB1_CLK_H07,8
MEM_MB1_CLK_L07,8

MEM_MB1_CS_L17,8
MEM_MB1_CS_L07,8

MEM_MB1_ODT07,8

MEM_MB_CAS_L6,7,8
MEM_MB_WE_L6,7,8
MEM_MB_RAS_L6,7,8

MEM_MB_BANK26,7,8
MEM_MB_BANK16,7,8
MEM_MB_BANK06,7,8

MEM_MB_CKE17,8
MEM_MB_CKE06,8

MEM_MB_ADD[15..0]6,7,8

MEM_MB0_CLK_H2
MEM_MB0_CLK_L2
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H0
MEM_MB0_CLK_L0

MEM_MB0_CS_L1
MEM_MB0_CS_L0

MEM_MB0_ODT0

MEM_MB1_CLK_H2
MEM_MB1_CLK_L2
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H0
MEM_MB1_CLK_L0

MEM_MB1_CS_L1
MEM_MB1_CS_L0

MEM_MB1_ODT0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_CKE1
MEM_MB_CKE0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

MEM_MB_DM7
MEM_MB_DM6
MEM_MB_DM5
MEM_MB_DM4
MEM_MB_DM3
MEM_MB_DM2
MEM_MB_DM1
MEM_MB_DM0

AJ19

AK19

AE30
AC31

AD29
AL19

AL18

W29
W28

AE29
AB31

AD31

AC29
AC30
AB29

AA31
AA28

M31
M29

AE31

AA29

AA30
AK13

AJ13

AK17

AJ17
AK23
AL23
AL28
AL29

AJ14
AH17

AJ23
AK29

A18
A19
U31
U30

C19
D19

N31

N28
N29

N30
P29

P31
R29
R28
R31
R30
T31
T29
U29
U28

D31
C31
C24
C23
D17
C17
C14
C13

C30
A23
B17
B13

MB0_CLK_H(2)
MB0_CLK_L(2)
MB0_CLK_H(1)
MB0_CLK_L(1)
MB0_CLK_H(0)
MB0_CLK_L(0)

MB0_CS_L(1)
MB0_CS_L(0)

MB0_ODT(0)
MB1_CLK_H(2)

MB1_CLK_L(2)
MB1_CLK_H(1)
MB1_CLK_L(1)
MB1_CLK_H(0)
MB1_CLK_L(0)

MB1_CS_L(1)
MB1_CS_L(0)

MB1_ODT(0)

MB_CAS_L
MB_WE_L
MB_RAS_L

MB_BANK(2)
MB_BANK(1)
MB_BANK(0)

MB_CKE(1)
MB_CKE(0)

MB_ADD(15)
MB_ADD(14)
MB_ADD(13)
MB_ADD(12)
MB_ADD(11)
MB_ADD(10)
MB_ADD(9)
MB_ADD(8)
MB_ADD(7)
MB_ADD(6)
MB_ADD(5)
MB_ADD(4)
MB_ADD(3)
MB_ADD(2)
MB_ADD(1)
MB_ADD(0)

MB_DQS_H(7)
MB_DQS_L(7)
MB_DQS_H(6)
MB_DQS_L(6)
MB_DQS_H(5)
MB_DQS_L(5)
MB_DQS_H(4)
MB_DQS_L(4)
MB_DQS_H(3)
MB_DQS_L(3)
MB_DQS_H(2)
MB_DQS_L(2)
MB_DQS_H(1)
MB_DQS_L(1)
MB_DQS_H(0)
MB_DQS_L(0)

MB_DM(7)
MB_DM(6)
MB_DM(5)
MB_DM(4)
MB_DM(3)
MB_DM(2)
MB_DM(1)
MB_DM(0)

MEM_MA_CHECK[7..0] 6,7

CPU1C

MEMORY INTERFACE B

MB_DATA(63)
MB_DATA(62)
MB_DATA(61)
MB_DATA(60)
MB_DATA(59)
MB_DATA(58)
MB_DATA(57)
MB_DATA(56)
MB_DATA(55)
MB_DATA(54)
MB_DATA(53)
MB_DATA(52)
MB_DATA(51)
MB_DATA(50)
MB_DATA(49)
MB_DATA(48)
MB_DATA(47)
MB_DATA(46)
MB_DATA(45)
MB_DATA(44)
MB_DATA(43)
MB_DATA(42)
MB_DATA(41)
MB_DATA(40)
MB_DATA(39)
MB_DATA(38)
MB_DATA(37)
MB_DATA(36)
MB_DATA(35)
MB_DATA(34)
MB_DATA(33)
MB_DATA(32)
MB_DATA(31)
MB_DATA(30)
MB_DATA(29)
MB_DATA(28)
MB_DATA(27)
MB_DATA(26)
MB_DATA(25)
MB_DATA(24)
MB_DATA(23)
MB_DATA(22)
MB_DATA(21)
MB_DATA(20)
MB_DATA(19)
MB_DATA(18)
MB_DATA(17)
MB_DATA(16)
MB_DATA(15)
MB_DATA(14)
MB_DATA(13)
MB_DATA(12)
MB_DATA(11)
MB_DATA(10)

MB_DATA(9)
MB_DATA(8)
MB_DATA(7)
MB_DATA(6)
MB_DATA(5)
MB_DATA(4)
MB_DATA(3)
MB_DATA(2)
MB_DATA(1)
MB_DATA(0)

MB_DQS_H(8)

MB_DQS_L(8)

MB_DM(8)

MB_CHECK(7)
MB_CHECK(6)
MB_CHECK(5)
MB_CHECK(4)
MB_CHECK(3)
MB_CHECK(2)
MB_CHECK(1)
MB_CHECK(0)

AH13
AL13
AL15
AJ15
AF13
AG13
AL14
AK15
AL16
AL17
AK21
AL21
AH15
AJ16
AH19
AL20
AJ22
AL22
AL24
AK25
AJ21
AH21
AH23
AJ24
AL27
AK27
AH31
AG30
AL25
AL26
AJ30
AJ31
E31
E30
B27
A27
F29
F31
A29
A28
A25
A24
C22
D21
A26
B25
B23
A22
B21
A20
C16
D15
C21
A21
A17
A16
B15
A14
E13
F13
C15
A15
A13
D13

J31
J30

J29
K29

K31
G30
G29
L29
L28
H31
G31

MEM_MB_DATA63
MEM_MB_DATA62
MEM_MB_DATA61
MEM_MB_DATA60
MEM_MB_DATA59
MEM_MB_DATA58
MEM_MB_DATA57
MEM_MB_DATA56
MEM_MB_DATA55
MEM_MB_DATA54
MEM_MB_DATA53
MEM_MB_DATA52
MEM_MB_DATA51
MEM_MB_DATA50
MEM_MB_DATA49
MEM_MB_DATA48
MEM_MB_DATA47
MEM_MB_DATA46
MEM_MB_DATA45
MEM_MB_DATA44
MEM_MB_DATA43
MEM_MB_DATA42
MEM_MB_DATA41
MEM_MB_DATA40
MEM_MB_DATA39
MEM_MB_DATA38
MEM_MB_DATA37
MEM_MB_DATA36
MEM_MB_DATA35
MEM_MB_DATA34
MEM_MB_DATA33
MEM_MB_DATA32
MEM_MB_DATA31
MEM_MB_DATA30
MEM_MB_DATA29
MEM_MB_DATA28
MEM_MB_DATA27
MEM_MB_DATA26
MEM_MB_DATA25
MEM_MB_DATA24
MEM_MB_DATA23
MEM_MB_DATA22
MEM_MB_DATA21
MEM_MB_DATA20

MEM_MB_DATA19
MEM_MB_DATA18
MEM_MB_DATA17
MEM_MB_DATA16
MEM_MB_DATA15
MEM_MB_DATA14
MEM_MB_DATA13
MEM_MB_DATA12
MEM_MB_DATA11
MEM_MB_DATA10

MEM_MB_DATA9

MEM_MB_DATA8

MEM_MB_DATA7

MEM_MB_DATA6

MEM_MB_DATA5

MEM_MB_DATA4

MEM_MB_DATA3

MEM_MB_DATA2

MEM_MB_DATA1

MEM_MB_DATA0

MEM_MB_DQS_H8
MEM_MB_DQS_L8

MEM_MB_DM8

MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0

MEM_MB_DQS_H8 6,7
MEM_MB_DQS_L8 6,7

MEM_MB_DM8 6,7

MEM_MB_CHECK[7..0] 6,7

MEM_MB_DATA[63..0] 6,7

A A

Micro Star Restricted Secret

Title

ATHLON64 DDR MEMORY I/F

Document Number

MICRO-STAR INT ' L C O.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hs i e n, Taiwan

5

4

3

2

http://www.msi.com.tw

MS-7225H1

Last Revision Date:
Sheet

1

Monday, September 12, 2005

433

Rev

0A

of

5

4

3

2

1

VCCP

CPU1F

VDD1

A4

VDD1

A6

VDD2

AA8

VDD3

D D

C C

B B

AA10
AA12
AA14
AA16
AA18

AB11

AC10

AE10

AB7
AB9

AC4
AC5
AC8

AD2
AD3
AD7
AD9

AF7
AF9
AG4
AG5
AG7
AH2
AH3

E10

F11

G10
G12

H11
H23

K11
K13
K15
K17
K19
K21
K23

Y17
Y19

VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27

B3

VDD28

B5

VDD29

B7

VDD30

C2

VDD31

C4

VDD32

C6

VDD33

C8

VDD34

D3

VDD35

D5

VDD36

D7

VDD37

D9

VDD38

E4

VDD39

E6

VDD40

E8

VDD41
VDD42

F5

VDD43

F7

VDD44

F9

VDD45
VDD46

G6

VDD47

G8

VDD48
VDD49
VDD50

H7

VDD51
VDD52
VDD53

J8

VDD54

J12

VDD55

J14

VDD56

J16

VDD57

J18

VDD58

J20

VDD59

J22

VDD60

J24

VDD61

K7

VDD62

K9

VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70

L4

VDD71

L5

VDD72

L8

VDD73

L10

VDD74

L12

VDD75
VDD150
VDD151

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74

VSS240
VSS241

A3
A7
A9
A11
AA4
AA5
AA7
AA9
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AB2
AB3
AB8
AB10
AB12
AB14
AB16
AB18
AB20
AB22
AC7
AC9
AC11
AC13
AC15
AC17
AC19
AC21
AC23
AD8
AD10
AD12
AD14
AD16
AD20
AD22
AD24
AE4
AE5
AE9
AE11
AF2
AF3
AF8
AF10
AF12
AF14
AF16
AF18
AF20
AF22
AF24
AF26
AF28
AG10
AG11
AH14
AH16
AH18
AH20
AH22
AH24
AH26
AH28
AH30
AK2
AK14
AK16
AK18
Y14
Y16

VCCP

M11
M13
M15
M17
M19

N10
N12
N14
N16
N18

P11
P13
P15
P17
P19

R10
R12
R14
R16
R18
R20

U10
U12
U14
U16
U18
U20

V11
V13
V15
V17
V19
V21

W10
W12
W14
W16
W18
W20

Y11
Y13
Y15
Y21

CPU1G

L14
L16
L18

T11
T13
T15
T17
T19
T21

VDD2

VDD1
VDD2
VDD3

M2

VDD4

M3

VDD5

M7

VDD6

M9

VDD7
VDD8
VDD9
VDD10
VDD11
VDD12

N8

VDD13
VDD14
VDD15
VDD16
VDD17
VDD18

P7

VDD19

P9

VDD20
VDD21
VDD22
VDD23
VDD24
VDD25

R4

VDD26

R5

VDD27

R8

VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34

T2

VDD35

T3

VDD36

T7

VDD37

T9

VDD38
VDD39
VDD40
VDD41
VDD42
VDD43
VDD44

U8

VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51

V9

VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58

W4

VDD59

W5

VDD60

W8

VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67

Y2

VDD68

Y3

VDD69

Y7

VDD70

Y9

VDD71
VDD72
VDD73
VDD74
VDD75

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75

AK20
AK22
AK24
AK26
AK28
AK30
AL5
B4
B9
B11
B14
B16
B18
B20
B22
B24
B26
B28
B30
C3
D14
D16
D18
D20
D22
D24
D26
D28
D30
E11
F4
F14
F16
F18
F20
F22
F24
F26
F28
F30
G9
G11
H8
H10
H12
H14
H16
H18
H22
H24
H26
H28
H30
J4
J5
J7
J9
J11
J13
J15
J17
J19
J21
J23
K2
K3
K8
K10
K12
K14
K16
K18
K20
K22
Y18

VCCP

AA20
AA22
AB13
AB15
AB17
AB19
AB21
AB23
AC12
AC14
AC16
AC18
AC20
AC22
AD11
AD23
AE12
AF11

M21
M23
N20
N22

R22
U22
W22

L20
L22

P21
P23

T23
V23
Y23

CPU1H

VDD3

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32

5

GND

6

GND

7

GND

8

GND

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

N17
N19
N21
N23
P2
P3
P8
P10
P12
P14
P16
P18
P20
P22
R7
R9
R11
R13
R15
R17
R19
R21
R23
T8
T10
T12
T14
T16
T18
T20
T22
U4
U5
U7
U9
U11
U13
U15
U17
U19
U21
U23
V2
V3
V10
V12
V14
V16
V18
V20
V22
W9
W11
W13
W15
W17
W19
W21
W23
Y8
Y10
Y12
W7
Y20
Y22

VCCP

C557

C556

C22U6.3X1206/B

C22U6.3X1206/B

C22U6.3X1206/B

VCC_DDR

C560

VCC1_2HT

VTT_DDR

VCCP

C22U6.3X1206/B

C564
C0.22U16X/B

C552

AJ4

VLDT_A1

AJ3

VLDT_A2

AJ2

VLDT_A3

AJ1

VLDT_A4

D12

VTT1

C12

VTT2

B12

VTT3

A12

VTT4

AB24

VDDIO1

AB26

VDDIO2

AB28

VDDIO3

AB30

VDDIO4

AC24

VDDIO5

AD26

VDDIO6

AD28

VDDIO7

AD30

VDDIO8

AF30

VDDIO9

M24

VDDIO10

M26

VDDIO11

M28

VDDIO12

M30

VDDIO13

P24

VDDIO14

P26

VDDIO15

P28

VDDIO16

P30

VDDIO17

T24

VDDIO18

T26

VDDIO19

T28

VDDIO20

T30

VDDIO21

V25

VDDIO22

V26

VDDIO23

V28

VDDIO24

V30

VDDIO25

Y24

VDDIO26

Y26

VDDIO27

Y28

VDDIO28

Y29

VDDIO29

C575
C0.22U16X/B

C554

C22U6.3X1206/B

CPU1I

VDDIO

VLDT_B1
VLDT_B2
VLDT_B3
VLDT_B4

VTT5
VTT6
VTT7
VTT8
VTT9

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8

VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28

C571
C0.22U16X/B

C553

C22U6.3X1206/B

H6
H5
H2
H1

AK12
AJ12
AH12
AG12
AL12

K24
K26
K28
K30
L7
L9
L11
L13
L15
L17
L19
L21
L23
M8
M10
M12
M14
M16
M18
M20
M22
N4
N5
N7
N9
N11
N13
N15

C547
C0.01U50X/B

C570

C22U6.3X1206/B

VLDT_RUN_B

VTT_DDR

C548
_C10P25N0402/0.25/B

C550

C22U6.3X1206/B

C549

C22U6.3X1206/B

C94
C4.7U16Y1206

GND 3,6,7,8,9, 10,11,12,13,14,15,16, 17,18,19,20,21,22,23,24,25,26,27,28

C558

C22U6.3X1206/B

C60

C22U6.3X1206

C561

C22U6.3X1206/B

C90

C22U6.3X1206

C563

C22U6.3X1206/B

C136

C22U6.3X1206

VTT_DDR

C36
C4.7U10Y0805

C50
C10P16N

C39
C10P16N

C74
C1000P50X

C53
C1000P50X

C34
C42
C0.22U16X

A A

C68
C0.22U16X

C4.7U10Y0805

VCC_DDR

C551
C0.22U16X/B

C559
C0.22U16X/B

C224
C0.22U16X

C259
C4.7U10Y0805

C76
C4.7U10Y0805

VCC_DDR

C22U6.3X1206/B

C562

C567

C4.7U10Y0805

C22U6.3X1206/B

C102

C87

C4.7U10Y0805

C555
C0.22U16X/B

C179
C0.22U16X

C97
C0.22U16X

C574
C0.01U50X/B

C269
_C10P25N0402/0.25

VTT_DDR

C189
C0.22U16X

C192
C0.22U16X

5

C201

C4.7U10Y0805

C203
C4.7U10Y0805

C194
C10P16N

C169
C10P16N

C160
C1000P50X

C187
C1000P50X

4

Micro Star Restricted Secret

Title

ATHLON64 PWR & GND

Document Number

MICRO-STAR INT ' L C O.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hs i e n, Taiwan

3

2

http://www.msi.com.tw

MS-7225H1

Last Revision Date:
Sheet

1

Monday, September 12, 2005

533

Rev

0A

of

5

4

3

2

1

MEM_MA_DQS_H[7..0]4,7
MEM_MA_DQS_L[7..0]4,7

D D

MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

R192 33R
R187 33R

MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_ADD15
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0

MEM_MA0_CLK_H0
MEM_MA0_CLK_L0
MEM_MA0_CLK_H1
MEM_MA0_CLK_L1
MEM_MA0_CLK_H2
MEM_MA0_CLK_L2

MEM_MA_CKE0

MEM_MA_RAS_L
MEM_MA_CAS_L

MEM_MA0_CS_L0
MEM_MA0_CS_L1

5

MEM_MA_DM8

MEM_MA_DM7

MEM_MA_DM6

MEM_MA_DM5

MEM_MA_DM4

MEM_MA_DM3

MEM_MA_DM2

MEM_MA_DM1

MEM_MA_DM0

SMB_MEMCLK
SMB_MEMDATA

MEM_MA_DM84,7

MEM_MA_DM[7..0]4,7

MEM_MA_DQS_H84,7
MEM_MA_DQS_L84,7

C C

SMB_MEM_CLK13

SMB_MEM_DATA13
MEM_MA_BANK24,7,8
MEM_MA_BANK14,7,8
MEM_MA_BANK04,7,8

MEM_MA_ADD[15..0]4,7,8

B B

MEM_MA_CHECK[7..0]4,7

MEM_MA0_CLK_H04,8
MEM_MA0_CLK_L04,8
MEM_MA0_CLK_H14,8
MEM_MA0_CLK_L14,8
MEM_MA0_CLK_H24,8
MEM_MA0_CLK_L24,8

MEM_MA_CKE04,8
MEM_MA_RAS_L4,7,8

MEM_MA_CAS_L4,7,8

A A

MEM_MA0_CS_L04,8
MEM_MA0_CS_L14,8

VCC_DDR

69

170

172

178

184

187

189

VDD1

VDD2

VDD3

VDD4

164

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

VDD5

175

197

64

VDD6

VDD753VDD859VDD9

VDD1067VDD11

VDDQ1

VDDQ2

DIMM 3

ADDR=1010000B

181

VDDQ3

191

194

VDDQ4

VDDQ5

72

VDDQ651VDDQ756VDDQ862VDDQ9

VCC3

78

VDDQ1075VDDQ11

238

DIMM3

VDDSPD

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

WE_L
VREF

ODT0
ODT1

ERR_OUT_L

PAR_IN

MEM_MA_DATA63

236

MEM_MA_DATA62

235

MEM_MA_DATA61

230

MEM_MA_DATA60

229

MEM_MA_DATA59

117

MEM_MA_DATA58

116

MEM_MA_DATA57

111

MEM_MA_DATA56

110

MEM_MA_DATA55

227

MEM_MA_DATA54

226

MEM_MA_DATA53

218

MEM_MA_DATA52

217

MEM_MA_DATA51

108

MEM_MA_DATA50

107

MEM_MA_DATA49

99

MEM_MA_DATA48

98

MEM_MA_DATA47

215

MEM_MA_DATA46

214

MEM_MA_DATA45

209

MEM_MA_DATA44

208

MEM_MA_DATA43

96

MEM_MA_DATA42

95

MEM_MA_DATA41

90

MEM_MA_DATA40

89

MEM_MA_DATA39

206

MEM_MA_DATA38

205

MEM_MA_DATA37

200

MEM_MA_DATA36

199

MEM_MA_DATA35

87

MEM_MA_DATA34

86

MEM_MA_DATA33

81

MEM_MA_DATA32

80

MEM_MA_DATA31

159

MEM_MA_DATA30

158

MEM_MA_DATA29

153

MEM_MA_DATA28

152

MEM_MA_DATA27

40

MEM_MA_DATA26

39

MEM_MA_DATA25

34

MEM_MA_DATA24

33

MEM_MA_DATA23

150

MEM_MA_DATA22

149

MEM_MA_DATA21

144

MEM_MA_DATA20

143

MEM_MA_DATA19

31

MEM_MA_DATA18

30

MEM_MA_DATA17

25

MEM_MA_DATA16

24

MEM_MA_DATA15

141

MEM_MA_DATA14

140

MEM_MA_DATA13

132

MEM_MA_DATA12

131

MEM_MA_DATA11

22

MEM_MA_DATA10

21

MEM_MA_DATA9

13

DQ9

MEM_MA_DATA8

12

DQ8

MEM_MA_DATA7

129

DQ7

MEM_MA_DATA6

128

DQ6

MEM_MA_DATA5

123

DQ5

MEM_MA_DATA4

122

DQ4

MEM_MA_DATA3

10

DQ3

MEM_MA_DATA2

9

DQ2

MEM_MA_DATA1

4

DQ1

MEM_MA_DATA0MEM_MA_CHECK7

3

DQ0

MEM_MA_WE_L

73

VDDR_VREF

1
102

TEST

MEM_MA0_ODT0

195
77

55
68

19

NC1

4

MEM_MA_DATA[63..0] 4, 7

MEM_MA_WE_L 4,7,8

MEM_MA0_ODT0 4,8

VDDR_VREF

C52
C0.1U25Y

MEM_MB_DQS_H[7..0]4,7
MEM_MB_DQS_L[7..0]4,7

VCC3

MEM_MB_DM8

MEM_MB_DM7

MEM_MB_DM6

MEM_MB_DM5

MEM_MB_DM4

MEM_MB_DM3

MEM_MB_DM2

MEM_MB_DM1

MEM_MB_DM0

MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

SMB_MEMCLK
SMB_MEMDATA
MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_CHECK7

MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0

MEM_MB0_CLK_H0
MEM_MB0_CLK_L0
MEM_MB0_CLK_H1
MEM_MB0_CLK_L1
MEM_MB0_CLK_H2
MEM_MB0_CLK_L2

MEM_MB_CKE0

MEM_MB_RAS_L
MEM_MB_CAS_L

MEM_MB0_CS_L0
MEM_MB0_CS_L1

3

MEM_MB_DM84,7

MEM_MB_DM[7..0]4,7

MEM_MB_DQS_H84,7
MEM_MB_DQS_L84,7

MEM_MB_BANK24,7,8
MEM_MB_BANK14,7,8
MEM_MB_BANK04,7,8

MEM_MB_ADD[15..0]4,7,8

MEM_MB_CHECK[7..0]4,7

MEM_MB0_CLK_H04,8
MEM_MB0_CLK_L04,8
MEM_MB0_CLK_H14,8
MEM_MB0_CLK_L14,8
MEM_MB0_CLK_H24,8
MEM_MB0_CLK_L24,8

MEM_MB_CKE04,8
MEM_MB_RAS_L4,7,8

MEM_MB_CAS_L4,7,8
MEM_MB0_CS_L04,8

MEM_MB0_CS_L14,8

VCC_DDR

69

170

175

172

178

184

187

189

197

VDD1

VDD2

VDD3

VDD4

164

DQS17_H

165

DQS17_L

232

DQS16_H

233

DQS16_L

223

DQS15_H

224

DQS15_L

211

DQS14_H

212

DQS14_L

202

DQS13_H

203

DQS13_L

155

DQS12_H

156

DQS12_L

146

DQS11_H

147

DQS11_L

134

DQS10_H

135

DQS10_L

125

DQS9_H

126

DQS9_L

46

DQS8_H

45

DQS8_L

114

DQS7_H

113

DQS7_L

105

DQS6_H

104

DQS6_L

93

DQS5_H

92

DQS5_L

84

DQS4_H

83

DQS4_L

37

DQS3_H

36

DQS3_L

28

DQS2_H

27

DQS2_L

16

DQS1_H

15

DQS1_L

7

DQS0_H

6

DQS0_L

101

SA2

240

SA1

239

SA0

120

SCL

119

SDA

54

BA2

190

BA1

71

BA0

173

A15

174

A14

196

A13

176

A12

57

A11

70

A10

177

A9

179

A8

58

A7

180

A6

60

A5

61

A4

182

A3

63

A2

183

A1

188

A0

168

CB7

167

CB6

162

CB5

161

CB4

49

CB3

48

CB2

43

CB1

42

CB0

185

CK0_H

186

CK0_L

137

CK1_H

138

CK1_L

220

CK2_H

221

CK2_L

18

RESET_L

52

CKE0

171

CKE1

192

RAS_L

74

CAS_L

193

S0_L

76

S1_L

VDD5

181

64

VDD6

VDD753VDD859VDD9

VDD1067VDD11

VDDQ1

VDDQ2

DIMM 1

ADDR=1010001B

191

VDDQ3

194

VDDQ4

VDDQ5

72

VDDQ651VDDQ756VDDQ862VDDQ9

78

VDDQ1075VDDQ11

VCC3

238

VDDSPD

ERR_OUT_L

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

WE_L
VREF

TEST

ODT0
ODT1

PAR_IN

DIMM1

MEM_MB_DATA63

236

MEM_MB_DATA62

235

MEM_MB_DATA61

230

MEM_MB_DATA60

229

MEM_MB_DATA59

117

MEM_MB_DATA58

116

MEM_MB_DATA57

111

MEM_MB_DATA56

110

MEM_MB_DATA55

227

MEM_MB_DATA54

226

MEM_MB_DATA53

218

MEM_MB_DATA52

217

MEM_MB_DATA51

108

MEM_MB_DATA50

107

MEM_MB_DATA49

99

MEM_MB_DATA48

98

MEM_MB_DATA47

215

MEM_MB_DATA46

214

MEM_MB_DATA45

209

MEM_MB_DATA44

208

MEM_MB_DATA43

96

MEM_MB_DATA42

95

MEM_MB_DATA41

90

MEM_MB_DATA40

89

MEM_MB_DATA39

206

MEM_MB_DATA38

205

MEM_MB_DATA37

200

MEM_MB_DATA36

199

MEM_MB_DATA35

87

MEM_MB_DATA34

86

MEM_MB_DATA33

81

MEM_MB_DATA32

80

MEM_MB_DATA31

159

MEM_MB_DATA30

158

MEM_MB_DATA29

153

MEM_MB_DATA28

152

MEM_MB_DATA27

40

MEM_MB_DATA26

39

MEM_MB_DATA25

34

MEM_MB_DATA24

33

MEM_MB_DATA23

150

MEM_MB_DATA22

149

MEM_MB_DATA21

144

MEM_MB_DATA20

143

MEM_MB_DATA19

31

MEM_MB_DATA18

30

MEM_MB_DATA17

25

MEM_MB_DATA16

24

MEM_MB_DATA15

141

MEM_MB_DATA14

140

MEM_MB_DATA13

132

MEM_MB_DATA12

131

MEM_MB_DATA11

22

MEM_MB_DATA10

21

MEM_MB_DATA9

13

DQ9

MEM_MB_DATA8

12

DQ8

MEM_MB_DATA7

129

DQ7

MEM_MB_DATA6

128

DQ6

MEM_MB_DATA5

123

DQ5

MEM_MB_DATA4

122

DQ4

MEM_MB_DATA3

10

DQ3

MEM_MB_DATA2

9

DQ2

MEM_MB_DATA1

4

DQ1

MEM_MB_DATA0

3

DQ0

MEM_MB_WE_L

73

VDDR_VREF

1
102

MEM_MB0_ODT0

195
77

55
68

19

NC1

2

MEM_MB_DATA[63..0] 4, 7

MEM_MB_WE_L 4,7,8

VDDR_VREF

C63
C0.1U25Y

MEM_MB0_ODT0 4 ,8

SMB_MEMCLK

SMB_MEMDATA

SMB_MEM_CLK

SMB_MEM_DATA

VCC_DDR

R55

56.2R1%

R66

56.2R1%

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li- De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

SMB_MEMCLK 7
SMB_MEMDATA 7

VCC_DDR

2

3

D18
BAV99W_SOT323

1

VCC_DDR

2

3

D17
BAV99W_SOT323

1

VDDR_VREF

C43
C0.1U16X

VDDR_VREF

C56

C59

C1000P50X

C0.1U16X

Micro Star Restricted Secret

FIRST LOGICAL DDR DIMM

MS-7225H1

Last Revision Date:

Monday, September 12, 2005

Sheet

1

Rev

0A

of

633

5

4

3

2

1

MEM_MA_DQS_H[7..0]4,6
MEM_MA_DQS_L[7..0]4,6

D D

MEM_MA_DM84,6

MEM_MA_DM[7..0]4,6

MEM_MA_DQS_H84,6

C C

B B

MEM_MA_DQS_L84,6

SMB_MEMCLK6
SMB_MEMDATA6
MEM_MA_BANK24,6,8
MEM_MA_BANK14,6,8
MEM_MA_BANK04,6,8

MEM_MA_ADD[15..0]4,6,8

MEM_MA_CHECK[7..0]4,6

MEM_MA1_CLK_H04,8
MEM_MA1_CLK_L04,8
MEM_MA1_CLK_H14,8
MEM_MA1_CLK_L14,8
MEM_MA1_CLK_H24,8
MEM_MA1_CLK_L24,8

MEM_MA_CKE14,8

A A

MEM_MA_RAS_L4,6,8
MEM_MA_CAS_L4,6,8

MEM_MA1_CS_L04,8
MEM_MA1_CS_L14,8

MEM_MA_DM8

MEM_MA_DM7

MEM_MA_DM6

MEM_MA_DM5

MEM_MA_DM4

MEM_MA_DM3

MEM_MA_DM2

MEM_MA_DM1

MEM_MA_DM0

MEM_MA_DQS_H8
MEM_MA_DQS_L8
MEM_MA_DQS_H7
MEM_MA_DQS_L7
MEM_MA_DQS_H6
MEM_MA_DQS_L6
MEM_MA_DQS_H5
MEM_MA_DQS_L5
MEM_MA_DQS_H4
MEM_MA_DQS_L4
MEM_MA_DQS_H3
MEM_MA_DQS_L3
MEM_MA_DQS_H2
MEM_MA_DQS_L2
MEM_MA_DQS_H1
MEM_MA_DQS_L1
MEM_MA_DQS_H0
MEM_MA_DQS_L0

VCC3

SMB_MEMCLK
SMB_MEMDATA
MEM_MA_BANK2
MEM_MA_BANK1
MEM_MA_BANK0

MEM_MA_ADD15 MEM_MA_DATA17
MEM_MA_ADD14
MEM_MA_ADD13
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD10
MEM_MA_ADD9
MEM_MA_ADD8
MEM_MA_ADD7
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD2
MEM_MA_ADD1
MEM_MA_ADD0

MEM_MA_CHECK7
MEM_MA_CHECK6
MEM_MA_CHECK5
MEM_MA_CHECK4
MEM_MA_CHECK3
MEM_MA_CHECK2
MEM_MA_CHECK1
MEM_MA_CHECK0

MEM_MA1_CLK_H0
MEM_MA1_CLK_L0
MEM_MA1_CLK_H1
MEM_MA1_CLK_L1
MEM_MA1_CLK_H2
MEM_MA1_CLK_L2

MEM_MA_CKE1

MEM_MA_RAS_L
MEM_MA_CAS_L

MEM_MA1_CS_L0
MEM_MA1_CS_L1

5

VCC_DDR VCC3

69

VDD4

170

189

197

64

VDD5

VDD6

VDD753VDD859VDD9

VDD1067VDD11

172

178

184

187

VDD1

VDD2

DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L

SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0

CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L

RESET_L
CKE0

CKE1
RAS_L
CAS_L

S0_L
S1_L

VDD3

DIMM 4

ADDR=1010010B

164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126

46

45
114
113
105
104

93

92

84

83

37

36

28

27

16

15

7
6

101
240
239
120
119

54
190

71
173

174
196
176

57

70
177
179

58
180

60

61
182

63
183
188

168
167
162
161

49

48

43

42
185

186
137
138
220
221

18

52
171
192

74
193

76

175

VDDQ1

181

VDDQ2

191

VDDQ3

194

VDDQ4

VDDQ5

72

VDDQ651VDDQ756VDDQ862VDDQ9

78

VDDQ1075VDDQ11

238

VDDSPD

WE_L
VREF

ODT0
ODT1

ERR_OUT_L

PAR_IN

4

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

TEST

DIMM4

MEM_MA_WE_L 4,6,8

MEM_MA1_ODT0 4 ,8

MEM_MA_DATA[63..0] 4, 6

VDDR_VREF VDDR_VREF

C54
C0.1U25Y

3

MEM_MB_DM[7..0]4,6

MEM_MA_DATA63

236

MEM_MA_DATA62

235

MEM_MA_DATA61

230

MEM_MA_DATA60

229

MEM_MA_DATA59

117

MEM_MA_DATA58

116

MEM_MA_DATA57

111

MEM_MA_DATA56

110

MEM_MA_DATA55

227

MEM_MA_DATA54

226

MEM_MA_DATA53

218

MEM_MA_DATA52

217

MEM_MA_DATA51

108

MEM_MA_DATA50

107

MEM_MA_DATA49

99

MEM_MA_DATA48

98

MEM_MA_DATA47

215

MEM_MA_DATA46

214

MEM_MA_DATA45

209

MEM_MA_DATA44

208

MEM_MA_DATA43

96

MEM_MA_DATA42

95

MEM_MA_DATA41

90

MEM_MA_DATA40

89

MEM_MA_DATA39

206

MEM_MA_DATA38

205

MEM_MA_DATA37

200

MEM_MA_DATA36

199

MEM_MA_DATA35

87

MEM_MA_DATA34

86

MEM_MA_DATA33

81

MEM_MA_DATA32

80

MEM_MA_DATA31

159

MEM_MA_DATA30

158

MEM_MA_DATA29

153

MEM_MA_DATA28

152

MEM_MA_DATA27

40

MEM_MA_DATA26

39

MEM_MA_DATA25

34

MEM_MA_DATA24

33

MEM_MA_DATA23

150

MEM_MA_DATA22

149

MEM_MA_DATA21

144

MEM_MA_DATA20

143

MEM_MA_DATA19

31

MEM_MA_DATA18

30
25

MEM_MA_DATA16

24

MEM_MA_DATA15

141

MEM_MA_DATA14

140

MEM_MA_DATA13

132

MEM_MA_DATA12

131

MEM_MA_DATA11

22

MEM_MA_DATA10

21

MEM_MA_DATA9

13

DQ9

MEM_MA_DATA8

12

DQ8

MEM_MA_DATA7

129

DQ7

MEM_MA_DATA6

128

DQ6

MEM_MA_DATA5

123

DQ5

MEM_MA_DATA4

122

DQ4

MEM_MA_DATA3

10

DQ3

MEM_MA_DATA2

9

DQ2

MEM_MA_DATA1

4

DQ1

MEM_MA_DATA0

3

DQ0

MEM_MA_WE_L

73
1
102

MEM_MA1_ODT0

195
77

55
68

19

NC1

MEM_MB_DQS_L[7..0]4,6
MEM_MB_DQS_H[7..0]4,6

VCC_DDR VCC3

181

VDDQ2

191

VDDQ3

194

VDDQ4

VDDQ5

VDDQ651VDDQ756VDDQ862VDDQ9

78

238

72

DIMM2

VDDQ1075VDDQ11

VDDSPD

ERR_OUT_L

PAR_IN

DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10

WE_L
VREF
TEST
ODT0

ODT1

MEM_MB_DATA63

236

MEM_MB_DATA62

235

MEM_MB_DATA61

230

MEM_MB_DATA60

229

MEM_MB_DATA59

117

MEM_MB_DATA58

116

MEM_MB_DATA57

111

MEM_MB_DATA56

110

MEM_MB_DATA55

227

MEM_MB_DATA54

226

MEM_MB_DATA53

218

MEM_MB_DATA52

217

MEM_MB_DATA51

108

MEM_MB_DATA50

107

MEM_MB_DATA49

99

MEM_MB_DATA48

98

MEM_MB_DATA47

215

MEM_MB_DATA46

214

MEM_MB_DATA45

209

MEM_MB_DATA44

208

MEM_MB_DATA43

96

MEM_MB_DATA42

95

MEM_MB_DATA41

90

MEM_MB_DATA40

89

MEM_MB_DATA39

206

MEM_MB_DATA38

205

MEM_MB_DATA37

200

MEM_MB_DATA36

199

MEM_MB_DATA35

87

MEM_MB_DATA34

86

MEM_MB_DATA33

81

MEM_MB_DATA32

80

MEM_MB_DATA31

159

MEM_MB_DATA30

158

MEM_MB_DATA29

153

MEM_MB_DATA28

152

MEM_MB_DATA27

40

MEM_MB_DATA26

39

MEM_MB_DATA25

34

MEM_MB_DATA24

33

MEM_MB_DATA23

150

MEM_MB_DATA22

149

MEM_MB_DATA21

144

MEM_MB_DATA20

143

MEM_MB_DATA19

31

MEM_MB_DATA18

30

MEM_MB_DATA17

25

MEM_MB_DATA16

24

MEM_MB_DATA15

141

MEM_MB_DATA14

140

MEM_MB_DATA13

132

MEM_MB_DATA12

131

MEM_MB_DATA11

22

MEM_MB_DATA10

21

MEM_MB_DATA9

13

DQ9

MEM_MB_DATA8

12

DQ8

MEM_MB_DATA7

129

DQ7

MEM_MB_DATA6

128

DQ6

MEM_MB_DATA5

123

DQ5

MEM_MB_DATA4

122

DQ4

MEM_MB_DATA3

10

DQ3

MEM_MB_DATA2

9

DQ2

MEM_MB_DATA1

4

DQ1

MEM_MB_DATA0

3

DQ0

MEM_MB_WE_L

73
1
102

MEM_MB1_ODT0

195
77

55
68

19

NC1

MEM_MB1_ODT0 4 ,8

Title

Document Number

MICRO-STAR INT'L CO.,LTD.

No. 69, Li- De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MEM_MB_DATA[63..0] 4, 6

MEM_MB_WE_L 4,6,8

C46

C0.1U25Y

Micro Star Restricted Secret

SECOND LOGICAL DDR DIMM

MS-7225H1

Last Revision Date:

Monday, September 12, 2005

Sheet

1

733

Rev

0A

of

69

170

VDD5

197

VDD6

64

VDD753VDD859VDD9

175

VDD1067VDD11

VDDQ1

172

178

184

187

189

VDD1

VDD2

VDD3

MEM_MB_DM84,6

MEM_MB_DQS_H84,6
MEM_MB_DQS_L84,6

VCC3

SMB_MEMCLK6
SMB_MEMDATA6

MEM_MB_BANK24,6,8
MEM_MB_BANK14,6,8
MEM_MB_BANK04,6,8

MEM_MB_ADD[15..0]4,6,8

MEM_MB_DM8

MEM_MB_DM7

MEM_MB_DM6

MEM_MB_DM5

MEM_MB_DM4

MEM_MB_DM3

MEM_MB_DM2

MEM_MB_DM1

MEM_MB_DM0

MEM_MB_DQS_H8
MEM_MB_DQS_L8
MEM_MB_DQS_H7
MEM_MB_DQS_L7
MEM_MB_DQS_H6
MEM_MB_DQS_L6
MEM_MB_DQS_H5
MEM_MB_DQS_L5
MEM_MB_DQS_H4
MEM_MB_DQS_L4
MEM_MB_DQS_H3
MEM_MB_DQS_L3
MEM_MB_DQS_H2
MEM_MB_DQS_L2
MEM_MB_DQS_H1
MEM_MB_DQS_L1
MEM_MB_DQS_H0
MEM_MB_DQS_L0

SMB_MEMCLK
SMB_MEMDATA

MEM_MB_CHECK[7..0]4,6

MEM_MB1_CLK_H04,8
MEM_MB1_CLK_L04,8
MEM_MB1_CLK_H14,8
MEM_MB1_CLK_L14,8
MEM_MB1_CLK_H24,8
MEM_MB1_CLK_L24,8

MEM_MB_CKE14,8
MEM_MB_RAS_L4,6,8

MEM_MB_CAS_L4,6,8
MEM_MB1_CS_L04,8

MEM_MB1_CS_L14,8

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_CHECK7
MEM_MB_CHECK6
MEM_MB_CHECK5
MEM_MB_CHECK4
MEM_MB_CHECK3
MEM_MB_CHECK2
MEM_MB_CHECK1
MEM_MB_CHECK0

MEM_MB1_CLK_H0
MEM_MB1_CLK_L0
MEM_MB1_CLK_H1
MEM_MB1_CLK_L1
MEM_MB1_CLK_H2
MEM_MB1_CLK_L2

MEM_MB_CKE1

MEM_MB_RAS_L
MEM_MB_CAS_L

MEM_MB1_CS_L0
MEM_MB1_CS_L1

164
165
232
233
223
224
211
212
202
203
155
156
146
147
134
135
125
126

46

45
114
113
105
104

93

92

84

83

37

36

28

27

16

15

7
6

101
240
239
120
119

54
190

71
173

174
196
176

57

70
177
179

58
180

60

61
182

63
183
188

168
167
162
161

49

48

43

42
185

186
137
138
220
221

18

52
171
192

74
193

76

DQS17_H
DQS17_L
DQS16_H
DQS16_L
DQS15_H
DQS15_L
DQS14_H
DQS14_L
DQS13_H
DQS13_L
DQS12_H
DQS12_L
DQS11_H
DQS11_L
DQS10_H
DQS10_L
DQS9_H
DQS9_L
DQS8_H
DQS8_L
DQS7_H
DQS7_L
DQS6_H
DQS6_L
DQS5_H
DQS5_L
DQS4_H
DQS4_L
DQS3_H
DQS3_L
DQS2_H
DQS2_L
DQS1_H
DQS1_L
DQS0_H
DQS0_L

SA2
SA1
SA0
SCL
SDA
BA2
BA1
BA0

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0

CK0_H
CK0_L
CK1_H
CK1_L
CK2_H
CK2_L

RESET_L
CKE0

CKE1
RAS_L
CAS_L

S0_L
S1_L

2

VDD4

DIMM 2

ADDR=1010011B

5

4

3

2

1

MEM_MA_ADD[15..0]4,6,7

MEM_MA_BANK24,6,7

D D

MEM_MA_BANK04,6,7

MEM_MB0_CS_L04,6

MEM_MA_RAS_L4,6,7

MEM_MB_WE_L4,6,7

MEM_MB_RAS_L4,6,7

MEM_MA_BANK14,6,7

MEM_MA1_CS_L14,7

MEM_MB0_CS_L14,6
MEM_MB1_CS_L14,7

MEM_MA1_CS_L04,7
MEM_MA1_ODT04,7

C C

MEM_MA_ADD14
MEM_MA_BANK2
MEM_MB_ADD12
MEM_MB_ADD9
MEM_MA_ADD12
MEM_MA_ADD11
MEM_MA_ADD9
MEM_MA_ADD7
MEM_MB_ADD6
MEM_MA_ADD6
MEM_MA_ADD5
MEM_MB_ADD5
MEM_MB_ADD3
MEM_MA_ADD2
MEM_MB_ADD1
MEM_MB_ADD2

MEM_MA_BANK0
MEM_MB0_CS_L0
MEM_MA_RAS_L
MEM_MB_WE_L

MEM_MA_ADD0
MEM_MB_RAS_L
MEM_MA_ADD10
MEM_MA_BANK1

MEM_MA1_CS_L1
MEM_MB_ADD13
MEM_MB0_CS_L1
MEM_MB1_CS_L1

MEM_MA1_CS_L0
MEM_MA1_ODT0

RN15 8P4R-47R0402

1

2

3

4

5

6

7

RN16 8P4R-47R0402

RN18 8P4R-47R0402

RN20 8P4R-47R0402

RN24 8P4R-47R0402

RN22 8P4R-47R0402

RN28 8P4R-47R0402

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

R108 47R0402
R113 47R0402

MEM_MA0_CLK_H24,6

MEM_MA0_CLK_L24,6

MEM_MA0_CLK_H14,6

MEM_MA0_CLK_L14,6

MEM_MA0_CLK_H04,6

MEM_MA0_CLK_L04,6

MEM_MB0_CLK_H24,6

MEM_MB0_CLK_L24,6

MEM_MB0_CLK_H14,6

MEM_MB0_CLK_L14,6

MEM_MB0_CLK_H04,6

MEM_MB0_CLK_L04,6

MEM_MA0_CLK_H2

MEM_MA0_CLK_L2

MEM_MA0_CLK_H1

MEM_MA0_CLK_L1

MEM_MA0_CLK_H0

MEM_MA0_CLK_L0

MEM_MB0_CLK_H2

MEM_MB0_CLK_L2

MEM_MB0_CLK_H1

MEM_MB0_CLK_L1

MEM_MB0_CLK_H0

MEM_MB0_CLK_L0

C185
C1.5P50N0402

C72
C1.5P50N0402

C124

C1.5P50N0402

C176
C1.5P50N0402

C71
C1.5P50N0402

C122
C1.5P50N0402

C0.1U16X

VTT_DDR

VTT_DDR

C199

C0.1U16X

MEM_MA_ADD15

C565 C2 2 P50N0402/B

MEM_MA_ADD14

C566 C2 2 P50N0402/B

MEM_MA_ADD13

C590 C2 2 P50N0402/B

MEM_MA_ADD12

C568 C2 2 P50N0402/B

MEM_MA_ADD11

C573 C2 2 P50N0402/B

MEM_MA_ADD10

C587 C2 2 P50N0402/B

MEM_MA_ADD9

C572 C2 2 P50N0402/B

MEM_MA_ADD8

C577 C2 2 P50N0402/B

MEM_MA_ADD7

C576 C2 2 P50N0402/B

MEM_MA_ADD6

C578 C2 2 P50N0402/B

MEM_MA_ADD5

C580 C2 2 P50N0402/B

MEM_MA_ADD4

C583 C2 2 P50N0402/B

MEM_MA_ADD3

C579 C2 2 P50N0402/B

MEM_MA_ADD2

C585 C2 2 P50N0402/B

MEM_MA_ADD1

C581 C2 2 P50N0402/B

MEM_MA_ADD0

C588 C2 2 P50N0402/B

MEM_MA_CAS_L

C589 C2 2 P50N0402/B

MEM_MA_WE_L

C586 C2 2 P50N0402/B

MEM_MA_RAS_L

C584 C2 2 P50N0402/B

MEM_MA_BANK2

C569 C2 2 P50N0402/B

MEM_MA_BANK1

C591 C2 2 P50N0402/B

MEM_MA_BANK0

C582 C2 2 P50N0402/B

Decoupling Between Processor and DIMMs

Layout: Spread out on VTT pour

C193

C173

C0.1U16X

C156

C0.1U16X

C181

C0.1U16X

C190

C0.1U16X

C111

C0.1U16X

C150

C0.1U16X

C130

C0.1U16X

C0.1U16X

MEM_MB_ADD15
MEM_MB_ADD14
MEM_MB_ADD13
MEM_MB_ADD12
MEM_MB_ADD11
MEM_MB_ADD10
MEM_MB_ADD9
MEM_MB_ADD8
MEM_MB_ADD7
MEM_MB_ADD6
MEM_MB_ADD5
MEM_MB_ADD4
MEM_MB_ADD3
MEM_MB_ADD2
MEM_MB_ADD1
MEM_MB_ADD0

MEM_MB_CAS_L
MEM_MB_WE_L
MEM_MB_RAS_L

MEM_MB_BANK2
MEM_MB_BANK1
MEM_MB_BANK0

C137

C202

C0.1U16X

C109 C22 P 50N0402
C110 C22 P 50N0402
C171 C22 P 50N0402
C116 C22 P 50N0402
C118 C22 P 50N0402
C161 C22 P 50N0402
C119 C22 P 50N0402
C132 C22 P 50N0402
C128 C22 P 50N0402
C133 C22 P 50N0402
C141 C22 P 50N0402
C148 C22 P 50N0402
C140 C22 P 50N0402
C152 C22 P 50N0402
C145 C22 P 50N0402
C162 C22 P 50N0402

C167 C22 P 50N0402
C158 C22 P 50N0402
C151 C22 P 50N0402

C115 C22 P 50N0402
C172 C22 P 50N0402
C147 C22 P 50N0402

C159

C0.1U16X

C0.1U16X

C95

C121

C0.1U16X

VCC_DDRVCC_DDR

C0.1U16X

C125

C112

C0.1U16X

VCC_DDR

MEM_MB_ADD[15..0]4,6,7

MEM_MA_CKE1

RN14 8P4R-47R0402

MEM_MA_CKE14,7

MEM_MB_BANK24,6,7

B B

MEM_MB_BANK14,6,7
MEM_MB_BANK04,6,7

MEM_MA_WE_L4,6,7

MEM_MB_CAS_L4,6,7
MEM_MA0_CS_L04,6
MEM_MA0_CS_L14,6

MEM_MB_CKE14,7

MEM_MB_CKE04,6

MEM_MA_CKE04,6

MEM_MA_CAS_L4,6,7
MEM_MA0_ODT04,6

MEM_MB0_ODT04,6

MEM_MB1_CS_L04,7

MEM_MB1_ODT04,7

MEM_MB_ADD14
MEM_MB_BANK2
MEM_MA_ADD15
MEM_MB_ADD11
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MA_ADD8
MEM_MA_ADD4
MEM_MA_ADD3
MEM_MA_ADD1
MEM_MB_ADD4
MEM_MB_ADD0
MEM_MB_BANK1
MEM_MB_ADD10
MEM_MB_BANK0

MEM_MA_WE_L
MEM_MB_CAS_L
MEM_MA0_CS_L0
MEM_MA0_CS_L1

MEM_MB_CKE1
MEM_MB_CKE0
MEM_MA_CKE0
MEM_MB_ADD15

MEM_MA_CAS_L

MEM_MA0_ODT0
MEM_MA_ADD13
MEM_MB0_ODT0

MEM_MB1_CS_L0
MEM_MB1_ODT0

1
3
5
7

RN17 8P4R-47R0402

1
3
5
7

RN19 8P4R-47R0402

1
3
5
7

RN21 8P4R-47R0402

1
3
5
7

RN26 8P4R-47R0402

1
3
5
7

RN13 8P4R-47R0402

1
3
5
7

RN27 8P4R-47R0402

1
3
5
7

R105 47R0402
R117 47R0402

VTT_DDR

2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8

2
4
6
8

2
4
6
8

2
4
6
8

MEM_MA1_CLK_H24,7

MEM_MA1_CLK_L24,7

MEM_MA1_CLK_H14,7

MEM_MA1_CLK_L14,7

MEM_MA1_CLK_H04,7

MEM_MA1_CLK_L04,7

MEM_MB1_CLK_H24,7

MEM_MB1_CLK_L24,7

MEM_MB1_CLK_H14,7

MEM_MB1_CLK_L14,7

A A

MEM_MB1_CLK_H04,7

MEM_MB1_CLK_L04,7

5

4

MEM_MA1_CLK_H2

MEM_MA1_CLK_L2

MEM_MA1_CLK_H1

MEM_MA1_CLK_L1

MEM_MA1_CLK_H0

MEM_MA1_CLK_L0

MEM_MB1_CLK_H2

MEM_MB1_CLK_L2

MEM_MB1_CLK_H1

MEM_MB1_CLK_L1

MEM_MB1_CLK_H0

MEM_MB1_CLK_L0

C186
C1.5P50N0402

C61
C1.5P50N0402

C129
C1.5P50N0402

C180
C1.5P50N0402

C67
C1.5P50N0402

C127
C1.5P50N0402

3

VTT_DDR

C103

C0.1U16X

C105

C0.1U16X

C28

C0.1U16X

C86

C0.1U16X

C29

C0.1U16X

C77

C0.1U16X

C241

C0.1U16X

2

C250

C0.1U16X

VTT_DDR

VCC_DDR

C231

C0.1U16X

C0.1U16X

C223
X_C10P50N0402

C242
X_C10P50N0402

C222

C108

C0.1U16X

C0.1U16X

For EMI

C227
X_C10P50N0402

C58
X_C10P50N0402

Title

Document Number

MICRO-STAR I NT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsi en , Taiwan
http://www.msi.com.tw

C123

C262

C254

C0.1U16X

C0.1U16X

C256
X_C10P50N0402

C200
X_C10P50N0402

C0.1U16X

C26
X_C10P50N0402

Micro Star Restricted Secret

DDR Terminatior

MS-7225H1

C30

C131

C0.1U16X

C22
X_C10P50N0402

Last Revision Date:

Monday, September 12, 2005

Sheet

833

1

of

Rev

0A

5

4

3

2

1

U13F

HT_CADO UT_H[15..0]3

D D

HT_CADOUT_L[15..0]3

C C

HT_CADOUT_H[15..0]

HT_CADOUT_L[15..0]

HT_CLKOUT_H03

HT_CLKOUT_L03

HT_CLKOUT_H13

HT_CLKOUT_L13

HT_CTLOUT_H03
HT_CTLOUT_L03

HT_CADOUT_H0
HT_CADOUT_H1
HT_CADOUT_H2
HT_CADOUT_H3
HT_CADOUT_H4
HT_CADOUT_H5
HT_CADOUT_H6
HT_CADOUT_H7
HT_CADOUT_H8
HT_CADOUT_H9
HT_CADOUT_H10
HT_CADOUT_H11
HT_CADOUT_H12
HT_CADOUT_H13
HT_CADOUT_H14
HT_CADOUT_H15

HT_CADOUT_L0
HT_CADOUT_L1
HT_CADOUT_L2
HT_CADOUT_L3
HT_CADOUT_L4
HT_CADOUT_L5
HT_CADOUT_L6
HT_CADOUT_L7
HT_CADOUT_L8
HT_CADOUT_L9
HT_CADOUT_L10
HT_CADOUT_L11
HT_CADOUT_L12
HT_CADOUT_L13
HT_CADOUT_L14
HT_CADOUT_L15

HT_CTLOUT_H0
HT_CTLOUT_L0

Y23
W24
V24
U22
R24
P24
P22
N22
Y21
V21
W21

T21
R18
P16
N20
M17

Y22
W23
V23
U21
R23
P23
P21
N21
Y20
W20
W22
U20
R19
P17
N19
N18

T23

T22
R21
R20

M23
M22

HT_CPU_RXD0_P
HT_CPU_RXD1_P
HT_CPU_RXD2_P
HT_CPU_RXD3_P
HT_CPU_RXD4_P
HT_CPU_RXD5_P
HT_CPU_RXD6_P
HT_CPU_RXD7_P
HT_CPU_RXD8_P
HT_CPU_RXD9_P
HT_CPU_RXD10_P
HT_CPU_RXD11_P
HT_CPU_RXD12_P
HT_CPU_RXD13_P
HT_CPU_RXD14_P
HT_CPU_RXD15_P

HT_CPU_RXD0_N
HT_CPU_RXD1_N
HT_CPU_RXD2_N
HT_CPU_RXD3_N
HT_CPU_RXD4_N
HT_CPU_RXD5_N
HT_CPU_RXD6_N
HT_CPU_RXD7_N
HT_CPU_RXD8_N
HT_CPU_RXD9_N
HT_CPU_RXD10_N
HT_CPU_RXD11_N
HT_CPU_RXD12_N
HT_CPU_RXD13_N
HT_CPU_RXD14_N
HT_CPU_RXD15_N

HT_CPU_RX_CLK0_P
HT_CPU_RX_CLK0_N
HT_CPU_RX_CLK1_P
HT_CPU_RX_CLK1_N

HT_CPU_RXCTL_P
HT_CPU_RXCTL_N

VCC1_2HT

W19

HT_CPU_CAL_1P2V

Y19

?

N16

T13

HT_CPU_CAL_GND

+1.2V_PLLHTCPU

+1.2V_PLLHTMCP

?

B B

1P2VPLL_PWR10,11

R147 150R1%

FB19 30L500m_200/B

PLACE ON BACK SIDE

R150 150R1%

1P2VPLL_FILT1P2VPLL_PWR

C598

C1U10Y/B

C600

C0.1U25Y/B

C51

SEC 1 OF 6

HT_CPU_TXD0_P
HT_CPU_TXD1_P
HT_CPU_TXD2_P
HT_CPU_TXD3_P
HT_CPU_TXD4_P
HT_CPU_TXD5_P
HT_CPU_TXD6_P
HT_CPU_TXD7_P
HT_CPU_TXD8_P

HT_CPU_TXD9_P
HT_CPU_TXD10_P
HT_CPU_TXD11_P
HT_CPU_TXD12_P
HT_CPU_TXD13_P
HT_CPU_TXD14_P
HT_CPU_TXD15_P

HT_CPU_TXD0_N
HT_CPU_TXD1_N
HT_CPU_TXD2_N
HT_CPU_TXD3_N
HT_CPU_TXD4_N
HT_CPU_TXD5_N
HT_CPU_TXD6_N
HT_CPU_TXD7_N
HT_CPU_TXD8_N
HT_CPU_TXD9_N

HT_CPU_TXD10_N
HT_CPU_TXD11_N
HT_CPU_TXD12_N
HT_CPU_TXD13_N
HT_CPU_TXD14_N
HT_CPU_TXD15_N

HT_CPU_TX_CLK0_P
HT_CPU_TX_CLK0_N
HT_CPU_TX_CLK1_P
HT_CPU_TX_CLK1_N

HT_CPU_TXCTL_P
HT_CPU_TXCTL_N

CLKOUT_PRI_200MHZ_P

CLKOUT_PRI_200MHZ_N
CLKOUT_SEC_200MHZ_P
CLKOUT_SEC_200MHZ_N

HT_CPU_REQ*

HT_CPU_STOP*

HT_CPU_RESET*

HT_CPU_PWRGD

+2.5V_PLLHTCPU

VCC2_5

HT_CADIN_H0

C23

HT_CADIN_H1

D23

HT_CADIN_H2

E22

HT_CADIN_H3

F23

HT_CADIN_H4

H22

HT_CADIN_H5

J21

HT_CADIN_H6

K21

HT_CADIN_H7

K23

HT_CADIN_H8

D21

HT_CADIN_H9

F19

HT_CADIN_H10

F21

HT_CADIN_H11

G20

HT_CADIN_H12

J19

HT_CADIN_H13

L17

HT_CADIN_H14

L20

HT_CADIN_H15

L18

HT_CADIN_L0

C24

HT_CADIN_L1

D24

HT_CADIN_L2

E23

HT_CADIN_L3

F24

HT_CADIN_L4

H23

HT_CADIN_L5

J22

HT_CADIN_L6

K22

HT_CADIN_L7

K24

HT_CADIN_L8

D22

HT_CADIN_L9

E20

HT_CADIN_L10

E21

HT_CADIN_L11

G19

HT_CADIN_L12

J18

HT_CADIN_L13

K17

HT_CADIN_L14

K19

HT_CADIN_L15

L19

G23
G24
G22
G21

L23
L24

R143 47.5R1%

B24

R142 47.5R1%

B23
A22
B21

F18
G18
D20
E19

L16

C244

C4.7U10Y0805

HT_CLKIN_H0
HT_CLKIN_L0
HT_CLKIN_H1
HT_CLKIN_L1

HT_CTLIN_H0
HT_CTLIN_L0

2P5V_PLL

C595
C0.1U25Y/B

HT_CADIN_H[15..0]

HT_CADIN_L[15..0]

HT_CLKIN_H0 3
HT_CLKIN_L0 3
HT_CLKIN_H1 3
HT_CLKIN_L1 3

HT_CTLIN_H0 3
HT_CTLIN_L0 3

CPU_CLK 3

R139
_261R1%-LF

CPU_CLK# 3

HT_STOP#
LDT_RST
CPU_PWRGD

HT_CADIN_H[15..0] 3

HT_CADIN_L[15..0] 3

HT_STOP# 3

FB2030L500m_200/B

C597

C1U10Y/B

LDT_RST 3
CPU_PWRGD 3

C599

C0.1U25Y/B

2P5V_PLL 10

HTMCP_UP[7 ..0 ]12

HTMCP_UP#[7..0]12

HTMCP_UP[7..0]

HTMCP_UP#[7..0]

HTMCP_UPCLK012

HTMCP_UPCLK0#12

HTMCP_UPCNTL12

HTMCP_UPCNTL#12

HTMCP_REQ#12

HTMCP_STOP#12

HTMCP_RST#12

HTMCP_PWRGD12

MCPOUT_25MHZ12

MCPOUT_200MHZ12

MCPOUT_200MHZ#12

HTMCP_UP0
HTMCP_UP1
HTMCP_UP2
HTMCP_UP3
HTMCP_UP4
HTMCP_UP5
HTMCP_UP6
HTMCP_UP7

HTMCP_UPCLK0
HTMCP_UPCLK0#

HTMCP_UPCNTL
HTMCP_UPCNTL#

HTMCP_REQ#
HTMCP_STOP#
HTMCP_RST#
HTMCP_PWRGD

MCPOUT_25MHZ

MCPOUT_200MHZ
MCPOUT_200MHZ#

HTMCP_UP#0
HTMCP_UP#1
HTMCP_UP#2
HTMCP_UP#3
HTMCP_UP#4
HTMCP_UP#5
HTMCP_UP#6
HTMCP_UP#7

AD10
AD11
AC12
AC13

AA11

AC10
AC11
AB12
AB13

AD14
AC14

AD6
AC7
AA8
AA9

AA6

W7

Y10

V11
W12

AC6
AB7
AB8
AB9

AA7

W9

W10

Y12
W11
V13

AD9
AC9
U10

T10

AB5
AA5
AC5
AD5

AC4

W5

Y8
V9

Y6
Y7

Y5

U13A

?

HT_MCP_RXD0_P
HT_MCP_RXD1_P
HT_MCP_RXD2_P
HT_MCP_RXD3_P
HT_MCP_RXD4_P
HT_MCP_RXD5_P
HT_MCP_RXD6_P
HT_MCP_RXD7_P
HT_MCP_RXD8_P
HT_MCP_RXD9_P
HT_MCP_RXD10_P
HT_MCP_RXD11_P
HT_MCP_RXD12_P
HT_MCP_RXD13_P
HT_MCP_RXD14_P
HT_MCP_RXD15_P

HT_MCP_RXD0_N
HT_MCP_RXD1_N
HT_MCP_RXD2_N
HT_MCP_RXD3_N
HT_MCP_RXD4_N
HT_MCP_RXD5_N
HT_MCP_RXD6_N
HT_MCP_RXD7_N
HT_MCP_RXD8_N
HT_MCP_RXD9_N
HT_MCP_RXD10_N
HT_MCP_RXD11_N
HT_MCP_RXD12_N
HT_MCP_RXD13_N
HT_MCP_RXD14_N
HT_MCP_RXD15_N

HT_MCP_RX_CLK0_P
HT_MCP_RX_CLK0_N
HT_MCP_RX_CLK1_P
HT_MCP_RX_CLK1_N

HT_MCP_RXCTL_P
HT_MCP_RXCTL_N

HT_MCP_REQ*
HT_MCP_STOP*
HT_MCP_RESET*
HT_MCP_PWRGD

CLKIN_25MHZ

CLKIN_200MHZ_P
CLKIN_200MHZ_N

?

C51

SEC 2 OF 6

SCLKIN_MCLKOUT_200MHZ_P

SCLKIN_MCLKOUT_200MHZ_N

HT_MCP_TXD0_P
HT_MCP_TXD1_P
HT_MCP_TXD2_P
HT_MCP_TXD3_P
HT_MCP_TXD4_P
HT_MCP_TXD5_P
HT_MCP_TXD6_P
HT_MCP_TXD7_P
HT_MCP_TXD8_P

HT_MCP_TXD9_P
HT_MCP_TXD10_P
HT_MCP_TXD11_P
HT_MCP_TXD12_P
HT_MCP_TXD13_P
HT_MCP_TXD14_P
HT_MCP_TXD15_P

HT_MCP_TXD0_N

HT_MCP_TXD1_N

HT_MCP_TXD2_N

HT_MCP_TXD3_N

HT_MCP_TXD4_N

HT_MCP_TXD5_N

HT_MCP_TXD6_N

HT_MCP_TXD7_N

HT_MCP_TXD8_N

HT_MCP_TXD9_N

HT_MCP_TXD10_N
HT_MCP_TXD11_N
HT_MCP_TXD12_N
HT_MCP_TXD13_N
HT_MCP_TXD14_N
HT_MCP_TXD15_N

HT_MCP_TX_CLK0_P

HT_MCP_TX_CLK0_N

HT_MCP_TX_CLK1_P

HT_MCP_TX_CLK1_N

HT_MCP_TXCTL_P
HT_MCP_TXCTL_N

CLKOUT_CTERM

HT_MCP_CAL_1P2V
HT_MCP_CAL_GND

HTMCP_DWN0

AC24

HTMCP_DWN1

AD23

HTMCP_DWN2

AC22

HTMCP_DWN3

AC20

HTMCP_DWN4

AB18

HTMCP_DWN5

AA17

HTMCP_DWN6

AB16

HTMCP_DWN7

AC16
AB21
AB20
AB19
W18
W15
AA15
Y14
W13

HTMCP_DWN#0

AC23

HTMCP_DWN#1

AD22

HTMCP_DWN#2

AC21

HTMCP_DWN#3

AD20

HTMCP_DWN#4

AC18

HTMCP_DWN#5

AB17

HTMCP_DWN#6

AB15

HTMCP_DWN#7

AD16
AB22
AA20
AA19
V17
V15
Y15
W14
Y13

AC19
AD19
Y17
W17

AC15
AD15

B22
A20

B20

AB23
AB24

HTMCP_DWN[7..0]

HTMCP_DWNCLK0
HTMCP_DWNCLK0#

HTMCP_DWNCNTL
HTMCP_DWNCNTL#

R155 590R1%

2.37 Ohm

R148 150R1%

R149 150R1%

HTMCP_DWN#[7..0]

VCC1_2

HTMCP_DWN[7..0] 12

HTMCP_DWN#[7..0] 12

HTMCP_DWNCLK0 12
HTMCP_DWNCLK0# 12

HTMCP_DWNCNTL 12
HTMCP_DWNCNTL# 12

A A

5

4

PLACE ON BACK SIDE

Micro Star Restricted Secret

Title

Document Number

3

2

C51PV-1/ HT CPU & MCP

MICRO-STAR INT'L CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7225H1

1

Last Revision Date:

Monday, September 12, 2005

Sheet

Rev

0A

933

of