MSI MS-7196 Schematics
1
COVER SHEET
BLOCK DIAGRAM
CLOCK MAP
POWER MAP
1
2
3
4
MS-7196 (MS-6404)
Version 0B
CPU:
Intel Prescott ( L2=2MB ) - 3.4G & Above
GPIO & JUMPER SETTING
Intel LGA775-CPU
VRM10.1 Intersil 6566 3Phase
Intel Lakeport -GMCH
DDR II DIMM 1and DIMM2 1 & 2
PCI EXPRESS X16 SLOT
5
6-8
9
10-13
14-16
17
Intel Cendar Mill (65nm) - 3.73G & Above
Intel Smithfield (90nm Dual core)
System Chipset:
Intel Lakeport - GMCH (North Bridge)
Intel ICH7 (South Bridge)
On Board Chipset:
VGA CONNECTOR
Clock Generator - ICS954119
18
19
BIOS -- FWH FLASH 4Mb
HD AUDIO CODEC(ALC880/882)
ICH7
A A
PCI Slot 1 & mini PCI
PCI_MS1 & FWH
20-22
23
24
LPC Super I/O -- W83627EHF
LAN - Realtek 8110SB
1394 -- VIA VT-6307
Clock Generator - ICS954119
LAN - Realtek 8110SB
25
Main Memory:
VIA VT-6307
26
DDR II * 2 (Max 2GB)
USB CONNECTORS
HD AUDIO CODEC(ALC 880)
SIO-W83627THF & KB/MS
ATX,F_ PANEL
27
28
29
30
Expansion Slots:
PCI Express X16 SLOT * 1
PCI 2.3 SLOT * 1
mini PCI SLOT * 1
IDE, SATA & FAN CONTROL
31
Intersil PWM:
MS7 ACPI Controller
Front Audio
32
33
Controller:
ISL6566CR_QFN40
Auto BOM manual
PWOK MAP
History
34
35
36
MSI
Title
Size Document Number Rev
1
Date: Sheet
MICRO-STAR INt'L CO., LTD.
COVER SHEET
MS-7196
of
136Monday, September 05, 2005
0B
VRM_GD
1
VTT_PWG
PCIRST#2
VRM 10.1
Intersil 6565
3-Phase PWM
PCI
EXPRESS
X16
Connector
Analog
Intel LGA775 Processor
FSB
H_PWRGD
H_CPURST#
Lakeport
GMCH
DDRII
266/333
MHz
Block Diagram
PWR_GD
2 DDR II
DIMM
Modules
PCIRST#1
MS7
VID_GD
RSMRST#
HD_RST#
Video
HD_RST#
Out
IDE Primary
UltraDMA
33/66/100
VRM_GD
DMI
PLRST#
PWR_GD
SLP_S4#
PCIRST_ICH6#
PCI Slot 1
MINI PCI Slot 1
SERIAL ATA1
A A
SERIAL ATA2
USB2.0
USB Port0~ 7
USB
RSMRST#
PWRBTN#
LPC Bus
SLP_S3#
PSON#
PLTRST#
ICH7
PCI
PWR_OK
ATX1
PCIRST#2
PCIRST#1
ALC880
HD Audio
LAN
Realtek 8110S
1394
VIA VT-6307
PCI
JFP1
WINBOND
83627EHF
CLKGEN
LM90
FWH
FP_RST#SW_ON#
Keyboard
Mouse
PLTRST#
1
Serial
MSI
Title
Size Document Number R e v
Date: Sheet
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
MS-7196
236Tuesday, September 06, 2005
of
0B
5
4
3
2
1
HCLK
LGA775
CLOCK MAP
D D
ICS954101 1/2
Clock
Generator
C C
SIO_PCLK
MCHCLK
DOTCLK
96MHz
ICHCLK
SATACLK
USB48MHz
ICH14.318MHz
SIO48MHz
33MHz
Lakeport
MCH
ICH7R or DH
W83627EHF
LPC IO
PCI_E1PCI_E1_100MHz
PCI-Express X 16
ICS954119 2/2
Clock
Generator
1394_PCLK
33MHz
B B
VT6307 or 6308
1394
PCI_CLK2
LAN - 8110SB
33MHz
SIO_PCLK
33MHz
FWH
FWH_PCLK
33MHz
A A
5
PCICLK 0
PCICLK 1
33MHz
33MHz
PCI1
MICRO-STAR INt'L CO., LTD.
MSI
MINI
PCI
4
3
2
Title
Size Document Number Re v
Date: Sheet
CLOCK MAP
MS-7196
1
336Tuesday, Se pt em be r 0 6, 2005
0B
of
5
POWER MAP
4
3
2
1
D D
C C
B B
ATX POWER
+12V +5V +3.3V +5VSB
MSI
ACPI
Controller
9.9*1.8/5/0.8 = 4.45A
5VDIMM
MS - 7
25.8*1.5/3/0.8 = 15.8A
VCC3
3.775A
VCC3_SB VTT_DDR
MSI
V_1P5_CORE
MSI
V_1P05_CORE
MSI
V_FSB_VTT
MSI
LINEAR
W83310DS
MS6 +
MS6 +
LINEAR
8.7+1.2 = 9.9A
VCC_DDR
25.38A
6.2A
6.2A
PCI_E1
0.375A
5.5A
3A
125A 5.3A
1.2A
LGA775VRM 10.1
Lakeport
4A
8.7A
17.87A
1.31A
1.31A
1.2A
MCH
13.8A + 1.5A
= 15.3A
4.7A
DDR2 X 2
1.2A
TBD (2.57A)
1.31A
ICH7
0.7A
14mA
0.9A
PCI1
VCC3_SB 0.375A
3.3V 7.6A
5V 5A
+12V 0.5A
-12V 0.1A
2.5V
Realtek
1.8V
8110SB
5VDUAL
A A
5
4A
4
4.0A
USB
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Docum e n t N u mb er Re v
3
2
Date: Sheet
POWER MAP
MS-7196
1
0B
of
436Tuesday, Sept ember 06, 2005
8
7
6
5
4
3
2
1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name or status
GPIO[0] BM_BUSY# AB18 I/O Vcc3p3 N Y 5 Input pull high VCC3
GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
GPIO[6] ATADET0 AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
GPIO[7] GPI7 AC18 I/O Vcc3p3 N Y 3.3 Input pull high VCC3
GPIO[8] SIO_PME# E21 I/O VccSus3p3 N Y
3.3 Input SIO_PME# pull high VCC3_SB
FWH
GPIO Pin# Power Tol Signal Name
FPGI[0] 6 Main 3.3 pull-down
FPGI[1] 5 Main 3.3 pull-down
FPGI[2] 4 Main 3.3 pull-down
FPGI[3] 3 Main 3.3 pull-down
FPGI[4] 30 Main 3.3 pull-down
PCI Config.
GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
DEVICE
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[13] CD_SMI# E19 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[14] LM86_ALERT# R4 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input pull high VCC3_SB
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
C C
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[24] Lan disable R3 I/O VccSus3p3 N N 3.3 No Change NC
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 NC
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[27] EL_STATE0 B21 I/O VccSus3p3 N N 3.3 0 EASTFORK LED0
GPIO[28] EL_STATE1 E23 I/O VccSus3p3 N N 3.3 0 EASTFORK LED1
GPIO[29] OC#2345 C3 I/O VccSus3p3 N N 3.3 Input OC#2345
GPIO[30] OC#67 A2 I/O VccSus3p3 N N 3.3 Input OC#67
GPIO[31] OC#67 B3 I/O VccSus3p3 N N 3.3 Input OC#67
GPIO[32] CLEAR_CMOS# AG18 I/O Vcc3p3 N N 3.3 1 CLEAR_CMOS#, ONLY pull high VCC3
GPIO[33] BIOS_WP# AC19 I/O Vcc3p3 N N 3.3 1 BIOS_WP#
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input pull high VCC3
B B
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input pull high VCC3
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A GNT4#
SIGNAL DEVICE
PCIRST#1
PCIRST#2
PLTRST#
PCIRST_ICH6#
HD_RST#
H_CPURST#
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
GPI[15..0] can configured to cause a SMI# or SCI.
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
SMBCLK, SMBDATA DDR2, PCIEX16, CLKGEN, ICH7, PCI SLOT, LM90, MS-7
DDRII DIMM Config.
DIMM 1
SIO W83627THF
PIN NAME NOTES
GPIO33
GPIO45
A A
GPIO35
GPIO50
71 OUTPUT ODGPIO43
89
69
86
110
USAGE
unused
unused
unused
unused
unused
Input/OutputPIN#
OUTPUT OD
OUTPUT OD
OUTPUT OD
OUTPUT
JUMPER SETTING
JBAT1
Note: FWH GPs should only be used for static options,
do not put dynamic nets on these
MCP1 INT Pin
PCI1
PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#DMINIPCI AD20 PCI_CLK1
PIRQ#A
PIRQ#B
PIRQ#C
LAN PCI_CLK2AD18PIRQ#C
1394, PCISLOT1, MINIPCI, LAN
PCIE X16,
MCH, FWH, SIO
MS-7
IDE1
CPU
A0H
A4H
(1-2)NORMAL
REQ#/GNT#
PREQ#3PIRQ#E1394
PGNT#3
PREQ#0
PGNT#0
PREQ#4
PGNT#4
PREQ#2
PGNT#2
LAN
CLOCKDEVICE ADDRESS
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1
MCLK_A2/MCLK_A#2
MCLK_B0/MCLK_B#0
MCLK_B1/MCLK_B#1DIMM 2
MCLK_B2/MCLK_B#2
(2-3)CLEAR
IDSEL
AD19
AD16
CLOCK
1394_PCLK
PCI_CLK0
Title
Size Document Number Re v
8
7
6
5
4
3
Date: Sheet
2
GPIO MAP
MS-7196
0B
of
536Tuesday, September 06, 2005
1
MICRO-STAR INt'L CO., LTD.
MSI
8
7
6
5
4
3
2
1
AN4
AN3
AN6
AN5
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D13#
D12#D8D11#
D10#
D9#
B12
B10
A11
C11
H_D#12
H_D#13
H_D#9
H_D#11
H_D#10
R263 X_1KR-1
C237
X_C10U16Y1206
<VOLTAGE>
TP18
AM5
AM7
AJ3
AK3
RSVD
ITP_CLK1
ITP_CLK0
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A10
H_D#7
H_D#8
H_D#4
H_D#5
H_D#6
H_D#3
VID5
VID4
AL4
AK4
VID6#
VID5#
VID4#
VID_SELECT
GTLREF_SEL
CS_GTLREF
LINT0/INTR
H_D#1
H_D#2
CPU SIGNAL BLOCK
D D
H_INIT#20
H_BPRI#10
H_A20M#20
R262 X_62R-1
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TESTHI13VTT_OUT_LEFT
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_DBI#[0..3]10
H_IERR#7
H_FERR#7,20
H_STPCLK#20
H_DBSY#10
H_DRDY#10
H_TRDY#10
C C
B B
A A
H_ADS#10
H_LOCK#10
H_BNR#10
H_HIT#10
H_HITM#10
H_DEFER#10
CPU_TMPA29
VTIN_GND29
TRMTRIP#20
H_PROCHOT#7
H_IGNNE#20
ICH_H_SMI#20
R253 _62R-1
VTT_OUT_RIGHT
H_FSBSEL07,12,19
H_FSBSEL17,12,19
H_FSBSEL27,12,19
H_PWRGD7,20
H_CPURST#7,10
H_D#[0..63]10
VCCP
R259
X_4.7KR-1
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
H_A#[3..31]10
U11A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
H_D#53
D53#
H_D#52
H_A#6
H_A#8
H_A#10
H_A#5
H_A#4
H_A#7
H_A#26
H_A#31
H_A#30
H_A#29
H_A#28
H_A#27
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
AB4
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
F21
G22
H_D#47
D22
H_D#46
E22
H_D#45
G21
H_D#44
H_D#43
E21
H_D#42
F20
H_D#41
E19
H_D#40
E18
H_D#39
A14
C14
C15
D17
D20
H_D#49
H_D#48
H_D#51
H_D#50
H_A#25
A26#
D39#
H_D#38
AC5
F18
A25#
D38#
H_A#24
AB5
F17
H_D#37
H_A#23
A24#
D37#
H_D#36
H_A#19
H_A#22
H_A#21
AA5
AD6
AA4
A23#
A22#
D36#
D35#
E16
G17
G18
H_D#34
H_D#35
H_A#20
H_A#18
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
D32#
E15
G16
H_D#31
H_D#33
H_D#32
H_A#14
H_A#17
H_A#16
H_A#15
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D31#
D30#
D29#
D28#
F15
F14
G15
G14
H_D#30
H_D#29
H_D#28
H_D#27
H_A#13
H_A#12
H_A#11
U6
D27#
D26#
D25#
D24#
F12
F11
E13
D13
G13
H_D#25
H_D#24
H_D#26
H_D#23
H_A#9
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
H_D#19
H_D#22
H_D#18
H_D#21
H_D#20
H_D#17
H_A#3
L5
H_D#16
D11
H_D#15
AC2
DBR#
D14#
C12
H_D#14
VID2
VID0
VID1
VID3
AL6
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
AN7
H1
GTLREF0
H2
GTLREF1
H29
E24
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
TESTHI12
P1
TESTHI11
H5
TESTHI10
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
FORCEPH
G6
RSVD
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
ADSTB1#
R6
ADSTB0#
C17
DSTBP3#
G19
DSTBP2#
E12
DSTBP1#
B9
DSTBP0#
A16
DSTBN3#
G20
DSTBN2#
G12
DSTBN1#
C8
DSTBN0#
L1
LINT1/NMI
K1
ZIF-SOCK775-15u-in
B4
H_D#0
FP_RST# 21,30
VID[0..5] 9
R223 _62R-1
TP_GTLREF_SEL
MCH_GTLREF_CPU
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
RSVD_AK6
RSVD_G6
H_RS#2
H_RS#1
H_RS#0
TP3
TP2
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
VCC_VRM_SENSE
VSS_VRM_SENSE
CPU_GTLREF0
CPU_GTLREF1
MCH_GTLREF_CPU 10
H_REQ#[0..4] 10
R257 _62R-1
R156 _62R-1
R256 _62R-1
R155 _62R-1
R231 X_62R-1
R258 X_62R-1
CK_H_CPU# 19
CK_H_CPU 19
H_RS#[0..2] 10
R439 _60.4R1%-1
R433 _60.4R1%-1
R438 _60.4R1%-1
R429 _60.4R1%-1
R435 _60.4R1%-1
R177 _60.4R1%-1
TP10
TP11
TP15
TP13
H_ADSTB#1 10
H_ADSTB#0 10
H_DSTBP#3 10
H_DSTBP#2 10
H_DSTBP#1 10
H_DSTBP#0 10
H_DSTBN#3 10
H_DSTBN#2 10
H_DSTBN#1 10
H_DSTBN#0 10
H_NMI 20
H_INTR 20
CPU_GTLREF0 7
CPU_GTLREF1 7
TP5
RN25 _8P4R-62R-LF
1 2
3 4
5 6
7 8
VTT_OUT_LEFT
V_FSB_VTT
VCC_VRM_SENSE 9
VSS_VRM_SENSE 9
VTT_OUT_RIGHT 7,8
VTT_OUT_LEFT 7
C261
X_C0.1U25Y
BSEL
1
02
FSB FREQUENCY
TABLE
267 MHZ (1067)000
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
RN24
_8P4R-680R-LF
VID3
1
VID1
VID2
VID4
VID0
VID5
H_BR#0 7,10
VTT_OUT_RIGHT
C245 C0.1U25Y
C241 C0.1U25Y R431 _49.9R1%-1
PLACE BPM TERM I N A T I O N NEAR CPU
2
3
4
5
6
7
8
R234 _680R-1
R235 _680R-1
RN45 _8P4R-62R-LF
1 2
3 4
5 6
7 8
R501 _62R-1
R502 _62R-1
R503 _49.9R1%-1
R504 _49.9R1%-1
R434 X_49.9R1%-1
R264 _49.9R1%-1
VTT_OUT_RIGHT
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_BPM#2
H_BPM#4
H_TMS
H_TDI
H_TDO
H_TRST#
H_TCK
THERM#21,29
THERM# H_PROCHOT#
Q40
X_N-MMBT3904_NL_SOT23
8
7
6
5
4
3
MSI
Title
Size Document Number Re v
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Signals
MS-7196
2
636Tuesda y, S ep te mb er 06, 2005
1
0B
of
8
VCCP
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
U11B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y23
Y24
Y25
Y26
Y27
Y28
Y29
W30
VCCP
D D
C C
AG22
VCC
VCC
W29
AG25
VCC
VCC
W28
AG26
VCC
VCC
W27
AG27
VCC
VCC
W26
AG28
W25
VCC
VCC
AG29
VCC
VCC
W24
7
AG30
VCC
W23
AG8
VCC
AG9
VCC
VCCU8VCCV8VCC
AH11
VCC
VCC
U30
AH12
VCC
VCC
U29
AH14
VCC
VCC
U28
AH15
VCC
VCC
U27
AH18
VCC
VCC
U26
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
U23
AH25
VCC
VCCT8VCC
AH26
VCC
VCC
T30
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
VCC
VCC
T27
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
AJ11
T23
VCC
AJ12
VCC
AJ14
VCC
AJ15
VCC
VCCN8VCCP8VCCR8VCC
6
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N23
N24
N25
N26
N27
N28
N29
N30
M24
M25
M26
M27
M28
M29
M30
VCC
VCC
AK25
VCC
M23
AK26
VCC
5
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
K25
K26
K27
K28
K29
K30
AM18
VCC
VCC
J21
AM19
VCC
VCC
J20
AM21
VCC
VCC
J19
AM22
VCC
VCC
J18
AM25
VCC
VCC
J15
AM26
VCC
VCC
J14
4
AM29
VCC
VCC
J13
AM30
VCC
VCC
J12
AM8
J11
VCC
VCC
AM9
VCC
VCC
J10
AN11
VCC
VCC
AN9
AN12
VCC
VCC
AN8
AN14
AN15
AN18
AN19
VCC
VCC
VCC
VCC
VTT_OUT_RIGHT
VTT_OUT_LEFT
VCC
VCC
VCC
VCC
AN25
AN26
AN29
AN30
AN21
AN22
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTTPWRGD
VTT_SEL
RSVD
HS11HS22HS33HS4
A23
B23
D23
C23
A25
VTT
A26
VTT
A27
VTT
A28
VTT
A29
VTT
A30
VTT
B25
VTT
B26
VTT
B27
VTT
B28
VTT
B29
VTT
B30
VTT
C25
VTT
C26
VTT
C27
VTT
C28
VTT
C29
VTT
C30
VTT
D25
VTT
D26
VTT
D27
VTT
D28
VTT
D29
VTT
D30
VTT
AM6
AA1
J1
F27
F29
ZIF-SOCK775-15u-in
4
3
H_VCCA
H_VSSA
H_VCCABB
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
R153
V_FSB_VTT
_0R-1
2
V_FSB_VTT
C127 C10U10Y0805
C175 C10U10Y0805
C132 C10U10Y0805
C123 C10U10Y0805
C509
C511
1
C0.1U25Y
C0.1U25Y
CAPS FOR FSB GE NERIC
VTT_OUT_LEFT
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
B B
VTT_OUT_LEFT
R432 _124R1%-LF
R427
_210R1%-1
R273 _124R1%-LF
R274
_210R1%-1
R430 10R
C545
C0.1U25Y
R426 10R
C265
C0.1U25Y
C544
C100P50N
C543
C100P50N
CPU_GTLREF0 6
V_FSB_VTT
L5 10U125m_0805-1
CPU_GTLREF1 6
PLACE AT CPU END OF ROUTE
H_IERR#
7
H_PROCHOT#
H_CPURST#
H_PWRGD
H_BR#0
H_FERR# 6,20
H_PROCHOT# 6
H_CPURST# 6,10
H_PWRGD 6,20
H_BR#0 6,10
H_IERR# 6
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
RN21
1
3
5
7
_8P4R-470R-LF
6
5
VTT_OUT_RIGHT6,8
VTT_OUT_LEFT6
A A
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
V_FSB_VTT
R190 _62R-1
R260 _100R-1
R277 _62R-1
R254 X_100R-1
R261 _62R-1
R440 _62R-1
H_FERR#
PLACE AT ICH END OF ROUTE
8
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
H_VCCABB
2
4
6
8
L7 10U125m_0805-1
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
4
VID_GD#9,32
H_FSBSEL1 6 ,12 ,19
H_FSBSEL0 6 ,12 ,19
H_FSBSEL2 6 ,12 ,19
VTT_OUT_RIGHT
VCC5_SB
R237
_1KR-1
C131
X_C1U10Y
R229 _680R-1
R236
_5.6KR-1
3
C134
C10U10Y0805
VTT_PWG
Q36
N-MMBT3904_NL_SOT23
C133
C10U10Y0805
C239
H_VCCA
H_VSSA
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
X_C1U10Y
MSI
Title
Size Document Number Re v
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Power
MS-7196
2
736Tuesda y, S ep te mb er 06, 2005
1
0B
of
8
7
6
5
4
3
2
1
V_FSB_VTT
D D
C C
B B
VTT_OUT_RIGHT6,7
TP7
D14
RSVDD1RSVD
VSS
AF10
AF13
E23
VSS
AF16
RSVD
VSS
AF17
VSS
AF20
TP16
TP9
TP17
F23
F6
RSVDE5RSVDE6RSVDE7RSVD
VSS
VSS
VSS
VSS
AF23
AF24
AF25
AF26
B13
RSVD
IMPSEL#
VSS
VSS
VSS
AF27
AF28
VSS
AF29
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
A12
A15
A18
A2
A21
A24
A6
A9
R436
_60.4R1%-1
U11C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE29
H_COMP6
H_COMP7
AE3
COMP6Y3COMP7
VSS
VSS
AE5
AE30
R437
_60.4R1%-1
AE4
RSVD
VSS
AE7
R275
_62R-1
P5
RSVDJ3RSVDN4RSVD
VSS
VSS
AF3
AF6
AF30
VSS
R276
X_62R-1
R255
_62R-1
W1
AC4
RSVD
MSID[1]V1MSID[0]
VSS
VSS
VSS
VSS
AF7
AG10
AG13
AG16
2005 Perf FMB 0 0
2005 Value FMB 0 1
V30
V29
V28
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
AG17
AG20
AG23
AG24
AG7
VSS
AH1
VSS
VSS
AH10
VSS
AH13
VSS
AH16
VSS
AH17
VSSV3VSS
VSS
AH20
VSS
AH23
VSS
VSS
AH24
V27
AH3
VSS
VSS
V26
AH6
V25
VSS
VSS
AH7
MSID1 MSID0
V24
V23
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
VSS
AJ24
VSS
AJ27
VSS
AJ28
VSS
R30
AJ29
VSS
R29
AJ30
VSS
VSS
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
AN1
VSS
VSS
AN10
AN13
VSS
AN16
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
VSS
AN17
H28
AN2
VSS
VSS
VSS
VSS
AN20
VSS
VSS
AN23
AN24
VSS
VSS
VSS
VSS
AN27
VSS
VSS
AN28
VSS
VSS
VSS
VSSB1VSS
B11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZIF-SOCK775-15u-in
B14
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
VSS
AL17
VSS
AL20
VSS
AL23
VSS
AL24
VSS
AL27
VSS
L30
AL28
VSS
VSSL3VSS
VSS
AL3
L29
L28
L27
VSS
VSS
VSS
VSS
VSS
AL7
AM1
AM10
L26
VSS
VSS
AM13
L25
VSS
VSS
AM16
L24
VSS
VSS
AM17
L23
VSS
VSS
AM20
VSSK7VSS
VSS
AM23
K5
VSS
AM24
K2
VSS
AM27
VSS
AM28
VSS
AM4
A A
MSI
Title
Size Document Number Re v
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - GND
MS-7196
2
836Tuesda y, S ep te mb er 06, 2005
0B
of
1
5
VREG_12V_POWER
R230
_5.6KR-1
ENLL
R233 _1KR-1
Q39
VID[0..5]6
R443 _2.2KR-1
X_C560P50XC551
R271 _100R-1
R472 _0R-1
R473 _0R-1
R267 _100R-1
R449 200KR
R448 X_47KR-1
R239
X_1.65KR1%-LF
C259
5
R238 _10KR-1
C554 C2200P16X
COP
X_C10P50NC553
R444 X_750R-LF
C264 X_C1000P50X
C262
X_C0.1U25Y
R451 _100KR-1
C556 C0.01U50X
R265 _2.2KR1%-LF
R249 37.4KR1%
C0.022U16X
VID_GD# 7,32
VID4
VID3
VID2
VID1
VID0
VID5
ENLL
COMP
FB
VDIFF
OFS
FS
REF
C550
X_C0.01U50X
VCCP
U27
ISL6566CRZ_QFN40
38
VID4
39
VID3
40
VID2
1
VID1
2
VID0
3
DACSEL/VID5
35
PGOOD
37
ENLL
8
COMP
9
FB
10
VDIFF
12
VSEN
11
RGND
6
OFST
36
FS
5
REF
4
VRM10
13
OCSET
14
ICOMP
15
ISUM
16
IREF
C549
C0.01U50X
R251 _33KR1%-1
R248 _33KR1%-1
R244 _33KR1%-1
D D
C C
VCC_VRM_SENSE6
VSS_VRM_SENSE6
B B
Close low side
mosfet
X_4.7KRT
A A
N-MMBT3904_NL_SOT23
VRM_GD21,32
R445 15KR
VCCP
VCC5
R241 _0R-1
R240
VCC5
7
VCC
GND
41
4
R447
_4.7R0805-LF
C555
C4.7U10Y0805
33
PVCC1
BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
PVCC2
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PVCC3
BOOT3
UGATE3
PHASE3
ISEN3
LGATE3
BOTTOM PAD CONNECT TO GND
THROUGH 10 vias
PHASE1
PHASE2
PHASE3
BOOT1
30
U_G1
31
PHASE1
29
R279 2.4KR1%
32
L_G1
34
24
BOOT2
26
U_G2
27
PHASE2
28
R268 2.4KR1%
25
L_G2
23
18
BOOT3
21
U_G3
20
PHASE3
22
R250 2.4KR1%
19
L_G3
17
R272 _2.2R0805-LF
R252 _2.2R0805-LF
R243 _2.2R0805-LF
CPU DECOUPLING CAPACITORS
4
C557 C1U16Y0805
12VP1
R450 _4.7R0805-LF
C267
C0.1U25Y
C552 C1U16Y0805
12VP2
R446 _4.7R0805-LF
C258
C0.1U25Y
C548 C1U16Y0805
12VP3
R442 _4.7R0805-LF
C249
C0.1U25Y
VREG_12V_POWER
VREG_12V_POWER
VREG_12V_POWER
3
R208
_10KR-1
R425
X_10KR-1
R185
_10KR-1
R410
X_10KR-1
VCCP
3
+12VP_FET
EC26
+
CD1000U16EL20-1
U_G1
R247
PHASE1
_10KR-1
L_G1
R428
X_10KR-1
U_G2
PHASE2
L_G2
U_G3
PHASE3
L_G3
VCCP
C210
C10U6.3X51206
C197
C10U6.3X51206
C190
C10U6.3X51206
C194
C10U6.3X51206
C199
C10U6.3X51206
VREG_12V_POWER
CD1000U16EL20-1
12
N-P75N02LR_TO252-RH
CD1000U16EL20-1
N-P75N02LR_TO252-RH
CD1000U16EL20-1
N-P75N02LR_TO252-RH
C189
C10U6.3X51206
C186
C10U6.3X51206
C187
C10U6.3X51206
C234
X_C10U6.3X51206
C537
X_C10U6.3X51206
C277
C0.01U50X
+12VP_FET
EC40
12
+
N-IPF09N03LAG_TO252-RH
R246
1R0805
UG1
G
Q38
G
+12VP_FET
EC39
+
12
R207
1R0805
UG2
G
Q30
G
+12VP_FET
EC21
+
12
R184
UG3
1R0805
Q21
VCCP
G
G
JPW1
3
12V
4
12V
PWR-2X2M_white-4.2pitch-RH
C251 C4.7U35Y1206
C225 C1U16Y0805
DS
G
Q33
N-P75N02LR_TO252-RH
DS
G
Q37
C147 C4.7U35Y1206
C220 C1U16Y0805
DS
N-IPF09N03LAG_TO252-RH
G
Q26
N-P75N02LR_TO252-RH
DS
G
Q29
C177 C4.7U35Y1206
C182 C1U16Y0805
DS
N-IPF09N03LAG_TO252-RH
G
Q19
N-P75N02LR_TO252-RH
DS
G
Q20
VCCP
C200
C10U6.3X51206
C193
C10U6.3X51206
C130
C10U6.3X51206
C202
C10U6.3X51206
C209
C10U6.3X51206
2
1
GND
2
GND
L18
CH-1.2U18A-LF
DS
N-IPF09N03LAG_TO252-RH
DS
R245
_2.2R0805-LF
C252
Q32
C1000P50X
DS
N-IPF09N03LAG_TO252-RH
DS
R211
_2.2R0805-LF
Q25
C226
C1000P50X
DS
N-IPF09N03LAG_TO252-RH
DS
R189
_2.2R0805-LF
C180
Q18
C1000P50X
C153
X_C10U6.3X51206
C540
X_C10U6.3X51206
C224
X_C10U6.3X51206
C206
C10U6.3X51206
C217
C10U6.3X51206
2
VREG_12V_POWER
C274
X_C4.7U35Y1206
L17
CH-0.6U40A-RH-1
HS1
HS-MS7033-RH
112
2
MOSFET Heatsinks
L16
CH-0.6U40A-RH-1
HS2
HS-MS7033-RH
112
2
L11
CH-0.6U40A-RH-1
HS3
HS-MS7033-RH
112
2
Title
Size Document Number Re v
Date: Sheet
MSI
1
VCCP VCCP
12
+
EC37
X_CD560U2.5FP
VCCP VCCP VCCP
12
12
+
+
VCCP VCCP VCCP VCCP
12
+
VCCP
VCCP
VCCP
SP Capacitors
VCCP
Solder Side
VCCP
EC14
CD560U2.5FP
EC15
CD560U2.5FP
C535
+
1 2
C531
+
1 2
C533
+
1 2
C169
+
1 2
C518
+
1 2
C146
+
1 2
C528
+
1 2
EC29
CD560U2.5FP
12
+
EC24
CD560U2.5FP
C330U2SP-LF
C330U2SP-LF
C330U2SP-LF
X_C330U2SP-LF
X_C330U2SP-LF
X_C330U2SP-LF
X_C330U2SP-LF
MICRO-STAR INt'L CO., LTD.
VRM10.1 Intersil 6566 3Phase
MS-7196
1
OS-CON
12
Capactiors
+
EC34
CD560U2.5FP
12
+
EC23
CD560U2.5FP
12
+
EC8
CD560U2.5FP
EL Capacitors
VCCP
VCCP
12
+
EC36
CD560U2.5FP
12
+
EC31
CD560U2.5FP
EC35
+
1 2
_CD1800U6.3EL20-3
EC13
+
1 2
_CD1800U6.3EL20-3
EC25
+
1 2
_CD1800U6.3EL20-3
936Tuesday, Se pt em be r 0 6, 2005
of
0B
8
7
6
5
4
3
2
1
V_1P5_CORE
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF30
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AH1
AH2
AH4
AJ5
AJ13
AJ14
AK2
AK3
AK4
AK14
AK15
AK20
R15
R17
R18
R20
R21
R23
R24
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
W24
W26
W27
Y15
VCC
VCC
AA17
VCC
VCC
AA18
VCC
VCC
AA19
VCC
VCC
AA20
VCC
VCC
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
M17
P41
HD0#
M39
HD1#
VCC
P42
HD2#
M42
HD3#
N41
HD4#
M40
HD5#
L40
HD6#
M41
HD7#
K42
HD8#
G39
HD9#
J41
HD10#
G42
HD11#
G40
HD12#
G41
HD13#
F40
HD14#
F43
HD15#
F37
HD16#
E37
HD17#
J35
HD18#
D39
HD19#
C41
HD20#
B39
HD21#
B40
HD22#
H34
HD23#
C37
HD24#
J32
HD25#
B35
HD26#
J34
HD27#
B34
HD28#
F32
HD29#
L32
HD30#
J31
HD31#
H31
HD32#
M33
HD33#
K31
HD34#
M27
HD35#
K29
HD36#
F31
HD37#
H29
HD38#
F29
HD39#
L27
HD40#
M24
HD41#
J26
HD42#
K26
HD43#
G26
HD44#
H24
HD45#
K24
HD46#
F24
HD47#
E31
HD48#
A33
HD49#
E40
HD50#
D37
HD51#
C39
HD52#
D38
HD53#
D33
HD54#
C35
HD55#
D34
HD56#
C34
HD57#
B31
HD58#
C31
HD59#
C32
HD60#
D32
HD61#
B30
HD62#
D30
HD63#
K40
KDINV_0#
A38
HDINV_1#
E29
HDINV_2#
B32
HDINV_3#
K41
L43
F35
G34
J27
M26
E34
B37
(INTEL-QG82945G-A2-LF)
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 6
H_DSTBN#0 6
H_DSTBP#1 6
H_DSTBN#1 6
H_DSTBP#2 6
H_DSTBN#2 6
H_DSTBP#3 6
H_DSTBN#3 6
H_D#[0..63] 6
H_DBI#[0..3] 6
U12A
H_A#3 H_D#0
H_A#[3..31]6
D D
H_ADSTB#06
H_ADSTB#16
C C
H_BR#06,7
H_BPRI#6
H_BNR#6
H_LOCK#6
H_ADS#6
H_REQ#[0..4]6
H_HIT#6
H_HITM#6
H_DEFER#6
H_TRDY#6
H_DBSY#6
H_DRDY#6
H_RS#[0..2]6
CK_H_MCH19
CK_H_MCH#19
B B
ICH_SYNC#21
PWR_GD21,32
H_CPURST#6,7
PLTRST#20,24,29
ICH_SYNC#
R171 16.9R1%-LF
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
M34
M38
AA37
M36
AA41
W42
G37
W41
W40
M31
M29
AJ12
M18
J39
K38
J42
K35
J37
N35
R33
N32
N34
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
V35
F38
D42
U39
U40
E41
D41
K36
E42
U41
P40
U42
V41
Y40
T40
Y43
T43
AJ9
C30
A28
C27
B27
D27
D28
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
VCC
VCC
VCC
VCC
VCC
RSVRD
AA35
VCC
RSVRD
AA42
AA34
VCC
VCC
RSVRD
RSVRD
AA38
VCC
RSVRD
L15
M15
VCC
VCC
RSVRD
RSVRD
U27
VCC
RSVRD
R27
VCC
RSVRD
A43
VCC
RSVRD
M11
AG25
VCC
VCC
RSVRD
RSVRD
AG26
VCC
RSVRD
AJ24
AG27
VCC
VCC
RSVRD
RSVRD
AJ27
VCC
RSVRD
AL39
AK40
VCC
VCC
RSVRD
RSVRD
AW17
VCC
RSVRD
AY14
AW18
VCC
VCC
RSVRD
RSVRD
BC16
VCC
RSVRD
AD30
AC34
VCC
VCC
RSVRD
RSVRD
Y30
VCC
RSVRD
Y33
AF31
VCC
VCC
RSVRD
RSVRD
AD31
VCC
RSVRD
U30
VCC
RSVRD
V31
VCC
RSVRD
AA30
VCC
RSVRD
AK21
AC30
VCC
VCC
RSVRD
RSVRD
AJ23
VCC
RSVRD
AJ26
AL29
VCC
VCC
RSVRD
RSVRD
AL20
VCC
RSVRD
AJ21
VCC
RSVRD
AL26
AK27
VCC
VCC
RSVRD
RSVRD
AJ29
VCC
RSVRD
AG29
VCC
RSVRD
V30
VCC
BC43NCBC42
VCC
NC
VCC
VCC
NC
BC2NCBC1
VCC
VCC
NC
BB43
VCC
VCC
NC
BB2NCBB1NCBA2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NCC2NC
NCB3NCB2NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E35
B43NCB42NCB41
A42
Y17
Y18
Y19
Y21
Y23
Y25
C42
AW2
AV27NCAV26
AW26
Y27
AA15
V_1P5_CORE
V_FSB_VTT
A A
R174
_60.4R1%-1
HXSCOMP
C167
X_C2.2P50N
R163
_84.5R1%-LF
V_FSB_VTT
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
PLACE DIVIDER RESISTOR NEAR VTT
R161
_301R1%-1
R179 _62R-1
C157
C0.01U50X
HXSWING
V_FSB_VTT
R165
_124R1%-LF
R164 10R
R167
_210R1%-1
CAPS SHOULD BE PLACED NEAR MCH PIN
8
7
6
5
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
MCH_GTLREF
C166
C0.1U25Y
C163
X_C220P16X
R168 _0R-1
4
MCH_GTLREF_CPU 6
MSI
Title
Size Document Number Re v
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU
MS-7196
2
10 36Tuesday, Se pt em be r 0 6, 2005
0B
of
1
8
7
6
5
4
3
2
1
SCKE_A[0..1]14,16
DQM_A[0..7]14
DATA_A[0..63]14
DQM_A6
DQM_A1
DQM_A4
DQM_A2
DQM_A7
DQM_A3
DATA_A16
DATA_A21
DATA_A6
DATA_A4
AN1
SADQ3
SADQ4
SBDQ1
SBDQ2
AP8
DATA_B2
DATA_A5
AP4
SADQ5
SBDQ3
AP9
DATA_B3
AU5
SADQ6
SBDQ4
AJ11
DATA_B4
DATA_A7
AU2
SADQ7
SBDQ5
AL9
DATA_B5
DATA_A8
AW3
SADQ8
SBDQ6
AM10
DATA_B6
DATA_A9
AY3
SADQ9
SBDQ7
AP6
DATA_B7
DATA_A10
DATA_A11
BA7
BB7
SADQ10
SBDQ8
AV6
AU7
DATA_B8
DATA_B9
DATA_A12
DATA_A13
AV1
AW4
SADQ11
SADQ12
SBDQ9
SBDQ10
AV12
AM11
DATA_B11
DATA_B10
DATA_A14
DATA_A15
BC6
AY7
SADQ13
SADQ14
SBDQ11
SBDQ12
AR5
AR7
DATA_B12
DATA_B13
DATA_A17
AW12
AY10
SADQ15
SADQ16
SBDQ13
SBDQ14
AR12
AR10
DATA_B14
DATA_B15
DATA_A0
DATA_A1
DATA_A3
D D
SCS_A#[0..1]14,16
RAS_A#14,16
CAS_A#14,16
WE_A#14,16
MAA_A[0..13]14,16
C C
B B
ODT_A[0..1]14,16
SBS_A[0..2]14,16
DQS_A014
DQS_A#014
DQS_A114
DQS_A#114
DQS_A214
DQS_A#214
DQS_A314
DQS_A#314
DQS_A414
DQS_A#414
DQS_A514
DQS_A#514
DQS_A614
DQS_A#614
DQS_A714
DQS_A#714
P_DDR0_A14
N_DDR0_A14
P_DDR1_A14
N_DDR1_A14
P_DDR2_A14
N_DDR2_A14
SCS_A#0
SCS_A#1
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
ODT_A0
ODT_A1
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
SMPCOMP_N
SMPCOMP_P MCH_VREF_B
BB37
BA39
BA35
AY38
BA34
BA37
BB35
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
AW37
AY39
AY37
BB40
BC33
AY34
BA26
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
BB32
AY32
AK42
AK41
BA31
BB31
AH40
AH43
AU4
AR2
BA3
BB4
AY5
BB5
AY6
BA5
AM3
AL5
AJ6
AJ8
U12B
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACLK0
SACLK0#
SACLK1
SACLK1#
SACLK2
SACLK2#
SACLK3
SACLK3#
SACLK4
SACLK4#
SACLK5
SACLK5#
MCH_SRCOMP0
MCH_SRCOMP1
SMOCDCOMP0
SMOCDCOMP1
AP3
SADQ0
DATA_A2
AP2
SADQ1
AU3
SADQ2
AV4
SBDQ0
R194 _80.6R1%-LF
(INTEL-QG82945G-A2-LF)
SMPCOMP_P
AL6
AL8
DATA_B0
DATA_B1
DATA_A18
DATA_A19
BA12
BB12
SADQ17
SADQ18
SBDQ15
SBDQ16
AM15
AM13
DATA_B17
DATA_B16
DATA_A20
BA9
BB9
SADQ19
SADQ20
SBDQ17
SBDQ18
AV15
AM17
DATA_B18
DATA_B19
DATA_A22
DATA_A23
BC11
AY12
SADQ21
SADQ22
SBDQ19
SBDQ20
AN12
AR13
DATA_B21
DATA_B20
DATA_A24
DATA_A25
AM20
AM18
SADQ23
SADQ24
SBDQ21
SBDQ22
AT15
AP15
DATA_B23
DATA_B22
DATA_A26
DATA_A27
AV20
AM21
SADQ25
SADQ26
SBDQ23
SBDQ24
AM24
AM23
DATA_B24
DATA_B25
DATA_A29
DATA_A28
AP17
AR17
SADQ27
SADQ28
SBDQ25
SBDQ26
AV24
AM26
DATA_B27
DATA_B26
DATA_A30
AP20
SADQ29
SBDQ27
AP21
DATA_B28
DATA_B[0..63]15
DATA_A32
DATA_A31
AT20
AP32
SADQ30
SADQ31
SBDQ28
SBDQ29
AP24
AR21
DATA_B30
DATA_B29
DATA_A34
DATA_A33
AV34
AV38
SADQ32
SADQ33
SBDQ30
SBDQ31
AT24
AU27
DATA_B32
DATA_B31
DATA_A35
DATA_A36
AU39
AV32
SADQ34
SADQ35
SBDQ32
SBDQ33
AN29
AR31
DATA_B34
DATA_B33
DATA_A37
DATA_A38
AT32
AR34
SADQ36
SADQ37
SADQ38
SBDQ34
SBDQ35
SBDQ36
AP27
AM31
DATA_B35
DATA_B36
DATA_A40
DATA_A39
AU37
AR41
SADQ39
SBDQ37
AP31
AR27
DATA_B37
DATA_B38
DATA_A41
DATA_A42
AR42
AN43
SADQ40
SADQ41
SBDQ38
SBDQ39
AP35
AU31
DATA_B40
DATA_B39
DATA_A43
DATA_A44
AM40
AU41
SADQ42
SADQ43
SBDQ40
SBDQ41
AP37
AN32
DATA_B42
DATA_B41
DATA_A45
DATA_A46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
DATA_B43
DATA_B44
DATA_A48
DATA_A47
AN40
AL41
SADQ46
SADQ47
SBDQ44
SBDQ45
AU38
AM38
DATA_B46
DATA_B45
DATA_A49
DATA_A50
AL42
AF39
SADQ48
SADQ49
SBDQ46
SBDQ47
AL34
AM34
DATA_B47
DATA_B48
DATA_A52
DATA_A51
AE40
AM41
SADQ50
SADQ51
SBDQ48
SBDQ49
AJ34
AF32
DATA_B49
DATA_B50
DATA_A53
DATA_A54
AM42
AF41
SADQ52
SADQ53
SBDQ50
SBDQ51
AL31
AF34
DATA_B52
DATA_B51
DATA_A56
DATA_A55
AF42
AD40
SADQ54
SADQ55
SBDQ52
SBDQ53
AJ32
AG35
DATA_B54
DATA_B53
DATA_A57
DATA_A58
AD43
AA39
SADQ56
SADQ57
SBDQ54
SBDQ55
AD32
AC32
DATA_B55
DATA_B56
DATA_A60
DATA_A59
AA40
AE42
SADQ58
SADQ59
SBDQ56
SBDQ57
Y32
AD34
DATA_B57
DATA_B58
DATA_A61
DATA_A62
AE41
AB41
SADQ60
SADQ61
SBDQ58
SBDQ59
AF35
AA32
DATA_B60
DATA_B59
DATA_A63
AB42
SADQ62
SADQ63
SBDQ60
SBDQ61
AF37
AC33
DATA_B61
DATA_B62
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SBDQ62
SBDQ63
AC35
DATA_B63
BC24
BA25
SACKE1
SACKE2
SBCKE0
BA14
AY16
SCKE_B0
SCKE_B1
SACKE3
SBCKE1
BA13
SCKE_B[0..1]15,16
DQM_B[0..7]15
VCC_DDR
A A
R195 _80.6R1%-LF
C185
C0.1U25Y
SMPCOMP_N
8
7
6
5
4
DQM_A0
AR3
SBCKE2
SBCKE3
BB13
AY2
SADM1
SADM0
SBDM7
AD39
DQM_B7
DQM_B6
AP18
BB10
SADM2
SBDM6
AJ39
AR38
DQM_B5
DQM_A5
AT34
SADM4
SADM3
SBDM4
SBDM5
AR29
DQM_B3
DQM_B4
AG40
AP39
SADM5
SBDM3
AP13
AP23
DQM_B2
AC40
SADM7
SADM6
SBDM1
SBDM2
AW7
DQM_B1
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1
SMVREF0
SBDM0
AL11
DQM_B0
SCS_B#0
BA40
SCS_B#1
AW41
BA41
AW40
RAS_B#
BA23
CAS_B#
AY24
WE_B#
BB23
MAA_B0
BB22
MAA_B1
BB21
MAA_B2
BA21
MAA_B3
AY21
MAA_B4
BC20
MAA_B5
AY19
MAA_B6
AY20
MAA_B7
BA18
MAA_B8
BA19
MAA_B9
BB18
MAA_B10
BA22
MAA_B11
BB17
MAA_B12
BA17
MAA_B13MAA_A13
AW42
ODT_B0
AY42
ODT_B1
AV40
AV43
AU40
SBS_B0
AW23
SBS_B1
AY23
SBS_B2
AY17
DQS_B0
AM8
DQS_B#0
AM6
DQS_B1
AV7
DQS_B#1
AR9
DQS_B2
AV13
DQS_B#2
AT13
DQS_B3
AU23
DQS_B#3
AR23
DQS_B4
AT29
DQS_B#4
AV29
DQS_B5
AP36
DQS_B#5
AM35
DQS_B6
AG34
DQS_B#6
AG32
DQS_B7
AD36
DQS_B#7
AD38
P_DDR0_B
AM29
N_DDR0_B
AM27
P_DDR1_B
AV9
N_DDR1_B
AW9
P_DDR2_B
AL38
N_DDR2_B
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
AM2
MCH_VREF_A
AM4
PLACE 0.1UF CAP CLOSE TO MCH
3
SCS_B#[0..1] 15,16
RAS_B# 15,16
CAS_B# 15,16
WE_B# 15,16
MAA_B[0..13] 15,16
ODT_B[0..1] 15,16
SBS_B[0..2] 15,16
DQS_B0 15
DQS_B#0 15
DQS_B1 15
DQS_B#1 15
DQS_B2 15
DQS_B#2 15
DQS_B3 15
DQS_B#3 15
DQS_B4 15
DQS_B#4 15
DQS_B5 15
DQS_B#5 15
DQS_B6 15
DQS_B#6 15
DQS_B7 15
DQS_B#7 15
P_DDR0_B 15
N_DDR0_B 15
P_DDR1_B 15
N_DDR1_B 15
P_DDR2_B 15
N_DDR2_B 15
C184
C0.1U25Y
VCC_DDR
MCH_VREF_A
PLACE 0.1UF CAP CLOSE TO MCH
C183
C0.1U25Y
CP3
X_COPPER
R191 _1KR1%-1
R188 X_0R-1
MCH_VREF_A
MCH_VREF_B
R187
_1KR1%-1
MSI
Title
Size Document Number Re v
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - Memory
MS-7196
2
11 36Tuesday, Se pt em be r 0 6, 2005
of
1
0B
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