MSI MS-7187 Schematics
1
COVER SHEET
BLOCK DIAGRAM
CLOCK MAP
POWER MAP
1
2
3
4
MS-7187M1
CPU:
Version 1A
Intel Prescott ( L2=2MB ) - 3.4G & Above
GPIO & JUMPER SETTING
Intel LGA775-CPU
VRM10.1 Intersil 6566 3Phase
Intel Lakeport -MCH
DDR II DIMM 1and DIMM2 1 & 2&3 & 4
PCI EXPRESS X16 SLOT
5
6-8
9
10-13
14-16
17
Intel Cendar Mill (65nm) - 3.73G & Above
Intel Smithfield (90nm Dual core)
System Chipset:
Intel Lakeport - GMCH (North Bridge)
Intel ICH7R (South Bridge)
On Board Chipset:
NA
Clock Generator - ICS954119
ICH7
18
19
20-22
BIOS -- FWH FLASH 4Mb
Azalia CODEC(CMI9880L)
LPC Super I/O -- W83627THF
A A
PCI Slot 1 & 2 & 3
PCI_MS1 & FWH
LAN - 82562EZ
23
24
25
LAN - Intel 82562EZ
1394 -- VIA VT-6307
Clock Generator - ICS954119
Main Memory:
VIA VT-6307
26
DDR II * 4 (Max 4GB)
USB CONNECTORS
Azalia CODEC(CMI9880L)
SIO-W83627THF & KB/MS
27
28
29
Expansion Slots:
PCI Express X16 SLOT * 1
PCI Express X1 SLOT * 1
ATX,F_ PANEL,FAN CONTROL
30
PCI 2.3 SLOT * 2
IDE & SATA&COM1&LPT
MS7 ACPI Controller
Auto BOM manual
PWOK MAP
31
32
33
34
35History
Intersil PWM:
Controller:
1
ISL6566CR_QFN40
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
COVER SHEET
COVER SHEET
COVER SHEET
MS-7187M1
MS-7187M1
MS-7187M1
of
of
of
135Tuesday, November 01, 2005
135Tuesday, November 01, 2005
135Tuesday, November 01, 2005
1A
1A
1A
VRM_GD
1
VTT_PWG
VRM 10.1
Intersil 6565
3-Phase PWM
PCIRST#1
HD_RST#
PCI
EXPRESS
X16
Connector
IDE Primary
SERIAL ATA1
SERIAL ATA2
A A
SERIAL ATA3
SERIAL ATA4
USB2.0
P.28
P.15
P.19
P.18
P.18
P.18
P.18
P.18
UltraDMA
33/66/100
USB
Intel LGA775 Processor
FSB
H_PWRGD
H_CPURST#
Lakeport
MCH
P.6~9
DMI
PLRST#
VRM_GD
ICH7
P.10~12
PWR_GD
LPC Bus
P.3~5
DDRII
266/333
MHz
SLP_S4#
SLP_S3#
PSON#
USB Port0~ 7
P.25
RSMRST#
PWRBTN#
Block Diagram
4 DDR II
DIMM
Modules
PCIRST_ICH6#
PCI
PWR_OK
PCIRST#2
ATX1
PWR_GD
PCIRST#1
PCI Slot 1
PCI Slot 2
PCI Slot 3
P.23 P.23 P.15
MS7
VID_GD
RSMRST#
HD_RST#
PCIRST#2
PCI Extender
P.30
PCIRST#1
CMI9880L
Azalia Codec
LAN
INTEL 82562EZ
1394
VIA VT-6307
P.16
P.17
P.26
PCI
JFP1
LPC SIO
W83627THF
P.14
FWH
P.30
FP_RST#SW_ON#
Keyboard
Mouse
PCIRST_ICH6#
1
P.14
P.14
Floopy Parallel Serial
P.14 P.18 P.18
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
MS-7187M1
MS-7187M1
MS-7187M1
235Tuesday, November 01, 2005
235Tuesday, November 01, 2005
235Tuesday, November 01, 2005
of
of
of
1A
1A
1A
5
4
3
2
1
HCLK
LGA775
CLOCK MAP
D D
ICS954119 1/2
Clock
Generator
C C
MCHCLK
DOTCLK
96MHz
ICHCLK
SATACLK
USB48MHz
ICH14.318MHz
SIO48MHz
Lakeport
MCH
ICH7
W83627THF
LPC IO
ICS954119 2/2
Clock
Generator
PCI_E1PCI_E1_100MHz
PCI-Express X 16
PCI_E1CK_PE_100M_1PORT
PCI-Express X 1
INTELCK_PE_100M_LAN
LAN_82562EZ
1394_PCLK
33MHz
B B
FWH_PCLK
33MHz
VT6306
1394
FWH
SIO_PCLK
33MHz
A A
5
PCICLK[0..3]
33MHz
PCI2
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
PCI3
4
3
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
CLOCK MAP
CLOCK MAP
CLOCK MAP
MS-7187M1
MS-7187M1
MS-7187M1
1
335Tuesday, November 01, 2005
335Tuesday, November 01, 2005
335Tuesday, November 01, 2005
of
of
of
1A
1A
1A
5
POWER MAP
4
3
2
1
D D
C C
B B
ATX POWER
+12V +5V +3.3V +5VSB
MSI
ACPI
Controller
38.81*1.8/5/0.8 = 17.46A
5VDIMM
MS - 7
4+9.4+15.3+2.6+1.31+6.2 = 38.81A
MSI
MS6 +
V_1P5_CORE
V_1P05_CORE
V_FSB_VTT
6.2A
125A 5.3A
VCC_DDR
17.87A
1.31A
1.875A
6.5A
5A
12.6A
PCI_E1
PCI_E3
LGA775VRM 10.1
Lakeport
4A
MCH
13.8A + 1.5A
= 15.3A
9.4A
DDR2 X 4
1.2A
TBD (2.57A)
1.31A
ICH7
0.7A
14mA
0.9A
PCI2
PCI3
VLAN25
INTEL
3.775A
Tekoa
VLAN12
and
VCC3_SB VTT_DDR
W83627THF
1.2A
82562EZ
5VDUAL
A A
5
4A
4
4.0A
USB
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
2
Date: Sheet
POWER MAP
POWER MAP
POWER MAP
MS-7187M1
MS-7187M1
MS-7187M1
1
1A
1A
1A
of
of
of
435Tuesday, November 01, 2005
435Tuesday, November 01, 2005
435Tuesday, November 01, 2005
8
7
6
5
4
3
2
1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name
GPIO[0] SIO_SMI# AB18 I/O Vcc3p3 N Y 5 Input SIO_SMI#
GPIO[1] PREQ#5 C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
GPIO[6] unmuxed AC21 I/O Vcc3p3 N Y 3.3 Input ATADET0
GPIO[7] THERM(#) AC18 I/O Vcc3p3 N Y 3.3 Input (GPI7)THERM(#) function
GPIO[8] SIO_PME# E21 I/O VccSus3p3 N Y 3.3 Input SIO_PME#
FWH
GPIO Pin# Power Tol Signal Name
FPGI[0] 6 Main 3.3 pull-down
FPGI[1] 5 Main 3.3 pull-down
FPGI[2] 4 Main 3.3 pull-down
FPGI[3] 3 Main 3.3 pull-down
FPGI[4] 30 Main 3.3 pull-down
PCI Config.
GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input SMB_ALERT#(only pull high vcc3_sb)
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input (NA)pull high vcc3_sb
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A PGNT#5
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 FAN_CTRL
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input NA(pull high vcc3)
C C
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input PULL HIGH VCC3
GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change LAN_DISABLE#
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 NC
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 Connect 0 OHM(for future chip design)
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 Connect a jump connector
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 Connect a jump connector
GPIO[29] OC5# C3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[30] OC6# A2 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[31] OC7# B3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[32] unmuxed AG18 I/O Vcc3p3 N N 3.3 1 CLEAR_CMOS#
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 BIOS_WP#
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
B B
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input NA(Pull high vcc3)
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A PGNT#4
DDRII DIMM Config.
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
SIO W83627THF
PIN NAME
GPIO33
GPIO45
A A
GPIO35
GPIO50
71 OUTPUT ODGPIO43
89
69
86 Diag LED Output
110
USAGE
Input/OutputPIN#
OUTPUT OD
OUTPUT OD
OUTPUT
NOTES
Diag LED Output
Diag LED Output
Diag LED OutputOUTPUT OD
PCI_EX Over clock Output
JUMPER SETTING
Note: FWH GPs should only be used for static options,
do not put dynamic nets on these
DEVICE
PCI2
MCP1 INT Pin
PIRQ#A
PIRQ#B
PIRQ#C
PCI3
PIRQ#D
DEVICE ADDRESS
DIMM 1
DIMM 2
A0H
A1H
A2H
DIMM 2
JBAT1
A3H
(1-2)NORMAL
REQ#/GNT#
PREQ#3PIRQ#E1394
IDSEL
AD19
PGNT#3
PREQ#0
PGNT#0
PREQ#1
AD16
AD17
AD18
PGNT#1 PCI_CLK2
PREQ#2
PREQ#2
PREQ#4
AD20PGNT#4
CLOCK
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1
MCLK_A2/MCLK_A#2
MCLK_A3/MCLK_A#3
MCLK_A4/MCLK_A#4
MCLK_A5/MCLK_A#5
MCLK_B0/MCLK_B#0
MCLK_B1/MCLK_B#1DIMM 3
MCLK_B2/MCLK_B#2
MCLK_B3/MCLK_B#3
MCLK_B4/MCLK_B#4
MCLK_B5/MCLK_B#5
(2-3)CLEAR
CLOCK
1394_PCLK
PCI_CLK0
PCI_CLK1
PCI_CLK3
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Date: Sheet
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Date: Sheet
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GPIO MAP
GPIO MAP
GPIO MAP
MS-7187M1
MS-7187M1
MS-7187M1
1A
1A
1A
of
of
of
535Tuesday, November 01, 2005
535Tuesday, November 01, 2005
535Tuesday, November 01, 2005
1
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
8
7
6
5
4
3
2
1
AN4
AN3
AN6
AN5
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D13#
D12#D8D11#
D10#
D9#
B12
B10
A11
C11
H_D#12
H_D#13
H_D#9
H_D#11
H_D#10
R68 X_1KRR68 X_1KR
TP4TP4
AM5
AM7
AJ3
AK3
RSVD
ITP_CLK1
ITP_CLK0
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A10
H_D#7
H_D#8
H_D#4
H_D#5
H_D#6
H_D#3
VID5
VID4
AL4
AK4
VID6#
VID5#
VID4#
VID_SELECT
GTLREF_SEL
CS_GTLREF
LINT0/INTR
H_D#1
H_D#2
CPU SIGNAL BLOCK
D D
H_INIT#20
H_BPRI#10
H_A20M#20
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_TESTHI13VTT_OUT_LEFT
R54 62RR54 62R
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_DBI#[0..3]10
H_IERR#7
H_FERR#7,20
H_STPCLK#20
H_DBSY#10
H_DRDY#10
H_TRDY#10
H_HITM#10
H_DEFER#10
THERMDA_CPU29
THERMDC_CPU29
TRMTRIP#20
H_PROCHOT#7
ICH_H_SMI#20
R90 62RR90 62R
VTT_OUT_RIGHT
H_FSBSEL07,12,19
H_FSBSEL17,12,19
H_FSBSEL27,12,19
H_CPURST#7,10
H_D#[0..63]10
H_ADS#10
H_LOCK#10
H_BNR#10
H_HIT#10
H_IGNNE#20
H_PWRGD7,20
C C
B B
A A
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
H_A#[3..31]10
U3A
U3A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
H_D#53
D53#
D52#
C14
H_D#52
D51#
A14
C15
H_D#51
H_D#50
D50#
D49#
D17
H_D#49
AJ6
AJ5
A35#
D48#
D20
G22
H_D#48
H_D#47
AH5
A34#
A33#
D47#
D46#
D22
H_D#46
H_A#31
AH4
AG5
A32#
D45#
E22
G21
H_D#44
H_D#45
H_A#30
AG4
A31#
A30#
D44#
D43#
F21
H_D#43
H_A#29
H_A#28
AG6
AF4
A29#
D42#
F20
E21
H_D#42
H_D#41
H_A#26
H_A#27
AF5
A28#
A27#
D41#
D40#
E19
H_D#40
H_D#39
AB4
A26#
D39#
E18
H_A#25
H_A#24
AC5
AB5
A25#
D38#
F18
F17
H_D#38
H_D#37
H_A#23
AA5
A24#
A23#
D37#
D36#
G17
H_D#36
H_A#22
H_A#21
AD6
AA4
A22#
D35#
E16
G18
H_D#34
H_D#35
H_A#19
H_A#20
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
D32#
E15
G16
H_D#33
H_D#32
H_A#17
H_A#18
H_A#16
H_A#15
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D31#
D30#
D29#
D28#
F15
F14
G15
G14
H_D#30
H_D#31
H_D#29
H_D#28
H_A#14
H_A#13
D27#
D26#
E13
G13
H_D#26
H_D#27
H_A#12
H_A#11
D25#
F12
D13
H_D#25
H_D#24
H_A#10
U6
D24#
F11
H_D#23
H_A#6
H_A#8
H_A#5
H_A#7
H_A#9
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
H_D#19
H_D#22
H_D#18
H_D#21
H_D#20
H_A#4
H_A#3
L5
H_D#16
H_D#17
AC2
D11
C12
H_D#15
H_D#14
DBR#
D14#
VID2
VID0
VID1
VID3
AL6
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
AN7
H1
GTLREF0
H2
GTLREF1
H29
E24
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
TESTHI12
P1
TESTHI11
H5
TESTHI10
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
FORCEPH
G6
RSVD
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
T2
COMP5
J2
COMP4
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
ADSTB1#
R6
ADSTB0#
C17
DSTBP3#
G19
DSTBP2#
E12
DSTBP1#
B9
DSTBP0#
A16
DSTBN3#
G20
DSTBN2#
G12
DSTBN1#
C8
DSTBN0#
L1
LINT1/NMI
K1
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B4
H_D#0
FP_RST# 21,30
VID[0..5] 9
R6 62RR6 62R
TP_GTLREF_SEL
MCH_GTLREF_CPU
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
RSVD_AK6
RSVD_G6
H_RS#2
H_RS#1
H_RS#0
TP6TP6
TP5TP5
H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0
CPU_GTLREF0
CPU_GTLREF1
RN8 8P4R-62RRN8 8P4R-62R
1 2
3 4
5 6
7 8
R75 62RR75 62R
R129 62RR129 62R
R66 62RR66 62R
R125 62RR125 62R
R11 X_62RR11 X_62R
R77 X_62RR77 X_62R
CK_H_CPU# 19
CK_H_CPU 19
RN58 8P4R-62RRN58 8P4R-62R
1 2
3 4
5 6
7 8
R72 62RR72 62R
R131 62RR131 62R
TP7TP7
TP11TP11
TP10TP10
TP8TP8
H_ADSTB#1 10
H_ADSTB#0 10
H_DSTBP#3 10
H_DSTBP#2 10
H_DSTBP#1 10
H_DSTBP#0 10
H_DSTBN#3 10
H_DSTBN#2 10
H_DSTBN#1 10
H_DSTBN#0 10
H_NMI 20
H_INTR 20
VCC_VRM_SENSE
VSS_VRM_SENSE
CPU_GTLREF0 7
CPU_GTLREF1 7
TP9TP9
MCH_GTLREF_CPU 10
H_REQ#[0..4] 10
H_RS#[0..2] 10
VCC_VRM_SENSE 9
VSS_VRM_SENSE 9
VTT_OUT_LEFT
V_FSB_VTT
VTT_OUT_RIGHT 7,8
VTT_OUT_LEFT 7
C42
C42
X_C0.1U25Y
X_C0.1U25Y
BSEL
1
02
FSB FREQUENCY
TABLE
267 MHZ (1067)000
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
RN4
RN4
8P4R-680R
8P4R-680R
VID3
1
VID1
VID4
VID2
VID0
VID5
H_BR#0 7,10
VTT_OUT_RIGHT
C25 C0.1U25YC25 C0.1U25Y
C11 C0.1U25YC11 C0.1U25Y R47 49.9R1%R47 49.9R1%
PLACE BPM TERMINATION NEAR CPU
2
3
4
5
6
7
8
R42 680RR42 680R
R22 680RR22 680R
RN3 8P4R-51R-LF RN3 8P4R-51R-LF
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
RN6 8P4R-51R-LF RN6 8P4R-51R-LF
R34 X_49.9R1%R34 X_49.9R1%
R64 49.9R1%R64 49.9R1%
VTT_OUT_RIGHT
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TMS
H_TDI
H_BPM#2
H_BPM#4
H_TDO
H_TRST#
H_TCK
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Signals
Intel LGA775 - Signals
Intel LGA775 - Signals
MS-7187M1
MS-7187M1
MS-7187M1
2
1A
1A
635Tuesday, November 01, 2005
635Tuesday, November 01, 2005
635Tuesday, November 01, 2005
1
1A
of
of
of
8
VCCP
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
U3B
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
U3B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y23
Y24
Y25
Y26
Y27
Y28
Y29
W30
VCCP
D D
C C
AG22
VCC
VCC
W29
AG25
VCC
VCC
W28
AG26
VCC
VCC
W27
AG27
VCC
VCC
W26
AG28
W25
VCC
VCC
AG29
VCC
VCC
W24
7
AG30
VCC
W23
AG8
VCC
AG9
VCC
VCCU8VCCV8VCC
AH11
VCC
VCC
U30
AH12
VCC
VCC
U29
AH14
VCC
VCC
U28
AH15
VCC
VCC
U27
AH18
VCC
VCC
U26
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
U23
AH25
VCC
VCCT8VCC
AH26
VCC
VCC
T30
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
VCC
VCC
T27
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
AJ11
T23
VCC
AJ12
VCC
AJ14
VCC
AJ15
VCC
VCCN8VCCP8VCCR8VCC
6
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N23
N24
N25
N26
N27
N28
N29
N30
M24
M25
M26
M27
M28
M29
M30
VCC
VCC
AK25
VCC
M23
AK26
VCC
5
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
K25
K26
K27
K28
K29
K30
AM18
VCC
VCC
J21
AM19
VCC
VCC
J20
AM21
VCC
VCC
J19
AM22
VCC
VCC
J18
AM25
VCC
VCC
J15
AM26
VCC
VCC
J14
4
AM29
VCC
VCC
J13
AM30
VCC
VCC
J12
AM8
J11
VCC
VCC
AM9
VCC
VCC
J10
AN11
AN9
AN12
VCC
VCC
AN8
AN14
AN15
AN18
VCC
VCC
VCC
VCC
VTT_OUT_RIGHT
VCC
VCC
VCC
VCC
AN26
AN29
AN30
AN19
AN21
AN22
VCC
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTTPWRGD
VTT_OUT_LEFT
VTT_SEL
RSVD
VCC
HS11HS22HS33HS4
AN25
A23
B23
D23
C23
A25
VTT
A26
VTT
A27
VTT
A28
VTT
A29
VTT
A30
VTT
B25
VTT
B26
VTT
B27
VTT
B28
VTT
B29
VTT
B30
VTT
C25
VTT
C26
VTT
C27
VTT
C28
VTT
C29
VTT
C30
VTT
D25
VTT
D26
VTT
D27
VTT
D28
VTT
D29
VTT
D30
VTT
AM6
AA1
J1
F27
F29
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
4
3
H_VCCA
H_VSSA
H_VCCABB
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
R1220RR122
V_FSB_VTT
2
0R
V_FSB_VTT
C78 C10U10Y0805C78 C10U10Y0805
C128 C10U10Y0805C128 C10U10Y0805
C87 C10U10Y0805C87 C10U10Y0805
1
CAPS FOR FSB GENERIC
VTT_OUT_LEFT
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
B B
VTT_OUT_LEFT
R89 124R1%R89 124R1%
R78 124R1%R78 124R1%
R88
R88
210R1%
210R1%
R86
R86
210R1%
210R1%
R91 10RR91 10R
C45
C44
C44
C0.1U25Y
C0.1U25Y
R74 10RR74 10R C85
C43
C43
C0.1U25Y
C0.1U25Y
C45
C100P50N
C100P50N
C39
C39
C100P50N
C100P50N
CPU_GTLREF0 6
V_FSB_VTT
L4 10uH/8/125mA/Rdc=0.7L4 10uH/8/125mA/Rdc=0.7
CPU_GTLREF1 6
PLACE AT CPU END OF ROUTE
H_IERR#
7
H_PROCHOT#
H_CPURST#
H_PWRGD
H_BR#0
H_FERR# 6,20
H_PROCHOT# 6
H_CPURST# 6,10
H_PWRGD 6,20
H_BR#0 6,10
H_IERR# 6
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
RN24
RN24
1
3
5
7
8P4R-470R
8P4R-470R
6
5
VTT_OUT_RIGHT6,8
VTT_OUT_LEFT6
A A
VTT_OUT_RIGHT
VTT_OUT_LEFT
V_FSB_VTT
V_FSB_VTT
R387 62RR387 62R
R23 100RR23 100R
R130 62RR130 62R
R87 X_100RR87 X_100R
R69 62RR69 62R
R61 62RR61 62R
H_FERR#
PLACE AT ICH END OF ROUTE
8
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
H_VCCABB
2
4
6
8
L5 10uH/8/125mA/Rdc=0.7L5 10uH/8/125mA/Rdc=0.7
VID_GD#9,32
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
4
VTT_OUT_RIGHT
VCC5_SB
R63
R63
1KR
1KR
R62 10KRR62 10KR
H_FSBSEL1 6,12,19
H_FSBSEL0 6,12,19
H_FSBSEL2 6,12,19
C75
C75
X_C1U10Y
X_C1U10Y
R53 680RR53 680R
C82
C82
C10U10Y0805
C10U10Y0805
VTT_PWG
Q4
Q4
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
3
C85
C10U10Y0805
C10U10Y0805
H_VCCA
H_VSSA
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
C38
C38
X_C1U10Y
X_C1U10Y
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - Power
Intel LGA775 - Power
Intel LGA775 - Power
MS-7187M1
MS-7187M1
MS-7187M1
2
1A
1A
735Tuesday, November 01, 2005
735Tuesday, November 01, 2005
735Tuesday, November 01, 2005
1
1A
of
of
of
8
7
6
5
4
3
2
1
V_FSB_VTT
D D
C C
B B
VTT_OUT_RIGHT6,7
TP14TP14
D14
RSVDD1RSVD
VSS
AF10
AF13
E23
VSS
AF16
RSVD
VSS
AF17
VSS
AF20
TP15TP15
TP12TP12
TP13TP13
F23
F6
RSVDE5RSVDE6RSVDE7RSVD
VSS
VSS
VSS
VSS
AF23
AF24
AF25
AF26
B13
RSVD
IMPSEL#
VSS
VSS
VSS
AF27
AF28
VSS
AF29
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
R58
R58
R28
R28
60.4R1%
60.4R1%
60.4R1%
60.4R1%
H_COMP6
H_COMP7
AE3
AE4
U3C
U3C
RSVD
A12
A15
A18
A21
A24
COMP6Y3COMP7
VSS
VSS
VSS
A2
VSS
VSS
VSS
A6
VSS
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE5
AE7
AE29
AE30
R67
R67
62R
62R
P5
RSVDJ3RSVDN4RSVD
VSS
VSS
AF3
AF6
AF30
VSS
R59
R59
X_62R
X_62R
R65
R65
62R
62R
W1
AC4
RSVD
MSID[1]V1MSID[0]
VSS
VSS
VSS
VSS
AF7
AG10
AG13
AG16
2005 Perf FMB 0 0
2005 Value FMB 0 1
V30
V29
V28
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
AG17
AG20
AG23
AG24
AG7
VSS
AH1
VSS
VSS
AH10
VSS
AH13
AH16
VSS
VSS
AH17
VSSV3VSS
VSS
AH20
VSS
AH23
VSS
VSS
AH24
V27
AH3
VSS
VSS
V26
AH6
V25
VSS
VSS
AH7
MSID1 MSID0
V24
V23
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
VSS
AJ24
VSS
AJ27
VSS
AJ28
VSS
R30
AJ29
VSS
R29
AJ30
VSS
VSS
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
AN1
VSS
VSS
AN10
AN13
VSS
AN16
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
VSS
AN17
H28
AN2
VSS
VSS
VSS
VSS
AN20
VSS
VSS
AN23
AN24
VSS
VSS
VSS
VSS
AN27
VSS
VSS
AN28
VSS
VSS
VSS
VSSB1VSS
B11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZIF-SOCK775-15u-in
ZIF-SOCK775-15u-in
B14
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
VSS
AL17
VSS
AL20
VSS
AL23
VSS
AL24
VSS
AL27
VSS
L30
AL28
VSS
VSSL3VSS
VSS
AL3
L29
L28
L27
VSS
VSS
VSS
VSS
VSS
AL7
AM1
AM10
L26
VSS
VSS
AM13
L25
VSS
VSS
AM16
L24
VSS
VSS
AM17
L23
VSS
VSS
AM20
VSSK7VSS
VSS
AM23
K5
VSS
AM24
K2
VSS
AM27
VSS
AM28
VSS
AM4
A A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 - GND
Intel LGA775 - GND
Intel LGA775 - GND
MS-7187M1
MS-7187M1
MS-7187M1
2
1A
1A
835Tuesday, November 01, 2005
835Tuesday, November 01, 2005
835Tuesday, November 01, 2005
1
1A
of
of
of
5
4
3
2
1
VREG_12V_POWER
R9
5.6KRR95.6KR
ENLL
R13 1KRR13 1KR
Q1
Q1
VID[0..5]6
R8 2.2KRR8 2.2KR
X_C560P50XC6 X_C560P50XC6
R18 100RR18 100R
R17 100RR17 100R
R4 200KRR4 200KR
R5 X_47KRR5 X_47KR
R25
R25
X_1.65KR1%
X_1.65KR1%
C17 C0.047U16XC17 C0.047U16X
5
R12 10KRR12 10KR
C2 C2200P16XC2 C2200P16X
COP
X_C10P50NC3 X_C10P50NC3
R7 X_750RR7 X_750R
C9 X_C1000P50XC9 X_C1000P50X
X_C0.1U25Y
X_C0.1U25Y
R16 100KR1%R16 100KR1%
C5 C0.01U50XC5 C0.01U50X
R21 2.2KRR21 2.2KR
VCCP
R26 _30KR1%-1R26 _30KR1%-1
VID_GD# 7,32
VID4
VID3
VID2
VID1
VID0
VID5
ENLL
COMP
FB
VDIFF
C8
C8
OFS
FS
REF
C18
C18
X_C0.01U50X
X_C0.01U50X
U2
U2
ISL6566CRZ_QFN40
ISL6566CRZ_QFN40
38
VID4
39
VID3
40
VID2
1
VID1
2
VID0
3
DACSEL/VID5
35
PGOOD
37
ENLL
8
COMP
9
FB
10
VDIFF
12
VSEN
11
RGND
6
OFST
36
FS
5
REF
4
VRM10
13
OCSET
14
ICOMP
15
ISUM
16
IREF
C20
C20
C0.01U50X
C0.01U50X
R29 24.3KR1%R29 24.3KR1%
R37 24.3KR1%R37 24.3KR1%
R45 24.3KR1%R45 24.3KR1%
D D
C C
VCC_VRM_SENSE6
VSS_VRM_SENSE6
B B
Close low side
mosfet
X_4.7KRT
X_4.7KRT
A A
VRM_GD21,32
N-MMBT3904_NL_SOT23
N-MMBT3904_NL_SOT23
R1 15KRR1 15KR
VCCP
VCC5
R24 0RR24 0R
R33
R33
VCC5
R3
4.7R0805R34.7R0805
C4
C4
C4.7U10Y0805
C4.7U10Y0805
7
VCC
GND
41
33
PVCC1
BOOT1
UGATE1
PHASE1
ISEN1
LGATE1
PVCC2
BOOT2
UGATE2
PHASE2
ISEN2
LGATE2
PVCC3
BOOT3
UGATE3
PHASE3
ISEN3
LGATE3
BOTTOM PAD CONNECT TO GND
THROUGH 10 vias
PHASE1
PHASE2
PHASE3
BOOT1
30
U_G1
31
PHASE1
29
R27 2.4KR1%R27 2.4KR1%
32
L_G1
34
24
BOOT2
26
U_G2
27
PHASE2
28
R49 2.4KR1%R49 2.4KR1%
25
L_G2
23
18
BOOT3
21
U_G3
20
PHASE3
22
R35 2.4KR1%R35 2.4KR1%
19
L_G3
17
4
R40 2.2R0805R40 2.2R0805
R41 2.2R0805R41 2.2R0805
R36 2.2R0805R36 2.2R0805
C14 C1U16Y0805C14 C1U16Y0805
12VP1
R32 4.7R0805R32 4.7R0805
C23
C23
C0.1U25Y
C0.1U25Y
C22 C1U16Y0805C22 C1U16Y0805
12VP2
R52 4.7R0805R52 4.7R0805
C24
C24
C0.1U25Y
C0.1U25Y
C21 C1U16Y0805C21 C1U16Y0805
12VP3
R39 4.7R0805R39 4.7R0805
C27
C27
C0.1U25Y
C0.1U25Y
VREG_12V_POWER
VREG_12V_POWER
VREG_12V_POWER
+12VP_FET
EC38
EC38
+
+
12
CD1000U16EL20-1
CD1000U16EL20-1
U_G1
R48
R48
PHASE1
10KR
10KR
L_G1
R361
R361
X_10KR
X_10KR
U_G2
R368
R368
10KR
10KR
L_G2
R369
R369
X_10KR
X_10KR
R112
R112
10KR
10KR
L_G3
R370
R370
X_10KR
X_10KR
3
U_G3
N-P70N02LR_TO252
N-P70N02LR_TO252
PHASE2
N-P70N02LR_TO252
N-P70N02LR_TO252
PHASE3
VCCP VCCPVCCP
VREG_12V_POWER
CD1000U16EL20-1
CD1000U16EL20-1
N-P60N03LR_TO252
N-P60N03LR_TO252
R51
R51
1R0805
1R0805
CD1000U16EL20-1
CD1000U16EL20-1
N-P60N03LR_TO252
N-P60N03LR_TO252
R101
R101
1R0805
1R0805
CD1000U16EL20-1
CD1000U16EL20-1
N-P60N03LR_TO252
N-P60N03LR_TO252
R115
R115
1R0805
1R0805
N-P70N02LR_TO252
N-P70N02LR_TO252
EC12
EC12
C10U10Y1206
C10U10Y1206
EC11
EC11
X_C10U10Y1206
X_C10U10Y1206
EC20
EC20
C10U10Y1206
C10U10Y1206
EC14
EC14
X_C10U10Y1206
X_C10U10Y1206
EC26
EC26
X_C10U10Y0805
X_C10U10Y0805
C0.01U50X
C0.01U50X
EC22
EC22
UG1
G
Q2
Q2
G
Q3
Q3
EC34
EC34
UG2
G
Q10
Q10
G
Q11
Q11
EC23
EC23
UG3
G
Q14
Q14
G
Q17
Q17
C97
C97
+12VP_FET
12
+
+
DS
DS
+12VP_FET
+
+
12
DS
DS
+12VP_FET
+
+
12
DS
DS
JPW1
JPW1
3
12V
4
12V
PWR-2X2M_white-4.2pitch-RH
PWR-2X2M_white-4.2pitch-RH
C66 C4.7U35Y1206C66 C4.7U35Y1206
C99 C1U16Y0805C99 C1U16Y0805
G
Q5
Q5
G
C40 C4.7U35Y1206C40 C4.7U35Y1206
C30 C1U16Y0805C30 C1U16Y0805
G
Q12
Q12
G
Q13
Q13
C69 C4.7U35Y1206C69 C4.7U35Y1206
C46 C1U16Y0805C46 C1U16Y0805
G
Q16
Q16
G
Q15
Q15
N-P70N02LR_TO252
N-P70N02LR_TO252
EC10
EC10
X_C10U10Y1206
X_C10U10Y1206
EC32
EC32
X_C10U10Y1206
X_C10U10Y1206
EC21
EC21
C10U10Y1206
C10U10Y1206
EC29
EC29
X_C10U10Y0805
X_C10U10Y0805
EC30
EC30
C10U10Y1206
C10U10Y1206
EC33
EC33
X_C10U10Y1206
X_C10U10Y1206
1
GND
2
GND
COIL4
COIL4
CH-1.2U18A-LF
CH-1.2U18A-LF
DS
N-P60N03LR_TO252
N-P60N03LR_TO252
DS
R73
R73
C41
C41
Q6
Q6
C1000P50X
C1000P50X
N-P70N02LR_TO252
N-P70N02LR_TO252
DS
N-P60N03LR_TO252
N-P60N03LR_TO252
DS
R102
R102
2.2R0805
2.2R0805
C54
C54
C1000P50X
C1000P50X
N-P70N02LR_TO252
N-P70N02LR_TO252
DS
N-P60N03LR_TO252
N-P60N03LR_TO252
DS
R124
R124
2.2R0805
2.2R0805
C91
C91
C1000P50X
C1000P50X
EC18
EC18
X_C10U10Y1206
X_C10U10Y1206
EC16
EC16
X_C10U10Y1206
X_C10U10Y1206
EC19
EC19
X_C10U10Y1206
X_C10U10Y1206
EC17
EC17
X_C10U10Y1206
X_C10U10Y1206
EC25
EC25
X_C10U10Y1206
X_C10U10Y1206
2
2.2R0805
2.2R0805
VREG_12V_POWER
C104
C104
X_C4.7U35Y1206
X_C4.7U35Y1206
COIL1
COIL1
CH-0.6U40A-RH-1
CH-0.6U40A-RH-1
HS1
HS1
HS-MS7033-RH
HS-MS7033-RH
112
2
MOSFET Heatsinks
COIL2
COIL2
CH-0.6U40A-RH-1
CH-0.6U40A-RH-1
HS2
HS2
HS-MS7033-RH
HS-MS7033-RH
112
2
COIL3
COIL3
CH-0.6U40A-RH-1
CH-0.6U40A-RH-1
HS3
HS3
HS-MS7033-RH
HS-MS7033-RH
112
2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
MSI
VCCP
EC62
EC62
+
+
1 2
C100U2SP-LF
C100U2SP-LF
EC61
EC61
+
+
1 2
X_C100U2SP-LF
X_C100U2SP-LF
EC24
EC24
+
+
1 2
C100U2SP-LF
VCCP
VCCP
VCCP
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
VRM10.1 Intersil 6566 3Phase
VRM10.1 Intersil 6566 3Phase
VRM10.1 Intersil 6566 3Phase
C100U2SP-LF
EC63
EC63
+
+
1 2
C100U2SP-LF
C100U2SP-LF
EC5
EC5
+
+
1 2
CD680U4EL8
CD680U4EL8
EC2
EC2
+
+
1 2
CD1800U6.3EL20-2
CD1800U6.3EL20-2
EC4
EC4
+
+
1 2
CD680U4EL8
CD680U4EL8
EC8
EC8
+
+
1 2
CD680U4EL8
CD680U4EL8
+
+
1 2
CD1800U6.3EL20-2
CD1800U6.3EL20-2
EC13
EC13
+
+
1 2
CD680U4EL8
CD680U4EL8
EC3
EC3
+
+
1 2
CD680U4EL8
CD680U4EL8
EC6
EC6
+
+
1 2
CD680U4EL8
CD680U4EL8
EC9
EC9
+
+
1 2
CD680U4EL8
CD680U4EL8
EC31
EC31
+
+
1 2
CD680U4EL8
CD680U4EL8
EC35
EC35
+
+
1 2
CD1800U6.3EL20-2
CD1800U6.3EL20-2
EC7
EC7
+
+
1 2
CD680U4EL8
CD680U4EL8
MS-7187M1
MS-7187M1
MS-7187M1
1
EC1
EC1
1A
1A
935Tuesday, November 01, 2005
935Tuesday, November 01, 2005
935Tuesday, November 01, 2005
1A
of
of
of
8
H_A#[3..31]6
D D
H_ADSTB#06
H_ADSTB#16
C C
B B
PLTRST#20,24,29
ICH_SYNC#21
R142 16.9R1%R142 16.9R1%
H_BR#06,7
H_BPRI#6
H_BNR#6
H_LOCK#6
H_ADS#6
H_REQ#[0..4]6
H_HIT#6
H_HITM#6
H_DEFER#6
H_TRDY#6
H_DBSY#6
H_DRDY#6
H_RS#[0..2]6
CK_H_MCH19
CK_H_MCH#19
PWR_GD21,32
H_CPURST#6,7
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
7
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
AF6
VCC
RSVRD
AA34
VCC
RSVRD
L15
AA38
VCC
VCC
RSVRD
RSVRD
M15
VCC
RSVRD
U27
R27
AF7
VCC
RSVRD
A43
U6A
U6A
H_A#3 H_D#0
J39
HA3#
H_A#4
K38
HA4#
VCC
VCC
VCC
VCC
VCC
RSVRD
AA35
VCC
RSVRD
AA42
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
M34
M38
AA37
M36
AA41
W42
G37
W41
W40
M31
M29
AJ12
M18
J42
K35
J37
N35
R33
N32
N34
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
V35
F38
D42
U39
U40
E41
D41
K36
E42
U41
P40
U42
V41
Y40
T40
Y43
T43
AJ9
C30
A28
C27
B27
D27
D28
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
AF8
VCC
VCC
RSVRD
RSVRD
M11
AF9
VCC
RSVRD
AG25
AF10
VCC
RSVRD
AG26
AF11
AF12
VCC
RSVRD
AJ24
AG27
6
AF13
VCC
VCC
RSVRD
RSVRD
AJ27
AF14
VCC
RSVRD
AK40
AF30
AG2
VCC
RSVRD
AL39
AW17
AG3
VCC
VCC
RSVRD
RSVRD
AW18
V_1P5_CORE
AG4
AG5
AG6
VCC
VCC
RSVRD
RSVRD
AY14
BC16
AD30
AG7
VCC
VCC
RSVRD
RSVRD
AC34
AG8
VCC
RSVRD
Y30
AG9
AG10
VCC
RSVRD
Y33
AF31
AG11
VCC
VCC
RSVRD
RSVRD
AD31
AG12
VCC
RSVRD
U30
AG13
AG14
VCC
RSVRD
V31
AA30
AH1
VCC
VCC
RSVRD
RSVRD
AC30
AH2
AH4
VCC
RSVRD
AJ23
AK21
AJ5
VCC
VCC
RSVRD
RSVRD
AJ26
AJ13
VCC
RSVRD
AL29
AJ14
VCC
RSVRD
AL20
5
AK2
VCC
RSVRD
AJ21
AK3
AK4
VCC
RSVRD
AL26
AK27
AK14
VCC
VCC
RSVRD
RSVRD
AJ29
AK15
VCC
RSVRD
AG29
AK20
R15
VCC
RSVRD
V30
R17
VCC
BC43NCBC42
VCC
NC
4
R18
R20
R21
R23
R24
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
NC
NC
NC
NC
NC
NC
NC
NC
NCC2NC
NCB3NCB2NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E35
B43NCB42NCB41
A42
Y17
Y18
Y19
Y21
Y23
Y25
BC2NCBC1
BB43
BB2NCBB1NCBA2
C42
AW2
AV27NCAV26
AW26
Y27
AA15
AA17
AA18
W24
VCC
VCC
AA19
W26
VCC
VCC
AA20
W27
Y15
M17
VCC
VCC
VCC
KDINV_0#
HDINV_1#
HDINV_2#
HDINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
3
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
Lakeport
Lakeport
V_1P5_CORE
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
K40
A38
E29
B32
K41
L43
F35
G34
J27
M26
E34
B37
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 6
H_DSTBN#0 6
H_DSTBP#1 6
H_DSTBN#1 6
H_DSTBP#2 6
H_DSTBN#2 6
H_DSTBP#3 6
H_DSTBN#3 6
2
H_D#[0..63] 6
U6_X1
U6_X1
H_DBI#[0..3] 6
X5
X6
X7
X8
MCH
MCH
Heatsink
Heatsink
MCH_HS
MCH_HS
1
X1
X2
X3
X4
R146
V_FSB_VTT
A A
R146
60.4R1%
60.4R1%
HXSCOMP
C122
C122
X_C2.2P50N
X_C2.2P50N
V_FSB_VTT
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
PLACE DIVIDER RESISTOR NEAR VTT
R143
R143
301R1%
301R1%
R145
R145
84.5R1%
84.5R1%
R144 62RR144 62R
C121
C121
C0.01U50X
C0.01U50X
HXSWING
V_FSB_VTT
R141
R141
124R1%
124R1%
R139
R139
210R1%
210R1%
CAPS SHOULD BE PLACED NEAR MCH PIN
8
7
6
5
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
MCH_GTLREF
C115
C115
C0.1U25Y
C0.1U25Y
C117
C117
X_C220P50N
X_C220P50N
R135 0RR135 0R
4
MCH_GTLREF_CPU 6
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU
Intel Lakeport - CPU
Intel Lakeport - CPU
MS-7187M1
MS-7187M1
MS-7187M1
2
1A
1A
10 35Tuesday, November 01, 2005
10 35Tuesday, November 01, 2005
10 35Tuesday, November 01, 2005
1
1A
of
of
of
8
7
6
5
4
3
2
1
DATA_A37
DATA_A38
AT32
AR34
SADQ36
SADQ37
SADQ38
SBDQ34
SBDQ35
SBDQ36
AP27
AM31
DATA_B35
DATA_B36
DATA_A40
DATA_A39
AU37
AR41
SADQ39
SBDQ37
AP31
AR27
DATA_B37
DATA_B38
DATA_A41
DATA_A42
AR42
AN43
SADQ40
SADQ41
SBDQ38
SBDQ39
AP35
AU31
DATA_B40
DATA_B39
SCKE_A[0..3]14,16
DATA_A43
DATA_A44
AM40
AU41
SADQ42
SADQ43
SBDQ40
SBDQ41
AP37
AN32
DATA_B42
DATA_B41
5
DATA_A45
DATA_A46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
DATA_B43
DATA_B44
DATA_A48
DATA_A47
AN40
AL41
SADQ46
SADQ47
SBDQ44
SBDQ45
AU38
AM38
DATA_B46
DATA_B45
DATA_A49
DATA_A50
AL42
AF39
SADQ48
SADQ49
SBDQ46
SBDQ47
AL34
AM34
DATA_B47
DATA_B48
DATA_A51
SADQ50
SBDQ48
DATA_B49
DATA_A[0..63]14
DATA_A16
DATA_A21
DATA_A6
DATA_A4
AN1
SADQ3
SADQ4
SBDQ1
SBDQ2
AP8
DATA_B2
DATA_A5
AP4
SADQ5
SBDQ3
AP9
DATA_B3
AU5
SADQ6
SBDQ4
AJ11
DATA_B4
DATA_A7
AU2
SADQ7
SBDQ5
AL9
DATA_B5
DATA_A8
AW3
SADQ8
SBDQ6
AM10
DATA_B6
DATA_A9
AY3
SADQ9
SBDQ7
AP6
DATA_B7
DATA_A10
DATA_A11
BA7
BB7
SADQ10
SBDQ8
AV6
AU7
DATA_B8
DATA_B9
DATA_A12
DATA_A13
AV1
AW4
SADQ11
SADQ12
SBDQ9
SBDQ10
AV12
AM11
DATA_B11
DATA_B10
DATA_A14
DATA_A15
BC6
AY7
SADQ13
SADQ14
SBDQ11
SBDQ12
AR5
AR7
DATA_B12
DATA_B13
DATA_A17
AW12
AY10
SADQ15
SADQ16
SBDQ13
SBDQ14
AR12
AR10
DATA_B14
DATA_B15
DATA_A0
DATA_A1
DATA_A3
D D
C C
B B
A A
SCS_A#[0..3]14,16
MAA_A[0..13]14,16
ODT_A[0..3]14,16
SBS_A[0..2]14,16
R194 80.6R1%R194 80.6R1%
VCC_DDR
R193 80.6R1%R193 80.6R1%
C183
C183
C0.1U25Y
C0.1U25Y
U6B
BB37
BA39
BA35
AY38
BA34
BA37
BB35
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
AW37
AY39
AY37
BB40
BC33
AY34
BA26
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
BB32
AY32
AK42
AK41
BA31
BB31
AH40
AH43
AU4
AR2
BA3
BB4
AY5
BB5
AY6
BA5
AM3
AL5
AJ6
AJ8
DATA_B[0..63]15
U6B
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACLK0
SACLK0#
SACLK1
SACLK1#
SACLK2
SACLK2#
SACLK3
SACLK3#
SACLK4
SACLK4#
SACLK5
SACLK5#
MCH_SRCOMP0
MCH_SRCOMP1
SMOCDCOMP0
SMOCDCOMP1
Lakeport
Lakeport
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#14,16
CAS_A#14,16
WE_A#14,16
DQS_A014
DQS_A#014
DQS_A114
DQS_A#114
DQS_A214
DQS_A#214
DQS_A314
DQS_A#314
DQS_A414
DQS_A#414
DQS_A514
DQS_A#514
DQS_A614
DQS_A#614
DQS_A714
DQS_A#714
P_DDR0_A14
N_DDR0_A14
P_DDR1_A14
N_DDR1_A14
P_DDR2_A14
N_DDR2_A14
P_DDR3_A14
N_DDR3_A14
P_DDR4_A14
N_DDR4_A14
P_DDR5_A14
N_DDR5_A14
8
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SMPCOMP_N
SMPCOMP_P MCH_VREF_AMCH_VREF_B
SMPCOMP_P
SMPCOMP_N
DATA_A2
AP3
AP2
AU3
AV4
SADQ0
SADQ1
SADQ2
SBDQ0
AL6
AL8
DATA_B0
DATA_B1
7
DATA_A18
DATA_A19
BA12
BB12
SADQ17
SADQ18
SBDQ15
SBDQ16
AM15
AM13
DATA_B17
DATA_B16
DATA_A20
BA9
BB9
SADQ19
SADQ20
SBDQ17
SBDQ18
AV15
AM17
DATA_B18
DATA_B19
6
DATA_A22
DATA_A23
BC11
AY12
SADQ21
SADQ22
SBDQ19
SBDQ20
AN12
AR13
DATA_B21
DATA_B20
DATA_A24
DATA_A25
AM20
AM18
SADQ23
SADQ24
SBDQ21
SBDQ22
AT15
AP15
DATA_B23
DATA_B22
DATA_A26
DATA_A27
AV20
AM21
SADQ25
SADQ26
SBDQ23
SBDQ24
AM24
AM23
DATA_B24
DATA_B25
DATA_A29
DATA_A28
AP17
AR17
SADQ27
SADQ28
SBDQ25
SBDQ26
AV24
AM26
DATA_B27
DATA_B26
DATA_A31
DATA_A30
AP20
AT20
SADQ29
SADQ30
SBDQ27
SBDQ28
AP21
AR21
DATA_B28
DATA_B29
DATA_A32
DATA_A33
AP32
AV34
SADQ31
SADQ32
SBDQ29
SBDQ30
AT24
AP24
DATA_B31
DATA_B30
DATA_A34
DATA_A35
AV38
AU39
SADQ33
SADQ34
SBDQ31
SBDQ32
AU27
AN29
DATA_B32
DATA_B33
DATA_A36
AV32
SADQ35
SBDQ33
AR31
DATA_B34
DATA_A52
AE40
AM41
SADQ51
SADQ52
SBDQ49
SBDQ50
AJ34
AF32
DATA_B50
DATA_A53
DATA_A54
AM42
AF41
SADQ53
SBDQ51
AL31
AF34
DATA_B52
DATA_B51
SCKE_B[0..3]15,16
DATA_A56
DATA_A55
AF42
AD40
SADQ54
SADQ55
SBDQ52
SBDQ53
AJ32
AG35
DATA_B54
DATA_B53
DQM_A[0..7]14
DATA_A57
DATA_A58
AD43
AA39
SADQ56
SADQ57
SBDQ54
SBDQ55
AD32
AC32
DATA_B55
DATA_B56
DQM_B[0..7]15
DATA_A60
DATA_A59
AA40
AE42
SADQ58
SADQ59
SBDQ56
SBDQ57
Y32
AD34
DATA_B57
DATA_B58
DATA_A61
DATA_A62
AE41
AB41
SADQ60
SADQ61
SBDQ58
SBDQ59
AF35
AA32
DATA_B60
DATA_B59
DATA_A63
AB42
SADQ62
SADQ63
SBDQ60
SBDQ61
AF37
AC33
DATA_B61
DATA_B62
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SBDQ62
SBDQ63
AC35
DATA_B63
4
SCKE_A3
SCKE_A2
BC24
BA25
SACKE1
SACKE2
SBCKE0
BA14
AY16
SCKE_B0
SCKE_B1
SACKE3
SBCKE1
SBCKE2
BA13
BB13
SCKE_B3
SCKE_B2
DQM_A1
DQM_A0
AY2
AR3
SADM0
SBCKE3
AD39
DQM_B7
DQM_A2
BB10
SADM2
SADM1
SBDM6
SBDM7
AJ39
DQM_B6
DQM_A3
AP18
SADM3
SBDM5
AR38
DQM_B5
DQM_A4
AT34
SADM4
SBDM4
AR29
DQM_B4
DQM_A5
AP39
AP23
DQM_B3
DQM_A6
AG40
SADM6
SADM5
SBDM2
SBDM3
AP13
DQM_B2
DQM_A7
AC40
SADM7
SBDM1
AW7
DQM_B1
DQM_B0
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1
SMVREF0
SBDM0
AL11
SCS_B#0
BA40
SCS_B#1
AW41
SCS_B#2
BA41
SCS_B#3
AW40
RAS_B#
BA23
CAS_B#
AY24
WE_B#
BB23
MAA_B0
BB22
MAA_B1
BB21
MAA_B2
BA21
MAA_B3
AY21
MAA_B4
BC20
MAA_B5
AY19
MAA_B6
AY20
MAA_B7
BA18
MAA_B8
BA19
MAA_B9
BB18
MAA_B10
BA22
MAA_B11
BB17
MAA_B12
BA17
MAA_B13MAA_A13
AW42
ODT_B0
AY42
ODT_B1
AV40
ODT_B2
AV43
ODT_B3
AU40
SBS_B0
AW23
SBS_B1
AY23
SBS_B2
AY17
DQS_B0
AM8
DQS_B#0
AM6
DQS_B1
AV7
DQS_B#1
AR9
DQS_B2
AV13
DQS_B#2
AT13
DQS_B3
AU23
DQS_B#3
AR23
DQS_B4
AT29
DQS_B#4
AV29
DQS_B5
AP36
DQS_B#5
AM35
DQS_B6
AG34
DQS_B#6
AG32
DQS_B7
AD36
DQS_B#7
AD38
P_DDR0_B
AM29
N_DDR0_B
AM27
P_DDR1_B
AV9
N_DDR1_B
AW9
P_DDR2_B
AL38
N_DDR2_B
AL36
P_DDR3_B
AP26
N_DDR3_B
AR26
P_DDR4_B
AU10
N_DDR4_B
AT10
P_DDR5_B
AJ38
N_DDR5_B
AJ36
AM2
MCH_VREF_A
AM4
PLACE 0.1UF CAP CLOSE TO MCH
3
SCS_B#[0..3] 15,16
RAS_B# 15,16
CAS_B# 15,16
WE_B# 15,16
MAA_B[0..13] 15,16
ODT_B[0..3] 15,16
SBS_B[0..3] 15,16
DQS_B0 15
DQS_B#0 15
DQS_B1 15
DQS_B#1 15
DQS_B2 15
DQS_B#2 15
DQS_B3 15
DQS_B#3 15
DQS_B4 15
DQS_B#4 15
DQS_B5 15
DQS_B#5 15
DQS_B6 15
DQS_B#6 15
DQS_B7 15
DQS_B#7 15
P_DDR0_B 15
N_DDR0_B 15
P_DDR1_B 15
N_DDR1_B 15
P_DDR2_B 15
N_DDR2_B 15
P_DDR3_B 15
N_DDR3_B 15
P_DDR4_B 15
N_DDR4_B 15
P_DDR5_B 15
N_DDR5_B 15
C179
C179
C0.1U25Y
C0.1U25Y
VCC_DDR
C178
PLACE 0.1UF CAP CLOSE TO MCH
R199 1KR1%R199 1KR1%
R196
R196
1KR1%
1KR1%
MSI
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
2
C178
C0.1U25Y
C0.1U25Y
CP3
CP3
X_COPPER
X_COPPER
R198 X_0RR198 X_0R
MCH_VREF_A
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - Memory
Intel Lakeport - Memory
Intel Lakeport - Memory
MS-7187M1
MS-7187M1
MS-7187M1
MCH_VREF_B
11 35Tuesday, November 01, 2005
11 35Tuesday, November 01, 2005
11 35Tuesday, November 01, 2005
1
of
of
of
1A
1A
1A
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