MSI MS-7178 Schematics
1
COVER SHEET
BLOCK DIAGRAM
CLOCK Map/POWER Map
GPIO MAP
1
2
3
4
MS-7178
CPU:
Version 0A
Intel Prescott ( L2=2MB ) - 3.4G & Above
Intel LGA775-CPU
VRM10.1 Intersil 6566 3Phase
Intel Lakeport -GMCH
DDR II DIMM 1 / 2 / 3 / 4
PCI EXPRESS X16 & X1 SLOT
VGA CONNECTOR
5-7
8
9-12
13-15
16
17
Intel Cendar Mill (65nm) - 3.73G & Above
Intel Smithfield (90nm Dual core)
System Chipset:
Intel Lakeport - GMCH (North Bridge)
Intel ICH7 (South Bridge)
On Board Chipset:
Clock Generator - ICS954519
ICH7
PCI Slot 1 & 2 & 3
18
19-21
22
BIOS -- FWH FLASH 4Mb
AC97 ALC655 / Azalia ALC880/882
LPC Super I/O -- W83627EHF
A A
LAN RTL8110S(B)/8100C
FWH & USB CONNECTORS
23
24
LAN - RTL8110S(B)/8100C
Clock Generator - ICS954519
Audio Codec ALC655/880/882
SIO-W83627EHF & KB/MS
ATX,F_ PANEL,FAN CONTROL
IDE & SATA&COM&LPT
MS7 ACPI &SYSTEM Regulator
Auto BOM manual
History
25
26
27
28
29
30
31
Main Memory:
DDR II * 4 (Max 4GB)
Expansion Slots:
PCI Express X16 SLOT * 1
PCI Express X1 SLOT * 1
PCI 2.3 SLOT * 3
Intersil PWM:
Controller:
1
ISL6566CR_QFN40
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
COVER SHEET
MS-7178
131Thursday, May 26, 2005
of
0A
1
Block Diagram
VRM 10.1
Intersil 6565
3-Phase PWM
PCIRST#2
PCI
EXPRESS
P.28
VRM_GD
VTT_PWG
Intel LGA775 Processor
FSB
H_PWRGD
H_CPURST#
DDRII
P.3~5
4 DDR II
DIMM
Modules
PWR_GD
MS7
VID_GD
RSMRST#
HD_RST#
X16
Connector
HD_RST#
IDE Primary
SERIAL ATA1
SERIAL ATA2
A A
SERIAL ATA3
SERIAL ATA4
USB2.0
USB Port0~ 7
P.15
P.18
P.18
P.18
P.18
P.18
P.25
UltraDMA
33/66/100
USB
RSMRST#
VRM_GD
Lakeport
GMCH
DMI
ICH7
PWRBTN#
P.6~9
PLTRST#
P.10~12
PWR_GD
LPC Bus
266/333
MHz
SLP_S4#
SLP_S3#
PSON#
PLTRST#
PCIRST_ICH6#
PCI
ATX1
PWR_OK
PCIRST#1
PCI Slot 1
PCI Slot 2
P.23 P.23
LAN
RTL
8110S/8100C
PCI Slot 3
P.15
PCIRST#2
ALC 655/880/882
AC97/Azalia Codec
P.16
PCI
EXPRESS
X1
Connector
P.17
PCI EXPRESS
JFP1
LPC SIO
W83627EHF
P.14
FWH
P.30
FP_RST#FP_RST#
Keyboard
Mouse
PLTRST#
1
P.14
P.14
Floopy Parallel Serial
P.14 P.18 P.18
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
BLOCK DIAGRAM
MS-7178
231Thursday, May 26, 2005
of
0A
8
7
6
5
4
3
2
1
INTEL LAKEPORT PLATFORM CLOCK GENERATOR MAP
MCLK_1L0~2/
MCLK_1L#0~2
3.3V 5V 5VSB 12V
DDR CHA
D D
HOST CLK
CK_H_CPU/#
CPU CLK
CK_H_MCH/#
96 Mhz
CK_96M_DREF/#
Intel LGA775
Processor
Lakeport GMCH
DDR CLK
MCLK_1H0~2/
MCLK_1H#0~2
CK_PE_100M_MCH/#
DDR CHB
CLOCK GENERATOR
14.318 Mhz
14.318MHZ
CK_14M_ICH
INTEL LAKEPORT PLATFORM POWER DELIVERY MAP
OP 2.5V
VREG
VRM
MS7 VCC_VID
VREG
MS6+
1.5V VREG
PROCESSOR VCORE
PROCESSOR V_FSB_VTT
PCIE X16 & 1 SLOT
MCH V_1P05_CORE
MCH V_2P5_MCH
MCH VCC_DDR
S3
48 Mhz
C C
48MHZ
CK_48M_USB_ICH
ICH_PCLK
PCI_CLK 0~2
PCI CLK
25M Hz
GLAN_PCLK
CK_25M_LAN
ICH7
PCI Slot 1~3
Reltek LAN
8110S/8100C
CK_PE_100M_ICH/#
S0
S3
S0
MS7
3VSB
VREG
MS6+
1.8V VREG
VTT VREG
DDRII DIMM1-4 / 1.8V
DDRII VTT
ICH S0 Power V_1P05_CORE
ICH S0 Power V_FSB_VTT
ICH S0 Power VCC3
ICH S5 Power RESUME VCC3_SB
ICH S5 Power VCC5_SB
LAN
FWH_ PCLK
B B
SIO_PCLK
SIO_48MCLK
AC97_CLK
FWH
ROM
LPC SIO
Winbond
83627EHF
AC97/ALC 655
Lan 2.5VSB
VREG
Lan 1.8VSB
VREG
RTL 8100C VCC3_SB
RTL 8110S 2.5VSB
RTL 8110S 1.8VSB
FWH ROM 3.3V
LPC SUPER I/O 3.3V
100 MHz
CK_PE_100M_16PORT/#
CK_PE_100M_1PORT/#
PCIE X16 SLOT
PCIE X1 SLOT
AC97 VDD5
S3
VREG
CLK Gen. 3.3V
AC97 VDD5
USB Power
A A
CK_ICHSATA/#
8
7
SATA
6
5
S0
4
5VDUAL
VREG
MSI
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
Title
Size Document Number Rev
3
Date: Sheet
CLOCK Map/POWER M ap
2
MS-7178
0A
of
331Monday, May 30, 2005
1
8
7
6
5
4
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2
1
ICH7
GPIO Alt Func Pin I/O/NC Power PU SMI Tol Default Signal Name
GPIO[0] BM_BUSY# AB18 I/O Vcc3p3 N Y 5 Input strapped hi
GPIO[1] PCIREQ[5]# C8 I/O V5REF N Y 5 Input PREQ#5
GPIO[2] PIRQE# G8 I/OD V5REF N Y 5 Input PIRQ#E
GPIO[3] PIRQF# F7 I/OD V5REF N Y 5 Input PIRQ#F
GPIO[4] PIRQG# F8 I/OD V5REF N Y 5 Input PIRQ#G
D D
GPIO[5] PIRQH# G7 I/OD V5REF N Y 5 Input PIRQ#H
FWH
GPIO Pin# Power Tol Signal Name
FPGI[0] 6 Main 3.3 pull-down
FPGI[1] 5 Main 3.3 pull-down
FPGI[2] 4 Main 3.3 pull-down
FPGI[3] 3 Main 3.3 pull-down
FPGI[4] 30 Main 3.3 pull-downGPIO[6] unmuxed AC21 I/O Vcc3p3 N Y 3.3 Input JAUD2_EN
GPIO[7] unmuxed AC18 I/O Vcc3p3 N Y 3.3 Input strapped hi
GPIO[8] unmuxed E21 I/O VccSus3p3 N Y 3.3 Input strapped hi
PCI Config.
GPIO[9] unmuxed E20 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[10] unmuxed A20 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[11] SMBALERT# B23 I/O VccSus3p3 N Y 3.3 Input SMB_ALERT#
GPIO[12] unmuxed F19 I/O VccSus3p3 N Y 3.3 Input SIO_PME#
GPIO[13] unmuxed E19 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[14] unmuxed R4 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[15] unmuxed E22 I/O VccSus3p3 N Y 3.3 Input strapped hi
GPIO[16] unmuxed AC22 I/O Vcc3p3 N N 3.3 0 NC
GPIO[17] PCIGNT[5]# D8 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[18] unmuxed AC20 I/O Vcc3p3 N N 3.3 1 NC
GPIO[19] SATA1GP AH18 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[20] unmuxed AF21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[21] SATA0GP AF19 I/O Vcc3p3 N N 3.3 Input strapped hi
C C
GPIO[22] PCIREQ[4]# A13 I/O Vcc3p3 N N 3.3 Input PREQ#4
GPIO[23] LDRQ1# AA5 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[24] unmuxed R3 I/O VccSus3p3 N N 3.3 No Change LAN_DISABLE#
GPIO[25] unmuxed D20 I/O VccSus3p3 Y N 3.3 1 NC
GPIO[26] unmuxed A21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[27] unmuxed B21 I/O VccSus3p3 N N 3.3 0 NC
GPIO[28] unmuxed E23 I/O VccSus3p3 N N 3.3 0 FAN_CTRL
GPIO[29] OC5# C3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[30] OC6# A2 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[31] OC7# B3 I/O VccSus3p3 N N 3.3 Input OC#2
GPIO[32] unmuxed AG18 I/O Vcc3p3 N N 3.3 1 BIOS_WP#
GPIO[33] unmuxed AC19 I/O Vcc3p3 N N 3.3 1 NC
GPIO[34] unmuxed U2 I/O Vcc3p3 N N 3.3 0 NC
GPIO[35] unmuxed AD21 I/O Vcc3p3 N N 3.3 1 NC
GPIO[36] SATA2GP AH19 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[37] SATA3GP AE19 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[38] unmuxed AD20 I/O Vcc3p3 N N 3.3 Input strapped hi
B B
GPIO[39] unmuxed AE20 I/O Vcc3p3 N N 3.3 Input strapped hi
GPIO[48] GNT4# A14 I/O Vcc3p3 N N 3.3 N/A NC
GPIO[49] CPUPWRGD AG24 I/O V_CPU_IO N N CPU N/A H_PWRGD
Following are the GPIOs that need to be terminated properly if not used:
GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused.
GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused.
Note: FWH GPs should only be used for static options,
do not put dynamic nets on these
DEVICE
PCI1
PCI2
PCI3
LAN
MCP1 INT Pin
PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#B
PIRQ#E
REQ#/GNT#
PREQ#0
PGNT#0
PREQ#1
PGNT#1
PREQ#2
PREQ#2
PREQ#3
PGNT#3
IDSEL
AD16
AD17
AD18
AD19
CLOCK
PCI_CLK0
PCI_CLK1
PCI_CLK2
LAN_PCLK
DDRII DIMM Config.
DEVICE
DIMM 1
DIMM 2
DIMM 3
DIMM 4
ADDRESS
A0H
A2H
A4H
A6H
JUMPER SETTING
Open
(1-2)NORMAL
Chassis Intrision
Normal
Chassis Open
JBAT1
JCI1
(1-2)
CLOCK
P_DDR0_A/N_DDR0_A
P_DDR1_A/N_DDR1_A
P_DDR2_A/N_DDR2_A
P_DDR3_A/N_DDR3_A
P_DDR4_A/N_DDR4_A
P_DDR5_A/N_DDR5_A
P_DDR0_B/N_DDR0_B
P_DDR1_B/N_DDR1_B
P_DDR2_B/N_DDR2_B
P_DDR3_B/N_DDR3_B
P_DDR4_B/N_DDR4_B
P_DDR5_B/N_DDR5_B
(2-3)CLEAR
SIO W83627EHF
PIN NAME NOTES
GPIO33
GPIO45
A A
GPIO35
GPIO50
71 OUTPUT ODGPIO43
89
69
86
110
USAGE
NA
NA
NA
NA
NA
Input/OutputPIN#
OUTPUT OD
OUTPUT OD
OUTPUT OD
OUTPUT
Title
Size Document Number Rev
8
7
6
5
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3
Date: Sheet
2
GPIO MAP
MS-7178
431Thursday, May 26, 2005
1
0A
of
MICRO-STAR INt'L CO ., L TD.
MSI
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
8
7
6
5
4
3
2
1
R56 X__1KR0402-1
AC2
DBR#
D14#
C12
B12D8C11
AN3
AN4
VSS_SENSE
VCC_SENSE
D13#
D12#
D11#
VCC_VRM_SENSE
VSS_VRM_SENSE
TP1
OK OK
VID5
AN5
AN6
AJ3
AK3
AM5
AL4
AM7
RSVD
VID6#
ITP_CLK1
ITP_CLK0
VSS_MB_REGULATION
VCC_MB_REGULATION
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
B10
A11
A10A7B7B6A5C6A4C5B4
VID4
AK4
VID5#
VID4#
VID_SELECT
GTLREF_SEL
CS_GTLREF
LINT0/INTR
D2#
D1#
CPU SIGNAL BLOCK
H_A#30
AG4
F21
H_A#29
AG6
A30#
A29#
D43#
D42#
E21
H_A#28
H_A#27
AF4
AF5
A28#
D41#
F20
E19
ok
H_A#24
H_A#26
AB4
A27#
D40#
E18
H_A#19
H_A#22
H_A#23
A26#
D39#
H_A#25
AC5
F18
AB5
A25#
D38#
F17
H_A#17
H_A#20
H_A#18
H_A#21
H_A#16
AA5
AD6
AA4Y4Y6W6AB6W5V4V5U4U5T4U6T5R4M4L4M5P6L5
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
A16#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
G17
G18
E16
E15
G16
G15
F15
G14
H_A#15
A15#
D28#
F14
H_A#14
H_A#13
A14#
D27#
G13
E13
H_A#12
A13#
A12#
D26#
D25#
D13
H_A#10
H_A#11
A11#
D24#
F12
F11
H_A#9
A10#
D23#
A9#
D22#
D10
H_A#6
H_A#8
H_A#5
H_A#4
H_A#7
H_A#3
A8#
A7#
A6#
A5#
A4#
A3#
D21#
D20#
D19#
D18#
D17#
D16#
E10D7E9F9F8G9D11
D15#
D D
H_INIT#19
H_LOCK#9
H_HIT#9
H_BPRI#9
H_A20M#19
R67 X_62R0402
H_TESTHI13VTT_OUT_LEFT
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TMS
H_TRST#
H_TCK
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
ok
H_DBI#[0..3]9
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
C C
B B
ok
ok
ok
ok
ok
ok
ok
ok
OK
OK
OK
OK
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
OK
OK
OK
No
ok
ok
H_IERR#6
H_FERR#6,19
H_STPCLK#19
H_DBSY#9
H_DRDY#9
H_TRDY#9
H_ADS#9
H_BNR#9
H_HITM#9
H_DEFER#9
THERMDA_CPU26
THERMDC_CPU26
TRMTRIP#19
H_PROCHOT#6
H_IGNNE#19
ICH_H_SMI#19
R100 _62R0402
VTT_OUT_RIGHT
H_FSBSEL06,11,18
H_FSBSEL16,11,18
H_FSBSEL26,11,18
H_PWRGD6,19
H_CPURST#6,9
H_D#[0..63]9
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
H_A#[3..31]9
U5A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
B15
D53#
H_A#31
AJ6
AJ5
AH5
AH4
AG5
A35#
A34#
A33#
A32#
A31#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
C14
C15
A14
D17
D20
G22
D22
E22
G21
EC14 C10U10Y1206
VID2
VID0
VID1
VID3
AL6
AM3
AL5
AM2
VID3#
VID2#
VID1#
VID0#
GTLREF0
GTLREF1
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
RSVD
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
D0#
_ZIF-SOCK775-15u
FP_RST# 20,27
VCC_VRM_SENSE 8
VSS_VRM_SENSE 8
VID[0..5] 8
R11 _62R0402
AN7
H1
H2
TP_GTLREF_SEL
H29
MCH_GTLREF_CPU
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
H_TESTHI9
G4
H_TESTHI8
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
RSVD_AK6
AK6
RSVD_G6
G6
G28
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
U3
U2
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
OK
OK
OK
OK
CPU_GTLREF0
CPU_GTLREF1
OK
OK
OK
OK
OK
H_REQ#[0..4] 9
RN7 8P4R-62R0402
1 2
3 4
5 6
7 8
R96 _62R0402
R139 _62R0402
R74 _62R0402
R136 _62R0402
R12 X__62R0402
R101 X__62R0402
CK_H_CPU# 18
CK_H_CPU 18
H_RS#[0..2] 9
RN8 8P4R-62R0402
1 2
3 4
5 6
7 8
R83 _62R0402
R141 _62R0402
TP2
TP6
TP5
TP3
H_ADSTB#1 9
H_ADSTB#0 9
H_DSTBP#3 9
H_DSTBP#2 9
H_DSTBP#1 9
H_DSTBP#0 9
H_DSTBN#3 9
H_DSTBN#2 9
H_DSTBN#1 9
H_DSTBN#0 9
H_NMI 19
H_INTR 19
CPU_GTLREF0 6
CPU_GTLREF1 6
TP4
MCH_GTLREF_CPU 9
ok
ok
VTT_OUT_LEFT
V_FSB_VTT
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
OK
OK
OK
OK
OKok
OK
OK
OK
OK
OK
OK
OK
OK
VTT_OUT_RIGHT 6,7
H_BR#0 6,9
VTT_OUT_LEFT 6
C49
X_C0.1U16Y0402
ok
OK
OK
OK
OK
OK
OK
VTT_OUT_RIGHT
C16 C0.1U16Y0402
C13 C0.1U16Y0402
BSEL
02
1
0
01 200 MHZ (800)
1
0 0 133 MHZ (533)
Prescott / Cedar Mill
LL_ID[1:0] = 00
GTLREF_SEL = 0
VTT_SEL = 1
VID2
ok
OK
OK
OK
OK
OK
OK
1
VID4
3
VID3
5
VID1
7
R66 680R0402
VID0
R17 680R0402
VID5
RN2 8P4R-51R0402
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
RN4 8P4R-51R0402
R28 _62R0402
R45 _62R0402
PLACE BPM TERMINATION NEAR CPU
TABLE
FSB FREQUENCY
267 MHZ (1067)000
RN1
8P4R-680R
2
4
6
8
VTT_OUT_RIGHT
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TMS
H_TDI
H_BPM#2
H_BPM#4
H_TRST#
H_TCK
OK
OK
OK
OK
OK
OK
OK
OK
OKOK
OK
OK
H_D#36
H_D#49
H_D#50
H_D#48
H_D#47
H_D#46
H_D#45
H_D#44
H_D#43
H_D#42
H_D#41
H_D#40
H_D#39
H_D#38
H_D#37
H_D#53
H_D#52
A A
H_D#51
ok
8
7
H_D#34
H_D#35
6
H_D#33
H_D#32
H_D#30
H_D#31
H_D#29
H_D#28
H_D#26
H_D#27
H_D#25
H_D#24
H_D#22
H_D#23
H_D#21
H_D#20
H_D#19
H_D#18
H_D#16
H_D#17
H_D#15
H_D#14
H_D#12
H_D#13
5
H_D#11
H_D#10
H_D#8
H_D#9
H_D#7
H_D#6
H_D#4
H_D#5
H_D#2
H_D#3
H_D#0
H_D#1
MSI
Title
Size Document Number Rev
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
Intel LGA775 - Signals
MS-7178
2
531Thursday, June 02, 2005
of
1
0A
8
VCCP
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCCP
U5B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W30W8Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y8
VCCP
D D
C C
AG22
VCC
VCC
W29
AG25
VCC
VCC
W28
AG26
VCC
VCC
W27
AG27
VCC
VCC
W26
AG28
VCC
VCC
W25
AG29
VCC
VCC
W24
7
AG30
VCC
VCC
W23
AG8
VCC
VCC
AG9
VCC
VCC
AH11
VCC
VCC
U30U8V8
AH12
VCC
VCC
U29
AH14
U28
VCC
VCC
AH15
VCC
VCC
U27
AH18
U26
VCC
VCC
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
VCC
AH25
VCC
VCC
AH26
VCC
VCC
T30T8U23
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
T27
VCC
VCC
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
AJ11
VCC
VCC
AJ12
VCC
VCC
AJ14
VCC
VCC
AJ15
VCC
VCC
6
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
M24
M25
M26
M27
M28
M29
M30M8N23
N24
N25
N26
N27
N28
N29
N30N8P8R8T23
VCC
VCC
AK25
VCC
VCC
M23
AK26
VCC
VCC
5
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J22
J23
J24
J25
J26
J27
J28
J29
J30J8J9
K23
K24
K25
K26
K27
K28
K29
K30K8L8
AM18
VCC
VCC
J21
AM19
VCC
VCC
J20
AM21
VCC
VCC
J19
AM22
VCC
VCC
J18
AM25
VCC
VCC
J15
AM26
VCC
VCC
J14
4
AM29
VCC
VCC
J13
AM30
VCC
VCC
J12
AM8
J11
VCC
VCC
AM9
VCC
VCC
J10
AN11
VCC
VCC
AN9
AN12
VCC
VCC
AN8
AN14
AN15
AN18
AN19
VCC
VCC
VCC
VCC
VTT_OUT_RIGHT
VTT_OUT_LEFT
VCC
VCC
VCC
VCC
AN25
AN26
AN29
AN30
AN21
AN22
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTTPWRGD
VTT_SEL
RSVD
HS1
HS2
123
HS3
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
HS4
4
3
H_VCCA
A23
H_VSSA
B23
D23
H_VCCABB
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
F27
F29
_ZIF-SOCK775-15u
CP4 X_COPPER
R128 X_0R-1
V_FSB_VTT
OK
OK
2
ok
ok
ok
ok
V_FSB_VTT
C87 C10U10Y0805
C151 C10U10Y0805
C97 X_C10U10Y0805
1
CAPS FOR FSB GENERIC
VTT_OUT_LEFT
GTLREF VOLTAGE SHOULD BE
0.63*VTT = 0.756V
B B
VTT_OUT_LEFT
R98 X_124R1%
R103
X_210R1%
R92 124R1%
R89
210R1%
R102 X_10R
C50
X_C0.1U16Y0402
R84 10R C92
C45
C0.1U16Y0402
C54
X_C100P50N0402
C44
C100P50N0402
CP27
X_COPPER
CPU_GTLREF0 5
CPU_GTLREF1 5
V_FSB_VTT
L4 X_
CP5 X_COPPER
H_VCCABB
PLACE AT CPU END OF ROUTE
H_CPURST#
H_FERR#
7
H_IERR#
H_PROCHOT#VTT_OUT_RIGHT
H_PWRGD
H_BR#0
H_FERR# 5,19
H_PROCHOT# 5VTT_OUT_RIGHT5,7
H_PWRGD 5,19
H_BR#0 5,9
H_IERR# 5
H_CPURST# 5,9
ok
No
ok
ok
ok
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
RN25
1
3
5
7
_8P4R-470R0402-LF
ok
6
5
R15 100R0402
VTT_OUT_LEFT5
A A
VTT_OUT_LEFT
V_FSB_VTT
V_FSB_VTT
R87 _62R0402
8
R90 X_100R0402
R97 _62R0402
R64 _62R0402
R140 _62R0402
PLACE AT ICH END OF ROUTE
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
L5 X_
2
4
6
8
H_FSBSEL1
H_FSBSEL0
H_FSBSEL2
CP6 X_COPPER
X__C1U6.3Y50402/80-20%
VTT_OUT_RIGHT
VID_GD#8,29
H_FSBSEL1 5,11,18
H_FSBSEL0 5,11,18
H_FSBSEL2 5,11,18
4
VCC5_SB
C85
R71 680R0402
R282
_1KR0402-1
R76 10KR0402
OK
OK
OK
C10U10Y0805
N-MMBT3904_NL_SOT23
3
C89
VTT_PWG
Q5
X_C10U10Y0805
H_VCCA
H_VSSA
VTT_PWG SPEC :
High > 0.9V
Low < 0.3V
Trise < 150ns
C42
X__C1U6.3Y50402/80-20%
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
Intel LGA775 - Power
MS-7178
2
631Thursday, June 02, 2005
1
0A
of
8
D D
C C
B B
VTT_OUT_RIGHT5,6
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
A12
A15
A18
A21
A24
A2
A6
A9
R70
_62R0402
U5C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
7
OK
OK
V_FSB_VTT
OK
OK
ok
TP10
TP7
R79
AF23
RSVD
VSS
AF24
RSVD
VSS
AF25
TP8
RSVD
IMPSEL#
VSS
VSS
AF26
RSVD
VSS
AF27
_62R0402
VSS
AF28
AF29
VSS
AF3
RSVD
VSS
AF30
RSVD
VSS
AF6
RSVD
VSS
AF7
VSS
AG10
MSID[1]
VSS
MSID[0]
VSS
AG13
TP9
E23E5E6E7F23F6B13J3N4P5V1W1AC4Y7Y5Y2W7W4V7V6V30V3V29
RSVD
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
AF10
AF13
AF16
AF17
AF20
H_COMP6
Y3
COMP6
VSS
VSS
AE29
AE30
R33
_62R0402
H_COMP7
AE3
AE4D1D14
RSVD
COMP7
VSS
VSS
AE5
AE7
6
R78
X__62R0402
R77
_62R0402
RSVD
VSS
VSS
VSS
AG16
AG17
AG20
AG23
2005 Perf FMB 0 0
MSID1 MSID0
2005 Value FMB 0 1
V28
V27
V26
V25
V24
V23U7U1T7T6T3R7R5R30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AG24
AG7
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
AH3
AH6
AH7
AJ10
AJ13
AJ16
AJ17
VSS
VSS
VSS
VSS
AJ20
AJ23
VSS
VSS
5
AJ24
VSS
VSS
AJ27
VSS
VSS
AJ28
VSS
VSS
AJ29
VSS
VSS
R29
AJ30
VSS
VSS
4
R28
R27
R26
R25
R24
R23R2P7P4P30
P29
P28
P27
P26
P25
P24
P23N7N6N3M7M1L7L6L30L3L29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
VSS
VSS
AL24
VSS
VSS
AL27
VSS
VSS
VSS
VSS
AL28
L28
L27
L26
L25
L24
L23K7K5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL3
AL7
AM1
AM10
AM13
AM16
AM17
AM20
VSS
VSS
AM23
VSS
VSS
AM24
K2
VSS
VSS
AM27
VSS
VSS
AM28
AM4
VSS
VSS
VSS
AN1
3
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28
H3H6H7H8H9J4J7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN10
AN13
AN16
AN17
AN2
AN20
AN23
AN24
AN27
AN28B1B11
B14
_ZIF-SOCK775-15u
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
2
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
1
A A
MSI
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
Intel LGA775 - GND
MS-7178
2
731Thursday, June 02, 2005
of
1
0A
5
VREG_12V_POWER
R18
5.6KR
R20 1KR
ENLL
Q1
VCC3
R301
1KR
R5 15KR
VCCP
VCC5
R29 _0R-1
R32
X_1.65KR1%
R19 1KR
VID[0..5]5
COP
C47P50NC9
R16 2.2KR
X_C560P50XC15
R23 100R
R13 X_0R-1
R7 X_0R-1
R21 100R
R8 200KR
R9 X_47KR
R24 100KR1%
C10 C0.01U50X
R27 2.2KR
R35 _30KR1%-1
C28 C0.047U16X
5
VID_GD# 6,29
VID4
VID3
VID2
VID1
VID0
VID5
ENLL
C8 C2200P16X
R14 X_750R
C19 X_C1000P50X
C18
X_C0.1U25Y
OFS
VCCP
C29
X_C0.01U50X
_ISL6566CR_QFN40
COMP
FB
VDIFF
FS
REF
C32
C0.01U50X
U2
38
VID4
39
VID3
40
VID2
1
VID1
2
VID0
3
DACSEL/VID5
35
PGOOD
37
ENLL
8
COMP
9
FB
10
VDIFF
12
VSEN
11
RGND
6
OFST
36
FS
5
REF
4
VRM10
13
OCSET
14
ICOMP
15
ISUM
16
IREF
R42 24.3KR1%
R48 24.3KR1%
R55 24.3KR1%
D D
N-MMBT3904_NL_SOT23
VRM_GD20,29
C C
VCC_VRM_SENSE5
VSS_VRM_SENSE5
B B
Close low side
mosfet
X_4.7KRT
A A
R26
VCC5
7
VCC
GND
41
4
R10
2.2R0805
C12
C4.7U10Y0805
33
PVCC1
30
BOOT1
31
UGATE1
29
PHASE1
32
ISEN1
34
LGATE1
24
PVCC2
26
BOOT2
27
UGATE2
28
PHASE2
25
ISEN2
23
LGATE2
18
PVCC3
21
BOOT3
20
UGATE3
22
PHASE3
19
ISEN3
17
LGATE3
BOTTOM PAD CONNECT TO GND
THROUGH 10 vias
PHASE1
PHASE2
PHASE3
4
12VP1
R53 2.2R0805
BOOT1
U_G1
PHASE1
R40 2.4KR1%
L_G1
12VP2
R54 2.2R0805
BOOT2
U_G2
PHASE2
R61 2.4KR1%
L_G2
12VP3
R47 2.2R0805
BOOT3
U_G3
PHASE3
R44 2.4KR1%
L_G3
C25 C1U16Y0805
R41 2.2R0805
C36
C0.1U25X
C34 C1U16Y0805
R63 2.2R0805
C37
C0.1U25X
C33 C1U16Y0805
R52 2.2R0805
C38
C0.1U25X
+12VP_FET
12
+
EC66
CD1000U16EL20-1
VREG_12V_POWER
VREG_12V_POWER
VREG_12V_POWER
3
12
+
EC43
CD1000U16EL20-1
U_G1
R58
10KR
L_G1
R420
X_10KR
U_G2
R112
10KR
L_G2
R421
X_10KR
R123
10KR
L_G3
R422
X_10KR
3
12
+
PHASE1
PHASE2
U_G3
PHASE3
VCCP VCCPVCCP
EC22
CD1000U16EL20-1
_N-IPF09N03LA_TO252
R62
1R0805
UG1
_N-IPF06N03LA_TO252-3
_N-IPF09N03LA_TO252
R111
1R0805
UG2
_N-IPF06N03LA_TO252-3
_N-IPF09N03LA_TO252
R121
1R0805
UG3
_N-IPF06N03LA_TO252-3
EC36
C10U10Y1206
EC34
C10U10Y1206
EC35
C10U10Y1206
EC24
C10U10Y1206
EC16
C10U10Y1206
EC17
C10U10Y1206
12
+
EC41
CD1000U16EL20-1
+12VP_FET
G
Q3
G
Q4
+12VP_FET
G
Q10
G
Q11
+12VP_FET
G
Q16
G
Q19
12
+
CD1000U16EL20-1
C57 C4.7U35Y1206
C120 C1U16Y0805
DS
G
Q6
_N-IPF06N03LA_TO252-3
DS
G
C47 C4.7U35Y1206
C40 C1U16Y0805
DS
G
Q12
_N-IPF06N03LA_TO252-3
DS
G
C80 C4.7U35Y1206
C56 C1U16Y0805
DS
G
Q18
_N-IPF06N03LA_TO252-3
DS
G
EC20
C10U10Y1206
EC27
C10U10Y1206
EC31
C10U10Y1206
EC32
C10U10Y1206
EC25
C10U10Y1206
EC28
C10U10Y1206
EC23
DS
_N-IPF09N03LA_TO252
DS
Q7
DS
_N-IPF09N03LA_TO252
DS
Q13
DS
_N-IPF09N03LA_TO252
DS
Q17
2
2
COIL4
CH-1.2U18A
R93
2.2R0805
C48
C1000P50X
R114
2.2R0805
C68
C1000P50X
R134
2.2R0805
C105
C1000P50X
EC29
C10U10Y1206
EC19
C10U10Y1206
EC33
C10U10Y1206
EC26
C10U10Y1206
EC18
C10U10Y1206
EC21
C10U10Y1206
VREG_12V_POWER
C0.01U50X
VREG_12V_POWER
C128
X_C4.7U35Y1206
COIL1
CH-0.6U40A
HS1
HS-MS7033
MOSFET Heatsinks
COIL2
CH-0.6U40A
HS2
HS-MS7033
COIL3
CH-0.6U40A
HS3
HS-MS7033
1
JPW1
3
C118
1
2
1
2
1
2
1
2
1
2
1
2
MSI
Title
Size Document Number Rev
Date: Sheet
4
_PWR-2X2M
VCCP
VCCP
VCCP
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
VRM10.1 Intersil 6566 3Phase
12V
12V
1
GND
2
GND
VCCP
MS-7178
EC7
+
1 2
X_CD560U4OS-2
EC2
+
1 2
X_CD1800U6.3EL20-2
EC6
+
1 2
CD560U4OS-2
EC10
+
1 2
CD560U4OS-2
EC1
+
1 2
X_CD560U4OS-2
EC13
+
1 2
CD560U4OS-2
EC5
+
1 2
CD560U4OS-2
EC8
+
1 2
CD560U4OS-2
EC11
+
1 2
CD560U4OS-2
EC37
+
1 2
CD560U4OS-2
EC12
+
1 2
CD560U4OS-2
EC9
+
1 2
CD560U4OS-2
EC4
+
1 2
X_CD560U4OS-2
1
831Friday, June 03, 2005
of
0A
8
ok
H_A#[3..31]5
D D
ok
ok
ok
C C
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
B B
ok
ok
ok
ok
ICH_SYNC#20
ok
ok
H_ADSTB#05
H_ADSTB#15
H_BR#05,6
H_BPRI#5
H_BNR#5
H_LOCK#5
H_ADS#5
H_REQ#[0..4]5
H_HIT#5
H_HITM#5
H_DEFER#5
H_TRDY#5
H_DBSY#5
H_DRDY#5
H_RS#[0..2]5
CK_H_MCH18
CK_H_MCH#18
PWR_GD20,29
H_CPURST#5,6
PLTRST#19,24,26
R149 16.9R1%
ICH_SYNC#
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
7
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
VCC
RSVRD
AA42
VCC
RSVRD
AA34
AA38
VCC
VCC
RSVRD
RSVRD
L15
VCC
RSVRD
M15
U27
AF6
VCC
RSVRD
R27
AA37
AA41
AJ12
K38
K35
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
M36
V35
D42
U39
U40
W42
E41
D41
K36
G37
E42
U41
W41
P40
W40
U42
V41
Y40
Y43
M31
M29
C30
M18
A28
C27
B27
D27
D28
J39
J42
J37
F38
T40
T43
AJ9
U8A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
VCC
VCC
VCC
VCC
VCC
RSVRD
AA35
H_A#3 H_D#0
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
AF7
VCC
VCC
RSVRD
RSVRD
A43
AF8
AF9
VCC
RSVRD
M11
AG25
AF10
VCC
VCC
RSVRD
RSVRD
AG26
AF11
AF12
VCC
RSVRD
AG27
AJ24
6
AF13
VCC
VCC
RSVRD
RSVRD
AJ27
AF14
AF30
VCC
RSVRD
AK40
AL39
AG2
VCC
VCC
RSVRD
RSVRD
AW17
V_1P5_CORE
AG3
AG4
AG5
VCC
VCC
RSVRD
RSVRD
AW18
AY14
BC16
AG6
VCC
VCC
RSVRD
RSVRD
AD30
AG7
VCC
RSVRD
AC34
AG8
VCC
RSVRD
Y30
AG9
VCC
RSVRD
Y33
AG10
AG11
VCC
RSVRD
AF31
AD31
AG12
VCC
VCC
RSVRD
RSVRD
U30
AG13
AG14
VCC
RSVRD
AA30
V31
AH1
AH2
VCC
VCC
RSVRD
RSVRD
AC30
AK21
AH4
VCC
VCC
RSVRD
RSVRD
AJ23
AJ5
VCC
RSVRD
AJ26
AJ13
AJ14
VCC
RSVRD
AL29
AL20
5
AK2
AK3
VCC
VCC
RSVRD
RSVRD
AJ21
AL26
AK4
AK14
AK15
AK20
R15
R17
R18
R20
R21
R23
R24
U15
U17
U18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
AK27
AJ29
AG29
V30
BC43
BC42
BC2
BC1
BB43
BB2
BB1
BA2
AW26
VCC
4
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AW2
AV27
AV26
E35
C42C2B43
B42
B41B3B2
A42
Y17
Y18
Y19
Y21
Y23
Y25
Y27
AA15
AA17
W22
VCC
VCC
AA18
W24
VCC
VCC
AA19
W26
VCC
VCC
AA20
W27
Y15
M17
VCC
VCC
VCC
KDINV_0#
HDINV_1#
HDINV_2#
HDINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
3
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
X_Lakeport
V_1P5_CORE
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
K40
A38
E29
B32
K41
L43
F35
G34
J27
M26
E34
B37
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 5
H_DSTBN#0 5
H_DSTBP#1 5
H_DSTBN#1 5
H_DSTBP#2 5
H_DSTBN#2 5
H_DSTBP#3 5
H_DSTBN#3 5
2
H_D#[0..63] 5
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
ok
U6_X1
H_DBI#[0..3] 5
ok
X5
X6
X7
X8
MCH
Heatsink
MCH_HS
ok
1
X1
X2
X3
X4
V_FSB_VTT
A A
R155 _62R0402
HXSCOMP
C142
X_C2.2P25N0402
R150
_301R1%0402-1
R152
_84.5R1%0402-1
V_FSB_VTT
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/3*VTT +/- 2%
PLACE DIVIDER RESISTOR NEAR VTT
R151 _62R0402
C139
C0.01U16X0402
HXSWING
R148
124R1%0402
R146
210R1%0402
V_FSB_VTT
C0.1U16Y0402
CAPS SHOULD BE PLACED NEAR MCH PIN
8
7
6
5
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
MCH_GTLREF
C133
R144 _0R-1
C135
X_C220P50N
MCH_GTLREF_CPU 5
4
OK
MSI
Title
Size Document Number Rev
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
Intel Lakeport - CPU
MS-7178
2
931Thursday, June 02, 2005
of
1
0A
8
7
6
5
4
3
2
1
SCKE_A[0..3]13,15
DQM_A[0..7]13
DATA_A[0..63]13
DQM_A6
DQM_A1
DQM_A4
DQM_A2
DQM_A7
DQM_A3
DQM_A5
DATA_A16
DATA_A21
D D
C C
B B
SCS_A#[0..3]13,15
RAS_A#13,15
CAS_A#13,15
MAA_A[0..13]13,15
ODT_A[0..3]13,15
SBS_A[0..2]13,15
DQS_A013
DQS_A#013
DQS_A113
DQS_A#113
DQS_A213
DQS_A#213
DQS_A313
DQS_A#313
DQS_A413
DQS_A#413
DQS_A513
DQS_A#513
DQS_A613
DQS_A#613
DQS_A713
DQS_A#713
P_DDR0_A13
N_DDR0_A13
P_DDR1_A13
N_DDR1_A13
P_DDR2_A13
N_DDR2_A13
P_DDR3_A13
N_DDR3_A13
P_DDR4_A13
N_DDR4_A13
P_DDR5_A13
N_DDR5_A13
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#
CAS_A#
WE_A#
WE_A#13,15
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SMPCOMP_N
SMPCOMP_P MCH_VREF_AMCH_VREF_B
BB37
BA39
BA35
AY38
BA34
BA37
BB35
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
AW37
AY39
AY37
BB40
BC33
AY34
BA26
AU4
AR2
BA3
BB4
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
BB32
AY32
AY5
BB5
AK42
AK41
BA31
BB31
AY6
BA5
AH40
AH43
AM3
AL5
AJ6
AJ8
U8B
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACLK0
SACLK0#
SACLK1
SACLK1#
SACLK2
SACLK2#
SACLK3
SACLK3#
SACLK4
SACLK4#
SACLK5
SACLK5#
MCH_SRCOMP0
MCH_SRCOMP1
SMOCDCOMP0
SMOCDCOMP1
DATA_A1
AP3
AP2
SADQ0
X_Lakeport
R244 80.6R1%0402
SMPCOMP_P
DATA_A3
DATA_A2
AU3
AV4
SADQ1
SADQ2
SBDQ0
AL6
AL8
DATA_B0
DATA_B1
DATA_A4
DATA_A5
AN1
AP4
SADQ3
SADQ4
SBDQ1
SBDQ2
AP8
AP9
DATA_B3
DATA_B2
DATA_A7
AU5
AU2
SADQ5
SADQ6
SBDQ3
SBDQ4
AJ11
AL9
DATA_B4
DATA_B5
DATA_A8
DATA_A9
AW3
AY3
SADQ7
SADQ8
SBDQ5
SBDQ6
AM10
AP6
DATA_B7
DATA_B6
BA7
BB7
SADQ9
SADQ10
SBDQ7
SBDQ8
AU7
AV6
DATA_B8
DATA_B9
AV1
AW4
SADQ11
SADQ12
SADQ13
SBDQ9
SBDQ10
SBDQ11
AV12
AM11
DATA_B11
DATA_B10
BC6
AY7
AW12
SADQ14
SADQ15
SADQ16
SBDQ12
SBDQ13
SBDQ14
AR5
AR7
AR12
DATA_B14
DATA_B12
DATA_B13
AY10
AR10
DATA_B15
DATA_A10
DATA_A12
DATA_A13
DATA_A17
DATA_A14
DATA_A15
DATA_A11
DATA_A6
DATA_A0
DATA_A19
DATA_A18
BA12
BB12
SADQ17
SADQ18
SADQ19
SBDQ15
SBDQ16
SBDQ17
AM15
AM13
DATA_B17
DATA_B16
DATA_A22
DATA_A20
BA9
BB9
BC11
SADQ20
SADQ21
SADQ22
SBDQ18
SBDQ19
SBDQ20
AV15
AM17
AN12
DATA_B20
DATA_B18
DATA_B19
DATA_A24
DATA_A25
DATA_A23
AY12
AM20
AM18
SADQ23
SADQ24
SADQ25
SBDQ21
SBDQ22
SBDQ23
AR13
AP15
AT15
DATA_B21
DATA_B23
DATA_B22
DATA_A28
DATA_A26
DATA_A27
AV20
AM21
AP17
SADQ26
SADQ27
SADQ28
SBDQ24
SBDQ25
SBDQ26
AM24
AM23
AV24
DATA_B24
DATA_B25
DATA_B26
DATA_A29
DATA_A30
AR17
AP20
SADQ29
SBDQ27
AM26
AP21
DATA_B27
DATA_B28
DATA_A32
DATA_A31
AT20
AP32
SADQ30
SADQ31
SADQ32
SBDQ28
SBDQ29
SBDQ30
AR21
AP24
DATA_B30
DATA_B29
DATA_A34
DATA_A35
DATA_A33
AV34
AV38
AU39
SADQ33
SADQ34
SADQ35
SBDQ31
SBDQ32
SBDQ33
AT24
AU27
AN29
DATA_B32
DATA_B31
DATA_B33
DATA_A37
DATA_A36
DATA_A38
AV32
AT32
AR34
SADQ36
SADQ37
SADQ38
SBDQ34
SBDQ35
SBDQ36
AR31
AM31
AP27
DATA_B35
DATA_B36
DATA_B34
DATA_A40
DATA_A41
DATA_A39
AU37
AR41
AR42
SADQ39
SADQ40
SADQ41
SBDQ37
SBDQ38
SBDQ39
AR27
AP31
AU31
DATA_B39
DATA_B37
DATA_B38
DATA_A43
DATA_A42
DATA_A44
AN43
AM40
AU41
SADQ42
SADQ43
SADQ44
SBDQ40
SBDQ41
SBDQ42
AP35
AP37
AN32
DATA_B40
DATA_B42
DATA_B41
DATA_A45
DATA_A47
DATA_A46
AU42
AP41
AN40
SADQ45
SADQ46
SADQ47
SBDQ43
SBDQ44
SBDQ45
AL35
AR35
AU38
DATA_B45
DATA_B43
DATA_B44
DATA_A49
DATA_A48
DATA_A50
AL41
AL42
AF39
SADQ48
SADQ49
SADQ50
SBDQ46
SBDQ47
SBDQ48
AM38
AM34
AL34
DATA_B48
DATA_B46
DATA_B47
DATA_A53
DATA_A52
DATA_A51
AE40
AM41
AM42
SADQ51
SADQ52
SADQ53
SBDQ49
SBDQ50
SBDQ51
AJ34
AF32
AF34
DATA_B49
DATA_B51
DATA_B50
DATA_A56
DATA_A54
DATA_A55
AF41
AF42
AD40
SADQ54
SADQ55
SADQ56
SBDQ52
SBDQ53
SBDQ54
AL31
AJ32
AG35
DATA_B52
DATA_B54
DATA_B53
DATA_A57
DATA_A58
DATA_A59
AD43
AA39
AA40
SADQ57
SADQ58
SADQ59
SBDQ55
SBDQ56
SBDQ57
AD32
AC32
AD34
DATA_B55
DATA_B57
DATA_B56
DATA_A61
DATA_A62
DATA_A60
AE42
AE41
AB41
SADQ60
SADQ61
SADQ62
SBDQ58
SBDQ59
SBDQ60
Y32
AA32
AF35
DATA_B58
DATA_B60
DATA_B59
DATA_A63
AB42
SADQ63
SBDQ61
AF37
AC33
DATA_B61
DATA_B62
DATA_B[0..63]14
SCKE_B[0..3]14,15
VCC_DDR
A A
R243 80.6R1%0402
C209
C0.1U16Y0402
8
SMPCOMP_N
7
6
5
DQM_B[0..7]14
SCKE_A1
SCKE_A0
BB25
AY25
SACKE0
SACKE1
SBDQ62
SBDQ63
AC35
DATA_B63
4
SCKE_A3
SCKE_A2
BC24
BA25
SACKE2
SACKE3
SBCKE0
SBCKE1
BA14
AY16
BA13
SCKE_B0
SCKE_B2
SCKE_B1
DQM_A0
AR3
SADM0
SBCKE2
SBCKE3
BB13
SCKE_B3
BB10
AY2
SADM2
SADM1
SBDM6
SBDM7
AJ39
AD39
DQM_B7
DQM_B6
AT34
AP18
SADM4
SADM3
SBDM4
SBDM5
AR29
AR38
DQM_B5
DQM_B4
AG40
AP39
SADM6
SADM5
SBDM2
SBDM3
AP13
AP23
DQM_B2
DQM_B3
DQM_B1
AC40
SADM7
SMVREF1
SMVREF0
SBDM1
AL11
AW7
DQM_B0
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SBDM0
SCS_B#0
BA40
SCS_B#1
AW41
SCS_B#2
BA41
SCS_B#3
AW40
RAS_B#
BA23
CAS_B#
AY24
WE_B#
BB23
MAA_B0
BB22
MAA_B1
BB21
MAA_B2
BA21
MAA_B3
AY21
MAA_B4
BC20
MAA_B5
AY19
MAA_B6
AY20
MAA_B7
BA18
MAA_B8
BA19
MAA_B9
BB18
MAA_B10
BA22
MAA_B11
BB17
MAA_B12
BA17
MAA_B13MAA_A13
AW42
ODT_B0
AY42
ODT_B1
AV40
ODT_B2
AV43
ODT_B3
AU40
SBS_B0
AW23
SBS_B1
AY23
SBS_B2
AY17
DQS_B0
AM8
DQS_B#0
AM6
DQS_B1
AV7
DQS_B#1
AR9
DQS_B2
AV13
DQS_B#2
AT13
DQS_B3
AU23
DQS_B#3
AR23
DQS_B4
AT29
DQS_B#4
AV29
DQS_B5
AP36
DQS_B#5
AM35
DQS_B6
AG34
DQS_B#6
AG32
DQS_B7
AD36
DQS_B#7
AD38
P_DDR0_B
AM29
N_DDR0_B
AM27
P_DDR1_B
AV9
N_DDR1_B
AW9
P_DDR2_B
AL38
N_DDR2_B
AL36
P_DDR3_B
AP26
N_DDR3_B
AR26
P_DDR4_B
AU10
N_DDR4_B
AT10
P_DDR5_B
AJ38
N_DDR5_B
AJ36
AM2
MCH_VREF_A
AM4
PLACE 0.1UF CAP CLOSE TO MCH
3
SCS_B#[0..3] 14,15
RAS_B# 14,15
CAS_B# 14,15
WE_B# 14,15
MAA_B[0..13] 14,15
ODT_B[0..3] 14,15
SBS_B[0..2] 14,15
DQS_B0 14
DQS_B#0 14
DQS_B1 14
DQS_B#1 14
DQS_B2 14
DQS_B#2 14
DQS_B3 14
DQS_B#3 14
DQS_B4 14
DQS_B#4 14
DQS_B5 14
DQS_B#5 14
DQS_B6 14
DQS_B#6 14
DQS_B7 14
DQS_B#7 14
P_DDR0_B 14
N_DDR0_B 14
P_DDR1_B 14
N_DDR1_B 14
P_DDR2_B 14
N_DDR2_B 14
P_DDR3_B 14
N_DDR3_B 14
P_DDR4_B 14
N_DDR4_B 14
P_DDR5_B 14
N_DDR5_B 14
C206
C0.1U16Y0402
VCC_DDR
PLACE 0.1UF CAP CLOSE TO MCH
C205
C0.1U16Y0402
CP20
X_COPPER
R250 1KR1%0402
R249 X__0R-1
MCH_VREF_A
MCH_VREF_B
R248
1KR1%0402
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
No.69, Li-De St, Jung-He City, Taipei Hsien, Taiwan. http://www.msi.com.tw
Intel Lakeport - Memory
MS-7178
2
10 31Thursday, June 02, 2005
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1
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