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Cover Sheet 1.1
Block Diagram
D D
POWER MAP
GPIO/MEMORY/PCI/HW STRAPPING
Intel LG775 - Signals
Intel LG775 - Power
Intel LG775 - GND
Intel Grantsdale_CPU
Intel Grantsdale_Memory
Intel Grantsd ale_PCIE & RGB
Intel Grantsdale_GND
DDRII DIMM 1 & 2
C C
DDRII DIMM 3 & 4
DDR Termination Resistors
ICH6_PCI, DMI, CPU, IRQ
ICH6_LPC, ATA, USB, RTC
ICH6_POWER
Clock Gen. & FWH & FDD
SIO, KBMS, COM, Print
AC97 Audio_ALC6555
PCI EXPRESS 16 PORT
IDE, SATA,VGA
B B
PCI Slot 1, 2, 3
ACPI CoNTROLLER
ATX & Front Panel
USB CONNECTORS
LAN_RTL8100C/8110S
VRM10 Intersil 6566 3 Phases
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
MS-7177
Version:20
CPU:
Intel Tejas & Prescott LGA775 Processor
System Chipset:
Intel Grantsdale: 915GV/915PP/915G/910GL
Intel ICH6
On Board Chipset:
BIOS -- FWH EEPROM
AC'97 Codec -- ALC655
LPC Super I/O -- W83627THF Ver:E
LAN --RTL8100C/RTL8110S
CLOCK --Cypress 28416
Main Memory:
DDRII * 4
Expansion Slots:
PCI EXPRESS X16 SLOT
PCI SLOT * 3
FAN, Header, IR
29
PWM:
Jumper Setting / Manual Part
Modify History
A A
8
BOM History
7
6
30
31
32
Controller: Inter sil 6566
Title
Cover Sheet
Size Document Number Re v
Custom
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7177 20
of
133Wednesday, June 22, 2005
1
8
7
Block Diagram
6
5
4
3
2
1
ISL 6566
D D
3-Phase PWM
Graphic on Board
PCI_ Express 16
C C
UltraDMA 33/66/ 100
IDE
Intel LGA775 Processor
FSB
Grantsdale
915 GV
915 P
915 G
DMI
ICH6
64bit DDR
Channel 1
64bit DDR
Channel 2
4 DDRII
DIMM
Modules
PCI Slot 1
LAN RTL8100C/8110S
PCI Slot 2
PCI Slot 3
USB Port 0
USB Port 1
USB
LPC Bus
USB Port 2
USB Port 3
B B
USB Port 4
USB Port 5
USB Port 6
SATA0
SATA1
SATA2
SATA3
LPC SIO
Winbond
83627THF
USB Port 7
AC'97 Link
Flash
AC97 ALC655
A A
8
7
6
5
Keyboard
Mouse
Floopy Parallel
4
Serial
Title
Block Diagram
Size Document Number Re v
Custom
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7177 20
of
233Wednesday, June 22, 2005
1
8
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1
Tejas
D D
0.8375V - 1.6000V Core
1.2V FSB Vtt
- 95A
- TBD A
ISL6566
VCCP
0.8375V-1.6000V
3-Phase Switch
VRM 10.1
95A
DDR DIMM & TERMINATOR
0.9V VTT_DDR - 1.2A
1.8V VCC_DDR
(S0,S1)
(S3) -400mA
-9.4A1.8V VCC_DDR
W83310DS
Gransdale GMCH
- 1.0A1.2V FSB Vtt
1.8V DDRII I/O -4.7A
(S0,S1)
-25mA(S3)1.8V DDRII I/O
*2.5V DAC
2.5V HV
C C
1.5V Core
(Integrated)
(Discrete) - 7.7A
- 0.07A
- TBD A
- 9.7A1.5V Core
- 1.4A*1.5V PCI Express
ICH6
1.2V VCC_CPU
1.5V Core
*1.5V PCI Express
1.5V SATA
(G3) - 5uARTC
B B
5VrefSus
- tbdmA
- 1.88A
- 260mA
- 430mA
- 330mA+3.3V VccSus
- TBD A5VRef
- TBD A
VTT_DDR
Linear
1.0A1.3V
MS7 Regulator
V_FSB_VTT
Linear1.2V 5.0A
VCC_DDR
Linear
(S0,S1)
(S3)
8.0A1.8V
570mA
V_2P5_MCH
2.5V Linear
100mA
VCC3_SB
3.3V Linear
1.5A
5VDUAL1,2
5V Linear
22mA
MS6+ Regulator
V_1P5_CORE
1.5V
Switch 14A
PCI Express x16 slot
+12V
+3.3Vaux
+3.3Vaux
+3.3V
(wake)
(no wake)
- 5.5A
- 375mA
- 20mA
- 3.0A
PCI slot x3
+3.3Vaux
+3.3Vaux
+3.3V
+5V
+12V
(wake)
(no wake)
- 375mA
- 20mA
- 7.6A
- 5.0A
- 0.5A
USB
+5V - 4A(S0,S1)
+5V (S3) - 20mA
+3.3V
- 180mA
PS2
FWH
+5V (S3) - 2.0mA
+3.3V (S0,S1) - 107mA
3V
A A
Battery
+3.3V+5V+12V +5VSB
- 345mA+5V (S0,S1)
ATX POWER
Title
POWER MAP
Size Document Number Re v
Custom
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7177 20
of
333Wednesday, June 22, 2005
1
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PCI Configuration
D D
ICH6 Not modify yet
GPIO PinIType
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
C C
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17 O
GPIO 19
GPIO 20
GPIO 21
GPIO 23
GPIO 24
GPIO 25
GPIO 26
GPIO 27
GPIO 28
B B
GPIO 29
GPIO 30
GPIO 31
GPIO 32
GPIO 33
GPIO 34
GPIO 40
GPIO 41
GPIO 48
GPIO 49
Function
REQ#6 pull-up to VCC5 with 2.7K
I
REQ#5 pull-up to VCC5 with 2.7 K,and connect to RTL8100C
I
PIRQ#E pull-up to VCC5 with 2.7K
I
PIRQ#F pull-up to VCC5 with 2.7K
PIRQ#G pull-up to VCC5 with 2.7K
I
PIRQ#H pull-up to VCC5 with 2.7K
I
GPI6 pull-up to VCC3 with 10K
I
GPI7 pull-up to VCC3 with 10K
I
GPI8 pull-up to VCC3_SB with 10K
I
OC#3_4 connect to USB connector
I
OC#3_4 connect to USB connector
I
SMB_ALERT# pull-up to VCC3_SB with 10K
I
PS_DETECT p u l l- u p t o V C C3 with 10K
I
SIO_PME# co nnect to LPC I/O
I
OC#3_4 connect to USB connector
I
OC#3_4 connect to USB connector
I
NC
O
PGNT#5 connect to RTL8100C
NC
OGPIO 18
BIOS_WP# co n nect to FWH
O
NC
O
NC
O
GPO23_TBL# connect to FWH
O
GPIO24 conn ect to Lenovo header
I/O
pull-down to GND with 1K directly (enable internal 2.5V VRM)
I/O
pull-up to V CC 3 w it h 1 0 K directly
I
GPIO27 conn ect to Lenovo header
I/O
NC
I/O
pull-up to V CC 3 w it h 1 0 K directly
I
pull-up to V CC 3 w it h 1 0 K directly
I
pull-up to V CC 3 w it h 1 0 K directly
I
LEO_CLKRUN#
I/O
NC
I/O
GPIO34 conn ect to Lenovo header
I/O
PREQ#4 pull-up to VCC5 with 2.7K
I
NC
I
NC
O
H_PWRGD pull - u p t o V TT _ O U T_LEFT with 100
OD
ohm,and connect to CPU
Power Pin
5V
5V
5V
5V
5V
5V
3.3V
3.3V
3.3V_SB
3.3V_SB
3.3V_SB
3.3V_SB
3.3V
3.3V_SB
3.3V_SB
3.3V_SB
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V_SB
3.3V_SB
3.3V
3.3V_SB
3.3V_SB
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
5V
3.3V
3.3V
VCPU
B7
E8
D9
C7
C6
M3
AD19
AE19
R1
C23
D23
W6
M2
R6
C25
C24
D8
F6
AC21
AB21
AD22
AD20
AD21
V3
P5
AF17
R3
T3
AE18
AF18
AG18
AF19
AF20
AC18
F7
P4
E7
AG25
DEVICE
PCI Slot 2
PCI Slot 1
PCI RESET DEVICE
Signals Target
PLTRST# Grandstale,MS7
PCIRST_ICH6#
PCIRST#1
HD_RST#
DDR DIMM Config.
DEVICE
DIMM 1
DIMM 2 MCLK_B1/MCLK_B#1
JUMPER SETTING
RTCRST
INT Pin REQ#/GNT#
INTB#
INTC#
INTD#
PCI_GNT#1
INTA#
INTC#
INTD#
INTA#
PCI_REQ#2PCI Slot 3
PCI_GNT#2
INTB#
INTD#
PCI_REQ#3 PCICLK3
INTA# PCI_GNT#3
INTB#
INTC#
INTH#
PCI_REQ#5LAN
PCI_GNT#5
PCIE_16, LAN
FWH , SIO , LEO Header
PCI Slot 1,2,3PCIRST#2
IDE
ADDRESS
CLOCK
MCLK_A0/MCLK_A#0
MCLK_A1/MCLK_A#1A0H
MCLK_A2/MCLK_A#2
MCLK_B0/MCLK_B#0
A4H
MCLK_B2/MCLK_B#2
(1-2)CLEAR(2-3)NORMAL
IDSEL
AD18
AD19
AD20
AD27
CLOCK
PCICLK1PCI_REQ#1
PCICLK2
LAN_CLK
FWH
Function
GPI 0 PD_DETI
A A
TypeGPIO Pin
Title
GPIO/MEMORY/PCI/HW STRAPPING
Size Document Number Re v
Custom
8
7
6
5
4
3
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7177 20
of
433Wednesday, June 22, 2005
1
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CPU SIGNAL BLOCK
H_A#[3..31][8]
D D
C C
B B
A A
Chipset does not support extended
addressing over 4GB,leave A[35:32]#
unconnected.
VTT_OUT_RIGHT
H_D#[0..63][8]
H_DBI#[0..3][8]
H_EDRDY#[8]
FERR#[15]
STPCLK#[15]
HINIT#[15]
H_DBSY#[8]
H_DRDY#[8]
H_TRDY#[8]
H_ADS#[8]
H_LOCK#[8]
H_BNR#[8]
H_HIT#[8]
H_HITM#[8]
H_BPRI#[8]
H_DEFER#[8]
CPU_TMPA[19]
VTIN_GND[19]
TRMTRIP#[15]
IGNNE#[15]
SMI#[15]
A20M#[15]
SLP#[15]
X_C0.1U10X0402C483
R405 X_1KR0402
H_PWRGD[15]
H_CPURST#[8]
H_FSBSEL0[6,10,18]
H_FSBSEL1[6,10,18]
H_FSBSEL2[6,10,18]
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_IERR#
H_PROCHOT#
CPU_BOOT
H_PWRGD
H_CPURST#
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
U901A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
B15
H_D#53
H_A#10
H_A#8
H_A#6
H_A#5
H_A#7
H_A#4
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D22#
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
E10
D10
H_D#18
H_D#19
H_D#20
H_D#21
H_A#3
AN5
L5
D11
H_D#15
H_D#16
H_D#17
AN6
AN4
AN3
D13#
H_D#12
VSS_SENSE
VCC_SENSE
D12#D8D11#
B10
C11
H_D#10
H_D#11
RSVD
D10#
A11
H_D#9
RSVD
D9#
AJ3
D8#
A10
H_D#7
H_D#8
AC2
DBR#
D14#
B12
C12
H_D#13
H_D#14
H_A#31
H_A#30
H_A#28
H_A#29
H_A#25
H_A#26H_D#39
H_A#22
H_A#23
H_A#19
H_A#17
H_A#16
H_A#14
H_A#12
H_A#11
G16
H_A#18
D32#
G15
H_D#31
D31#
H_D#30
AB6
D30#
F15
H_A#13
H_A#15
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D29#
D28#
D27#
D26#
D25#
F14
F12
E13
D13
G14
G13
H_D#29
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
U6
D24#
F11
H_D#23
H_A#9
D23#
H_D#22
AB4
E18
AC5
A26#
D39#
F18
H_D#38
H_A#24
AB5
A25#
D38#
F17
H_D#37
AA5
A24#
D37#
G17
H_D#36
AD6
A23#
D36#
G18
H_D#35
H_A#21
AA4
A22#
D35#
E16
H_D#34
H_A#20
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
E15
H_D#32
H_D#33
H_A#27
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
AF4
AF5
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
F21
G22
F20
E22
E21
D22
H_D#46
E19
G21
H_D#44
H_D#43
H_D#42
H_D#41
H_D#40
H_D#45
A14
C14
C15
D17
D20
H_D#51
H_D#52
H_D#50
H_D#49
H_D#48
H_D#47
VCC_VRM_SENSE
VSS_VRM_SENSE
VID4
VID3
VID5
AM5
AL4
AK4
AK3
ITP_CLK1
AL6
RSVD
VID5#
VID4#
VID3#
ITP_CLK0
TESTHI12
TESTHI11
TESTHI10
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
B4
H_D#0
H_D#1
H_D#6
H_D#5
H_D#2
H_D#3
H_D#4
VID[0..5] [28]
VID2
VID0
VID1
AM3
AL5
AM2
VID2#
VID1#
VID0#
H1
GTLREF
AG3
BPM5#
AF2
BPM4#
AG2
BPM3#
AD2
BPM2#
AJ1
BPM1#
AJ2
BPM0#
G5
PCREQ#
J6
REQ4#
K6
REQ3#
M6
REQ2#
J5
REQ1#
K4
REQ0#
W2
P1
H5
G4
TESTHI9
G3
TESTHI8
F24
TESTHI7
G24
TESTHI6
G26
TESTHI5
G27
TESTHI4
G25
TESTHI3
F25
TESTHI2
W3
TESTHI1
F26
TESTHI0
AK6
RSVD
G6
RSVD
G28
BCLK1#
F28
BCLK0#
A3
RS2#
F5
RS1#
B3
RS0#
U3
AP1#
U2
AP0#
F3
BR0#
R1
COMP3
G2
COMP2
T1
COMP1
A13
COMP0
J17
DP3#
H16
DP2#
H15
DP1#
J16
DP0#
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
ZIF-SOCK775-15u
CPU_GTLREF
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
H_PCREQ#
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
RSVD_AK6
RSVD_G6
H_RS#2
H_RS#1
H_RS#0
TSET-U3
TSET-U2
H_BR#0
H_COMP3
H_COMP2
H_COMP1
H_COMP0
TSET-J17
TSET-H16
TSET-H15
TSET-J16
VCC_VRM_SENSE [28]
VSS_VRM_SENSE [28]
VID3
VID1
VID2
VID4
VID0
R396 680R0402
VID5
R397 680R0402
C490
C220P50N
H_PCREQ# [8]
H_REQ#[0..4] [8]
R398 62R0402
1 2
3 4
5 6
7 8
RN73
_8P4R-62R0402-LF
R399 62R0402
R400 62R0402
R401 62R0402
R402 62R0402
R403 62R0402
CPU_CLK# [ 18 ]
CPU_CLK [18]
H_RS#[0..2] [8]
T1
T2
R404 100R1%0402
R406 100R1%0402
R407 60.4R1%0402
R408 60.4R1%0402
T3
T4
T5
T6
H_ADSTB#1 [8]
H_ADSTB#0 [8]
H_DSTBP#3 [8]
H_DSTBP#2 [8]
H_DSTBP#1 [8]
H_DSTBP#0 [8]
H_DSTBN#3 [8]
H_DSTBN#2 [8]
H_DSTBN#1 [8]
H_DSTBN#0 [8]
NMI [15]
INTR [15]
H_BR#0 [8]
Pin AN3 & AN4: CPU Silicon Die sense
Pin AN5 & AN6: CPU package Pin U27/V27 sense
RN70
8P4R-680R
1
2
3
4
5
6
7
8
C489
C0.1U25Y
PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE
CPU_GTLREF [6]
VTT_OUT_LEFT
V_FSB_VTT
VTT_OUT_LEFT
C484
X_C0.1U25Y
C0.1U25Y
VTT_OUT_RIGHT
C482
VTT_OUT_RIGHT
C481
C0.1U25Y
H_BPM#0
1 2
H_BPM#1
3 4
H_BPM#5
5 6
7 8
RN71
8P4R-51R0402
H_TRST#
1 2
H_BPM#3
3 4
H_TDO
5 6
H_BPM#4
7 8
RN72
8P4R-51R0402
H_TMS
7 8
H_TDI
5 6
H_BPM#2
3 4
H_TCK
1 2
RN74
8P4R-51R0402
H_PWRGD
H_BR#0
H_PROCHOT#
H_CPURST#
H_PROCHOT# have intrnal R ,
so no longer required
H_IERR#
R417 100R0402
R418 62R0402
R416 X_120R0402
R414 62R0402
R421 62R0402
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_OUT_RIGHT
V_FSB_VTT
Pin Y1: BootSelect input Pin
CPU will not operate if this signal is low.
This input has a weak internal pull-up to VCC.
8
7
Pin V2 and AA2: LL_ID0:1 Output Pin
Configure the proper loadline slope for the CPU.
LL_ID[1:0] = 00 for the 775 CPU
6
5
PIN AE8: SKTOCC# Output
(Socket Occupied) will be pulled to ground by PCU.
4
3
Title
Intel LG775 - Signals
Size Document Number Rev
Custom
Date: Sheet of
MICRO-START INT'L CO.,LTD.
MS-7177 20
2
533Wednesday, June 22, 2005
1
8
VCCP
AG14
AG12
AG11
AF9
AF8
AF22
AF21
U901B
VCCP
AF19
D D
C C
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y25
Y26
Y27
Y28
Y29
Y30
7
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCU8VCCV8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
Y23
Y24
W29
W30
W28
W27
W26
W25
W24
W23
U30
U29
U28
U27
U26
U25
AH21
U24
6
AH27
AH26
AH25
AH22
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN8VCCP8VCCR8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCT8VCC
VCC
T23
T24
T25
T26
T27
T28
T29
U23
T30
N30
N29
N28
N27
N26
N25
5
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
K25
K26
K27
K28
K29
N24
N23
M30
M29
M28
M27
M26
M25
M24
M23
K30
4
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
3
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
A23
VCCA
B23
VSSA
D23
RSVD
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT_OUT
VTT_OUT
VTT_SEL
HS11HS22HS33HS4
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
AA1
J1
F27
F29
4
ZIF-SOCK775-15u
VCC-IOPLL
VTTPWRGD
RSVD/VTT_PKGSENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
J10
J11
J12
J13
AN8
AN9
AN25
AN26
AN29
AN30
2
H_VCCA
H_VSSA
H_VCCA
V_FSB_VTT
VTT_PWG
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
Pin F27: VTT_SEL Output Pin
VTT_SEL = 1 for the Pentium 4 processor
in the 775-land package.
VTT_OUT_RIGHT
VTT_OUT_LEFT
R409 X_1KR0402
0
1
VCC3
TEJ/PSC
RSVD
1
VTT_OUT_RIGHT
B B
GTLREF VOLTAGE SHOULD BE
0.67*VTT = 0.8V
A A
V_FSB_VTT
8
R410 49.9R1%
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
CPU_GTLREF
R411
100R1%
RN75
1
2
3
4
5
6
7
8
8P4R-470R0402
7
CPU_GTLREF [5]
H_FSBSEL1 [5,10,18]
H_FSBSEL2 [5,10,18]
H_FSBSEL0 [5,10,18]
6
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
V_FSB_VTT
5
L21 10U100m_0805
VCC5_SB
R413 1KR0402
VID_GD#[24,28]
C488
C10U10Y0805
R415 10KR0402
4
H_VCCA
C491
C1U16Y
H_VSSA
VTT_OUT_LEFT
R412
680R0402
Q48
1.25V VTT_PWRGOOD
VTT_PWG
N-MMBT3904_NL_SOT23
3
CAPS FOR FSB GENERIC
V_FSB_VTT
Title
Intel LG775 - Power
Size Document Number Rev
Custom
Date: Sheet
C485 C10U10Y0805
C486 C10U10Y0805
C487 X_C22U6.3X1206
MICRO-START INT'L CO.,LTD.
MS-7177 20
2
633Wednesday, June 22, 2005
of
1
8
D D
VTT_OUT_LEFT
AC4
AE3
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE4
RSVD
RSVD
RSVD
VSS
VSS
VSS
VSS
AE5
AE7
AE29
AE30
U901C
A12
A15
A18
A2
A21
A24
A6
C C
B B
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
A9
7
R422 X_60.4R1%0402
R423 X_60.4R1%0402
T9
T8
T7
TEST-E23
D14
RSVDD1RSVD
VSS
VSS
AF10
AF13
T10
TEST-E7
TEST-F23
TEST-F6
E23
E24
F23
B13
RSVD
RSVD
RSVDE5RSVDE6RSVDE7RSVD
RSVDF6RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF16
AF17
AF20
AF23
AF24
AF25
AF26
AF27
AF28
RSVDH2RSVDJ2RSVDJ3RSVDN4RSVDP5RSVDT2RSVDV1RSVDW1RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AF6
AF7
AF29
AF30
AG10
AG13
Y3
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
AG16
AG17
AG20
AG23
6
V30
V29
V28
V27
V26
V25
V24
V23
VSSV3VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH1
AG7
AH10
AH13
AG24
AH3
AH6
AH7
AJ10
AJ13
AJ16
AH16
AH17
AH20
AH23
AH24
AJ17
VSS
5
R30
R29
R28
R27
R26
R25
R24
R23
P30
P29
P28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AK2
AK10
AK13
AK16
AK17
AK20
AK23
AK24
AK27
AK28
VSS
VSS
P27
P26
VSS
VSS
VSS
VSS
AK29
AK30
4
P25
P24
P23
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
AK5
AK7
AL10
AL13
3
Pin 29 : GTLREF_SEL Output Pin
GTLREF_SEL = 0 for the Pentium 4 processor in the 775-land package.
H23
H24
H25
H26
H27
H28
VSS
AM7
VSS
H29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AN1
AN2
AN10
AN13
AN16
AN17
AN20
AN23
AN24
AN27
AN28
VSS
VSS
K2
L25
L24
L23
K5
VSS
VSS
VSS
VSSK7VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM16
AM17
AM4
AM20
AM23
AM24
AM27
AM28
L30
L29
L28
L27
L26
VSSL3VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL3
AL7
AL16
AL17
AL20
AL23
AM1
AL24
AL27
AL28
AM10
AM13
H22
AN7
H21
VSS
VSS
H20
VSS
VSS
VSSB1VSS
B11
H19
VSS
VSS
B14
2
H17
H18
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ZIF-SOCK775-15u
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
1
A A
Title
Intel LG775 - GND
Size Document Number Rev
Custom
8
7
6
5
4
3
Date: Sheet
MICRO-START INT'L CO.,LTD.
MS-7177 20
2
733Wednesday, June 22, 2005
of
1
8
7
6
5
4
3
2
1
V_1P5_CORE
AC11
AB11
Y20
Y19
Y17
Y16
W20
W16
U20
U16
T20
T19
T17
T16
AA13
AA14
AA16
AA18
AA20
AA21
AA22
AA23
AA24
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
AB21
AB22
AB23
AB24
N13
N14
N15
N16
N18
N20
N21
P13
P14
P15
P17
P19
P21
P22
R13
R14
R15
R16
R18
R20
R22
R23
T13
T14
T15
T21
T23
T24
U13
U14
U22
U24
V13
V14
V15
V21
V23
V24
W13
W14
W22
W24
Y13
Y14
Y15
Y21
Y23
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
NCB1NC
B35
AP1
Y24
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
NC
_B01-915GV15-IX6
A2
A34
3
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
J33
H33
J34
G35
H35
G34
F34
G33
D34
C33
D33
B34
C34
B33
C32
B32
E28
C30
D29
H28
G29
J27
F28
F27
E27
E25
G25
J25
K25
L25
L23
K23
J22
J24
K22
J21
M21
H23
M19
K21
H20
H19
M18
K18
K17
G18
H18
F17
A25
C27
C31
B30
B31
A31
B27
A29
C28
A28
C25
C26
D27
A27
E24
B25
E34
J26
K19
B26
E33
E35
H26
F26
J19
F19
B29
C29
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_D#[0..63] [5]
H_DBI#[0..3] [5]
H_DSTBP#0 [5]
H_DSTBN#0 [5]
H_DSTBP#1 [5]
H_DSTBN#1 [5]
H_DSTBP#2 [5]
H_DSTBN#2 [5]
H_DSTBP#3 [5]
H_DSTBN#3 [5]
Title
Intel Grantsdale_CPU
Size Document Number Re v
Custom
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7177 20
of
833Wednesday, June 22, 2005
1
D D
C C
H_A#[3..31][5]
H_ADSTB#0[5]
H_ADSTB#1[5]
H_PCREQ#[5]
H_BR#0[5]
H_BPRI#[5]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_BNR#[5]
H_LOCK#[5]
H_ADS#[5]
H_REQ#[0..4][5]
H_HIT#[5]
H_HITM#[5]
H_DEFER#[5]
H_TRDY#[5]
H_DBSY#[5]
H_DRDY#[5]
H_EDRDY#[5]
B B
PLRST# active to
H_CPURST# active:1ms
H_RS#[0..2][5]
CK_H_MCH[18]
CK_H_MCH#[18]
MS7_POK[16,24]
H_CPURST#[5]
ICH_SYNC#[16]
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
PLTRST#[15,24]
HXRCOMP
HXSCOMP
HXSWING
MCH_GTLREF
V_2P5_MCH
A A
ICH_SYNC#
R183 20R1%
R228 8.2KR0402
HXRCOMP
V_FSB_VTT
U10A
H29
HA3#
K29
HA4#
J29
HA5#
G30
HA6#
G32
HA7#
K30
HA8#
L29
HA9#
M30
HA10#
L31
HA11#
L28
HA12#
J28
HA13#
K27
HA14#
K33
HA15#
M28
HA16#
R29
HA17#
L26
HA18#
N26
HA19#
M26
HA20#
N31
HA21#
P26
HA22#
N29
HA23#
P28
HA24#
R28
HA25#
N33
HA26#
T27
HA27#
T31
HA28#
U28
HA29#
T26
HA30#
T29
HA31#
J31
HAD_STB0#
N27
HAD_STB1#
E31
HPCREQ#
R33
BREQ0#
E30
BPRI#
M35
BNR#
L33
HLOCK#
M31
ADS#
F33
HREQ0#
E32
HREQ1#
H31
HREQ2#
G31
HREQ3#
F31
HREQ4#
L34
HIT#
N35
HITM#
J35
DEFER#
N34
HTRDY#
L35
DBSY#
M32
DRDY#
P33
HEDRDY#
K34
RS0#
P34
RS1#
J32
RS2#
M23
HCLKP
M22
HCLKN
AG7
PWROK
G24
CPURST#
AF7
RSTIN#
M14
ICH_SYNC#
B23
HDRCOMP
D24
HDSCOMP
A23
HDSWING
A24
HDVREF
R170
60.4R1%0402
VCCNCTF
HS11HS33HS55HS7
7
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
AJ21
AL21
AL20
AK21
AK24
HXSCOMP
C195
X_C2.2P50N0402
VCCNCTF
VCCNCTF
RSVRD
RSVRD
AJ24
AJ23
AK18
V_FSB_VTT
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AJ18
AJ20
VCCNCTF
VCCNCTF
RSVRD
RSVRD
V31
V30
U30
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
V32
Y30
AB29
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
R31
R30
VCCNCTF
VCCNCTF
VCCNCTF
RSVRD
RSVRD
RSVRD
AA31
AA30
AC12
R335
49.9R1%
R166
100R1%
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
P12NCP23NCP24
NC
R12NCR24
RSVRD
AC13
AC14
RSVRD
RSVRD
AC15
RSVRD
AC16
AC17
RSVRD
RSVRD
AC18
RSVRD
AC19
RSVRD
AC20
RSVRD
AC21
AC22
RSVRD
N12NCN22NCN23NCN24
GTLREF VOLTAGE SHOULD BE 0.67*VTT=0.8V
MCH_GTLREF
C185
C189
C0.1U25Y
X_C220P16X0402
VCCNCTF
VCCNCTF
NC
NC
T12
V12
U12
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
NC
Y12
W12
AA12NCAB12
V_FSB_VTT
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
AC23NCAC24NCAN19
VCCNCTF
VCCNCTF
VCCNCTF
NC
AL28
VCCNCTF
VCCNCTF
NC
NC
AG6
AJ14
AH24
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
NC
L19NCL12
P30
AD30
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
VCCNCTF
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
J12
F24NCF12
K12
R173
301R1%
R174
102R1%
E16
H17NCH15NCH12
C16
G12
HD_SWING VOLTAGE "10 MIL TRACE , 7 MIL
SPACE" HD_SWING S/B 1/4*VTT +/- 2%
AR35NCAR34
AR2NCAR1
AP35
PLACE DIVIDER RESISTOR NEAR VTT
HXSWING
C198
C0.01U50X
CAPS SHOULD BE PLACED NEAR MCH PIN
8
7
6
5
4
8
7
6
5
4
3
2
1
SCKE_A[0..3][12,14]
DQM_A[0..7][12]
DATA_A[0..63][12]
DQM_A5
DQM_A6
DQM_A1
DQM_A3
DQM_A2
DQM_A4
AL1
AN7
SADM0
SADM1
SBCKE3
W31
DQM_B7
AH16
SADM2
SADM3
SBDM6
SBDM7
AD24
DQM_B6
DQM_B5
AK29
AG34
SADM4
SBDM5
AH31
AG24
DQM_B4
AA33
SADM5
SBDM4
AG20
DQM_B3
DQM_A7
U33
SBCS0#
SBCS1#
SBCS2#
SADM6
SADM7
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCK0
SBCK0#
SBCK1
SBCK1#
SBCK2
SBCK2#
SBCK3
SBCK3#
SBCK4
SBCK4#
SBCK5
SBCK5#
SBDDR1MA13
SBRCVENOUT#
SBRCVENIN#
SMSLEWIN1
SMSLEWOUT1
SMVREF1
SBDM0
SBDM1
SBDM2
SBDM3
AJ5
AH9
AH13
_B01-915GV15-IX6
DQM_B1
DQM_B2
DQM_B0
SCS_B#0
AN33
SCS_B#1
AM34
SCS_B#2
AP34
SCS_B#3
AN34
RAS_B#
AN17
CAS_B#
AP18
WE_B#
AP17
MAA_B0
AM15
MAA_B1
AR15
MAA_B2
AN15
MAA_B3
AL15
MAA_B4
AP14
MAA_B5
AM12
MAA_B6
AP13
MAA_B7
AL12
MAA_B8
AN13
MAA_B9
AR12
MAA_B10
AP15
MAA_B11
AP11
MAA_B12
AR11
MAA_B13MAA_A13
AL33
ODT_B0
AM33
ODT_B1
AL34
ODT_B2
AL35
ODT_B3
AK34
SBS_B0
AR16
SBS_B1
AN16
SBS_B2
AN11
DQS_B0
AK5
DQS_B#0
AL4
DQS_B1
AK10
DQS_B#1
AH10
DQS_B2
AK13
DQS_B#2
AL14
DQS_B3
AD20
DQS_B#3
AF20
DQS_B4
AH25
DQS_B#4
AG26
DQS_B5
AH28
DQS_B#5
AH30
DQS_B6
AB31
DQS_B#6
AC30
DQS_B7
W27
DQS_B#7
Y28
P_DDR0_B
AH22
N_DDR0_B
AG23
P_DDR1_B
AK9
N_DDR1_B
AL9
P_DDR2_B
AE26
N_DDR2_B
AE25
P_DDR3_B
AL23
N_DDR3_B
AK22
P_DDR4_B
AJ11
N_DDR4_B
AL11
P_DDR5_B
AD28
N_DDR5_B
AD29
AD32
AK15
AN14
SM_YSLEWIN
AF9
AE10
MCH_VREF_B
AE8
PLACE 0.1UF CAP CLOSE TO MCH
3
RAS_B# [13,14]
CAS_B# [13,14]
WE_B# [13,14]
MAA_B[0..13] [ 13,14]
SBS_B[0..2] [13,14]
DQS_B0 [13]
DQS_B#0 [13]
DQS_B1 [13]
DQS_B#1 [13]
DQS_B2 [13]
DQS_B#2 [13]
DQS_B3 [13]
DQS_B#3 [13]
DQS_B4 [13]
DQS_B#4 [13]
DQS_B5 [13]
DQS_B#5 [13]
DQS_B6 [13]
DQS_B#6 [13]
DQS_B7 [13]
DQS_B#7 [13]
P_DDR0_B [13]
N_DDR0_B [13]
P_DDR1_B [13]
N_DDR1_B [13]
P_DDR2_B [13]
N_DDR2_B [13]
P_DDR3_B [13]
N_DDR3_B [13]
P_DDR4_B [13]
N_DDR4_B [13]
P_DDR5_B [13]
N_DDR5_B [13]
C618
C0.1U25Y
VCC_DDR
CP21
X_COPPER
R501 1KR1%
R500 X_0R
MCH_VREF_A
MCH_VREF_B
R502
1KR1%
Title
Intel Gra ntsdale_Memory
Size Document Number Re v
Custom
Date: Sheet
2
MICRO-START INT'L CO.,LTD.
MS-7177 20
of
933Wednesday, June 22, 2005
1
DATA_A0
DATA_A3
DATA_A8
DATA_A7
DATA_A4
DATA_A6
DATA_A2
DATA_A5
D D
C C
B B
SCS_A#[0..3][12,14] SCS_B#[0..3] [13,14]
RAS_A#[12,14]
CAS_A#[12,14]
WE_A#[ 1 2,14]
MAA_A[0..13][12,14]
ODT_A[0..3][12,14] ODT_B[0..3] [13,14]
SBS_A[0..2][12,14]
DQS_A0[12]
DQS_A#0[12]
DQS_A1[12]
DQS_A#1[12]
DQS_A2[12]
DQS_A#2[12]
DQS_A3[12]
DQS_A#3[12]
DQS_A4[12]
DQS_A#4[12]
DQS_A5[12]
DQS_A#5[12]
DQS_A6[12]
DQS_A#6[12]
DQS_A7[12]
DQS_A#7[12]
P_DDR0_A[12]
N_DDR0_A[12]
P_DDR1_A[12]
N_DDR1_A[12]
P_DDR2_A[12]
N_DDR2_A[12]
P_DDR3_A[12]
N_DDR3_A[12]
P_DDR4_A[12]
N_DDR4_A[12]
P_DDR5_A[12]
N_DDR5_A[12]
SCS_A#0
SCS_A#1
SCS_A#2
SCS_A#3
RAS_A#
CAS_A#
WE_A#
MAA_A0
MAA_A1
MAA_A2
MAA_A3
MAA_A4
MAA_A5
MAA_A6
MAA_A7
MAA_A8
MAA_A9
MAA_A10
MAA_A11
MAA_A12
ODT_A0
ODT_A1
ODT_A2
ODT_A3
SBS_A0
SBS_A1
SBS_A2
DQS_A0
DQS_A#0
DQS_A1
DQS_A#1
DQS_A2
DQS_A#2
DQS_A3
DQS_A#3
DQS_A4
DQS_A#4
DQS_A5
DQS_A#5
DQS_A6
DQS_A#6
DQS_A7
DQS_A#7
P_DDR0_A
N_DDR0_A
P_DDR1_A
N_DDR1_A
P_DDR2_A
N_DDR2_A
P_DDR3_A
N_DDR3_A
P_DDR4_A
N_DDR4_A
P_DDR5_A
N_DDR5_A
SM_XSLEWIN
MCH_VREF_A
SMPCOMP_P
SMPCOMP_N
U10B
AR29
SACS0#
AP32
SACS1#
AR28
SACS2#
AN31
SACS3#
AP27
SARAS#
AN29
SACAS#
AN28
SAWE#
AP26
SAMA0
AR24
SAMA1
AL24
SAMA2
AP23
SAMA3
AR23
SAMA4
AP22
SAMA5
AN23
SAMA6
AP21
SAMA7
AN22
SAMA8
AN21
SAMA9
AM27
SAMA10
AM21
SAMA11
AR20
SAMA12
AP31
SAMA13
AP30
SAODT0
AN32
SAODT1
AP29
SAODT2
AP33
SAODT3
AR27
SABA0
AN27
SABA1
AN20
SABA2
AG1
SADQS0
AG2
SADQS0#
AL3
SADQS1
AL2
SADQS1#
AP7
SADQS2
AR7
SADQS2#
AF17
SADQS3
AG17
SADQS3#
AM30
SADQS4
AL29
SADQS4#
AG35
SADQS5
AG33
SADQS5#
AA34
SADQS6
AA35
SADQS6#
U34
SADQS7
U35
SADQS7#
AN26
SACK0
AP25
SACK0#
AM2
SACK1
AM3
SACK1#
AC34
SACK2
AC35
SACK2#
AN25
SACK3
AM24
SACK3#
AN3
SACK4
AN2
SACK4#
AC33
SACK5
AB34
SACK5#
AB33
SADDR1MA13
AH15
SARCVENOUT#
AE16
SARCVENIN#
AJ12
SMSLEWIN0
AK12
SMSLEWOUT0
AE7
SMVREF0
AG8
SMRCOMP1
AG4
SMRCOMP0
R49840.2R1%
AE5
SMOCDCOMP1
R49940.2R1%
AF5
SMOCDCOMP0
MCH_VREF_A
PLACE 0.1UF CAP CLOSE TO MCH
C619
C0.1U25Y
DATA_A1
AE3
SADQ0
AF3
SADQ1
DATA_B0
AH3
SADQ2
SBDQ0
AH4
DATA_B1
AJ2
SADQ3
SBDQ1
AJ6
AE2
SADQ4
SBDQ2
AL6
DATA_B2
AE1
AN6
DATA_B3
AG3
SADQ5
SADQ6
SBDQ3
SBDQ4
AG9
DATA_B4
DATA_B5
AH2
SADQ7
SBDQ5
AH7
DATA_B6
AK2
AL5
DATA_A9
AK3
SADQ8
SADQ9
SBDQ6
SBDQ7
AM5
DATA_B7
DATA_A11
DATA_A10
AN4
SADQ10
SBDQ8
AJ8
DATA_B8
DATA_B9
DATA_A12
AP4
AJ1
SADQ11
SBDQ9
AL8
AF11
DATA_B10
DATA_A14
DATA_A13
AJ3
AP2
SADQ12
SADQ13
SBDQ10
SBDQ11
AJ7
AE11
DATA_B11
DATA_B12
DATA_A15
DATA_A16
AP3
AR5
SADQ14
SADQ15
SBDQ12
SBDQ13
AL7
AG10
DATA_B14
DATA_B13
DATA_A17
DATA_A18
AP6
AP9
SADQ16
SADQ17
SBDQ14
SBDQ15
AF13
AG11
DATA_B15
DATA_B16
DATA_A19
DATA_A20
AN9
AN5
SADQ18
SADQ19
SBDQ16
SBDQ17
AH12
AD14
DATA_B17
DATA_B18
DATA_A21
DATA_A22
AP5
AN8
SADQ20
SADQ21
SBDQ18
SBDQ19
AD15
AD12
DATA_B20
DATA_B19
DATA_A24
DATA_A23
AR8
AL17
SADQ22
SADQ23
SBDQ20
SBDQ21
AE13
AG14
DATA_B21
DATA_B22
DATA_A26
DATA_A25
AJ17
AF19
SADQ24
SADQ25
SBDQ22
SBDQ23
AF14
AK19
DATA_B23
DATA_B24
DATA_A27
AH18
SADQ26
SBDQ24
AH19
DATA_B25
DATA_B[0..63][13]
A A
R503 80.6R1%
8
SMPCOMP_P SMPCOMP_N
VCC_DDR
R504 80.6R1%
C620
C0.1U25Y
7
6
DATA_A29
DATA_A28
AK16
AF16
SADQ27
SADQ28
SBDQ25
SBDQ26
AH21
AD21
DATA_B27
DATA_B26
DATA_A30
DATA_A31
AD17
AE19
SADQ29
SADQ30
SBDQ27
SBDQ28
AL18
AD18
DATA_B28
DATA_B29
DATA_A32
DATA_A33
AK27
AJ28
SADQ31
SADQ32
SBDQ29
SBDQ30
AF22
AE22
DATA_B31
DATA_B30
DATA_A34
DATA_A35
AL31
AK31
SADQ33
SADQ34
SBDQ31
SBDQ32
AF24
AF25
DATA_B32
DATA_B33
DATA_A36
DATA_A37
AH27
AL27
SADQ35
SADQ36
SBDQ33
SBDQ34
AJ26
AL26
DATA_B34
DATA_B35
DATA_A39
DATA_A38
AN30
AL30
SADQ37
SADQ38
SBDQ35
SBDQ36
AF23
AD23
DATA_B36
DATA_B37
DATA_A41
DATA_A40
AH33
AH35
SADQ39
SADQ40
SBDQ37
SBDQ38
AJ25
AL25
DATA_B39
DATA_B38
DATA_A42
DATA_A43
AF33
AE33
SADQ41
SADQ42
SBDQ39
SBDQ40
AJ31
AK32
DATA_B40
DATA_B41
5
DATA_A45
DATA_A44
AJ33
AJ34
SADQ43
SADQ44
SBDQ41
SBDQ42
AF28
AG31
DATA_B42
DATA_B43
DATA_A46
DATA_A47
AG32
AF34
SADQ45
SADQ46
SBDQ43
SBDQ44
AJ29
AK33
DATA_B45
DATA_B44
DATA_A48
DATA_A49
AD31
AD35
SADQ47
SADQ48
SBDQ45
SBDQ46
AG30
AG27
DATA_B46
DATA_B47
DATA_A51
DATA_A50
Y33
W34
SADQ49
SADQ50
SBDQ47
SBDQ48
AF27
AE27
DATA_B48
DATA_B49
SCKE_B[0..3][13,14]
DATA_A52
DATA_A53
AE35
AE34
SADQ51
SADQ52
SBDQ49
SBDQ50
AB26
AC26
DATA_B51
DATA_B50
DATA_A55
DATA_A54
AA32
Y35
SADQ53
SADQ54
SBDQ51
SBDQ52
AE31
AE29
DATA_B52
DATA_B53
DQM_B[0..7][13]
DATA_A56
DATA_A57
V34
V33
SADQ55
SADQ56
SBDQ53
SBDQ54
AB27
AC28
DATA_B55
DATA_B54
DATA_A59
DATA_A58
R32
R34
SADQ57
SADQ58
SBDQ55
SBDQ56
W29
AA28
DATA_B57
DATA_B56
DATA_A61
DATA_A60
W35
W33
SADQ59
SADQ60
SBDQ57
SBDQ58
V28
V29
DATA_B58
DATA_B59
DATA_A63
DATA_A62
T33
T35
SADQ61
SADQ62
SBDQ59
SBDQ60
Y26
AA29
DATA_B61
DATA_B60
SCKE_A0
AP19
SADQ63
SBDQ61
SBDQ62
U26
W26
DATA_B63
DATA_B62
4
SCKE_A1
SCKE_A2
AM18
AN18
SACKE0
SACKE1
SBDQ63
AP10
SCKE_B0
SCKE_A3
AR19
SACKE2
SACKE3
SBCKE0
SBCKE1
AR9
AN10
SCKE_B2
SCKE_B1
DQM_A0
AF2
SBCKE2
AM9
SCKE_B3
8
EXP_A_TXP_[0..15] [21]
EXP_A_TXN_[0..15] [21]
EXP_A_RXP_[0..15] [21]
EXP_A_RXN_[0..15] [21]
H_FSBSEL0
H_FSBSEL1
H_FSBSEL2
V_1P5_CORE
V_2P5_MCH
C193
C0.1U16Y0402
VCCA_MPLL
C219
X_C10U10Y0805
VCCA_DPLLB
EXP_A_RXP_0
EXP_A_RXN_0
EXP_A_RXP_1
EXP_A_RXN_1
EXP_A_RXP_2
EXP_A_RXN_2
EXP_A_RXP_3
EXP_A_RXN_3
EXP_A_RXP_4
EXP_A_RXN_4
EXP_A_RXP_5
EXP_A_RXN_5
EXP_A_RXP_6
EXP_A_RXN_6
EXP_A_RXP_7
EXP_A_RXN_7
EXP_A_RXP_8
EXP_A_RXN_8
EXP_A_RXP_9
EXP_A_RXN_9
EXP_A_RXP_10
EXP_A_RXN_10
EXP_A_RXP_11
EXP_A_RXN_11
EXP_A_RXP_12
EXP_A_RXN_12
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
EXP_A_RXP_15
EXP_A_RXN_15
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
SDVO_CTRL_DATA
SDVO_CTRL_CLK
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
EXP_A_RXP_0[21]
EXP_A_RXN_0[21]
EXP_A_RXP_1[21]
EXP_A_RXN_1[21]
EXP_A_RXP_2[21]
V_FSB_VTT
X_C0.22U16Y
X_C10U10Y0805
8
EXP_A_RXN_2[21]
EXP_A_RXP_3[21]
EXP_A_RXN_3[21]
EXP_A_RXP_4[21]
EXP_A_RXN_4[21]
EXP_A_RXP_5[21]
EXP_A_RXN_5[21]
EXP_A_RXP_6[21]
EXP_A_RXN_6[21]
EXP_A_RXP_7[21]
EXP_A_RXN_7[21]
EXP_A_RXP_8[21]
EXP_A_RXN_8[21]
EXP_A_RXP_9[21]
EXP_A_RXN_9[21]
EXP_A_RXP_10[21]
EXP_A_RXN_10[21]
EXP_A_RXP_11[21]
EXP_A_RXN_11[21]
EXP_A_RXP_12[21]
EXP_A_RXN_12[21]
EXP_A_RXP_13[21]
EXP_A_RXN_13[21]
EXP_A_RXP_14[21]
EXP_A_RXN_14[21]
EXP_A_RXP_15[21]
EXP_A_RXN_15[21]
DMI_ITP_MRP_0[15]
DMI_ITN_MRN_0[15]
DMI_ITP_MRP_1[15]
DMI_ITN_MRN_1[15]
DMI_ITP_MRP_2[15]
DMI_ITN_MRN_2[15]
DMI_ITP_MRP_3[15]
DMI_ITN_MRN_3[15]
CK_PE_100M_MCH[18]
CK_PE_100M_MCH#[18]
SDVO_CTRL_DATA[21]
SDVO_CTRL_CLK[21]
H_FSBSEL0[5,6,18]
H_FSBSEL1[5,6,18]
H_FSBSEL2[5,6,18]
R205 1KR1%0402
R204 X_1KR1%0402
V_2P5_DAC_FILTERED
C215
C260
D D
C C
B B
CP5 X_COPPER
V_1P5_CORE
A A
V_1P5_CORE
L6 X_10U100m_0805
CP11 X_COPPER
L12 X_10U100m_0805
MTYPE
EXP_SLR
C217
C0.1U16Y0402
C251
C0.1U16Y0402
7
V_1P5_CORE
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD10
U10C
E11
F11
J11
H11
F9
E9
F7
E7
B3
B4
D5
E5
G6
G5
H8
H7
J6
J5
K8
K7
L6
L5
P10
R10
M8
M7
N6
N5
P7
P8
R6
R5
U5
U6
T9
T8
V7
V8
V10
U10
A11
B11
K13
J13
H16
E15
D17
M16
F15
C15
A16
B15
C14
K15
L10
M10
A17
B17
A12
B13
A14
A13
E13
D13
F13
C188
C0.1U16Y0402
V_1P5_CORE V_1P5_CORE
V_1P5_CORE
7
EXPARXP0
EXPARXN0
EXPARXP1
EXPARXN1
EXPARXP2
EXPARXN2
EXPARXP3
EXPARXN3
EXPARXP4
EXPARXN4
EXPARXP5
EXPARXN5
EXPARXP6
EXPARXN6
EXPARXP7
EXPARXN7
EXPARXP8
EXPARXN8
EXPARXP9
EXPARXN9
EXPARXP10
EXPARXN10
EXPARXP11
EXPARXN11
EXPARXP12
EXPARXN12
EXPARXP13
EXPARXN13
EXPARXP14
EXPARXN14
EXPARXP15
EXPARXN15
DMI RXP0
DMI RXN0
DMI RXP1
DMI RXN1
DMI RXP2
DMI RXN2
DMI RXP3
DMI RXN3
GCLKINP
GCLKINN
SDVOCTRLDATA
SDVOCTRLCLK
BSEL0
BSEL1
BSEL2
RSVRD
RSVRD
MTYPE
EXP_SLR
RSVRD
RSVRD
RSVRD
DREFSSCLKINP
DREFSSCLKINN
VCCAHPLL
VCCAMPLL
VCCADPLLA
VCCADPLLB
VCCA3GPLL
VCCHV
VCCACRTDAC
VCCACRTDAC
VSSACRTDAC
VCC
C200
C0.1U16Y0402
CP10 X_COPPER
CP6 X_COPPER
AD2
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
F22
F21
F20
E22
E21
H22
G22
G21
L10 X_10U100m_0805
X_C10U10Y0805
L7 X_10U100m_0805
X_C10U10Y0805
AD1
E20
C247
C226
6
AC10
AC9
AC8
AC7
AC2
AC6
AC5
AC4
AC3
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
E19
D22
D21
D20
VTT
C22
D19
C21
C20
C19
VCCA_DPLLA
VCCA_HPLL
6
VTT
AB9
AC1
AB10
VCC
VCC
VCC
VTT
VTT
VTT
B21
B20
B22
C244
C0.1U16Y0402
C223
C0.1U16Y0402
AB4
AB8
AB7
AB6
AB5
AB3
AB2
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
B19
A22
A21
A20
A19
5
VCC_DDR
AR26
AP28
AR33
AR31
AR22
AR18
AR14
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
Y11
V25
V20
V16
V11
W25
W11
L8 10U100m_0805
L9 0R0805
AR10
VCCSM
VCCSM
VSSNCTF
VSSNCTF
U25
U11
X_C10U10Y0805
AB1
VCC
AC25
W18
VCC
VCC
VSSNCTF
VSSNCTF
AB25
U18
V19
V17
VCC
VCC
VCC
VSSNCTF
VSSNCTF
VSSNCTF
Y25
AA25
AA11
V_1P5_CORE
VSSNCTF
Y18
L9 must be 0 ohm, can't use L
5
4
V_1P5_PCIEXPRESS
AM28
AM26
AM25
AP16
VCCSM
AP12
AM23
AN35
AM32
AM22
AM20
AM19
AM11
AM10
AK35
AM17
AM16
AM14
AM13
W1
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCC3GY9VCC3GY8VCC3GY7VCC3GY6VCC3GY5VCC3GY4VCC3GY3VCC3GY2VCC3GY1VCC3GW9VCC3GW8VCC3GW7VCC3GW6VCC3GW4VCC3GW3VCC3GW2VCC3G
EXPATXP0
EXPATXN0
EXPATXP1
EXPATXN1
EXPATXP2
EXPATXN2
EXPATXP3
EXPATXN3
EXPATXP4
EXPATXN4
EXPATXP5
EXPATXN5
EXPATXP6
EXPATXN6
EXPATXP7
EXPATXN7
EXPATXP8
EXPATXN8
EXPATXP9
EXPATXN9
EXPATXP10
EXPATXN10
EXPATXP11
EXPATXN11
EXPATXP12
EXPATXN12
EXPATXP13
EXPATXN13
EXPATXP14
EXPATXN14
EXPATXP15
EXPATXN15
DMI TXP0
DMI TXN0
DMI TXP1
DMI TXN1
DMI TXP2
DMI TXN2
DMI TXP3
DMI TXN3
EXPACOMPO
EXPACOMPI
CRTHSYNC
CRTVSYNC
CRTRED
CRTGREEN
CRTBLUE
CRTREDB
CRTGREENB
CTRBLUEB
CRTDDCDATA
CRTDDCCLK
DREFCLKINP
DREFCLKINN
AP24
AP20
VCCSM
VCCSM
VCCSM
CRTIREF
PMEXTTS
PMBMBUSY#
TESTIN#
MCHDETECT
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
VSSNCTF
T25
T18
T11
P25
P11
R25
R11
N25
N11
N17
M11
AA15
AA17
AA19
AD25
VCCA_GPLL
C250
C258
C228
C0.1U16Y0402
V_1P5_PCIEXPRESS
C232
P16
P18
P20
N19
V_2P5_MCH
C10U10Y0805
X_C10U10Y0805
R17
R19
R21
T22
U15
U21
U23
L11 0.1U400m
4
V22
Y22
W15
W21
W23
C264
C10U10Y0805
_B01-915GV15-IX6
V_2P5_DAC_FILTERED
C252
C0.1U16Y0402
For 915PL: C264 (X)
For 915GL: C264 (Y)
3
V_1P5_CORE
EXP_A_TXP_0
C10
EXP_A_TXN_0
C9
EXP_A_TXP_1
A9
EXP_A_TXN_1
A8
EXP_A_TXP_2
C8
EXP_A_TXN_2
C7
EXP_A_TXP_3
A7
EXP_A_TXN_3
A6
EXP_A_TXP_4
C6
EXP_A_TXN_4
C5
EXP_A_TXP_5
C2
EXP_A_TXN_5
D2
EXP_A_TXP_6
E3
EXP_A_TXN_6
F3
EXP_A_TXP_7
F1
EXP_A_TXN_7
G1
EXP_A_TXP_8
G3
EXP_A_TXN_8
H3
EXP_A_TXP_9
H1
EXP_A_TXN_9
J1
EXP_A_TXP_10
J3
EXP_A_TXN_10
K3
EXP_A_TXP_11
K1
EXP_A_TXN_11
L1
EXP_A_TXP_12
L3
EXP_A_TXN_12
M3
EXP_A_TXP_13
M1
EXP_A_TXN_13
N1
EXP_A_TXP_14
N3
EXP_A_TXN_14
P3
EXP_A_TXP_15
P1
EXP_A_TXN_15
R1
DMI_MTP_IRP_0
R3
DMI_MTN_IRN_0
T3
DMI_MTP_IRP_1
T1
DMI_MTN_IRN_1
U1
DMI_MTP_IRP_2
U3
DMI_MTN_IRN_2
V3
DMI_MTP_IRP_3
V5
DMI_MTN_IRN_3
W5
GRCOMP
Y10
W10
H_SYNC
E12
V_SYNC
D12
R250 11L500m_50
F14
R251 11L500m_50
D14
R252 11L500m_50
H14
G14
E14
J14
3VDDCDA
L14
3VDDCCL
M15
CK_96M_DREF
M13
CK_96M_DREF#
M12
DACREFSET
A15
EXTTS
K16
G16
TP6
R35
To prevent Grantsdale VSYNC and HSYNC signal level issue
TP7
A35
C257
_C0.01U6X0402/20%
3
EXP_A_TXP_0 [2 1]
EXP_A_TXN_0 [21]
EXP_A_TXP_1 [2 1]
EXP_A_TXN_1 [21]
EXP_A_TXP_2 [2 1]
EXP_A_TXN_2 [21]
EXP_A_TXP_3 [2 1]
EXP_A_TXN_3 [21]
EXP_A_TXP_4 [2 1]
EXP_A_TXN_4 [21]
EXP_A_TXP_5 [2 1]
EXP_A_TXN_5 [21]
EXP_A_TXP_6 [2 1]
EXP_A_TXN_6 [21]
EXP_A_TXP_7 [2 1]
EXP_A_TXN_7 [21]
EXP_A_TXP_8 [2 1]
EXP_A_TXN_8 [21]
EXP_A_TXP_9 [2 1]
EXP_A_TXN_9 [21]
EXP_A_TXP_10 [21]
EXP_A_TXN_10 [21]
EXP_A_TXP_11 [21]
EXP_A_TXN_11 [21]
EXP_A_TXP_12 [21]
EXP_A_TXN_12 [21]
EXP_A_TXP_13 [21]
EXP_A_TXN_13 [21]
EXP_A_TXP_14 [21]
EXP_A_TXN_14 [21]
EXP_A_TXP_15 [21]
EXP_A_TXN_15 [21]
DMI_MTP_IRP_0 [15]
DMI_MTN_IRN_0 [15]
DMI_MTP_IRP_1 [15]
DMI_MTN_IRN_1 [15]
DMI_MTP_IRP_2 [15]
DMI_MTN_IRN_2 [15]
DMI_MTP_IRP_3 [15]
DMI_MTN_IRN_3 [15]
V_1P5_PCIEXPRESS
R233
24.9R1%0402
C267
3VDDCDA [22]
3VDDCCL [22]
CK_96M_DREF [18]
CK_96M_DREF# [18]
R207 255R1%
R227 10KR0402
H_SYNC
V_SYNC
C266
C265
V_2P5_MCH
1
2
5
6
CRT_R
CRT_G
CRT_B
C27P50N0402
C27P50N0402
C27P50N0402
VCC3
84
U11A
_NC7WZ08_US8
VCC3
84
U11B
_NC7WZ08_US8
2
C222
C273
VCC_DDR
C175 C10U10Y0805
C170 X_C10U10Y0805
C218 X_C10U10Y0805
C196 C10U10Y0805
C171 X_C10U10Y0805
C231 C10U10Y0805
MCH MEMORY DECOUPLING
From NB to 1th 150 ohm : 12 mil
From 1th to 2th 150 ohm : 7 mil
CRT_R
CRT_G
CRT_B
CRT_R [22]
CRT_G [22]
CRT_B [22]
7
CRT_HSYNC [22]
C270
C0.1U16Y0402
3
CRT_VSYNC [22]
2
1
C10U10Y0805
C10U10Y0805
R218 150R1%0402
R216 150R1%0402
R213 150R1%0402
For 915P / 915PL
CRT_R
R477 X_0R0402
CRT_G
R478 X_0R0402
CRT_B
R479 X_0R0402
DACREFSET
R480 X_0R0402
CK_96M_DREF
R481 X_0R0402
H_SYNC
R482 X_0R0402
V_SYNC
R483 X_0R0402
3VDDCDA
R484 X_0R0402
3VDDCCL
CK_96M_DREF#
Title
Size Document Number Rev
Custom
Date: Sheet
MICRO-START INT'L CO.,LTD.
Intel Grantsdale_PCI EXPRESS & RGB
MS-7177 20
R485 X_0R0402
R486 X_0R0402
V_2P5_MCH
of
10 33Wednesday, June 22, 2005
1
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