MSI MS-7169 Schematics
5
4
3
2
1
CONTENT
Cover Sheet
D D
C C
B B
GPIO SPEC
AMD K8->754-A,B,C
System Memory
DDR DIMM 1 & 2
DDR Terminations R & C
DDR Damping R & Bypass Cap.
Clock Synthesizer ICS950405
NB VIA K8M800/K8T800 PRO (HT)
K8 Core Power(HIP6568CR)
VIA VT8237R
FAN & Digital Temperature Sensor
AGP SLOT 8X
PCI slot 1 & 2 & 3
AC'97 Audio - ALC655
ATA 66 / 100 / 133
USB Connectors
LPC I/O - W83627EHF & FWH
VGA Connector & KeyBoard / Mouse Port
LPT / COM Port
VIA VT6103L 10/100 Base-T LAN
ACPI Power Controller ( MS-6 )
Front Pannel & Power OK Circuit & System Voltage
SHEET
1
2Block diagram
3
4-6
7
8
9
10
11-13
14
15-17
18
19
20
21
22
23
24
25
26
27
28
29
MS-7169
CPU:
System Chipset:
On Board Chipset:
Main Memory:
Expansion SLOT
Intersil PWM:
AMD PGA 754 K8-Processor
K8M800 / K8T800Pro (North Bridge)
VIA VT8237R (South Bridge)
BIOS --LPC FLASH 4Mb
AC'97 Codec -- ALC655
LPC Super I/O -- Winbond W83627EHF
CLOCK -- ICS950405
VIA VT6103L 10/100 Base-T LAN
DDR DIMM * 2
AGP SLOT * 1 ( 8X )
PCI 2.3 SLOT * 3
Controller: HIP6568CR
Version 0A
Regulators
Decoupling Cap
A A
Power Delivery
Manual Parts
Revision History
5
4
30
31
32
33
MSI
Title
Size Document Number Rev
3
2
Date: Sheet of
MICRO-STAR
Cover Sheet
MS-7169
1
00A
33Tuesday, January 25, 2005
1
5
Block Diagram
4
3
2
1
D D
CPUCLK+ & CPUCLK-(100/133/166/200)
AMD K8 Socket 754
DDR400
HCLK+ & HCLK-(100/133/166/200) / GCLK(66)
SYSTEM CLOCK
Synthesizer /
ICS950405
C C
AGPCLK(66)
A
G
AGP 8X /Fast Write
P
S
L
O
T
VIA
HT
DDR * 2
K8M800/K8T800 pro
VCLK(66) / OSC(14) / PCISB(33) / USBCLK(48) / APICCLK(14)
VLINK
PCICLK[1~3]
B B
3 PCI Slots
PCI-33
MII
VT8237R
Dual ATA 100/133
LPC BUS
IDE Slot
==>ATA66,100,133 *2
ALC655
AC97
Keyboard
Mouse
Floopy
USB
VIA
VT6103L
10/100
A A
AC_14(14)
Base-T LAN
SERIAL ATA *2
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *4 ,
Back-Port *4
Parallel
Serial
SUPER I/O
W83627EHF
LPC
BUS
SIOPCLK(33)/SIO48M(48)
5
4
3
2
4M ROM
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR
Block Diagram
MS-7169
1
33Wednesday, January 12, 2005
2
00A
5
4
3
2
1
GPIO FUNCTION
VT8237 GPIO Function Define
PIN NAME
D D
GPO0 (VSUS33)
GPO1 (VSUS33)
NA
NA
GPO2/SUSA#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
NA (Exteranl Pull up to 3VDUAL)
HT_SEL0
HT_SEL1
GPO7/GNT5#
GPO8/GPI8/VGATE
GPO9/GPI9/IPBIN1
C C
GPI10/GPO10/APICD0
GPI11/GPO11/APICD1
GPO12/GPI12/INTE#
GPO13/GPI13/INTF#
APICD0
APICD1
BIOS_WP# for Lenovo
BIOS_boot block protect for Lenovo
GPO14/GPI14/INTG#
GPO15/GPI15/INTH#
GPO16/SA16/STRAP
GPO17/SA17/STRAP
GPO18/SA18/STRAP
GPO19/SA19/STRAP
GPO20/GPI20
/ACSDIN2/PCS0#/EI
B B
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/GHI#
GPO23/GPI23/DPSLP#
DPSLP#
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOB
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
VIDSEL/SATALED#
GPO29/GPI29/
VRDSLP
GPO30/GPI30/GPIOC
A A
SATALED#
GPO31/GPI31/GPIOD
(Exteranl Pull up to 3V)
(Exteranl Pull up to 3V)
SUSA#
SUSST#
(Exteranl Pull up to 3V)
(Exteranl Pull up to 3V)
LDTSTOP#
VGATE
NA
(Exteranl Pull up to VCC3)
(Exteranl Pull up to VCC3)
As GPO:H=>can flash(default)
As GPO:L=>can't flash Pull up to VCC3
NA
(Exteranl Pull up to VCC)
(Exteranl Pull up to VCC)
NA
LDT Freq Strapping Bit0
LDT Freq Strapping Bit1
LDT Width (Low=8 Bit)
Fast Command (Low=Disable)
NA
NA
GHI#
(Exteranl Pull up to VCC3)
(Exteranl Pull up to VCC3)
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
(Exteranl Pull up to VCC3)
NA
NA
NA
PIN NAME Function defineFunction define
GPI0
GPI1
GPI2/EXTSMI#
GPI3/RING#
GPI4/LID#
GPI5/BATLOW#
GPI6/AGPBZ#
GPI7/REQ#5
GPI16/INTRUDER#
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPI19/IORDY
As GPO:H=>Boot block can be flash
As GPO:L=>can't flash boot block(default)
THERM_ALERT#
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
(Exteranl Pull up to 3VDUAL)NA
AGPBZ#
(Exteranl Pull up to 3VDUAL)
NA
(Exteranl Pull up to VBAT)
NA
NA (Exteranl Pull up to 3VDUAL)
THRM#
(Exteranl Pull up to VCC3)NA
Pull up to VCC3
S/IO GPIO Function Define
PIN NAME
SUSB#/GP52
Function define
SUSB#
FWHUB FUNCTION DEFINE
PCI Routing
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
IDSEL
AD17
AD18
AD19
REQ#/GNT#
PREQ#0
PGNT#0
PREQ#1
PGNT#1
PREQ#2
PGNT#2
CLOCK
PCICLK1
PCICLK2
PCICLK3
PIN NAME Function define
MSI
Title
Size Document Number Rev
5
4
3
2
Date: Sheet of
MICRO-STAR
GPIO Spec.
MS-7169
1
00A
33Saturday, February 05, 2005
3
5
4
3
2
1
C2550 X_C1000P50N
VREF routed as 40~50 mils trace wide ,
D D
C C
B B
A A
Space>25 mils
DDR_VREF<7>
VCC_DDR
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
R2067 15R1%
R2068 15R1%
MD[63..0]<9>
DM[7..0]<9>
AE13
C1000P50X
AG12
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17 MAA3
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
AJ10
MD7
AH11
MD6
AJ11
MD5
AH15
MD4
AJ15
MD3
AG11
MD2
AJ12
MD1
AJ14
MD0
AJ16
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
AH13
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
AJ13
-MDQS[7..0]<9>
5
C2048
X_C1000P50N
VTT_SENSE
MEMVREF1
D14
MEMZN
C14
MEMZP
A16
MEMDATA63
B15
MEMDATA62
A12
MEMDATA61
B11
MEMDATA60
A17
MEMDATA59
A15
MEMDATA58
C13
MEMDATA57
A11
MEMDATA56
A10
MEMDATA55
B9
MEMDATA54
C7
MEMDATA53
A6
MEMDATA52
C11
MEMDATA51
A9
MEMDATA50
A5
MEMDATA49
B5
MEMDATA48
C5
MEMDATA47
A4
MEMDATA46
E2
MEMDATA45
E1
MEMDATA44
A3
MEMDATA43
B3
MEMDATA42
E3
MEMDATA41
F1
MEMDATA40
G2
MEMDATA39
G1
MEMDATA38
L3
MEMDATA37
L1
MEMDATA36
G3
MEMDATA35
J2
MEMDATA34
L2
MEMDATA33
M1
MEMDATA32
W1
MEMDATA31
W3
MEMDATA30
AC1
MEMDATA29
AC3
MEMDATA28
W2
MEMDATA27
Y1
MEMDATA26
AC2
MEMDATA25
AD1
MEMDATA24
AE1
MEMDATA23
AE3
MEMDATA22
AG3
MEMDATA21
AJ4
MEMDATA20
AE2
MEMDATA19
AF1
MEMDATA18
AH3
MEMDATA17
AJ3
MEMDATA16
AJ5
MEMDATA15
AJ6
MEMDATA14
AJ7
MEMDATA13
AH9
MEMDATA12
AG5
MEMDATA11
AH5
MEMDATA10
AJ9
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
R1
MEMDQS17
A13
MEMDQS16
A7
MEMDQS15
C2
MEMDQS14
H1
MEMDQS13
AA1
MEMDQS12
AG1
MEMDQS11
AH7
MEMDQS10
MEMDQS9
T1
MEMDQS8
A14
MEMDQS7
A8
MEMDQS6
D1
MEMDQS5
J1
MEMDQS4
AB1
MEMDQS3
AJ2
MEMDQS2
AJ8
MEMDQS1
MEMDQS0
VTT_DDR_SUS
U2004B
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
RSVD_MEMADDA15
RSVD_MEMADDA14
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
MCKE0 <7,8>
MCKE1 <7,8>
MEMCLK_H7 <7,8>
MEMCLK_L7 <7,8>
MEMCLK_H6 <7,8>
MEMCLK_L6 <7,8>
MEMCLK_H5 <7,8>
MEMCLK_L5 <7,8>
MEMCLK_H4 <7,8>
MEMCLK_L4 <7,8>
MEMCLK_H1 <7,8>
MEMCLK_L1 <7,8>
MEMCLK_H0 <7,8>
MEMCLK_L0 <7,8>
-MCS3 <7,8>
-MCS2 <7,8>
-MCS1 <7,8>
-MCS0 <7,8>
-MSRASA <7,8>
-MSCASA <7,8>
-MSWEA <7,8>
MEMBANKA1 <7,8>
MEMBANKA0 <7,8>
MAA[13..0] <7,8>
-MSRASB <7,8>
-MSCASB <7,8>
-MSWEB <7,8>
MEMBAKB1 <7,8>
MEMBAKB0 <7,8>
MAB[13..0] <7,8>
VCC1_2HT
C0.22U16Y
C2174
X_C0.22U16Y
VCC1_2HT
CADIP[0..15]<11>
CLKIP1<11>
CLKIN1<11>
CLKIP0<11>
CLKIN0<11>
VLDT0
R2034 49.9R1%
CTLIP0<11>
CTLIN0<11>
3
R2038 49.9R1%
CADIP15
CADIN15
CADIP14
CADIN14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
CTLIP1
CTLIN1
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
C2218
C0.22U16Y
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
T27
T28
V29
U29
V27
V28
Y29
W29
Y25
W25
Y27
Y28
R27
R26
T29
R29
X_C0.22U16Y
C2189
U2004A
N12-7540010-F02
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
HYPER TRANSPORT - LINK0
2
C2173
C2203
C0.22U16Y
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
C2382
C0.22U16Y
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
C2190
C0.22U16YC2062
VLDT0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
CADOP15
N26
CADON15
N27
CADOP14
L25
CADON14
M25
CADOP13
L26
CADON13
L27
CADOP12
J25
CADON12
K25
CADOP11
G25
CADON11
H25
CADOP10
G26
CADON10
G27
CADOP9
E25
CADON9
F25
CADOP8
E26
CADON8
E27
CADOP7
N29
CADON7
P29
CADOP6
M28
CADON6
M27
CADOP5
L29
CADON5
M29
CADOP4
K28
CADON4
K27
CADOP3
H28
CADON3
H27
CADOP2
G29
CADON2
H29
CADOP1
F28
CADON1
F27
CADOP0
E29
CADON0
F29
CLKOP1
J26
CLKON1
J27
CLKOP0
J29
CLKON0
K29
N25
P25
CTLOP0
P28
CTLON0
P27
MSI
Title
Size Document Number Rev
Date: Sheet of
VLDT0 <5>
CADOP[0..15] <11>
CADON[0..15] <11>CADIN[0..15]<11>
CLKOP1 <11>
CLKON1 <11>
CLKOP0 <11>
CLKON0 <11>
CTLOP0 <11>
CTLON0 <11>
MICRO-STAR
K8 DDR & HT
MS-7169
C2069
C4.7U10Y0805
1
4 33Friday, February 18, 2005
00A
5
D D
VDDA_25
C2221
X_C0.1U25Y
4
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
VDDA_25
traces to exit ball field) and 500 mils long.
FB2005 300L700m_250_0805
CPU_VDDA_25
3
C4.7U10Y0805
C2070
C2053
C0.22U16Y
C2068
C3300P50X
2
1
AH25
C2043
C2073
C1000P50X
NC_C18
NC_A19
TDO
X_C1000P50N
VCC_DDR
1 2
3 4
5 6
7 8
C2072
C1000P50X
VDDA_25 VCC_DDR
VDDA_25
C C
PS_OUT#<28,29>
B B
A A
DBREQ_L
DBRDY
TCK
TMS
TDI
TRST_L
NC_C21
NC_AJ18
NC_AG17
NC_D18
NC_B19
NC_C19
NC_D20
5
-LDTSTOP
NC_AH18
NC_AG18
R2018
1KR
Q2024
X_NDS7002AS
R2026 X_1KR
R2027 X_1KR
RN2036 X_8P4R-1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R2309 X_1KR
R2310 X_1KR
HDT Test Port Signal .
1 2
3 4
5 6
7 8
VDDA_25
C2220
C4.7U10Y0805
RN2008
8P4R-680R
RN2035
8P4R-680R
CPU_PWRGD<28>
VLDT0
4
R2033 44.2R1%
R2032 44.2R1%
VLDT0<4>
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
CPU_RST#<29>
-LDTSTOP<11,17>
COREFB_H<14>
COREFB_L<14>
Differential , "10:10:5:10:10" .
CPUCLK0_H<10>
Near CPU in 0.5" .
CPUCLK0_L<10>
VDDIO_SENSE
C2047
C2544
X_C1000P50N
X_C1000P50N
8P4R-1KR
RN2038
3
C2057 C392p
C2056 C392p
VTT_DDR_SUS
VCC_DDR
CPU_PWRGD
L0_REF1
L0_REF0
VDDIO_SENSE
R2035
R2025 820R
R2039 820R
7 8
169R1%
3 4
5 6
RN2004
1 2
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
X_8P4R-1KR
AJ25
AF20
AE18
AJ27
AF27
AE26
A23
A24
B23
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
C16
AG15
AH17
C15
E20
E17
B21
A21
C18
A19
A28
AJ28
AE23
AF23
AF22
AF21
AA2
AG2
B18
AH1
AE21
C20
AG4
AG6
AE9
AG9
C1
J3
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
U2004C
THERMTRIP_L
G_FBCLKOUT_H
G_FBCLKOUT_L
2
THERMDA
THERMDC
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
VID4
VID3
VID2
VID1
VID0
TDO
A20
A26
A27
AG13
AF14
AG14
AF15
AE15
AG18
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
CPU_THRIP#
THERMDA_CPU
THERMDC_CPU
CPU_THRIP# <18,28>
THERMDA_CPU <18,24>
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
FBCLKOUT_H
R2040
80.6R1%
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
R2302
X_0
follow AMD checklist
THERMDC_CPU <18,24>
VID4 <14>
VID3 <14>
VID2 <14>
VID1 <14>
VID0 <14>
LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )
VCC_DDR
MSI
Title
Size Document Number Rev
Date: Sheet of
K8 HDT & MISC
MS-7169
THERMDC_CPU
FB2006
X_120S/0603
close to U2004
MICRO-STAR
1
5 33Tuesday, February 22, 2005
00A
5
U2004E
GROUND
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
VCORE
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
AA21
AC21
AB22
AD22
AA23
AC23
AB24
AD24
AH24
AE25
GNDGND
H18
B20
E21
H22
J23
H24
F26
V10
G13
K14
Y14
G15
J15
H16
K16
Y16
G17
J17
F18
K18
Y18
E19
G19
J19
F20
H20
K20
M20
P20
T20
V20
Y20
G21
J21
L21
N21
R21
U21
W21
F22
K22
M22
P22
T22
V22
Y22
E23
G23
L23
N23
R23
U23
W23
B24
D24
F24
K24
M24
P24
T24
V24
Y24
K26
P26
V26
U2004D
L7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
N7
VDD10
L9
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD39
VDD38
VDD37
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
POWER
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
D D
C C
B B
A A
AG27
AA10
AE16
AA20
AC20
AE20
AG20
AJ20
AD21
AG21
AG29
AA22
AC22
AG22
AH22
AJ22
AB23
AD23
AG23
AA24
AC24
AG24
AJ24
AD26
AF26
AH26
AB17
AD17
AA18
AC18
AB19
AD19
AF19
5
AF2
AA8
AB9
J12
B14
Y15
J18
G20
R20
U20
W20
D21
F21
H21
K21
M21
P21
T21
V21
Y21
B22
E22
G22
J22
L22
N22
R22
U22
D23
F23
H23
K23
P23
T23
V23
Y23
E24
G24
J24
N24
R24
U24
W24
B25
C25
B26
D26
H26
M26
T26
Y26
C27
B28
D28
G28
F15
H15
B16
G18
D19
F19
H19
K19
Y19
J20
L20
N20
VSS9
D2
VSS10
VSS11
W6
VSS12
Y7
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS187
VSS188
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
4
VCC_DDR
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
VCC_DDR
C2547
3
Place between DIMN1 & 2
VCC_DDR
C2163
C2139
C2169
C0.1U10X_0402
C0.1U10X_0402
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer, 2
in middle of HT link, and 12 along bottom left side of Claw-hammer.
C2200
C2145
C0.1U10X_0402
GND
C0.1U10X_0402
C0.1U10X_0402
2
RECOMMEND 4 PLACEDIN TOP SOCKET CAVITY
AND 2 ON THE BOTTOM DIRECTLY UNDER
SOCKET CAVITY
106P/1206
C2538
X_106P/1206
C2539
106P/1206
X_106P/1206
C2541
C2540
1
VCOREVCORE
C2542
106P/1206_B
BOTTOM
C2543
106P/1206_B
VCORE
C2519
{nopop}
X_C1U16Y
VCORE
C2515
{nopop}
X_C6.8P50N
C2514
C2066
X_C1U16Y
X_C6.8P50N
In CPU.
C2067
X_C6.8P50N
GND
VTT_DDR_SUS
C2509
X_C0.1U25Y
C2207
X_C0.1U25Y
GND
X_C0.22U16Y
C2113
C2127
C2133
C2136
C2116
C0.22U16Y
X_C0.22U16Y
C0.22U16Y
C0.22U16Y
C2117
C0.22U16Y
VCC_DDR VTT_DDR_SUS
C2140
X_C0.22U16Y
{nopop}
U2004F
1
GND
2
LAYOUT: Place beside processor.
{nopop}
C2548
C2549
C2148
X_C4.7U10Y0805
X_C4.7U10Y0805
X_C4.7U10Y0805
C2078
C2100
C2235
C1U16Y
C1U6.3Y_0402
C4.7U10Y0805
C4.7U10Y0805
C2256
C1U16Y0805
C2271
C2185
X_C1U16Y0805
X_C1U16Y0805
C2223
C2106
X_C0.22U16Y
C2119
C0.22U16Y
{nopop}
C2181
C2093
C1000P50X
C4.7U10Y0805
C2277
C0.22U16Y
C1U6.3Y_0402
C2155
C2545
C2546
C0.22U16Y
X_C0.22U16Y
X_C0.22U16Y
GND
MSI
GND
3
GND
4
GND
5
GND
6
GND
7
GND
8
GND
9
GND
10
GND
775 776
GND GND
GND
Title
Size Document Number Rev
3
2
Date: Sheet of
11
GND
12
GND
13
GND
14
GND
15
GND
16
GND
17
GND
18
GND
19
GND
20
GND
MICRO-STAR
K8 POWER & GND
MS-7169
1
6 33Monday, February 21, 2005
00A
5
4
3
2
1
VCC_DDR
738467085
108
120
148
168223054627796
104
D D
C C
B B
DR_MD[63..0]<8,9>
VCC_DDR
R2106 4.7KR
DDR_VREF
VREF routed as 40~50
mils trace wide ,
Space>25 mils
-MSWEA<4,8>
C2041
C0.1U25Y
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
Place 104p and 1000p Cap. near the DIMM
Place near the DIMM
VCC_DDR
R2017
A A
1KR1%
R2016
1KR1%
5
C2506
X_C0.1U25Y
DDR_VREF
C2040
C1U10Y
VREF routed as 40~50 mils trace wide ,
Space>25 mils
DDR_VREF <4>
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VSS0
VSS1
VSS2
VSS3
VSS4
3111826344250586674818993
4
VDDQ5
DDR DIMM
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
DIMM1 SLAVE ADDRESS
= (10100000)B = A0
SYSTEM MEMORY
112
128
136
143
156
164
172
1801582
184
VDDQ11
VDDQ12
VDDQ13
VDDQ14
184
PIN
NC(RESET#)
VSS17
VSS18
VSS19
VSS20
139
145
152
160
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
DDR1
DIMM-184_green
176
N13-1840051-A10
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
157
158
71
163
5
14
25
36
56
67
78
86
47
103
48
43
41
130
37
32
125
29
122
27
141
118
115
167
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
SOCKET
VSS12
VSS13
VSS14
VSS15
VSS16
100
116
124
132
-MCS0
-MCS0 <4,8>
-MCS1
-MCS1 <4,8>
-DR_MDQS0
-DR_MDQS0 <8,9>
-DR_MDQS1
-DR_MDQS1 <8,9>
-DR_MDQS2
-DR_MDQS2 <8,9>
-DR_MDQS3
-DR_MDQS3 <8,9>
-DR_MDQS4
-DR_MDQS4 <8,9>
-DR_MDQS5
-DR_MDQS5 <8,9>
-DR_MDQS6
-DR_MDQS6 <8,9>
-DR_MDQS7
-DR_MDQS7 <8,9>
MAA[13..0]
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12 MAB12
MAA13
SMBCLK
SMBDATA
MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7
MCKE0
MCKE1
-MSCASA
-MSRASA
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
MAA[13..0] <4,8>
MEMBANKA0 <4,8>
MEMBANKA1 <4,8>
SMBCLK <10,16,18,24,28>
SMBDATA <10,16,18,24,28>
MEMCLK_H5 <4,8>
MEMCLK_L5 <4,8>
MEMCLK_H0 <4,8>
MEMCLK_L0 <4,8>
MEMCLK_H7 <4,8>
MEMCLK_L7 <4,8>
MCKE0 <4,8>
MCKE1 <4,8>
-MSCASA <4,8>
-MSRASA <4,8>
DR_DM[7..0]
3
DR_DM[7..0] <8,9>
VCC_DDR
-MSWEB<4,8>
R2109 4.7KR
DDR_VREF
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VCC_DDR
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VSS0
VSS1
VSS2
VSS3
VSS4
3111826344250586674818993
DIMM2 SLAVE ADDRESS
= (10100001)B = A1
2
104
112
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
DDR DIMM
SOCKET
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
100
128
136
143
156
164
172
1801582
184
VDDQ7
VDDQ8
VSS13
VSS14
116
VDDQ9
VSS15
124
VDDQ10
VSS16
132
VDDID
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDSPD
-MCS2
157
CS0#
158
CS1#
71
CS2#
163
CS3#
-DR_MDQS0
5
DQS0
-DR_MDQS1
14
DQS1
-DR_MDQS2
25
DQS2
-DR_MDQS3
36
DQS3
-DR_MDQS4
56
DQS4
-DR_MDQS5
67
DQS5
-DR_MDQS6
78
DQS6
-DR_MDQS7
86
DQS7
47
DQS8
103
FETEN
48
A0
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
A10_AP
118
A11
115
A12
167
A13
MEMBAKB0
59
BA0
MEMBAKB1
52
BA1
113
BA2
92
SCL
91
SDA
PIN
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
176
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
DDR2
DIMM-184_green
N13-1840051-A10
184
NC(RESET#)
VSS17
VSS18
VSS19
VSS20
139
145
152
160
MSI
Title
Size Document Number Rev
Date: Sheet of
-MCS2 <4,8>
-MCS3
-MCS3 <4,8>
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB13
MEMBAKB0 <4,8>
MEMBAKB1 <4,8>
SMBCLK
SMBDATA
VCC_DDR
MCKE0
MCKE1
-MSCASB
-MSCASB <4,8>
-MSRASB
-MSRASB <4,8>
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
MICRO-STAR
DDR DIMM1&2
MS-7169
1
MAB[13..0] <4,8>
MEMCLK_H4 <4,8>
MEMCLK_L4 <4,8>
MEMCLK_H1 <4,8>
MEMCLK_L1 <4,8>
MEMCLK_H6 <4,8>
MEMCLK_L6 <4,8>
7 33Monday, February 21, 2005
00A
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS
DR_MD44
DR_MD35
D D
DR_MD59
DR_MD63
DR_MD62
DR_MD58
-DR_MDQS7
DR_DM7
DR_MD57
DR_MD61
DR_MD60
DR_MD56
DR_MD51
DR_MD55
C C
B B
MEMBAKB0<4,7>
MEMBANKA0<4,7>
DR_MD50
DR_MD54
-DR_MDQS6
DR_DM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD48
DR_MD49
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_DM5
DR_MD41
-MCS1
-MCS1<4,7>
-MCS0
-MCS0<4,7>
-DR_MDQS5
-MSCASA
-MSCASA<4,7>
-MSWEB
-MSWEB<4,7>
DR_MD45
-MSRASB
-MSRASB<4,7>
-MSRASA
-MSRASA<4,7>
DR_MD37
DR_MD33
RN2061 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2059 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2057 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2055 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2053 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2052 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2050 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2047 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2045 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2039 8P4R-47R0402
7 8
5 6
3 4
1 2
MEMBAKB1<4,7>
MEMBANKA1<4,7>
DR_MD40
DR_MD39
DR_MD38
DR_MD34
DR_DM4
-DR_MDQS4
DR_MD36
DR_MD32
MAB0
MAB10
MAA10
MAA0
MAA2
MAB2
DR_MD30
MAA3
MAA4
MAA6
MAB6
MAB5
DR_MD26
DR_DM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
MAB3
MAB4
MAA5
MAA8
DR_MD24
DR_MD19
VTT_DDR_SUS
RN2044 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2041 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2037 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2034 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2032 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2028 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2030 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2029 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2026 8P4R-47R0402
7 8
5 6
3 4
1 2
DR_MD23
MAB8
MAB7
DR_MD22
MAA11
MAB11
MAB9
DR_MD21
DR_MD18
MAA7
MAA9
DR_DM2
-DR_MDQS2
DR_MD17
MAA12
MAB12
DR_MD16
DR_MD11
MCKE0<4,7>
MCKE1<4,7>
DR_MD20
DR_MD10
DR_MD15
DR_MD14
DR_DM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD6
DR_MD7
DR_MD2
DR_DM0
-DR_MDQS0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
DR_MD27
DR_MD31
MAB1
MAA1
RN2023 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2020 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2021 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2018 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2016 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2014 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2013 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2009 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2006 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2002 8P4R-47R0402
7 8
5 6
3 4
1 2
RN2033 8P4R-47R0402
7 8
5 6
3 4
1 2
VTT_DDR_SUS
-MCS3
-MCS3<4,7>
-MCS2
-MCS2<4,7>
-MSCASB
-MSCASB<4,7>
-MSWEA
-MSWEA<4,7>
RN2049 8P4R-47R0402
7 8
5 6
3 4
1 2
DR_DM[7..0]<7,9>
A A
For DIMM2 Clock
MEMCLK_H4<4,7> MEMCLK_L5 <4,7>
MEMCLK_H1<4,7>
MEMCLK_H6<4,7>
5
MEMCLK_H4
MEMCLK_H1
R2311 120RST
R2312 120RST
R2313 120RST R2316 120RST
MEMCLK_L4
MEMCLK_L1
MEMCLK_L6MEMCLK_H6
MEMCLK_L4 <4,7>
MEMCLK_L1 <4,7>
MEMCLK_L6 <4,7>
4
For DIMM1 Clock
MEMCLK_H5<4,7>
MEMCLK_H7<4,7>
MEMCLK_H0<4,7>
MEMCLK_H5
MEMCLK_H7
R2314 120RST
R2315 120RST
3
MEMCLK_L5
MEMCLK_L7
MEMCLK_L0MEMCLK_H0
MEMCLK_L7 <4,7>
MEMCLK_L0 <4,7>
-DR_MDQS[7..0]<7,9>
DR_MD[63..0]<7,9>
MAB[13..0]<4,7>
MAA[13..0]<4,7>
DR_DM[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
2
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR
DDR Terminations Part 1
MS-7169
1
8 33Saturday, February 05, 2005
00A
5
4
3
2
1
C2260
C2084
GND
C2287
X_C0.1U25Y
C2208
X_C0.1U25Y
C2240
C1U25Y
C2180
C1U25Y
C2152
X_C0.1U25Y
C2156
C1U25Y
C2108
C1U25Y
X_C0.1U25Y
X_C0.1U25Y
C2188
C2269
C2138
C1U16Y0805
VCC_DDR VCC3
C2296
X_C0.1U25Y
C2232
X_C0.1U25Y
C2098
VCC5
X_C0.1U25Y
C2020
X_C0.1U25Y
C2217
X_C0.1U25Y
C2039
X_C0.1U25Y
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVCC_DDR VCC_DDR VCC_DDRVCC_DDR
C2115
X_C0.1U25Y
C2300
C0.1U25Y
C2081
C1U25Y
C2134
X_C0.1U25Y
C2224
X_C0.1U25Y
C2246
X_C0.1U25Y
X_C0.1U25Y
C1U25Y
C2252
C2251
VCC_DDR
C2042
C2186
X_C0.1U25Y
X_C0.1U25Y
C2275
C2226
C1U10Y
C1U25Y
LAYOUT: Locate close to
Dimm2 socket.
C2367
C2088
C0.1U25Y
C0.1U25Y
2
C1U25Y
X_C1U10Y
C2065
C2282
C2233
GND
X_C0.1U25Y
X_C0.1U25Y
C2191
C0.1U25Y
GND
C2285
C2234
VCC_DDR
C2227
C0.1U25Y
C2121
C0.1U25Y
C2178
C0.1U25Y
C2281
C0.1U25Y
C2262
C0.1U25Y
C2179
C0.1U25Y
C2248
X_C0.1U25Y
C2293
C0.1U25Y
GND
C2201
C2213
C1U10Y
C2243
X_C0.1U25Y
C0.1U25Y
C2219
C1U10Y
X_C1U10Y
C1U25Y
X_C0.1U25Y
GND
C2245
C2299
C0.1U25Y
C0.1U10X_0402
GND
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR
DDR Terminations Part 2
MS-7169
1
00A
33Tuesday, February 22, 2005
9
LAYOUT: Locate close
MD38
R2079 10R0402
RN2040 8P4R-10R0402
1 2
3 4
D D
C C
B B
DDR Terminations
-MDQS0 -DR_MDQS0
R2029 10R0402
RN2003 8P4R-10R0402
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN2007 8P4R-10R0402
DM0
1 2
3 4
MD7
5 6
MD6
7 8
RN2010 8P4R-10R0402
1 2
MD8 DR_MD8
3 4
MD9 DR_MD9
5 6
7 8
MD15
R2051 10R0402
RN2011 8P4R-10R0402
-MDQS1
1 2
MD13 DR_MD13
3 4
DM1
5 6
MD14 DR_MD14
7 8
RN2019 8P4R-10R0402
MD17
1 2
-MDQS2
3 4
MD21 DR_MD21
5 6
DM2
7 8
MD18
R2052 10R0402
RN2015 8P4R-10R0402
MD10
1 2
MD20
3 4
MD11
5 6
MD16 DR_MD16
7 8
RN2024 8P4R-10R0402
1 2
MD23 DR_MD23
3 4
5 6
MD24
7 8
RN2027 8P4R-10R0402
1 2
MD29
3 4
5 6
-MDQS3
7 8
RN2031 8P4R-10R0402
MD26
1 2
3 4
MD31
5 6
MD27
7 8
DR_MD0
DR_MD4
DR_MD5
DR_MD1
DR_DM0
DR_MD2MD2
DR_MD7
DR_MD6
DR_MD3MD3
DR_MD12MD12
DR_MD15
-DR_MDQS1
DR_DM1
DR_MD17
-DR_MDQS2
DR_DM2
DR_MD18
DR_MD10
DR_MD20
DR_MD11
DR_MD22MD22
DR_MD19MD19
DR_MD24
DR_MD28MD28
DR_MD29
DR_MD25MD25
-DR_MDQS3
DR_MD26
DR_MD30MD30
DR_MD31
DR_MD27
5 6
7 8
RN2042 8P4R-10R0402
1 2
-MDQS4 -DR_MDQS4
3 4
DM4
5 6
MD34 DR_MD34
7 8
MD42
R2082 10R0402
RN2043 8P4R-10R0402
MD39
1 2
MD40
3 4
MD35
5 6
MD44 DR_MD44
7 8
RN2048 8P4R-10R0402
1 2
-MDQS5
3 4
MD41
5 6
DM5 DR_DM5
7 8
RN2051 8P4R-10R0402
MD43
1 2
MD46 DR_MD46
3 4
MD47 DR_MD47
5 6
MD49 DR_MD49
7 8
RN2054 8P4R-10R0402
MD48 DR_MD48
1 2
3 4
MD53 DR_MD53
5 6
7 8
MD51
R2096 10R0402
RN2056 8P4R-10R0402
1 2
3 4
MD50
5 6
MD55
7 8
RN2058 8P4R-10R0402
MD56
1 2
MD60
3 4
MD61 DR_MD61
5 6
MD57 DR_MD57
7 8
RN2060 8P4R-10R0402
DM7
1 2
-MDQS7
3 4
MD58 DR_MD58
5 6
7 8
R2105 10R0402
MD63
R2103 10R0402
DM3
R2056 10R0402
DR_MD38
DR_MD32MD32
DR_MD36MD36
DR_MD33MD33
DR_MD37MD37
DR_DM4
DR_MD42
DR_MD39
DR_MD40
DR_MD35
DR_MD45MD45
-DR_MDQS5
DR_MD41
DR_MD43
DR_MD52MD52
DR_DM6DM6
DR_MD51
-DR_MDQS6-MDQS6
DR_MD54MD54
DR_MD50
DR_MD55
DR_MD56
DR_MD60
DR_DM7
-DR_MDQS7
DR_MD62MD62
DR_MD59MD59
DR_MD63
DR_DM3
LAYOUT: Place on backside,
evenly spaced around VTT fill.
C2215
C1000P50X
{nopop}
C2052
X_C0.22U16Y-0402
{nopop}
C2264
X_C0.22U16Y
{nopop}
X_C0.22U16Y
{nopop}
C2099
X_C0.1U25Y
C2162
X_C0.1U25Y
C2037
X_C0.1U25Y
C2272
X_C0.1U25Y
C2229
C1U25Y
C2290
X_C0.1U25Y
C2254
X_C0.1U25Y
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.
VTT_DDR_SUS
C2103
C2167
X_C1U10Y
VTT_DDR_SUS
C2147
C2153
C1U10Y
VTT_DDR_SUSVCC_DDR
C2171
C2026
C1U10Y
C2061
X_C0.1U25Y
VTT_DDR_SUS
5
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
DR_DM[7..0]
DM[7..0]
C0.22U16Y
C1U16Y0805
C2034
C2049
C2032
X_C0.22U16Y
VTT_DDR_SUS
X_C1000P50X
C2003
C2175
4
C2033
X_C1000P50X-0402
3
X_C4.7U10Y0805
-MDQS[7..0]<4>
-DR_MDQS[7..0]<7,8>
DR_MD[63..0]<7,8>
MD[63..0]<4>
A A
DR_DM[7..0]<7,8>
DM[7..0]<4>
to Clawhammer
socket.
VTT_DDR_SUS
GND
C2258
X_C0.1U25Y
C2265
C1U25Y
C2195
X_C0.1U25Y
C2036
X_C0.1U25Y
C2063
X_C0.1U25Y
C2280
X_C0.1U25Y
C2087
C2143
X_C0.1U25Y
C1U25Y
C2009
X_C0.1U25Y
X_C0.1U25Y
C2112
C2122
C1U25Y
X_C0.1U25Y
LAYOUT: Locate close to
Clawhammer socket.
C1U16Y0805
C2004
C2046
C2241
X_C4.7U10Y0805
X_C1000P50X-0402
EC2018
CE470U10VD25A400RO
C2255
C2097
C1U10Y
C1U10Y
C2074
C2129
X_C1U10Y
X_C1U10Y
C1000P50X
C2060
C2159
X_C4.7U10Y0805
X_C100P50N-0402
GND
C1000P50X
C1U16Y0805
C2274
C2176
C2316
C0.22U16Y
5
4
3
2
1
Clock Synthesizer
VCC3
D D
C C
APICCLK<16,17>
"FS0~FS3" are all internal
pull-up via 100K ohm ..
FS0
FS2
B B
FS1
FS3
C2354
X_104P
AC_14<21>
GUICLK<12>
R2169 10KR
R2130 10KR
R2135 10KR
R2128 10KR
FB2019 X_120S/0805
CP2006
X_COPPER
CLKVCC3
APICCLK
GUICLK
CLKVCC3
For K8M800
M:
CLKVCC3
R214010KR
R218022R
R213422R
R2119M_22R
C2355
X_4.7u/0805
FS0AC_14
FS1
FS2
2
9
16
19
29
35
38
43
46
32
5
10
15
20
27
30
33
34
39
42
47
1
48
45
C2332
104P
U2008
VDDHTT
VDDPCI
VDDPCI
VDDPCI
AVDD48
VDDCPU
VDDCPU
VDDA
VDDREF
PD#*
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
*FS0/REF0
*FS1/REF1
*FS2/REF2
ICS950405
33P50N
C2363
C2334
C2335
104P
104P
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK10
HTTCLK0/ModeA*
PCICLK8/HTTCLK1/ModeB*
PCICLK9/HTTCLK2
PCICLK11/HTTCLK3
24_48M/24_48SEL#
48MHz/FS3**
X1
3
CLKX1
Y2000
14.318MHZ
X2
4
CLKX2
C2359
33P50N
C2336
104P
SCLK
SDATA
RESET#
C2375
104P
41
40
37
36
13
14
17
18
21
22
23
24
12
6
7
8
11
28
31
25
26
44
C2379
104P
For K8T800 Rev:B
T:
FOR K8T800 Pro
R2136 T_15RST
R2137 T_15RST
R2138 15RST
R2139 15RST
R2181 22R
R2182 22R
RN2067
MODEA
MODEB
HT_66_2
SEL_24
R2142 33R
R2114 22R
SMBCLK
SMBDATA
R2127 10KR
C2380
104P
RN2068
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2
C2333
104P
HCLK+
HCLKCPUCLK0_H
CPUCLK0_L
8P4R-22R
8P4R-22R
SMBCLK <7,16,18,24,28>
SMBDATA <7,16,18,24,28>
FP_RST# <28,29>
LPC_PCLK
SIOPCLK
PCICLK1
PCICLK2
PCICLK3
SBPCLK
VCLK
GCLK_SLOT
GCLK_NB
SIO48M
USBCLK_SBFS3
HCLK+ <11>
HCLK- <11>
CPUCLK0_H <5>
CPUCLK0_L <5>
LPC_PCLK <24>
SIOPCLK <24>
PCICLK1 <20>
PCICLK2 <20>
PCICLK3 <20>
SBPCLK <17>
VCLK <17>
GCLK_SLOT <19>
GCLK_NB <12>
SIO48M <24>
USBCLK_SB <15>
APICCLK
VCLK
GCLK_SLOT
GCLK_NB
USBCLK_SB
SIO48M
AC_14
GUICLK
SBPCLK
PCICLK3
PCICLK2
PCICLK1
SIOPCLK
LPC_PCLK
CPUCLK0_H
CPUCLK0_L
HCLK+
HCLK-
For K8T800 Pro
T:
For K8T800 Rev:B
C2331 X_10P
CN2006
7 8
5 6
3 4
1 2
8P4C-10P
C2326 X_10P
C2328 X_10P
C2378 X_10P
C2321 X_10P
C2390 X_10P
C2389 10P
CN2007
1 2
3 4
5 6
7 8
8P4C-10P
C2324 X_5P
C2325 X_5P
C2322 T_C10P50N
C2323 T_C10P50N
FS(3:0)
0000
100.90
0001
133.90
0010
168.00
0011
202.00
0100
100.20
0101
133.50
0110
166.70
0111
200.40
1000
150.00
1001
180.00
A A
5
1010
1011
1100
1101
1110
1111
210.00
240.00
270.00
233.33
266.67
300.00
67.27 33.63
66.95
67.20
67.33
66.80
66.75
66.68
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
PCIHTTCPU
33.48
33.60
33.67
33.40
33.38
33.34
33.4066.80
30.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
MODEA
R2190 10KR
MODEB
R2195 10KR
MODE BMODE A
00
HTTCLK1
0
1
1
0
11
4
HTTCLK1
PCICLK8
HTTCLK1
HTTCLK2
HTTCLK2
PCICLK9
PCICLK9
PIN11PIN8PIN7
PCICLK11
HTTCLK3
PCICLK11
PCICLK11
SEL_24
R2133 X_10KR
SEL_24
PIN28
48M
0
24M
1
MSI
Title
Size Document Number Rev
3
2
Date: Sheet of
MICRO-STAR
CLOCK GEN
MS-7169
1
10 33Tuesday, February 22, 2005
00A
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