MSI MS-7164 Schematics
1
Cover Sheet
1
MS-7164 VER:0C
Block Diagram
Intel LGA775 CPU - Signals
Intel LGA775 CPU - Power
Intel LGA775 CPU- GND
Intel Lakeport - CPU
Intel Lakeport - Memory
Intel Lakeport - PCI Express
Intel Lakeport - GND
ICH7 Signal, Power, GND 10-12
Clock - CLOC K ICS954101DF & FWH
SIO NS PC8375L/K/T & I/O CONNECTOR
SERIAL PORT & VGA CONNECTOR
AC97 Audio Codec- AD1888
A A
LAN Intel Tekoa 82573E
DDR2 System Memory 1 , 2
DDR VTT DECPUPLING
IBM Slim IDE & SATA Conn.
ATX & FRONT PANEL & FAN
13
14
15
16
17PCI-E X1 & PCI & ADD2R-N SLOT
18
20
21
22
23
2
3
4
5
6
7
8
9
CPU:
Intel Prescott ( L2=2MB )
Intel Cendar Mill (65nm)
Intel Smithfield
System Chipset:
Intel Lakeport - GMCH (North Bridge)
Intel ICH7 South Bridge
On Board Chipset:
BIOS -- FWH(TSOP_40 Pin) 8M EEPROM
AC'97 Codec -- AD1888
LPC Super I/O -- NS PC8375L/K/T
LAN --Imtel Tekoa 82573E
CLOCK -- ICS954101DF
Main Memory:
2 CHANNEL DDR2 * 2 (Max 2GB)
PCI-E Slots:
Rear Side I/O
USB
USB
Line_Out
Line_In
LAN
USB
USB
LPT Port
COM B Port
.............
............
.....
....
VGA Port
.....
.....
.....
MS
KB
.
.
.
.
.
.
.
.
.
.
.
.
PCI-E X1 & PCI & ADD2-N SLOT
Intersil PWM: 4-phase
Controller: HIP6556BCR
Front Side I/O
Line_Out Mic_In USB USB
Driver: HIP6602BCR *2
USB Connectors
MS-7 ACPI CONTROLLER
VRM10.1 - INTERSIL 6556 4PHASE
Decoupling CAP
GPIO & Jumper setting
Power Delivery Mapping
Revision History
Manual Parts
24
25
26
27
28
29
30
BOM Config
Option ERP NumberMODEL Config. ORCAD Config.
MSI
1
Title
Size Document Number Re v
Date: Sheet
MICRO-STAR INt'L CO., LTD.
COVER SHEET
(MS-7164)
of
131Monday, June 27, 2005
0C
VRM_GD
VTT_PWG
VRM 10.1
Intersil 6556
4-Phase PWM
P.27
VTT_PWG
Intel LGA775 Processor
FSB
533/800/1066
H_CPURST#
P.3~5
CHANNEL A
CHANNEL B
533/667
1
2 DDR2
DIMM
Modules
VID_GD
VTT_PWG
MS-7164
System Block Diagram
P.20-21
PCI-E Slot 1
P.25
Intel
82573E
PCIRST_ICH6#
SLP_S4#
SLP_S3#
ATX1
PCIRST#2
P.18
PWR_OK
PCIRST#2
PCIRST#1
RSMRST#
PWR_GD
MS7
RSMRST#
HD_RST#
P.27
P.6~9
PWR_GD
ADD2
PWR_GD
PCI + PCI-E x1
PCI-E x1
Analog
Video
Out
HD_RST#
UltraBay Silm
Enhance
A A
SERIAL ATA1
P.15
P.23
P.22
H_PWRGD
VRM_GD
UltraDMA 33/66/100
Lakeport
GMCH
DMI
ICH7
PLTRST#
USB2.0
USB Port 0~ 7
P.24
JFP1
P.24
RSMRST#
PWRBTN#
P.10~12
LPC Bus
FWH
AD1888
AC'97 Codec
AC-LINK
P.16
8M Flash
P.14
LPC SIO
NS
PC8374L/K/T
P.14
Keyboard
Mouse
Parallel Port
P.14
P.14
Serial Port
COM B
P.15P.14
CPU_FAN1
REAR_FAN1
SYS_FAN1
1
P.23
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet
BLOCK DIAGRAM
(MS-7164)
231Thursday, June 23, 2005
of
0C
8
7
6
5
4
DBRESET#
3
DBRESET# [11]
2
1
CPU SIGNAL BLOCK
H_VID1
AL5
RSVD
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
DP3#
DP2#
DP1#
DP0#
H_VID0
AM2
VID1#
VID0#
VCC_VRM_SENSE [26]
VSS_VRM_SENSE [26]
H_VID[0..5] [26]
VID_SELECT
L--VRD10.1
H--VRD11
AN7
CPU_GTLREF0
H1
CPU_GTLREF1
H2
TEST_H29
H29
MCH_GTLREF_CPU
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2
H_PCREQ#
G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
H_TESTHI9
G4
H_TESTHI8
G3
F24
G24
G26
G27
G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
RSVD_AK6
AK6
RSVD_G6
G6
CK_H_CPU#
G28
CK_H_CPU
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
TEST_U3
U3
TEST_U2
U2
H_BR#0
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
TEST_J17
J17
TEST_H16
H16
TEST_H15
H15
TEST_J16
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
3
R14 62R0402
TEST_H29
MCH_GTLREF_CPU [6]
H_BPM#[0..5] [19]
For ITP Port
H_PCREQ# [6]
H_REQ#[0..4] [6]
R8 62R0402
R9 62R0402
R10 62R0402
R12 X_62R0402
CK_H_CPU# [13]
CK_H_CPU [13]
H_RS#[0..2] [6]
TEST_U3
TEST_U2
R22 60.4R1%0402
R23 60.4R1%0402
R13 60.4R1%0402
R15 60.4R1%0402
R16 60.4R1%0402
R17 60.4R1%0402
TEST_J17
TEST_H16
TEST_H15
TEST_J16
H_ADSTB#1 [6]
H_ADSTB#0 [6]
H_DSTBP#3 [6]
H_DSTBP#2 [6]
H_DSTBP#1 [6]
H_DSTBP#0 [6]
H_DSTBN#3 [6]
H_DSTBN#2 [6]
H_DSTBN#1 [6]
H_DSTBN#0 [6]
H_NMI [10]
H_INTR [10]
VID Pull-Up Resistor
VTT_OUT_RIGHT
RN1
8P4R-680R
H_VID3
1 2
H_VID1
3 4
H_VID4
5 6
H_VID2
7 8
H_VID0
R2 680R0402
H_VID5
R3 680R0402
VTT_OUT_RIGHT
H_TMS
R6 49.9R1%0402
H_BPM#4
H_TDO
H_BPM#2
H_TDI
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
VTT_OUT_LEFT
H_TESTHI12
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI11
V_FSB_VTT
VTT_OUT_LEFT
V_FSB_VTT
VTT_OUT_RIGHT
VTT_OUT_LEFT
H_BR#0 [6]
PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE
COMP5 Rt
COMP4 Rt
COMP3 Rt
COMP2 Rt
COMP1 Rt
COMP0 Rt
Lakeport Design Guide Define
COMP[7:4] Rpu=60.4ohm +- 1%
COMP[3:0] Rpd=60.4ohm +- 1%
MSI
Title
Size Document Number Rev
Date: Sheet
2
V_FSB_VTT
VTT_OUT_LEFT
VTT_OUT_RIGHT
Prescott Celeron-D CedarMill Smithfield
NC
NC
NC
NC
VSS
VSS
MICRO-STAR INt'L CO., LTD.
RN2
_8P4R-51R0402-LF
1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2
R7 62R0402
7 8
5 6
3 4
1 2
RN4 _8P4R-62R0402-LF
VTT
VTT
VTT
VTT
VTT
NC
VTT
NC
VSS
VSS
VSS
VSS
C1 C0.1U25Y
RN3
_8P4R-51R0402-LF
C2 C0.1U25Y
C520 C0.1U2 5 Y
V_FSB_VTT [4,5,6,8,12,25]
VTT_OUT_LEFT [4]
VTT_OUT_RIGHT [4,5,19]
VTT_OUT_RIGHT
C5
X_C0.1U25Y
NC
NC
VSS
VSS
VSS
VSS
Intel LGA775 CPU - Signals
(MS-7164)
331Monday, June 27, 2005
1
0C
of
TEST_AN4
TEST_AN3
H_A#[3..31][6]
D D
H_A#7
H_A#5
H_A#6
H_A#4
D21#
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
H_D#19
H_D#17
H_D#20
H_D#18
H_A#3
L5
H_D#16
H_D#15
DBRESET#
VSS_SENSE
VCC_VRM_SENSE
VSS_VRM_SENSE
VCC_SENSE
AN4
AN6
AN3
AN5
AC2
DBR#
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D14#
D13#
D12#D8D11#
D10#
D9#
B12
B10
A11
C12
H_D#14
H_D#13
H_D#12
C11
H_D#11
H_D#10
A10
H_D#8
H_D#9
D11
4
H_VID5
AJ3
AK3
AM7
AM5
AL4
RSVD
VID6#
ITP_CLK1
ITP_CLK0
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
H_D#4
H_D#5
H_D#2
H_D#6
H_D#7
H_D#3
H_VID4
H_VID2
H_VID3
AK4
AL6
AM3
VID5#
VID4#
VID3#
VID2#
VID_SELECT
GTLREF0
GTLREF1
GTLREF_SEL
CS_GTLREF
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
FORCEPH
BCLK1#
BCLK0#
COMP5
COMP4
COMP3
COMP2
COMP1
COMP0
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
B4
ZIF-SOCK775-15u
H_D#0
H_D#1
H_A#10
H_A#11
H_A#9
D28#
H_A#14
G13
H_D#27
D27#
H_A#13
E13
H_D#26
H_A#12
D26#
D13
H_D#25
D25#
H_D#24
U6
D24#
F12
F11
H_D#23
H_A#8
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D23#
D22#
E10
D10
H_D#21
H_D#22
H_A#25
H_A#31
H_A#26
H_A#30
H_A#29
AJ6
AJ5
AH5
AH4
AG5
AG4
D49#
H_D#48
AG6
A35#
A34#
A33#
A32#
A31#
A30#
D48#
D47#
D46#
D45#
D44#
D43#
F21
E22
E21
D20
D22
G22
G21
H_D#42
H_D#44
H_D#43
H_D#45
H_D#47
H_D#46
100 OHMS OVER 210 OHMS RESISTORS
GTLREF VOLTAGE SHOULD BE
0.67*VTT = 0.8V
VTT_OUT_LEFT
VTT_OUT_LEFT
C C
R20
49.9R1%0402
R18
49.9R1%0402
R21
100R1%0402
R19
100R1%0402
CPU_GTLREF0
C6
C1U10Y
CPU_GTLREF1
C3
C1U10Y
C7
X_C2200P16X
C4
X_C2200P16X
PLACE AT CPU END OF ROUTE
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_OUT_LEFT
R24 62R0402
R25 120R0402
R27 100R1%0402
R28 62R0402
R29 62R0402
R4 49.9R1%0402
R5 49.9R1%0402 R11 X_62R0402
H_CPURST#
H_PROCHOT#
H_PWRGD
H_BR#0
H_TESTHI13
H_TRST#
H_TCK
H_DBI#[0..3][6]
H_EDRDY#[6]
H_IERR#[4]
H_FERR#[4,10]
H_STPCLK#[ 10]
H_INIT#[10]
H_DBSY#[6]
H_DRDY#[6]
H_TRDY#[6]
H_ADS#[6]
H_LOCK#[6]
H_BNR#[6]
H_HIT#[6]
H_HITM#[6]
H_BPRI#[6]
H_DEFER#[6]
H_TDI[ 19]
H_TDO[19]
H_TMS[ 19]
H_TRST#[19]
H_TCK[19]
THERMDP#[ 14]
THERMDN#[14]
TRMTRIP#[4,10]
H_IGNNE#[10]
ICH_H_SMI#[10,14]
H_A20M#[10]
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
H_PROCHOT#
H_TESTHI13
LL_ID[1:0] = TBD for the Smithfield
H_FSBSEL0
H_FSBSEL1
H_FSBSEL2
LL_ID0
LL_ID1
LL_ID0
LL_ID1
H_FSBSEL0[8,13]
H_FSBSEL1[8,13]
H_FSBSEL2[8,13]
H_PWRGD[10]
H_CPURST#[6,19]
H_D#[0..63][6]
7
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
VTT_OUT_RIGHT
VTT_OUT_RIGHT
B B
FSBSEL RESISTOR CAN BE REMOVED IF ONLY
TEAJS AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
BSEL
2
1
0
0
0
1
0
01
A A
R30 X_62R0402
R31 X_62R0402
RN6
8P4R-470R
12
34
56
78
TABLE
0 FSB FREQUENCY
267 MHZ (1067)
0
200 MHZ (800)
0
133 MHZ (533)
8
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
6
U1A
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
TESTI_13
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
B15
C14
H_D#52
H_D#53
D52#
H_D#51
D51#
D50#
A14
C15
D17
H_D#50
H_D#49
H_A#28
A29#
D42#
H_D#41
H_A#22
H_A#23
H_A#27
H_A#24
AF4
AF5
AB4
AC5
AB5
AA5
AD6
A28#
A27#
A26#
A25#
A24#
A23#
D41#
D40#
D39#
D38#
D37#
D36#
F20
F18
F17
E19
E18
G17
G18
H_D#39
H_D#35
H_D#36
H_D#38
H_D#40
H_D#37
5
H_A#21
AA4
A22#
D35#
E16
H_D#34
H_A#19
H_A#20
A21#
A20#Y4A19#Y6A18#W6A17#
D34#
D33#
E15
G16
H_D#32
H_D#33
H_A#18
H_A#16
H_A#17
AB6
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D32#
D31#
D30#
D29#
F15
G15
G14
H_D#29
H_D#30
H_D#31
H_A#15
F14
H_D#28
8
7
6
5
4
3
2
1
VCCP
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
U1B
VCCP
D D
C C
AF19
AF18
AF15
AF14
AF12
AF11
AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AB8
AA8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y23
Y24
Y25
Y26
Y27
Y28
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
W27
W28
W29
W30
W26
VCC
VCC
VCC
VCC
VCC
VCC
VCCU8VCCV8VCC
VCC
VCC
VCC
W23
W24
W25
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U25
U26
U27
U28
U29
U30
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCN8VCCP8VCCR8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCT8VCC
VCC
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
T30
U23
U24
N29
N30
N23
N24
N25
N26
N27
N28
M29
M30
M23
M24
M25
M26
M27
M28
K30
K29
K28
K27
K26
T23
T24
T25
T26
T27
T28
T29
K25
K24
K23
J30
AN9
AN8
AN30
ZIF-SOCK775-15u
AN25
AN26
AN29
A23
B23
D23
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
F27
F29
H_VCCA
H_VSSA
H_VCCIOPLL
V_FSB_VTT
VCCFUSEPRG
VIDFUSEPRG
VTT_PWG
R522
X_0R0402
D23 VCCPLL Smithfield define the
support future processor.
V_FSB_VTT [3 ,5,6,8,12]
VTT_OUT_RIGHT [3,5,19]
VTT_OUT_LEFT [3]
R521 X_1KR0402
V_FSB_VTT
VTT_SEL
B B
It must close bulk caps.
V_FSB_VTT H_VCCIOPLL
DC voltage drop should
be less than 70mV.
It support DC current if 125mA.
L1 X_10U100m_0805
CP15 X_COPPER
L2 X_10U100m_0805
EC1
C22U6.3X1206
EC2
X_C10U10Y0805
H_VSSA
C11
C1U10Y
H_VCCA
PLACE AT ICH END OF ROUTE
RN5 _8P4R-62R0402-LF
12
34
56
78
TRMTRIP#VTT_OUT_RIGHT
H_FERR#
H_IERR#
TRMTRIP# [3,10]
H_FERR# [3,10]
H_IERR# [3]
MSI
VTT_OUT_RIGHT
R524
A A
VCC5_SB
R523
1KR0402
VID_GD#[25,26]
R525
1KR0402
8
7
1.25V VTT_PWRGOOD
680R0402
VTT_PWG
SOT23EBC
Q1
N-MMBT3904_NL_SOT23
ECB
6
V_FSB_VTT
5
C8 X_C10U10Y0805
C9 C10U10Y0805
C10 C10U10Y0805
4
Title
MICRO-STAR INt'L CO., LTD.
Intel LGA775 CPU - Power
Size Document Number Rev
(MS-7164)
3
Date: Sheet
2
431Monday, June 27, 2005
1
0C
of
8
R526
A12
A15
A18
A21
A24
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
AB1
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AB7
AC3
AC6
AC7
AD4
AD7
AE10
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
AE27
AE28
A2
A6
A9
62R0402
R527
62R0402
U1C
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE29
VTT_OUT_RIGHT[3,4]
D D
C C
B B
VSS
COMP6Y3COMP7
VSS
AE30
AE3
VSS
AE5
TEST_E23
AE4
RSVD
RSVDD1RSVD
VSS
VSS
AE7
AF10
D14
AF13
7
TEST_E23
E23
VSS
AF16
TEST_E7
RSVD
VSS
VSS
AF17
AF20
TEST_F23
TEST_F23
TEST_E7
TEST_F6
F23
RSVDE5RSVDE6RSVDE7RSVD
VSS
VSS
VSS
VSS
AF23
AF24
AF25
TEST_F6
B13
F6
RSVD
IMPSEL#
VSS
VSS
AF26
AF27
AF28
VSS
VSS
AF29
RSVDJ3RSVDN4RSVD
VSS
VSS
AF3
AF30
6
VTT_OUT_LEFT [3,4]
5
4
3
2
1
MSID1 MSID0
2005 Perf FMB 0 0
2005 Value FMB 0 1
R529 62R0402
R530 X_62R0402
R528 62R0402
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
V30
V29
V28
V27
V26
V25
V24
W1
P5
AC4
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
RSVD
MSID[1]V1MSID[0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF6
AF7
AG10
AG13
AG16
AG17
AG20
AG23
AG24
AG7
VSSV3VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH1
AH10
AH13
AH16
AH17
AH20
AH23
V23
VSS
VSS
VSS
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH3
AH6
AH7
AJ10
AJ13
AJ16
AH24
AJ17
R30
R29
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AJ20
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
VSS
AL17
VSS
AL20
VSS
AL23
VSS
AL24
VSS
AL27
L30
VSS
AL28
VSSL3VSS
VSS
AL3
L29
AL7
VSS
L28
AM1
VSS
VSS
L27
AM10
VSS
VSS
L26
VSS
VSS
AM13
L25
AM16
VSS
VSS
L24
AM17
VSS
VSS
L23
AM20
VSS
VSS
VSSK7VSS
VSS
AM23
K2
K5
VSS
VSS
VSS
VSS
AM4
AM24
AM27
AM28
H28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSB1VSS
VSS
B11
AN1
AN2
AN10
AN13
AN16
AN17
AN20
AN23
AN24
B14
AN27
AN28
H14
VSS
H13
VSS
H12
VSS
H11
VSS
H10
VSS
G1
VSS
F7
VSS
F4
VSS
F22
VSS
F19
VSS
F16
VSS
F13
VSS
F10
VSS
E8
VSS
E29
VSS
E28
VSS
E27
VSS
E26
VSS
E25
VSS
E20
VSS
E2
VSS
E17
VSS
E14
VSS
E11
VSS
D9
VSS
D6
VSS
D5
VSS
D3
VSS
D24
VSS
D21
VSS
D18
VSS
D15
VSS
D12
VSS
C7
VSS
C4
VSS
C24
VSS
C22
VSS
C19
VSS
C16
VSS
C13
VSS
C10
VSS
B8
VSS
B5
VSS
B24
VSS
B20
VSS
B17
VSS
ZIF-SOCK775-15u
HEAT SINK Retention Module
U25
HEATSINK_RM
8
1
5
6
7
A A
16
15
14
3
13
8
7
6
5
9
2
10
11
12
18
19
20
4
17
4
3
MSI
Title
Size Document Numbe r Rev
Date: Sheet
MICRO-STA R INt'L CO., LTD.
Intel LGA775 CPU - GND
(MS-7164)
2
531Monday, June 2 7, 2005
of
1
0C
8
7
6
5
4
3
2
1
V_1P5_CORE
AA37
AA41
W42
W41
W40
AJ12
K38
K35
M34
N35
R33
N32
N34
M38
N42
N37
N38
R32
R36
U37
R35
R38
V33
U34
U32
V42
U35
Y36
Y38
V32
Y34
M36
V35
D42
U39
U40
E41
D41
K36
G37
E42
U41
P40
U42
V41
Y40
Y43
M31
M29
C30
M18
A28
C27
B27
D27
D28
J39
J42
J37
F38
T40
T43
AJ9
U2A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
HPCREQ#
HBREQ0#
HBPRI#
HBNR#
HLOCK#
HADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HHIT#
HHITM#
HDEFER#
HTRDY#
HDBSY#
HDRDY#
HEDRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
HCPURST#
RSTIN#
ICH_SYNC#
HRCOMP
HSCOMP
HSWING
HDVREF
HACCVREF
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF30
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AH1
AH2
AH4
AJ5
AJ13
AJ14
AK2
AK3
AK4
AK14
AK15
AK20
R15
R17
R18
R20
R21
R23
R24
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
W24
W26
W27
Y15
VCC
VCC
VCC
VCC
VCC
RSVRD
AA35
AA42
VCC
VCC
RSVRD
RSVRD
AA34
VCC
RSVRD
L15
AA38
VCC
VCC
RSVRD
RSVRD
M15
VCC
RSVRD
U27
VCC
RSVRD
A43
R27
VCC
VCC
RSVRD
RSVRD
M11
VCC
RSVRD
AG25
VCC
RSVRD
AG26
AG27
VCC
VCC
RSVRD
RSVRD
AJ24
VCC
RSVRD
AJ27
AK40
VCC
VCC
RSVRD
RSVRD
AL39
AW17
VCC
VCC
RSVRD
RSVRD
AW18
VCC
RSVRD
AY14
VCC
RSVRD
BC16
AD30
VCC
VCC
RSVRD
RSVRD
AC34
VCC
RSVRD
Y30
Y33
VCC
VCC
RSVRD
RSVRD
AF31
VCC
RSVRD
U30
AD31
VCC
VCC
RSVRD
RSVRD
V31
VCC
RSVRD
AA30
AC30
VCC
VCC
RSVRD
RSVRD
AK21
VCC
RSVRD
AJ23
VCC
RSVRD
AJ26
AL29
VCC
VCC
RSVRD
RSVRD
AL20
VCC
RSVRD
AJ21
VCC
RSVRD
AL26
VCC
RSVRD
AJ29
AK27
VCC
VCC
RSVRD
RSVRD
AG29
VCC
RSVRD
V30
VCC
VCC
NC
BC43NCBC42
VCC
VCC
NC
BC2NCBC1
VCC
VCC
NC
BB43
VCC
VCC
NC
BB2NCBB1NCBA2
VCC
M17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
KDINV_0#
HDINV_1#
HDINV_2#
HDINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
AA15
VCC
VCC
AA17
VCC
AA18
AA19
VCC
VCC
AA20
HD_STBN3#
NC
NC
NC
NC
NC
NCC2NC
NCB3NCB2NC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
E35
B43NCB42NCB41
A42
Y17
Y18
Y19
Y21
Y23
Y25
C42
AW2
AV27NCAV26
AW26
Y27
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
P41
M39
P42
M42
N41
M40
L40
M41
K42
G39
J41
G42
G40
G41
F40
F43
F37
E37
J35
D39
C41
B39
B40
H34
C37
J32
B35
J34
B34
F32
L32
J31
H31
M33
K31
M27
K29
F31
H29
F29
L27
M24
J26
K26
G26
H24
K24
F24
E31
A33
E40
D37
C39
D38
D33
C35
D34
C34
B31
C31
C32
D32
B30
D30
K40
A38
E29
B32
K41
L43
F35
G34
J27
M26
E34
B37
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
H_DBI#0
H_DBI#1
H_DBI#2
H_DBI#3
H_DSTBP#0 [3]
H_DSTBN#0 [3]
H_DSTBP#1 [3]
H_DSTBN#1 [3]
H_DSTBP#2 [3]
H_DSTBN#2 [3]
H_DSTBP#3 [3]
H_DSTBN#3 [3]
H_D#[0..63] [3]
H_DBI#[0..3] [3]
V_1P5_CORE
(INTEL-QG82945G-A2-LF)
H_A#[3..31][3]
D D
H_ADSTB#0[3]
H_ADSTB#1[3]
C C
H_PCREQ#[3]
H_BR#0[3]
H_BPRI#[3]
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_BNR#[3]
H_LOCK#[3]
H_ADS#[3]
H_REQ#[0..4][3]
H_HIT#[3]
H_HITM#[3]
H_DEFER#[3]
H_TRDY#[3]
H_DBSY#[3]
H_DRDY#[3]
H_EDRDY#[3]
H_RS#[0..2][3]
CK_H_MCH[13]
B B
V_2P5_MCH
20R1%0402
R509
16.9ohm
CK_H_MCH#[13]
PWR_GD[1 4,25]
H_CPURST#[3,19]
PLTRST#[10,13]
ICH_SYNC#[11]
R508 X_4.7KR
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#0
H_RS#1
H_RS#2
HRCOMP
HSCOMP
HSWING
MCH_GTLREF
V_1P5_CORE
C13
C12
C10U10Y0805
C10U10Y0805
5 mils trace 8 mils space rout in
A A
same layer within 750 mils
V_FSB_VTT[3,4,5,8,12,25]
R507 60.4R1%0402
HSCOMP
C16
X_C2.2P50N
HD_SWING VOLTAGE "20 MIL TRACE , 10MIL
SPACE" HD_SWING S/B 0.22*VTT +/- 2%n
R502 62R0402
R504
102R1%0402
C14
C0.01U50X
HSWING MCH_GTLREF
PLACE DIVIDER RESISTOR NEAR VTT
8
7
6
5
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V
124 OHM OVER 210 RESISTORS
V_FSB_VTTV_FSB_VTT
R505 49.9R1%0402
R501 62R0402R503 301R1%0402
R506
100R1%0402
4
C15
C0.1U25Y
R500 0R0402
3
MCH_GTLREF_CPU [3]
Title
Size Document Number Rev
MSI
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU Signals
(MS-7164)
2
0C
of
631Monday, June 27, 2005
1
8
7
6
5
4
3
2
1
M_CHA_DQ36
M_CHA_DQ35
AU39
AV32
SADQ35
SBDQ33
AN29
AR31
M_CHA_DQ37
M_CHA_DQ38
AT32
AR34
SADQ36
SADQ37
SBDQ34
SBDQ35
AP27
AM31
M_CHA_DQ40
M_CHA_DQ39
AU37
AR41
SADQ38
SADQ39
SBDQ36
SBDQ37
AP31
AR27
M_CHA_CKE[0..1][20,21]
M_CHA_DQ42
M_CHA_DQ41
AR42
AN43
SADQ40
SADQ41
SBDQ38
SBDQ39
AP35
AU31
M_CHA_DQ44
M_CHA_DQ43
AM40
AU41
SADQ42
SADQ43
SBDQ40
SBDQ41
AP37
AN32
M_CHA_DQ45
M_CHA_DQ46
AU42
AP41
SADQ44
SADQ45
SBDQ42
SBDQ43
AL35
AR35
M_CHA_DQ47
M_CHA_DQ48
AN40
AL41
SADQ46
SADQ47
SADQ48
SBDQ44
SBDQ45
SBDQ46
AU38
AM38
M_CHA_DQ49
AL42
AM34
M_CHA_DQ[0..63][20]
D D
~M_CHA_CS[0..1][20,21]
~M_CHA_RAS[20,21]
~M_CHA_CAS[20,21]
~M_CHA_WE[20,21]
M_CHA_MA[0..13][20,21]
C C
M_CHA_OD T [0..1][20,21]
M_CHA_BA[0..2][20,21]
M_CHA_DQS0[20]
~M_CHA_DQS0[20]
M_CHA_DQS1[20]
~M_CHA_DQS1[20]
M_CHA_DQS2[20]
~M_CHA_DQS2[20]
M_CHA_DQS3[20]
~M_CHA_DQS3[20]
M_CHA_DQS4[20]
~M_CHA_DQS4[20]
M_CHA_DQS5[20]
~M_CHA_DQS5[20]
M_CHA_DQS6[20]
~M_CHA_DQS6[20]
M_CHA_DQS7[20]
~M_CHA_DQS7[20]
M_CHA_SCK0[20]
~M_CHA_SCK0[20]
B B
M_CHA_SCK1[20]
~M_CHA_SCK1[20]
M_CHA_SCK2[20]
~M_CHA_SCK2[20]
~M_CHA_CS0
~M_CHA_CS1
~M_CHA_RAS
~M_CHA_CAS
~M_CHA_WE
M_CHA_MA0
M_CHA_MA1
M_CHA_MA2
M_CHA_MA3
M_CHA_MA4
M_CHA_MA5
M_CHA_MA6
M_CHA_MA7
M_CHA_MA8
M_CHA_MA9
M_CHA_MA10
M_CHA_MA11
M_CHA_MA12
M_CHA_MA13
M_CHA_ODT0
M_CHA_ODT1
M_CHA_BA0
M_CHA_BA1
M_CHA_BA2
M_CHA_DQS0
~M_CHA_DQS0
M_CHA_DQS1
~M_CHA_DQS1
M_CHA_DQS2
~M_CHA_DQS2
M_CHA_DQS3
~M_CHA_DQS3
M_CHA_DQS4
~M_CHA_DQS4
M_CHA_DQS5
~M_CHA_DQS5
M_CHA_DQS6
~M_CHA_DQS6
M_CHA_DQS7
~M_CHA_DQS7
M_CHA_SCK0
~M_CHA_SCK0
M_CHA_SCK1
~M_CHA_SCK1
M_CHA_SCK2
~M_CHA_SCK2
SM_RCOMP_P
SM_RCOMP_N
SMOCDCOMP1
SMOCDCOMP0
U2B
(INTEL-QG82945G-A2-LF)
BB37
BA39
BA35
AY38
BA34
BA37
BB35
BA32
AW32
BB30
BA30
AY30
BA27
BC28
AY27
AY28
BB27
AY33
AW27
BB26
BC38
AW37
AY39
AY37
BB40
BC33
AY34
BA26
AU4
AR2
BA3
BB4
AY11
BA10
AU18
AR18
AU35
AV35
AP42
AP40
AG42
AG41
AC42
AC41
BB32
AY32
AY5
BB5
AK42
AK41
BA31
BB31
AY6
BA5
AH40
AH43
AL5
AJ6
AJ8
AM3
SACS0#
SACS1#
SACS2#
SACS3#
SARAS#
SACAS#
SAWE#
SAMA0
SAMA1
SAMA2
SAMA3
SAMA4
SAMA5
SAMA6
SAMA7
SAMA8
SAMA9
SAMA10
SAMA11
SAMA12
SAMA13
SAODT0
SAODT1
SAODT2
SAODT3
SABA0
SABA1
SABA2
SADQS0
SADQS0#
SADQS1
SADQS1#
SADQS2
SADQS2#
SADQS3
SADQS3#
SADQS4
SADQS4#
SADQS5
SADQS5#
SADQS6
SADQS6#
SADQS7
SADQS7#
SACLK0
SACLK0#
SACLK1
SACLK1#
SACLK2
SACLK2#
SACLK3
SACLK3#
SACLK4
SACLK4#
SACLK5
SACLK5#
MCH_SRCOMP0
MCH_SRCOMP1
SMOCDCOMP0
SMOCDCOMP1
M_CHA_DQ0
AP3
SADQ0
M_CHA_DQ1
AP2
SADQ1
M_CHA_DQ2
AU3
AL6
M_CHA_DQ3
M_CHA_DQ4
AV4
SADQ2
SADQ3
SBDQ0
SBDQ1
AL8
M_CHA_DQ5
AN1
SADQ4
SBDQ2
AP8
AP4
SADQ5
SBDQ3
AP9
M_CHA_DQ7
M_CHA_DQ6
AU5
SADQ6
SBDQ4
AJ11
AU2
SADQ7
SBDQ5
AL9
M_CHA_DQ8
AW3
AM10
M_CHA_DQ9
AY3
SADQ8
SADQ9
SBDQ6
SBDQ7
AP6
M_CHA_DQ10
M_CHA_DQ11
BA7
BB7
SADQ10
SBDQ8
AV6
AU7
M_CHA_DQ12
M_CHA_DQ13
AV1
AW4
SADQ11
SADQ12
SBDQ9
SBDQ10
AV12
AM11
M_CHA_DQ15
M_CHA_DQ14
BC6
AY7
SADQ13
SADQ14
SBDQ11
SBDQ12
AR5
AR7
M_CHA_DQ16
M_CHA_DQ17
AW12
AY10
SADQ15
SADQ16
SBDQ13
SBDQ14
AR12
AR10
M_CHA_DQ18
M_CHA_DQ19
BA12
BB12
SADQ17
SADQ18
SBDQ15
SBDQ16
AM15
AM13
M_CHA_DQ20
M_CHA_DQ21
BA9
BB9
SADQ19
SADQ20
SBDQ17
SBDQ18
AV15
AM17
M_CHA_DQ23
M_CHA_DQ22
BC11
AY12
SADQ21
SADQ22
SBDQ19
SBDQ20
AN12
AR13
M_CHA_DQ24
M_CHA_DQ25
AM20
AM18
SADQ23
SADQ24
SBDQ21
SBDQ22
AT15
AP15
M_CHA_DQ26
AV20
SADQ25
SBDQ23
AM24
M_CHA_DQ28
M_CHA_DQ27
AM21
AP17
SADQ26
SADQ27
SBDQ24
SBDQ25
AV24
AM23
M_CHA_DQ29
M_CHA_DQ30
AR17
AP20
SADQ28
SADQ29
SBDQ26
SBDQ27
AP21
AM26
M_CHA_DQ31
M_CHA_DQ32
AT20
AP32
SADQ30
SADQ31
SBDQ28
SBDQ29
AP24
AR21
M_CHA_DQ33
M_CHA_DQ34
AV34
AV38
SADQ32
SADQ33
SBDQ30
SBDQ31
AT24
AU27
SADQ34
SBDQ32
M_CHA_DQ51
M_CHA_DQ50
AF39
AE40
SADQ49
SADQ50
SBDQ47
SBDQ48
AJ34
AL34
M_CHA_DQ53
M_CHA_DQ52
AM41
AM42
SADQ51
SADQ52
SBDQ49
SBDQ50
AF32
AF34
M_CHA_DQ55
M_CHA_DQ54
AF41
AF42
SADQ53
SADQ54
SBDQ51
SBDQ52
AJ32
AL31
M_CHA_DM[0..7][20]
M_CHA_DQ57
M_CHA_DQ56
AD40
AD43
SADQ55
SADQ56
SBDQ53
SBDQ54
AD32
AG35
M_CHA_DQ58
M_CHA_DQ59
AA39
AA40
SADQ57
SADQ58
SBDQ55
SBDQ56
AC32
AD34
M_CHA_DQ60
M_CHA_DQ61
AE42
AE41
SADQ59
SADQ60
SBDQ57
SBDQ58
Y32
AA32
M_CHA_DQ63
M_CHA_DQ62
AB41
AB42
SADQ61
SADQ62
SBDQ59
SBDQ60
AF35
AF37
M_CHA_CKE0
BB25
SADQ63
SBDQ61
SBDQ62
AC33
AC35
M_CHA_CKE1
AY25
BC24
SACKE0
SACKE1
SBDQ63
BA14
BA25
SACKE2
SACKE3
SBCKE0
SBCKE1
AY16
BA13
M_CHA_DM0
AR3
SBCKE2
SBCKE3
BB13
M_CHA_DM1
AY2
SADM1
SADM0
SBDM7
AD39
M_CHA_DM2
BB10
AJ39
M_CHA_DM4
M_CHA_DM3
AP18
SADM3
SADM2
SBDM5
SBDM6
AR38
M_CHA_DM5
AP39
AT34
SADM4
SBDM4
AP23
AR29
M_CHA_DM6
M_CHA_DM7
AG40
SADM6
SADM5
SBDM2
SBDM3
AP13
AC40
SADM7
SBDQS0#
SBDQS1#
SBDQS2#
SBDQS3#
SBDQS4#
SBDQS5#
SBDQS6#
SBDQS7#
SMVREF1
SMVREF0
SBDM1
AW7
AL11
SBCS0#
SBCS1#
SBCS2#
SBCS3#
SBRAS#
SBCAS#
SBWE#
SBMA0
SBMA1
SBMA2
SBMA3
SBMA4
SBMA5
SBMA6
SBMA7
SBMA8
SBMA9
SBMA10
SBMA11
SBMA12
SBMA13
SBODT0
SBODT1
SBODT2
SBODT3
SBBA0
SBBA1
SBBA2
SBDQS0
SBDQS1
SBDQS2
SBDQS3
SBDQS4
SBDQS5
SBDQS6
SBDQS7
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SBDM0
~M_CHB_CS0
BA40
~M_CHB_CS1
AW41
BA41
AW40
~M_CHB_RAS
BA23
~M_CHB_CAS
AY24
~M_CHB_WE
BB23
M_CHB_MA0
BB22
M_CHB_MA1
BB21
M_CHB_MA2
BA21
M_CHB_MA3
AY21
M_CHB_MA4
BC20
M_CHB_MA5
AY19
M_CHB_MA6
AY20
M_CHB_MA7
BA18
M_CHB_MA8
BA19
M_CHB_MA9
BB18
M_CHB_MA10
BA22
M_CHB_MA11
BB17
M_CHB_MA12
BA17
M_CHB_MA13
AW42
M_CHB_ODT0
AY42
M_CHB_ODT1
AV40
AV43
AU40
M_CHB_BA0
AW23
M_CHB_BA1
AY23
M_CHB_BA2
AY17
M_CHB_DQS0
AM8
~M_CHB_DQS0
AM6
M_CHB_DQS1
AV7
~M_CHB_DQS1
AR9
M_CHB_DQS2
AV13
~M_CHB_DQS2
AT13
M_CHB_DQS3
AU23
~M_CHB_DQS3
AR23
M_CHB_DQS4
AT29
~M_CHB_DQS4
AV29
M_CHB_DQS5
AP36
~M_CHB_DQS5
AM35
M_CHB_DQS6
AG34
~M_CHB_DQS6
AG32
M_CHB_DQS7
AD36
~M_CHB_DQS7
AD38
M_CHB_SCK0
AM29
~M_CHB_SCK0
AM27
M_CHB_SCK1
AV9
~M_CHB_SCK1
AW9
M_CHB_SCK2
AL38
~M_CHB_SCK2
AL36
AP26
AR26
AU10
AT10
AJ38
AJ36
SM_VREF SM_VREF
AM2
SM_VREF
AM4
PLACE 0.1UF CAP CLOSE TO MCH
~M_CHB_CS[0..1] [20,21]
~M_CHB_RAS [20,21]
~M_CHB_CAS [20,21]
~M_CHB_WE [20,21]
M_CHB_MA[0..13] [20,21]
M_CHB_ODT[0..1] [20,21]
M_CHB_BA[0..2] [20,21]
M_CHB_DQS0 [20]
~M_CHB_DQS0 [20]
M_CHB_DQS1 [20]
~M_CHB_DQS1 [20]
M_CHB_DQS2 [20]
~M_CHB_DQS2 [20]
M_CHB_DQS3 [20]
~M_CHB_DQS3 [20]
M_CHB_DQS4 [20]
~M_CHB_DQS4 [20]
M_CHB_DQS5 [20]
~M_CHB_DQS5 [20]
M_CHB_DQS6 [20]
~M_CHB_DQS6 [20]
M_CHB_DQS7 [20]
~M_CHB_DQS7 [20]
M_CHB_SCK0 [20]
~M_CHB_SCK0 [20]
M_CHB_SCK1 [20]
~M_CHB_SCK1 [20]
M_CHB_SCK2 [20]
~M_CHB_SCK2 [20]
C19
C0.1U25Y
U41
X1
MCH
X7
X8
Heatsink
X2
E31-0401730-K08
CPU STRAPPING RESISTORS
ALL COMPONENTS CLOSE TO CPU
R37
80.6R1%0402
C17
X_C0.1U25Y
R41 80.6R1%0402
R38 40.2R1%0402
R42 40.2R1%0402
R39
1KR1%0402
R40
1KR1%0402
PLACE CLOSE TO MCH
C18
C0.1U25Y
V_SM
SM_RCOMP_N
SM_RCOMP_P
SMOCDCOMP1
SMOCDCOMP0
V_SM
M_CHB_DQ24
M_CHB_DQ20
M_CHB_DQ10
M_CHB_DQ14
M_CHB_DQ11
M_CHB_DQ5
M_CHB_DQ4
M_CHB_DQ1
M_CHB_DQ2
M_CHB_DQ3
M_CHB_DQ6
A A
8
M_CHB_DQ[0..63][20]
M_CHB_DQ0
7
M_CHB_DQ13
M_CHB_DQ12
M_CHB_DQ9
M_CHB_DQ7
M_CHB_DQ8
M_CHB_DQ21
M_CHB_DQ18
M_CHB_DQ15
M_CHB_DQ16
M_CHB_DQ23
M_CHB_DQ17
M_CHB_DQ25
M_CHB_DQ22
M_CHB_DQ19
6
M_CHB_DQ32
M_CHB_DQ28
M_CHB_DQ27
M_CHB_DQ26
M_CHB_DQ31
M_CHB_DQ29
M_CHB_DQ33
M_CHB_DQ30
M_CHB_DQ40
M_CHB_DQ34
M_CHB_DQ39
M_CHB_DQ38
M_CHB_DQ37
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ46
M_CHB_DQ42
M_CHB_DQ44
M_CHB_DQ43
M_CHB_DQ41
5
M_CHB_DQ48
M_CHB_DQ47
M_CHB_DQ45
M_CHB_DQ55
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ49
M_CHB_DQ50
M_CHB_CKE[0..1][20,21]
M_CHB_DQ57
M_CHB_DQ56
M_CHB_DQ51
M_CHB_DQ58
M_CHB_DQ54
M_CHB_DM[0..7][20]
M_CHB_CKE0
M_CHB_DQ61
M_CHB_DQ59
M_CHB_CKE1
M_CHB_DQ63
M_CHB_DQ60
M_CHB_DQ62
4
M_CHB_DM1
M_CHB_DM0
M_CHB_DM3
M_CHB_DM2
M_CHB_DM7
M_CHB_DM6
M_CHB_DM5
M_CHB_DM4
Title
Size Document Number Rev
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU Signals
(MS-7164)
2
0C
of
731Monday, June 27, 2005
1
8
D D
V_1P5_CORE
EXP_EN
State Description
Only SDVO or PCI-e
LOW
operating
HIGH
SDVO and PCI-e
operating
C C
B B
simultaneously
BSEL
2
0
1
00
0
0
0
1
0
1
0
SDVO_CTRL_DATA[17]
SDVO_CTRL_CLK[17]
H_FSBSEL0[3,13]
H_FSBSEL1[3,13]
H_FSBSEL2[3,13]
TABLE
PSB FREQUENCY
RESERVED
133 MHZ (533)
200 MHZ (800)
V_1P5_CORE
CK_PE_100M_MCH[13]
CK_PE_100M_MCH#[13]
H_FSBSEL0
H_FSBSEL1
H_FSBSEL2
EXP_SLR (R46 and Normal high)
State Description
Only SDVO or PCI-e
LOW
operating
SDVO and PCI-e
HIGH
operating
simultaneously
V_1P5_CORE
A A
V_1P5_CORE
8
7
V_1P5_CORE
EXP_A_RXP_13[17]
EXP_A_RXN_13[17]
EXP_A_RXP_14[17]
EXP_A_RXN_14[17]
DMI_ITP_MRP_0[10]
DMI_ITN_MRN_0[10]
DMI_ITP_MRP_1[10]
DMI_ITN_MRN_1[10]
DMI_ITP_MRP_2[10]
DMI_ITN_MRN_2[10]
DMI_ITP_MRP_3[10]
DMI_ITN_MRN_3[10]
SDVO_CTRL_DATA
SDVO_CTRL_CLK
EC3
+
_CD470U10EL11-2
C31
C36 C10U10Y0805
C44 C0.1U25Y
C57
X_C0.01U50X
R53 X_1KR0402
R54 1KR0402
R44 _220R0402-1
R45 _220R0402-1
RN7
7 8
5 6
3 4
1 2
8P4R-10KR0402
R46 X_1KR0402
C30
C0.1U25Y
V_2P5_MCH
V_2P5_MCH
CP18
1 2
CP20
1 2
7
C10U10Y0805
C58
X_C0.1U25Y
EXP_A_RXP_13
EXP_A_RXN_13
EXP_A_RXP_14
EXP_A_RXN_14
DMI_ITP_MRP_0
DMI_ITN_MRN_0
DMI_ITP_MRP_1
DMI_ITN_MRN_1
DMI_ITP_MRP_2
DMI_ITN_MRN_2
DMI_ITP_MRP_3
DMI_ITN_MRN_3
CK_PE_100M_MCH
CK_PE_100M_MCH#
VCCA_HPLLVCCA_HPLL
VCCA_MPLL
VCCA_DPLLA
VCCA_DPLLB
VCCA_GPLL
(INTEL-QG82945G-A2-LF)
G12
F12
D11
D12
J13
H13
E10
F10
J9
H10
F7
F9
C4
D3
G6
J6
K9
K8
F4
G4
M6
M7
K2
L1
U11
U10
R8
R7
P4
N3
Y10
Y11
F20
Y7
Y8
AA9
AA10
AA6
AA7
AC9
AC8
B14
B16
F15
E15
BSEL0
F21
BSEL1
H21
BSEL2
L20
AK17
AL17
EXP_SLR
K21
AK23
AK18
L21
L18
N21
C21
B20
C19
B19
B17
D19
C18
B18
A18
V_FSB_VTT
C28
X_C0.1U25Y
C37
X_C0.22U16Y
6
V_1P5_CORE
U2C
EXPARXP0
EXPARXN0
EXPARXP1
EXPARXN1
EXPARXP2
EXPARXN2
EXPARXP3
EXPARXN3
EXPARXP4
EXPARXN4
EXPARXP5
EXPARXN5
EXPARXP6
EXPARXN6
EXPARXP7
EXPARXN7
EXPARXP8
EXPARXN8
EXPARXP9
EXPARXN9
EXPARXP10 / SDVOC_INT+
EXPARXN10 / SDVOC_INTÂEXPARXP11
EXPARXN11
EXPARXP12
EXPARXN12
EXPARXP13 / SDVO_STALL+
EXPARXN13 / SDVO_STALLÂEXPARXP14 / SDVOB_INT+
EXPARXN14 / SDVOB_INTÂEXPARXP15 / SDVO_TVCLKIN+
EXPARXN15 / SDVO_TVCLKIN+
EXP_EN
DMI RXP0
DMI RXN0
DMI RXP1
DMI RXN1
DMI RXP2
DMI RXN2
DMI RXP3
DMI RXN3
GCLKP
GCLKN
SDVOCTRLDATA
SDVOCTRLCLK
BSEL0
BSEL1
BSEL2
RSV_TP[0]
RSV_TP[1]
EXP_SLR
RSV_TP[2]
RSV_TP[3]
RSV_TP[4]
RSV_TP[5]
RSV_TP[6]
VCCAHPLL
VCCAMPLL
VCCADPLLA
VCCADPLLB
VCCA_EXPPLL
VCC2
VCCADAC
VCCADAC
VSSA_DAC
C29
C0.1U25Y
VCCA_HPLL
C32
X_C10U10Y0805
VCCA_MPLL
C38
X_C10U10Y0805
I=45mA
I=60mA
AA24
VCC
6
AA26
AB17
AB18
VCC
VCC
VCC
VTT
VTT
VTT
B23
A24
B24
C33
C0.1U25Y
C39
C0.1U25Y
AB19
AB20
AB24
VCC
VCC
VTT
VTT
B25
B26
C23
V_FSB_VTT[3,4,5,6,25]
V_1P5_CORE
V_1P5_CORE
VCC
VTT
5
V_SM
AV23
AV18
AV21
VCC
AY43
AE26
AE27
AF15
AF17
AF19
VCC
VCC
VCC
VCC
VCC
VCCSM
VCCSM
VCCSM
VCCSM
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF21
AF23
AF25
AF26
AF27
AF29
AG15
AG17
AG18
AG19
V_1P5_CORE
V_1P5_CORE
C35
C0.1U25Y
ANALOG FILTERS
C41
V_1P5_CORE
C0.1U25Y
AB25
AB26
AB27
AC15
AC17
AC18
AC20
AD17
AD19
AC24
AC26
AC27
AD15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
C25
C26
D23
VTT
VTT
VTT
F23
F27
E27
E23
E24
E26
D24
D25
CP19
1 2
CP21
1 2
H23
G23
V_FSB_VTT
AE20
AD23
AD25
AD26
AE17
AE18
AE22
AE24
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
L23
P23
N23
M23
I=55mA
VCCA_DPLLA VCCA_GPLL
C34
X_C10U10Y0805
I=55mA
VCCA_DPLLB
C40
X_C10U10Y0805
5
VCC
VTT
AD21
VCC
VCC
VTT
VTT
J23
K23
AV31
AV42
VCCSM
VCC
AG20
AG21
AW13
VCCSM
VCCSM
VCC
VCC
AG22
AW20
AW15
VCCSM
VCC
AG23
AG24
AW21
VCCSM
VCCSM
VCC
VCC
AJ15
4
AW24
VCCSM
VCC
AJ17
4
AY41
AW29
AW34
AW35
AW31
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCC
VCC
AJ18
AJ20
R51 1R1%
R52 1R1%
L21
0R2010
BB16
BB20
BB24
BB28
BB33
VCCSM
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
AE4
AE3
AE2
AD12
C521
C10U10Y0805
BB38
BB42
BC13
BC18
BC22
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AD8
AD6
AD5
AD4
AD10
I=45mA
C42
X_C10U10Y0805
Ver 0C
C522
C10U10Y0805
3
VCC_EXP
BC26
BC31
BC35
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AD2
BC40
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AD1
AC6
AC13
VCC_EXP
N12
N11
N10
N5
VCCSM
VCC_EXP
VCC_EXP
VCC_EXPN9VCC_EXPN7VCC_EXP
SDVOB_ALPHA+ / SDVOC_R+ / EXPATXP11
SDVOB_ALPHA- / SDVOC_R- / EXPATXN11
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXPV9VCC_EXP
Y13
V13
V10
AA5
AC5
AA13
C43
C0.1U25Y
C523
C10U10Y0805
3
U13
R13
R11
R10
VCC_EXP
VCC_EXPU8VCC_EXPU7VCC_EXPU6VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXPR5VCC_EXP
SDVOC_CLK+ / EXPATXP8
SDVOC_CLK+ / EXPATXN8
SDVOB_CLK+ / EXPATXP12
SDVOB_CLK- / EXPATXN12
VCC_EXPV7VCC_EXPV6VCC_EXP
EXPATXP0
EXPATXN0
EXPATXP1
EXPATXN1
EXPATXP2
EXPATXN2
EXPATXP3
EXPATXN3
EXPATXP4
EXPATXN4
EXPATXP5
EXPATXN5
EXPATXP6
EXPATXN6
EXPATXP7
EXPATXN7
SDVOC_B+ / EXPATXP9
SDVOC_B- / EXPATXN9
SDVOC_G+ / EXPATXP10
SDVOC_G- / EXPATXN10
SDVOB_B+ / EXPATXP13
SDVOB_B- / EXPATXN13
SDVOB_G+ / EXPATXP14
SDVOB_G- / EXPATXN14
SDVOB_R+ / EXPATXP15
SDVOB_R- / EXPATXN15
DMI TXP0
DMI TXN0
DMI TXP1
DMI TXN1
DMI TXP2
DMI TXN2
DMI TXP3
DMI TXN3
EXP_COMPO
EXP_COMPI
HSYNC
VSYNC
GREEN
GREENB
BLUE#
DDC_DATA
DDC_CLK
DREFCLKINP
DREFCLKINN
EXTTS#
XORTEST
ALLZTEST
V5
VCC_EXP
2
V_SM
C20 C10U10Y0805
C22 C10U10Y0805
C24 C10U10Y0805
C26 C10U10Y0805
V_SM
C21 C10U10Y0805
C23 C10U10Y0805
C25 X_C10U10Y0805
C27 X_C10U10Y0805
GRCOMP
R43 24.9R1%
CRT_HSYNC
CRT_VSYNC
CRT_R
CRT_G
CRT_B
R48 255R1%
R49 10KR
EXP_A_TXP_12 [17]
EXP_A_TXN_12 [17]
EXP_A_TXP_13 [17]
EXP_A_TXN_13 [17]
EXP_A_TXP_14 [17]
EXP_A_TXN_14 [17]
EXP_A_TXP_15 [17]
EXP_A_TXN_15 [17]
DMI_MTP_IRP_0 [10]
DMI_MTN_IRN_0 [10]
DMI_MTP_IRP_1 [10]
DMI_MTN_IRN_1 [10]
DMI_MTP_IRP_2 [10]
DMI_MTN_IRN_2 [10]
DMI_MTP_IRP_3 [10]
DMI_MTN_IRN_3 [10]
V_1P5_CORE
CRT_HSYNC [15]
CRT_VSYNC [15]
CRT_R [15]
CRT_G [15]
CRT_B [15]
3VDDCDA [15]
3VDDCCL [15]
DOT_96M [13]
-DOT_96M [13 ]
V_2P5_MCH
TESTIN# [19]
GROMP trace 20mils
RED
BLUE
RED#
IREF
D14
C13
A13
B12
A11
B10
C10
C9
A9
B7
D7
D6
A6
B5
E2
F1
G2
J1
J3
K4
L4
M4
M2
N1
P2
T1
T4
U4
U2
V1
V3
W4
W2
Y1
AA2
AB1
Y4
AA4
AB3
AC4
AC12
AC11
D17
C17
F17
K17
H18
G17
J17
J18
N18
N20
J15
H15
A20
J20
H20
K18
EXP_A_TXP_12
EXP_A_TXN_12
EXP_A_TXP_13
EXP_A_TXN_13
EXP_A_TXP_14
EXP_A_TXN_14
EXP_A_TXP_15
EXP_A_TXN_15
DMI_MTP_IRP_0
DMI_MTN_IRN_0
DMI_MTP_IRP_1
DMI_MTN_IRN_1
DMI_MTP_IRP_2
DMI_MTN_IRN_2
DMI_MTP_IRP_3
DMI_MTN_IRN_3
3VDDCDA
3VDDCCL
DOT_96M
-DOT_96M
EXTTS
MICRO-STAR INt'L CO., LTD.
Title
Intel Lakeport - CPU Signals
Size Document Number Re v
Date: Sheet
2
(MS-7164)
831Monday, June 27, 2005
1
DMI Differential
impedance 100ohm
+-20%
of
1
0C
8
7
6
5
4
3
2
1
(INTEL-QG82945G-A2-LF)
D D
C C
B B
U2D
A16
A22
A26
A31
A35
B11
B13
B21
B22
B28
B33
B38
C12
C14
C22
C40
D10
D16
D20
D21
E12
E13
E17
E18
E20
E21
E32
F13
F18
F26
F34
F42
G10
G13
G15
G18
G20
G21
G24
G27
G29
G31
G32
G35
G38
H12
H17
H26
H27
H32
AL37
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
B4
VSS
B6
VSS
B9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C3
VSS
C5
VSS
C7
VSS
VSS
VSS
VSS
VSS
D2
VSS
D5
VSS
VSS
VSS
VSS
VSS
E3
VSS
E4
VSS
E7
VSS
E9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F2
VSS
F6
VSS
VSS
VSS
VSS
VSS
VSS
G3
VSS
G5
VSS
G7
VSS
G9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J2
VSS
J5
VSS
J7
VSS
J10
VSS
VSS
VSS
VSS
VSS
VSS
J12
J21
J24
J43
J38
J29
VSS
VSS
VSS
VSS
VSS
VSSK7VSSK6VSSK5VSSK3VSS
K10
VSS
VSS
K20
K15
K13
K12
K34
K32
K27
VSS
VSS
AP5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSD1VSS
VSSA4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSL2VSS
VSS
L29
L26
L24
L13
L12
K39
K37
VSSM9VSSM8VSSM5VSSM3VSS
L31
L42
M10
VSS
M13
VSS
M20
VSS
M21
VSS
M35
VSS
M37
VSS
VSSN8VSSN6VSS
N2
N24
N15
N13
N26
N27
N29
N31
N33
N36
N39
VSS
N43
VSS
VSS
VSS
VSSP3VSS
P24
P15
P14
VSSR9VSSR6VSS
VSS
VSS
VSS
P26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSST2VSS
VSSU3VSSU5VSSU9VSS
VSS
VSS
VSS
VSS
VSS
VSSV2VSSV8VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSW3VSSY2VSSY5VSSY6VSSY9VSS
R31
R34
R37
R39
T42
U12
U14
U31
U33
U36
U38
V11
V12
V14
V34
V36
V37
V38
V39
V43
P30
P29
P27
R12
R14
R30
VSS
VSS
VSS
VSS
Y12
Y14
Y31
Y35
Y37
Y39
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF20
AF22
AF24
AY1
BC4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL33
VSS
AL32
VSS
AL27
VSS
AL24
VSS
AL23
VSS
AL21
VSS
AL18
VSS
AL15
VSS
AL13
VSS
AL12
VSS
AL10
VSS
AL7
VSS
AL3
VSS
AL2
VSS
AL1
VSS
AK30
VSS
AK29
VSS
AK26
VSS
AK24
VSS
AJ37
VSS
AJ35
VSS
AJ33
VSS
AJ31
VSS
AJ30
VSS
AJ10
VSS
AJ7
VSS
AH42
VSS
AG39
VSS
AG38
VSS
AG37
VSS
AG36
VSS
AG33
VSS
AG31
VSS
AG30
VSS
AF43
VSS
AF38
VSS
AF36
VSS
AF33
VSS
AF5
VSS
AF3
VSS
AF2
VSS
AF1
VSS
AD42
VSS
AD37
VSS
AD35
VSS
AD33
VSS
AD13
VSS
AD11
VSS
AD9
VSS
AD7
VSS
AC39
VSS
AC38
VSS
AC37
VSS
AC36
VSS
AC31
VSS
AC23
VSS
AC21
VSS
AC14
VSS
AC10
VSS
AC7
VSS
AC3
VSS
AC2
VSS
AB43
VSS
AB2
VSS
AA36
VSS
AA33
VSS
AA31
VSS
AA23
VSS
AA21
VSS
AA14
VSS
AA12
VSS
AA11
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AA8
L17
AF18
AE21
AE23
AE25
Y42
AA3
AE19
AD29
AD27
AD24
AD22
AD20
AD18
AC29
AC25
AC19
AA29
AA27
AA25
Y29
Y26
Y24
Y22
Y20
W25
W23
W21
V29
V26
V24
U29
R29
R26
D43
A40
BC9
BB41
BB39
BB34
BB19
BB14
BB11
BB6
BB3
BA42
BA4
AW10
AV37
AV17
AV10
AV2
AU34
AU32
AU29
AU26
AU24
AU21
AU20
AU17
AU15
AU13
AU12
AU9
AU6
AT31
AT27
AT26
AT23
AT21
AT18
AT17
AT12
AR43
AR39
AR37
AR32
AR24
AR20
AR15
AR6
AR1
AP38
AP34
AP29
AP12
AP10
AP7
AN42
AN31
AN27
AN26
AN24
AN23
AN21
AN20
AN18
AN17
AN15
AN13
AN4
AN2
AM39
AM37
AM36
AM33
AM9
AM7
AM5
AL43
A A
MSI
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU Signals
(MS-7164)
2
931Monday, June 27, 2005
0C
of
1
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