MSI MS-7164 Schematics

1
Cover Sheet
1
MS-7164 VER:0D
Block Diagram Intel LGA775 CPU - Signals Intel LGA775 CPU - Power Intel LGA775 CPU- GND Intel Lakeport - CPU Intel Lakeport - Memory Intel Lakeport - PCI Express Intel Lakeport - GND ICH7 Signal, Power, GND 10-12 Clock - CLOCK ICS954101DF & FWH SIO NS PC8375L/K/T & I/O CONNECTOR SERIAL PORT & VGA CONNECTOR AC97 Audio Codec- AD1888
A A
LAN Intel Tekoa 82573E DDR2 System Memory 1 , 2 DDR VTT DECPUPLING IBM Slim IDE & SATA Conn. ATX & FRONT PANEL & FAN
13 14 15 16 17PCI-E X1 & PCI & ADD2R-N SLOT 18 20 21 22 23
2 3 4 5 6 7 8 9
CPU:
Intel Prescott ( L2=2MB ) Intel Cendar Mill (65nm) Intel Smithfield
System Chipset:
Intel Lakeport - GMCH (North Bridge) Intel ICH7 South Bridge
On Board Chipset:
Main Memory:
2 CHANNEL DDR2 * 2 (Max 2GB)
PCI-E Slots:
Rear Side I/O
USB USB
Line_Out
Line_In
LAN USB USB
LPT Port
COM B Port
.............
............
.....
....
VGA Port
.....
.....
.....
MS
KB
.
.
.
.
...
.
.
.
.
.
PCI-E X1 & PCI & ADD2-N SLOT
Intersil PWM: 4-phase
Controller: HIP6556BCR
Front Side I/O
Line_Out Mic_In USB USB
Driver: HIP6602BCR *2
USB Connectors MS-7 ACPI CONTROLLER VRM10.1 - INTERSIL 6556 4PHASE Decoupling CAP GPIO & Jumper setting Power Delivery Mapping Revision History Manual Parts
24 25 26 27 28 29 30
BOM Config
Option ERP NumberMODEL Config. ORCAD Config.
MSI
1
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR INt'L CO., LTD .
COVER SHEET
(MS-7164)
131Tuesday, August 16, 2005
0D
VRM_GD
VTT_PWG
VRM 10.1 Intersil 6556 4-Phase PWM
P.27
VTT_PWG
Intel LGA775 Processor
FSB
533/800/1066
H_CPURST#
P.3~5
CHANNEL A CHANNEL B
533/667
1
2 DDR2 DIMM Modules
VID_GD
VTT_PWG
MS-7164
System Block Diag ram
P.20-21
1
P.25
Intel 82573E
PCIRST_ICH6#
SLP_S4#
SLP_S3#
ATX1
PCIRST#2
PCI-E Slot
P.18
PWR_OK
PCIRST#2
PCIRST#1
RSMRST#
PWR_GD
MS7
RSMRST#
HD_RST#
P.27
P.6~9
PWR_GD
ADD2
PWR_GD
PCI + PCI-E x1
PCI-E x1
Analog Video Out
HD_RST#
A A
UltraBay Silm Enhance
SERIAL ATA1
P.15
P.23
P.22
H_PWRGD
VRM_GD
UltraDMA 33/66/100
Lakeport GMCH
DMI
ICH7
PLTRST#
USB2.0 USB Port 0~ 7
P.24
JFP1
P.24
RSMRST#
PWRBTN#
P.10~12
LPC Bus
FWH
AD1888
AC'97 Codec
AC-LINK
P.16
8M Flash
P.14
LPC SIO NS
PC8374L/K/T
Keyboard
Mouse
P.14
P.14
Parallel Port
P.14
Serial Port
COM B
P.15P.14
CPU_FAN1
REAR_FAN1
SYS_FAN1
MICRO-STAR INt'L CO., LTD.
MSI
P.23
1
Title
Size Document Number Rev
Date: Sheet
BLOCK DIAGRAM
(MS-7164)
231Tuesday, August 16, 2005
of
0D
8
7
6
5
4
DBRESET#
3
DBRESET# [11,19]
2
1
CPU SIGNAL BLOCK
H_VID1
AL5
VID2#
VID1#
BPM5# BPM4# BPM3# BPM2# BPM1# BPM0#
REQ4# REQ3# REQ2# REQ1# REQ0#
RSVD
RS2# RS1# RS0#
AP1# AP0# BR0#
DP3# DP2# DP1# DP0#
H_VID0
AM2
VID0#
VCC_VRM_SENSE [26] VSS_VRM_SENSE [26]
H_VID[0..5] [26]
VID_SELECT L--VRD10.1 H--VRD11
AN7
CPU_GTLREF0
H1
CPU_GTLREF1
H2
TEST_H29
H29
MCH_GTLREF_CPU
E24
H_BPM#5
AG3
H_BPM#4
AF2
H_BPM#3
AG2
H_BPM#2
AD2
H_BPM#1
AJ1
H_BPM#0
AJ2 G5
H_REQ#4
J6
H_REQ#3
K6
H_REQ#2
M6
H_REQ#1
J5
H_REQ#0
K4
H_TESTHI12
W2
H_TESTHI11
P1
H_TESTHI10
H5
H_TESTHI9
G4
H_TESTHI8
G3 F24 G24 G26 G27 G25
H_TESTHI2_7
F25
H_TESTHI1
W3
H_TESTHI0
F26
RSVD_AK6
AK6
RSVD_G6
G6
CK_H_CPU#
G28
CK_H_CPU
F28
H_RS#2
A3
H_RS#1
F5
H_RS#0
B3
TEST_U3
U3
TEST_U2
U2
H_BR#0
F3
H_COMP5
T2
H_COMP4
J2
H_COMP3
R1
H_COMP2
G2
H_COMP1
T1
H_COMP0
A13
TEST_J17
J17
TEST_H16
H16
TEST_H15
H15
TEST_J16
J16 AD5
R6 C17 G19 E12 B9 A16 G20 G12 C8 L1 K1
3
R14 62R0402
TEST_H29
MCH_GTLREF_CPU [6] H_BPM#[0..5] [19]
For ITP Port
H_REQ#[0..4] [6]
0D Lenovo Request
RSVD_AK6
R8 62R0402 R9 62R0402 R10 62R0402
R12 X_62R0402
CK_H_CPU# [13] CK_H_CPU [13]
H_RS#[0..2] [6]
TEST_U3 TEST_U2
R22 60.4R1%0402 R23 60.4R1%0402 R13 60.4R1%0402 R15 60.4R1%0402 R16 60.4R1%0402 R17 60.4R1%0402
TEST_J17 TEST_H16 TEST_H15 TEST_J16
H_ADSTB#1 [6] H_ADSTB#0 [6] H_DSTBP#3 [6] H_DSTBP#2 [6] H_DSTBP#1 [6] H_DSTBP#0 [6] H_DSTBN#3 [6] H_DSTBN#2 [6] H_DSTBN#1 [6] H_DSTBN#0 [6] H_NMI [10] H_INTR [10]
VID Pull-Up Resistor
VTT_OUT_RIGHT
RN1
8P4R-680R
H_VID3
1 2
H_VID1
3 4
H_VID4
5 6
H_VID2
7 8
H_VID0
R2 680R0402 R3 680R0402
H_VID5
VTT_OUT_RIGHT
R6 49.9R1%0402
H_TMS
H_BPM#4 H_TDO H_BPM#2
H_TDI
H_BPM#3 H_BPM#5 H_BPM#1 H_BPM#0
VTT_OUT_LEFT
H_TESTHI12 H_TESTHI10 H_TESTHI9 H_TESTHI8 H_TESTHI11
R846 0R0402
V_FSB_VTT VTT_OUT_LEFT V_FSB_VTT VTT_OUT_RIGHT VTT_OUT_LEFT
H_BR#0 [6]
PLACE RESISTORS OUTSIDE SOCKET CAVITY IF NO ROOM FOR VARIABLE RESISTOR DON'T PLACE
COMP5 Rt COMP4 Rt COMP3 Rt COMP2 Rt COMP1 Rt COMP0 Rt
Lakeport Design Guide Define COMP[7:4] Rpu=60.4ohm +- 1% COMP[3:0] Rpd=60.4ohm +- 1%
MSI
Title
Size Document Number Rev
Date: Sheet
2
V_FSB_VTT VTT_OUT_LEFT VTT_OUT_RIGHT
Prescott Celeron-D CedarMill Smithfield
NC NC NC NC VSS VSS
MICRO-STAR INt'L CO., LTD.
RN2 _8P4R-51R0402-LF
1 2 3 4 5 6 7 8
7 8 5 6 3 4 1 2
R7 62R0402
7 8 5 6 3 4 1 2
RN4 _8P4R-62R0402-LF
VTT
VTT
VTT
VTT
VTT
NC
VTT
NC VSS
VSS
VSS
VSS
C1 C0.1U25Y RN3 _8P4R-51R0402-LF
C2 C0.1U25Y
C520 C0.1U25Y
H_FORCEPH_IO [14] V_FSB_VTT [4,6,8,12,25]
VTT_OUT_LEFT [4,5]
VTT_OUT_RIGHT [4,5,19]
VTT_OUT_RIGHT
C5
X_C0.1U25Y
NC NC VSS VSS VSS VSS
Intel LGA775 CPU - Signals
(MS-7164)
1
331Tuesday, August 16, 2005
0D
of
TEST_AN4
TEST_AN3
H_A#[3..31][6]
D D
H_A#5
H_A#9
H_A#10
H_A#8
H_A#31
H_A#26
H_A#25
H_A#30
H_A#29
AJ6
AJ5
AH5
AH4
AG5
AG4
AG6
A35#
A34#
A33#
A32#
A31#
A30#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D20
G22
D22
E22
G21
F21
E21
H_D#42
H_D#43
H_D#45
H_D#46
H_D#44
H_D#47
H_D#48
100 OHMS OVER 210 OHMS RESISTORS
GTLREF VOLTAGE SHOULD BE
0.67*VTT = 0.8V
VTT_OUT_LEFT
VTT_OUT_LEFT
C C
R20
49.9R1%0402
R18
49.9R1%0402
R21 100R1%0402
R19 100R1%0402
CPU_GTLREF0
C6 C1U10Y
CPU_GTLREF1
C3 C1U10Y
C7
X_C2200P16X
C4
X_C2200P16X
PLACE AT CPU END OF ROUTE
VTT_OUT_RIGHT
VTT_OUT_LEFT VTT_OUT_LEFT
R24 62R0402 R25 120R0402
R27 100R1%0402 R28 62R0402 R29 62R0402
R4 49.9R1%0402 R5 49.9R1%0402 R11 X_62R0402
H_CPURST# H_PROCHOT#
H_PWRGD H_BR#0 H_TESTHI13
H_TRST# H_TCK
H_DBI#[0..3][6]
H_IERR#[4]
H_FERR#[4,10]
H_STPCLK#[10]
H_INIT#[10]
H_DBSY#[6] H_DRDY#[6] H_TRDY#[6]
H_ADS#[6] H_LOCK#[6]
H_BNR#[6]
H_HIT#[6]
H_HITM#[6]
H_BPRI#[6] H_DEFER#[6]
H_TDI[19]
H_TDO[19] H_TMS[19] H_TRST#[19] H_TCK[19]
THERMDP#[14] THERMDN#[14]
TRMTRIP#[4,10,14]
H_IGNNE#[10]
ICH_H_SMI#[10,14]
H_A20M#[10]
H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3
H_TDI H_TDO H_TMS H_TRST# H_TCK
H_PROCHOT#
H_TESTHI13
LL_ID[1:0] = TBD for the Smithfield
VTT_OUT_RIGHT VTT_OUT_RIGHT
B B
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEAJS AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
BSEL
1
2
0
0
1
0
0
01
A A
R30 X_62R0402 R31 X_62R0402
RN6 8P4R-470R
12 34 56 78
TABLE
0 FSB FREQUENCY
267 MHZ (1067)
0
0
200 MHZ (800)
133 MHZ (533)
8
H_FSBSEL1 H_FSBSEL2 H_FSBSEL0
LL_ID0 LL_ID1
LL_ID0 LL_ID1
H_FSBSEL0[8,13] H_FSBSEL1[8,13] H_FSBSEL2[8,13]
H_PWRGD[10,19]
H_CPURST#[6,19]
H_D#[0..63][6]
7
H_D#63 H_D#62 H_D#61 H_D#60 H_D#59 H_D#58 H_D#57 H_D#56 H_D#55 H_D#54
G11 D19 C20
AB2 AB3
AD3
AD1 AF1 AC1 AG1 AE1 AL1 AK1
AE8 AL2
AH2 AE6 G10
D16 A20
AA2 G29
H30 G30
G23 B22
A22 A19 B19 B21 C21 B18 A17 B16 C18
6
U1A
A8
F2
R3 M3
P3 H4
B2 C1 E3
D2 C3 C2 D4 E4 G8 G7
M2
N2 P2 K3
L2
N5 C9
Y1 V2
N1
DBI0# DBI1# DBI2# DBI3#
EDRDY# IERR# MCERR# FERR#/PBE# STPCLK# BINIT# INIT# RSP#
DBSY# DRDY# TRDY#
ADS# LOCK# BNR# HIT# HITM# BPRI# DEFER#
TDI TDO TMS TRST# TCK THERMDA THERMDC THERMTRIP# GND/SKTOCC# PROCHOT# IGNNE# SMI# A20M# TESTI_13
RSVD RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5
BOOTSELECT LL_ID0 LL_ID1
BSEL0 BSEL1 BSEL2
PWRGOOD RESET# D63#
D62# D61# D60# D59# D58# D57# D56# D55# D54#
D53#
B15
C14
H_D#52
H_D#53
D52#
D51#
D50#
C15
A14
D17
H_D#50
H_D#49
H_D#51
H_A#22
H_A#23
H_A#27
H_A#28
AF4
AF5
AB4
A29#
A28#
A27#
D42#
D41#
D40#
F20
E19
E18
H_D#41
H_D#39
H_D#40
H_A#19
H_A#24
H_A#20
H_A#21
H_A#18
AC5
AB5
AA5
AD6
AA4Y4Y6W6AB6W5V4V5U4U5T4U6T5R4M4L4M5P6L5
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
F18
F17
G17
G18
E16
E15
G16
G15
H_D#38
H_D#34
H_D#31
H_D#36
H_D#33
H_D#37
H_D#35
H_D#32
5
H_A#11
H_A#16
H_A#15
H_A#12
H_A#14
H_A#13
H_A#17
A18#
A17#
A16#
D31#
D30#
D29#
F15
G14
H_D#30
H_D#29
A9#
A15#
A14#
A13#
A12#
A11#
A10#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
F14
G13
E13
D13
F12
F11
D10
E10D7E9F9F8G9D11
H_D#28
H_D#23
H_D#24
H_D#21
H_D#26
H_D#25
H_D#27
H_D#22
DBRESET#
H_A#7
H_A#3
VSS_SENSE
VCC_VRM_SENSE
H_A#6
H_A#4
A8#
A7#
A6#
A5#
A4#
D21#
D20#
D19#
D18#
D17#
H_D#16
H_D#19
H_D#17
H_D#20
H_D#18
VSS_VRM_SENSE
VCC_SENSE
AC2
AN3
AN4
AN5
AN6
A3#
DBR#
VSS_SENSE
VCC_SENSE
VSS_MB_REGULATION
VCC_MB_REGULATION
D16#
D15#
D14#
D13#
D12#
D11#
D10#
D9#
C12
B12D8C11
B10
A11
A10A7B7B6A5C6A4C5B4
H_D#14
H_D#13
H_D#15
H_D#12
H_D#10
H_D#11
H_D#8
H_D#9
4
H_VID4
H_VID2
H_VID3
H_VID5
AJ3
AK3
AM5
AL4
AK4
AL6
AM3
AM7
VID6#
VID5#
VID4#
VID3#
RSVD
VID_SELECT
ITP_CLK1
ITP_CLK0
GTLREF0 GTLREF1
GTLREF_SEL
CS_GTLREF
PCREQ#
TESTHI12 TESTHI11 TESTHI10
TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0
FORCEPH
BCLK1# BCLK0#
COMP5 COMP4 COMP3 COMP2 COMP1 COMP0
ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1# DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0#
LINT1/NMI
D8#
H_D#7
LINT0/INTR
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
ZIF-SOCK775-15u
H_D#0
H_D#6
H_D#5
H_D#3
H_D#1
H_D#4
H_D#2
8
7
6
5
4
3
2
1
VCCP
AF21
U1B
VCCP
D D
C C
AF19 AF18 AF15 AF14 AF12 AF11
AE9 AE23 AE22 AE21 AE19 AE18 AE15 AE14 AE12 AE11
AD8
AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23
AC8
AC30 AC29 AC28 AC27 AC26 AC25 AC24 AC23
AB8
AA8
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
VCC
VCC
VCC
VCC
Y30
Y8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y23
Y24
Y25
Y26
Y27
Y28
Y29
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W27
W28
W29
W30
W8
VCC
VCC
W26
W25
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W23
W24
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
U25
U26
U27
U28
U29
U30U8V8
AH28
AH29
AH30
AH8
AH9
AJ11
AJ12
AJ14
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
AK25
AK26
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
AM18
AM19
AM21
AM22
AM25
AM26
AM29
AM30
AM8
AM9
AN11
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VSSA
VCCPLL
VCC-IOPLL
VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT
VTTPWRGD
VTT_OUT_RIGHT
VTT_OUT_LEFT
VTT_SEL
RSVD
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AN9
J10
J11
J12
J13
J14
J15
J18
J19
J20
J21
J22
J23
J24
J25
J26
J27
J28
J29
J30J8J9
K23
K24
K25
K26
K27
K28
K29
K30K8L8
M23
M24
M25
M26
M27
M28
M29
M30M8N23
N24
N25
N26
N27
N28
N29
N30N8P8R8T23
T24
T25
T26
T27
T28
T29
T30T8U23
U24
AN30
AN8
ZIF-SOCK775-15u
AN25
AN26
AN29
H_VCCA
A23
H_VSSA
B23 D23
H_VCCIOPLL
C23
A25 A26 A27 A28 A29 A30 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28
VCCFUSEPRG
D29
VIDFUSEPRG
D30
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1 F27
F29
D23 VCCPLL Smithfield define the
support future processor.
V_FSB_VTT
VTT_OUT_RIGHT [3,5,19] VTT_OUT_LEFT [3,5]
R521 X_1KR0402
R522
VTT_SEL
X_0R0402
V_FSB_VTT [3,6,8,12]
V_FSB_VTT
AH27
AH26
AH25
AH22
AH21
AH19
AH18
AH15
AH14
AH12
AH11
AG9
AG8
AG30
AG29
AG28
AG27
AG26
AG25
AG22
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
VCCP
B B
It must close bulk caps.
V_FSB_VTT H_VCCIOPLL
DC voltage drop should be less than 70mV.
It support DC current if 125mA.
L1 X_10U100m_0805
CP15 X_COPPER
L2 X_10U100m_0805
EC1
C22U6.3X1206
EC2
X_C10U10Y0805
H_VSSA
C11
C1U10Y
H_VCCA
PLACE AT ICH END OF ROUTE
RN5 _8P4R-62R0402-LF
TRMTRIP#VTT_OUT_RIGHT
12
H_FERR#
34 56
H_IERR#
78
TRMTRIP# [3,10,14] H_FERR# [3,10]
H_IERR# [3]
MSI
VTT_OUT_RIGHT
R524
A A
VCC5_SB
R523 1KR0402
VID_GD#[25,26]
R525 10KR0402
8
7
1.25V VTT_PWRGOOD
680R0402
VTT_PWG
SOT23EBC
Q1
N-MMBT3904_NL_SOT23
ECB
6
V_FSB_VTT
5
C8 X_C10U10Y0805 C9 C10U10Y0805 C10 C10U10Y0805
4
Title
MICRO-STAR INt'L CO., LTD.
Intel LGA775 CPU - Power
Size Document Number Rev
(MS-7164)
431Tuesday, August 16, 2005
3
Date: Sheet
2
of
1
0D
8
3
]
R526
VTT_OUT_RIGHT
,4,19
D D
C C
B B
62R0402 TEST_F6
R527 62R0402
U1C
A12
VSS
A15
VSS
A18
VSS
A2
VSS
A21
VSS
A24
VSS
A6
VSS
A9
VSS
AA23
VSS
AA24
VSS
AA25
VSS
AA26
VSS
AA27
VSS
AA28
VSS
AA29
VSS
AA3
VSS
AA30
VSS
AA6
VSS
AA7
VSS
AB1
VSS
AB23
VSS
AB24
VSS
AB25
VSS
AB26
VSS
AB27
VSS
AB28
VSS
AB29
VSS
AB30
VSS
AB7
VSS
AC3
VSS
AC6
VSS
AC7
VSS
AD4
VSS
AD7
VSS
AE10
VSS
AE13
VSS
AE16
VSS
AE17
VSS
AE2
VSS
AE20
VSS
AE24
VSS
AE25
VSS
AE26
VSS
AE27
VSS
AE28
VSS
AE29
7
TEST_F23
TEST_E23
TEST_E7
TEST_F23
TEST_F6
TEST_E7
TEST_E23
Y3
AE3
AE4D1D14
E23E5E6E7F23F6B13J3N4P5V1W1AC4Y7Y5Y2W7W4V7V6V30V3V29
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
IMPSEL#
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF20
AF23
AF24
AF25
AF26
AF27
AF28
AF29
VSS
COMP6
COMP7
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE30
AE5
AE7
AF10
AF13
AF16
AF17
VSS
R529X_62R0402
R528 62R0402
RSVD
RSVD
RSVD
MSID[1]
MSID[0]
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AF30
AF6
AF7
AG10
AG13
AG16
RSVD
VSS
6
0D
R530 62R0402
VSS
VSS
VSS
VSS
VSS
VSS
AG17
AG20
AG23
AG24
AG7
VTT_OUT_LEFT [3,4]
V28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH1
AH10
AH13
AH16
AH17
AH20
AH23
AH24
V27
V26
V25
VSS
VSS
VSS
VSS
VSS
VSS
AH3
AH6
AH7
5
MSID1 MSID0 2005 Perf FMB 0 0 2005 Value FMB 0 1
V24
V23U7U1T7T6T3R7R5R30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ10
AJ13
AJ16
AJ17
AJ20
VSS
VSS
R29
R28
R27
R26
R25
R24
R23R2P7P4P30
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ23
AJ24
AJ27
AJ28
AJ29
AJ30
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
4
P29
P28
P27
P26
P25
P24
P23N7N6N3M7M1L7L6L30L3L29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
AL17
AL20
AL23
AL24
AL27
AL28
AL3
AL7
L28
AM1
VSS
VSS
L27
AM10
VSS
VSS
L26
AM13
VSS
VSS
L25
AM16
VSS
VSS
L24
VSS
VSS
AM17
3
L23K7K5
VSS
VSS
VSS
VSS
AM20
AM23
2
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
H28H3H6H7H8H9J4J7K2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AM24
AM27
AM28
AM4
AN1
AN10
AN13
AN16
AN17
AN2
AN20
AN23
AN24
AN27
AN28B1B11
B14
H14
VSS
H13
VSS
H12
VSS
H11
VSS
H10
VSS
G1
VSS
F7
VSS
F4
VSS
F22
VSS
F19
VSS
F16
VSS
F13
VSS
F10
VSS
E8
VSS
E29
VSS
E28
VSS
E27
VSS
E26
VSS
E25
VSS
E20
VSS
E2
VSS
E17
VSS
E14
VSS
E11
VSS
D9
VSS
D6
VSS
D5
VSS
D3
VSS
D24
VSS
D21
VSS
D18
VSS
D15
VSS
D12
VSS
C7
VSS
C4
VSS
C24
VSS
C22
VSS
C19
VSS
C16
VSS
C13
VSS
C10
VSS
B8
VSS
B5
VSS
B24
VSS
B20
VSS
B17
VSS
ZIF-SOCK775-15u
1
HEAT SINK Retention Module
U25
HEATSINK_RM
8
1
5 6 7
A A
16 15 14
13
3
8
7
6
5
9
2
10 11 12
18 19 20
4
17
4
3
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel LGA775 CPU - GND
(MS-7164)
2
531Thursday, August 18, 2005
of
1
0D
8
7
6
V_1P5_CORE
5
4
3
2
1
M34
M38
AA37
M36
AA41
W42
W41
W40
M31 M29
AJ12
M18
J39
K38
J42
K35
J37
N35 R33 N32 N34
N42 N37 N38 R32 R36 U37 R35 R38 V33 U34 U32 V42 U35 Y36 Y38
V32 Y34
V35
F38
D42 U39 U40
E41 D41 K36 G37 E42
U41 P40
U42 V41 Y40
T40
Y43
T43
AJ9 C30
A28 C27 B27
D27 D28
U2A
HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31#
HAD_STB0# HAD_STB1# HPCREQ#
HBREQ0# HBPRI#
HBNR# HLOCK# HADS# HREQ0#
HREQ1# HREQ2# HREQ3# HREQ4#
HHIT# HHITM# HDEFER#
HTRDY# HDBSY# HDRDY# HEDRDY#
RS0# RS1# RS2#
HCLKP HCLKN
PWROK HCPURST#
RSTIN# ICH_SYNC#
HRCOMP HSCOMP HSWING
HDVREF HACCVREF
N17
P17
P18
P20
P21
AA22
AB21
AB22
AB23
AC22
AD14
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF30
AG2
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AG11
AG12
AG13
AG14
AH1
AH2
AH4
AJ5
AJ13
AJ14
AK2
AK3
AK4
AK14
AK15
AK20
R15
R17
R18
R20
R21
R23
R24
U15
U17
U18
U19
U20
U21
U22
U23
U24
U25
U26
V15
V17
V18
V19
V20
V21
V22
V23
V25
V27
W17
W18
W19
W20
W22
W24
W26
W27
Y15
VCC
VCC
VCC
VCC
VCC
RSVRD
AA35
AA42
VCC
VCC
RSVRD
RSVRD
AA34
VCC
RSVRD
AA38
VCC
RSVRD
L15
M15
VCC
VCC
RSVRD
RSVRD
U27
R27
VCC
VCC
RSVRD
RSVRD
A43
M11
VCC
VCC
RSVRD
RSVRD
AG25
VCC
RSVRD
AG26
AG27
VCC
VCC
RSVRD
RSVRD
AJ24
VCC
RSVRD
AJ27
AK40
VCC
VCC
RSVRD
RSVRD
AL39
AW17
VCC
VCC
RSVRD
RSVRD
AW18
VCC
RSVRD
AY14
BC16
VCC
VCC
RSVRD
RSVRD
AD30
VCC
RSVRD
AC34
VCC
RSVRD
Y30
Y33
VCC
VCC
RSVRD
RSVRD
AF31
VCC
RSVRD
AD31
U30
VCC
VCC
RSVRD
RSVRD
V31
VCC
RSVRD
AC30
AA30
VCC
VCC
RSVRD
RSVRD
AK21
AJ23
VCC
VCC
RSVRD
RSVRD
AJ26
VCC
RSVRD
AL29
VCC
RSVRD
AL20
VCC
RSVRD
AJ21
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
RSVRD
RSVRD
RSVRD
RSVRD
RSVRD
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
AL26
AK27
AJ29
AG29
V30
BC43
BC42
BC2
BC1
BB43
BB2
BB1
BA2
VCC
M17
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
KDINV_0# HDINV_1# HDINV_2# HDINV_3#
HD_STBP0# HD_STBN0#
HD_STBP1# HD_STBN1#
HD_STBP2# HD_STBN2#
HD_STBP3#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AW26
AW2
AV27
AV26
E35
C42C2B43
B42
B41B3B2
A42
Y17
Y18
Y19
Y21
Y23
Y25
Y27
HD_STBN3#
VCC
VCC
VCC
VCC
VCC
AA15
AA17
AA18
AA19
AA20
V_1P5_CORE
HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8#
HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63#
P41 M39 P42 M42 N41 M40 L40 M41 K42 G39 J41 G42 G40 G41 F40 F43 F37 E37 J35 D39 C41 B39 B40 H34 C37 J32 B35 J34 B34 F32 L32 J31 H31 M33 K31 M27 K29 F31 H29 F29 L27 M24 J26 K26 G26 H24 K24 F24 E31 A33 E40 D37 C39 D38 D33 C35 D34 C34 B31 C31 C32 D32 B30 D30
K40 A38 E29 B32
K41 L43
F35 G34
J27 M26
E34 B37
H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63
H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3
H_DSTBP#0 [3] H_DSTBN#0 [3]
H_DSTBP#1 [3] H_DSTBN#1 [3]
H_DSTBP#2 [3] H_DSTBN#2 [3]
H_DSTBP#3 [3] H_DSTBN#3 [3]
H_D#[0..63] [3]
H_DBI#[0..3] [3]
(INTEL-QG82945G-A2-LF)
HRCOMP HSCOMP HSWING
MCH_GTLREF
C10U10Y0805
C10U10Y0805
H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31
H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4
H_RS#0 H_RS#1 H_RS#2
H_A#[3..31][3]
D D
H_ADSTB#0[3] H_ADSTB#1[3]
C C
0D change Remove the HPCREQ# and HEDRDY#
B B
V_2P5_MCH
16.9R1%0603 R509
16.9ohm
H_REQ#[0..4][3]
H_DEFER#[3]
H_RS#[0..2][3]
CK_H_MCH#[13]
V_1P5_CORE
C13 C12
H_BR#0[3]
H_BPRI#[3]
H_BNR#[3]
H_LOCK#[3]
H_ADS#[3]
H_HIT#[3]
H_HITM#[3]
H_TRDY#[3] H_DBSY#[3] H_DRDY#[3]
CK_H_MCH[13]
PWR_GD[11,14,25]
H_CPURST#[3,19]
PLTRST#[10,13]
ICH_SYNC#[11]
R508 X_4.7KR
5 mils trace 8 mils space rout in
A A
8
same layer within 750 mils
V_FSB_VTT[3,4,8,12,25]
R507 60.4R1%0402
7
C16 X_C2.2P50N
HD_SWING VOLTAGE "20 MIL TRACE , 10MIL SPACE" HD_SWING S/B 0.22*VTT +/- 2%n
R503 301R1%0402
R504
84.5R1%0603
R502 62R0402
C14 C0.01U50X
PLACE DIVIDER RESISTOR NEAR VTT
6
5
HSWING MCH_GTLREFHSCOMP
0D Change R505 -->124R 0402 R506 -->210R 0402 R500 -->10R 0402 R501 -->0R 0402 R504 -->84.5R 0603 R509 -->16.9R 0603
GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V 124 OHM OVER 210 RESISTORS
V_FSB_VTTV_FSB_VTT
R505 124R1%0402
4
R501 0R0402
R506 210R1%0402
C15
R500 10R0402
C0.1U25Y
3
MCH_GTLREF_CPU [3]
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU Signals
(MS-7164)
2
631Tuesday, August 16, 2005
of
1
0D
8
7
6
5
4
3
2
1
M_CHA_DQ[0..63][20]
D D
~M_CHA_CS[0..1]
0,21]
~M_CHA_RAS[20,21] ~M_CHA_CAS[20,21]
~M_CHA_WE[20,21]
M_CHA_MA[0..13]
0,21]
C C
M_CHA_ODT[0..1]
0,21]
M_CHA_BA[0..2][20,21]
M_CHA_DQS0[20]
~M_CHA_DQS0[20]
M_CHA_DQS1[20]
~M_CHA_DQS1[20]
M_CHA_DQS2[20]
~M_CHA_DQS2[20]
M_CHA_DQS3[20]
~M_CHA_DQS3[20]
M_CHA_DQS4[20]
~M_CHA_DQS4[20]
M_CHA_DQS5[20]
~M_CHA_DQS5[20]
M_CHA_DQS6[20]
~M_CHA_DQS6[20]
M_CHA_DQS7[20]
~M_CHA_DQS7[20]
M_CHA_SCK0[20]
~M_CHA_SCK0[20]
B B
M_CHA_SCK1[20]
~M_CHA_SCK1[20]
M_CHA_SCK2[20]
~M_CHA_SCK2[20]
~M_CHA_CS0 ~M_CHA_CS1
~M_CHA_RAS ~M_CHA_CAS ~M_CHA_WE
M_CHA_MA0 M_CHA_MA1 M_CHA_MA2 M_CHA_MA3 M_CHA_MA4 M_CHA_MA5 M_CHA_MA6 M_CHA_MA7 M_CHA_MA8 M_CHA_MA9 M_CHA_MA10 M_CHA_MA11 M_CHA_MA12 M_CHA_MA13
M_CHA_ODT0 M_CHA_ODT1
M_CHA_BA0 M_CHA_BA1 M_CHA_BA2
M_CHA_DQS0 ~M_CHA_DQS0 M_CHA_DQS1 ~M_CHA_DQS1 M_CHA_DQS2 ~M_CHA_DQS2 M_CHA_DQS3 ~M_CHA_DQS3 M_CHA_DQS4 ~M_CHA_DQS4 M_CHA_DQS5 ~M_CHA_DQS5 M_CHA_DQS6 ~M_CHA_DQS6 M_CHA_DQS7 ~M_CHA_DQS7
M_CHA_SCK0 ~M_CHA_SCK0 M_CHA_SCK1
~M_CHA_SCK1 M_CHA_SCK2 ~M_CHA_SCK2
SM_RCOMP_P SM_RCOMP_N SMOCDCOMP1 SMOCDCOMP0
U2B
(INTEL-QG82945G-A2-LF)
BB37 BA39 BA35 AY38
BA34 BA37 BB35
BA32
AW32
BB30 BA30 AY30 BA27 BC28 AY27 AY28 BB27 AY33
AW27
BB26 BC38
AW37
AY39 AY37 BB40
BC33 AY34 BA26
AU4 AR2 BA3
BB4 AY11 BA10 AU18 AR18 AU35 AV35 AP42 AP40 AG42 AG41 AC42 AC41
BB32 AY32
AY5
BB5 AK42 AK41 BA31 BB31
AY6
BA5 AH40 AH43
AL5
AJ6
AJ8
AM3
SACS0# SACS1# SACS2# SACS3#
SARAS# SACAS# SAWE#
SAMA0 SAMA1 SAMA2 SAMA3 SAMA4 SAMA5 SAMA6 SAMA7 SAMA8 SAMA9 SAMA10 SAMA11 SAMA12 SAMA13
SAODT0 SAODT1 SAODT2 SAODT3
SABA0 SABA1 SABA2
SADQS0 SADQS0# SADQS1 SADQS1# SADQS2 SADQS2# SADQS3 SADQS3# SADQS4 SADQS4# SADQS5 SADQS5# SADQS6 SADQS6# SADQS7 SADQS7#
SACLK0 SACLK0# SACLK1 SACLK1# SACLK2 SACLK2# SACLK3 SACLK3# SACLK4 SACLK4# SACLK5 SACLK5#
MCH_SRCOMP0 MCH_SRCOMP1 SMOCDCOMP0 SMOCDCOMP1
M_CHA_DQ0
AP3
M_CHA_DQ3
M_CHA_DQ1
M_CHA_DQ5
M_CHA_DQ8
M_CHA_DQ2
M_CHA_DQ6
M_CHA_DQ4
M_CHA_DQ7
AP2
AU3
AV4
AN1
AP4
AU5
AU2
AW3
SADQ0
SADQ1
SADQ2
SADQ3
SADQ4
SADQ5
SADQ6
SADQ7
SBDQ0
SBDQ1
SBDQ2
SBDQ3
SBDQ4
SBDQ5
AL6
AL8
AP8
AP9
AJ11
AL9
AM10
M_CHA_DQ15
M_CHA_DQ12
M_CHA_DQ14
M_CHA_DQ16
M_CHA_DQ10
M_CHA_DQ9
AY3
BA7
SADQ8
SADQ9
SBDQ6
SBDQ7
AP6
AU7
M_CHA_DQ17
M_CHA_DQ13
M_CHA_DQ18
M_CHA_DQ11
BB7
AV1
SADQ10
SADQ11
SBDQ8
SBDQ9
AV6
AV12
M_CHA_DQ19
AW4
BC6
AY7
AW12
AY10
BA12
BB12
SADQ12
SADQ13
SADQ14
SADQ15
SADQ16
SADQ17
SADQ18
SBDQ10
SBDQ11
SBDQ12
SBDQ13
SBDQ14
SBDQ15
SBDQ16
AM11
AR5
AR7
AR12
AR10
AM15
AM13
M_CHA_DQ26
M_CHA_DQ20
M_CHA_DQ23
M_CHA_DQ22
M_CHA_DQ21
M_CHA_DQ24
M_CHA_DQ25
BA9
BB9
BC11
AY12
AM20
AM18
AV20
SADQ19
SADQ20
SADQ21
SADQ22
SADQ23
SADQ24
SADQ25
SBDQ17
SBDQ18
SBDQ19
SBDQ20
SBDQ21
SBDQ22
SBDQ23
AV15
AM17
AN12
AR13
AP15
AT15
AM24
M_CHA_DQ33
M_CHA_DQ31
M_CHA_DQ28
M_CHA_DQ29
M_CHA_DQ27
AM21
SADQ26
SBDQ24
AM23
M_CHA_DQ34
M_CHA_DQ30
M_CHA_DQ32
AP17
AR17
AP20
AT20
AP32
AV34
AV38
SADQ27
SADQ28
SADQ29
SADQ30
SADQ31
SADQ32
SADQ33
SADQ34
SBDQ25
SBDQ26
SBDQ27
SBDQ28
SBDQ29
SBDQ30
SBDQ31
SBDQ32
AV24
AM26
AP21
AR21
AP24
AT24
AU27
M_CHA_CKE[0..1][20,21]
M_CHA_DQ42
M_CHA_DQ40
M_CHA_DQ37
M_CHA_DQ36
M_CHA_DQ38
M_CHA_DQ35
AU39
AV32
AT32
AR34
SADQ35
SADQ36
SADQ37
SBDQ33
SBDQ34
SBDQ35
AN29
AR31
AM31
AP27
M_CHA_DQ45
M_CHA_DQ44
M_CHA_DQ39
M_CHA_DQ41
AU37
AR41
AR42
AN43
SADQ38
SADQ39
SADQ40
SADQ41
SBDQ36
SBDQ37
SBDQ38
SBDQ39
AR27
AP31
AU31
AP35
M_CHA_DQ49
M_CHA_DQ46
M_CHA_DQ47
M_CHA_DQ43
M_CHA_DQ48
AM40
AU41
AU42
AP41
AN40
AL41
AL42
SADQ42
SADQ43
SADQ44
SADQ45
SADQ46
SADQ47
SADQ48
SBDQ40
SBDQ41
SBDQ42
SBDQ43
SBDQ44
SBDQ45
SBDQ46
AP37
AN32
AL35
AR35
AU38
AM38
AM34
M_CHA_DM[0..7][20]
M_CHA_DM2
M_CHA_DM6
M_CHA_DM1
M_CHA_DM7
M_CHA_DM4
M_CHA_DM5
BA25
SACKE3
SBCKE1
AY16
BA13
M_CHA_DM0
AR3
SBCKE2
SBCKE3
BB13
M_CHA_DM3
AC40
AG40
AP39
AT34
AP18
BB10
AY2
SADM2
SADM1
SADM0
SBDM6
SBDM7
AJ39
AD39
SBCS0# SBCS1# SBCS2#
SADM7
SADM6
SADM5
SADM4
SADM3
SBCS3#
SBRAS# SBCAS#
SBWE#
SBMA0 SBMA1 SBMA2 SBMA3 SBMA4 SBMA5 SBMA6 SBMA7 SBMA8
SBMA9 SBMA10 SBMA11 SBMA12 SBMA13
SBODT0 SBODT1 SBODT2 SBODT3
SBBA0
SBBA1
SBBA2 SBDQS0
SBDQS0#
SBDQS1
SBDQS1#
SBDQS2
SBDQS2#
SBDQS3
SBDQS3#
SBDQS4
SBDQS4#
SBDQS5
SBDQS5#
SBDQS6
SBDQS6#
SBDQS7
SBDQS7#
SBCLK0
SBCLK0#
SBCLK1
SBCLK1#
SBCLK2
SBCLK2#
SBCLK3
SBCLK3#
SBCLK4
SBCLK4#
SBCLK5
SBCLK5#
SMVREF1 SMVREF0
SBDM0
SBDM1
SBDM2
SBDM3
SBDM4
SBDM5
AL11
AW7
AP13
AP23
AR29
AR38
~M_CHB_CS0
BA40
~M_CHB_CS1
AW41 BA41 AW40
~M_CHB_RAS
BA23
~M_CHB_CAS
AY24
~M_CHB_WE
BB23
M_CHB_MA0
BB22
M_CHB_MA1
BB21
M_CHB_MA2
BA21
M_CHB_MA3
AY21
M_CHB_MA4
BC20
M_CHB_MA5
AY19
M_CHB_MA6
AY20
M_CHB_MA7
BA18
M_CHB_MA8
BA19
M_CHB_MA9
BB18
M_CHB_MA10
BA22
M_CHB_MA11
BB17
M_CHB_MA12
BA17
M_CHB_MA13
AW42
M_CHB_ODT0
AY42
M_CHB_ODT1
AV40 AV43 AU40
M_CHB_BA0
AW23
M_CHB_BA1
AY23
M_CHB_BA2
AY17
M_CHB_DQS0
AM8
~M_CHB_DQS0
AM6
M_CHB_DQS1
AV7
~M_CHB_DQS1
AR9
M_CHB_DQS2
AV13
~M_CHB_DQS2
AT13
M_CHB_DQS3
AU23
~M_CHB_DQS3
AR23
M_CHB_DQS4
AT29
~M_CHB_DQS4
AV29
M_CHB_DQS5
AP36
~M_CHB_DQS5
AM35
M_CHB_DQS6
AG34
~M_CHB_DQS6
AG32
M_CHB_DQS7
AD36
~M_CHB_DQS7
AD38
M_CHB_SCK0
AM29
~M_CHB_SCK0
AM27
M_CHB_SCK1
AV9
~M_CHB_SCK1
AW9
M_CHB_SCK2
AL38
~M_CHB_SCK2
AL36 AP26 AR26 AU10 AT10 AJ38 AJ36
SM_VREF SM_VREF
AM2
SM_VREF
AM4
PLACE 0.1UF CAP CLOSE TO MCH
~M_CHB_RAS [20,21] ~M_CHB_CAS [20,21] ~M_CHB_WE [20,21]
~M_CHB_CS[0..1] [20,21]
M_CHB_MA[0..13] [20,21]
M_CHB_ODT[0..1] [20,21]
M_CHB_BA[0..2] [20,21]
M_CHB_DQS0 [20] ~M_CHB_DQS0 [20] M_CHB_DQS1 [20] ~M_CHB_DQS1 [20] M_CHB_DQS2 [20] ~M_CHB_DQS2 [20] M_CHB_DQS3 [20] ~M_CHB_DQS3 [20] M_CHB_DQS4 [20] ~M_CHB_DQS4 [20] M_CHB_DQS5 [20] ~M_CHB_DQS5 [20] M_CHB_DQS6 [20] ~M_CHB_DQS6 [20] M_CHB_DQS7 [20] ~M_CHB_DQS7 [20]
M_CHB_SCK0 [20] ~M_CHB_SCK0 [20] M_CHB_SCK1 [20] ~M_CHB_SCK1 [20] M_CHB_SCK2 [20] ~M_CHB_SCK2 [20]
C19 C0.1U25Y
M_CHA_DQ53
M_CHA_DQ58
M_CHA_DQ57
M_CHA_DQ55
M_CHA_DQ51
M_CHA_DQ50
M_CHA_DQ54
M_CHA_DQ59
M_CHA_DQ56
M_CHA_DQ52
AF39
AE40
AM41
AM42
AF41
AF42
AD40
AD43
AA39
AA40
SADQ49
SADQ50
SADQ51
SADQ52
SADQ53
SADQ54
SADQ55
SADQ56
SADQ57
SADQ58
SBDQ47
SBDQ48
SBDQ49
SBDQ50
SBDQ51
SBDQ52
SBDQ53
SBDQ54
SBDQ55
SBDQ56
AL34
AJ34
AF32
AF34
AL31
AJ32
AG35
AD32
AC32
AD34
M_CHA_CKE1
M_CHA_DQ63
M_CHA_CKE0
M_CHA_DQ60
M_CHA_DQ61
M_CHA_DQ62
AE42
AE41
AB41
AB42
BB25
AY25
BC24
SADQ59
SADQ60
SADQ61
SADQ62
SADQ63
SACKE0
SACKE1
SACKE2
SBDQ57
SBDQ58
SBDQ59
SBDQ60
SBDQ61
SBDQ62
SBDQ63
SBCKE0
Y32
AA32
AF35
AF37
AC33
AC35
BA14
U41
X1
MCH
X7 X8
Heatsink
X2
E31-0401730-K08
CPU STRAPPING RESISTORS
ALL COMPONENTS CLOSE TO CPU
R37
80.6R1%0402
C17
0D change
C0.1U25Y
Swap SM_RCOMP_P and SM_RCOMP_N
R41 80.6R1%0402
R38 40.2R1%0402
R42 40.2R1%0402
R40 1KR1%0402
SM_RCOMP_P
SM_RCOMP_N
SMOCDCOMP1
SMOCDCOMP0
R39 1KR1%0402
PLACE CLOSE TO MCH
C18 C0.1U25Y
V_SM
V_SM
M_CHB_DQ24
M_CHB_DQ20
M_CHB_DQ10
M_CHB_DQ14
M_CHB_DQ11
M_CHB_DQ13
M_CHB_DQ5
M_CHB_DQ4
M_CHB_DQ1
M_CHB_DQ2
M_CHB_DQ3
A A
8
M_CHB_DQ[0..63][20]
M_CHB_DQ0
7
M_CHB_DQ12
M_CHB_DQ9
M_CHB_DQ7
M_CHB_DQ8
M_CHB_DQ6
M_CHB_DQ21
M_CHB_DQ18
M_CHB_DQ15
M_CHB_DQ16
M_CHB_DQ23
M_CHB_DQ17
M_CHB_DQ25
M_CHB_DQ22
M_CHB_DQ19
6
M_CHB_DQ32
M_CHB_DQ28
M_CHB_DQ27
M_CHB_DQ26
M_CHB_DQ31
M_CHB_DQ29
M_CHB_DQ33
M_CHB_DQ30
M_CHB_DQ40
M_CHB_DQ34
M_CHB_DQ39
M_CHB_DQ38
M_CHB_DQ37
M_CHB_DQ35
M_CHB_DQ36
M_CHB_DQ46
M_CHB_DQ42
M_CHB_DQ44
M_CHB_DQ43
M_CHB_DQ41
5
M_CHB_DQ48
M_CHB_DQ47
M_CHB_DQ45
M_CHB_DQ55
M_CHB_DQ52
M_CHB_DQ53
M_CHB_DQ49
M_CHB_DQ50
M_CHB_CKE[0..1][20,21]
M_CHB_DQ57
M_CHB_DQ56
M_CHB_DQ51
M_CHB_DQ58
M_CHB_DQ54
M_CHB_DM[0..7][20]
M_CHB_CKE0
M_CHB_DQ61
M_CHB_DQ59
M_CHB_CKE1
M_CHB_DQ63
M_CHB_DQ60
M_CHB_DQ62
4
M_CHB_DM1
M_CHB_DM0
M_CHB_DM3
M_CHB_DM2
M_CHB_DM7
M_CHB_DM6
M_CHB_DM5
M_CHB_DM4
Title
Size Document Number Rev
3
Date: Sheet
MICRO-STAR INt'L CO., LTD .
Intel Lakeport - CPU Signals
(MS-7164)
2
731Tuesday, August 16, 2005
1
0D
of
8
D D
V_1P5_CORE
EXP_EN
State Description
C C
0D Add R847,R848 for SDVO function
B B
Only SDVO or PCI-e
LOW
operating SDVO and PCI-e
HIGH
operating simultaneously
SDVO_CTRL_DATA[17] SDVO_CTRL_CLK[17]
BSEL
2
1
0
0
0
0
1
V_2P5_MCH
V_2P5_MCH
V_2P5_MCH
0
00
1
0
SDVO_CTRL_DATA SDVO_CTRL_CLK
H_FSBSEL0[3,13] H_FSBSEL1[3,13]
H_FSBSEL2[3,13]
TABLE
PSB FREQUENCY
RESERVED
133 MHZ (533)
200 MHZ (800)
R840 0R0805
CK_PE_100M_MCH[13] CK_PE_100M_MCH#[13]
R847 X_4.7KR0402 R44 _220R0402-1 R45 _220R0402-1 R848 X_4.7KR0402
H_FSBSEL0 H_FSBSEL1 BSEL1
H_FSBSEL2
EXP_SLR (R46 and Normal high)
State Description
GMCH's PCI-E lane
LOW
Numbers are reversed(for BTX)
Normal operation(for ATX)HIGH
V_1P5_CORE
A A
V_1P5_CORE
8
7
V_1P5_CORE
+
C31 C36 C10U10Y0805 C44 C0.1U25Y
C57 X_C0.01U50X
EXP_A_RXP_13[17] EXP_A_RXN_13[17] EXP_A_RXP_14[17] EXP_A_RXN_14[17]
DMI_ITP_MRP_0[10] DMI_ITN_MRN_0[10] DMI_ITP_MRP_1[10] DMI_ITN_MRN_1[10] DMI_ITP_MRP_2[10] DMI_ITN_MRN_2[10] DMI_ITP_MRP_3[10] DMI_ITN_MRN_3[10]
R46 X_1KR0402
VCCADAC
C529 X_C10U10Y0805
R53 X_1KR0402 R54 1KR0402
7 8 5 6 3 4 1 2
8P4R-10KR0402
C30 C0.1U25Y
R841 0R0805
R843 0R0805
7
V_1P5_CORE
EC3 _CD470U10EL11-2
C10U10Y0805
C58 X_C0.1U25Y
EXP_A_RXP_13 EXP_A_RXN_13 EXP_A_RXP_14 EXP_A_RXN_14
DMI_ITP_MRP_0 DMI_ITN_MRN_0 DMI_ITP_MRP_1 DMI_ITN_MRN_1 DMI_ITP_MRP_2 DMI_ITN_MRN_2 DMI_ITP_MRP_3 DMI_ITN_MRN_3
CK_PE_100M_MCH CK_PE_100M_MCH#
RN7
V_2P5_MCH
C530 C0.1U25Y
(INTEL-QG82945G-A2-LF)
BSEL0 BSEL2
EXP_SLR
VCCA_HPLLVCCA_HPLL VCCA_MPLL VCCA_DPLLA VCCA_DPLLB VCCA_GPLL
V_FSB_VTT
C37 X_C0.22U16Y
U2C
G12
EXPARXP0
F12
EXPARXN0
D11
EXPARXP1
D12
EXPARXN1
J13
EXPARXP2
H13
EXPARXN2
E10
EXPARXP3
F10
EXPARXN3
J9
EXPARXP4
H10
EXPARXN4
F7
EXPARXP5
F9
EXPARXN5
C4
EXPARXP6
D3
EXPARXN6
G6
EXPARXP7
J6
EXPARXN7
K9
EXPARXP8
K8
EXPARXN8
F4
EXPARXP9
G4
EXPARXN9
M6
EXPARXP10 / SDVOC_INT+
M7
EXPARXN10 / SDVOC_INT-
K2
EXPARXP11
L1
EXPARXN11
U11
EXPARXP12
U10
EXPARXN12
R8
EXPARXP13 / SDVO_STALL+
R7
EXPARXN13 / SDVO_STALL-
P4
EXPARXP14 / SDVOB_INT+
N3
EXPARXN14 / SDVOB_INT-
Y10
EXPARXP15 / SDVO_TVCLKIN+
Y11
EXPARXN15 / SDVO_TVCLKIN+
F20
EXP_EN
Y7
DMI RXP0
Y8
DMI RXN0
AA9
DMI RXP1
AA10
DMI RXN1
AA6
DMI RXP2
AA7
DMI RXN2
AC9
DMI RXP3
AC8
DMI RXN3
B14
GCLKP
B16
GCLKN
F15
SDVOCTRLDATA
E15
SDVOCTRLCLK
F21
BSEL0
H21
BSEL1
L20
BSEL2
AK17
RSV_TP[0]
AL17
RSV_TP[1]
K21
EXP_SLR
AK23
RSV_TP[2]
AK18
RSV_TP[3]
L21
RSV_TP[4]
L18
RSV_TP[5]
N21
RSV_TP[6]
C21
VCCAHPLL
B20
VCCAMPLL
C19
VCCADPLLA
B19
VCCADPLLB
B17
VCCA_EXPPLL
D19
VCC2
C18
VCCADAC
B18
VCCADAC
A18
VSSA_DAC
C29
C28
C0.1U25Y
X_C0.1U25Y
C32 X_C10U10Y0805
C38 X_C10U10Y0805
I=45mA
VCCA_HPLL
I=60mA
VCCA_MPLL
6
V_1P5_CORE
AA26
AB17
AA24
VCC
VCC
VCC
VTT
VTT
B23
A24
C33 C0.1U25Y
C39 C0.1U25Y
6
AB18
AB19
AB20
AB24
VCC
VCC
VCC
VTT
VTT
VTT
B24
B25
B26
C23
V_FSB_VTT[3,4,6,12,25]
V_1P5_CORE
V_1P5_CORE
VCC
VTT
AB25
C25
AB26
VCC
VTT
C26
VCC
VTT
AB27
AC15
VCC
VTT
D24
D23
AC17
AC18
AC20
AC24
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
D25
E23
E24
E26
R842 0R0805
R844 0R0805
VCC
VTT
AC26
E27
AC27
VCC
VTT
F23
AD17
AD15
VCC
VCC
VTT
VTT
F27
G23
V_FSB_VTT
VCC
VTT
5
V_SM
AE20
AD23
AD25
AD26
AE17
AE18
AE22
AE24
AE26
AE27
VCC
VTT
AF15
VCC
VCC
VCC
VCC
VCC
VCC
VTT
VCC
VCC
P23
AF21
AF23
AF25
AD19
AD21
VCC
VCC
VCC
VCC
VCC
VTT
VTT
VTT
VTT
VTT
J23
K23
L23
M23
N23
H23
VCC
VCC
AF17
VCC
VCC
AF26
AY43
AF19
VCC
VCCSM
VCC
VCC
VCC
AF27
AF29
AG15
V_1P5_CORE
AV18
VCCSM
VCC
AG17
AV21
VCCSM
VCC
AG18
AV23
VCCSM
VCC
AG19
I=55mA
VCCA_DPLLA
C34
X_C10U10Y0805
VCCA_DPLLB
C40
X_C10U10Y0805
5
I=55mA
C35 C0.1U25Y
C41 C0.1U25Y
V_1P5_CORE
ANALOG FILTERS
V_1P5_CORE
AV31
VCCSM
VCC
AG20
AV42
AW13
VCCSM
VCC
AG21
AG22
AW20
AW15
VCCSM
VCCSM
VCC
VCC
AG23
AG24
AW21
VCCSM
VCCSM
VCC
VCC
AJ15
4
AW24
VCCSM
VCC
AJ17
4
AY41
AW29
AW34
AW35
AW31
VCCSM
VCCSM
VCCSM
VCCSM
VCC
VCC
AJ18
AJ20
R51 1R1% R52 1R1%
L21
0R1210
BB16
BB20
BB24
BB28
VCCSM
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
AE4
AE3
AE2
C521
C10U10Y0805
BB33
BB38
BB42
BC13
VCCSM
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AD12
AD10
AD8
AD6
I=45mA
VCCA_GPLL
C42
X_C10U10Y0805
Ver 0C
BC26
BC31
BC18
BC22
VCCSM
VCCSM
VCCSM
VCCSM
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AD5
AD4
AD2
AD1
VCC_EXP
C522
C10U10Y0805
3
VCC_EXP
BC35
N5
BC40
VCCSM
VCCSM
VCCSM
VCC_EXP
SDVOB_ALPHA+ / SDVOC_R+ / EXPATXP11
SDVOB_ALPHA- / SDVOC_R- / EXPATXN11
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
AC13
AC6
AC5
AA13
AA5
C43 C0.1U25Y
C523
C10U10Y0805
N10N9N7
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
Y13
V13V9V10V7V6
3
VCC_EXP
VCC_EXP
N11
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
R11
R10R5N12
VCC_EXP
VCC_EXP
VCC_EXP
SDVOC_CLK+ / EXPATXP8 SDVOC_CLK+ / EXPATXN8
SDVOC_B+ / EXPATXP9
SDVOC_B- / EXPATXN9 SDVOC_G+ / EXPATXP10 SDVOC_G- / EXPATXN10
SDVOB_CLK+ / EXPATXP12 SDVOB_CLK- / EXPATXN12
SDVOB_B+ / EXPATXP13
SDVOB_B- / EXPATXN13 SDVOB_G+ / EXPATXP14 SDVOB_G- / EXPATXN14 SDVOB_R+ / EXPATXP15
SDVOB_R- / EXPATXN15
VCC_EXP
VCC_EXP
VCC_EXP
V5
VCC_EXP
VCC_EXP
VCC_EXP
VCC_EXP
U13U8U7U6R13
VCC_EXP
VCC_EXP
EXPATXP0 EXPATXN0 EXPATXP1 EXPATXN1 EXPATXP2 EXPATXN2 EXPATXP3 EXPATXN3 EXPATXP4 EXPATXN4 EXPATXP5 EXPATXN5 EXPATXP6 EXPATXN6 EXPATXP7 EXPATXN7
DMI TXP0 DMI TXN0 DMI TXP1 DMI TXN1 DMI TXP2 DMI TXN2 DMI TXP3 DMI TXN3
EXP_COMPO
EXP_COMPI
HSYNC VSYNC
GREEN
GREENB
DDC_DATA
DDC_CLK
DREFCLKINP DREFCLKINN
EXTTS#
XORTEST
ALLZTEST
2
V_SM
C20 C10U10Y0805 C22 C10U10Y0805 C24 C10U10Y0805 C26 C10U10Y0805
V_SM
C21 C10U10Y0805 C23 C10U10Y0805 C25 X_C10U10Y0805 C27 X_C10U10Y0805
R43 24.9R1%
CRT_HSYNC CRT_VSYNC
CRT_R CRT_G CRT_B
R48 255R1% R49 10KR
EXP_A_TXP_12 [17] EXP_A_TXN_12 [17] EXP_A_TXP_13 [17] EXP_A_TXN_13 [17] EXP_A_TXP_14 [17] EXP_A_TXN_14 [17] EXP_A_TXP_15 [17] EXP_A_TXN_15 [17]
DMI_MTP_IRP_0 [10] DMI_MTN_IRN_0 [10] DMI_MTP_IRP_1 [10] DMI_MTN_IRN_1 [10] DMI_MTP_IRP_2 [10] DMI_MTN_IRN_2 [10] DMI_MTP_IRP_3 [10] DMI_MTN_IRN_3 [10]
V_1P5_CORE
CRT_HSYNC [15] CRT_VSYNC [15]
CRT_R [15] CRT_G [15] CRT_B [15]
3VDDCDA [15] 3VDDCCL [15]
DOT_96M [13]
-DOT_96M [13]
V_2P5_MCH
TESTIN# [19]
RED BLUE RED#
BLUE#
IREF
D14 C13 A13 B12 A11 B10 C10 C9 A9 B7 D7 D6 A6 B5 E2 F1 G2 J1 J3 K4 L4 M4 M2 N1 P2 T1 T4 U4 U2 V1 V3 W4
W2 Y1 AA2 AB1 Y4 AA4 AB3 AC4
AC12 AC11
D17 C17
F17 K17 H18
G17 J17 J18
N18 N20
J15 H15
A20 J20 H20 K18
EXP_A_TXP_12 EXP_A_TXN_12 EXP_A_TXP_13 EXP_A_TXN_13 EXP_A_TXP_14 EXP_A_TXN_14 EXP_A_TXP_15 EXP_A_TXN_15
DMI_MTP_IRP_0 DMI_MTN_IRN_0 DMI_MTP_IRP_1 DMI_MTN_IRN_1 DMI_MTP_IRP_2 DMI_MTN_IRN_2 DMI_MTP_IRP_3 DMI_MTN_IRN_3
GRCOMP
3VDDCDA 3VDDCCL
DOT_96M
-DOT_96M
EXTTS
MICRO-STAR INt'L CO., LTD.
Title
Intel Lakeport - CPU Signals
Size Document Number Rev
Date: Sheet
2
(MS-7164)
1
DMI Differential impedance 100ohm +-20%
GROMP trace 20mils
831Wednesday, August 17, 2005
of
1
0D
8
7
6
5
4
3
2
1
(INTEL-QG82945G-A2-LF)
D D
C C
B B
U2D
G10 G13 G15 G18 G20 G21 G24 G27 G29 G31 G32 G35 G38 H12 H17 H26 H27 H32
A16 A22 A26 A31 A35
B11 B13 B21 B22 B28 B33 B38
C12 C14 C22 C40
D10 D16 D20 D21
E12 E13 E17 E18 E20 E21 E32
F13 F18 F26 F34 F42
J10
AL37
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS VSS VSS VSS VSS
B4
VSS
B6
VSS
B9
VSS VSS VSS VSS VSS VSS VSS VSS
C3
VSS
C5
VSS
C7
VSS VSS VSS VSS VSS
D2
VSS
D5
VSS VSS VSS VSS VSS
E3
VSS
E4
VSS
E7
VSS
E9
VSS VSS VSS VSS VSS VSS VSS VSS
F2
VSS
F6
VSS VSS VSS VSS VSS VSS
G3
VSS
G5
VSS
G7
VSS
G9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
J2
VSS
J5
VSS
J7
VSS VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J12
J21
J24
J43
J38
J29
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K20
K15
K13
K12
K10K7K6K5K3
K34
K32
K27
VSS
VSS
AP5
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L29
L26
L24
L13
L12L2K39
K37
VSS
VSS
VSS
VSS
VSS
L31
L42
VSS
VSS
VSS
VSS
VSS
VSS
M35
M21
M20
M13
M10M9M8M5M3
VSS
VSS
VSS
VSS
VSS
M37
N24
N15
N13N8N6
N2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
N36
N33
N31
N29
N27
N26
VSS
VSS
VSS
VSS
VSS
VSS
P24
P15
P14P3N43
N39
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R9R6P30
P29
P27
P26
R12
R14
R30
R31
R34
R37
R39T2T42U3U5U9U12
U14
U31
U33
U36
U38V2V8
V11
V12
V14
V34
V36
V37
V38
V39
V43W3Y2Y5Y6Y9Y12
Y14
Y31
Y35
Y37
Y39
VSS
VSS
AF20
AF22
AF24
AY1
BC4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AL33
VSS
AL32
VSS
AL27
VSS
AL24
VSS
AL23
VSS
AL21
VSS
AL18
VSS
AL15
VSS
AL13
VSS
AL12
VSS
AL10
VSS
AL7
VSS
AL3
VSS
AL2
VSS
AL1
VSS
AK30
VSS
AK29
VSS
AK26
VSS
AK24
VSS
AJ37
VSS
AJ35
VSS
AJ33
VSS
AJ31
VSS
AJ30
VSS
AJ10
VSS
AJ7
VSS
AH42
VSS
AG39
VSS
AG38
VSS
AG37
VSS
AG36
VSS
AG33
VSS
AG31
VSS
AG30
VSS
AF43
VSS
AF38
VSS
AF36
VSS
AF33
VSS
AF5
VSS
AF3
VSS
AF2
VSS
AF1
VSS
AD42
VSS
AD37
VSS
AD35
VSS
AD33
VSS
AD13
VSS
AD11
VSS
AD9
VSS
AD7
VSS
AC39
VSS
AC38
VSS
AC37
VSS
AC36
VSS
AC31
VSS
AC23
VSS
AC21
VSS
AC14
VSS
AC10
VSS
AC7
VSS
AC3
VSS
AC2
VSS
AB43
VSS
AB2
VSS
AA36
VSS
AA33
VSS
AA31
VSS
AA23
VSS
AA21
VSS
AA14
VSS
AA12
VSS
AA11
VSS
VSS
VSS
VSS
VSS
AA8
VSS
VSS
AF18
AE21
AE23
AE25
L17
VSS
VSS
Y42
AA3
AE19
AD29
AD27
AD24
AD22
AD20
AD18
AC29
AC25
AC19
AA29
AA27
AA25
Y29
Y26
Y24
Y22
Y20
W25
W23
W21
V29
V26
V24
U29
R29
R26
D43D1A40A4BC9
BB41
BB39
BB34
BB19
BB14
BB11
BB6
BB3
BA42
BA4
AW10
AV37
AV17
AV10
AV2
AU34
AU32
AU29
AU26
AU24
AU21
AU20
AU17
AU15
AU13
AU12
AU9
AU6
AT31
AT27
AT26
AT23
AT21
AT18
AT17
AT12
AR43
AR39
AR37
AR32
AR24
AR20
AR15
AR6
AR1
AP38
AP34
AP29
AP12
AP10
AP7
AN42
AN31
AN27
AN26
AN24
AN23
AN21
AN20
AN18
AN17
AN15
AN13
AN4
AN2
AM39
AM37
AM36
AM33
AM9
AM7
AM5
AL43
A A
MSI
Title
Size Document Number Rev
8
7
6
5
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Lakeport - CPU Signals
(MS-7164)
2
931Tuesday, August 16, 2005
0D
of
1
8
D D
C C
ICH_PCLK[13]
PCIRST_ICH7#[25]
B B
TP1Testing Point TP2Testing Point
VCC3_SB
SPI_MOSI[18]
A A
SPI_MISO[18] SPI_CS#[18]
SPI_CLK[18] SPI_ARB[18]
8
7
AD[0..31][17]
C_BE#[0..3][17]
DEVSEL#[17]
FRAME#[17]
TRDY#[17]
STOP#[17] LOCK#[17]
SERR#[17] PERR#[17]
PCI_PME#[17]
PREQ#0[17] PREQ#1[17] PREQ#2[17] PREQ#3[17] PREQ#4[17] PREQ#5[17]
PGNT#1[17] PGNT#2[17]
R838 X_10KR0402 R839 X_10KR0402
PIRQ#A[17] PIRQ#B[17] PIRQ#C[17] PIRQ#D[17] PIRQ#E[17] PIRQ#F[17] PIRQ#G[17] PIRQ#H[17]
SERIRQ[14] IDE_IRQ[22]
R540 X_10KR R541 X_10KR R542 X_10KR
SPI_MOSI
R543 X_0R0402
SPI_MISO
R544 X_0R0402 R545 X_0R0402
SPI_CS# SPI_CLK
R546 X_0R0402
SPI_ARB
7
6
U3A (INTEL-NH82801GB-A1-LF)
AD0
E18 C18 A16 F18 E16 A18 E17 A17 A15 C14 E14 D14 B12 C13 G15 G13 E12 C11 D11 A11 A10 F11 F10
B15 C12 D12 C15
A12 F16
F14 F15 E10 E11 B10
B19
B18
C16 C17 E13 A13
D16 D17 F13 A14
AH21 AH16
E9 D9 B9 A8 A6 C7 B6 E6 D6
A7
C9
A9
D7
C8
E7
D8 A3
B4 C5 B5 G8 F7 F8 G7
P5 P2 P6 R2 P1
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE0# C/BE1# C/BE2# C/BE3#
DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PLOCK# SERR# PERR# PME#
PCICLK PCIRST#
REQ0# REQ1# REQ2# REQ3# GPIO22/REQ4# GPIO1/REQ5#
GNT0# GNT1# GNT2# GNT3# GPIO48/GNT4# GPIO17/GNT5#
PIRQA# PIRQB# PIRQC# PIRQD# GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH#
SERIRQ IDEIRQ
SPI_MOSI SPI_MISO SPI_CS# SPI_CLK SPI_ARB
VSS_0
VSS_1
VSS_2
A4
A23B1B8
6
PCI INTERFACE INTERRUPT
PART 1/3
SPI
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
B11
B14
B17
B20
B26
B28C2C6
D10
D13
AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE#0 C_BE#1 C_BE#2 C_BE#3
IRDY#[17]
PAR[17]
PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5
PGNT#1 PGNT#2
GPIO48 GPIO17
5
ICH 7
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
D18
D21
D24E1E2E8E15F3F4F5F12
5
4
AH28
A20M#
AG27
CPUSLP#
AG26
FERR#
AG22
IGNNE#
AF22
INIT#
AG21
INIT3_3V#
AF25
INTR
AH24
NMI
AF23
SMI#
AH22
STPCLK#
AG23
RCIN#
AE22
CPULAN PCI EXPRESSDIRECT MEDIA
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
F27
F28G1G2G5G6G9G14
G18
G21
A20GATE
THRMTRIP#
GPO49/CPUPWRGD
PLTRST#
PERN_1
PERP_1 PETN_1 PETP_1
PERN_2 PERP_2 PETN_2
PETP_2
PERN_3 PERP_3 PETN_3
PETP_3
PERN_4 PERP_4 PETN_4
PETP_4
PERN_5 PERP_5 PETN_5
PETP_5
PERN_6 PERP_6 PETN_6
PETP_6
DMI_0RXN DMI_0RXP DMI_0TXN
DMI_0TXP
DMI_1RXN DMI_1RXP DMI_1TXN
DMI_1TXP
DMI_2RXN DMI_2RXP DMI_2TXN
DMI_2TXP
DMI_3RXN DMI_3RXP DMI_3TXN
DMI_3TXP
DMI_CLKN DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
LAN_CLK
LAN_RSTSYNC
LAN_RXD0 LAN_RXD1 LAN_RXD2
LAN_TXD0 LAN_TXD1 LAN_TXD2
EE_DIN
EE_DOUT
EE_SHCLK
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
G24
G25
G26H3H4
H5
4
EE_CS
AF26 AG24
C26 F26
F25 E28
ICHPETP_1 ICH_PETP_1
E27 H26
H25
ICHPETN_2
G28
ICHPETP_2
G27 K26
K25 J28 J27
M26 M25 L28 L27
P26 P25 N28 N27
T25 T24 R28 R27
V26 V25 U28 U27
Y26 Y25 W28 W27
AB26 AB25 AA28 AA27
AD25 AD24 AC28 AC27
AE28 AE27
DMI_BIAS
C25 D25
PLACE THE RESISTOR WHIN 5MILS
V3 U3 U5 V4 T5
U7 V6 V7
W1 W3 Y2 Y1
3
R548 22R0402
C471 C0.1U16X C472 C0.1U16X
C473 C0.1U16X C474 C0.1U16X
R547 24.9R1%
3
2
H_A20M# [3] H_FERR# [3,4]
H_IGNNE# [3] H_INIT# [3] FWH_INIT# [13] H_INTR [3] H_NMI [3] ICH_H_SMI# [3,14] H_STPCLK# [3] KBRST# [14] A20GATE [14] TRMTRIP# [3,4,14] H_PWRGD [3,19]
ICH_PERN_1 ICH_PERP_1 ICH_PETN_1ICHPETN_1
ICH_PERN_2 ICH_PERP_2 ICH_PETN_2 ICH_PETP_2
DMI_MTN_IRN_0 [8] DMI_MTP_IRP_0 [8] DMI_ITN_MRN_0 [8] DMI_ITP_MRP_0 [8]
DMI_MTN_IRN_1 [8] DMI_MTP_IRP_1 [8] DMI_ITN_MRN_1 [8] DMI_ITP_MRP_1 [8]
DMI_MTN_IRN_2 [8] DMI_MTP_IRP_2 [8] DMI_ITN_MRN_2 [8] DMI_ITP_MRP_2 [8]
DMI_MTN_IRN_3 [8] DMI_MTP_IRP_3 [8] DMI_ITN_MRN_3 [8] DMI_ITP_MRP_3 [8]
CK_PE_100M_ICH# [13] CK_PE_100M_ICH [13]
V_1P5_CORE
MSI
Title
Size Document Number Rev
Date: Sheet
PLTRST# [6,13] ICH_PERN_1 [17]
ICH_PERP_1 [17] ICH_PETN_1 [17] ICH_PETP_1 [17]
ICH_PERN_2 [18] ICH_PERP_2 [18] ICH_PETN_2 [18] ICH_PETP_2 [18]
VCC3
CB1 X_C0.1U25Y CB2 X_C0.1U25Y CB3 X_C0.1U25Y CB4 C0.1U25Y
PLACE 1 EACH NEAR A3 & F1
PLACE REMAINDER ANUWHERE
DMI Differential impedance 100ohm +-20%
U26
XX1
XX1
MICRO-STAR INt'L CO., LTD .
Intel ICH7 - PCI & DMI & CPU & I RQ
(MS-7164)
2
XX2
XX2
1
XX3
XX3
E31-0401760-K08
of
10 31Tuesday, August 16, 2005
1
XX4
XX4
0D
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