MSI MS-7157 Schematics
8
7
6
5
4
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1
Cover Sheet 1
Block Diagram
2
MS(7157)
Version
0A
GPIO
D D
Voltage Distribution
CLK MAP
History
Intel µPGA478B CPU Signals
Intel µPGA478B CPU Power
Intel Springdale - Host Signals
Intel Springdale - Memory Signals
C C
Intel Springdale - AGP
DDR DIMM 1,2
PCB Holes
ICH5(1)
ICH5(2)
Clock & FWH & FDD
LPC I/O -W83627THF
AC97 Audio
B B
AGP 4X/8X Slot & FAN
PCI Slots 1 & 2
PCI Slots 3 & 4
ATA33/66/100 IDE & Video Connectors
USB Connectors
ACPI controller
ATX & Front Panel
VRM
A A
EMI parts
Broadcom 4401
8
7
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Intel (R) 848 (GMCH) + ICH5 Chipset
P4 Socket 478 Northwood/Prescott
CPU:
P4 Socket 478 Northwood/Prescott
System Chipset:
Intel 848 - GMCH (North Bridge)
Intel ICH5 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM
ADI 1888
LPC Super I/O -- W83627THF
LAN --Broadcom 4401
CLOCK --Realtek
363-213
Main Memory:
DDR * 2 (Max 2GB)
Expansion Slots:
PCI SLOT * 4
PWM:
Controller:
RT8800B
23
24
25
26
27
28
29BOM PART
6
5
4
3
Title
Size Document Number Re v
Date: Sheet
MICRO-STAR INt'L CO., LTD.
MSI
COVER SHEET
MS-7157
2
129Monday, March 07, 2005
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Block Diagram
RT880B
2-Phase PWM
D D
AGP 1.5V
Connector
P4 Socket 478 Northwood/Prescott
4X/8X
Springdale
FSB
64bit DDR
Channel 1
2 DDR
RTL8100C/8110S
DIMM
Modules
HUB
Link
C C
IDE Primary
IDE Secondary
UltraDMA 33/66/ 100
ICH5
PCI CNTRL
PCI ADDR/DATA
PCI Slot 1
PCI Slot 2
PCI Slot 3
PCI Slot 4
USB Port 0
USB Port 1
USB Port 2
USB
LPC Bus
USB Port 3
USB Port 4
SATA
LPC SIO
B B
USB Port 5
Winbond
83627THF
USB Port 6
USB Port 7
AC'97 Codec
AC'97 Link
Flash
Keyboard Parallel Serial
Floopy
Mouse
A A
MSI
Title
Size Document Number Re v
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Date: Sheet
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
MS-7157
2
229Monday, March 07, 2005
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ICH5
FunctionTypeGPIO Pin
GPIO 0
GPIO 1
GPIO 2
GPIO 3
D D
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
C C
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23
PREQ#B
I
PREQ#B
I
PIRQ#E
I
PIRQ#F
I
PIRQ#G
I
PIRQ#H
I
GPI6
I
GPI7
I
CSA_PME#
I
OC4#
I
OC5#
I
SIO_SMI#
I
EXTSMI#
I
SIO_PME#
I
IOC#6
OC#7
I
PGNT#A
O
PGNT#B
O
OGPO18
BIOS_WP#
O
GPO20
O
OGPO21
OD
O
GPO23
GPIO 24 I/O GPIO24
GPIO 25 I/O
GPIO 27
*
GPIO 28
GPIO 32
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48
B B
GPIO 49
LAN_DISABLE#
GPIO27
I/O
I/O GPIO28
I/O
GPIO32
I/O
GPIO33
I/O
GPIO34
I
GPI41
I
OPGNT#4
OD
CPUPWRGD
Power well
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
default output
default output
default output
default output
default output
default output
default output
PCI Config.
DEVICE
PCI Slot 2
PCI Slot 3 PCI_REQ#2
PCI Slot 5
INTA#
INTB#
PCI_REQ#0PCI Slot 1
PCI_GNT#0
INTC#
INTD#
INTB#
INTC#
PCI_REQ#1 AD17 PCICLK1
PCI_GNT#1
INTD#
INTA#
INTC#
INTD#
PCI_GNT#2
INTA#
INTB#
INTD#
PCI_REQ#3PCI Slot 4 AD19
INTA# PCI_GNT#3
INTB#
INTC#
INTB#
INTC#
PCI_REQ#4 AD21 PCICLK4
PCI_GNT#4
INTD#
INTA#
DDR DIMM Config.
DEVICE
DIMM 1 MCLK_A0/MCLK_A0#
DIMM 2
1010000B
1010001B
CLOCKADDRESS
MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#
IDSEL
AD16
AD18
CLOCKREQ#/GNT#
PCICLK0
PCICLK2
PCICLK3
CLK GEN PIN OUTMCP1 INT Pin
13 (PCI_CLK0)
14 (PCI_CLK1)
15 (PCI_CLK2)
16 (PCI_CLK3)
19 (PCI_CLK4)
FWH
Function
GPI 0
GPI 1
*
GPI 3
*
TypeGPIO Pin
PD_DET
I
I
SD_DET
Pull down thr ou gh 1K ohms (unused)GPI 2
I
Pull down thr ou gh 1K ohms (unused)
I
I
Pull down thr ou gh 1K ohms (unused)GPI 4
PCI RESET DEVICE
Signals
PCIRST#1
HD_RST#
Springdale,LAN,FWH, Super I/O
PCI slot 1-3, AGP slotPCIRST#2
Primary, Sco n dary IDE
Target
A A
Title
Size Document Number Re v
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Date: Sheet
MICRO-STAR INt'L CO., LTD.
MSI
General Purpose Spec
MS-7157
2
329Monday, March 07, 2005
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Power Delivery Map
ATX P/S
5VSB
+/-5%
D D
3.3V Standby
regulator
5V 3.3V 12V -12V
+/-5% +/-5% +/-5% +/-10%
2.5V regulator
VID voltage
regulator
VRM 10/0
VCC_AGP
1.5V regulator
with 1A Stby curre n t
Processor
VCCVID
1.2V
30mA
VccCORE/Vtt
1.15V-1.75V
80A
BG GMCH
VCC
1.5V
Vcc_AGP
1.5V
Vcca_AGP
1.5V
Vtt
1.15V-1.75V
2.5V Standby
regulator
Memory
C C
5V regulator
AC97
5V
1.25V regulator
3.3V
Vdd/Vddq
2.5V
7A
Vtt
1.25V
2.1A
VccDDR
2.5V
Vcc_DAC
3.3V
ICH5
Vcc1_5
1.5V
V5REF_SUS
5V
85mA
V_CPU_IO
1.15V-1.75V
45mA
Vcc3_3
B B
3.3V
610mA
Vccsus3_3
3.3V
70mA
CK-408
Vcc
3.3V
LPC Super I/O
5V
3.3V
FWH
A A
8
7
6
PCI Slot (per slot)
-12V 3.3Vaux
12V
3.3V
5V
5
AGP Slot
5V 2.0A
3.3V
6.0A
12V
1.0A
3.3Vaux
0.375A
1.5V
2.0A
3.3V
3.3Vaux
4
LAN
USB
5V
5VSB
Vdd
3.3V
67mA
MSI
Title
Size Document Number Rev
3
Date: Sheet
MICRO-STAR INT'L CO.,LTD.
Power Delivery Map
MS-7154
2
0A
429Monday, March 07, 2005
of
1
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CLK MAP
7
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1
478
D D
REALTEK
CLOCK
GENERATOR
HCLK
MCHCLK
ICH66MHz
SATACLK
USB 48MHz
ICH 14.318MHz
SIOPCLK
SIO48MHz
FWHPCLK
Springdale
ICH5
Winbond
LPC I/O
FWH
C C
PCI1
PCICLK[0:3]
PCI2
PCI3
PCI4
ACCLK14.318MHz
AC97
LAN_CLK33MHz
LANCLK
B B
A A
MSI
Title
Size Document Number Re v
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Date: Sheet
2
MICRO-STAR INT'L CO.,LTD.
CLK MAP
MS-7154
529Monday, March 07, 2005
of
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1
93/06/29
1.Create MS7097 ver:0A circuit.
D D
93/08/26
1.Add R213 for PICCLK6 enable.
2.Modified VRM circuit.
3.Swap LAN LED TX_RX and LINK100 signal.
4.Modified HDD LED pull up to VCC5.
6.Change USB2 and USB3 to JUSB1 and JUSB2.
7.Modified VRM choke to 40A.
8.Add 1.1A polyfuse on front USB.
9.Remove RN21.
10.Swap CPU and system fan on super IO pin out.
11.Modified Audio quality issue.
93/10/05
C C
Page23
Page23,29
Page25
Page 16
1.Reserved S3 remove circuit.
2.Add USB power select jumper.
3.Add two DIP high side mos in VRM.
4.USE GP30 SIO pin92 to strapping S3 en/disable.
93/10/20
Page22
Page22
Page25
1.Change common choke footprint.
2.Reserved protection diode for USB ports.
3.Change VRM choke footprint.
B B
A A
MSI
Title
Size Document Number Re v
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Date: Sheet
MICRO-STAR INt'L CO., LTD.
HISTORY
MS-7157
2
629Monday, March 07, 2005
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VCCP
CPU SIGNAL BLOCK
D D
HDBI#[0..3]9
FERR#15
STPCLK#15
HDBI#0
HDBI#1
HDBI#2
HDBI#3
HINIT#15,16
HDBSY#9
HDRDY#9
C C
B B
HTRDY#9
HADS#9
HLOCK#9
HBNR#9
HIT#9
HITM#9
HBPRI#9
HDEFER#9
CPU_TMPA17
VTIN_GND17
TRMTRIP#15
H_PROCHOT#9
IGNNE#15
SMI#15
A20M#15
SLP#15
Near CPU
C25 X_C0.1U25Y
R458 0R
BOOTSELECT
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
OPTIMIZED
H_FSBSEL0
H_FSBSEL1
H_PWRGD15
H_CPURST#9
HD#[0..63]9
A A
8
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
HA#[3..31]9
U5A
E21
DBI0#
G25
DBI1#
P26
DBI2#
V21
DBI3#
AC3
IERR#
V6
MCERR#
B6
FERR#
Y4
STPCLK#
AA3
BINIT#
W5
INIT#
AB2
RSP#
H5
DBSY#
H2
DRDY#
J6
TRDY#
G1
ADS#
G4
LOCK#
G2
BNR#
F3
HIT#
E3
HITM#
D2
BPRI#
E2
DEFER#
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
D4
TCK
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AF26
GND/SKTOCC#
C3
PROCHOT#
B2
IGNNE#
B5
SMI#
C6
A20M#
AB26
SLP#
A22
RESERVED0
A7
RESERVED1
AE21
RESERVED2
AF24
RESERVED3
AF25
RESERVED4
AD1
BOOTSELECT
AE26
OPTIMIZED/COMPAT#
AD6
BSEL0
AD5
BSEL1
AB23
PWRGOOD
AB25
RESET#
AA24
D63#
AA22
D62#
AA25
D61#
Y21
D60#
Y24
D59#
Y23
D58#
W25
D57#
Y26
D56#
W26
D55#
V24
D54#
7
HA#25
HA#31
HA#30
HA#29
HA#22
HA#27
HA#28
HA#26
HA#19
HA#20
HA#21
HA#24
HA#23
AB1
A35#
A34#Y1A33#W2A32#V3A31#U4A30#T5A29#W1A28#R6A27#V2A26#T4A25#U3A24#P6A23#U1A22#T2A21#R3A20#P4A19#P3A18#R2A17#T1A16#N5A15#N4A14#N2A13#M1A12#N1A11#M4A10#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
T23
T22
T25
V22
V25
U21
HD#52
HD#53
HD#51
T26
U23
U24
U26
HD#49
HD#50
HD#48
P24
R24
R25
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
P21
R21
N25
N26
N23
M26
M24
HD#40
HD#35
HD#36
HD#37
HD#38
HD#39
HD#34
6
HA#6
HA#5
HA#7
HA#8
HA#9
A9#L2A8#M6A7#L3A6#K1A5#L6A4#K4A3#
D25#
D24#
D23#
D22#
D21#
L21
F26
F24
E25
D26
HD#24
HD#20
HD#21
HD#22
HD#23
HA#4
D20#
HD#19
HA#3
AE25
K2
DBR#
D19#
D18#
D17#
D16#
D15#
F23
E24
H22
D25
G23
HD#16
HD#17
HD#18
HD#15
HA#18
HA#10
HA#11
HA#14
HA#17
HA#13
HA#15
HA#16
HA#12
M3
D33#
D32#
D31#
D30#
D29#
D28#
D27#
D26#
J24
L22
K23
N22
H25
H24
M23
HD#32
HD#33
G26
M21
HD#31
HD#29
HD#30
HD#26
HD#27
HD#28
HD#25
R45 X_1KR R455
CPUVID_GD
VID5
VID1
VID2
VID3
VID0
VID4
AE1
AE2
AE3
AE4
AE5
AD3
AD2
AD26
AC26
A4
A5
VID4#
VID3#
VID2#
VID1#
VID0#
VID5#
VCC_SENSE
D14#
D13#
J21
D23
C26
HD#12
HD#13
HD#14
5
ITP_CLK1
ITP_CLK0
VSS_SENSE
D12#
D11#
D10#
D9#
B25
H21
C24
G22
HD#8
HD#9
HD#10
HD#11
VIDPWRGD
D8#
D7#
C23
HD#7
HD#6
GTLREF3
GTLREF2
GTLREF1
GTLREF0
TESTHI12
TESTHI11
TESTHI10
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D6#
D5#
D4#
D3#
D2#
D1#
D0#
B24
A25
A23
B22
B21
D22
C21
HD#2
HD#3
HD#4
HD#5
HD#0
HD#1
CPUVID_GD 26
VID[0..5] 26
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
SOCK478-DIP
ICH_RST# 15
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
HRS#2
HRS#1
HRS#0
H_COMP1
H_COMP0
4
C410 C220P16V3X7RL
GTLREF1
HREQ#[0..4] 9
RN6 8P4R-62R
1 2
3 4
5 6
7 8
R64 62R
R85 62R
R48 62R
CPU_CLK# 16
CPU_CLK 16
HRS#[0..2] 9
R50 61.9R1%
R97 61.9R1%
HADSTB#1 9
HADSTB#0 9
HDSTBP#3 9
HDSTBP#2 9
HDSTBP#1 9
HDSTBP#0 9
HDSTBN#3 9
HDSTBN#2 9
HDSTBN#1 9
HDSTBN#0 9
NMI 15
INTR 15
X1
X2
CPU Retention
GTLREF1 9
CPU1
VCCP
GTLREF1
2/3*Vccp
C409
C1U10Y
49.9R1%
R456
100R1%
X3
X4
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
RN21
1
3
5
7
X_8P4R-470R
H_FSBSEL1
2
4
6
H_FSBSEL0
8
H_FSBSEL1 16
H_FSBSEL0 16
VCCP
H_BR#0 9
H_TDI
H_TRST#
R457 150R3
R42 680R3
VCCP
H_TMS
H_TDO
H_TCK
R44 39R3
R459 75R
R43 27R3
VCCP
H_PROCHOT#
H_PWRGD
H_BR#0
H_CPURST#
TRMTRIP#
FERR#
VCCP
MSI
Title
Size Document Number Re v
3
Date: Sheet
2
R30 62R
R464 300R3
R68 220R
R56 62R
R55 62R
R52 62R
RN86
7 8
5 6
3 4
1 2
8P4R-51R3
H_BPM#3
H_BPM#1
H_BPM#4
H_BPM#2
H_BPM#0
H_BPM#5
MICRO-STAR INt'L CO., LTD.
Intel µPGA478B - Signals
MS-7157
729Monday, March 07, 2005
1
0A
of
8
CPU VOLTAGE BLOCK
D D
VCCP
A10
A12
A14
A16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
AD10
VCC
VSS
AD12
VCC
VSS
AD14
VCC
VSS
AD16
A18
VCC
VSS
AD18
U5B
D10
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
C C
B B
AA17
AA19
AA23
AA26
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AA4
AA7
AA9
AB3
AB6
AB8
A20
VCC
VSS
AD21
VCCA8VCC
VSS
AD23
AA10
VSS
AD4
AA12
VCC
VSS
AD8
AA14
VCC
VSS
AE11
AA16
AE13
VCC
VSS
7
AA18
VCC
VSS
AE15
AA8
VCC
VSS
AE17
AB11
VCC
VSS
AE19
AB13
VCC
VSS
AE22
AB15
VCC
VSS
AE24
AB17
VCC
VSS
AE7
AB19
VCC
VSS
AE9
6
5
VID Voltage is from 1.14V to 1.32V .
It is derived from 3.3V.
It should be able to source 150mA.
It drives th e power logic of BSEL[1:0] and VID[5:0].
VID to VIDGD delay time is from 1ms to 10ms.
VID to VIDGD deassertion time is 1ms for max.
4
V_FSB_VTT
1.2V 150mA
3
2
1
C411 X_C0.1U25Y
C412 C1U10Y
Near processor
CPU_IOPLL
It support DC current if 100mA.
L10 X_L4D 7UHD1AD9R6
VCCP
L11 L4D7UHD1AD9R6
DC voltage drop should
C415
X_C1U10Y
VSSA
The ESL is less than 5nH, and the ESR is less than 0.3ohm.
AD22
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24
C414
X_C1U10Y
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
C10
C12
C14
C16
C18
C20
D11
D13
D15
D17
D19
E10
E12
E14
E16
E18
E20
F11
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCB7VCCB9VCC
VCC
VCC
VCC
VCC
VCC
VCCC8VCC
VCC
VCC
VCC
VCC
VCCD7VCCD9VCC
VCC
VCC
VCC
VCC
VCC
VCCE8VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSB4VSSB8VSS
VSS
VSS
VSS
VSSC2VSS
VSS
VSS
VSSC5VSSC7VSSC9VSS
VSS
VSS
VSS
VSS
VSS
VSSD3VSS
VSSD6VSSD8VSSE1VSS
VSS
VSS
VSS
VSS
VSS
VSSE7VSSE9VSS
VSS
VSS
VSS
VSS
VSSF2VSS
VSS
VSSE4VSS
F10
B10
B12
B14
B16
B18
B23
B20
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B26
C11
C13
C15
C17
C19
C22
C25
D12
D14
D16
D18
D20
E11
E13
E15
E17
D21
D24
E19
F12
E23
E26
VSSF5VSSF8VSS
F14
F16
F18
F22
F25
G21
F13
F15
VCC
VCC
VSSG3VSSH1VSS
G24
AF4
F17
F19
F9
AD20
VCC
VCC
VCC
VSSG6VSS
VSS
H23
H26
VCC-VID
VCC-VIDPRG
VSSH4VSSJ2VSS
J22
VSS
J25
VCCA
VSSA
VCC-IOPLL
VSSJ5VSS
SOCK478-DIP
K21
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AF3
AE23
be less than 70mV.
C416
C10U6D3V6Y5VL
C413
X_C10U10Y0805
CPU DECOUPLING CAPACITORS
VCCP VCCP
C417 X_C10U6D3V6Y5VL
C418 C10U6D3V6Y5VL
C424 X_C10U6D3V6Y5VLC422 X_C10U6D3V6Y5VL C423 C10U6D3V6Y5VL
C426 X_C10U6D3V6Y5VL
C430 X_C10U6D3V6Y5VL
C431 C10U6D3V6Y5VL
C428 C10U6D3V6Y5VL
C432 C10U6D3V6Y5VL
C433 X_C10U6D3V6Y5VL
C434 X_C10U6D3V6Y5VL
C435 X_C10U6D3V6Y5VL
A A
Place these caps within north side of processor
8
7
6
Place these caps within socket cavity
5
4
VCCPVCCP
C421 X_C10U10Y0805C420 C10U6D3V6Y5VL
C425 X_C10U10Y0805
C429 X_C10U10Y0805C427 X_C10U6D3V6Y5VL
Place these caps within south side of processor
3
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Re v
Date: Sheet
2
06 Intel µP GA 478B - Power
MS-7157
829Monday, March 07, 2005
1
of
0A
8
HA#[3..31]7
D D
HADSTB#07
HADSTB#17
H_BR#07
C C
HBPRI#7
HBNR#7
HLOCK#7
HADS#7
HREQ#[0..4]7
HIT#7
HITM#7
HDEFER#7
HTRDY#7
HDBSY#7
HDRDY#7
HRS#[0..2]7
MCH_CLK16
MCH_CLK#16
MS5_POK15
H_CPURST#7
B B
PCIRST#117,24,28
ICH_SYNC#
H_PROCHOT#7
R106 20R1%
0.63*Vccp
BSEL0_SPG
BSEL1_SPG
GTLREF1
BSEL0_SPG16
BSEL1_SPG16
GTLREF17
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
HRCOMP
HSWING
VCCA_FSB
D26
D30
L23
E29
B32
K23
C30
C31
J25
B31
E30
B33
J24
F25
D34
C32
F28
C34
J27
G27
F29
E28
H27
K24
E32
F31
G30
J26
G26
B30
D28
B24
B26
B28
E25
F27
B29
J23
L22
C29
J21
K21
E23
L21
D24
E27
G24
G22
C27
B27
B7
C7
AE14
E8
AK4
AJ8
L20
L13
L12
E24
C25
F23
C116
C0.1U25Y
C113 C0.1U25Y
VCCA_DPLL
U6A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
BREQ0#
BPRI#
BNR#
HLOCK#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HIT#
HITM#
DEFER#
HTRDY#
DBSY#
DRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
CPURST#
RSTIN#
ICH_SYNC#
PROCHOT#
BSEL0
BSEL1
HDRCOMP
HDSWING
HDVREF
7
VCC_AGP
B3
A31
B4
VCCJ6VCCJ7VCCJ8VCCJ9VCCK6VCCK7VCCK8VCCK9VCCL6VCCL7VCCL9VCC
VCCA_FSB
VCCA_FSB
VCCA_DPLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C8
C10
VSS
C12
C14
C16
C18
C20
C22
C24
6
N11
P10
P11
R11
T16
T17
T18
T19
U16
U17
U20
V16
V18
V20
W16
N10
M10
M11
M9
L10
L11
VCC
VCCN9VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VSS
VSS
VSSD1VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D9
C26
C28
D11
D13
D15
D17
D19
VSS
D21
D23
D25
D27
D29
D31
D33
VCC
VCC
VCC
VCC
VCC
VSS
VSSF3VSSF5VSSF8VSS
VSSE3VSSF1VSS
VSSE1VSS
D35
VCC
T20
VCC
VCC
F10
W19
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
F18
F20
F22
F24
F14
F16
F12
VCC
VSS
W20
F26
VCC
VSS
5
Y16
VCC
VSS
G28
A33NCA35NCB2NCB25NCB34NCC1NCC23NCC35NCE26NCM31NCAF13NCAF23NCAJ12NCAN1NCAP2NCAR3NCAR33NCAR35
Y17
Y18
Y19
Y20
NCA3NC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSH8VSS
H2
H5
H9
H12
H14
H16
G31
G35
H18
R25
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J10
J12
J14
H20
H22
H24
J16
H26
H30
H33
4
VCCP
A11
A13
A16
A20
A23
A25
A27
A29
A32
C4
VSSA7VSSA9VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J18
J20
J22
J28
J32
J35
K11
K12
K14
K16
K18
K20
K22
VTTD5VTTD6VTTD7VTTE6VTTE7VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L24
L25
L26
L35
L31
K33
K25
K27
K29
F7
VSSM3VSSM6VSS
M26
M27
3
C6
VTTA4VTTA5VTTA6VTTB5VTTB6VTTC5VTT
VSS
VSS
VSS
VSS
VSSN1VSS
RG82865PE-A2
<Priority>
N4
M28
M30
M33
VTT_FSB1
VTT_FSB2
A15
A21
HD0#
HD1#
HD2#
HD3#
VTT_FSB
VTT_FSB
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
C128 C0.47U16Y
C123 C0.47U16Y
HD#0
B23
HD#1
E22
HD#2
B21
HD#3
D20
HD#4
B22
HD#5
D22
HD#6
B20
HD#7
C21
HD#8
E18
HD#9
E20
HD#10
B16
HD#11
D16
HD#12
B18
HD#13
B17
HD#14
E16
HD#15
D18
HD#16
G20
HD#17
F17
HD#18
E19
HD#19
F19
HD#20
J17
HD#21
L18
HD#22
G16
HD#23
G18
HD#24
F21
HD#25
F15
HD#26
E15
HD#27
E21
HD#28
J19
HD#29
G14
HD#30
E17
HD#31
K17
HD#32
J15
HD#33
L16
HD#34
J13
HD#35
F13
HD#36
F11
HD#37
E13
HD#38
K15
HD#39
G12
HD#40
G10
HD#41
L15
HD#42
E11
HD#43
K13
HD#44
J11
HD#45
H10
HD#46
G8
HD#47
E9
HD#48
B13
HD#49
E14
HD#50
B14
HD#51
B12
HD#52
B15
HD#53
D14
HD#54
C13
HD#55
B11
HD#56
D10
HD#57
C11
HD#58
E10
HD#59
B10
HD#60
C9
HD#61
B9
HD#62
D8
HD#63
B8
HDBI#0
C17
HDBI#1
L17
HDBI#2
L14
HDBI#3
C15
B19
C19
L19
K19
G9
F9
D12
E12
2
HD#[0..63] 7
HDBI#[0..3] 7
HDSTBP#0 7
HDSTBN#0 7
HDSTBP#1 7
HDSTBN#1 7
HDSTBP#2 7
HDSTBN#2 7
HDSTBP#3 7
HDSTBN#3 7
VCCP
C136
C0.1U25Y
1
VCC3
I=30mA
I=35mA
C145
X_C0.1U25Y
6
VCCA_FSB
C144
C0.1U25Y
ESR is 0.1mohm to GMCH
VCCA_DPLL
CP19
VCCP
A A
HSWING
C115
C10000P50Y5
8
R121
1/4*Vccp
300R1%
R103
100R
7
X_
CP8
R130 X_220R
X_
VCC_AGP
VCC_AGP
ICH_SYNC#
MSI
Title
Size Document Number Re v
5
4
3
Date: Sheet
2
R178
X_220R
MICRO-STAR INt'L CO., LTD.
Intel Springdale - CPU Signals
MS-7157
929Monday, March 07, 2005
of
1
0A
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