MSI MS-7156 Schematics

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Cover Sheet 1
Block Diagram
GPIO

D D

History
Intel PGA478B CPU - Signals
Intel PGA478B CPU - Power

2
3
4
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6

MS(7156)

Intel (R) 865P (GMCH) + ICH5 Chipset
P4 Socket 478 Northwood/Prescott

CPU:

P4 Socket 478 Northwood/Prescott

Version
0A

Intel Springdale - Host Signals
Intel Springdale - Memory Signals
Intel Springdale - AGP
DDR DIMM 1,2
PCB Holes

C C

ICH5(1)
ICH5(2)
Clock & FWH & FDD
LPC I/O -W83627THF
AC97 Audio
AGP 4X/8X Slot & FAN
PCI Slots 1 & 2

B B

PCI Slots 3 & 4
ATA33/66/100 IDE & Video Connectors
USB Connectors
ACPI controller
ATX & Front Panel

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

System Chipset:

Intel 865P - GMCH (North Bridge)
Intel ICH5 (South Bridge)

On Board Chipset:

BIOS -- FWH EEPROM
ADI 1888
LPC Super I/O -- W83627THF
LAN --Broadcom 4401
CLOCK --Realtek
363-213

Main Memory:

DDR * 2 (Max 2GB)

Expansion Slots:

PCI SLOT * 4

PWM:

Controller:
RT8800B

VRM

24
25EMI parts
26Broadcom 4401

A A

LAN Connector 27

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MICRO-STAR INt'L CO., LTD.

MSI

COVER SHEET

MS-7156

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RT880B
2-Phase PWM

D D

AGP 1.5V
Connector

C C

IDE Primary

UltraDMA 33/66/100

IDE Secondary

P4 Socket 478 Northwood/Prescott

FSB

4X/8X

Springdale

HUB Link

ICH5

64bit DDR
Channel 1

64bit DDR
Channel 2

2 DDR
DIMM
Modules

PCI CNTRL

PCI ADDR/DATA

PCI Slot 2

PCI Slot 1

Block Diagram

RTL8100C/8110S

PCI Slot 3

PCI Slot 4

USB Port 0

USB Port 1

USB Port 2

USB

LPC Bus

USB Port 3

USB Port 4

SATA

LPC SIO

USB Port 5

Winbond
83627THF

B B

USB Port 6

USB Port 7

AC'97 Link

AC'97 Codec

Flash

Keyboard

Floopy Parallel Serial

Mouse

A A

MSI

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MICRO-STAR INt'L CO., LTD.

BLOCK DIAGRAM

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ICH5

FunctionTypeGPIO Pin

GPIO 0
GPIO 1
GPIO 2

D D

GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17

C C

GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23

I

PREQ#B

I

PREQ#B

I

PIRQ#E
PIRQ#F

I

PIRQ#G

I

PIRQ#H

I

GPI6

I

GPI7

I
I

CSA_PME#

I

OC4#

I

OC5#

I

SIO_SMI#

I

EXTSMI#

I

SIO_PME#

I OC#6

OC#7

I

PGNT#A

O
O

PGNT#B

O GPO18

BIOS_WP#

O
O

GPO20
O GPO21
OD
O

GPO23

GPIO 24 I/O GPIO24
GPIO 25 I/O
GPIO 27
GPIO 28

*

GPIO 32
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48

B B

GPIO 49

LAN_DISABLE#

I/O

GPIO27
I/O GPIO28

GPIO32

I/O

GPIO33

I/O

GPIO34

I/O
I
I

GPI41
O PGNT#4

CPUPWRGD

OD

Power well

MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN

default output
default output
default output
default output
default output
default output
default output

PCI Config.

DEVICE

PCI Slot 2

PCI Slot 3 PCI_REQ#2

PCI Slot 5

INTA#
INTB#

PCI_REQ#0PCI Slot 1

PCI_GNT#0
INTC#
INTD#
INTB#
INTC#

PCI_REQ#1 AD17 PCICLK1

PCI_GNT#1
INTD#
INTA#
INTC#
INTD#

PCI_GNT#2
INTA#
INTB#
INTD#

PCI_REQ#3PCI Slot 4 AD19
INTA# PCI_GNT#3
INTB#
INTC#
INTB#
INTC#

PCI_REQ#4 AD21 PCICLK4

PCI_GNT#4
INTD#
INTA#

DDR DIMM Config.

DEVICE

DIMM 1 MCLK_A0/MCLK_A0#

DIMM 2

1010000B

1010001B

CLOCKADDRESS

MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#

IDSEL

AD16

AD18

CLOCKREQ#/GNT#

PCICLK0

PCICLK2

PCICLK3

CLK GEN PIN OUTMCP1 INT Pin

13 (PCI_CLK0)

14 (PCI_CLK1)

15 (PCI_CLK2)

16 (PCI_CLK3)

19 (PCI_CLK4)

FWH

Function

TypeGPIO Pin

PD_DET

GPI 0
GPI 1

*

GPI 3

*

I
I

SD_DET
Pull down through 1K ohms (unused)GPI 2

I
I

Pull down through 1K ohms (unused)
Pull down through 1K ohms (unused)GPI 4

I

PCI RESET DEVICE

Signals

PCIRST#1

HD_RST#

Springdale,LAN,FWH, Super I/O
PCI slot 1-3, AGP slotPCIRST#2
Primary, Scondary IDE

Target

A A

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MICRO-STAR INt'L CO., LTD.

General Purpose Spec

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93/06/29

1.Create MS7097 ver:0A circuit.

93/08/26

D D

1.Add R213 for PICCLK6 enable.

2.Modified VRM circuit.

3.Swap LAN LED TX_RX and LINK100 signal.

4.Modified HDD LED pull up to VCC5.

6.Change USB2 and USB3 to JUSB1 and JUSB2.

7.Modified VRM choke to 40A.

8.Add 1.1A polyfuse on front USB.

9.Remove RN21.

10.Swap CPU and system fan on super IO pin out.

11.Modified Audio quality issue.

93/10/05

Page23

Page23,29

C C

Page25
Page 16

1.Reserved S3 remove circuit.

2.Add USB power select jumper.

3.Add two DIP high side mos in VRM.

4.USE GP30 SIO pin92 to strapping S3 en/disable.

93/10/20

Page22
Page22
Page25

1.Change common choke footprint.

2.Reserved protection diode for USB ports.

3.Change VRM choke footprint.

B B

A A

MSI

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MICRO-STAR INt'L CO., LTD.

HISTORY

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VCCP

CPU SIGNAL BLOCK

D D

HDBI#[0..3]7

FERR#13

STPCLK#13

HDBI#0
HDBI#1
HDBI#2
HDBI#3

HINIT#13,14

HDBSY#7

HDRDY#7

C C

B B

HTRDY#7

HADS#7

HLOCK#7

HBNR#7

HIT#7

HITM#7

HBPRI#7

HDEFER#7

CPU_TMPA15
VTIN_GND15

TRMTRIP#13

H_PROCHOT#7

IGNNE#13

SMI#13

A20M#13

SLP#13

Near CPU

C25 X_CD1U25V3Y5VL

R458 0R

BOOTSELECT

H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK

OPTIMIZED
H_FSBSEL0

H_FSBSEL1

H_PWRGD13

H_CPURST#7

HD#[0..63]7

A A

8

HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54

HA#[3..31]7

U5A

E21

DBI0#

G25

DBI1#

P26

DBI2#

V21

DBI3#

AC3

IERR#

V6

MCERR#

B6

FERR#

Y4

STPCLK#

AA3

BINIT#

W5

INIT#

AB2

RSP#

H5

DBSY#

H2

DRDY#

J6

TRDY#

G1

ADS#

G4

LOCK#

G2

BNR#

F3

HIT#

E3

HITM#

D2

BPRI#

E2

DEFER#

C1

TDI

D5

TDO

F7

TMS

E6

TRST#

D4

TCK

B3

THERMDA

C4

THERMDC

A2

THERMTRIP#

AF26

GND/SKTOCC#

C3

PROCHOT#

B2

IGNNE#

B5

SMI#

C6

A20M#

AB26

SLP#

A22

RESERVED0

A7

RESERVED1

AE21

RESERVED2

AF24

RESERVED3

AF25

RESERVED4

AD1

BOOTSELECT

AE26

OPTIMIZED/COMPAT#

AD6

BSEL0

AD5

BSEL1

AB23

PWRGOOD

AB25

RESET#

AA24

D63#

AA22

D62#

AA25

D61#

Y21

D60#

Y24

D59#

Y23

D58#

W25

D57#

Y26

D56#

W26

D55#

V24

D54#

7

HA#25

HA#31

HA#30

HA#29

HA#27

HA#28

HA#26

HA#24

HA#23

HA#22

HA#21

HA#19

HA#20

AB1

A35#

A34#Y1A33#W2A32#V3A31#U4A30#T5A29#W1A28#R6A27#V2A26#T4A25#U3A24#P6A23#U1A22#T2A21#R3A20#P4A19#P3A18#R2A17#T1A16#N5A15#N4A14#N2A13#M1A12#N1A11#M4A10#

D53#

D52#

D51#

D50#

D49#

D48#

D47#

D46#

D45#

D44#

D43#

D42#

D41#

D40#

D39#

D38#

D37#

D36#

D35#

D34#

T23

T22

T25

U23

HD#49

HD#50

U24

U26

HD#47

HD#48

HD#45

HD#46

T26

HD#43

HD#44

R24

R25

HD#41

HD#42

P24

R21

HD#40

HD#39

N25

N26

HD#37

HD#38

M26

N23

HD#35

HD#36

M24

P21

HD#34

6

V22

HD#52

HD#53

U21

V25

HD#51

HA#17

HA#18

D33#

N22

HD#32

HD#33

M23

HA#16

D32#

H25

HD#31

HA#15

D31#

K23

HD#30

HA#14

D30#

J24

HD#29

HA#13

D29#

L22

HD#28

HA#12

D28#

M21

HD#27

HA#11

D27#

H24

HD#26

HA#7

HA#10

HA#8

HA#9

M3

A9#L2A8#M6A7#L3A6#K1A5#L6A4#K4A3#

D26#

D25#

D24#

D23#

L21

F26

D26

G26

HD#24

HD#25

HD#22

HD#23

HA#6

D22#

E25

HD#21

HA#5

D21#

F24

HD#20

HA#4

D20#

F23

HD#19

HA#3

K2

D19#

G23

HD#18

D18#

E24

HD#17

D17#

H22

HD#16

AE25

D16#

D25

HD#15

DBR#

D15#

R45 X_1KR R455

CPUVID_GD

VID5

VID1

VID2

VID3

VID0

VID4

AD2

AE1

AE2

AE3

AE4

AE5

AD3

A4

A5

AD26

AC26

VID4#

VID3#

VID2#

VID1#

VID0#

VID5#

VCC_SENSE

D14#

D13#

J21

D23

C26

HD#12

HD#13

HD#14

5

ITP_CLK1

ITP_CLK0

VSS_SENSE

D12#

D11#

D10#

D9#

B25

H21

C24

G22

HD#8

HD#9

HD#10

HD#11

VIDPWRGD

D8#

D7#

C23

HD#7

HD#6

GTLREF3
GTLREF2
GTLREF1
GTLREF0

TESTHI12
TESTHI11
TESTHI10

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

LINT1/NMI

LINT0/INTR

D6#

D5#

D4#

D3#

D2#

D1#

D0#

B24

A25

A23

B22

B21

D22

C21

HD#2

HD#3

HD#4

HD#5

HD#0

HD#1

CPUVID_GD 24

VID[0..5] 24

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1#
BCLK0#

RS2#
RS1#
RS0#

AP1#
AP0#
BR0#

COMP1
COMP0

DP3#
DP2#
DP1#
DP0#

SOCK478-DIP

ICH_RST# 13

AA21
AA6
F20
F6

AB4
AA5
Y6
AC4
AB5
AC6

H3
J3
J4
K5
J1

AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24

AF23
AF22

F4
G5
F1

V5
AC1
H6

P1
L24

L25
K26
K25
J26

R5
L5
W23
P23
J23
F21
W22
R22
K22
E22

E5
D1

H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8

H_TESTHI2_7
H_TESTHI1

HRS#2
HRS#1
HRS#0

H_COMP1
H_COMP0

4

C410 C220P16V3X7RL

GTLREF1

HREQ#[0..4] 7

RN6 8P4R-62R

1 2
3 4
5 6
7 8

R64 62R

R85 62R
R48 62R

CPU_CLK# 14
CPU_CLK 14

HRS#[0..2] 7

R50 61.9R1%
R97 61.9R1%

HADSTB#1 7
HADSTB#0 7
HDSTBP#3 7
HDSTBP#2 7
HDSTBP#1 7
HDSTBP#0 7
HDSTBN#3 7
HDSTBN#2 7
HDSTBN#1 7
HDSTBN#0 7

NMI 13
INTR 13

X1
X2

CPU Retention

GTLREF1 7

CPU1

VCCP

GTLREF1

2/3*Vccp

C409
C1U10V3Y5VL

49D9R3F

R456
100R3F

X3

X4

FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED

V_FSB_VTT

RN21

1
3
5
7

X_8P4R-470R

H_FSBSEL1

2
4
6

H_FSBSEL0

8

H_FSBSEL1 14

H_FSBSEL0 14

VCCP

H_BR#0 7

H_TDI
H_TRST#

R457 150R3
R42 680R3

VCCP

H_TMS
H_TDO

H_TCK

R44 39R3
R459 75R3

R43 27R3

VCCP

H_PROCHOT#
H_PWRGD
H_BR#0
H_CPURST#
TRMTRIP#
FERR#

VCCP

MSI

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Date: Sheet

2

R30 62R3
R464 300R3
R68 220R
R56 62R3
R55 62R3
R52 62R3

RN86

7 8
5 6
3 4
1 2

8P4R-51R3

H_BPM#3
H_BPM#1
H_BPM#4
H_BPM#2
H_BPM#0
H_BPM#5

MICRO-STAR INt'L CO., LTD.

Intel PGA478B - Signals

MS-7156

530Thursday, June 09, 2005

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CPU VOLTAGE BLOCK

D D

VCCP

A10

A12

A14

A16

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VCC

VSS

AD10

VCC

VSS

AD12

VCC

VSS

AD14

VCC

VSS

AD16

A18

VCC

VSS

AD18

U5B

D10
A11
A13
A15
A17
A19
A21
A24
A26

A3
A9

AA1
AA11
AA13
AA15

C C

B B

AA17
AA19
AA23
AA26

AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24

AC11
AC13
AC15
AC17
AC19

AC22
AC25

AA4

AA7

AA9

AB3

AB6

AB8

AC2

AC5

AC7

AC9

A20

VCC

VSS

AD21

VCCA8VCC

VSS

AD23

AA10

VSS

AD4

AA12

VCC

VSS

AD8

AA14

VCC

VSS

AE11

AA16

VCC

VSS

AE13

7

AA18

VCC

VSS

AE15

AA8

VCC

VSS

AE17

AB11

VCC

VSS

AE19

AB13

VCC

VSS

AE22

AB15

VCC

VSS

AE24

AB17

VCC

VSS

AE7

AB19

VCC

VSS

AE9

6

AB7

AB9

AC10

AC12

AC14

AC16

AC18

AC8

AD11

AD13

AD15

AD17

AD19

AD7

AD9

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AE8

AF11

AF13

AF15

AF17

AF19

AF2

AF21

AF5

AF7

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSB4VSSB8VSS

VSS

VSS

VSS

VSSC2VSS

VSS

VSS

VSSC5VSSC7VSSC9VSS

B10

B12

B14

B16

B18

B23

B20

AF1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

AF8

B26

C11

C13

C15

C17

C19

C22

C25

D12

D14

VCC

VSS

5

VID Voltage is from 1.14V to 1.32V.
It is derived from 3.3V.
It should be able to source 150mA.
It drives the power logic of BSEL[1:0] and VID[5:0].
VID to VIDGD delay time is from 1ms to 10ms.
VID to VIDGD deassertion time is 1ms for max.

AF9

B11

B13

B15

B17

B19

C10

C12

C14

C16

C18

C20

D11

D13

D15

D17

D19

VCC

VCC

VCC

VCC

VCC

VCC

VCCB7VCCB9VCC

VCC

VCC

VCC

VCC

VCC

VCCC8VCC

VCC

VCC

VCC

VCC

VCCD7VCCD9VCC

VSS

VSS

VSS

VSS

VSSD3VSS

VSSD6VSSD8VSSE1VSS

VSS

VSS

VSS

VSS

VSS

VSSE7VSSE9VSS

VSS

VSS

VSSE4VSS

F10

F12

E11

E13

E15

E17

E19

D16

D18

D20

D21

D24

E23

F14

E26

4

V_FSB_VTT

1.2V 150mA

C411 X_CD1U25V3Y5VL
C412 C1U10V3Y5VL

Near processor

E10

E12

E14

E16

E18

E20

F11

F13

F15

F17

F19

VCC

VCC

VCC

VCC

VCC

VCCE8VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSSF2VSS

VSS

VSSF5VSSF8VSS

VSSG6VSS

VSSG3VSSH1VSS

F16

F18

F22

F25

G21

G24

AD20

F9

AF4

AF3

AE23

VCC

VSS

H23

H26

VCC-VID

VCC-VIDPRG

VSSH4VSSJ2VSS

J22

VCC-IOPLL

VSS

VSSJ5VSS

J25

VCCA

VSSA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SOCK478-DIP

K21

AD22

Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24

3

C414
X_C1U10V3Y5VL

2

It support DC current if 100mA.

CPU_IOPLL

C415
X_C1U10V3Y5VL

VSSA

The ESL is less than 5nH, and the ESR is less than 0.3ohm.

L10 X_L4D7UHD1AD9R6
L11 L4D7UHD1AD9R6

DC voltage drop should

be less than 70mV.

C416
C10U6D3V6Y5VL

VCCP

C413
X_C10U10V5Y5VL

1

CPU DECOUPLING CAPACITORS

VCCP VCCP

C417 X_C10U6D3V6Y5VL

C426 C10U6D3V6Y5VL
C430 C10U6D3V6Y5VL
C433 C10U6D3V6Y5VL
C434 X_C10U6D3V6Y5VL
C435 X_C10U6D3V6Y5VL

A A

Place these caps within north side of processor

8

7

C418 X_C10U6D3V6Y5VL
C423 X_C10U6D3V6Y5VL
C427 C10U6D3V6Y5VL
C431 X_C10U6D3V6Y5VL

6

VCCP VCCPVCCP

+

C419 X_CSP100U2V C420 X_C10U6D3V6Y5VL

Place these caps within socket cavity

5

C424 C10U6D3V6Y5VLC422 C10U6D3V6Y5VL
C428 X_C10U6D3V6Y5VL
C432 X_C10U6D3V6Y5VL

C421 X_C10U10V5Y5VL
C425 X_C10U10V5Y5VL
C429 X_C10U10V5Y5VL

Place these caps within south side of processor

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

4

3

Date: Sheet

2

06 Intel PGA478B - Power

MS-7156

630Thursday, June 09, 2005

1

0A

of

8

HA#[3..31]5

D D

HADSTB#05
HADSTB#15

H_BR#05

C C

HBPRI#5

HBNR#5

HLOCK#5

HADS#5

HREQ#[0..4]5

HIT#5

HITM#5

HDEFER#5

HTRDY#5
HDBSY#5

HDRDY#5

HRS#[0..2]5

MCH_CLK14

MCH_CLK#14

MS5_POK13
H_CPURST#5

B B

PCIRST#115,22,26

ICH_SYNC#

H_PROCHOT#5

R106 20R1%

0.63*Vccp

BSEL0_SPG
BSEL1_SPG

GTLREF1

BSEL0_SPG14
BSEL1_SPG14

GTLREF15

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HRS#0
HRS#1
HRS#2

HRCOMP
HSWING

VCCA_FSB

D26
D30

L23
E29
B32
K23
C30
C31

J25
B31
E30
B33

J24
F25
D34
C32
F28
C34

J27
G27
F29
E28
H27
K24
E32
F31
G30

J26
G26

B30
D28

B24
B26

B28
E25
F27
B29

J23

L22
C29

J21
K21

E23

L21
D24

E27
G24

G22
C27
B27

B7
C7

AE14

E8

AK4
AJ8

L20

L13

L12
E24
C25
F23

C116
C0.1U25Y

C113 C0.1U25Y

VCCA_DPLL

U6A

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HAD_STB0#
HAD_STB1#

BREQ0#
BPRI#

BNR#
HLOCK#
ADS#
HREQ0#

HREQ1#
HREQ2#
HREQ3#
HREQ4#

HIT#
HITM#
DEFER#

HTRDY#
DBSY#
DRDY#

RS0#
RS1#
RS2#

HCLKP
HCLKN

PWROK
CPURST#

RSTIN#
ICH_SYNC#

PROCHOT#

BSEL0
BSEL1

HDRCOMP
HDSWING
HDVREF

7

VCC_AGP

A31

B4

B3

VCCJ6VCCJ7VCCJ8VCCJ9VCCK6VCCK7VCCK8VCCK9VCCL6VCCL7VCCL9VCC

VCCA_FSB

VCCA_FSB

VCCA_DPLL

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

C8

C10

VSS

C12

C14

C16

C18

C20

C22

C24

6

N11

P10

P11

R11

T16

T17

T18

T19

U16

U17

U20

V16

V18

V20

W16

N10

M10

M11

M9

L10

L11

VCC

VCCN9VCC

VCC

VCC

VCCM8VCC

VCC

VCC

VSS

VSS

VSSD1VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

D9

C26

C28

D11

D13

D15

D17

D19

VSS

D21

D23

D25

D27

D29

D31

D33

VCC

VCC

VCC

VCC

VCC

VSS

VSSF3VSSF5VSSF8VSS

VSSE3VSSF1VSS

VSSE1VSS

D35

VCC

T20

VCC

VCC

F10

W19

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

F18

F20

F22

F24

F14

F16

F12

VCC

VSS

W20

F26

VCC

VSS

5

Y16

VCC

VSS

G28

A33NCA35NCB2NCB25NCB34NCC1NCC23NCC35NCE26NCM31NCAF13NCAF23NCAJ12NCAN1NCAP2NCAR3NCAR33NCAR35

Y17

Y18

Y19

Y20

NCA3NC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSSH8VSS

H2

H5

H9

H12

H14

H16

G31

G35

H18

R25

NC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

J10

J12

J14

H20

H22

H24

J16

H26

H30

H33

4

VCCP

A11

A13

A16

A20

A23

A25

A27

A29

A32

C4

VSSA7VSSA9VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

J18

J20

J22

J28

J32

J35

K11

K12

K14

K16

K18

K20

K22

VTTD5VTTD6VTTD7VTTE6VTTE7VTT

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

L24

L25

L26

L35

L31

K33

K25

K27

K29

F7

VSSM3VSSM6VSS

M26

M27

3

C6

VTTA4VTTA5VTTA6VTTB5VTTB6VTTC5VTT

VSS

VSS

VSS

VSS

VSSN1VSS

RG82865PE-A2

<Priority>

N4

M28

M30

M33

VTT_FSB1
VTT_FSB2

A15

A21

HD0#
HD1#
HD2#
HD3#

VTT_FSB

VTT_FSB

HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DINV_0#
DINV_1#
DINV_2#
DINV_3#

HD_STBP0#
HD_STBN0#

HD_STBP1#
HD_STBN1#

HD_STBP2#
HD_STBN2#

HD_STBP3#
HD_STBN3#

C128 C0.47U16Y
C123 C0.47U16Y

HD#0

B23

HD#1

E22

HD#2

B21

HD#3

D20

HD#4

B22

HD#5

D22

HD#6

B20

HD#7

C21

HD#8

E18

HD#9

E20

HD#10

B16

HD#11

D16

HD#12

B18

HD#13

B17

HD#14

E16

HD#15

D18

HD#16

G20

HD#17

F17

HD#18

E19

HD#19

F19

HD#20

J17

HD#21

L18

HD#22

G16

HD#23

G18

HD#24

F21

HD#25

F15

HD#26

E15

HD#27

E21

HD#28

J19

HD#29

G14

HD#30

E17

HD#31

K17

HD#32

J15

HD#33

L16

HD#34

J13

HD#35

F13

HD#36

F11

HD#37

E13

HD#38

K15

HD#39

G12

HD#40

G10

HD#41

L15

HD#42

E11

HD#43

K13

HD#44

J11

HD#45

H10

HD#46

G8

HD#47

E9

HD#48

B13

HD#49

E14

HD#50

B14

HD#51

B12

HD#52

B15

HD#53

D14

HD#54

C13

HD#55

B11

HD#56

D10

HD#57

C11

HD#58

E10

HD#59

B10

HD#60

C9

HD#61

B9

HD#62

D8

HD#63

B8

HDBI#0

C17

HDBI#1

L17

HDBI#2

L14

HDBI#3

C15
B19

C19
L19

K19
G9

F9
D12

E12

2

HD#[0..63] 5

HDBI#[0..3] 5

HDSTBP#0 5
HDSTBN#0 5

HDSTBP#1 5
HDSTBN#1 5

HDSTBP#2 5
HDSTBN#2 5

HDSTBP#3 5
HDSTBN#3 5

U6_H2

_

VCCP

C136
C0.1U25Y

1

VCC3

I=30mA

VCCP

A A

HSWING

C115
C10000P50Y5

8

R121

1/4*Vccp

300R1%

R103
100R

7

VCCA_FSB

C144
C0.1U25Y

I=35mA

ESR is 0.1mohm to GMCH

VCCA_DPLL

C146
X_0R

6

CP19

X

CP8

R130 X_220R

X

VCC_AGP

VCC_AGP

ICH_SYNC#

MSI

Title

Size Document Number Rev

5

4

3

Date: Sheet

2

R178

X_220R

MICRO-STAR INt'L CO., LTD.

Intel Springdale - CPU Signals

MS-7156

of

730Thursday, June 09, 2005

1

0A

8

MCS_A#010
MCS_A#110

D D

MRAS_A#10
MCAS_A#10

MWE_A#10

MA_A[0..12]10

MBA_A010
MBA_A110

C C

MDQM_A[0..7]10

MDQS_A[0..7]10

MCLK_A010

MCLK_A#010

MCLK_A110

MCLK_A#110

MCLK_A210

MCLK_A#210

B B

C10000P50Y5C204

C10000P50Y5C189

C10000P50Y5C208

C0.1U25YC110

MDQ_A[0..63]10 MCKE_A[0..1] 10

AA34

Y31
Y32

W34

AC33

Y34

AB34

MA_A0

AJ34

MA_A1

AL33

MA_A2

AK29

MA_A3

AN31

MA_A4

AL30

MA_A5

AL26

MA_A6

AL28

MA_A7

AN25

MA_A8

AP26

MA_A9

AP24

MA_A10

AJ33

MA_A11

AN23

MA_A12

AN21

AL34
AM34
AP32
AP31
AM26

AE33
AH34

MDQM_A0

AP12

MDQM_A1

AP16

MDQM_A2

AM24

MDQM_A3

AP30

MDQM_A4

AF31

MDQM_A5

W33

MDQM_A6

M34

MDQM_A7

H32

MDQS_A0

AN11

MDQS_A1

AP15

MDQS_A2

AP23

MDQS_A3

AM30

MDQS_A4

AF34

MDQS_A5

V34

MDQS_A6

M32

MDQS_A7

H31

AK32
AK31

AP17
AN17

N33
N34

AK33
AK34

AM16

AL16

P31
P32

XRCOMP

AK9

XCOMPH

AN9

XCOMPL

AL9

XVREF

E34

C107 X_C2.2U6.3Y

A A

8

7

MDQ_A9

MDQ_A6

MDQ_A5

AL10

AL12

SDQ_A4

SDQ_A5

MDQ_A8

MDQ_A7

AP13

AP14

SDQ_A6

SDQ_A7

MDQ_A10

AL18

AM14

SDQ_A8

SDQ_A9

MDQ_A11

MDQ_A12

AP19

AL14

SDQ_A10

SDQ_A11

U6B

SCS_A0#
SCS_A1#
SCS_A2#
SCS_A3#

SRAS_A#
SCAS_A#

MDQ_A1

MDQ_A0

AP10

AP11

SDQ_A0

SDQ_A1

MDQ_A2

MDQ_A3

AM12

AN13

SDQ_A2

SDQ_A3

MDQ_A4

AM10

SWE_A#

SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12

SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5

SBA_A0
SBA_A1

SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7

SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7

SMDCLK_A0
SMDCLK_A0#

SMDCLK_A1
SMDCLK_A1#

SMDCLK_A2
SMDCLK_A2#

SMDCLK_A3
SMDCLK_A3#

SMDCLK_A4
SMDCLK_A4#

SMDCLK_A5
SMDCLK_A5#

SMXRCOMP
SMXCOMPVOH

SMXCOMPVOL
SMVREF_A

VCC_DDR

VCC_DDR

E35

R35

AA35

VCC_DDR

VCC_DDR

VCC_DDR

AL6

AR15

AR21

VCC_DDR

VCC_DDR

VCC_DDR

AL7

AM1

AM2

VCC_DDR

VCC_DDR

VCC_DDR

AP3

AP4

AN8

C106 C0.47U16Y
C121 C0.22U16Y

VCC_DDR

C126 C10000P50Y5
C164 C0.22U16Y
C167 C0.1U25Y

VCC_DDR_C3
VCC_DDR_C2

values still need verification

XRCOMP

R155 42.2R1%
R171 42.2R1%

YRCOMP XCOMPH

R116 42.2R1%
R109 42.2R1%

7

VCC_DDR_C3

6

MDQ_A17

MDQ_A14

MDQ_A15

MDQ_A13

MDQ_A16

AN15

AP18

AM18

AP22

AM22

SDQ_A12

SDQ_A13

SDQ_A14

SDQ_A15

SDQ_A16

SDQ_A17

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

AP5

AP6

AP7

AR4

AR5

VCC_DDR VCC_DDR

AA35AA33

MDQ_A24

MDQ_A21

MDQ_A23

MDQ_A29

MDQ_A25

MDQ_A30

MDQ_A33

MDQ_A20

MDQ_A22

MDQ_A18

MDQ_A19

AL24

AN27

AP21

AL22

AP25

AP27

AP28

AP29

SDQ_A18

SDQ_A19

SDQ_A20

SDQ_A21

SDQ_A22

SDQ_A23

SDQ_A24

VCC_DDR

VCC_DDR

SDQ_B0

SDQ_B1

SDQ_B2

SDQ_B3

AR31

6

AJ10

AL11

AE15

AE16

MDQ_B2

MDQ_B0

MDQ_B3

MDQ_B1

R168 31.6KR1%
R177 10.2KR1%

R145 10.2KR1%
R144 31.6KR1%

AL8

MDQ_B4

AR7

XCOMPL YCOMPL

MDQ_A27

MDQ_A26

AP33

AM33

SDQ_A25

SDQ_A26

SDQ_A27

SDQ_B4

SDQ_B5

SDQ_B6

AF12

AK11

MDQ_B5

MDQ_B6

MDQ_A28

AM28

AN29

AM31

SDQ_A28

SDQ_A29

SDQ_B7

SDQ_B8

AL13

AE17

AG12

MDQ_B9

MDQ_B8

MDQ_B7

MDQ_A32

MDQ_A31

AN34

AH32

SDQ_A30

SDQ_A31

SDQ_A32

SDQ_B9

SDQ_B10

SDQ_B11

AL17

AK17

MDQ_B11

MDQ_B10

MDQ_A34

MDQ_A35

AG34

AF32

AD32

SDQ_A33

SDQ_A34

SDQ_B12

SDQ_B13

AJ14

AJ16

AK13

MDQ_B14

MDQ_B12

MDQ_B13

VCC_DDR

MDQ_A36

MDQ_A37

AH31

AG33

SDQ_A35

SDQ_A36

SDQ_A37

SDQ_B14

SDQ_B15

SDQ_B16

AJ18

AE19

MDQ_B15

MDQ_B16

MDQ_A38

MDQ_B17

MDQ_A40

MDQ_A39

AE34

AD34

SDQ_A38

SDQ_A39

SDQ_B17

SDQ_B18

AE20

AG23

MDQ_B18

MDQ_B19

5

MDQ_A41

MDQ_A42

AC34

AB31

V32

SDQ_A40

SDQ_A41

SDQ_B19

SDQ_B20

AL19

AK23

AK21

MDQ_B20

MDQ_B21

R33

YCOMPH

5

MDQ_A43

MDQ_A44

V31

AD31

SDQ_A42

SDQ_A43

SDQ_A44

SDQ_B21

SDQ_B22

SDQ_B23

AJ24

AE22

MDQ_B22

MDQ_B23

MDQ_A49

MDQ_A48

MDQ_A45

MDQ_A46

MDQ_A47

AB32

U34

U33

T34

T32

SDQ_A45

SDQ_A46

SDQ_A47

SDQ_A48

SDQ_B24

SDQ_B25

SDQ_B26

SDQ_B27

AJ26

AF27

AK25

AH26

AG27

MDQ_B24

MDQ_B26

MDQ_B27

MDQ_B28

MDQ_B25

R102 31.6KR1%
R100 10.2KR1%

R108 10.2KR1%
R101 31.6KR1%

MDQ_A51

MDQ_A50

K34

K32

SDQ_A49

SDQ_A50

SDQ_A51

SDQ_B28

SDQ_B29

SDQ_B30

AJ27

AD25

MDQ_B30

MDQ_B29

MDQ_A52

MDQ_A53

MDQ_A54

T31

P34

L34

SDQ_A52

SDQ_A53

SDQ_B31

SDQ_B32

AF28

AE30

AC27

MDQ_B31

MDQ_B33

MDQ_B32

MDQ_A56

MDQ_A55

L33

J33

SDQ_A54

SDQ_A55

SDQ_A56

SDQ_B33

SDQ_B34

SDQ_B35

Y29

AC30

MDQ_B35

MDQ_B34

MDQ_A57

MDQ_A59

MDQ_A58

H34

E33

F33

SDQ_A57

SDQ_A58

SDQ_A59

SDQ_B36

SDQ_B37

SDQ_B38

AE31

AB29

AA26

MDQ_B38

MDQ_B37

MDQ_B36

VCC_DDR_C2

R35

MDQ_A61

MDQ_A60

MDQ_A62

K31

J34

G34

SDQ_A60

SDQ_A61

SDQ_B39

SDQ_B40

W30

AA27

AA30

MDQ_B40

MDQ_B39

MDQ_B41

4

MDQ_A63

F34

SDQ_A62

SDQ_A63

SDQ_B41

SDQ_B42

SDQ_B43

T25

U27

MDQ_B43

MDQ_B42

4

MCKE_A1

MCKE_A0

AL20

AN19

AM20

SCKE_A0

SCKE_A1

SDQ_B44

SDQ_B45

V29

U25

AA31

MDQ_B44

MDQ_B45

MDQ_B46

AP20

SCKE_A2

SCKE_A3

SDQ_B46

SDQ_B47

SDQ_B48

P29

R27

MDQ_B47

MDQ_B48

AC26

AB25

AC25

VCCA_DDR

VCCA_DDR

VCCA_DDR

SDQ_B49

SDQ_B50

SDQ_B51

L30

K28

R30

MDQ_B51

MDQ_B49

MDQ_B50

VCCA_DDR

AL35

AN4

VCCA_DDR

SDQ_B52

SDQ_B53

P25

R31

R26

MDQ_B53

MDQ_B52

MDQ_B54

C0.1U25Y

C0.1U25YC133

AM3

AN5

AM5

VCC_DDR

VCC_DDR

VCC_DDR

SDQ_B54

SDQ_B55

SDQ_B56

L32

K30

H29

MDQ_B55

MDQ_B56

MDQ_B57

VCCA_DDR

AM6

AM7

AM8

VCC_DDR

VCC_DDR

VCC_DDR

SDQ_B57

SDQ_B58

SDQ_B59

F32

N25

G33

MDQ_B59

MDQ_B58

MDQ_B60

C153

VCC_DDR

AN2

AN6

AN7

VCC_DDR

VCC_DDR

VCC_DDR

SDQ_B60

SDQ_B61

SDQ_B62

J29

G32

M25

MDQ_B63

MDQ_B62

MDQ_B61

3

N35

N32

VSS

VSS

VCC_DDR

SDQ_B63

SCKE_B0

SCKE_B1

AF19

AK19

MCKE_B0

MCKE_B1

VCCA_DDR

CP9 X

3

P8

SCS_B0#

VSSP3VSSP6VSS

SCS_B1#
SCS_B2#
SCS_B3#

SRAS_B#
SCAS_B#

SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8

SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12

SMAB_B1

SMAB_B2

SMAB_B3

SMAB_B4

SMAB_B5

SDQS_B0

SDQS_B1

SDQS_B2

SDQS_B3

SDQS_B4

SDQS_B5

SDQS_B6

SDQS_B7

SCMDCLK_B0

SCMDCLK_B0#

SCMDCLK_B1

SCMDCLK_B1#

SCMDCLK_B2

SCMDCLK_B2#

SCMDCLK_B3

SCMDCLK_B3#

SCMDCLK_B4

SCMDCLK_B4#

SCMDCLK_B5

SCMDCLK_B5#

SMYRCOMP

SMYCOMPVOH
SMYCOMPVOL

SMVREF_B

SCKE_B2

SCKE_B3

RG82865PE-A2

<Priority>

AE18

AG19

Its current is 5.1A.

U26
T29
V25
W25

W26
W31

W27

SWE_B#

AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20

AE27
AD26
AL29
AL27
AE23

Y25

SBA_B0

AA25

SBA_B1

AG11

SDM_B0

AG15

SDM_B1

AE21

SDM_B2

AJ28

SDM_B3

AC31

SDM_B4

U31

SDM_B5

M29

SDM_B6

J31

SDM_B7

AF15
AG13
AG21
AH27
AD29
U30
L27
J30

AG29
AG30

AF17
AG17

N27
N26

AJ30
AH29

AK15
AL15

N31
N30

AA33
R34

R33
AP9

MCKE_B[0..1] 10MDQ_B[0..63]10

Solder side.

CB10 X_C1U16Y0805
CB11 X_C1U16Y0805

MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12

MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7

MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7

YRCOMP
YCOMPH

YCOMPL

YVREF

VCC_AGP

2

MCS_B#0 10
MCS_B#1 10

MRAS_B# 10
MCAS_B# 10

1

MWE_B# 10

MA_B[0..12] 10

VCC_DDR

CB3 X_C1U16Y0805
CB7 X_C1U16Y0805
CB6 C100P50N0805

MBA_B0 10
MBA_B1 10

MDQM_B[0..7] 10

MDQS_B[0..7] 10

MCLK_B0 10
MCLK_B#0 10

MCLK_B1 10
MCLK_B#1 10

MCLK_B2 10
MCLK_B#2 10

C10000P50Y5C122
C10000P50Y5C119

C10000P50Y5C105
C0.1U25YC176

R156 150R1%
R173 150R1%
C205 X_C2.2U6.3Y

MSI

Title

Size Document Number Rev

Date: Sheet

MICRO-STAR INt'L CO., LTD.

Intel Springdale - Memory Signals

2

MS-7156

VCC_DDR

of

830Thursday, June 09, 2005

1

0A

8

7

6

5

4

3

2

1

C194 C0.1U25Y

C166 C0.1U25Y

VCC_AGP

P26

P27

P28

P30

P33

R32

VSS

VSS

AE26

VSS

VSS

AE32

VSSR1VSSR4VSS

VSS

VSS

AF3

AE35

T3

VSST1VSS

VSST6VSST8VSST9VSS

VSS

VSS

VSS

VSS

AF6

AF9

AF11

AF14

VSS

AD30

VSS

AD33

VSS

AD28

P9

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AE1

AE4

AE10

AE11

AE12

AE13

AE25

GAD[0..31]17

D D

C C

GC_BE#[0..3]17

AD_STB017

AD_STB#017

AD_STB117

AD_STB#117

GREQ#17

GGNT#17

ST[0..2]17

RBF#17

WBF#17

GFRAME#17

GIRDY#17

GTRDY#17

GDEVSEL#17

GSTOP#17

GAD0
GAD1

GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3

ST0
ST1
ST2

RBF#
WBF#

GPAR17

MCH_6614

VCC_AGP

SBA[0..7]17

SB_STB17

SB_STB#17

PIPE#17

DBI_LO17

R140 43.2R1%

C10000P50Y5C170

GSWING17

C10000P50Y5C191

AGP_REF17

B B

A A

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

GRCOMP
GSWING

U6C

AE6

GAD0/DVOB_HSYNC

AC11

GAD1/DVOB_VSYNC

AD5

GAD2/DVOB_D1

AE5

GAD3/DVOB_D0

AA10

GAD4/DVOB_D3

AC9

GAD5/DVOB_D2

AB11

GAD6/DVOB_D5

AB7

GAD7/DVOB_D4

AA9

GAD8/DVOB_D6

AA6

GAD9/DVOB_D9

AA5

GAD10/DVOB_D8

W10

GAD11/DVOB_D11

AA11

GAD12/DVOB_D10

W6

GAD13/DVOBC_CLKINT

W9

GAD14/DVOB_FLDSTL

V7

GAD15/MDDC_DATA

AA2

GAD16/DVOC_VSYNC

Y4

GAD17/DVOC_HSYNC

Y2

GAD18/DVOC_BLANK#

W2

GAD19/DVOC_D0

Y5

GAD20/DVOC_D1

V2

GAD21/DVOC_D2

W3

GAD22/DVOC_D3

U3

GAD23/DVOC_D4

T2

GAD24/DVOC_D7

T4

GAD25/DVOC_D6

T5

GAD26/DVOC_D9

R2

GAD27/DVOC_D8

P2

GAD28/DVOC_D11

P5

GAD29/DVOC_D10

P4

GAD30/DVOBC_INTR#

M2

GAD31/DVOC_FLDSTL

Y7

GCBE0/DVOB_D7

W5

GCBE1/DVOB_BLANK#

AA3

GCBE2

U2

GCBE3/DVOC_D5

AC6

GADSTBF0/DVOB_CLK

AC5

GADSTBS0/DVOB_CLK#

V4

GADSTBF1/DVOC_CLK

V5

GADSTBS1/DVOC_CLK#

N6

GREQ

M7

GGNT

N3

GST0

N5

GST1

N2

GST2

R10

GRBF

R9

GWBF

U6

GFRAME/MDVI_DATA

V11

GIRDY/MI2CCLK

AB5

GTRDY/MDVI_CLK

AB4

GDEVSEL/MI2CDATA

W11

GSTOP/MDDC_CLK

AB2

GPAR/ADD_DETECT

H4

GCLKIN

R6

GSBA0#/ADD_ID0

P7

GSBA1#/ADD_ID1

R3

GSBA2#/ADD_ID2

R5

GSBA3#/ADD_ID3

U9

GSBA4#/ADD_ID4

U10

GSBA5#/ADD_ID5

U5

GSBA6#/ADD_ID6

T7

GSBA7#/ADD_ID7

U11

GSBSTBF

T11

GSBSTBS

M4

DBI_HI

M5

DBI_LO

AC2

GRCOMP/DVOBC_RCOMP

AC3

GVSWING

AD2

GVREF

AF16

VSS

AF18

VSS

T10

VSS

VSS

AF20

T26

AF22

VSS

VSS

T27

AF24

VSS

VSS

T28

VSS

VSS

AF25

T30

AF30

VSS

T33

VSS

VSS

AF33

H_SWING=(0.8*VCC_AGP)+-2%

VCC_AGP

R170 226R1%
R167 147R1%

R172 113R1%

C200 C0.1U25Y

C173 C0.1U25Y

HL_SWING
H_SWING

HL_VREF
H_VREF

800mV

H_SWING 13

350mV

H_VREF 13

T35

AG4

VSS

VSS

VSSU4VSS

VSS

AG8

U18

VSS

AG14

U19

VSS

VSS

AG16

U32

VSS

VSS

AG18

V6

VSS

VSSV3VSSV8VSSV9VSS

VSS

VSS

VSS

VSS

AG20

AG22

AG24

AG26

V10

VSS

AG28

V17

VSS

VSS

AG32

V19

VSS

VSS

AG35

V26

AH3

VSS

VSS

V27

AH6

VSS

VSS

V28

VSS

VSS

AH10

V30

VSS

VSS

AH12

V33

VSS

VSS

AH14

VSSW4VSS

VSS

AH16

W17

VSS

AH18

W18

AH20

VSS

VSS

W32

VSS

VSS

AH22

Y3

VSS

VSSY6VSSY8VSSY9VSS

VSS

VSS

VSS

AH24

AH30

AH33

Y28

Y30

Y33

Y35

Y26

Y27

AA1

AA4

AA32

AB10

AB26

AB27

AB28

AB30

AB9

VSS

VSS

AK24

VSS

VSS

AK26

VSS

VSS

AK28

AB33

VSS

VSS

VSS

VSS

VSS

VSS

AL1

AM9

AL32

AM11

AB3

AB6

VSS

VSS

AK10

VSS

VSS

AK12

VSS

VSS

AK14

VSS

VSS

AK16

VSS

VSS

AK18

VSS

VSS

AK20

AB8

VSS

VSS

AK22

Y10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AJ1

AJ4

AJ9

AK3

AK8

AJ32

AJ35

Springdale Decoupling Capacitors

VCC_DDR

VSS

VSS

AC1

VSS

VSS

AM13

AC4

VSS

VSS

AM15

AC32

AC35

VSS

VSS

VSS

VSS

AM17

AM19

C182
C2.2U6.3Y

AD3

AD6

AD8

AD9

AD10

L5

VSS

VSS

VSS

VSS

VSS

VCC_AGPL1VCC_AGP

VCC_AGPY1VCC_AGPJ1VCC_AGPJ2VCC_AGPJ3VCC_AGPK2VCC_AGPK3VCC_AGPK4VCC_AGPK5VCC_AGPJ4VCC_AGPJ5VCC_AGPL4VCC_AGPL2VCC_AGP

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AN10

AN12

AN14

AN16

AM29

AM35

AN18

AM21

AM23

AM25

AM27

VSS

VSS

AN20

LAN CSA port

VSS

VSS

VSS

AN22

AN24

AN26

VSS

AN28

VSS

AN30

VSS

AN32

VSS

AR9

VSS

AR11

L3

VSS

AR13

AG1

Y11

VCCA_AGP

VCCA_AGP

HI10

HI_STRF
HI_STRS

HI_RCOMP

HI_SWING

HI_VREF

CI10

CISTRF

CISTRS

CI_RCOMP

CI_SWING

CI_VREF

DREFCLK

DDCA_CLK

DDCA_DATA

VSYNC
HSYNC

BLUE

BLUE#

GREEN

GREEN#

RED

RED#

REFSET

VCC_DAC
VCC_DAC

VCCA_DAC

VSSA_DAC

EXTTS#

RESERVED
RESERVED
RESERVED
RESERVED
RESERVED

VSS
VSS
VSS
VSS

VSS

VSS

VSS

RG82865PE-A2

<Priority>

AR23

AR16

AR20

HL0

AF5

HI0

HL1GAD2

AG3

HI1

HL2

AK2

HI2

HL3

AG5

HI3

HL4

AK5

HI4

HL5

AL3

HI5

HL6

AL2

HI6

HL7

AL4

HI7

HL8

AJ2

HI8

HL9

AH2

HI9

HL10

AJ3
AH5

AH4

HL_COMP

AD4

HL_SWING

AE3

HL_VREF

AE2
AK7

CI0

AH7

CI1

AD11

CI2

AF7

CI3

AD7

CI4

AC10

CI5

AF8

CI6

AG7

CI7

AE9

CI8

AH9

CI9

AG6
AJ6

AJ5

CI_RCOMP

AG2
AF2

AF4

G4
F2

H3
E2

G3
H7

G6
H6

G5
F4

E4
D2
G1

G2

C2

D3

AP8
AG9

AG10
AN35
AP34
AR1

AR25
AR27
AR29
AR32

H_SWING=(0.233*VCC_AGP)+-2%

8

7

6

5

4

3

VCC_AGP

C156
C0.1U25Y

HL[0..10] 13

HI_RCOMP Calculation
R=[(1.5V-08V)/0.8V]*60ohm=52.5ohm

HL_STRF 13
HL_STRS 13

R138 52.3R1%

C10000P50Y5C183

VCC_AGP

C10000P50Y5C192

VCC_AGP

CB5 X_C1U16Y0805

R146 52.3R1%

CI_SWING
CI_VREF

C149
C10000P50Y5

VCC_AGP

MSI

Title

Size Document Number Rev

Date: Sheet

2

VCC_AGP

X_C0.01U50XC185
X_C0.01U50XC193

VCC3

R158 226R1%
R159 147R1%

R160 113R1%

CI_SWING

CI_VREF

MICRO-STAR INt'L CO., LTD.

Intel Springdale - AGP & HLink & LAN Signals

MS-7156

of

930Thursday, June 09, 2005

1

800mV

350mV

0A