MSI MS-7145 Schematics

5

4

3

2

1

1 Cover Sheet
2

MS-7145 Ver : 0A

Processor : AMD OuPGA754 (Athlon 64)
Chipset : ATI RS480 + ATI SB400

D D

CPU:

AMD OuPGA754 (HT800)
ClawHammer / NewCastle / Paris

10

System Chipset:

ATI RS480 Rev : A13
ATI SB400 Rev : A31

On Board Chipset:

C C

LPC Super I/O : W83627THF Rev : E
LAN : BCM 4401
IEEE1394a : VT6307

Code : ALC850

Expansion Slots:

PCIE X 16 ----Slot * 1
DDR 400------Slot * 2
PCI 2.2--------Slot * 3

B B

Size 244mm * 244mm

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29

Block Diagram
Clock Generator -- ICS951412A

3

Athlon64 OuPGA754 -- HT / IF / CTRL / Debug

4

Athlon64 OuPGA754 -- DDR / IF

5

Athlon64 OuPGA754 -- Power

6
7

DIMM1 / DIMM2
DDR Terminator

8

ATI RS480 North Bridge -- HT / PCIE / SIDE MEM

9

ATI RS480 North Bridge -- Video / IF / Clock / Strap
ATI RS480 North Bridge -- Power
PCIE X 16
ATI SB400 South Bridge -- PCI / CPU / LPC / RTC
ATI SB400 South Bridge -- ACPI / GPIO / AC97 / USB
ATI SB400 South Bridge -- IDE / S-ATA
ATI SB400 South Bridge -- Power
ATI SB400 South Bridge -- Straps
IDE Connector / S-ATA Connector
LAN BCM4401
IEEE1394a VT6301
PCI 1 / PCI 2 / PCI 3 Slots
AC97 Audio CODEC ALC850 / Connector
USB Connector
LPC I/O W83627THF-E / ROM / FDD Connector
COM Port / FAN Connector
VRM K8 (OuPGA754) - ISL6568
MS6-RBF ACPI Controller / Regulators
VGA Connector
Front Panel / ATX power Com

CPU

L1 Cache 64KB + 64KB

L2 Cache

CPU

架構

Cool n'Quiet

.....

A A

.... .....

MODEL Config.
MS7145 STD

.....

.....

cfg7045-std

5

STD + Lan + 4M BIOS

4

OptionORCAD Config.

Kernel

ERP NumberFunction

STD

3

Athlon 64

64KB + 64KB

1MB

64-bit

Yes

ClawHammer

2

SempronAthlon 64

64KB + 64KB

512KB

64-bit

Yes

NewCastle

Title

Cover Sheet

Size Document Number Rev

Custom

Date: Sheet

256KB

32-bit

No

Paris

62WMax Power 89W89W 89W

MICRO-START INT'L CO.,LTD.

MS-7145 0A

1

Sempron

64KB + 64KB

256KB

32-bit

No

Palermo

132Friday, December 31, 2004

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5

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AMD Hammer

1.1000V ~ 1.5500V
60 A

D D

AMD 754 Pin

Processor

ClawHammer / NewCastle

Paris

100 MHz / 133M Hz / 200M Hz

Differential Clock Pair

DDR 266 / DDR333 / DDR400

Max 2GB

DEVICE

PCI Slot 1

PCI Slot 2 PCI_CLK2

200 MHz

PCIE * 16 Slot

100 MHz

Differential Clock Pair

PCIE * 16

ATI

Differential Clock Pair

EXT 14.318 MHz

PCI Slot 2

RS400

North Bridge

On Die VGA

C C

A-Link

PCIE * 2

664-Balls

BGA Package

100 MHz

Differential Clock Pair

100 MHz

Differential Clock Pair

48 MHz

14.318 MHz

Clock

Generator

(ICS951412)

14.318 MHz
48 MHz

IEEE1394a PCI_CLK1INTG#

SIO

INT#

INTE#

INTG#
INTH#
INTF#
INTG#
INTH#
INTE#
INTG#
INTH#
INTE#
INTF#

INTH#LAN

PCI_REQ#0INTF#
PCI_GNT#0

PCI_REQ#1
PCI_GNT#1

PCI_REQ#2
PCI_GNT#2

PCI_REQ#3
PCI_GNT#3

PCI_REQ#5
PCI_GNT#5

IDSELREQ#/GNT#

PCI_AD16

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

CLOCK

PCI_CLK5

PCI_CLK3

PCI_CLK0

PCI_CLK6BIOS

PCI_CLK7

EXT 32.768 KHz

ATA 133/100/66/33

IDE Primary

Dual IDE

IDE Secondary

S-ATA 0
S-ATA 1

B B

S-ATA 2
S-ATA 3

S-ATA 1.0

RAID 0 / 1 / 0+1

USB 1/2

ATI

SB400

Sourth Bridge

BGA Package

USB 3/4

USB 1/2 : Connector
USB 3/4 : Connector
USB 5/6 : Header follow Intel Standard
USB 7/8 : Header follow Intel Standard

USB 5/6
USB 7/8

USB 2.0/1.1

PCI Interface 2.2
3 PCI Master

PCI Bus

LAN

BCM4401

IEEE1394a

VT6307

33 MHz

33 MHz

EXT 25 MHz

33 MHz

EXT 24 MHz

14.318 MHz

SIO

A A

AC'97 Codec

7.1 Channel Speaker
ALC850

5

W83627THF

33 MHz

48 MHz

4

LPC ROM

2M

Floopy

3

Serial

Port * 1

Title

Block Diagram

Size Document Number Rev

Custom

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7145 0A

1

of

232Friday, December 31, 2004

5

+3.3V CLK_VDD

L22 X_L28RD9A5D1
CP18 X_CP

1 2

C495
C10U10V5Y5VL

D D

+3.3V

L20 X_L28RD9A5D1
CP16

1 2

C C

C22P50V2NPOLC465 R221 33R2F

C22P50V2NPOLC472

C491
X_CD1U16V3Y5VL

21

Y2

14.318MHZ-16PF

CLK_VDD48

C473
C1U10V3Y5VL

R209
X_1MR2

4

C449
X_C10U10V5Y5VL

CLK_VDD

X1
X2

C423
CD1U16V2Y5VL

U21

43

VDDCPU

14

VDDSRC3

21

VDDSRC2

32

VDDSRC1

35 44

VDD_SRC0 CPUCLK8C0

51

VDD_PCI

3

VDD48

48

VDDHTT

56

VDDREF

5

GND1

55

GND2

36

GNDSRC0

31

GNDSRC1

26

GNDSRC2

20

GNDSRC3

15

GNDSRC4

49

GNDPCI

46

GNDHTT

42

GNDCPU

1

X1

2

X2

6

NC

C424
CD1U16V2Y5VL

VDDA

GNDA
CPUCLK8T0
CPUCLK8T1

CPUCLK8C1

SRCCLKT7
SRCCLKC7
SRCCLKT6
SRCCLKC6
SRCCLKT5
SRCCLKC5
SRCCLKT4
SRCCLKC4
SRCCLKT3
SRCCLKC3
SRCCLKT2
SRCCLKC2
SRCCLKT1
SRCCLKC1
SRCCLKT0
SRCCLKC0

SEL75#/100/PCICLK0

C426
CD1U16V2Y5VL

39
38

45
41

40
12

13
16
17
18
19
22
23
24
25
27
28
30
29
34
33

50

3

CLK_VDDA

CPUCLK_EXT_R
CPUCLK#_EXT_R

SBSRCCLK_R
SBSRCCLK#_R
GFXCLK_R
GFXCLK#_R
NBSRCCLK_R
NBSRCCLK#_R
SBLINKCLK_R
SBLINKCLK#_R

C418
CD1U16V2Y5VL

C425
CD1U16V2Y5VL

R178 15R3F
R179 15R3F

R220 33R2F
R214 33R2F

R215 33R2F
R176 33R2F
R177 33R2F
R174 33R2F
R175 33R2F

CLK_VDD

C474
CD1U16V2Y5VL

L17 X_L28RD9A5D1
CP12 X_CP

C410
X_C10U10V5Y5VL

SBSRCCLK
SBSRCCLK#
GFXCLK
GFXCLK#
NBSRCCLK
NBSRCCLK#
SBLINKCLK
SBLINKCLK#

2

C475
CD1U16V2Y5VL

12

CPU_CLK
CPU_CLK#

GFXCLK
GFXCLK#
NBSRCCLK
NBSRCCLK#
SBLINKCLK
SBLINKCLK#
SBSRCCLK
SBSRCCLK#

R232 49D9R2F
R233 49D9R2F
R226 49D9R2F
R227 49D9R2F
R167 49D9R2F
R168 49D9R2F
R165 49D9R2F
R166 49D9R2F

C484
X_C10U10V5Y5VL

+3.3V

CPU_CLK 4
CPU_CLK# 4

GFXCLK 12
GFXCLK# 12
NBSRCCLK 10
NBSRCCLK# 10
SBLINKCLK 10
SBLINKCLK# 10
SBSRCCLK 13
SBSRCCLK# 13

1

CPU

PCIE

N/B

N/B

S/B

SMB_CLK4,7,12,14,19,27

SMB_DATA4,7,12,14,19,27

B B

Ioh = 5 * Iref (2.32mA)

Voh = 0.71V @ 60 ohm

SMB_CLK
SMB_DATA

OSC14M_REFOUT

CLK_VDD

R216
X_10KR2

R219
0R2

IREF

R193
475R2F

CLKREQB#

7

SCLK

8

SDATA

52

REF2

37

IREF

11

CLKREQB#

10

CLKREQA#

ICS951412AG

FS0/REF0
FS1/REF1

FS2

USB_48MHz

HTTCLK0

54
53
9

4
47

AC97_CLK_R
SB_OSC_14M_R
FS2

USBCLK_EXT_R
HTREFCLK_R

8P4R-10KR2

1 2

3 4

5 6

7 8

R217 33R2F
R192 33R2F

R169
51D1R3F

RN75

USBCLK_EXT
HTREFCLK

C479
X_C10P25V2NPOL

OSC14M_REFOUT

USBCLK_EXT 14
HTREFCLK 10

RN76

1 2
3 4
5 6
7 8

8P4R-33R3

7

8

AC97_CLK
SB_OSC_14M

NB_OSC_14M

135

CN6

X_8P4C-10P50V3NPO

246

AC97_CLK 22
SB_OSC_14M 14
NB_OSC_14M 10

EXT CLK FREQUENCY SELECT TABLE(MHZ)

CPU

FS1

FS0

FS2

0 0 0
0 0 1

A A

0 1 0
0 1 1
1 0 0
1 0 1
1 1 1

SRCCLK

[2:1]

100.00

Hi-Z
X

100.00 48.00

180.00

100.00 48.00

100.00

220.00

100.00

100.00

133.33

200.00

100.00 48.00

5

HTT

Hi-Z
X/3

60.00

36.56

66.66

66.66

66.66

PCI

Hi-Z
X/6

30.00

73.12

33.33

33.33

33.33

USB

48.00

COMMENT

Reserved
Reserved
Reserved
Reserved

48.00
Reserved

48.00

48.00

Reserved100.00
Normal HAMMER operation

4

1- PLACE ALL THE SERIES TERMINATION RESISTORS AS CLOSE AS U7 AS POSSIBLE
2- ROUTE ALL CPUCLK/#, NBSRCCLK/#, GPPCLK/# AS DIFFERENT PAIR RULE
3- PUT DECOUPLING CAPS CLOSE TO U7 POWER PIN

Title

Clock Generator - ICS951412

Size Document Number Rev

Custom

3

2

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7145 0A

1

of

332Friday, December 31, 2004

5

Q8
2N7002S

VCC_DDR

C26

D D

C C

X_C1U10V3Y5VL

VCC1_2HT_OUT5

CPU_CLK3

CPU_CLK#3

VDD_25 VDD_25+12VP

C22
X_C10U10V5Y5VL

VCC1_2HT_OUT

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

CPU_CLK

CPU_CLK#

R33 44D2R3F
R34 44D2R3F

Near CPU in 0.5" .

RN10

8P4R-680R3

C427
X_C1000P16V2X7RL

C66
C1000P16V2X7RL

C3900P50V3X7RLC61

C3900P50V3X7RLC60

VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".

Place all filters close to the PGA.

Keep all power and signal trace away from
the VR1.

Place a cut in the GND plane around the
VCCA_PLL regulator circuit.

B B

A A

NC_C18
NC_A19
NC_C21

NC_D18
NC_B19
NC_C19
NC_D20

THERMDA_CPU24

THERMDC_CPU24

THERMDA_CPU

THERMDC_CPU
CPU_THRIP#

Already have pull high to VCC2_5 in MS6

5

VDDA_25

RN40

1 2
3 4
5 6
7 8

8P4R-680R3

RN41

1 2
3 4
5 6
7 8

8P4R-680R3

C3
X_C1000P16V2X7RL

VCC_DDR

OD

C201
X_C1U10V3Y5VL

+3.3V

4

VDDA_25

78

CPU_THRIP#

56

LDT_RST#

34

LDTSTOP#

12

C67
C1000P16V2X7RL

R45
169R3F

VCC_DDR

R36 820R3F
R35 820R3F

C38
X_C1000P16V2X7RL

NC_AG17
NC_AH18
NC_AG18
NC_AJ18

Since THERM_ALERT# is S5 power plant in SB400.
ATI's recommend to pull-up to 3V-dual.

U1

1

VDD

2

D+

3

D-

4 8

T_CRIT_A# SMC

X_LM90

4

RN9

1 2
3 4
5 6
7 8

8P4R-680R3

GND

ALERT#

SMD

FB2 L300RD7A5D25

C27
X_C10U10V5Y5VL

LDT_RST#13

LDTSTOP#10,13

CPU_VTT_SENSE27

VDDIOSENSE27

NC_AJ23
NC_AH23

VDDIOSENSE

5

OD

6
7

3

CPU_VDDA_25LDT_PG

C10U10V5Y5VLC28
CD22U16V3X7RLC49
C1000P16V2X7RLC68

LDT_RST#

LDT_PG13

COREFB_H26

COREFB_L26

RN11
X_8P4R-1KR2

Already have pull high to 3VSB in S/B

THERM_ALERT#
SMB_DATA
SMB_CLK

LDT_PG
LDTSTOP#

L0_REF1
L0_REF0

Differential , "10:10:5:10:10" .

COREFB_H
COREFB_L

CPU_VTT_SENSE
VDDIOSENSE

CLKIN_H
CLKIN_L

NC_AJ23
NC_AH23

NC_C18
NC_A19

NC_AE23
NC_AF23
NC_AF22
NC_AF21

+5V

C57
CD1U16V2Y5VL

1 2

3 4

5 6

7 8

THERM_ALERT# 14,24
SMB_DATA 3,7,12,14,19,27
SMB_CLK 3,7,12,14,19,27

3

VTT_DDR

2

LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
traces to exit ball field) and 500 mils long.

U9C

AH25

VDDA1

AJ25

VDDA2

AF20

RESET_L

AE18

PWROK

AJ27

LDTSTOP_L

AF27

L0_REF1

AE26

L0_REF0

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AJ21

CLKIN_H

AH21

CLKIN_L

AJ23

NC_AJ23

AH23

NC_AH23

AE24

NC_AE24

AF24

NC_AF24

C16

VTT_A5

AG15

VTT_B5

AH17

DBRDY

C15

NC_C15

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

C18

NC_C18

A19

NC_A19

A28

KEY1

AJ28

KEY0

AE23

NC_AE23

AF23

NC_AF23

AF22

NC_AF22

AF21

NC_AF21

C1

FREE29

J3

FREE31

R3

FREE33

AA2

FREE35

D3

FREE1

AG2

FREE37

B18

FREE4

AH1

FREE38

AE21

FREE41

C20

FREE7

AG4

FREE11

C6

FREE12

AG6

FREE13

AE9

FREE14

AG9

FREE40

ZIF-SOCKET754-1.27pitch

THERMTRIP_L

THERMDA
THERMDC

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17

NC_AJ18

G_FBCLKOUT_H

G_FBCLKOUT_L

DBREQ_L

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

TDO

NC_AF18

RSVD_SCL
RSVD_SDA

FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27

2

Pull high to VCC2_5 on MS6 & VDDA_25

CPU_THRIP#

A20

THERMDA_CPU

A26

THERMDC_CPU

A27

VID4

AG13

VID3

AF14

VID2

AG14

VID1

AF15

VID0

AE15

NC_AG18

AG18

NC_AH18

AH18

NC_AG17

AG17

NC_AJ18

AJ18

FBCLKOUT_H

AH19

Zdiff = 80.6 ohm

AJ19

FBCLKOUT_L

AE19

NC_D20

D20

NC_C21

C21

NC_D18

D18

NC_C19

C19

NC_B19

B19
A22

AF18

(May 2004) Schematic Review Checklist Rev:2.19

Connected directly to VDDIO

★

D22
C22

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

Title

Athlon64 OuPGA754 -- HT / IF / CTRL / Debug

Size Document Number Rev

Custom

Date: Sheet

CPU_THRIP# 27
THERMDA_CPU 24

THERMDC_CPU 24
VID4 26

VID3 26
VID2 26
VID1 26
VID0 26

R44
80D6R3F

VCC_DDR

+12VP

VCC_DDR

VDD_25

VDDA_25

VTT_DDR

+12VP 26

VCC_DDR 5,6,7,8,27

VDD_25

VDDA_25 27

VTT_DDR 5,8,27

MICRO-START INT'L CO.,LTD.

MS-7145 0A

1

LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )

of

432Friday, December 31, 2004

1

5

VREF routed as 40~50 mils trace wide ,
Space>25 mils

4

3

2

1

X_C1000P16V2X7RLC41

C43 C1U10V3Y5VL

D D

DDR_VREF7

C42 C1U10V3Y5VL

VCC_DDR

R72 15R3F
R73 15R3F

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

C C

B B

MD[63..0]8

DM[7..0]8

A A

VTT_SEN

DDR_VREF

MEMZN
MEMZP

MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49

MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

MDQS7
MDQS6
MDQS5
MDQS4
MDQS3
MDQS2
MDQS1
MDQS0

MDQS[7..0]8

5

U9B

AE13

VTT_SENSE

AG12

MEMVREF1

D14

MEMZN

C14

MEMZP

A16

MEMDATA63

B15

MEMDATA62

A12

MEMDATA61

B11

MEMDATA60

A17

MEMDATA59

A15

MEMDATA58

C13

MEMDATA57

A11

MEMDATA56

A10

MEMDATA55

B9

MEMDATA54

C7

MEMDATA53

A6

MEMDATA52

C11

MEMDATA51

A9

MEMDATA50

A5

MEMDATA49

B5

MEMDATA48

C5

MEMDATA47

A4

MEMDATA46

E2

MEMDATA45

E1

MEMDATA44

A3

MEMDATA43

B3

MEMDATA42

E3

MEMDATA41

F1

MEMDATA40

G2

MEMDATA39

G1

MEMDATA38

L3

MEMDATA37

L1

MEMDATA36

G3

MEMDATA35

J2

MEMDATA34

L2

MEMDATA33

M1

MEMDATA32

W1

MEMDATA31

W3

MEMDATA30

AC1

MEMDATA29

AC3

MEMDATA28

W2

MEMDATA27

Y1

MEMDATA26

AC2

MEMDATA25

AD1

MEMDATA24

AE1

MEMDATA23

AE3

MEMDATA22

AG3

MEMDATA21

AJ4

MEMDATA20

AE2

MEMDATA19

AF1

MEMDATA18

AH3

MEMDATA17

AJ3

MEMDATA16

AJ5

MEMDATA15

AJ6

MEMDATA14

AJ7

MEMDATA13

AH9

MEMDATA12

AG5

MEMDATA11

AH5

MEMDATA10

AJ9

MEMDATA9

AJ10

MEMDATA8

AH11

MEMDATA7

AJ11

MEMDATA6

AH15

MEMDATA5

AJ15

MEMDATA4

AG11

MEMDATA3

AJ12

MEMDATA2

AJ14

MEMDATA1

AJ16

MEMDATA0

R1

MEMDQS17

A13

MEMDQS16

A7

MEMDQS15

C2

MEMDQS14

H1

MEMDQS13

AA1

MEMDQS12

AG1

MEMDQS11

AH7

MEMDQS10

AH13

MEMDQS9

T1

MEMDQS8

A14

MEMDQS7

A8

MEMDQS6

D1

MEMDQS5

J1

MEMDQS4

AB1

MEMDQS3

AJ2

MEMDQS2

AJ8

MEMDQS1

AJ13

MEMDQS0

ZIF-SOCKET754-1.27pitch

RSVD_MEMADDA15
RSVD_MEMADDA14

RSVD_MEMADDB15
RSVD_MEMADDB14

MEMORY INTERFACE

VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4

MEMRESET_L

MEMCKEA
MEMCKEB

MEMCLK_H7

MEMCLK_L7

MEMCLK_H6

MEMCLK_L6

MEMCLK_H5

MEMCLK_L5

MEMCLK_H4

MEMCLK_L4

MEMCLK_H3

MEMCLK_L3

MEMCLK_H2

MEMCLK_L2

MEMCLK_H1

MEMCLK_L1

MEMCLK_H0

MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10

MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

4

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

AG10
AE8

AE7
D10

C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

VTT_DDR

MCKE0
MCKE1

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4

MEMCLK_H1
MEMCLK_L1
MEMCLK_H0MD48
MEMCLK_L0

MCS3#
MCS2#
MCS1#
MCS0#

MSRASA#
MSCASA#
MSWEA#

MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

MSRASB#
MSCASB#
MSWEB#

MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

MCKE0 7,8

MEMCLK_H7 7,8
MEMCLK_L7 7,8
MEMCLK_H6 7,8
MEMCLK_L6 7,8
MEMCLK_H5 7,8
MEMCLK_L5 7,8
MEMCLK_H4 7,8
MEMCLK_L4 7,8

MEMCLK_H1 7,8
MEMCLK_L1 7,8
MEMCLK_H0 7,8
MEMCLK_L0 7,8

MCS3# 7,8
MCS2# 7,8
MCS1# 7,8
MCS0# 7,8

MSRASA# 7,8
MSCASA# 7,8
MSWEA# 7,8

MEMBANKA1 7,8
MEMBANKA0 7,8

MAA[13..0] 7,8

MSRASB# 7,8
MSCASB# 7,8
MSWEB# 7,8

MEMBAKB1 7,8
MEMBAKB0 7,8

MAB[13..0] 7,8

X_C10U10V5Y5VLC215

VCCA_1V2

X_C1U10V3Y5VLC216

C1U10V3Y5VLC198
CD22U16V3X7RLC199
CD1U25V3Y5VLC182
C10U10V5Y5VLC181

HT_CADIN_H[15..0]9
HT_CADIN_L[15..0]9

HT_CLKIN_H19

HT_CLKIN_L19

HT_CLKIN_H09

HT_CLKIN_L09

VCC1_2HT_OUT

HT_CTLIN_H09 HT_CTLOUT_H0 9
HT_CTLIN_L09

R42 49D9R2F
R43 49D9R2F

HT_CADIN_H15
HT_CADIN_L15
HT_CADIN_H14
HT_CADIN_L14
HT_CADIN_H13
HT_CADIN_L13
HT_CADIN_H12
HT_CADIN_L12
HT_CADIN_H11
HT_CADIN_L11
HT_CADIN_H10
HT_CADIN_L10
HT_CADIN_H9
HT_CADIN_L9
HT_CADIN_H8
HT_CADIN_L8
HT_CADIN_H7
HT_CADIN_L7
HT_CADIN_H6
HT_CADIN_L6
HT_CADIN_H5
HT_CADIN_L5
HT_CADIN_H4
HT_CADIN_L4
HT_CADIN_H3
HT_CADIN_L3
HT_CADIN_H2
HT_CADIN_L2
HT_CADIN_H1
HT_CADIN_L1
HT_CADIN_H0
HT_CADIN_L0

CTLIP1
CTLIN1

For DIMM1 Clock

MEMCLK_H55,7
MEMCLK_H75,7
MEMCLK_H05,7

For DIMM2 Clock

MEMCLK_H45,7
MEMCLK_H15,7

MEMCLK_H65,7 MEMCLK_L6 5,7

3

U9A

D29

VLDT0_A6

D27

VLDT0_A5

D25

VLDT0_A4

C28

VLDT0_A3

C26

VLDT0_A2

B29

VLDT0_A1

B27

VLDT0_A0

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

ZIF-SOCKET754-1.27pitch

MEMCLK_H5
MEMCLK_H7
MEMCLK_H0

MEMCLK_H4
MEMCLK_H1
MEMCLK_H6

HYPER TRANSPORT - LINK0

121R2FC95
121R2FC193
121R2FC149

121R2FC91
121R2FC144
121R2FC192

2

VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

VCC1_2HT_OUT

AH29
AH27
AG28
AG26
AF29
AE28
AF25

HT_CADOUT_H15

N26

HT_CADOUT_L15

N27

HT_CADOUT_H14

L25

HT_CADOUT_L14

M25

HT_CADOUT_H13

L26

HT_CADOUT_L13

L27

HT_CADOUT_H12

J25

HT_CADOUT_L12

K25

HT_CADOUT_H11

G25

HT_CADOUT_L11

H25

HT_CADOUT_H10

G26

HT_CADOUT_L10

G27

HT_CADOUT_H9

E25

HT_CADOUT_L9

F25

HT_CADOUT_H8

E26

HT_CADOUT_L8

E27

HT_CADOUT_H7

N29

HT_CADOUT_L7

P29

HT_CADOUT_H6

M28

HT_CADOUT_L6

M27

HT_CADOUT_H5

L29

HT_CADOUT_L5

M29

HT_CADOUT_H4

K28

HT_CADOUT_L4

K27

HT_CADOUT_H3

H28

HT_CADOUT_L3

H27

HT_CADOUT_H2

G29

HT_CADOUT_L2

H29

HT_CADOUT_H1

F28

HT_CADOUT_L1

F27

HT_CADOUT_H0

E29

HT_CADOUT_L0

F29
J26

J27
J29
K29

N25
P25
P28
P27

MEMCLK_L5
MEMCLK_L7
MEMCLK_L0

MEMCLK_L4
MEMCLK_L1
MEMCLK_L6

MEMCLK_L5 5,7
MEMCLK_L7 5,7
MEMCLK_L0 5,7

MEMCLK_L4 5,7
MEMCLK_L1 5,7

Title

Athlon64 OuPGA754 -- DDR / IF

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7145 0A

C10U10V5Y5VLC34

HT_CLKOUT_H1 9
HT_CLKOUT_L1 9
HT_CLKOUT_H0 9
HT_CLKOUT_L0 9

HT_CTLOUT_L0 9

1

VCC1_2HT_OUT 4MCKE1 7,8

HT_CADOUT_H[15..0] 9
HT_CADOUT_L[15..0] 9

of

532Friday, December 31, 2004

5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50

VDDIO6

VDD96
VDD97
VDD98

VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133

VDD93

VDD94

VDD95

VCC_DDRVCORE

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

VCORE

U9E

B2

VSS1

AH20

VSS3

AB21

VSS4

W22

VSS5

M23

VSS6

L24

VSS7

AG25

VSS8

AG27

VSS9

D2

D D

C C

B B

A A

VSS10

AF2

VSS11

W6

VSS12

Y7

VSS13

AA8

VSS14

AB9

VSS15

AA10

VSS16

J12

VSS17

B14

VSS18

Y15

VSS19

AE16

VSS20

J18

VSS21

G20

VSS22

R20

VSS23

U20

VSS24

W20

VSS25

AA20

VSS26

AC20

VSS27

AE20

VSS28

AG20

VSS29

AJ20

VSS30

D21

VSS31

F21

VSS32

H21

VSS33

K21

VSS34

M21

VSS35

P21

VSS36

T21

VSS37

V21

VSS38

Y21

VSS39

AD21

VSS40

AG21

VSS41

B22

VSS42

E22

VSS43

G22

VSS44

J22

VSS45

L22

VSS46

N22

VSS47

R22

VSS48

U22

VSS49

AG29

VSS50

AA22

VSS51

AC22

VSS52

AG22

VSS53

AH22

VSS54

AJ22

VSS55

D23

VSS56

F23

VSS57

H23

VSS58

K23

VSS59

P23

VSS60

T23

VSS61

V23

VSS62

Y23

VSS63

AB23

VSS64

AD23

VSS65

AG23

VSS66

E24

VSS67

G24

VSS68

J24

VSS69

N24

VSS70

R24

VSS71

U24

VSS72

W24

VSS73

AA24

VSS74

AC24

VSS75

AG24

VSS76

AJ24

VSS77

B25

VSS78

C25

VSS79

B26

VSS80

D26

VSS81

H26

VSS82

M26

VSS83

T26

VSS84

Y26

VSS85

AD26

VSS86

AF26

VSS87

AH26

VSS88

C27

VSS89

B28

VSS90

D28

VSS91

G28

VSS92

F15

VSS187

H15

VSS188

AB17

VSS206

AD17

VSS207

B16

VSS208

G18

VSS209

AA18

VSS210

AC18

VSS211

D19

VSS212

F19

VSS213

H19

VSS214

K19

VSS215

Y19

VSS216

AB19

VSS217

AD19

VSS218

AF19

VSS219

J20

VSS220

L20

VSS221

N20

VSS222

GROUND

ZIF-SOCKET754-1.27pitch

VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17

5

U9D

L7

VDD1

AC15

VDD2

H18

VDD3

B20

VDD4

E21

VDD5

H22

VDD6

J23

VDD7

H24

VDD8

F26

VDD9

N7

VDD10

L9

VDD11

V10

VDD12

G13

VDD13

K14

VDD14

Y14

VDD15

AB14

VDD16

G15

VDD17

J15

VDD18

AA15

VDD19

H16

VDD20

K16

VDD21

Y16

VDD22

AB16

VDD23

G17

VDD24

J17

VDD25

AA17

VDD26

AC17

VDD27

AE17

VDD28

F18

VDD29

K18

VDD30

Y18

VDD31

AB18

VDD32

AD18

VDD33

AG19

VDD34

E19

VDD35

G19

VDD36

AC19

VDD39

AA19

VDD38

J19

VDD37

F20

VDD40

H20

VDD41

K20

VDD42

M20

VDD43

P20

VDD44

T20

VDD45

V20

VDD46

Y20

VDD47

AB20

VDD48

AD20

VDD49

G21

VDD50

J21

VDD51

L21

VDD52

N21

VDD53

R21

VDD54

U21

VDD55

W21

VDD56

AA21

VDD57

AC21

VDD58

F22

VDD59

K22

VDD60

M22

VDD61

P22

VDD62

T22

VDD63

V22

VDD64

Y22

VDD65

AB22

VDD66

AD22

VDD67

E23

VDD68

G23

VDD69

L23

VDD70

N23

VDD71

R23

VDD72

U23

VDD73

W23

VDD74

AA23

VDD75

AC23

VDD76

B24

VDD77

D24

VDD78

F24

VDD79

K24

VDD80

M24

VDD81

P24

VDD82

T24

VDD83

V24

VDD84

Y24

VDD85

AB24

VDD86

AD24

VDD87

AH24

VDD88

AE25

VDD89

K26

VDD90

P26

VDD91

V26

VDD92

ZIF-SOCKET754-1.27pitch

POWER

4

VCORE

VCORE

VCORE

VCORE

VCORE

VCORE VCORE

4

CD1U25V3Y5VLC64
X_C10U10V6Y5VLC83
X_C10U10V6Y5VLC104

X_CD1U16V2Y5VLC156
X_CD1U16V2Y5VLC224

CD1U16V2Y5VLC240

CD1U25V3Y5VLC227

X_C6D8P50V3NPORC200

X_CD1U25V3Y5VLC88
X_CD1U25V3Y5VLC107
X_CD1U25V3Y5VLC128
X_CD1U25V3Y5VLC153

CD1U25V3Y5VLC166

CD1U25V3Y5VLC196

In CPU Socket Bottom

C10U10V6Y5VL (B)C617

C6D8P50V3NPOR (B)C620
X_C10U10V6Y5VL (B)C622

CD1U16V3Y5VL (B)C624

C10U10V6Y5VL (B)C626 CD01U25V3Y5VL (B)C625

In CPU Socket

C10U10V6Y5VLC119 CD1U25V3Y5VLC115

C8D2P50V3NPOLC130

VCORE

C10U10V6Y5VLC138

3

CD22U16V3Y5VLC136

3

Brand

Power Limit L2 SizeCPU

Architecture

AD A

Brand
Athlon 64 FX
Athlon 64 89 W
Mobile 64 (DTR)AM A

AM N
AM D
AH N
OS A
OS K
OS B

Mobile 64
Mobile 64
Athlon XP-M
Opteron
Opteron HW
Opteron EE
Sempron DesktopSD A

SD S Sempron Mobile

Part Definition

Athlon 64 754pin
Athlon 64 939pin

C0B3
AP

X

XX- ­Athlon 64 FX 939pin
Athlon 64 FX 940pin
Opteron Uni
Opteron Dual
Opteron Multi

XAKAT

AG

AK

AH

AL

AI

AW

Cool n’Quiet
Model# Voltage frequency
Normal
Intermediate

Max Max

1.2 V ~ 1.4 V 1.8 GHz ~ 2.2 GHz

Minimum

754pin OuPGA Model#
Athlon 64

ClawHammer

1024K 512K 512K 256K 256K

3200+
3400+
3700+

3000+
3200+
3400+

VCORE VCCA_1V2

VCORE

VCORE

frequency

L2 Cache

9.0X

1800
2000

10.0X

2200 11.0X

12.0X

2400

C1U10V3Y5VL (B)C618

X_C10U10V6Y5VL (B)C619

C6D8P50V3NPOR (B)C621

X_C10U10V6Y5VL (B)C623

CD22U16V3Y5VLC121CD22U16V3Y5VLC123
C10U10V6Y5VLC124
C6D8P50V3NPORC132
C8D2P50V3NPOLC135
C1U10V3Y5VLC142

2

TDP

89 W

81.5 W
62 W
35 W
62 W
89 W
55 W
30 W
65 W

CG

CG CG

AR

AX ­AW

AT

XX

AU
AV

2

Model#

H7DH7SH7

-AS X

-X

0.8 GHz1.2 V

NewCastle

2800+
3000+
3200+
3400+

CD1U25V3Y5VLC56

near PWM

CD1U25V3Y5VLC206

near CPU A21

CD1U25V3Y5VLC204

near CPU A18

V_Core Part DefinitionPackage T_Case

A3400 5ADA3400AEP5AR AD EA

P

Package

754pin、OuPGA

A
B

754pin、CuPGA Lidless

C

940pin、CuPGA
939pin、OuPGA

D

V_Core L2 Size

C

1.550

1.500

E
I

1.400 X

M

1.300

1.200

Q

1.150

S

T_Case
O
P

Y

69
70
95
100

℃

2

℃

3

℃

4
5

℃

Sempron

Paris

3100+

Palermo

3100+2800+

+5VVCORE

VCC_DDR

Title

Athlon64 OuPGA754 -- Power

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7145 0A

128K
256K
512K
1M

1

AR

of

1

632Friday, December 31, 2004

5

VCC_DDR

738467085

108

120

148

168223054627796

DR_MD[63..0]8

D D

C C

B B

DR_MD[63..0]

MSWEA#5,8

DDR_VREF5

C52
C1000P16V2X7RL

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

MSWEA#
DDR_VREF

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

102

NC4

VDD7

DDR DIMM
SOCKET

VSS0

VSS1

VSS2

VSS3

VSS4

3111826344250586674818993

VDD8

VDDQ0

VDDQ1

184
PIN

VSS5

VSS6

VSS7

VDDQ2

VSS8

VDDQ3

VSS9

VDDQ4

VSS10

104

VDDQ5

VSS11

112

VDDQ6

VSS12

100

128

VDDQ7

VSS13

116

136

VDDQ8

VSS14

124

143

VDDQ9

VDDQ10

VSS15

VSS16

132

156

VDDQ11

VSS17

139

164

VDDQ12

VSS18

145

4

172

1801582

VDDQ13

VSS19

152

160

VDDQ14

VSS20

NC(RESET#)

176

184

VDDID

VDDQ15

VDDSPD
CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10_AP

A11
A12
A13

BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VSS21

DDR1

DIMM-184_BLACK

157
158
71
163

5
14
25
36
56
67
78
86
47

103
48

43
41
130
37
32
125
29
122
27
141
118
115
167

59
52
113
92
91
181
182
183

44
45
49
51
134
135
142
144

16
17
137
138
76
75

173
10

21
111
65
154

97
107
119
129
149
159
169
177
140

MCS0#
MCS1#

DR_MDQS0
DR_MDQS1
DR_MDQS2
DR_MDQS3
DR_MDQS4
DR_MDQS5
DR_MDQS6
DR_MDQS7

MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12
MAA13

MEMBANKA0
MEMBANKA1

SMB_CLK
SMB_DATA

MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7

MCKE0
MCKE1
MSCASA#
MSRASA#

DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7

MCS0# 5,8
MCS1# 5,8

DR_MDQS0 8
DR_MDQS1 8
DR_MDQS2 8
DR_MDQS3 8
DR_MDQS4 8
DR_MDQS5 8
DR_MDQS6 8
DR_MDQS7 8

MAA[13..0]

MEMCLK_H5 5,8
MEMCLK_L5 5,8
MEMCLK_H0 5,8
MEMCLK_L0 5,8
MEMCLK_H7 5,8
MEMCLK_L7 5,8

MCKE0 5,8
MCKE1 5,8
MSCASA# 5,8
MSRASA# 5,8

MAA[13..0] 5,8

MEMBANKA0 5,8
MEMBANKA1 5,8

SMB_CLK 3,4,12,14,19,27
SMB_DATA 3,4,12,14,19,27

DR_DM[7..0]

DR_DM[7..0] 8

3

MSWEB#5,8

C53
X_CD1U16V3Y5VL

2

VCC_DDR

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

DR_MD0

2

DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9

DR_MD10
DR_MD12

DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25 MAB8
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

MSWEB#
DDR_VREF

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

102

NC4

VDD7

DDR DIMM
SOCKET

VSS0

VSS1

VSS2

VSS3

VSS4

3111826344250586674818993

VDD8

VSS5

VDDQ0

VSS6

VDDQ1

VDDQ2

VDDQ3

VDDQ4

184
PIN

VSS7

VSS8

VSS9

VSS10

104

VDDQ5

VSS11

112

VDDQ6

VSS12

100

128

VDDQ7

VSS13

116

136

VDDQ8

VDDQ9

VSS14

VSS15

124

143

VDDQ10

VSS16

132

156

VDDQ11

VSS17

139

164

VDDQ12

VSS18

145

172

1801582

VDDQ13

VSS19

152

160

VDDQ14

VSS20

VDDID

VDDQ15

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A10_AP

A11
A12
A13

BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC5

NC(RESET#)

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VSS21

DDR2

176

DIMM-184_BLACK

184

VDDSPD

157
158
71
163

DR_MDQS0

5

DR_MDQS1

14

DR_MDQS2

25

DR_MDQS3

36

DR_MDQS4

56

DR_MDQS5

67

DR_MDQS6DR_MD11

78

DR_MDQS7

86
47

103
48

A0

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141
118

MAB12

115

MAB13

167

MEMBAKB0

59

MEMBAKB1

52
113

SMB_CLK

92

SMB_DATA

91
181
182
183

44
45
49
51
134
135
142
144

16
17
137
138
76
75

173
10

MCKE0

21

MCKE1

111

MSCASB#

65

MSRASB#

154
97

107
119
129
149
159
169
177
140

MCS2#
MCS3#

MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7

MAB9
MAB10
MAB11

DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7

MCS2# 5,8
MCS3# 5,8

MAB[13..0]

MEMBAKB0 5,8
MEMBAKB1 5,8

VCC_DDR

MEMCLK_H4 5,8
MEMCLK_L4 5,8
MEMCLK_H1 5,8
MEMCLK_L1 5,8
MEMCLK_H6 5,8
MEMCLK_L6 5,8

MSCASB# 5,8
MSRASB# 5,8

MAB[13..0] 5,8

1

VCC_DDR

X_C4D7U10V5Y5VLC81

CD1U25V3Y5VLC98

X_C4D7U10V5Y5VLC114

C148 C1U10V3Y5VL

CD1U25V3Y5VLC168

C188 C1U10V3Y5VL

X_CD1U16V3Y5VLC211

CD1U25V3Y5VLC223

X_C4D7U10V5Y5VLC248

C262 C1U10V3Y5VL

X_C4D7U10V5Y5VLC279

CD1U25V3Y5VLC296
CD1U25V3Y5VLC307

DIMM1

VCC_DDR

CD1U16V2Y5VLC72
CD1U16V2Y5VLC116
CD1U16V2Y5VLC146

X_CD1U16V2Y5VLC185

CD1U16V2Y5VLC209
CD1U16V2Y5VLC267
CD1U16V2Y5VLC320

DIMM1 & DIMM2

VCC_DDR

C78 C1U10V3Y5VL

X_CD1U16V3Y5VLC94

CD1U25V3Y5VLC106
C175 C1U10V3Y5VL
C187 X_C1U10V3Y5VL
C207 X_C1U10V3Y5VL

CD1U25V3Y5VLC217

C266 C1U10V3Y5VL

CD1U25V3Y5VLC290
C308 C1U10V3Y5VL

DIMM2

DIMM1 SLAVE ADDRES S
= (1010000X)B = A0

VREF routed as 40~50 mils trace wide ,
Space>25 mils

VCC_DDR

C46
C1U10V3Y5VL

A A

R31
1KR2F

R32
1KR2F

C47
X_CD1U16V3Y5VL

DDR_VREF

C48
C1U10V3Y5VL

VCC_DDR

C4D7U10V5Y5VLC120

CD1U25V3Y5VLC141
C158 C1U10V3Y5VL
C176 C1U10V3Y5VL
C190 C1U10V3Y5VL

CD1U25V3Y5VLC189

CD1U25V3Y5VLC194
C202 C1U10V3Y5VL

X_C4D7U10V5Y5VLC184

CPU Side

VCC_DDR

X_CD1U16V3Y5VLC25
X_CD1U16V3Y5VLC37
X_CD1U16V3Y5VLC50

X_CD1U16V2Y5VLC76

CD1U16V2Y5VLC164
X_CD1U16V2Y5VLC221
X_CD1U16V2Y5VLC258
X_CD1U16V2Y5VLC286

CD1U25V3Y5VLC230

Trace Side

5

4

3

DIMM2 SLAVE ADDRES S
= (1010001X)B = A2

VCC_DDR +12V

VCC_DDR +3.3V

VCC_DDR

CD1U25V3Y5VLC300CD1U25V3Y5VLC99

X_CD1U16V2Y5VLC180

+5V

X_CD1U16V2Y5VLC101
X_CD1U16V2Y5VLC30

2

Title

DIMM1 / DIMM2

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD.

MS-7145 0A

1

of

732Friday, December 31, 2004

5

4

3

2

1

DR_DM[7..0]7

DR_MDQS[7..0]7

DR_MD[63..0]7

MAB[13..0]5,7
MAA[13..0]5,7

D D

C C

MSWEA#5,7

MCS0#5,7

MSCASA#5,7

MSWEB#5,7

MSRASB#5,7
MSRASA#5,7

B B

DR_DM[7..0]
DR_MDQS[7..0]
DR_MD[63..0]
MAB[13..0]
MAA[13..0]

RN65 8P4R-47R2

DR_MD59
DR_MD63
DR_MD58
DR_MD62

DR_MDQS7
DR_DM7
DR_MD57
DR_MD61

DR_MD56
DR_MD60
DR_MD51
DR_MD55 MAB12

DR_MD50
DR_MD54
DR_MDQS6
DR_DM6

MAA13
MAB13
DR_MD53
DR_MD52

DR_MD49
DR_MD48
DR_MD47
DR_MD46

DR_MD43
DR_MD42
DR_DM5
DR_MDQS5

MSWEA#
MCS0#
DR_MD41
MSCASA#

MSWEB#
DR_MD45

MSRASB#
MSRASA#

DR_DM4
DR_MDQS4
DR_MD37
DR_MD33

7 8
5 6
3 4
1 2

RN64 8P4R-47R2

7 8
5 6
3 4
1 2

RN62 8P4R-47R2

7 8
5 6
3 4
1 2

RN60 8P4R-47R2

7 8
5 6
3 4
1 2

RN57 8P4R-47R2

7 8
5 6
3 4
1 2

RN56 8P4R-47R2

7 8
5 6
3 4
1 2

RN54 8P4R-47R2

7 8
5 6
3 4
1 2

RN51 8P4R-47R2

7 8
5 6
3 4
1 2

RN50 8P4R-47R2

7 8
5 6
3 4
1 2

RN44 8P4R-47R2

7 8
5 6
3 4
1 2

MEMBANKA05,7

MEMBAKB05,7

MEMBANKA15,7

MEMBAKB15,7

MCS3#5,7
MCS1#5,7

MSCASB#5,7

MCS2#5,7

DR_MD44
DR_MD40
DR_MD39
DR_MD35

DR_MD38
DR_MD34
MEMBANKA0
MEMBAKB0

DR_MD36
DR_MD32
MEMBANKA1
MEMBAKB1

MAB0
MAB10
MAA10
MAA0

MAB2
DR_MD31
DR_MD30
DR_MD26

DR_MD28
MAA6
MAB6
MAA5

MAA3
MAB3
MAA4
MAB4

DR_DM3
DR_MDQS3

DR_MD29

MAB5
DR_MD24
DR_MD19
DR_MD23

MCS3#
MCS1#
MSCASB#
MCS2#

RN48 8P4R-47R2

7 8
5 6
3 4
1 2

RN47 8P4R-47R2

7 8
5 6
3 4
1 2

RN43 8P4R-47R2

7 8
5 6
3 4
1 2

RN42 8P4R-47R2

7 8
5 6
3 4
1 2

RN37 8P4R-47R2

7 8
5 6
3 4
1 2

RN33 8P4R-47R2

7 8
5 6
3 4
1 2

RN36 8P4R-47R2

7 8
5 6
3 4
1 2

RN34 8P4R-47R2

7 8
5 6
3 4
1 2

RN31 8P4R-47R2

7 8
5 6
3 4
1 2

RN52 8P4R-47R2

7 8
5 6
3 4
1 2

VTT_DDR

VTT_DDR

MAA8
MAB8
MAB7
DR_MD22

MAB9
MAB11
MAA11
DR_MD21

MAA7
DR_MD18
MAA9
DR_DM2

DR_MD17
DR_MDQS2
MAA12

DR_MD16
DR_MD20
MCKE0

MCKE05,7

DR_MD11

MCKE1

MCKE15,7

DR_MD10
DR_MD15
DR_MD14

DR_DM1
DR_MD13
DR_MDQS1
DR_MD12

DR_MD9
DR_MD8
DR_MD3
DR_MD6

DR_MD7
DR_MD2
DR_DM0DR_MD25
DR_MDQS0

DR_MD1
DR_MD5
DR_MD4
DR_MD0

MAA1
MAB1
MAA2
DR_MD27

RN30 8P4R-47R2

7 8
5 6
3 4
1 2

RN28 8P4R-47R2

7 8
5 6
3 4
1 2

RN29 8P4R-47R2

7 8
5 6
3 4
1 2

RN26 8P4R-47R2

7 8
5 6
3 4
1 2

RN25 8P4R-47R2

7 8
5 6
3 4
1 2

RN21 8P4R-47R2

7 8
5 6
3 4
1 2

RN19 8P4R-47R2

7 8
5 6
3 4
1 2

RN16 8P4R-47R2

7 8
5 6
3 4
1 2

RN14 8P4R-47R2

7 8
5 6
3 4
1 2

RN13 8P4R-47R2

7 8
5 6
3 4
1 2

RN39 8P4R-47R2

7 8
5 6
3 4
1 2

VTT_DDR

DR_MDQS[7..0]7

MDQS0

MD0
MD4
MD5
MD1

DM0
MD2
MD7
MD6

MD3
MD8
MD9
MD12

MDQS1
MD13
DM1
MD14

MDQS2
MD17
MD21
DM2

MD18

MD10
MD11
MD20
MD16

MD22
MD23
MD19
MD24

MD28
MD29
MD25
MDQS3

MD26
MD30
MD31
MD27

MDQS[7..0]5

DR_MD[63..0]7

MD[63..0]5

DR_DM[7..0]7

DM[7..0]5

MDQS[7..0]
DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
DR_DM[7..0]
DM[7..0]

R46 10R2
RN12 8P4R-10R2

1 2
3 4
5 6
7 8

RN15 8P4R-10R2

1 2
3 4
5 6
7 8

RN17 8P4R-10R2

1 2
3 4
5 6
7 8

R59 10R2
RN20 8P4R-10R2

1 2
3 4
5 6
7 8

RN27 8P4R-10R2

1 2
3 4
5 6
7 8

R62 10R2
RN22 8P4R-10R2

1 2
3 4
5 6
7 8

RN32 8P4R-10R2

1 2
3 4
5 6
7 8

RN35 8P4R-10R2

1 2
3 4
5 6
7 8

RN38 8P4R-10R2

1 2
3 4
5 6
7 8

DR_MDQS0

DR_MD0
DR_MD4
DR_MD5
DR_MD1

DR_DM0
DR_MD2
DR_MD7
DR_MD6

DR_MD3
DR_MD8
DR_MD9
DR_MD12

DR_MD15MD15

DR_MDQS1
DR_MD13
DR_DM1
DR_MD14

DR_MDQS2
DR_MD17
DR_MD21
DR_DM2

DR_MD18

DR_MD10
DR_MD11
DR_MD20
DR_MD16

DR_MD22
DR_MD23
DR_MD19
DR_MD24

DR_MD28
DR_MD29
DR_MD25
DR_MDQS3

DR_MD26
DR_MD30
DR_MD31
DR_MD27

MD38

RN45 8P4R-10R2

MD32
MD36
MD33

RN46 8P4R-10R2

MD37
MDQS4
DM4
MD34

MD42

MD35
MD39
MD40
MD44

MD45
MD41
MDQS5
DM5

MD43
MD46
MD47
MD48

MD49
MD52
MD53
DM6

MD54
MD50
MD55

MD60
MD56
MD61
MD57

DM7
MDQS7
MD62
MD58

MD59
MD63
DM3

R86 10R2

1 2
3 4
5 6
7 8

1 2
3 4
5 6
7 8

R100 10R2
RN49 8P4R-10R2

1 2
3 4
5 6
7 8

RN53 8P4R-10R2

1 2
3 4
5 6
7 8

RN55 8P4R-10R2

1 2
3 4
5 6
7 8

RN58 8P4R-10R2

1 2
3 4
5 6
7 8

R116 10R2

RN61 8P4R-10R2

1 2
3 4
5 6
7 8

RN63 8P4R-10R2

1 2
3 4
5 6
7 8

RN66 8P4R-10R2

1 2
3 4
5 6
7 8

R132 10R2
R129 10R2
R67 10R2

DR_MD38

DR_MD32
DR_MD36
DR_MD33

DR_MD37
DR_MDQS4
DR_DM4
DR_MD34

DR_MD42

DR_MD35
DR_MD39
DR_MD40
DR_MD44

DR_MD45
DR_MD41
DR_MDQS5
DR_DM5

DR_MD43
DR_MD46
DR_MD47
DR_MD48

DR_MD49
DR_MD52
DR_MD53
DR_DM6

DR_MD51MD51

DR_MDQS6MDQS6
DR_MD54
DR_MD50
DR_MD55

DR_MD60
DR_MD56
DR_MD61
DR_MD57

DR_DM7
DR_MDQS7
DR_MD62
DR_MD58

DR_MD59
DR_MD63
DR_DM3

VTT_DDR VCC_DDR

CD1U25V3Y5VLC63
C71 X_C1U10V3Y5VL
C75 C1U10V3Y5VL

X_CD1U16V3Y5VLC77
C79 X_C1U10V3Y5VL
C82 X_C1U10V3Y5VL

CD1U25V3Y5VLC89
C92 C1U10V3Y5VL
C97 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC100
C102 C1U10V3Y5VL
C105 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC108
C111 C1U10V3Y5VL
C113 X_C1U10V3Y5VL

CD1U25V3Y5VLC117
C122 C1U10V3Y5VL
C129 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC133
C137 C1U10V3Y5VL
C143 X_C1U10V3Y5VL

CD1U25V3Y5VLC147
C152 C1U10V3Y5VL
C154 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC159
C160 C1U10V3Y5VL
C163 X_C1U10V3Y5VL

CD1U25V3Y5VLC165
C167 C1U10V3Y5VL
C170 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC174
C177 X_C1U10V3Y5VL
C179 C1U10V3Y5VL

X_CD1U16V3Y5VLC183
C191 X_C1U10V3Y5VL

CD1U25V3Y5VLC197

VTT_DDR

VTT_DDR VCC_DDR VCC_DDRVTT_DDRVTT_DDR

X_CD1U16V3Y5VL (B)C616

CPU Side

A A

CPU to DIMM

CD1U25V3Y5VLC69

X_CD1U16V3Y5VLC70

C4D7U10V5Y5VLC65

CD1U25V3Y5VLC62
X_C4D7U10V5Y5VLC39
X_CD1U16V3Y5VLC44
X_CD1U16V3Y5VLC45

C23 X_C1U10V3Y5VL

CD1U25V3Y5VLC32

X_CD1U16V3Y5VLC205

CD1U25V3Y5VLC208
C4D7U10V5Y5VLC219
CD1U25V3Y5VLC235

X_CD1U16V3Y5VLC245

C261 X_C1U10V3Y5VL

CD1U25V3Y5VLC284

CD1U25V3Y5VLC302
X_CD1U16V3Y5VLC317
X_CD1U16V3Y5VLC329

CPU to DIMM

CD1U25V3Y5VLC257
C259 C1U10V3Y5VL
C264 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC268
C271 X_C1U10V3Y5VL
C276 C1U10V3Y5VL

X_CD1U16V3Y5VLC283
C287 X_C1U10V3Y5VL
C291 X_C1U10V3Y5VL

CD1U25V3Y5VLC297
C301 C1U10V3Y5VL
C305 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC306

VCC_DDR

C222 C1U10V3Y5VL
C225 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC229
C231 X_C1U10V3Y5VL
C232 C1U10V3Y5VL

CD1U25V3Y5VLC233
C237 X_C1U10V3Y5VL
C238 X_C1U10V3Y5VL

X_CD1U16V3Y5VLC241
C247 C1U10V3Y5VL
C251 X_C1U10V3Y5VL

DIMM2

C312 X_C1U10V3Y5VL
C314 C1U10V3Y5VL

CD1U25V3Y5VLC316

DIMM2

5

4

3

2

Title

DDR Terminator

Size Document Number Rev

Custom

Date: Sheet

MICRO-START INT'L CO.,LTD .

MS-7145 0A

832Friday, December 31, 2004

1

of

5

4

3

2

1

W25

W24
AA25
AA24
AB26
AA26

AC25
AC24
AD26
AC26

W30

AB29
AA29

AC29
AC28

W26

W29

W28

R26
U25
U24

U26

R29
R28

R30

U29

N29
D27

AE1
AE2

AB2
AC2

AB5
AB4

AA4

AG1
AH1

AC5
AC6

AH3

T26

V26

T30
T28

T29
V29

Y30
Y28

Y29

Y26

P29

E27

D8
D7
D5
D4
E4

G5
G4
H4

H5
H6
G1
G2
K5
K4

M4
N5
N4
P4
R4
P5
P6
P2
R2
T5
T4
U4

V4
W1
W2

Y4

AJ3

U12A

RS480-A13

U12B

F4

J4

L4

RS480-A13

HT_RXCAD15P
HT_RXCAD15N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD8P
HT_RXCAD8N

HT_RXCAD7P
HT_RXCAD7N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD0P
HT_RXCAD0N

HT_RXCLK1P
HT_RXCLK1N

HT_RXCLK0P
HT_RXCLK0N

HT_RXCTLP
HT_RXCTLN

HT_RXCALN
HT_RXCALP

PART 2 OF 6

GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N

GPP_RX0P/SB_RX2P
GPP_RX0N/SB_RX2N

GPP_RX1P/SB_RX3P
GPP_RX1N/SB_RX3N

PCIE I/F TO SLOT

GPP_RX2P
GPP_RX2N

GPP_RX3P
GPP_RX3N

SB_RX0P
SB_RX0N

PCIE I/F TO SB

SB_RX1P
SB_RX1N

PCE_ISET
PCE_TXISET

HT_TXCTLP
HT_TXCTLN

HT_TXCALP
HT_TXCALN

A7
B7
B6
B5
A5
A4
B3
B2
C1
D1
D2
E2
F2
F1
H2
J2
J1
K1
K2
L2
M2
M1
N1
N2
R1
T1
T2
U2
V2
V1
Y2
AA2

AD2
AD1

AA1
AB1

Y5
Y6

W5
W4

AF2
AG2

AC4
AD4

AH2
AJ2

R24
R25
N26
P26
N24
N25
L26
M26
J26
K26
J24
J25
G26
H26
G24
G25

L30
M30
L28
L29
J29
K29
H30
H29
E29
E28
D30
E30
D28
D29
B29
C29

L24
L25

F29
G29

M29
M28

B28
A28

PART 1OF6

PCIE I/F TO

HT_TXCAD15P
HT_TXCAD15N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD10P
HT_TXCAD10N

HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD8P
HT_TXCAD8N

HT_TXCAD7P
HT_TXCAD7N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD0P
HT_TXCAD0N

HT_TXCLK1P
HT_TXCLK1N

HT_TXCLK0P
HT_TXCLK0N

HYPER TRANSPORT CPU

I/F

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

VIDEO

GPP_TX0P/SB_TX2P

GPP_TX0N/SB_TX2N

GPP_TX1P/SB_TX3P

GPP_TX1N/SB_TX3N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

SB_TX0P
SB_TX0N

SB_TX1P
SB_TX1N

PCE_PCAL

PCE_NCAL

4

HT_CADIN_H15

HT_CADIN_L15

HT_CADIN_H14

HT_CADIN_L14

HT_CADIN_H13

HT_CADIN_L13

HT_CADIN_H12

HT_CADIN_L12

HT_CADIN_H11

HT_CADIN_L11

HT_CADIN_H10

HT_CADIN_L10

HT_CADIN_H9

HT_CADIN_L9

HT_CADIN_H8

HT_CADIN_L8

HT_CADIN_H7

HT_CADIN_L7

HT_CADIN_H6

HT_CADIN_L6

HT_CADIN_H5

HT_CADIN_L5

HT_CADIN_H4

HT_CADIN_L4

HT_CADIN_H3

HT_CADIN_L3

HT_CADIN_H2

HT_CADIN_L2

HT_CADIN_H1

HT_CADIN_L1

HT_CADIN_H0

HT_CADIN_L0

HT_CLKIN_H1
HT_CLKIN_L1

HT_CLKIN_H0
HT_CLKIN_L0

HT_CTLIN_H0
HT_CTLIN_L0

HT_TXCALP
HT_TXCALN

4 X 1 Lane PCI Express Interface for
General Purpose External Devices

SB_TX0P_C
SB_TX0N_C

SB_TX1P_C
SB_TX1N_C

PCE_PCAL
PCE_NCAL

R91 100R2F

GFX_TX0P 12
GFX_TX0N 12
GFX_TX1P 12
GFX_TX1N 12
GFX_TX2P 12
GFX_TX2N 12
GFX_TX3P 12
GFX_TX3N 12
GFX_TX4P 12
GFX_TX4N 12
GFX_TX5P 12
GFX_TX5N 12
GFX_TX6P 12
GFX_TX6N 12
GFX_TX7P 12
GFX_TX7N 12
GFX_TX8P 12
GFX_TX8N 12
GFX_TX9P 12
GFX_TX9N 12
GFX_TX10P 12
GFX_TX10N 12
GFX_TX11P 12
GFX_TX11N 12
GFX_TX12P 12
GFX_TX12N 12
GFX_TX13P 12
GFX_TX13N 12
GFX_TX14P 12
GFX_TX14N 12
GFX_TX15P 12
GFX_TX15N 12

R139 X_150R2F
R126 84D5R3F

HT_CADOUT_H[15..0]5
HT_CADOUT_L[15..0]5

D D

HT_CLKOUT_L15
HT_CLKOUT_H05

HT_CLKOUT_L05

C C

B B

A A

HT_CTLOUT_H05
HT_CTLOUT_L05

C272
CD1U25V3Y5VL

VCCA_1V2

R124 14KR2F
R127 8K66R2F

5

HT_CADOUT_H15
HT_CADOUT_L15
HT_CADOUT_H14
HT_CADOUT_L14
HT_CADOUT_H13
HT_CADOUT_L13
HT_CADOUT_H12
HT_CADOUT_L12
HT_CADOUT_H11
HT_CADOUT_L11
HT_CADOUT_H10
HT_CADOUT_L10
HT_CADOUT_H9
HT_CADOUT_L9
HT_CADOUT_H8
HT_CADOUT_L8

HT_CADOUT_H7
HT_CADOUT_L7
HT_CADOUT_H6
HT_CADOUT_L6
HT_CADOUT_H5
HT_CADOUT_L5
HT_CADOUT_H4
HT_CADOUT_L4
HT_CADOUT_H3
HT_CADOUT_L3
HT_CADOUT_H2
HT_CADOUT_L2
HT_CADOUT_H1
HT_CADOUT_L1
HT_CADOUT_H0
HT_CADOUT_L0

R103 49D9R2F
R102 49D9R2F

GFX_RX0P12
GFX_RX0N12
GFX_RX1P12
GFX_RX1N12
GFX_RX2P12
GFX_RX2N12
GFX_RX3P12
GFX_RX3N12
GFX_RX4P12
GFX_RX4N12
GFX_RX5P12
GFX_RX5N12
GFX_RX6P12
GFX_RX6N12
GFX_RX7P12
GFX_RX7N12
GFX_RX8P12
GFX_RX8N12
GFX_RX9P12
GFX_RX9N12
GFX_RX10P12
GFX_RX10N12
GFX_RX11P12
GFX_RX11N12
GFX_RX12P12
GFX_RX12N12
GFX_RX13P12
GFX_RX13N12
GFX_RX14P12
GFX_RX14N12
GFX_RX15P12
GFX_RX15N12

A_RX0P13
A_RX0N13

A_RX1P13
A_RX1N13

HT_RXCALN
HT_RXCALP

A_RX0P
A_RX0N

A_RX1P
A_RX1N

PCIE_ISET
PCIE_TXISET

HT_CADIN_H[15..0] 5
HT_CADIN_L[15..0] 5

Stuff for RS480

VCC2_5

HT_CLKIN_H1 5HT_CLKOUT_H15
HT_CLKIN_L1 5

HT_CLKIN_H0 5
HT_CLKIN_L0 5

HT_CTLIN_H0 5
HT_CTLIN_L0 5

PCIEX-TXISET will help with our chip transmitted swing.
PCIEX-ISET can help with L1/L0 issues,
RCALN can help with some wirebond reflection.
Every resistor could help with one issue and should not
hurt other issues.

PCI_TXISET = 8.5K
PCI_ISET = 14K
PCE_PCAL = do not touch
PCE_NCAL = 84 ohms

R111 1KR2F

C282
CD1U16V2Y5VL

+1.8V_S0

L12 X_0R5
CP7 X_CP

1 2

C293
X_C10U10V5Y5VL

R108 1KR2F

CD47U10V3X7RLC243
CD47U10V3X7RLC315

1 X 16 Lane Interface for External General

VCCA_1V2

CD1U16V3X7RLC657
CD1U16V3X7RLC656

CD1U16V3X7RLC655
CD1U16V3X7RLC658

A_TX0P
A_TX0N

A_TX1P
A_TX1N

A_TX0P 13
A_TX0N 13

A_TX1P 13
A_TX1N 13

1 X 2 Lane Alink Express to IXP

Miscellaneous PCI Express Signals

C318
CD1U25V3Y5VL

3

SMEM_VREF

R113
1KR2F

MPVDD_PLL

C303
C1U10V3Y5VL

MEM_CAP1
MEM_CAP2

MEM_VMODE

SMEM_VREF
MPVDD_PLL

U12C

AF17

MEM_A0

AK17

MEM_A1

AH16

MEM_A2

AF16

MEM_A3

AJ22

MEM_A4

AJ21

MEM_A5

AH20

MEM_A6

AH21

MEM_A7

AK19

MEM_A8

AH19

MEM_A9

AJ17

MEM_A10

AG16

MEM_A11

AG17

MEM_A12

AH17

MEM_A13

AJ18

MEM_A14

AG26

MEM_DM0

AJ29

MEM_DM1

AE21

MEM_DM2

AH24

MEM_DM3

AH12

MEM_DM4

AG13

MEM_DM5

AH8

MEM_DM6

AE8

MEM_DM7

AF25

MEM_DQS0P

AH30

MEM_DQS1P

AG20

MEM_DQS2P

AJ25

MEM_DQS3P

AH13

MEM_DQS4P

AF14

MEM_DQS5P

AJ7

MEM_DQS6P

AG8

MEM_DQS7P

AG25

MEM_DQS0N

AH29

MEM_DQS1N

AF21

MEM_DQS2N

AK25

MEM_DQS3N

AJ12

MEM_DQS4N

AF13

MEM_DQS5N

AK7

MEM_DQS6N

AF9

MEM_DQS7N

AE17

MEM_RAS#

AH18

MEM_CAS#

AE18

MEM_WE#

AJ19

MEM_CS#

AF18

MEM_CKE

AK16

MEM_CKP

AJ16

MEM_CKN

AE28

MEM_CAP1

AJ4

MEM_CAP2

AJ20

MEM_VMODE

AK20

MEM_VREF

AJ15

MPVDD

AJ14

MPVSS

RS480-A13

Document Number: PA_RS480F1

2

PART 3 OF 6

MEM_A I/F

AF28

MEM_DQ0

AF27

MEM_DQ1

AG28

MEM_DQ2

AF26

MEM_DQ3

AE25

MEM_DQ4

AE24

MEM_DQ5

AF24

MEM_DQ6

AG23

MEM_DQ7

AE29

MEM_DQ8

AF29

MEM_DQ9

AG30

MEM_DQ10

AG29

MEM_DQ11

AH28

MEM_DQ12

AJ28

MEM_DQ13

AH27

MEM_DQ14

AJ27

MEM_DQ15

AE23

MEM_DQ16

AG22

MEM_DQ17

AF23

MEM_DQ18

AF22

MEM_DQ19

AE20

MEM_DQ20

AG19

MEM_DQ21

AF20

MEM_DQ22

AF19

MEM_DQ23

AH26

MEM_DQ24

AJ26

MEM_DQ25

AK26

MEM_DQ26

AH25

MEM_DQ27

AJ24

MEM_DQ28

AH23

MEM_DQ29

AJ23

MEM_DQ30

AH22

MEM_DQ31

AK14

MEM_DQ32

AH14

MEM_DQ33

AK13

MEM_DQ34

AJ13

MEM_DQ35

AJ11

MEM_DQ36

AH11

MEM_DQ37

AJ10

MEM_DQ38

AH10

MEM_DQ39

AE15

MEM_DQ40

AF15

MEM_DQ41

AG14

MEM_DQ42

AE14

MEM_DQ43

AE12

MEM_DQ44

AF12

MEM_DQ45

AG11

MEM_DQ46

AE11

MEM_DQ47

AJ9

MEM_DQ48

AH9

MEM_DQ49

AJ8

MEM_DQ50

AK8

MEM_DQ51

AH7

MEM_DQ52

AJ6

MEM_DQ53

AH6

MEM_DQ54

AJ5

MEM_DQ55

AG10

MEM_DQ56

AF11

MEM_DQ57

AF10

MEM_DQ58

AE9

MEM_DQ59

AG7

MEM_DQ60

AF8

MEM_DQ61

AF7

MEM_DQ62

AE7

MEM_DQ63

MEM_COMPP
MEM_COMPN

Title

Size Document Number Rev

Date: Sheet

AH5
AD30

ATI RS480 North Bridge -- HT / PCIE / SIDE MEM

Custom

MS-7145 0A

U11

1

XX1

MSI

DDR

HEATSINK

Don't stuff for
RS480 and RX480

MBM_COMPP
MBM_COMPN

MICRO-START INT'L CO.,LTD.

R120 X_49D9R2F
R87 X_49D9R2F

C244
X_CD1U25V3Y5VL

1

2

XX2

VCC2_5

of

932Friday, December 31, 2004