MSI MS-7144 Schematics
5
4
3
2
1
MS-7144 VER:100
PageTitle
Cover Sheet 1
*AMD PGA 754 K8-Processor (DDR 400)
D D
*VIA K8T800B / K8M800
*VIA VT8237R
(AGP 8X / VLink 8X)
*Winbond 83627THF LPC I/O
*8201CL 100/10 Bit LAN Support
*USB 2.0 support (integrated into VT8237R)
*ALC655 6 channel S/W Audio
*DDR DIMM * 2
C C
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 4
B B
Block Diagram 2
GPIO SPEC
3
AMD K8 -> 754 PGA Socket 4,5,6
Clock Synthesizer (ICS950410AF)
System Memory
DDR I DIMM 1 & 2
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T800B/K8M800 (HT)
K8 Vcore Power
AGP SLOT 8X
VT8237R
PCI Connectors * 4
ALC655 6 channel S/W Audio
IDE ATA 66/100 Connectors * 2
Front and Rear USB Port
LPC I/O W83627THF& ROM & Floppy&Fan
KeyBoard/Mouse/LPT/COM Connectors
10/100 LAN & VGA
ACPI Power CONTROLLER (MS-6)
System Regulator&Front Panel
Decoupling Cap.
Power Generation
History
OPTION PARTS
7
8
9
10
11,12,13
14
15
16,17,18
19,20
21
22
23
24
25
26
27
28
29
30
31
32
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Cover Sheet
MS-7144
1
Last Revision Date:
Wednesday, March 02, 2005
Sheet
Rev
100
132
of
5
Block Diagram
4
3
2
1
D D
CPUCLK+ & CPUCLK-(100/133/166/200)
AMD K8 Socket 754
HCLK+ & HCLK-(100/133/166/200) / GCLK(66)
DDR400
VIA
HT
VLINK
Dual ATA 100/133
IDE Slot
==>ATA66,100,133 *2
SYSTEM CLOCK
Synthesizer
C C
AGPCLK(66)
A
G
P
AGP 8X /Fast Write
S
L
O
T
K8T800B/K8M800
VCLK(66) / OSC(14) / PCISB(33) / USBCLK(48) / APICCLK(14)
PCICLK[1~4]
PCI-33
DDR I * 2
B B
A A
AC_14(14)
SIOPCLK(33)/SIO48M(48)
5
4 PCI Slots
AC97 => S/W Audio
ALC655 / 6 channel
AC97
SERIAL ATA *2
4
VT8237R
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *4 ,
Back-Port *4
3
USB
LPC BUS
MII
10/100 LAN
RTL8201CL
SUPER I/O
W83627THF
2
LPC
BUS
ROM
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
1
Block Diagram
MS-7144
Last Revision Date:
Sheet
Rev
100
Wednesday, March 02, 2005
232
of
5
4
3
2
1
GPIO FUNCTION
VT8237 GPIO Function Define
PIN NAME
D D
GPO0 (VSUS33)
GPO1/SUSA#(VSUS33)
GPO2/SUSB#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/SLP#
GPO8/GPI8/IPBIN0
GPO9/GPI9/IPBIN1
C C
GPO10/GPI10/IPBRDFR
GPO11/GPI11/IPBRDCK
GPO12/GPI12/INTE#
GPO13/GPI13/INTF#
GPO14/GPI14/INTG#
GPO15/GPI15/INTH#
GPO16/SA16/STRAP
GPO17/SA17/STRAP
GPO18/SA18/STRAP
GPO19/SA19/STRAP
B B
GPO20/GPI20
/ACSDIN2/PCS0#/EI
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/IOR#
GPO23/GPI23/DPSLP
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
VIDSEL
GPO29/GPI29/
A A
VRDSLP
GPO30/GPI30/GPIOD
GPO31/GPI31/GPIOE
5
NA
NA
SUSB#
SUSST#
NA (Exteranl Pull up to 3VDUAL)
NA (Exteranl Pull up to VCC3)
NA (Exteranl Pull up to VCC3)
LDTSTOP#
NA
NA
NA
NA
VSET0
VSET1
VSET2
NA
LDT Freq Strapping Bit0
LDT Freq Strapping Bit1
LDT Width (Low=8 Bit)
Fast Command (Low=Disable)
POWERF1
POWERF2
NA
ROMLOCK
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
NA
NA
NA
PIN NAME
GPI0
GPI1
GPI2/EXTSMI#
GPI3/RING#
GPI4/LID#
GPI5/BATLOW#
NA
GPI6/AGPBZ#
GPI7/REQ#5
GPI16/INTRUDER#
GPI17/CPUMISS
NA
NA
NA
GPI18/AOLGP1/THRM#
GPI19/IORDY
S/IO GPIO Function Define
PIN NAME Function define
GPBX/GP13
GPAY/GP15
GPAS1/GP10
GPAS2/GP17
GPAX/GP12
GPBY/GP14
GPBS1/GP11
GPBS2/GP16
4
Function defineFunction define
(Exteranl Pull up to VBAT)NA
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
(Exteranl Pull up to 3VDUAL)
POWERF3
(Exteranl Pull up to 3VDUAL)
(Exteranl Pull up to VBAT)
(Exteranl Pull up to 3VDUAL)
THRM#
(Exteranl Pull up to VCC3)NA
LED#4
LED#2
LED1
LED4
LED#3
LED#1
LED2
LED3
3
PCI Routing
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 4
PCI SLOT 5
Giga-Bit
LAN
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
INT#D
INT#A
INT#B
INT#C
INT#B
INT#C
INT#D
INT#A
INT#A AD22 GLAN_PCLK
2
IDSEL
AD16
AD17
AD18
AD19
AD21
REQ#/GNT#
PREQ#6
PGNT#6
PREQ#3
PGNT#3
PREQ#4
PGNT#4
PREQ#7
PGNT#7
PREQ#8
PGNT#8
PREQ#1
PGNT#1
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
CLOCK
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GPIO Spec.
MS-7144
Last Revision Date:
Sheet
Wednesday, March 02, 2005
332
1
Rev
100
of
5
4
3
2
1
VREF routed as 40~50 mils trace wide ,
Space>25 mils
C64
D D
C C
B B
A A
DDR_VREF8
MD[63..0]10
DM[7..0]10
-MDQS[7..0]10
R60 15R1%
R59 15R1%
5
VDD_25_SUS
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
C1000P50X
C52
MEMZN
MEMZP
X_C1000P50N
AE13
AG12
D14
C14
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
U2B
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MD63
A16
B15
A12
B11
A17
A15
C13
A11
A10
C11
AC1
AC3
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
A13
AA1
AG1
AH7
AH13
A14
AB1
AJ2
AJ8
AJ13
B9
C7
A6
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
W2
Y1
R1
A7
C2
H1
T1
A8
D1
J1
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
MEMORY INTERFACE
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17 MAA3
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
RSVD_MEMADDA15
RSVD_MEMADDA14
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
MCKE0
MCKE1
-MCS3
-MCS2
-MCS1
-MCS0
MCKE0 8,9
MCKE1 8,9
MEMCLK_H7 8,9
MEMCLK_L7 8,9
MEMCLK_H6 8,9
MEMCLK_L6 8,9
MEMCLK_H5 8,9
MEMCLK_L5 8,9
MEMCLK_H4 8,9
MEMCLK_L4 8,9
MEMCLK_H1 8,9
MEMCLK_L1 8,9
MEMCLK_H0 8,9
MEMCLK_L0 8,9
-MCS3 8,9
-MCS2 8,9
-MCS1 8,9
-MCS0 8,9
-MSRASA 8,9
-MSCASA 8,9
-MSWEA 8,9
MEMBANKA1 8,9
MEMBANKA0 8,9
MAA[13..0] 8,9
-MSRASB 8,9
-MSCASB 8,9
-MSWEB 8,9
MEMBAKB1 8,9
MEMBAKB0 8,9
MAB[13..0] 8,9
CADIP[0..15]11
CLKIP111
CLKIN111
CLKIP011
CLKIN011
VLDT0
R21 49.9R1%
CTLIP011
CTLIN011
3
R28 49.9R1%
VDD_12_A
X_C0.22U16Y
VDD_12_A
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
C156
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP2
CADIP1
CADIP0
CTLIP1
CTLIN1
C0.22U16Y
C186
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
T29
R29
C0.22U16Y
U2A
N12-7540031-L06
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
X_C0.22U16Y
C155
C166
HYPER TRANSPORT - LINK0
2
C174
C0.22U16Y
L0_CADOUT_H15
L0_CADOUT_H14
L0_CADOUT_H13
L0_CADOUT_H12
L0_CADOUT_H11
L0_CADOUT_H10
C256
C0.22U16Y
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CADOUT_L15
L0_CADOUT_L14
L0_CADOUT_L13
L0_CADOUT_L12
L0_CADOUT_L11
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C167
C0.22U16Y
VLDT0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
CADOP15
N26
CADON15
N27
CADOP14
L25
CADON14
M25
CADOP13
L26
CADON13
L27
CADOP12
J25
CADON12
K25
CADOP11
G25
CADON11
H25
CADOP10
G26
CADON10
G27
CADOP9
E25
CADON9
F25
CADOP8
E26
CADON8
E27
CADOP7
N29
CADON7
P29
CADOP6
M28
CADON6
M27
CADOP5
L29
CADON5
M29
CADOP4
K28
CADON4
K27
CADOP3
H28
CADON3
H27
CADOP2
G29
CADON2
H29
CADOP1
F28
CADON1
F27
CADOP0
E29
CADON0
F29
CLKOP1
J26
J27
J29
K29
N25
P25
P28
P27
CLKON1
CLKOP0
CLKON0
CTLOP0
CTLON0
CLKOP1 11
CLKON1 11
CLKOP0 11
CLKON0 11
CTLOP0 11
CTLON0 11
Micro Star Restricted Secret
K8 DDR & HT
MS-7144
Last Revision Date:
Sheet
1
VLDT0 5
C58
C4.7U10Y0805
CADOP[0..15] 11
CADON[0..15] 11CADIN[0..15]11
Rev
100
Wednesday, March 02, 2005
432
of
5
D D
4
C53
X_C1000P50N
VDDIO_SENSE
3
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
VCCA_PLL regulator circuit.
VDDA_25
VDDA_25
C C
-LDTSTOP
R22
1KR
VLDT04
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
HDT Test Port Signal .
B B
DBREQ_L
DBRDY
TCK
TMS
TDI
TRST_L
NC_AH18
NC_AJ18
NC_AG18
A A
NC_AG17
NC_D18
NC_B19
NC_C19
NC_D20
5
R23 X_1KR
R24 X_1KR
1 2
3 4
5 6
7 8
RN50 X_8P4R-1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
VDDA_25
C51
C4.7U10Y0805
RN20
8P4R-1KR
8P4R-1KR
RN47
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
traces to exit ball field) and 500 mils long.
C60
C1000P50X
NC_C18
NC_A19
NC_C21
TDO
CPU_VDDA_25
C63
X_C1000P50N
VDD_25_SUS
1 2
3 4
5 6
7 8
C59
C1000P50X
VDDA_25 VDD_25_SUS
Differential , "10:10:5:10:10" .
Near CPU in 0.5" .
8P4R-1KR
RN54
C4.7U10Y0805
-CPURST28
-LDTSTOP11,18
COREFB_H14
COREFB_L14
CPUCLK0_H7
CPUCLK0_L7
3
C73
VTT_DDR_SUS
FB1 300L700m_250_0805
CPU_GD27
VLDT0
R20 44.2R1%
R19 44.2R1%
4
C61
C0.22U16Y
CPU_GD
L0_REF1
L0_REF0
C67 C0.039U16X
C66 C0.039U16X
VDDIO_SENSE
169R1%
R31
R26 820R
R29 820R
5 6
7 8
C71
C1000P50X
RN18
X_8P4R-1KR
1 2
3 4
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
AH25
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
C16
AG15
AH17
C15
E20
E17
B21
A21
C18
A19
A28
AJ28
AE23
AF23
AF22
AF21
AA2
AG2
B18
AH1
AE21
C20
AG4
AG6
AE9
AG9
A23
A24
B23
C1
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
J3
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
THERMDC_CPU
FB2
X_120S/0603
U2C
THERMTRIP_L
THERMDA
THERMDC
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
2
THRM#
A20
THERMDA_CPU
A26
THERMDC_CPU
A27
VID4
AG13
AF14
AG14
AF15
AE15
AG18
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
VID4 14
VID3
VID3 14
VID2
VID2 14
VID1
VID1 14
VID0
VID0 14
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
FBCLKOUT_H
R30
80.6R1%
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
THRM# 27
THERMDA_CPU 24
THERMDC_CPU 24
LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )
K8 HDT & MISC
MS-7144
Last Revision Date:
Wednesday, March 02, 2005
Sheet
532
1
of
Rev
100
5
U2E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
AA8
AB9
AA10
AE16
G20
W20
AA20
AC20
AE20
AG20
AJ20
M21
AD21
AG21
G22
AG29
AA22
AC22
AG22
AH22
AJ22
AB23
AD23
AG23
G24
W24
AA24
AC24
AG24
AJ24
M26
AD26
AF26
AH26
G28
AB17
AD17
G18
AA18
AC18
AB19
AD19
AF19
D2
VSS10
AF2
VSS11
W6
VSS12
Y7
VSS13
VSS14
VSS15
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
VSS20
J18
VSS21
VSS22
R20
VSS23
U20
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
D21
VSS31
F21
VSS32
H21
VSS33
K21
VSS34
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
VSS40
VSS41
B22
VSS42
E22
VSS43
VSS44
J22
VSS45
L22
VSS46
N22
VSS47
R22
VSS48
U22
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
D23
VSS56
F23
VSS57
H23
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
VSS64
VSS65
VSS66
E24
VSS67
VSS68
J24
VSS69
N24
VSS70
R24
VSS71
U24
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
B25
VSS78
C25
VSS79
B26
VSS80
D26
VSS81
H26
VSS82
VSS83
T26
VSS84
Y26
VSS85
VSS86
VSS87
VSS88
C27
VSS89
B28
VSS90
D28
VSS91
VSS92
F15
VSS187
H15
VSS188
VSS206
VSS207
B16
VSS208
VSS209
VSS210
VSS211
D19
VSS212
F19
VSS213
H19
VSS214
K19
VSS215
Y19
VSS216
VSS217
VSS218
VSS219
J20
VSS220
L20
VSS221
N20
VSS222
GROUND
5
D D
C C
B B
A A
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
VCORE
AC15
AB14
AA15
AB16
AA17
AC17
AE17
AB18
AD18
AG19
AC19
AA19
AB20
AD20
W21
AA21
AC21
AB22
AD22
W23
AA23
AC23
AB24
AD24
AH24
AE25
GNDGND
H18
B20
E21
H22
H24
F26
V10
G13
K14
Y14
G15
H16
K16
Y16
G17
F18
K18
Y18
E19
G19
F20
H20
K20
M20
P20
T20
V20
Y20
G21
N21
R21
U21
F22
K22
M22
P22
T22
V22
Y22
E23
G23
N23
R23
U23
B24
D24
F24
K24
M24
P24
T24
V24
Y24
K26
P26
V26
U2D
L7
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
J23
VDD7
VDD8
VDD9
N7
VDD10
L9
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
J15
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
J17
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD39
VDD38
J19
VDD37
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
J21
VDD51
L21
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
L23
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92
POWER
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
4
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
3
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,
2 in middle of HT link, and 12 along bottom left side of
Claw-hammer.
VCORE
C72
C428
C436
C70
X_C6.8P50N
C46
C114
C8.2P50N
C110
C0.22U16Y
<nopop>
X_C6.8P50N
C99
X_C0.22U16Y
X_C0.22U16Y
C122
C115
C8.2P50N
X_C6.8P50N
GND
C111
C0.22U16Y
C125
X_C0.22U16Y
C123
C0.22U16Y
X_C6.8P50N
C178
C4.7U10Y0805
Place between DIMN1 & 2
VDD_25_SUS
C138
C147
C0.1U50Y
C0.1U50Y
VDD_25_SUS
C91
C56
<nopop>
C1U10Y
C429
<nopop>
X_C1U10Y
C102
C0.1U50Y
<nopop>
X_C6.8P50N
C140
C0.1U50Y
X_C1U10Y
C142
C0.1U50Y
GND
C437
C432
LAYOUT: Place beside processor.
C33
C152
C160
<nopop>
C1U10Y
C105
C0.22U16Y
C106
C180P50N
C1000P50X
C109
C180P50N
C129
C180P50N
3
C4.7U10Y0805
VCORE
C4.7U10Y0805
In CPU.
C1U16Y0805
C159
C134
C0.22U16Y
C126
X_C0.22U16Y
X_C1U16Y0805
C164
2
VDD_25_SUS VTT_DDR_SUS
C154
C197
C176
C1U10Y
C0.22U16Y
X_C1U16Y0805
GND
C108
C0.22U16Y
C135
C8.2P50N
2
C85
X_C0.22U16Y
<nopop>
C0.22U16Y
C435
C1U10Y
VTT_DDR_SUS
C424
X_C0.1U50Y
VDD_25_SUS
C431
C426
C1U10Y
BACK
GND
C425
X_C0.1U50Y
GND
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C1U10Y
K8 POWER & GND
MS-7144
1
VDD_25_SUSVCORE
C563
C0.1U50Y
Last Revision Date:
Sheet
1
Rev
100
Wednesday, March 02, 2005
of
632
5
Clock Synthesizer
D D
U9
CLKVCC3
C285 C0.1U50Y
CLKVCC3
CLKVCC3
C287 C0.1U50Y
CLKVCC3
C288 X_C0.1U50Y
CLKVCC3
C290 C0.1U50Y
CLKVCC3
C310 C0.1U50Y
CLKVCC3
CLKVCC3
C311 C0.1U50Y
CLKVCC3
C312 C0.1U50Y
CLKVDDA
C286 C0.1U50Y
CLKVCC3
R151 10KR
C C
ICS950410AF_SSOP48
46
VDDREF
47
GND
2
VDDHTT
5
GND
9
VDDPCI
10
GND
16
VDDPCI
15
GND
19
VDDPCI
20
GND
28
AVDD48
29
GND
40
VDDCPU
37
GND
36
VDDCPU
33
GND
44
VDDA
43
GND
31
PD#
32
Turbo#
FS0/REF0
FS1/REF1
RESET#
XIN
XOUT
ModeA/HTT66_0
ModeB/PCI33_8/HTT66_1
PCI33_9/HT66_2
PCI33_11/HT66_3
FS2/PCI33_10
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_4
PCI33_5
PCI33_6
PCI33_7
FS3/48M
24_48MHZ/SEL
SDATA
SCLK
CPUCLK8T0
CPUCLK8C0
CPUCLK8T1
CPUCLK8C1
CPUCLK8T2
CPUCLK8C2
1
48
45
3
4
6
7
8
11
12
13
14
17
18
21
22
23
24
30
27
26
25
42
41
39
38
35
34
4
FS0
FS1
CLKX1
CLKX2
MODEA
MODEB
FS2
SEL_24 USBCLK_SB
SMBDATA1
SMBCLK1
R135 33R
R150 33R
R126 X_33R
For K8M800
7 8
5 6
3 4
RN69 8P4R-22R
1 2
7 8
5 6
3 4
RN70 8P4R-22R
1 2
7 8
5 6
3 4
1 2
RN71 8P4R-22R
R127 33R
R141 33R
R137 15R1%
R138 15R1%
R139 15R1%
R140 15R1%
For K8T800 Pro
AC_14
APICCLK
GUICLK
C308 C27P50N
Y2 14.318MHZ32P_D
C305 C27P50N
VCLK
GCLK_NB
GCLK_SLOT
SIOPCLK
LPC_PCLK
PCICLK5
PCICLK4
PCICLK3
PCICLK1
PCICLK2
SBPCLK
SIO48MFS3
CPUCLK0_H
CPUCLK0_L
HCLK+
HCLK-
CPUCLK0_H 5
CPUCLK0_L 5
HCLK+ 11
HCLK- 11
AC_14 21
APICCLK 17,18
GUICLK 12
CLK_RESET# 27,28
VCLK 18
GCLK_NB 12
GCLK_SLOT 15
SIOPCLK 24
LPC_PCLK 24
PCICLK5 20
PCICLK4 20
PCICLK3 20
PCICLK1 19
PCICLK2 19
SBPCLK 18
SIO48M 24
USBCLK_SB 16
SMBDATA1 8,17,27
SMBCLK1 8,17,27
3
VCLK
C322 C10P50N
GCLK_NB
C323 C10P50N
GCLK_SLOT
C324 C10P50N
SIO48M
USBCLK_SB
AC_14
APICCLK
GUICLK
FS1
C279 C10P50N
C280 C10P50N
C284 X_C10P50N
C321 X_C10P50N
C274 X_C10P50N
C294 X_C10P50N
For K8M800
SIOPCLK
LPC_PCLK
PCICLK5
PCICLK4
PCICLK3
PCICLK1
PCICLK2
SBPCLK
HCLK+
HCLK-
CN10
7 8
5 6
3 4
1 2
8P4C-10P50N
CN11
7 8
5 6
3 4
1 2
8P4C-10P50N
C277 C10P50N
C278 C10P50N
For K8T800 Pro
2
ICS950410AF
Strapping CPU
FS0FS2FS3
FS1
0000
000
00 0
00
000
00
00
0
***
1
11
11
111
11
11 1
1
11
1
11
11
111
000
00
00
0
00
0
111
1111
ModeA ModeB
***
00
01
10
11
HTTCLK0
ModeA In
PCICLK7 PCICLK8 PCICLK9 PCICLK10
ModeA In
MHz
100.90
133.90
1
168.00
202.00
100.20
133.50
166.70
200.40
150.00
180.00
210.00
240.00
270.00
233.33
266.67
0
300.00
Pin6 Pin7
HTTCLK1 HTTCLK2 PCICLK10
HTTCLK1 HTTCLK2 HTTCLK3
PCICLK8 PCICLK9 PCICLK10
HTT
MHz
PCI
MHz
67.27 33.63
66.95
67.20
67.33
66.80
66.75
66.68
66.80
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
33.48
33.60
33.67
33.40
33.38
33.34
33.40
33.00
33.00
35.00
30.00
33.75
33.33
33.33
37.50
Pin8 Pin11
1
"FS0~FS3" are all internal
pull-up via 100K ohm ..
FS0
FS2
FS1
FS3
ModeA,B=0:0 ( Set Pin 7,8 clock
-> 66 MHz Pin11->33Mhz )
MODEB
MODEA
"24_48MHZ/SEL" Freq.-Out select
pin => Low->48MHz , Hi->24MHz .
( Internal pull-up via 100K ohm )
SEL_24
R149 10KR
R152 10KR
R136 10KR
R128 10KR
R166 10KR
R165 10KR
R142 10KR
CLKVCC3
VCC3
FB14 X_120S/0805
B B
CP10
X_COPPER
For EMI
VCC3 VCC
C364 C0.1U50Y
A A
CLKVDDA
C281
C1U16Y0805
C295
X_C0.1U50Y
VCC3
C291
C0.1U50Y
FB15 X_120S/0805
CP11
X_COPPER
C301
C1U16Y0805
CLKVCC3
C289
C0.1U50Y
VCC3
Decoupling Cap for CPU Clock
CPUCLK0_H
CPUCLK0_L
C309 C0.1U50Y
Near CK-Gen in 0.5" .
C275 C8.2P50N
C276 C8.2P50N
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
5
4
3
2
http://www.msi.com.tw
Clock Synthesizer
MS-7144
Last Revision Date:
Sheet
1
Wednesday, March 02, 2005
732
Rev
100
of
5
VDD_25_SUS
4
SYSTEM MEMORY
3
2
VDD_25_SUS
1
156
164
VDDQ11
VDDQ12
VSS17
VSS18
139
145
172
VDDQ13
PIN
VSS19
152
180
160
82
15
VDDQ14
VDDQ15
A10_AP
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
DDR1
DIMM-184_green
176
N13-1840061-K06
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
-MCS0
157
-MCS1
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
103
MAA0
48
MAA1
43
MAA2
41
MAA3
130
MAA4
37
MAA5
32
MAA6
125
MAA7
29
MAA8
122
MAA9
27
MAA10
141
MAA11
118
MAA12 MAB12
115
MAA13
167
59
52
113
SMBCLK1
92
SMBDATA1
91
181
182
183
44
45
49
51
134
135
142
144
MEMCLK_H5
16
MEMCLK_L5
17
MEMCLK_H0
137
MEMCLK_L0
138
MEMCLK_H7
76
MEMCLK_L7
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_DM0
97
DR_DM1
107
DR_DM2
119
DR_DM3
129
DR_DM4
149
DR_DM5
159
DR_DM6
169
DR_DM7
177
140
-MCS0 4,9
-MCS1 4,9
-DR_MDQS0 9,10
-DR_MDQS1 9,10
-DR_MDQS2 9,10
-DR_MDQS3 9,10
-DR_MDQS4 9,10
-DR_MDQS5 9,10
-DR_MDQS6 9,10
-DR_MDQS7 9,10
MAA[13..0]
MEMBANKA0 4,9
MEMBANKA1 4,9
SMBCLK1 7,17,27
SMBDATA1 7,17,27
MEMCLK_H5 4,9
MEMCLK_L5 4,9
MEMCLK_H0 4,9
MEMCLK_L0 4,9
MEMCLK_H7 4,9
MEMCLK_L7 4,9
MCKE0 4,9
MCKE1 4,9
-MSCASA 4,9
-MSRASA 4,9
MAA[13..0] 4,9
VDD_25_SUS
-MSWEB4,9
R74 4.7KR
DDR_VREF
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
108
120
148
168
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
1
9
101
102
VDD07VDD138VDD246VDD370VDD485VDD5
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
NC4
C20
C0.1U50Y
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
DR_MD[63..0]9,10
D D
C C
B B
VDD_25_SUS
R73 4.7KR
DDR_VREF
VREF routed as 40~50
mils trace wide ,
Space>25 mils
-MSWEA4,9
VDD6
VDD7
VDD8
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
Place 104p and 1000p Cap. near the DIMM
143
104
112
128
136
VDDQ7
VDDQ8
VDDQ9
VDDQ10
184
DDR DIMM
SOCKET
VSS14
VSS15
VSS16
100
116
124
132
143
104
112
128
136
VDDQ7
VDDQ8
VDDQ9
VDDQ10
184
DDR DIMM
SOCKET
VSS14
VSS15
VSS16
100
116
124
132
156
164
VDDQ11
VDDQ12
PIN
VSS17
VSS18
139
145
184
172
180
VDDQ13
VDDQ14
VSS19
VSS20
152
160
82
15
VDDID
VDDQ15
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC5
NC(RESET#)
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VSS21
176
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
-MCS2
157
-MCS3
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
103
MAB0
48
MAB1
43
MAB2
41
MAB3
130
MAB4
37
MAB5
32
MAB6
125
MAB7
29
MAB8
122
MAB9
27
MAB10
141
MAB11
118
115
MAB13
167
MEMBAKB0
59
MEMBAKB1
52
113
SMBCLK1
92
SMBDATA1
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
MCKE0
21
MCKE1
111
-MSCASB
65
-MSRASB
154
97
107
119
129
149
159
169
177
140
DDR2
DIMM-184_green
N13-1840061-K06
-MCS2 4,9
-MCS3 4,9
MEMBAKB0 4,9
MEMBAKB1 4,9
VDD_25_SUS
-MSCASB 4,9
-MSRASB 4,9
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
MAB[13..0] 4,9
MEMCLK_H4 4,9
MEMCLK_L4 4,9
MEMCLK_H1 4,9
MEMCLK_L1 4,9
MEMCLK_H6 4,9
MEMCLK_L6 4,9
Place near the DIMM
VDD_25_SUS
R13
1KR1%
A A
R14
1KR1%
C423
X_C0.1U50Y
DDR_VREF
C19
C1U10Y
VREF routed as 40~50 mils trace wide ,
Space>25 mils
DDR_VREF 4
5
DIMM1 SLAVE ADDRESS
= (1010000X)B = A0
4
DR_DM[7..0]
DR_DM[7..0] 9,10
3
DIMM2 SLAVE ADDRESS
= (1010001X)B = A2
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Micro Star Restricted Secret
System Memory : DDR DIMM 1
MS-7144
Last Revision Date:
Wednesday, March 02, 2005
Sheet
832
1
Rev
100
of
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS
DR_MD44
DR_MD35
DR_MD40
D D
DR_MD59
DR_MD63
DR_MD62
DR_MD58
-DR_MDQS7
DR_DM7
DR_MD57
DR_MD61
DR_MD60
DR_MD56
DR_MD51
DR_MD55
C C
B B
-MSCASA4,8
-MSWEB4,8
-MSRASB4,8
-MSRASA4,8
MEMBAKB04,8
MEMBANKA04,8
DR_MD50
DR_MD54
-DR_MDQS6
DR_DM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD48
DR_MD49
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_DM5
DR_MD41
-MCS1
-MCS14,8
-MCS0
-MCS04,8
-DR_MDQS5
-MSCASA
-MSWEB
DR_MD45
-MSRASB
-MSRASA
DR_MD37
DR_MD33
RN64 8P4R-47R0402
7 8
5 6
3 4
1 2
RN61 8P4R-47R0402
7 8
5 6
3 4
1 2
RN59 8P4R-47R0402
7 8
5 6
3 4
1 2
RN57 8P4R-47R0402
7 8
5 6
3 4
1 2
RN55 8P4R-47R0402
7 8
5 6
3 4
1 2
RN53 8P4R-47R0402
7 8
5 6
3 4
1 2
RN51 8P4R-47R0402
7 8
5 6
3 4
1 2
RN46 8P4R-47R0402
7 8
5 6
3 4
1 2
RN45 8P4R-47R0402
7 8
5 6
3 4
1 2
RN38 8P4R-47R0402
7 8
5 6
3 4
1 2
MEMBAKB14,8
MEMBANKA14,8
DR_MD39
DR_MD38
DR_MD34
DR_DM4
-DR_MDQS4
DR_MD36
DR_MD32
MAB0
MAB10
MAA10
MAA0
MAA2
MAB2
DR_MD30
MAA3
MAA4
MAA6
MAB6
MAB5
DR_MD26
DR_DM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
MAB3
MAB4
MAA5
MAA8
DR_MD24
DR_MD19
VTT_DDR_SUS
RN44 8P4R-47R0402
7 8
5 6
3 4
1 2
RN40 8P4R-47R0402
7 8
5 6
3 4
1 2
RN37 8P4R-47R0402
7 8
5 6
3 4
1 2
RN36 8P4R-47R0402
7 8
5 6
3 4
1 2
RN34 8P4R-47R0402
7 8
5 6
3 4
1 2
RN29 8P4R-47R0402
7 8
5 6
3 4
1 2
RN32 8P4R-47R0402
7 8
5 6
3 4
1 2
RN31 8P4R-47R0402
7 8
5 6
3 4
1 2
RN28 8P4R-47R0402
7 8
5 6
3 4
1 2
DR_MD23
MAB8
MAB7
DR_MD22
MAA11
MAB11
MAB9
DR_MD21
DR_MD18
MAA7
MAA9
DR_DM2
-DR_MDQS2
DR_MD17
MAA12
MAB12
DR_MD16
DR_MD11
MCKE04,8
MCKE14,8
DR_MD20
DR_MD10
DR_MD15
DR_MD14
DR_DM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD6
DR_MD7
DR_MD2
DR_DM0
-DR_MDQS0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
DR_MD27
DR_MD31
MAB1
MAA1
RN26 8P4R-47R0402
7 8
5 6
3 4
1 2
RN23 8P4R-47R0402
7 8
5 6
3 4
1 2
RN24 8P4R-47R0402
7 8
5 6
3 4
1 2
RN19 8P4R-47R0402
7 8
5 6
3 4
1 2
RN17 8P4R-47R0402
7 8
5 6
3 4
1 2
RN14 8P4R-47R0402
7 8
5 6
3 4
1 2
RN13 8P4R-47R0402
7 8
5 6
3 4
1 2
RN9 8P4R-47R0402
7 8
5 6
3 4
1 2
RN7 8P4R-47R0402
7 8
5 6
3 4
1 2
RN5 8P4R-47R0402
7 8
5 6
3 4
1 2
RN35 8P4R-47R0402
7 8
5 6
3 4
1 2
VTT_DDR_SUS
-MCS3
-MCS34,8
-MCS2
-MCS24,8
-MSCASB4,8
-MSWEA4,8
-MSCASB
-MSWEA
RN49 8P4R-47R0402
7 8
5 6
3 4
1 2
A A
For DIMM2 Clock
MEMCLK_H4
MEMCLK_H44,8 MEMCLK_L5 4,8
MEMCLK_H14,8
MEMCLK_H64,8
MEMCLK_H1
5
C75 X_C10P50N
C121 X_C10P50N
C163 X_C10P50N
MEMCLK_L4
MEMCLK_L1
MEMCLK_L6MEMCLK_H6
MEMCLK_L4 4,8
MEMCLK_L1 4,8
MEMCLK_L6 4,8
4
For DIMM1 Clock
MEMCLK_H54,8
MEMCLK_H74,8
MEMCLK_H04,8
MEMCLK_H5
MEMCLK_H7
C76 X_C10P50N
C161 X_C10P50N
C128 X_C10P50N
MEMCLK_L5
MEMCLK_L7
MEMCLK_L0MEMCLK_H0
3
MEMCLK_L7 4,8
MEMCLK_L0 4,8
DR_DM[7..0]8,10
-DR_MDQS[7..0]8,10
DR_MD[63..0]8,10
MAB[13..0]4,8
MAA[13..0]4,8
DR_DM[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
2
Micro Star Restricted Secret
Title
DDR Terminations Bank 0
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
MS-7144
Last Revision Date:
Wednesday, March 02, 2005
Sheet
932
1
Rev
100
of
5
MD38
DDR Terminations
-MDQS0 -DR_MDQS0
D D
C C
B B
-DR_MDQS[7..0]8,9
A A
R15 10R0402
RN6 8P4R-10R0402
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN8 8P4R-10R0402
DM0
1 2
3 4
MD7
5 6
MD6
7 8
RN10 8P4R-10R0402
1 2
MD8 DR_MD8
3 4
MD9 DR_MD9
5 6
7 8
MD15
R18 10R0402
RN12 8P4R-10R0402
-MDQS1
1 2
MD13 DR_MD13
3 4
DM1
5 6
MD14 DR_MD14
7 8
RN21 8P4R-10R0402
MD17
1 2
-MDQS2
3 4
MD21 DR_MD21
5 6
DM2
7 8
MD18
R27 10R0402
RN16 8P4R-10R0402
MD10
1 2
MD20
3 4
MD11
5 6
MD16 DR_MD16
7 8
RN27 8P4R-10R0402
1 2
MD23 DR_MD23
3 4
5 6
MD24
7 8
RN30 8P4R-10R0402
1 2
MD29
3 4
5 6
-MDQS3
7 8
RN33 8P4R-10R0402
MD26
1 2
3 4
MD31
5 6
MD27
7 8
-MDQS[7..0]4
DR_MD[63..0]8,9
MD[63..0]4
-DR_MDQS3
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
DR_MD0
DR_MD4
DR_MD5
DR_MD1
DR_DM0
DR_MD2MD2
DR_MD7
DR_MD6
DR_MD3MD3
DR_MD12MD12
DR_MD15
-DR_MDQS1
DR_DM1
DR_MD17
-DR_MDQS2
DR_DM2
DR_MD18
DR_MD10
DR_MD20
DR_MD11
DR_MD22MD22
DR_MD19MD19
DR_MD24
DR_MD28MD28
DR_MD29
DR_MD25MD25
DR_MD26
DR_MD30MD30
DR_MD31
DR_MD27
-MDQS4 -DR_MDQS4
DM4
MD34 DR_MD34
MD42
MD39
MD40
MD35
MD44 DR_MD44
-MDQS5
MD41
DM5 DR_DM5
MD43
MD46 DR_MD46
MD47 DR_MD47
MD49 DR_MD49
MD48 DR_MD48
MD53 DR_MD53
MD51
MD50
MD55
MD56
MD60
MD61 DR_MD61
MD57 DR_MD57
DM7
-MDQS7
MD58 DR_MD58
MD63
DM3
4
R54 10R0402
RN39 8P4R-10R0402
1 2
3 4
5 6
7 8
RN41 8P4R-10R0402
1 2
3 4
5 6
7 8
DR_MD32MD32
DR_MD36MD36
DR_MD33MD33
DR_MD37MD37
DR_DM4
R55 10R0402
RN43 8P4R-10R0402
1 2
3 4
5 6
7 8
RN48 8P4R-10R0402
1 2
3 4
5 6
7 8
RN52 8P4R-10R0402
1 2
3 4
5 6
7 8
RN56 8P4R-10R0402
1 2
3 4
5 6
7 8
DR_MD39
DR_MD40
DR_MD35
DR_MD45MD45
-DR_MDQS5
DR_MD41
DR_MD43
DR_MD52MD52
DR_DM6DM6
R65 10R0402
RN58 8P4R-10R0402
1 2
3 4
5 6
7 8
RN60 8P4R-10R0402
1 2
3 4
5 6
7 8
RN62 8P4R-10R0402
1 2
3 4
5 6
7 8
R71 10R0402
R69 10R0402
R34 10R0402
-DR_MDQS6-MDQS6
DR_MD54MD54
DR_MD50
DR_MD55
DR_MD56
DR_MD60
DR_DM7
-DR_MDQS7
DR_MD62MD62
DR_MD59MD59
DR_MD63
DR_DM3
DR_MD38
DR_MD42
DR_MD51
3
C54
X_C0.1U50Y
C100
C55
X_C0.1U50Y
C194
X_C0.1U50Y
C149
X_C0.1U50Y
C42
C0.1U50Y
C172
X_C0.1U50Y
VTT_DDR_SUS
C57
C1U10Y
VTT_DDR_SUS
C90
C1U10Y
VTT_DDR_SUS
C0.22U16Y
C29
VTT_DDR_SUS
2
LAYOUT: Place on backside,
evenly spaced around VTT fill.
VTT_DDR_SUSVTT_DDR_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUSVDD_25_SUS
C181
X_C0.1U50Y
C189
C0.1U50Y
C0.1U50Y
C136
X_C0.1U50Y
C48
X_C0.1U50Y
C30
X_C0.1U50Y
C198
X_C0.1U50Y
VTT_DDR_SUSVDD_25_SUS
C193
C1000P50X
<nopop>
C24
X_C0.22U16Y
<nopop>
C41
X_C0.22U16Y
<nopop>
X_C0.22U16Y
<nopop>
C107
C203
C0.1U50Y
C141
X_C0.1U50Y
C153
X_C0.1U50Y
C120
C0.1U50Y
C93
X_C0.1U50Y
C95
C0.1U50Y
C62
C0.1U50Y
LAYOUT: Locate close
to Clawhammer
socket.
VTT_DDR_SUS
+
EC21
X_.CD1000U6.3EL15
GND
C68
X_C0.1U50Y
GNDGND
C182
C0.1U50Y
C34
X_C0.1U50Y
C81
X_C0.1U50Y
C145
C0.1U50Y
C158
C0.1U50Y
+
EC4
.CD1000U6.3EL15
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.
C103
C1U10Y
C94
X_C0.1U50Y
C47
C1U16Y0805
C28
C17
X_C0.1U50Y
C27
X_C0.1U50Y
C23
X_C0.22U16Y
C88
C65
X_C0.1U50Y
C79
X_C0.1U50Y
X_C0.1U50Y
C32
X_C0.1U50Y
C1U10Y
C1U10Y
C45
C40
LAYOUT: Locate close to
Clawhammer socket.
C1000P50X
C35
C98
C11
C1U16Y0805
X_C4.7U10Y0805
GND
C177
C1U10Y
C80
C1U10Y
X_C100P50N
C185
C36
C191
X_C0.1U50Y
C82
X_C0.1U50Y
C170
X_C0.1U50Y
C165
C0.1U50Y
C127
X_C0.1U50Y
C195
X_C0.1U50Y
C50
C0.1U50Y
C146
C1U10Y
C200
X_C0.1U50Y
C150
C1U10Y
C202
X_C0.1U50Y
C151
X_C0.1U50Y
C139
C1U10Y
C157
X_C0.1U50Y
VDD_25_SUS
C39
C1U10Y
C1U10Y
C0.1U50Y
1
VDD_25_SUS VCC3
C462
X_C0.1U50Y
C463
X_C0.1U50Y
C464
VCC
X_C0.1U50Y
C465
X_C0.1U50Y
C466
X_C0.1U50Y
C467
Ver:00A modify
X_C0.1U50Y
VDD_25_SUS
C148
C0.1U50Y
C77
C0.1U50Y
C117
C0.1U50Y
C199
C0.1U50Y
C188
C0.1U50Y
C116
C0.1U50Y
C89
X_C0.1U50Y
C206
C0.1U50Y
GND
C143
C144
X_C0.1U50Y
X_C0.1U50Y
GND
C204
C209
C0.1U50Y
GND
C0.1U50Y
LAYOUT: Locate close to
Dimm2 socket.
C31
C0.1U50Y
C133
C0.1U50Y
GND
C0.1U50Y
C211
GND
DR_DM[7..0]8,9
DM[8..0]4
DR_DM[7..0]
DM[8..0]
5
X_C1000P50X
X_C1000P50NC113
C49
C13
X_C4.7U10Y0805
4
3
C22
C201
X_C4.7U10Y0805
X_C1000P50X
C225
C1000P50X
C212
C196
C1U16Y0805
C0.22U16Y
C183
GND
C1U16Y0805
2
Micro Star Restricted Secret
Title
DDR Terminations Bank 1
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
MS-7144
Last Revision Date:
Wednesday, March 02, 2005
Sheet
10 32
1
Rev
100
of
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