MSI MS-7142 Schematics
5
4
3
2
1
MS-7142 VER:100
PageTitle
Cover Sheet 1
*AMD PGA 754 K8-Processor (DDR 400)
D D
*VIA K8M800
*VIA VT8237R
(AGP 8X / VLink 8X)
*Winbond 83627THF LPC I/O
*VIA VT6103L 10/100 Base-T LAN
*USB 2.0 support (integrated into VT8237R)
*VIA VT1617 AC'97 Codec
*DDR DIMM * 2
*AGP SLOT * 1 ( 8X )
C C
*PCI SLOT * 3
B B
Block Diagram 2
GPIO SPEC
3
AMD K8 -> 754 PGA Socket 4,5,6
Clock Synthesizer
System Memory
DDR DIMM 1 & 2
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8M800/K8T800 PRO (HT)
K8 Vcore Power
AGP SLOT 8X
VT8237R
PCI Connectors * 3
VIA VT1617 AC'97 CODEC
IDE ATA 66/100 Connectors * 2
Front and Rear USB Port
LPC I/O W83627THF& ROM & Floppy&Fan
KeyBoard/M o u s e/LPT/COM Connectors
VIA VT6103L 10/100 LAN & VGA Connector
ACPI Power Controller (MS-6)
System Regulator&Front Panel
Decoupling Cap.
Power Sequence
History
Option Parts
7
8
9
10
11,12,13
14
15
16,17,18
19,20
21
22
23
24
25
26
27
28
29
30
31
32
EMI Parts 33
A A
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
5
4
3
2
Stelly Chang
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Cover Sheet
MS-7142
Last Revision Date:
Friday, Decemb er 1 7, 2004
Sheet
1
Rev
100
of
133
5
4
3
2
1
Block Diagram
D D
CPUCLK+ & CPU CLK-(100/133/166/200)
AMD K8 Socket 754
HCLK+ & HCLK -(100/133/166/200) / GCLK(66)
SYSTEM CLOCK
Synthesizer /
ICS950410AF
C C
AGPCLK(66)
A
G
P
AGP 8X /Fast Write
S
L
O
T
K8M800/K8T800 pro
HT
VIA
DDR400
DDR * 2
VCLK(66) / OSC(14) / PCISB(33) / USBCLK(48) / APICCLK(14)
VLINK
PCICLK[1~3]
B B
4 PCI Slots
PCI-33
AC97 => S/W Audio
VIA VT1617
VT8237
AC97
Dual ATA 100/133
LPC BUS
USB
A A
AC_14(14)
SERIAL ATA *2
Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *4 ,
Back-Port *4
10/100 LAN
VIA VT6103L
SIOPCLK(33) /SIO48M(48)
5
4
3
MII
IDE Slot
==>ATA66,100,133 *2
SUPER I/O
W83627THF
2
2M ROM
LPC
BUS
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
1
Block Diagram
MS-7142
Last Revision Date:
Sheet
Rev
Friday, December 17, 2004
233
of
100
5
GPIO FUNCTION
4
3
2
1
Default
Function
GPI0
GPI1
EXTSMI#
RING#
LID#
BATLOW#
AGPBZ
GPI7
GPI8
UDPWREN
GPI10
GPI11
GPI12
GPI13
GPI14
INTRUDER#
CPUMISS
AOLGP1
APICCLK
3
4.7K ohm Pull up to VBAT
ATADET0=>Detect IDE1 ATA100/66
4.7K ohm Pull up to 3VDUAL
4.7K ohm Pull up to 3VDUAL
ATADET1=>Detect IDE2 ATA100/66
4.7K ohm Pull up to 3VDUAL
4.7K ohm Pull up to VCC3
2.7K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
NA
330 ohm Pull up to VCC3
330 ohm Pull up to VCC3
NA
NA
NA
2.7K ohm Pull up to VCC3INTH#
1M ohm Pull up to VBAT
4.7K ohm Pull up to 3VDUAL
THRMS#
4.7K ohm Pull up to 3VDUAL
APICCLK
IDSEL
PREQ#0
PGNT#0
PREQ#1
PGNT#1
PREQ#2
AD19
AD20
AD21
CLOCKREQ#/GNT#
PCICLK1
PCICLK2
PCICLK3
USB
Rear
Front
PCI RESET DEVICE
Signals Target
PCISLOTRST#
PCIDEVRST#
HD_RST#
PCIRST# AGP SLOT
DDR DIMM Config.
DEVICE
DIMM 1
DIMM 2
CLK GEN PIN OUTMCP1 INT Pin
22 (PCICLK5)
23 (PCICLK6)
21 (PCICLK4)
2
Port DATA +/-
USB1
LAN_USB1
JUSB1
JUSB2
PCI slot 1-3
NB , Super I/O
Primary, Scondary IDE
1010000XB
1010001XB
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien , Taiwan
http://www.m si.com.tw
USB1USB1+
USB0USB0+
USB2USB2+
USB3USB3+
USB4USB4+
USB5USB5+
USB6USB6+
USB7USB7+
OC#
USB_OC#1
( OC#0~1 )
USB_OC#2
( OC#2~3 )
USB_OC#5
( OC#4~7 )
CLOCKADDRESS
MEMCLK_H5/MEMCLK_L5
MEMCLK_H0/MEMCLK_L0
MEMCLK_H7/MEMCLK_L7
MEMCLK_H4/MEMCLK_L4
MEMCLK_H1/MEMCLK_L1
MEMCLK_H6/MEMCLK_L6
Micro Star Restricted Secret
GPIO Spec.
MS-7142
Last Revision Date:
Friday, December 17, 2004
Sheet
1
Rev
100
of
333
/GPIOAGPO24/GPI24
/GPIOB
/GPIOC
/GPIOD
5
Default
Function
GPO0
GPO1
SUSA#
SUSST#
SUSCLK
CPUSTP#
PCISTP#
GPO7
GPI8
UDPWREN
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
GPI20/ACSDIN2
GPI21/ACSDIN3
GPI22
GPI23
GPI24
GPI25
SMBDT2
SMBCK2
GPO28
/VIDSEL
GPO29
/VRDSLP
GPI30
GPI31
NA
NA
4.7K ohm Pull up to 3VDUAL
4.7K ohm Pull up to 3VDUAL
SUSST#
4.7K ohm Pull up to 3VDUAL
4.7K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
2.7K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
NA
330 ohm Pull up to VCC3
330 ohm Pull up to VCC3
NA
NA
NA
2.7K ohm Pull up to VCC3INTH#
4.7K ohm Pull down
4.7K ohm Pull down
4.7K ohm Pull up to VCC3
4.7K ohm Pull up to VCC3
4.7K ohm Pull down
4.7K ohm Pull down
4.7K ohm Pull up to 3VDUAL
4.7K ohm Pull up to 3VDUAL
SATA_LED
4.7K ohm Pull down
4.7K ohm Pull down
4.7K ohm Pull down
4
PIN NAME Function define
D D
GPO0 (VDDS)
GPO1(VDDS)
GPO2/SUSA#
(VDDS)
GPO3/SUSST#(VDDS)
GPO4/SUSCLK(VDDS)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/GNT5
GPO8/GPI8/VGATE
*
C C
GPO9/GPI9/UDPWREN
*
GPO10/GPI10/PICD0
*
GPO11/GPI11/PICD1
*
*
GPO12/GPI12/INTE#
*
GPO13/GPI13/INTF#
*
GPO14/GPI14/INTG#
*
GPO15/GPI15/INTH#
GPO20/GPI20
/ACSDIN2/PCS0#
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/GHI#
B B
GPO23/GPI23/DPSLP
GPO25/GPI25
GPO26/GPI26/SMBDT2
(VDDS)
GPO27/GPI27/SMBCK2
(VDDS)
GPO28/GPI28/VIDSEL
GPO29/GPI29/VRDSLP
GPO30/GPI30
GPO31/GPI31
A A
PIN NAME Function define
GPI0
(VBAT)
GPI1
(VSUS3)
GPI2/EXTSMI#
(VSUS3)
GPI3/RING#
(VSUS3)
GPI4/LID#
(VSUS3)
GPI5/BATLOW# (VDDS)
GPI6/AGPBZ
GPI7/REQ5
GPI8/VGATE
*
GPI9/UDPWREN
*
GPI10/PICD0
*
GPI11/PICD1
*
GPI12/INTE#
*
GPI13/INTF#
*
GPI14/INTG#
*
GPI15/INTH# GPI15
*
GPI16/INTRUDER#
(VBAT)
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
GPI19/APICCLK
PCI Config.
DEVICE
PCI Slot 1
PCI Slot 2
PCI Slot 3
INTA#
INTB#
INTC#
INTD#
INTB#
INTC#
INTD#
INTA#
INTC#
INTD#
INTA# PGNT#2
INTB#
5
4
3
2
1
VREF routed as 40~50 mils trace wide ,
Space>25 mils
DDR_VREF8
D D
VDD_25_SUS
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
C C
B B
R70 15R1%
R71 15R1%
MD[63..0]10
DM[7..0]10
A A
-MDQS[7..0]10
5
C47
X_C1000P50N
C58
AE13
C1000P50X
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17 MAA3
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
VTT_SENSE
AG12
MEMVREF1
D14
MEMZN
C14
MEMZP
A16
MEMDATA63
B15
MEMDATA62
A12
MEMDATA61
B11
MEMDATA60
A17
MEMDATA59
A15
MEMDATA58
C13
MEMDATA57
A11
MEMDATA56
A10
MEMDATA55
B9
MEMDATA54
C7
MEMDATA53
A6
MEMDATA52
C11
MEMDATA51
A9
MEMDATA50
A5
MEMDATA49
B5
MEMDATA48
C5
MEMDATA47
A4
MEMDATA46
E2
MEMDATA45
E1
MEMDATA44
A3
MEMDATA43
B3
MEMDATA42
E3
MEMDATA41
F1
MEMDATA40
G2
MEMDATA39
G1
MEMDATA38
L3
MEMDATA37
L1
MEMDATA36
G3
MEMDATA35
J2
MEMDATA34
L2
MEMDATA33
M1
MEMDATA32
W1
MEMDATA31
W3
MEMDATA30
AC1
MEMDATA29
AC3
MEMDATA28
W2
MEMDATA27
Y1
MEMDATA26
AC2
MEMDATA25
AD1
MEMDATA24
AE1
MEMDATA23
AE3
MEMDATA22
AG3
MEMDATA21
AJ4
MEMDATA20
AE2
MEMDATA19
AF1
MEMDATA18
AH3
MEMDATA17
AJ3
MEMDATA16
AJ5
MEMDATA15
AJ6
MEMDATA14
AJ7
MEMDATA13
AH9
MEMDATA12
AG5
MEMDATA11
AH5
MEMDATA10
AJ9
MEMDATA9
AJ10
MEMDATA8
AH11
MEMDATA7
AJ11
MEMDATA6
AH15
MEMDATA5
AJ15
MEMDATA4
AG11
MEMDATA3
AJ12
MEMDATA2
AJ14
MEMDATA1
AJ16
MEMDATA0
R1
MEMDQS17
DM7
A13
MEMDQS16
DM6
A7
MEMDQS15
DM5
C2
MEMDQS14
DM4
H1
MEMDQS13
DM3
AA1
MEMDQS12
DM2
AG1
MEMDQS11
DM1
AH7
MEMDQS10
DM0
AH13
MEMDQS9
T1
MEMDQS8
A14
MEMDQS7
A8
MEMDQS6
D1
MEMDQS5
J1
MEMDQS4
AB1
MEMDQS3
AJ2
MEMDQS2
AJ8
MEMDQS1
AJ13
MEMDQS0
U6B
RSVD_MEMADDA15
RSVD_MEMADDA14
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
MCKE0 8,9
MCKE1 8,9
MEMCLK_H7 8, 9
MEMCLK_L7 8,9
MEMCLK_H6 8, 9
MEMCLK_L6 8,9
MEMCLK_H5 8, 9
MEMCLK_L5 8,9
MEMCLK_H4 8, 9
MEMCLK_L4 8,9
MEMCLK_H1 8, 9
MEMCLK_L1 8,9
MEMCLK_H0 8, 9
MEMCLK_L0 8,9
-MCS3 8,9
-MCS2 8,9
-MCS1 8,9
-MCS0 8,9
-MSRASA 8,9
-MSCASA 8,9
-MSWEA 8,9
MEMBANKA1 8,9
MEMBANKA0 8,9
MAA[13..0] 8,9
-MSRASB 8,9
-MSCASB 8,9
-MSWEB 8,9
MEMBAKB1 8,9
MEMBAKB0 8,9
MAB[13..0] 8,9
CADIP[0..15]11
CLKIP111
CLKIN111
CLKIP011
CLKIN011
VLDT0
CTLIP011
CTLIN011
3
VDD_12_A
VDD_12_A
R37 49.9R1%
R41 49.9R1%
C159
X_C0.22U16Y
CADIP15
CADIN15
CADIP14
CADIN14
CADIP13
CADIN13
CADIP12
CADIN12
CADIP11
CADIN11
CADIP10
CADIN10
CADIP9
CADIN9
CADIP8
CADIN8
CADIP7
CADIN7
CADIP6
CADIN6
CADIP5
CADIN5
CADIP4
CADIN4
CADIP3
CADIN3
CADIP2
CADIN2
CADIP1
CADIN1
CADIP0
CADIN0
CTLIP1
CTLIN1
C0.22U16Y
C196
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
T29
R29
C0.22U16Y
U6A
N12-7540031-L06
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
X_C0.22U16Y
C158
C171
HYPER TRANSPORT - LINK0
2
C182
C0.22U16Y
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
C350
C0.22U16Y
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Title
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C172
C0.22U16Y
VLDT0
AH29
AH27
AG28
AG26
AF29
AE28
AF25
CADOP15
N26
CADON15
N27
CADOP14
L25
CADON14
M25
CADOP13
L26
CADON13
L27
CADOP12
J25
CADON12
K25
CADOP11
G25
CADON11
H25
CADOP10
G26
CADON10
G27
CADOP9
E25
CADON9
F25
CADOP8
E26
CADON8
E27
CADOP7
N29
CADON7
P29
CADOP6
M28
CADON6
M27
CADOP5
L29
CADON5
M29
CADOP4
K28
CADON4
K27
CADOP3
H28
CADON3
H27
CADOP2
G29
CADON2
H29
CADOP1
F28
CADON1
F27
CADOP0
E29
CADON0
F29
CLKOP1
J26
CLKON1
J27
CLKOP0
J29
CLKON0
K29
N25
P25
P28
P27
CTLOP0
CTLON0
CLKOP1 11
CLKON1 11
CLKOP0 11
CLKON0 11
CTLOP0 11
CTLON0 11
Micro Star Restricted Secret
K8 DDR & HT
MS-7142
Last Revision Date:
Sheet
1
VLDT0 5
C64
C4.7U10Y0805
CADOP[0..15] 11
CADON[0..15] 11CADIN[0..15]11
Rev
100
Friday, December 17, 2004
of
433
5
D D
4
VDDIO_SENSE
C46
X_C1000P50N
LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil
VDDA_25
traces to exit bal l fi eld ) and 500 mils long.
FB7 300L700m_250_0805
CPU_VDDA_25
3
C4.7U10Y0805
2
C51
C0.22U16Y
C63
C1000P50X
C65
FB8
X_120S/0603
1
THERMDC_CPU
AH25
CLKIN_H
CLKIN_L
AF20
AE18
AF27
AE26
AE12
AF12
AE11
AH21
AH23
AE24
AF24
AG15
AH17
AE23
AF23
AF22
AF21
AE21
AJ25
AJ27
A23
A24
B23
AJ21
AJ23
C16
C15
E20
E17
B21
A21
C18
A19
A28
AJ28
AA2
AG2
B18
AH1
C20
AG4
AG6
AE9
AG9
C1
J3
R3
D3
C6
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
C41
C68
C1000P50X
NC_C18
NC_A19
NC_C21
TDO
X_C1000P50N
VDD_25_SUS
1 2
3 4
5 6
7 8
C67
C1000P50X
Differential , "10:10:5:10:10" .
Near CPU in 0.5" .
VDDA_25 VDD_25_SUS
-CPURST28
-LDTSTOP11,18
CPUCLK0_H7
CPUCLK0_L7
8P4R-1KR
RN40
COREFB_H14
COREFB_L14
3
C55 C392p
C54 C392p
VTT_DDR_SUS
CPU_GD
L0_REF1
L0_REF0
VDDIO_SENSE
R38
R29 820R
R42 820R
7 8
169R1%
3 4
5 6
1 2
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN6
X_8P4R-1KR
VDDA_25
C C
-LDTSTOP
R20
1KR
CPU_GD27
VLDT0
VLDT04
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
R36 44.2R1%
R35 44.2R1%
HDT Test Port Signal .
B B
DBREQ_L
DBRDY
TCK
TMS
TDI
TRST_L
NC_AH18
NC_AJ18
NC_AG18
A A
NC_AG17
NC_D18
NC_B19
NC_C19
NC_D20
5
R30 X_1KR
R31 X_1KR
1 2
3 4
5 6
7 8
RN38 X_8P4R-1KR
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
VDDA_25
C198
C4.7U10Y0805
RN10
8P4R-1KR
8P4R-1KR
RN37
4
U6C
THERMTRIP_L
THERMDA
THERMDC
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
2
A20
A26
A27
AG13
VID4
AF14
VID3
AG14
VID2
AF15
VID1
AE15
VID0
AG18
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
TDO
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
Title
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
THRM#
THERMDA_CPU
THERMDC_CPU
VID4
VID4 14
VID3
VID3 14
VID2
VID2 14
VID1
VID1 14
VID0
VID0 14
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
LAYOUT: Route
FBCLKOUT_H
FBCLKOUT_H/L d ifferentially
R43
with 20/8/5/8/20 spacing and
80.6R1%
trace width. ( In CPU
FBCLKOUT_L
breakout => r outed 5:5:5 )
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
Micro Star Restricted Secret
K8 HDT & MISC
THRM# 27
THERMDA_CPU 24
THERMDC_CPU 24
MS-7142
Last Revision Date:
Sheet
1
Rev
0A
Friday, December 17, 2004
of
533
5
U6E
VSS1
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS187
VSS188
VSS206
VSS207
VSS208
VSS209
VSS210
VSS211
VSS212
VSS213
VSS214
VSS215
VSS216
VSS217
VSS218
VSS219
VSS220
VSS221
VSS222
GROUND
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
VCORE
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
L7
VDD1
AC15
VDD2
H18
VDD3
B20
VDD4
E21
VDD5
H22
VDD6
J23
VDD7
H24
VDD8
F26
VDD9
N7
VDD10
L9
VDD11
V10
VDD12
G13
VDD13
K14
VDD14
Y14
VDD15
AB14
VDD16
G15
VDD17
J15
VDD18
AA15
VDD19
H16
VDD20
K16
VDD21
Y16
VDD22
AB16
VDD23
G17
VDD24
J17
VDD25
AA17
VDD26
AC17
VDD27
AE17
VDD28
F18
VDD29
K18
VDD30
Y18
VDD31
AB18
VDD32
AD18
VDD33
AG19
VDD34
E19
VDD35
G19
VDD36
AC19
VDD39
AA19
VDD38
J19
VDD37
F20
VDD40
H20
VDD41
K20
VDD42
M20
VDD43
P20
VDD44
T20
VDD45
V20
VDD46
Y20
VDD47
AB20
VDD48
AD20
VDD49
G21
VDD50
J21
VDD51
L21
VDD52
N21
VDD53
R21
VDD54
U21
VDD55
W21
VDD56
AA21
VDD57
AC21
VDD58
F22
VDD59
K22
VDD60
M22
VDD61
P22
VDD62
T22
VDD63
V22
VDD64
Y22
VDD65
AB22
VDD66
AD22
VDD67
E23
VDD68
G23
VDD69
L23
VDD70
N23
VDD71
R23
VDD72
U23
VDD73
W23
VDD74
AA23
VDD75
AC23
VDD76
B24
VDD77
D24
VDD78
F24
VDD79
K24
VDD80
M24
VDD81
P24
VDD82
T24
VDD83
V24
VDD84
Y24
VDD85
AB24
VDD86
AD24
VDD87
AH24
VDD88
AE25
VDD89
K26
VDD90
P26
VDD91
V26
VDD92
GNDGND
B2
AH20
AB21
W22
M23
L24
AG25
AG27
D D
C C
B B
A A
D2
AF2
W6
Y7
AA8
AB9
AA10
J12
B14
Y15
AE16
J18
G20
R20
U20
W20
AA20
AC20
AE20
AG20
AJ20
D21
F21
H21
K21
M21
P21
T21
V21
Y21
AD21
AG21
B22
E22
G22
J22
L22
N22
R22
U22
AG29
AA22
AC22
AG22
AH22
AJ22
D23
F23
H23
K23
P23
T23
V23
Y23
AB23
AD23
AG23
E24
G24
J24
N24
R24
U24
W24
AA24
AC24
AG24
AJ24
B25
C25
B26
D26
H26
M26
T26
Y26
AD26
AF26
AH26
C27
B28
D28
G28
F15
H15
AB17
AD17
B16
G18
AA18
AC18
D19
F19
H19
K19
Y19
AB19
AD19
AF19
J20
L20
N20
5
U6D
POWER
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
4
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
3
LAYOUT: Place 6 EMI caps along bottom right side of Clawhammer,
2 in middle of HT link, and 12 along bottom left side of
Claw-hammer.
VCORE
C476
C471
C61
Place between DIMN1 & 2
VDD_25_SUS
C128
C154
C0.1U10X_0402
VDD_25_SUS
C92
C135
<nopop>
C1U6.3Y_0402
C472
<nopop>
<nopop>
X_C1U16Y
X_C6.8P50N
C149
C180
C0.1U10X_0402
C0.1U10X_0402
C0.1U10X_0402
LAYOUT: Place beside processor.
C73
C211
<nopop>
C1U16Y
C4.7U10Y0805
C4.7U10Y0805
In CPU.
VCORE
C102
C0.22U16Y
C103
C180P50N
C475
X_C1U16Y
X_C6.8P50N
X_C6.8P50N
GND
C132
GND
C0.1U10X_0402
C85
C165
C1000P50X
C108
C180P50N
C114
C180P50N
3
C95
C230
C4.7U10Y0805
C112
C8.2P50N
C106
C0.22U16Y
X_C0.22U16Y
X_C0.22U16Y
C116
C113
C8.2P50N
C0.22U16Y
X_C0.22U16Y
C62
X_C6.8P50N
C107
C122
C117
C0.22U16Y
C1U16Y0805
C245
C168
X_C1U16Y0805
C125
C0.22U16Y
C121
X_C0.22U16Y
2
VDD_25_SUS VTT_DDR_SUS
C199
C248
C142
C0.22U16Y
X_C1U16Y0805
C1U6.3Y_0402
GND
C105
C0.22U16Y
C126
C8.2P50N
2
C129
X_C0.22U16Y
<nopop>
C0.22U16Y
C1U16Y
VTT_DDR_SUS
X_C0.1U25Y
C474
C478
C1U16Y
BACK
C467
C188
X_C0.1U25Y
GND
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien , Taiwan
http://www.m si.com.tw
1
VDD_25_SUS
C469
C1U16Y
GND
Micro Star Restricted Secret
K8 POWER & GND
MS-7142
1
Last Revision Date:
Friday, December 17, 2004
Sheet
633
Rev
0A
of
5
4
3
2
1
Clock Synthesizer
VCC3
D D
C C
APICCLK17,18
"FS0~FS3" are all internal
pull-up via 100K ohm ..
FS0
FS2
FS1
FS3
B B
C322
X_104P
AC_1421
GUICLK12
R171 10KR
R132 10KR
R137 10KR
R130 10KR
FB21 X_120S/0805
CP8
X_COPPER
AC_14
APICCLK
GUICLK
CLKVCC3
CLKVCC3
CLKVCC3
R14210KR
R18022R
R13622R
R12122R
C323
X_4.7u/0805
FS0
FS1
FS2
2
9
16
19
29
35
38
43
46
32
5
10
15
20
27
30
33
34
39
42
47
1
48
45
C303
104P
U10
VDDHTT
VDDPCI
VDDPCI
VDDPCI
AVDD48
VDDCPU
VDDCPU
VDDA
VDDREF
PD#*
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
*FS0/REF0
*FS1/REF1
*FS2/REF2
ICS950405
C330
33P50N
C305
104P
X1
3
CLKX1
C307
C306
104P
104P
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7
PCICLK10
HTTCLK0/ModeA*
PCICLK8/HTTCLK1/ModeB*
PCICLK9/HTTCLK2
PCICLK11/HTTCLK3
24_48M/24_48SEL#
48MHz/FS3**
SCLK
SDATA
RESET#
X2
4
CLKX2
Y2
14.318MHZ
C327
33P50N
C342
104P
41
40
37
36
13
14
17
18
21
22
23
24
12
6
7
8
11
28
31
25
26
44
C346
104P
FOR K8T800 Pro
RN69
MODEA
MODEB
HT_66_2
SEL_24
SMBCLK1
SMBDATA1
R129 10KR
C347
C304
104P
104P
R138 T_15RST
R139 T_15RST
R140 15RST
R141 15RST
RN70
7 8
5 6
3 4
1 2
R181 22R
R182 22R
7 8
5 6
3 4
1 2
R144 33R
R116 22R
8P4R-22R
8P4R-22R
HCLK+
HCLKCPUCLK0_H
CPUCLK0_L
LPC_PCLK
SIOPCLK
PCICLK1
PCICLK2
PCICLK3
SBPCLK
VCLK
GCLK_SLOT
GCLK_NB
SIO48M
USBCLK_SBFS3
SMBCLK1 8, 17,27
SMBDATA1 8,17,27
CLK_RESET# 27,28
HCLK+ 11
HCLK- 11
CPUCLK0_H 5
CPUCLK0_L 5
LPC_PCLK 24
SIOPCLK 24
PCICLK1 19
PCICLK2 19
PCICLK3 20
SBPCLK 18
VCLK 18
GCLK_SLOT 15
GCLK_NB 12
SIO48M 24
USBCLK_SB 16
APICCLK
VCLK
GCLK_SLOT
GCLK_NB
USBCLK_SB
SIO48M
AC_14
GUICLK
SBPCLK
PCICLK3
PCICLK2
PCICLK1
SIOPCLK
LPC_PCLK
CPUCLK0_H
CPUCLK0_L
HCLK+
C291 T_C10P50N
HCLK-
C292 T_C10P50N
For K8T800 Pro
C302 X_10P
CN8
7 8
5 6
3 4
1 2
8P4C-10P
C295 X_10P
C297 X_10P
C345 X_10P
C290 X_10P
C357 X_10P
C356 10P
CN9
1 2
3 4
5 6
7 8
8P4C-10P
C293 X_5P
C294 X_5P
FS(3:0)
CPU
0000
100.90
0001
133.90
0010
168.00
0011
202.00
0100
100.20
0101
133.50
0110
166.70
200.40
0111
1000
150.00
1001
180.00
1010
210.00
1011
1100
1101
1110
1111
240.00
270.00
233.33
266.67
300.00
A A
67.27
66.95
67.20
67.33
66.80
66.75
66.68
60.00
60.00
70.00
60.00
67.50
66.67
66.67
75.00
5
HTT
PCI
33.63
33.48
33.60
33.67
33.40
33.38
33.34
33.4066.80
30.00
30.00
35.00
30.00
33.75
33.33
33.33
37.50
MODEA
R191 10KR
MODEB
R195 10KR
MODE BMODE A
00
HTTCLK1
HTTCLK1
PCICLK8
HTTCLK1
HTTCLK2
HTTCLK2
PCICLK9
PCICLK9
0
1
1
0
11
4
PIN11PIN8PIN7
PCICLK11
HTTCLK3
PCICLK11
PCICLK11
SEL_24
SEL_24
0
1
3
R135 X_10KR
PIN28
48M
24M
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L CO.,LTD.
No. 69, Li- De St, J ung-He City,
Taipei Hsien, Taiwan
2
http://www. msi.com.tw
Clock Synthesizer
MS-7142
Last Revision Date:
Sheet
1
Friday, December 17, 2004
733
Rev
100
of
5
DR_MD0
DR_MD[63..0]9,10
D D
C C
B B
VDD_25_SUS
R106 4.7 KR
-MSWEA4,9
DDR_VREF
VREF routed as 40~50
mils trace wide ,
Space>25 mils
Place 104p and 1000p Cap. near the DIMM
Place near the DIMM
VDD_25_SUS
R19
1KR1%
A A
R18
1KR1%
C39
C0.1U25Y
C466
X_C0.1U25Y
DDR_VREF
C38
C1U10Y
5
2
DR_MD1
4
DR_MD2
6
DR_MD3
8
DR_MD4
94
DR_MD5
95
DR_MD6
98
DR_MD7
99
DR_MD8
12
DR_MD9
13
DR_MD10
19
DR_MD11
20
DR_MD12
105
DR_MD13
106
DR_MD14
109
DR_MD15
110
DR_MD16
23
DR_MD17
24
DR_MD18
28
DR_MD19
31
DR_MD20
114
DR_MD21
117
DR_MD22
121
DR_MD23
123
DR_MD24
33
DR_MD25
35
DR_MD26
39
DR_MD27
40
DR_MD28
126
DR_MD29
127
DR_MD30
131
DR_MD31
133
DR_MD32
53
DR_MD33
55
DR_MD34
57
DR_MD35
60
DR_MD36
146
DR_MD37
147
DR_MD38
150
DR_MD39
151
DR_MD40
61
DR_MD41
64
DR_MD42
68
DR_MD43
69
DR_MD44
153
DR_MD45
155
DR_MD46
161
DR_MD47
162
DR_MD48
72
DR_MD49
73
DR_MD50
79
DR_MD51
80
DR_MD52
165
DR_MD53
166
DR_MD54
170
DR_MD55
171
DR_MD56
83
DR_MD57
84
DR_MD58
87
DR_MD59
88
DR_MD60
174
DR_MD61
175
DR_MD62
178
DR_MD63
179
WP1
90
-MSWEA
63
1
9
101
102
VREF routed as 40~50 mils trace wide ,
Space>25 mils
DDR_VREF 4
VDD_25_SUS
108
120
148
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
NC4
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
VDD7
168
VDD8
4
SYSTEM MEMORY
104
112
128
136
143
156
164
172
180
15
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
PIN
184
DDR DIMM
SOCKET
CK1#(CK0#)
NC(RESET#)
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
100
DIMM1 SLAVE ADDRESS
= (1010000X)B = A0
VSS21
116
124
132
139
145
152
160
176
4
82
184
VDDID
VDDSPD
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK0#(DU)
CK1(CK0)
CK2(DU)
CK2#(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DDR1
DIMM-184_green
N13-1840061-K06
3
-MCS0
157
158
71
163
5
14
25
36
56
67
78
86
47
103
48
43
41
130
37
32
125
29
122
27
141
118
115
167
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
97
107
119
129
149
159
169
177
140
-MCS0 4,9
-MCS1
-MCS1 4,9
-DR_MDQS0
-DR_MDQS0 9,10
-DR_MDQS1
-DR_MDQS1 9,10
-DR_MDQS2
-DR_MDQS2 9,10
-DR_MDQS3
-DR_MDQS3 9,10
-DR_MDQS4
-DR_MDQS4 9,10
-DR_MDQS5
-DR_MDQS5 9,10
-DR_MDQS6
-DR_MDQS6 9,10
-DR_MDQS7
-DR_MDQS7 9,10
MAA[13..0]
MAA0
MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12 MAB12
MAA13
SMBCLK1
SMBDATA1
MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
MAA[13..0] 4,9
MEMBANKA0 4,9
MEMBANKA1 4,9
SMBCLK1 7,17,27
SMBDATA1 7,17,27
MEMCLK_H5 4,9
MEMCLK_L5 4,9
MEMCLK_H0 4,9
MEMCLK_L0 4,9
MEMCLK_H7 4,9
MEMCLK_L7 4,9
MCKE0 4,9
MCKE1 4,9
-MSCASA 4,9
-MSRASA 4,9
DR_DM[7..0]
3
VDD_25_SUS
DR_DM [7..0] 9,10
R109 4.7 KR
-MSWEB4,9
DDR_VREF
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
1
9
101
102
2
VDD_25_SUS
108
120
148
168
VDD07VDD138VDD246VDD370VDD485VDD5
VDD6
VDD7
VDD8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
NC4
VDDQ022VDDQ130VDDQ254VDDQ362VDDQ477VDDQ596VDDQ6
VSS03VSS111VSS218VSS326VSS434VSS542VSS650VSS758VSS866VSS974VSS1081VSS1189VSS1293VSS13
DIMM2 SLAVE ADDRESS
= (1010001X)B = A2
2
DDR DIMM
104
112
128
136
143
VDDQ7
VDDQ8
VDDQ9
VDDQ10
SOCKET
VSS14
VSS15
VSS16
100
116
124
132
82
156
164
172
180
15
VDDID
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
PIN
184
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
CKE0
CKE1
CAS#
RAS#
VSS17
VSS18
VSS19
VSS20
VSS21
139
145
152
160
176
Micro Star Restricted Secret
Title
System Me mory : DDR DIMM 1
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
CS0#
CS1#
CS2#
CS3#
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC5
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
184
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A12
A13
-MCS2
157
-MCS3
158
71
163
-DR_MDQS0
5
-DR_MDQS1
14
-DR_MDQS2
25
-DR_MDQS3
36
-DR_MDQS4
56
-DR_MDQS5
67
-DR_MDQS6
78
-DR_MDQS7
86
47
103
MAB0
48
MAB1
43
MAB2
41
MAB3
130
MAB4
37
MAB5
32
MAB6
125
MAB7
29
MAB8
122
MAB9
27
MAB10
141
MAB11
118
115
MAB13
167
MEMBAKB0
59
MEMBAKB1
52
113
SMBCLK1
92
SMBDATA1
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
MCKE0
21
MCKE1
111
-MSCASB
65
-MSRASB
154
97
107
119
129
149
159
169
177
140
DDR2
DIMM-184_green
N13-1840061-K06
MS-7142
1
-MCS2 4,9
-MCS3 4,9
MAB[13..0] 4,9
MEMBAKB0 4,9
MEMBAKB1 4,9
VDD_25_SUS
MEMCLK_H4 4,9
MEMCLK_L4 4,9
MEMCLK_H1 4,9
MEMCLK_L1 4,9
MEMCLK_H6 4,9
MEMCLK_L6 4,9
-MSCASB 4,9
-MSRASB 4,9
DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
Last Revision Date:
Friday, December 17, 2004
Sheet
833
1
Rev
100
of
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS
DR_MD44
DR_MD35
DR_MD40
D D
RN63 8P4R-47R0402
DR_MD59
7 8
DR_MD63
5 6
DR_MD62
3 4
DR_MD58
1 2
RN61 8P4R-47R0402
-DR_MDQS7
C C
B B
-DR_MDQS6
-MCS14,8
-MCS04,8
-DR_MDQS5
-MSCASA4,8
-MSWEB4,8
-MSRASB4,8
-MSRASA4,8
MEMBAKB04,8
MEMBANKA04,8
DR_DM7
DR_MD57
DR_MD61
DR_MD60
DR_MD56
DR_MD51
DR_MD55
DR_MD50
DR_MD54
DR_DM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD48
DR_MD49
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_DM5
DR_MD41
-MCS1
-MCS0
-MSCASA
-MSWEB
DR_MD45
-MSRASB
-MSRASA
DR_MD37
DR_MD33
7 8
5 6
3 4
1 2
RN59 8P4R-47R0402
7 8
5 6
3 4
1 2
RN57 8P4R-47R0402
7 8
5 6
3 4
1 2
RN55 8P4R-47R0402
7 8
5 6
3 4
1 2
RN54 8P4R-47R0402
7 8
5 6
3 4
1 2
RN52 8P4R-47R0402
7 8
5 6
3 4
1 2
RN49 8P4R-47R0402
7 8
5 6
3 4
1 2
RN47 8P4R-47R0402
7 8
5 6
3 4
1 2
RN41 8P4R-47R0402
7 8
5 6
3 4
1 2
MEMBAKB14,8
MEMBANKA14,8
DR_MD39
DR_MD38
DR_MD34
DR_DM4
-DR_MDQS4
DR_MD36
DR_MD32
MAB0
MAB10
MAA10
MAA0
MAA2
MAB2
DR_MD30
MAA3
MAA4
MAA6
MAB6
MAB5
DR_MD26
DR_DM3
-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28
MAB3
MAB4
MAA5
MAA8
DR_MD24
DR_MD19
VTT_DDR_SUS
RN46 8P4R-47R0402
7 8
5 6
3 4
1 2
RN43 8P4R-47R0402
7 8
5 6
3 4
1 2
RN39 8P4R-47R0402
7 8
5 6
3 4
1 2
RN36 8P4R-47R0402
7 8
5 6
3 4
1 2
RN34 8P4R-47R0402
7 8
5 6
3 4
1 2
RN29 8P4R-47R0402
7 8
5 6
3 4
1 2
RN32 8P4R-47R0402
7 8
5 6
3 4
1 2
RN31 8P4R-47R0402
7 8
5 6
3 4
1 2
RN28 8P4R-47R0402
7 8
5 6
3 4
1 2
RN25 8P4R-47R0402
DR_MD23
7 8
MAB8
5 6
MAB7
3 4
DR_MD22
1 2
RN22 8P4R-47R0402
MAA11
7 8
MAB11
5 6
MAB9
3 4
DR_MD21
1 2
RN23 8P4R-47R0402
DR_MD18
7 8
MAA7
5 6
MAA9
3 4
DR_DM2
1 2
RN20 8P4R-47R0402
-DR_MDQS2
7 8
DR_MD17
5 6
MAA12
3 4
MAB12
1 2
RN18 8P4R-47R0402
DR_MD16
7 8
DR_MD11
5 6
DR_MD20
DR_MD10
DR_MD15
DR_MD14
DR_DM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD6
DR_MD7
DR_MD2
DR_DM0
-DR_MDQS0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
DR_MD27
DR_MD31
MAB1
MAA1
3 4
1 2
RN16 8P4R-47R0402
7 8
5 6
3 4
1 2
RN15 8P4R-47R0402
7 8
5 6
3 4
1 2
RN11 8P4R-47R0402
7 8
5 6
3 4
1 2
RN8 8P4R-47R0402
7 8
5 6
3 4
1 2
RN4 8P4R-47R0402
7 8
5 6
3 4
1 2
RN35 8P4R-47R0402
7 8
5 6
3 4
1 2
MCKE04,8
MCKE14,8
-MCS3
-MCS34,8
-MCS2
-MCS24,8
-MSCASB
-MSCASB4,8
-MSWEA
-MSWEA4,8
VTT_DDR_SUS
RN51 8P4R-47R0402
7 8
5 6
3 4
1 2
A A
For DIMM2 Clock
MEMCLK_H4
MEMCLK_H44,8 MEMCLK_L5 4,8
MEMCLK_H14,8
MEMCLK_H64,8
MEMCLK_H1
5
C70 X_C10P50N
C115 X_C10P50N
C166 X_C10P50N
MEMCLK_L4
MEMCLK_L1
MEMCLK_L6MEMCLK_H6
MEMCLK_L4 4,8
MEMCLK_L1 4,8
MEMCLK_L6 4,8
4
For DIMM1 Clock
MEMCLK_H54,8
MEMCLK_H74,8
MEMCLK_H04,8
MEMCLK_H5
MEMCLK_H7
C71 X_C10P50N
C167 X_C10P50N
C124 X_C10P50N
MEMCLK_L5
MEMCLK_L7
MEMCLK_L0MEMCLK_H0
3
MEMCLK_L7 4,8
MEMCLK_L0 4,8
DR_DM[7..0]8,10
-DR_MDQS[7..0 ]8,10
DR_MD[63..0]8,10
MAB[13..0]4,8
MAA[13..0]4,8
DR_DM[7..0]
-DR_MDQ S[7 ..0 ]
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
2
Micro Star Restricted Secret
Title
DDR Terminations Bank 0
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
MS-7142
Last Revision Date:
Friday, December 17, 2004
Sheet
933
1
Rev
100
of
5
DDR Terminations
-MDQS0 -DR_MDQS0
D D
C C
B B
A A
R32 10R0402
RN5 8P4R-10R0402
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN9 8P4R-10R0402
DM0
1 2
3 4
MD7
5 6
MD6
7 8
RN12 8P4R-10R0402
1 2
MD8 DR_MD8
3 4
MD9 DR_MD9
5 6
7 8
MD15
R54 10R0402
RN13 8P4R-10R0402
-MDQS1
1 2
MD13 DR_MD13
3 4
DM1
5 6
MD14 DR_MD14
7 8
RN21 8P4R-10R0402
MD17
1 2
-MDQS2
3 4
MD21 DR_MD21
5 6
DM2
7 8
MD18
R55 10R0402
RN17 8P4R-10R0402
MD10
1 2
MD20
3 4
MD11
5 6
MD16 DR_MD16
7 8
RN26 8P4R-10R0402
1 2
MD23 DR_MD23
3 4
5 6
MD24
7 8
RN30 8P4R-10R0402
1 2
MD29
3 4
5 6
-MDQS3
7 8
RN33 8P4R-10R0402
MD26
1 2
3 4
MD31
5 6
MD27
7 8
-MDQS[7..0]4
-DR_MDQS[7..0 ]8,9
DR_MD[63..0]8,9
DR_DM[7..0]8,9
-MDQS[7..0]
-DR_MDQ S[7 ..0 ]
DR_MD[63..0]
MD[63..0]4
MD[63..0]
DR_DM[7..0]
DM[7..0]
DM[7..0]4
5
DR_MD0
DR_MD4
DR_MD5
DR_MD1
DR_DM0
DR_MD2MD2
DR_MD7
DR_MD6
DR_MD3MD3
DR_MD12MD12
-DR_MDQS1
DR_DM1
DR_MD17
-DR_MDQS2
DR_DM2
DR_MD10
DR_MD20
DR_MD11
DR_MD22MD22
DR_MD19MD19
DR_MD24
DR_MD28MD28
DR_MD29
DR_MD25MD25
-DR_MDQS3
DR_MD26
DR_MD30MD30
DR_MD31
DR_MD27
DR_MD15
DR_MD18
-MDQS7
MD63
DM3
4
MD38
R81 10R0402
RN42 8P4R-10R0402
1 2
3 4
5 6
7 8
RN44 8P4R-10R0402
1 2
-MDQS4 -DR_MDQS4
3 4
DM4
5 6
MD34 DR_MD34
7 8
MD42
R82 10R0402
RN45 8P4R-10R0402
MD39
1 2
MD40
3 4
MD35
5 6
MD44 DR_MD44
7 8
RN50 8P4R-10R0402
1 2
-MDQS5
3 4
MD41
5 6
DM5 DR_DM5
7 8
RN53 8P4R-10R0402
MD43
1 2
MD46 DR_MD46
3 4
MD47 DR_MD47
5 6
MD49 DR_MD49
7 8
RN56 8P4R-10R0402
MD48 DR_MD48
1 2
3 4
MD53 DR_MD53
5 6
7 8
MD51
R97 10R0402
RN58 8P4R-10R0402
1 2
3 4
MD50
5 6
MD55
7 8
RN60 8P4R-10R0402
MD56
1 2
MD60
3 4
MD61 DR_MD61
5 6
MD57 DR_MD57
7 8
RN62 8P4R-10R0402
DM7
1 2
3 4
MD58 DR_MD58
5 6
7 8
R105 10R0402
R103 10R0402
R58 10R0402
4
DR_MD32MD32
DR_MD36MD36
DR_MD33MD33
DR_MD37MD37
DR_DM4
DR_MD39
DR_MD40
DR_MD35
DR_MD45MD45
-DR_MDQS5
DR_MD41
DR_MD43
DR_MD52MD52
DR_DM6DM6
-DR_MDQS6-MDQS6
DR_MD54MD54
DR_MD50
DR_MD55
DR_MD56
DR_MD60
DR_DM7
-DR_MDQS7
DR_MD62MD62
DR_MD38
DR_MD42
DR_MD51
DR_MD59MD59
DR_MD63
DR_DM3
3
LAYOUT: Place on backside,
evenly spaced around VTT fill.
C91
X_C0.1U25Y
C148
X_C0.1U25Y
C33
X_C0.1U25Y
C243
X_C0.1U25Y
C205
C1U25Y
C262
X_C0.1U25Y
C228
X_C0.1U25Y
C232
X_C0.1U25Y
C237
C1U25Y
C176
X_C0.1U25Y
C35
X_C0.1U25Y
C59
X_C0.1U25Y
C250
X_C0.1U25Y
C221
C1000P50X
<nopop>
C50
X_C0.22U16Y
<nopop>
C239
X_C0.22U16Y
<nopop>
X_C0.22U16Y
<nopop>
VTT_DDR_SUSVDD_25_SUS
C156
C257
X_C0.1U25Y
C187
X_C0.1U25Y
C215
C1U25Y
C164
C1U25Y
C139
X_C0.1U25Y
C143
C1U25Y
C97
C1U25Y
2
LAYOUT: Locate close
to Clawhammer
socket.
VTT_DDR_SUS
EC23
CE470U10VD25A400RO
GND
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUSVDD_25_SUS
C104
X_C0.1U25Y
C272
C0.1U25Y
C76
C1U25Y
C123
X_C0.1U25Y
C200
X_C0.1U25Y
C220
X_C0.1U25Y
LAYOUT: Pl ace alternating caps t o GND and VDD_2.5_SUS in a single line along VTT island.
VTT_DDR_SUS
C94
VTT_DDR_SUS
C134
VTT_DDR_SUS
C0.22U16Y
C9
VTT_DDR_SUS
X_C1000P50NC160
3
X_C1U10Y
C1U10Y
C1U16Y0805
C6
C27
C83
C89
C229
C152
C131
C1U10Y
X_C0.1U25Y
X_C0.1U25Y
X_C0.1U25Y
C57
C101
C140
X_C0.1U25Y
C48
C12
X_C1000P50X
C32
X_C0.22U16Y
X_C4.7U10Y0805
C1U25Y
C3
X_C0.1U25Y
C1U16Y0805
C216
X_C4.7U10Y0805
C111
C1U25Y
LAYOUT: Locate close to
Clawhammer socket.
C7
X_C4.7U10Y0805
C45
X_C1000P50X
C234
C241
C1U10Y
C1U10Y
X_C0.1U25Y
X_C0.1U25Y
C69
C80
C127
C118
X_C1U10Y
C1000P50X
C56
X_C100P50N
C145
GND
C1000P50X
C191
C259
C261
C1U16Y0805
C1U25Y
X_C1U10Y
X_C0.1U25Y
C0.22U16Y
C186
C1U16Y0805
GND
2
C40
C226
C169
X_C0.1U25Y
X_C0.1U25Y
C246
C224
C1U10Y
C1U25Y
C255
C253
C1U10Y
C1U25Y
X_C0.1U25Y
C209
C210
C203
X_C1U10Y
X_C0.1U25Y
X_C0.1U25Y
VDD_25_SUS
Title
Document Number
MICRO-STAR IN T' L CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
1
VDD_25_SUS VCC3
C266
X_C0.1U25Y
C208
X_C0.1U25Y
C90
X_C0.1U25Y
C21
X_C0.1U25Y
C195
X_C0.1U25Y
C37
X_C0.1U25Y
VDD_25_SUS
C204
C0.1U25Y
C110
C0.1U25Y
C163
C0.1U25Y
C252
C0.1U25Y
C236
C0.1U25Y
C162
C0.1U25Y
C222
X_C0.1U25Y
C265
C0.1U25Y
C179
C197
C192
C1U25Y
C1U10Y
X_C0.1U25Y
GND
C219
C271
C218
C82
C0.1U25Y
C0.1U25Y
X_C1U10Y
GND
LAYOUT: Locate close to
Dimm2 socket.
C60
C173
C335
C0.1U25Y
C0.1U25Y
C0.1U25Y
GND
Micro Star Restricted Secret
DDR Terminations Bank 1
MS-7142
Last Revision Date:
Sheet
1
VCC
GND
GND
C0.1U25Y
Rev
100
Monday, December 20, 2004
of
10 33
Loading...