MSI MS-7138 Schematics
8
MS-7138
7
6
5
4
3
2
1
Version 00A
10/21/2004 Update
Cover Sheet
1
D D
* Intel LGA775 Processor
*SIS 649 / 662 + 965 / 965L
*REALTEK 8100C/8110S PCI LAN + 8201CL
*Winbond 83627EHF I/O
*USB 2.0 support x8
*ALC 655 AC97 CODEC
Block Diagram
MAIN CLOCK GEN & DDR CLOCK BUFFER
LGA775 INTEL CPU Sockets
SIS 649 / 662
DDR SLOT
DDR TERMINATOR
SIS 965 / 965L
Realtek PHY 8201CL
Realtek PCI Lan 8100C/8100S
C C
PCI SLOT 1,2,3
ERP BOM Function Description
Opt :STD501/601-7138 SiS 649+965 W/O 1394, W/ SATA
IDE CONNECTOR
PCI EXPRESS X 16
AC'97 CODEC (ALC655)
USB CONNECTOR
AUDIO CONNECTOR & VGA
FAN
2
3
4 - 6
7 - 10
11
12
13 - 16
17
18
19
20
21
22
23
24
25
B B
LAN CONNECTOR & PS/2 CONNECTOR
LPC I/O (W83627EHF)
PARALLEL & SERIAL PORT
ACPI CONTROLLER
FRONT PANEL & ATX POWER CONNECOTR
VRM 10
Decoupling Capacitor
A A
Micro-Star
Document Number
Last Revision Date:
8
7
6
5
4
3
Monday, November 22, 2004
2
26
27
28
29
30
31
32
Title
MS7138
Cover Sheet
Sheet of
1
Rev
0A
132
5
System Block Diagram
D D
P
C
I
|
C C
E
PCI-Express X 16
Graphic Interface
4
LGA775
SIS 649
/
SIS 662
HOST BUS
MuTIOL
System Bus
800MHz
Data Bus
up to 1GHz
MEMORY BUS
DDR
333/400MHz
3
D
D
I
I
M
M
M
M
1
2
2
GPIO Table on SIS965
GPIO_0
GPIO_1
GPIO_2
GPIO_3 EXTSMI#
GPIO_4
GPIO_5
GPIO_6
GPI_7 RESUME
GPI_8 RING
GPI_9
GPI_10
GPIO_11
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
GPIO_20
GPIO_21
GPIO_22
GPIO_23
GPIO_24
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
I/O
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
I/O
RESUME
I/O
RESUME
I/O
RESUME
O
RESUME
O
RESUME
O
RESUME
MAIN
I/O
MAIN
I/O
I
RESUME
I
RESUME
I
RESUME
I RESUME
Flash Rom protection
Boot Block protection
THERM#
Pull-Up
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Pull-Down
Pull-DownGPIO_12 RESUME
Pull-Up
Pull-Down
KBDAT
KBCLK
MSDAT
MSCLK
SMBCLK
SMBDAT
RESERVED
RESERVED
RESERVED
RESERVED
1
USB 2.0 X 8 USB 2.0 AC-LINK
PCI 1, 2,3
8100C/8110S
KEYBOARD/
MOUSE
B B
PHY 8201CL
PCI BUS
GMII
ATA133
SIS 965
SATA SATA 1,2,3,4
AC'97
AUDIO CODEC
IDE 1,2
PCI Config.
DEVICE
PCI Slot 2
PIRQ#B
PIRQ#C
PIRQ#D
PIRQ#A
PIRQ#C
PIRQ#D
PIRQ#A
PCI_REQ#0PCI Slot 1
AD17
IDSEL
CLOCKREQ#/GNT#MCP1 INT Pin
PCICLK1
PCI_GNT#0
PCI_REQ#1 AD18 PCICLK2
PCI_GNT#1
PIRQ#B
PCI Slot 3 PCI_REQ#2 AD19
PIRQ#D
PIRQ#A
PCI_GNT#2
PCICLK3
PIRQ#B
LPC BUS
LAN PIRQ#C PCI_REQ#3
PIRQ#C
AD22 LAN_PCLK
PCI_GNT#3
CPU_FAN SYS_FAN PWR_FAN
LPC ROM
FAN CONTROL
H/W MONITOR
LPC SUPER I/O
W83627EHF
FAN SPEED,VOTLAGE,TEMPERATURE
PCI RESET DEVICE
Signals
PCIRST#1
Northbridge,LAN,1394,S/IO,Flash Rom
Target
PCI1~3PCIRST#2
A A
GPIOS IR/CIR
5
COM1,2 PRINT ER FLOPPY
4
3
HDDRST#
Primary, Sco n dary IDE
2
Micro-Star
Title
Document Number
Last Revision Date:
Monday, Novem ber 22 , 2004
MS7138
System Block Diagram
Sheet of
1
Rev
0A
232
5
4
3
2
1
VCC3
VCC3
CB96
0.1u
CB90
X_0.1u
CB86
0.1u
R234
FP_RST#4,29,30
CB51
0.1u
VCC3
CB53
0.1u
CB95
0.1u
475RST
C271
X_4.7U/0805
CP41
L39
X_COPPER
1 2
CB88
CB92
X_0.1u
0.1u
VCC3 VCC3
R229
10K
Q47
2N3904S
C246
X_10p
VCCM
CB42
0.1u
CB87
0.1u
C72
4.7U/0805
R241
10K
Q48
2N3904S
VCCP
80_0805
R230
10K
D D
C C
B B
Main Clock Generator
U17
ICS953401BF_SSOP56
1
VDDREF
11
VDDZ
12
VDDPCI
18
VDDPCI
25
VDD48
29
VDDPE
34
VDDPE
37
VDDPE
56
VDDCPU
5
GNDREF
8
GNDZ
17
GNDPCI
23
GNDPCI
28
GND48
42
GNDPE
53
GNDCPU
50
Vtt_PwrGd/PD#*/(CLK_Stop#)*
44
IREF
24
*(CPU_Stop#)/RESET#
48
VDDA
CB85
102p
45
GNDA
X1
6
C274
14M-32pf-HC49S-D
27p
**FS2/PCICLK5
**FS3/PCICLK6
**FS4/PCICLK7
*(PCI_Stop#)/PCICLK4
**Mode/PCICLK3
PCICLK2/PECLKREQ#
24_48MHz/SEL24_48#*
12_48MHz/SEL12_48#**
X2
7
Y2
CPUCLKT0
CPUCLKC0
CPUCLKT1
CPUCLKC1
PECLK0T
PECLK0C
PECLK1T
PECLK1C
PECLK2T
PECLK2C
PECLK3T_F
PECLK3C_F
PECLK4T_F
PECLK4C_F
ZCLK0
ZCLK1
PCICLK1_F
PCICLK0_F
*FS0/REF1
**FS1/REF2
REF0
SCLK
SDATA
SATACLKT
SATACLKC
C261
27p
FS2
0
0
0133
0
1
1
55
54
52
51
41
40
39
38
36
35
33
32
31
30
9
10
13
14
15
16
19
20
21
22
3
4
2
27
43
49
47
46
26
CK_PE_SRC1
CK_PE_SRC1#
CK_PE_SRC2
CK_PE_SRC2#
REF0
R247
R248
R249
R250
1 2
3 4
5 6
7 8
RN50
8P4R-33
R282
R283
RN53
FS2
FS3
FS4
PCLK
PECLKREQ#
FS0
FS1
SEL12_48 OSC12
8P4R-33
PCLK
1 2
FS4
3 4
FS3
5 6
FS2
7 8
7 8
5 6
3 4
1 2
RN52 8P4R-33
7 8
REF0 REFCLK2
5 6
FS0 REFCLK1
3 4
FS1 DCLK
1 2
R285
R245
R246
R284
FS0
FS1FS4
0100
0
0
0000
CPUCLK1
33
CPUCLK-1
33
CPUCLK0
33
CPUCLK-0
33
CK_PE_100M_MCH
CK_PE_100M_MCH#
CK_PE_100M_16PORT
CK_PE_100M_16PORT#
ZCLK0
22
ZCLK1
22
96XPCLK
SIOPCLK
LAN_PCLK
FWH_CLK
PCICLK1
PCICLK2
PCICLK3
RN54
8P4R-33
SIO48MMULTISEL
22
SMBCLK
SMBDAT
SATACLK
33
SATACLK-
33
22
SRC
CPU
100
100
CPUCLK1 7
CPUCLK-1 7
CPUCLK0 4
CPUCLK-0 4
ZCLK0 10
ZCLK1 13
96XPCLK 13
SIOPCLK 27
LAN_PCLK 18
FWH_CLK 27
PCICLK1 19
PCICLK2 19
PCICLK3 19
REFCLK2 22
REFCLK1 14
DCLK 10
48MHz
SIO48M 27
SMBCLK 11,14,18,21,27,29
SMBDAT 11,14,18,21,27,29
SATACLK 15
SATACLK- 15
12MHz
OSC12 15
ZCLK
AGP
660
133
66
133
133 66 33100200
CK_PE_100M_MCH 7
CK_PE_100M_MCH# 7
CK_PE_100M_16PORT 21
CK_PE_100M_16PORT# 21
PCIFS3
330
33
VCC3
CB48
X_0.1u
EMI
MULTISEL i nternal Pull-Up 120K
MULTISEL
SEL12_48
FS0
FS1
FS2
FS3
FS4
PECLKREQ#
F0~F4 inte rnal Pull-Down 120K
0=48MHZ,1=24MHZ
0=48MHZ,1=12MHZ
RN51
10K_8P4R
1 2
3 4
5 6
7 8
R293 10K
R291 10K
R289 10K
R286 4.7K
R290 4.7K
VCC3
H_FSBSEL0 4,5
H_FSBSEL1 4,5,10
H_FSBSEL2 4,5
CPUCLK0
CPUCLK-0
CPUCLK1
CPUCLK-1
SATACLK
SATACLK-
CK_PE_100M_MCH
CK_PE_100M_MCH#
CK_PE_100M_16PORT
CK_PE_100M_16PORT#
PCICLK3
PCICLK2
PCICLK1
FWH_CLK
LAN_PCLK
SIOPCLK
96XPCLK
DCLK
REFCLK1
REFCLK2
SIO48M
OSC12
ZCLK0
ZCLK1
DDRCLK0
DDRCLK1
DDRCLK2
DDRCLK3
DDRCLK8
DDRCLK7
R239
R240
R237
R238
R232
R233
CN9 X_8P4C_10p
CN8 X_8P4C_10p
CN7 X_8P4C_10p
RN48
1 2
3 4
5 6
7 8
8P4R-51R
1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2
1 2
3 4
5 6
7 8
C294 X_10p
C293 X_10p
C291 X_10p
C292 X_10p
C96 X_10p
C68 X_10p
C74 X_10p
C98 X_10p
C66 X_10p
C64 X_10p
49.9RST
49.9RST
49.9RST
49.9RST
49.9RST
49.9RST
U7
CBVDD
VCCM
A A
VCC3
5
FWDSDCLKO8
R86 X_4.7K
option mounted
for RTM680-627
CB46
X_0.1u
SMBCLK
SMBDAT
CB52
0.1u
FWDSDCLKO
D2#/D6_SEL
12
23
10
22
20
18
21
4
3
7
8
9
ICS93732
VDD
VDD
VDD
AVDD
SCLK
SDATA
CLK_IN
FB_IN
NC
NC
NC
GND
6
GND11GND15GND
28
Clock Buffer (DDR)
DDRCLK0
2
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
FB_OUT
DDRCLK3
4
DDRCLK2
13
DDRCLK1
17
DDRCLK8
24
DDRCLK7
26
DDRCLK-0
1
DDRCLK-3
5
DDRCLK-2
14
DDRCLK-1
16
DDRCLK-8
25
DDRCLK-7
27
R87
19
DDRCLK0 11
DDRCLK3 11
DDRCLK2 11
DDRCLK1 11
DDRCLK8 11
DDRCLK7 11
DDRCLK-0 11
DDRCLK-3 11
DDRCLK-2 11
DDRCLK-1 11
DDRCLK-8 11
DDRCLK-7 11
10
FB_OUT
C67
10p
3
CB43
X_0.1u
VCC3
CB50
X_0.1u
FOR EMI
X_0.1u
CB40
CB56
X_0.1u
Micro-Star
Document Number
Last Revision Date:
2
Monday, November 22, 2004
DDRCLK-0
DDRCLK-1
DDRCLK-2
DDRCLK-3
DDRCLK-8
DDRCLK-7
Title
C97 X_10p
C69 X_10p
C75 X_10p
C99 X_10p
C65 X_10p
C63 X_10p
MS7138
MAIN CLOCK GEN & BUFFER
Sheet of
1
332
Rev
0A
8
D D
HDBI#[0..3]7
C C
HDEFER#7
CPU_TMPA27
VTIN_GND27
THERMTRIP#5,14
PROCHOT#5,14
CPUSLP#14
H_PWRGD5,7
8
C35 X_C0.1U25Y
R65 X_1KR
LL_ID031
HD#[0..63]
B B
A A
VTT_OUT_RIGHT
H_FSBSEL03,5
H_FSBSEL13,5,10
H_FSBSEL23,5
HD#[0..63]7
HDBI#0
HDBI#1
HDBI#2
HDBI#3
EDRDY#
EDRDY#7
IERR#5
FERR#5,14
STPCLK#14
HINIT#14
HDBSY#7
HDRDY#7
HTRDY#7
HADS#7
HLOCK#7
HBNR#7
HIT#7
HITM#7
HBPRI#7
H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK
IGNNE#14
SMI#14
A20M#14,27
CPU_BOOT
LL_ID0 H_COMP1
H_PWRGD
CPURST#5,7
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
HA#[3..31]7
G11
D19
C20
AB2
AB3
AD3
AD1
AF1
AC1
AG1
AE1
AL1
AK1
AE8
AL2
AH2
AE6
G10
D16
A20
AA2
G29
H30
G30
G23
B22
A22
A19
B19
B21
C21
B18
A17
B16
C18
A8
F2
R3
M3
P3
H4
B2
C1
E3
D2
C3
C2
D4
E4
G8
G7
M2
N2
P2
K3
L2
N5
C9
Y1
V2
N1
7
U6A
DBI0#
DBI1#
DBI2#
DBI3#
EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#
RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
BOOTSELECT
LL_ID0
LL_ID1
BSEL0
BSEL1
BSEL2
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
7
D53#
B15
HD#53
HA#[3..31]
D52#
D51#
C14
C15
HD#52
HD#51
6
CPU SIGNAL BLOCK
HA#27
HA#26
HA#25
HA#31
AJ6
AJ5
AH5
AH4
AG5
A35#
A34#
A33#
A32#
D50#
D49#
D48#
D47#
D46#
D45#
A14
E22
D17
D20
D22
G22
G21
HD#50
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
A31#
D44#
HA#30
AG4
F21
HD#43
HA#29
A30#
D43#
HD#42
AG6
E21
HA#28
A29#
D42#
HD#41
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
D27#
E13
HD#26
D26#
D25#
F12
D13
HD#25
HD#24
HA#7
U6
A9#T5A8#R4A7#M4A6#L4A5#M5A4#P6A3#
D24#
D23#
D22#
D21#
F11
E10
D10
HD#23
HD#22
HD#21
HD#20
HA#14
HA#15
AF4
AF5
AB4
AC5
AB5
AA5
AD6
AA4
AB6
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#Y4A19#Y6A18#W6A17#
A16#W5A15#V4A14#V5A13#U4A12#U5A11#T4A10#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
D31#
D30#
D29#
D28#
F20
F18
F17
E19
E18
HD#39
HD#38
HD#37
HD#40
F15
F14
E16
E15
G17
G18
G16
G15
G14
G13
HD#36
HD#35
6
HD#28
HD#30
HD#29
HD#31
HD#34
HD#27
HD#33
HD#32
HA#5
HA#3
HA#6
HA#4
L5
D20#D7D19#E9D18#F9D17#F8D16#G9D15#
D11
HD#15
HD#14
HD#19
HD#18
HD#17
HD#16
AC2
C12
5
DBR#
D14#
B12
HD#13
5
AN3
D13#
HD#12
AN4
RSVD
RSVD
D12#D8D11#
C11
HD#11
VCC_SENSE
AN5
B10
HD#10
R59 X1KR
VSS_SENSE
AJ3
AK3
AN6
ITP_CLK1
VSS_SENSE
VCC_SENSE
D10#
D9#
D8#
D7#A7D6#B7D5#B6D4#A5D3#C6D2#A4D1#C5D0#
A11
A10
HD#7
HD#6
HD#9
HD#8
ITP_CLK0
HD#5
HD#4
HD#3
AM5
VID5
AL4
RSVD
HD#2
VID4
VID5#
HD#1
VID0
VID1
VID3
VID2
AK4
AL6
AM3
AL5
VID4#
VID3#
VID2#
VID1#
GTLREF
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
PCREQ#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
RSVD
RSVD
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP3
COMP2
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
ZIF-SOCK775-15u
B4
HD#0
FP_RST# 3,29,30
VCC_SENSE 31
VSS_SENSE 31
AM2
VID0#
H1
AG3
AF2
AG2
AD2
AJ1
AJ2
G5
J6
K6
M6
J5
K4
W2
P1
H5
G4
G3
F24
G24
G26
G27
G25
F25
W3
F26
AK6
G6
G28
F28
A3
F5
B3
U3
U2
F3
R1
G2
T1
A13
J17
H16
H15
J16
AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1
4
VID[0..5] 27,31
CPU_GTLREF
H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0
PCREQ#
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
H_TESTHI12
H_TESTHI11
H_TESTHI10
H_TESTHI9
H_TESTHI8
H_TESTHI2_7
H_TESTHI1
H_TESTHI0
RSVD_AK6
RSVD_G6
HRS#2
HRS#1
HRS#0
T1
T2
BREQ#0
H_COMP3
H_COMP2
H_COMP0
HADSTB#1
HADSTB#0
HDSTB3
HDSTB2
HDSTB1
HDSTB0
HDSTB#3
HDSTB#2
HDSTB#1
HDSTB#0
NMI
INTR
4
R80 62R
R95 62R
R63 62R
R99 62R
R53 X_62R
R79 X_62R
R67 100R 1%
R81 100R 1%
R66 6 0 . 4R1%
R89 6 0 . 4R1%
T7
T8
T6
T5
3
RN12
H_TESTHI9
H_TESTHI10
H_TESTHI11
H_TESTHI12
PCREQ# 7
HREQ#4 7
HREQ#3 7
HREQ#2 7
HREQ#1 7
HREQ#0 7
CPUCLK-0 3
CPUCLK0 3
HRS#2 7
HRS#1 7
HRS#0 7
BREQ#0 5,7
PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE
HADSTB#1 7
HADSTB#0 7
HDSTB3 7
HDSTB2 7
HDSTB1 7
HDSTB0 7
HDSTB#3 7
HDSTB#2 7
HDSTB#1 7
HDSTB#0 7
NMI 14
INTR 14
1 2
3 4
5 6
7 8
CPU_GTLREF 5
8P4R-62R
VTT_OUT_LEFT
C49
X_C0.1U25Y
3
VTT_OUT_LEFT
V_FSB_VTT 5,7,9,16,29
VTT_OUT_RIGHT 5
VTT_OUT_LEFT 5
VTT_OUT_RIGHT
C41 C0.1U25Y
C45 C0.1U25Y
2
CLOSED TO 965
STPCLK#
HINIT#
SMI#
CPUSLP#
A20M#
INTR
NMI
IGNNE#
R73 49.9RST
R71 49.9RST
R69 49.9RST
R75 49.9RST
RN15
7 8
5 6
3 4
1 2
8P4R-56
RN2
8P4R-680R
VID3
1
VID1
3
VID4
5
VID2
7
VID0
R51 680R
VID5
R50 680R
RN4 8P4R-51R
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
RN6 8P4R-51R
R61 X49.9R1%
R57 X49.9R1%
R56 49.9R1%
PLACE BPM TERM I N A T I O N NEAR CPU
Micro-Star
Title
Document Number
Last Revision Date:
Monday, November 22, 2004
2
For 965
VTT_OUT_RIGHT
2
4
6
8
H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TDI
H_BPM#2
H_BPM#4
H_TDO
H_TMS
H_TCK
H_TRST#
MS7138
LGA775 CPU-1
Sheet of
1
VCCP
Rev
0A
432
1
8
VCCP
AG21
AG19
AG18
AG15
AG14
AG12
AG11
AF9
AF8
AF22
AF21
AF19
AF18
AF15
AF14
AF12
AF11
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23
AE9
AD8
AC8
AB8
AA8
U6B
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCW8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Y8
Y30
Y23
Y24
Y25
Y26
Y27
Y28
Y29
W30
VCCP
D D
C C
AG22
VCC
VCC
W29
AG25
VCC
VCC
W28
AG26
VCC
VCC
W27
AG27
VCC
VCC
W26
AG28
VCC
VCC
W25
AG29
VCC
VCC
W24
7
AG30
VCC
W23
AG8
VCC
AG9
VCC
VCCU8VCCV8VCC
AH11
VCC
VCC
U30
AH12
VCC
VCC
U29
AH14
VCC
VCC
U28
AH15
VCC
VCC
U27
AH18
VCC
VCC
U26
AH19
VCC
VCC
U25
AH21
VCC
VCC
U24
AH22
VCC
U23
AH25
VCC
VCCT8VCC
AH26
VCC
VCC
T30
AH27
VCC
VCC
T29
AH28
VCC
VCC
T28
AH29
VCC
VCC
T27
AH30
VCC
VCC
T26
AH8
T25
VCC
VCC
AH9
T24
VCC
VCC
AJ11
VCC
T23
AJ12
VCC
AJ14
VCC
AJ15
VCC
VCCN8VCCP8VCCR8VCC
6
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AJ9
AK11
AK12
AK14
AK15
AK18
AK19
AK21
AK22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCM8VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
N23
N24
N25
N26
N27
N28
N29
N30
M24
M25
M26
M27
M28
M29
M30
VCC
VCC
AK25
VCC
M23
AK26
VCC
5
AK8
AK9
AL11
AL12
AL14
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
AL30
AL8
AL9
AM11
AM12
AM14
AM15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCJ8VCCJ9VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCK8VCCL8VCC
J22
J23
J24
J25
J26
J27
J28
J29
J30
K23
K24
K25
K26
K27
K28
K29
K30
AM18
VCC
VCC
J21
AM19
VCC
VCC
J20
AM21
VCC
VCC
J19
AM22
VCC
VCC
J18
AM25
VCC
VCC
J15
AM26
VCC
VCC
J14
4
AM29
VCC
VCC
J13
AM30
VCC
VCC
J12
AM8
J11
VCC
VCC
AM9
J10
VCC
VCC
AN11
VCC
VCC
AN9
AN12
AN14
AN15
AN18
AN19
AN21
AN22
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC-IOPLL
VTTPWRGD
VTT_OUT
VTT_OUT
VTT_SEL
RSVD/VTT_PKGSENSE
VCC
VCC
VCC
VCC
VCC
HS11HS22HS33HS4
AN8
AN25
AN26
AN29
AN30
VCCA
VSSA
RSVD
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
4
3
H_VCCA
A23
H_VSSA
B23
D23
H_VCCA
C23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30
VTT_PWG
AM6
VTT_OUT_RIGHT
AA1
VTT_OUT_LEFT
J1
F27
F29
ZIF-SOCK775-15u
VTT_SEL
R103 X_1KR
V_FSB_VTT
TEJ/PSC
0
1
VCC3
RSVD
2
V_FSB_VTT
C71 C1U16Y0805
C81 10u/0805
C80 X_10u/0805
1
CAPS FOR FSB GE NERIC
PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS
100 OHMS OVER 210 OHMS RESISTORS
VTT_OUT_LEFT CPU_GTLREF
B B
GTLREF VOLTAGE SHOULD BE
0.67*VTT = 0.8V
R78 49.9R1%
R74
100R1%
C55
C0.1U25Y
C57
C220P50N
CPU_GTLREF 4
V_FSB_VTT
PLACE AT CPU END OF ROUTE
FERR#
THERMTRIP#
IERR#
CPURST#
7
PROCHOT#
H_PWRGD
BREQ#0
PROCHOT# 4,14
H_PWRGD 4,7
BREQ#0 4,7
FERR# 4,14
THERMTRIP# 4,14
IERR# 4
CPURST# 4,7
FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED
V_FSB_VTT
6
5
RN27
1
3
5
7
8P4R-470R
2
4
6
8
VTT_OUT_RIGHT4
VTT_OUT_LEFT4
VTT_OUT_RIGHT
VTT_OUT_LEFT
R52 120R
R72 100R
R82 62R
PLACE AT ICH END OF ROUTE
A A
V_FSB_VTT4,7,9,16,29
V_FSB_VTT
8
RN49
1 2
3 4
5 6
7 8
8P4R-62R
R107 62R
L9 X_10U100m_0805
CP6
X_COPPER
VID_GD29,31
H_FSBSEL1
H_FSBSEL2
H_FSBSEL0
4
H_FSBSEL1 3,4,10
H_FSBSEL2 3,4
H_FSBSEL0 3,4
5VSB
VTT_OUT_LEFT
R40
1KR
R45
1KR
R42
680R
Q13
N-MMBT3904_SOT23
3
C70
C10U10Y1206
C76
X_C1U10Y
1.25V VTT_PWRGOOD
VTT_PWG
H_VSSA
H_VCCA
Micro-Star
Title
Document Number
Last Revision Date:
Monday, November 22, 2004
2
MS7138
LGA775 CPU-1
Sheet of
Rev
0A
532
1
5
4
3
GTLREF_SEL 7
2
1
B13
H2
RSVDF6RSVD
VSS
VSS
AF27
AF28
T4
J2
RSVD
VSS
AF29
RSVDJ3RSVDN4RSVD
COMP4
VSS
VSS
AF3
AF30
VSS
P5
AF6
T3
VSS
T2
COMP5
VSS
AF7
AG10
Y3
RSVDV1RSVDW1RSVD
VSS
VSS
VSS
AG13
AG16
AG17
VSSY7VSSY5VSSY2VSSW7VSSW4VSSV7VSSV6VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH1
AG7
AG20
AG23
AG24
VSS
AH10
VSS
AH13
VSS
AH16
V30
VSS
AH17
VSSV3VSS
VSS
AH20
V29
VSS
AH23
V28
VSS
VSS
AH24
V27
AH3
VSS
VSS
V26
VSS
VSS
AH6
V25
V24
V23
VSS
VSS
VSS
VSSU7VSSU1VSST7VSST6VSST3VSSR7VSSR5VSS
VSS
VSS
VSS
VSS
AH7
AJ10
AJ13
AJ16
AJ17
VSS
VSS
AJ20
AJ23
VSS
AJ24
VSS
AJ27
VSS
AJ28
VSS
R30
AJ29
VSS
R29
AJ30
VSS
VSS
H17
H18
H19
H20
H21
H22
H23
H24
H25
H26
H27
AM7
VID7#
AN1
VSS
VSS
AN10
AN13
VSS
AN16
H28
H29
VSS
VSS
VSSH3VSSH6VSSH7VSSH8VSSH9VSSJ4VSSJ7VSS
GTLREF_SEL
VSS
VSS
VSS
VSS
AN2
AN17
AN20
VSS
VSS
AN23
VSS
VSS
AN24
VSS
VSS
AN27
AN28
VSS
VSS
VSS
VSS
VID_SELECT
VSSB1VSS
B11
AN7
VSS
VSS
VSS
VSS
VSS
ZIF-SOCK775-15u
B14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H14
H13
H12
H11
H10
G1
F7
F4
F22
F19
F16
F13
F10
E8
E29
E28
E27
E26
E25
E20
E2
E17
E14
E11
D9
D6
D5
D3
D24
D21
D18
D15
D12
C7
C4
C24
C22
C19
C16
C13
C10
B8
B5
B24
B20
B17
R28
R27
R26
R25
R24
R23
P30
P29
P28
P27
P26
P25
P24
P23
VSS
VSS
VSS
VSS
VSS
VSS
VSSR2VSSP7VSSP4VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSN7VSSN6VSSN3VSSM7VSSM1VSSL7VSSL6VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AJ4
AJ7
AK10
AK13
AK16
AK17
AK2
AK20
AK23
AK24
AK27
AK28
AK29
AK30
AK5
AK7
AL10
AL13
AL16
VSS
AL17
VSS
AL20
VSS
VSS
AL23
AL24
VSS
AL27
VSS
L30
AL28
VSS
VSSL3VSS
VSS
AL3
L29
L28
L27
VSS
VSS
VSS
VSS
VSS
AL7
AM1
AM10
L26
VSS
VSS
AM13
L25
VSS
VSS
AM16
L24
VSS
VSS
AM17
L23
VSS
VSS
AM20
VSSK7VSS
VSS
AM23
K5
VSS
AM24
K2
VSS
AM27
VSS
AM28
VSS
AM4
D D
AC4
AE3
AE4
U6C
RSVD
RSVD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE29
VSS
VSS
AE30
RSVD
VSS
VSS
AE5
AE7
AF10
A12
A15
A18
A2
A21
A24
A6
A9
AA23
AA24
AA25
AA26
AA27
AA28
AA29
AA3
AA30
AA6
AA7
C C
B B
AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AE10
AE13
AE16
AE17
AE20
AE24
AE25
AE26
AE27
AE28
AC3
AC6
AC7
AD4
AD7
AE2
AB1
AB7
T11
D14
E23
RSVDD1RSVD
VSS
VSS
AF13
AF16
E24
RSVD
VSS
AF17
RSVD
VSS
AF20
T9
T12
T10
F23
RSVDE5RSVDE6RSVDE7RSVD
VSS
VSS
VSS
VSS
AF23
AF24
AF25
AF26
A A
Micro-Star
Document Number
Last Revision Date:
5
4
3
2
Monday, November 22, 2004
Title
MS7138
LGA775 CPU-1
Sheet of
1
Rev
0A
632
5
A12
B12
B31
J28
A34
B17
D34
J27
B35
A31
B34
E30
B33
C33
A33
D32
C31
A32
D35
C36
G29
E29
D29
D33
J33
K28
L28
L29
J36
K29
H36
K30
H35
K32
H34
J31
J30
H32
J32
G36
G33
H30
G32
H33
G31
F36
F33
F35
F32
F34
F31
E32
E36
E33
D36
F30
D31
H29
U12A
CPUCLK
CPUCLK#
HLOCK#
DEFER#
HTRDY#
CPURST#
CPUPWRGD
BPRI#
BREQ0#
RS0#
RS1#
RS2#
ADS#
HITM#
HIT#
DRDY#
DBSY#
BNR#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HASTB0#
HASTB1#
HA35#
HA34#
HA33#
HA32#
HA31#
HA30#
HA29#
HA28#
HA27#
HA26#
HA25#
HA24#
HA23#
HA22#
HA21#
HA20#
HA19#
HA18#
HA17#
HA16#
HA15#
HA14#
HA13#
HA12#
HA11#
HA10#
HA9#
HA8#
HA7#
HA6#
HA5#
HA4#
HA3#
649/662
HNCOMP
HPCOMP
HD63#
A18
HD#63
D18
HD#62
HD62#
HD61#
D20
HD#61
C1XAVSS
C1XAVDD
F12
E12
C1XAVSS
C1XAVDD
HD60#
HD59#
A20
A19
HD#59
HD#60
E18
HD#58
HVREF
C4XAVSS
C4XAVDD
D13
C13
P25
M23
HVREF0
C4XAVSS
C4XAVDD
Host
HD58#
HD57#
HD56#
HD55#
HD54#
A21
A22
E20
B23
D22
HD#54
HD#56
HD#55
HD#57
HD#53
M21
M19
HVREF1
HVREF2
HD53#
HD52#
A23
C23
HD#51
HD#52
M17
HVREF3
HVREF4
HD51#
HD50#
A24
B21
HD#50
HD#49
HPCOMP
HD49#
HD#48
HIT#4
R122 14R1%
R125 100RST
CPUCLK1
CPUCLK-1
HLOCK#
HDEFER#
HTRDY#
CPURST#
H_PWRGD
HBPRI#
BREQ#0
HRS#2
HRS#1
HRS#0
HADS#
HITM#
HIT#
HDRDY#
HDBSY#
HBNR#
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
HADSTB#1
HADSTB#0
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
HD#[0..63]4
V_FSB_VTT4,5,9,16,29
D D
CPUCLK13
CPUCLK-13
HLOCK#4
HDEFER#4
HTRDY#4
CPURST#4,5
H_PWRGD4,5
HBPRI#4
BREQ#04,5
HRS#24
HRS#14
HRS#04
HADS#4
HITM#4
HDRDY#4
HDBSY#4
HBNR#4
HREQ#44
HREQ#34
HREQ#24
HREQ#14
C C
HA#[3..31]4
B B
HREQ#04
HADSTB#14
HADSTB#04
HNCOMP
B16
A16
HPCOMP
HNCOMP
HD48#
HD47#
J16
B19
HD#47
E16
HD#46
HD46#
HD45#
H16
HD#45
D16
HD#44
HD44#
HD43#
E17
HD#43
VCCP
G17
HD#42
4
HD42#
H18
HD#41
HD41#
HD40#
J18
HD#40
H20
HD#39
HD39#
HD38#
H19
HD#38
PCIEAVSS
EXP_A_RXN_0
EXP_A_RXN_1
PCIEAVDD
AJ2
AJ1
PCIEAVSS
PCIEAVDD
EXP_A_RXP_0
EXP_A_RXN_3
EXP_A_RXN_2
EXP_A_RXP_1
PERp0L7PERn0L8PERp1M5PERn1M6PERp2N7PERn2N8PERp3P5PERn3P6PERp4R7PERn4R8PERp5T5PERn5T6PERp6U7PERn6U8PERp7V5PERn7V6PERp8W7PERn8W8PERp9Y5PERn9
EXP_A_RXN_4
EXP_A_RXP_2
EXP_A_RXP_3
EXP_A_RXP_4
EXP_A_RXP_5
PCI Express
HD37#
HD36#
HD35#
HD34#
HD33#
HD32#
HD31#
HD30#
HD29#
HD28#
HD27#
HD26#
HD25#
HD24#
HD23#
J20
J19
J21
J22
E21
E23
H21
H22
G19
G21
HD#31
HD#35
HD#33
HD#37
HD#34
HD#36
HD#32
H23
G23
HD#28
HD#27
HD#29
HD#26
HD#30
E25
H24
H25
HD#23
HD#24
HD#25
HD#22
V_FSB_VTT 4,5,9,16,29
HD22#
J25
EXP_A_RXN_5
HD#21
EXP_A_RXP_6
HD21#
H26
HD#20
HD20#
H28
EXP_A_RXN_6
G27
HD#19
EXP_A_RXP_7
HD19#
HD18#
E27
HD#18
EXP_A_RXN_7
H27
HD#17
EXP_A_RXP_8
HD17#
HD16#
J26
HD#16
EXP_A_RXN_8
A25
HD#15
EXP_A_RXP_9
HD15#
HD14#
D24
HD#14
EXP_A_RXN_9
Y6
E24
HD#13
EXP_A_RXP_10
AA7
PERp10
HD13#
HD12#
A27
HD#12
EXP_A_RXP_11
EXP_A_RXN_10
AA8
PERn10
HD11#
B25
HD#11
HD#10
EXP_A_RXN_11
AB5
AB6
PERp11
HD10#
A26
C25
HD#9
EXP_A_RXP_12
EXP_A_RXN_12
AC7
AC8
PERn11
PERp12
HD9#
HD8#
D26
D28
HD#8
HD#7
3
EXP_A_RXP_13
EXP_A_RXN_13
AD5
AD6
PERn12
PERp13
HD7#
HD6#
A28
A29
HD#5
HD#6
EXP_A_RXP_14
EXP_A_RXN_14
AF5
PERn13
PERp14
HD5#
HD4#
C29
HD#4
HD#3
EXP_A_RXP_15
AF6
AH4
PERn14
HD3#
E28
D30
HD#2
EXP_A_RXN_15
AH5
PERp15
PERn15
HD2#
HD1#
B29
HD#1
HD#0
PCIERSET0
PCIERSET1
HDSTBN3#
HDSTBN2#
HDSTBN1#
HDSTBN0#
HDSTBP3#
HDSTBP2#
HDSTBP1#
HDSTBP0#
HD0#
A30
HDBI#3
PETp0
PETn0
PETp1
PETn1
PETp2
PETn2
PETp3
PETn3
PETp4
PETn4
PETp5
PETn5
PETp6
PETn6
PETp7
PETn7
PETp8
PETn8
PETp9
PETn9
PETp10
PETn10
PETp11
PETn11
PETp12
PETn12
PETp13
PETn13
PETp14
PETn14
PETp15
PETn15
REFCLK+
REFCLK-
INTX#
PCREQ#
EDRDY#
DBI3#
DBI2#
E19
C19
HDBI#2
HDBI#1
PME#
NC0
DBI1#
J23
HDBI#0
DBI0#
C27
EXP_A_TXP_0
M3
EXP_A_TXN_0
N3
EXP_A_TXP_1
N1
EXP_A_TXN_1
P1
EXP_A_TXP_2
P3
EXP_A_TXN_2
R3
EXP_A_TXP_3
R1
EXP_A_TXN_3
T1
EXP_A_TXP_4
T3
EXP_A_TXN_4
U3
EXP_A_TXP_5
U1
EXP_A_TXN_5
V1
EXP_A_TXP_6
V3
EXP_A_TXN_6
W3
EXP_A_TXP_7
W1
EXP_A_TXN_7
Y1
EXP_A_TXP_8
Y3
EXP_A_TXN_8
AA3
EXP_A_TXP_9
AA1
EXP_A_TXN_9
AB1
EXP_A_TXP_10
AB3
EXP_A_TXN_10
AC3
EXP_A_TXP_11
AC1
EXP_A_TXN_11
AD1
EXP_A_TXP_12
AD3
EXP_A_TXN_12
AE3
EXP_A_TXP_13
AE1
EXP_A_TXN_13
AF1
EXP_A_TXP_14
AF3
EXP_A_TXN_14
AG3
EXP_A_TXP_15
AG1
EXP_A_TXN_15
AH1
CK_PE_100M_MCH
L1
CK_PE_100M_MCH#
L2
AH3
AJ3
E11
F11
H_PCREQ#
C35
H_EDRDY#
C34
A17
HDSTB#3
E22
HDSTB#2
H17
HDSTB#1
J24
HDSTB#0
B27
HDSTB3
C21
HDSTB2
J17
HDSTB1
G25
HDSTB0
E26
HDBI#[0..3] 4
EXP_A_RXP_[0..15] 21
EXP_A_RXN_[0..15] 21
EXP_A_TXP_0 21
EXP_A_TXN_0 21
EXP_A_TXP_1 21
EXP_A_TXN_1 21
EXP_A_TXP_2 21
EXP_A_TXN_2 21
EXP_A_TXP_3 21
EXP_A_TXN_3 21
EXP_A_TXP_4 21
EXP_A_TXN_4 21
EXP_A_TXP_5 21
EXP_A_TXN_5 21
EXP_A_TXP_6 21
EXP_A_TXN_6 21
EXP_A_TXP_7 21
EXP_A_TXN_7 21
EXP_A_TXP_8 21
EXP_A_TXN_8 21
EXP_A_TXP_9 21
EXP_A_TXN_9 21
EXP_A_TXP_10 21
EXP_A_TXN_10 21
EXP_A_TXP_11 21
EXP_A_TXN_11 21
EXP_A_TXP_12 21
EXP_A_TXN_12 21
EXP_A_TXP_13 21
EXP_A_TXN_13 21
EXP_A_TXP_14 21
EXP_A_TXN_14 21
EXP_A_TXP_15 21
EXP_A_TXN_15 21
CK_PE_100M_MCH 3
R207 4 99R1%
R208 1 24R1%
CK_PE_100M_MCH# 3
INTA# 10,13,19
PCREQ# 4
EDRDY# 4
HDSTB#3 4
HDSTB#2 4
HDSTB#1 4
HDSTB#0 4
HDSTB3 4
HDSTB2 4
HDSTB1 4
HDSTB0 4
2
VCC1_8 VCC1_8
L20
CP13
C124
X_103P
L21
L17
X_80S/0603
C118
X_103P
L15
X_80S/0603
X_COPPER
C1XAVDD
CB68
0.1u
C1XAVSS
CP14
X_COPPER
CP9
X_COPPER
C4XAVDD
CB63
0.1u
C4XAVSS
CP8
X_COPPER
X_80S/0603
X_80S/0603
VCC1_8
1
L36
X_80S/0603
C223
X_103P
L35
X_80S/0603
CP29
X_COPPER
PCIEAVDD
CB84
0.1u
PCIEAVSS
CP28
X_COPPER
Closed to SIS649
R104
619R1%
A A
5
GTLREF_SEL6
2N7002S
Q27
R102
169R1%
4
R93
100R1%
C100
0.1u
C89
X_103P
HVREF
C377
0.1u
Please this capacitor
under 649/662 solder side.
Micro-Star
Document Number
Last Revision Date:
3
2
Monday, November 22, 2004
Title
MS7138
SIS 649-Host & AGP
Sheet of
1
Rev
0A
732
5
M34
M36
M35
W36
AB35
AB34
W33
W32
AA32
AB36
AA33
AA36
AH30
AJ32
AM30
AN30
AG29
AH32
AM32
AN32
AJ30
AL32
AK32
AH24
AH23
AH21
AM20
AJ24
AJ23
AJ21
AH22
AM22
AJ22
AK22
AM19
AT18
AT16
AR16
AT19
AN19
AN17
AM17
AR18
AT17
AP18
AN15
AM15
AM13
AT12
AP16
AT15
AT13
AN13
AT14
AP14
AR14
AT11
AN11
AR9
AR12
AP12
AP10
AM11
AR10
AT10
U12B
MD0A
N36
MD1A
R36
MD2A
R33
MD3A
MD4A
MD5A
P35
MD6A
P34
MD7A
N33
DQM0A
P36
DQS0A
N32
DQS0A#
T35
MD8A
T34
MD9A
V34
MD10A
MD11A
R32
MD12A
T36
MD13A
V36
MD14A
V35
MD15A
U36
DQM1A
U32
DQS1A
U33
DQS1A#
Y36
MD16A
Y35
MD17A
MD18A
MD19A
MD20A
MD21A
MD22A
MD23A
Y34
DQM2A
DQS2A
DQS2A#
MD24A
MD25A
MD26A
MD27A
MD28A
MD29A
MD30A
MD31A
DQM3A
DQS3A
DQS3A#
MD32A
MD33A
MD34A
MD35A
MD36A
MD37A
MD38A
MD39A
DQM4A
DQS4A
DQS4A#
MD40A
MD41A
MD42A
MD43A
MD44A
MD45A
MD46A
MD47A
DQM5A
DQS5A
DQS5A#
MD48A
MD49A
MD50A
MD51A
MD52A
MD53A
MD54A
MD55A
DQM6A
DQS6A
DQS6A#
MD56A
MD57A
MD58A
AP9
MD59A
MD60A
MD61A
MD62A
AT9
MD63A
DQM7A
DQS7A
DQS7A#
649/662
RMD0
RMD1
RMD2
RMD3
RMD4
RMD5
RMD6
RMD7
RDQM0
D D
C C
B B
RDQS0
RMD8
RMD9
RMD10
RMD11
RMD12
RMD13
RMD14
RMD15
RDQM1
RDQS1
RMD16
RMD17
RMD18
RMD19
RMD20
RMD21
RMD22
RMD23
RDQM2
RDQS2
RMD24
RMD25
RMD26
RMD27
RMD28
RMD29
RMD30
RMD31
RDQM3
RDQS3
RMD32
RMD33
RMD34
RMD35
RMD36
RMD37
RMD38
RMD39
RDQM4
RDQS4
RMD40
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RDQM5
RDQS5
RMD48
RMD49
RMD50
RMD51
RMD52
RMD53
RMD54
RMD55
RDQM6
RDQS6
RMD56
RMD57
RMD58
RMD59
RMD60
RMD61
RMD62
RMD63
RDQM7
RDQS7
4
MA0A
MA1A
MA2A
MA3A
MA4A
MA5A
MA6A
MA7A
MA8A
MA9A
MA10A
MA11A
MA12A
MA13A
MA14A
MA15A
RASA#
CASA#
WEA#
FWDSDCLKOA
FWDSDCLKOA#
CS0A#
CS1A#
CS2A#
CS3A#
ODT0A
ODT1A
ODT2A
ODT3A
CKE0A
CKE1A
CKE2A
CKE3A
D1XAVDD
D1XAVSS
D4XAVDD
D4XAVSS
DDRVREF0
DDRVREF1
DDRVREF2
DDRVREF3
DDRCOMP
DDRCOMN
OCDVREFP
OCDVREFN
S3AUXSW#
DRAM_SEL
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
3
RMD[0..63]
RDQM[0..7]
C84
X_0.1u
RDQS[0..7]
RMA[0..15]
RCS-[0..3]
CKE[0..3]
C139
0.1u
C153
0.1u
C44
0.1u
RMA0
AP33
RMA1
AN33
RMA2
AT34
RMA3
AR34
RMA4
AR35
RMA5
AP34
RMA6
AP35
RMA7
AM33
RMA8
AP36
RMA9
AN36
RMA10
AT33
RMA11
AR32
RMA12
AP32
RMA13
AM35
RMA14
AN34
RMA15
AM34
AM29
AM36
RSRAS#
AT32
RSCAS#
AP30
RSWE#
AT31
K36
K35
K34
L36
RCS-0
AM31
RCS-1
AN29
RCS-2
AN31
RCS-3
AT29
AR30
AP28
AT30
AR28
AJ33
CKE0
AH34
CKE1
AJ36
CKE2
AL34
CKE3
AL33
AH36
AH35
AK34
AL36
AJ34
AK35
AK36
DLLAVDD
A13
DLLAVSS
B13
DDRAVDD
AH28
DDRAVSS
AJ28
DDRVREF0
AE19
AE23
AC25
V25
R124 3 6R 1% C378
AJ29
R123 3 6R 1%
AH29
AR8
AT8
R164 22
F13
R171 4 .7K
B11
R117 22
S3AUXSW#
VCCM
RSRAS# 11,12
RSCAS# 11,12
RSWE# 11,12
FWDSDCLKOFWDSDCLKA
VCCM
S3AUXSW# 29
C108
10p
FWDSDCLKO 3
DIMM DECOUPLING
VCCM
VCCM
RMD[0..63] 11,12
RDQM[0..7] 11,12
RDQS[0..7] 11,12
RMA[0..15] 11,12
RCS-[0..3] 11,12
CKE[0..3] 11
C122
C159
X_1u
0.1u
C125
X_1u
2
VCC1_8 VCC1_8
VCCM
R109
150RST
R108
150RST
C103
X_4.7U/0805
C22
C168
0.1u
0.1u
Place these capacitors under SIS649 solder side
VCCM VCC1_8
C380
X_0.1u
CP12
X_COPPER
L19
DLLAVDD DDRAVDD
X_80S/0603
C120
CB66
0.1u
X_103P
DLLAVSS
CP10
X_COPPER
L18
X_80S/0603
C107
X_103P
DDRVREF0
C111
C376
103P
X_0.1u
place under 649/662 solder side
C381
X_0.1u
X_0.1u
1
L30
X_80S/0603
C175
X_103P
L29
X_80S/0603
DDRAVSS
C384
X_1u
CP22
X_COPPER
CB82
0.1u
CP20
X_COPPER
C383
X_1u
A A
Micro-Star
Document Number
Last Revision Date:
5
4
3
2
Monday, November 22, 2004
Title
MS7138
SIS 649-Memory
Sheet of
1
Rev
0A
832
5
4
3
2
1
VCCM
U12D
V23
VCCM
V24
VCCM
W23
VCCM
W24
VCCM
IVDD
AC19
AC20
AC21
AC22
AC23
AC24
AD19
AD20
AD21
AD22
AD23
AD24
AG34
AG35
AN35
AR21
AR23
AR25
AR27
AR29
AR31
AR33
AC16
AC17
AC18
AD16
AD17
AD18
AA23
AA24
AB23
AB24
AP31
AA22
AB16
AB17
AB18
AB19
AB20
AB21
AB22
Y23
VCCM
Y24
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
VCCM
N20
IVDD
N21
IVDD
N22
IVDD
N23
IVDD
N24
IVDD
P20
IVDD
P21
IVDD
P22
IVDD
P23
IVDD
P24
IVDD
R22
IVDD
R23
IVDD
R24
IVDD
T22
IVDD
T23
IVDD
T24
IVDD
U22
IVDD
U23
IVDD
U24
IVDD
V22
IVDD
W22
IVDD
Y22
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
H7
VDDVB1.8
H8
VDDVB1.8
H9
VDDVB1.8
J7
VDDVB1.8
J8
VDDVB1.8
J9
VDDVB1.8
K9
VDDVB1.8
A9
VDD3.3
A10
AUX1.8
A11
AUX3.3
649/662
Power
D D
C C
VDDPEX_N
(Reserved Pins
B B
A A
for SiS662)
VCC3
SB1.8V
VCC3SBY
V_FSB_VTT
V_FSB_VTT4,5,7,16,29
A14
VTT
A15
VTT
B14
VTT
B15
VTT
C14
VTT
C15
VTT
D14
VTT
D15
VTT
E14
VTT
E15
VTT
F14
VTT
F15
VTT
G14
VTT
G15
VTT
H14
VTT
H15
VTT
J14
VTT
J15
VTT
K14
VTT
K15
VTT
N15
VTT
N16
VTT
N17
VTT
N18
VTT
N19
VTT
P15
VTT
P16
VTT
P17
VTT
P18
VTT
P19
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
PVDDH
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VDDPEX
VTT
Y13
Y14
Y15
AA13
AA14
AA15
AB13
AB14
AB15
AC13
AC14
AC15
AD13
AD14
AD15
AD9
AE8
AE9
AF8
AF9
AG7
AG8
AG9
AH7
AH8
AH9
AJ6
AJ7
AJ8
AJ9
AK6
AK7
AK8
AK9
AL6
AL7
AL8
AL9
AM7
AM8
AN2
AN5
AN7
AP1
AR3
AR4
AT5
R15
R16
R17
R18
R19
R20
R21
T15
U15
V15
W15
N13
N14
P13
P14
R13
R14
T13
T14
U13
U14
V13
V14
W13
W14
VCC1_8
VDDPEX_N
U12E
B18
VSS
B20
VSS
B22
VSS
B24
VSS
B26
VSS
B28
VSS
B30
VSS
B32
VSS
C17
VSS
E31
VSS
E35
VSS
F17
VSS
F19
VSS
F21
VSS
F23
VSS
F25
VSS
F27
VSS
F29
VSS
G16
VSS
G18
VSS
G20
VSS
G22
VSS
G24
VSS
G26
VSS
G28
VSS
G30
VSS
G35
VSS
H31
VSS
J29
VSS
J35
VSS
K1
VSS
K7
VSS
K8
VSS
K17
VSS
K19
VSS
K21
VSS
K23
VSS
K25
VSS
K27
VSS
K31
VSS
L3
VSS
L4
VSS
L5
VSS
L6
VSS
L9
VSS
L30
VSS
L32
VSS
L33
VSS
L35
VSS
M1
VSS
M2
VSS
M4
VSS
M7
VSS
M8
VSS
M9
VSS
M27
VSS
M31
VSS
M32
VSS
N2
VSS
N4
VSS
N5
VSS
N6
VSS
N9
VSS
N30
VSS
N35
VSS
P2
VSS
P4
VSS
P7
VSS
P8
VSS
P9
VSS
P27
VSS
P31
VSS
R2
VSS
R4
VSS
R5
VSS
R6
VSS
R9
VSS
R30
VSS
R35
VSS
T2
VSS
T4
VSS
T7
VSS
T8
VSS
T9
VSS
T27
VSS
T31
VSS
U2
VSS
U4
VSS
U5
VSS
U6
VSS
U9
VSS
U30
VSS
U35
VSS
V2
VSS
V4
VSS
V7
VSS
V8
VSS
V9
VSS
V27
VSS
V31
VSS
T16
VSS
T17
VSS
T18
VSS
T19
VSS
T20
VSS
T21
VSS
U16
VSS
U17
VSS
U18
VSS
U19
VSS
U20
VSS
U21
VSS
V16
VSS
V17
VSS
V18
VSS
V19
VSS
V20
VSS
V21
VSS
649/662
Ground
W2
VSS
W4
VSS
W5
VSS
W6
VSS
W9
VSS
W16
VSS
W17
VSS
W18
VSS
W19
VSS
W20
VSS
W21
VSS
W30
VSS
W35
VSS
Y2
VSS
Y4
VSS
Y7
VSS
Y8
VSS
Y9
VSS
Y16
VSS
Y17
VSS
Y18
VSS
Y19
VSS
Y20
VSS
Y21
VSS
Y27
VSS
Y31
VSS
AA2
VSS
AA4
VSS
AA5
VSS
AA6
VSS
AA9
VSS
AA16
VSS
AA17
VSS
AA18
VSS
AA19
VSS
AA20
VSS
AA21
VSS
AA30
VSS
AA35
VSS
AB2
VSS
AB4
VSS
AB7
VSS
AB8
VSS
AB9
VSS
AB27
VSS
AB31
VSS
AC2
VSS
AC4
VSS
AC5
VSS
AC6
VSS
AC9
VSS
AC30
VSS
AC35
VSS
AD2
VSS
AD4
VSS
AD7
VSS
AD8
VSS
AD27
VSS
AD31
VSS
AE2
VSS
AE4
VSS
AE5
VSS
AE6
VSS
AE7
VSS
AE30
VSS
AE35
VSS
AF2
VSS
AF4
VSS
AF7
VSS
AF28
VSS
AF31
VSS
AG2
VSS
AG4
VSS
AG5
VSS
AG6
VSS
AG12
VSS
AG14
VSS
AG16
VSS
AG18
VSS
AG20
VSS
AG22
VSS
AG24
VSS
AG26
VSS
AG30
VSS
AH2
VSS
AH6
VSS
AH31
VSS
AJ4
VSS
AJ5
VSS
AJ35
VSS
AK2
VSS
AK4
VSS
AK11
VSS
AK13
VSS
AK15
VSS
AK17
VSS
AK19
VSS
AK21
VSS
AK23
VSS
AK25
VSS
AK27
VSS
AK29
VSS
AK31
VSS
AL1
VSS
AL10
VSS
AL12
VSS
AL14
VSS
AL16
VSS
AL18
VSS
AL20
VSS
AL22
VSS
AL24
VSS
AL26
VSS
AL28
VSS
AL30
VSS
AL35
VSS
AM3
VSS
AM5
VSS
AR11
VSS
AR13
VSS
AR15
VSS
AR17
VSS
AR19
VSS
IVDD
C379 X_C0.1U25Y
C225 C0.1U25Y
V_FSB_VTT
CB113 X_0.1u
Please these capacitors under 649/662 solder side
VDDPEX_N
VDDPEX_N VCC1_8
CB115 X_0.1u
VCCM
CB189 X_1u
CB185 X_1u
CB190 X_1u
CB193 X_0.1u
CB194 X_0.1u
IVDD
C160
0.1u
CB118 X_1u
CB117 X_1u
CB123 X_0.1uCB114 X_0.1u
CB116 X_0.1u
CB112 X_0.1u
MSI
Title
Size Docum ent Number Rev
5
4
3
2
Date: Sheet
MICRO-STAR INt'L CO., LTD.
SIS 649 POWER, GND
MS7138
1
932Monday, November 22, 2004
of
0A
5
VCC1_8 VCC1_8
ZCLK03
CP27
L34
X_80S/0603
D D
X_80S/0603
VCC1_8
C C
VCC1_8
X_COPPER
Z1XAVDD
CB83
C184
0.1u
X_0.1u
Z1XAVSS Z4XAVSS
L33
CP26
X_COPPER
R202 56R
R199 56R
C170
R205
150RST
X_0.1u
ZVREF
C186
R212
49.9RST
0.1u
L32
X_80S/0603
C172
X_0.1u
L31
X_80S/0603
ZCMP_N
ZCMP_P
CP25
X_COPPER
Z4XAVDD
CB81
0.1u
CP23
X_COPPER
VCC3
Open for 649/662 co-layout
Short for 662
ZUREQ13
ZDREQ13
ZSTB013
ZSTB-013
ZSTB113
ZSTB-113
ZAD[16..0]13
ROUT24
GOUT24
BOUT24
HSYNC24
VSYNC24
DDC1CLK24
DDC1DATA24
R130 G _4.7K
R134 G _4.7K
R135 G _4.7K
DCLK3
INTA#7,13,19
Enable Disable
RSYNC
LSYNC
B B
CSYNC VB
VGA
panel link
1
1
1
0
0
0
R153
4
ZCLK0
ZUREQ
ZDREQ
ZSTB0
ZSTB-0
ZSTB1
ZSTB-1
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5
ZAD6
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
ZVREF
ZCMP_N
ZCMP_P
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
VCOMP
VRSET
VVBWN
CSYNC
RSYNC
LSYNC
DACAVDD
DACAVSS
DACAVDD
DACAVSS
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
3
RSMRST#
C161 X_C0.1U25Y
MS7_POK
U12C
AK1
ZCLK
AN6
ZUREQ
AM6
ZDREQ
AL3
ZSTB0
AK3
ZSTB0#
AT4
ZSTB1
AT3
ZSTB1#
AL5
ZAD0
AP5
ZAD1
AK5
ZAD2
AM4
ZAD3
AR5
ZAD4
AL4
ZAD5
AN4
ZAD6
AP4
ZAD7
ZAD8
ZAD9
ZAD10
ZAD11
ZAD12
ZAD13
ZAD14
ZAD15
ZAD16
ZVREF
ZCMP_N
ZCMP_P
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
ROUT
GOUT
BOUT
HSYNC
VSYNC
VGPIO0
VGPIO1
VCOMP
VVBWN
VRSET
LSYNC
RSYNC
CSYNC
VOSCI
INTA#
DACAVDD1
DACAVSS1
DACAVDD2
DACAVSS2
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
649/662
MuTIOL
VGA
VSSB5VSSB6VSSC3VSSD1VSSE5VSSF3VSSG1VSSH5VSSJ3VSS
C12
AM2
AP3
AL2
AN1
AN3
AM1
AR2
AP2
AP6
AP7
AP8
AN8
AT6
AR6
AT7
AR7
A6
C6
B7
A7
C7
D7
A8
B8
C8
B9
B10
C10
C9
E8
G_0
F10
D10
E10
D9
E9
D6
E6
E7
F7
VB
TESTMODE0
TESTMODE1
TESTMODE2
ENTEST
TRAP0
TRAP1
TRAP2
AUXOK
PWROK
PCIRST#
VADE
VAD0
VAD1
VAD2
VAD3
VAD4
VAD5
VAD6
VAD7
VAD8
VAD9
VAD10
VAD11
VAGCLK
VAGCLKN
VAVSYNC
VAHSYNC
VBDE
VBD0
VBD1
VBD2
VBD3
VBD4
VBD5
VBD6
VBD7
VBD8
VBD9
VBD10
VBD11
VBGCLK
VBGCLKN
VBVSYNC
VBHSYNC
VBCTL0
VBCTL1
VBHCLK
VBCAD
VBCLK
AGPIO2
AGPIO3
F9
G6
G7
F6
G8
G9
F8
E13
C11
D12
D5
D2
C1
C2
B2
B3
G4
G5
E4
D3
D4
A3
C4
F5
K4
A4
B4
H4
J4
J1
J2
H2
H1
G3
F1
F2
F4
E1
E2
E3
G2
K6
H3
K2
K3
H6
A5
C5
J5
J6
K5
ENTEST
TMODE0
TMODE2
RSMRST#
MS7_POK
PCIRST1#
C119 X_C0.1U25Y
R145 4 .7KR
RSMRST# 14,17,27,29
MS7_POK 14,29
PCIRST1# 18,21,27,29
Reserved for SIS662
VCC1_8 VCC3 VCC3
L23
80S/0603
C135
G_0.1u
L22
80S/0603
2
C130 G_0.1u
C133 G_0.1u
C134
G_1u
R142 G_130RST
DACAVDD
DACAVSS
VVBWN
VCOMP
VRSET
L26
X_80S/0603
C144
X_0.1u
L27
X_80S/0603
CP17
X_COPPER
ECLKAVDD
CB75
G_0.1u
ECLKAVSS
CP18
X_COPPER
1
L24
X_80S/0603
C138
X_0.1u
L25
X_80S/0603
CP15
X_COPPER
DCLKAVDD
CB73
G_0.1u
DCLKAVSS
CP16
X_COPPER
BSEL function for 775 CPU
R151
R176
10K
10K
TMODE0
A A
H_FSBSEL1
H_FSBSEL13,4,5
R150 10K
5
Q34
N-MMBT3904_SOT23
R159 33
Q35
N-MMBT3904_SOT23
VCCP
4
R152
N-MMBT3904_SOT23
VCC3
VCC3VCC3 VCC3
R180
R165
10K
10K
TMODE2
R157 33
Q37
10K
Q36
N-MMBT3904_SOT23
Micro-Star
Document Number
Last Revision Date:
3
2
Monday, November 22, 2004
Title
MS7138
SIS 649-Power & HyperZip
Sheet of
1
Rev
0A
10 32
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