MSI MS-7102 Schematics

5

4

3

2

1

Version 0A

MS-7102

VIA (R) K8T800(8385)/K8M800(8380) / VT8237 Chipset
AMD PGA 754 Processor Schematics

D D

*AMD PGA 754 Processor
*VIA K8T800/K8M800 / VT8237 Chipset

(DDR 400 / AGP 8X / VLink 8X)
*Winbond 83687THF-VF LPC I/O
*VT6103 PHY 10 / 100
*AC'97 Codec ALC655 Codec
*USB 2.0 support (integrated into VT8237)
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 3
*DDR DIMM * 2

C C

K8T800

8237CD

4MB ROM

B B

Orcad Config ERP BOM

SMT5010
SMT5020

07/21/2004 Update

?
?
?

DIP

Total

?

Function Description

Create
Date.

Title Page

Cover Sheet 1
Block Diagram

Clock Synthesizer 7
System Memory

DDR DIMM 1 & 2 8
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T800/K8M800(HT)

VGA Connector
SB VT8237
PCI Connectors 1 & 2 & 3
FAN
AC97 Codec &

Audio Connector
ATA 66/100/133
VT6103 PHY 10/100
Front & Rear USB Port
LPC I/O W83687THF & Floppy
Hardware monitor/Fan/BIOS
Keyboard/Mouse & I/O Ports.
ACPI Power (MS6)
K8 Vcore power
PowerOK Circuit

/Front Panel
BULK / Decoupling
Power Generation
Manual Parts
History

2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket

9
10
11,12,13
14AGP SLOT 8X
15
16,17,18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

Cover Sheet

MS-7102

1

Last Revision Date:
Sheet

Rev

0A

Wednesday, July 21, 2004

1 36

of

5

Block Diagram

4

3

2

1

CPUCLK+ & CPUCLK-(100/133/166/200)

D D

HCLK+ & HCLK-(100/133/166/200) / GCLK(66)

AMD K8

Socket 754

HyperTransfer

SYSTEM CLOCK
Synthesizer

AGPCLK(66)

A

AGP 8X /Fast Write

C C

G
P

VIA

K8T800

DDR400

R,G,B,HSYNC,VSYNC

DDR * 2

VGA Connector

K8M800

VCLK(66) / OSC(14) / PCISB(33) / USBCLK(48) / APICCLK(14)

10/100 BaseT
Lan

B B

PCI 2

PCI 1

PCI 3

PCICLK[0~2]

PCI33

MII Interface

PCI Bus

AC'97 Link

VIA

VT8237

VLINK

Dual ATA
100/133

VT8237 S-ATA

IDE Slot
==>ATA66,100,133 *2

SATA Connector

SATA x2

LPC BUS

USB

A A

AC_14(14)

SIOPCLK(33)/SIO48M(48)

5

Onboard AC'97
Codec

4

Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *2 ,
Back-Port *2

3

SUPER I/O
W83687THF

X BUS

ROM Floopy Parallel Serial

Title

Document Number

2

Micro Star Restricted Secret

Block Diagram

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7102

1

Keyboard

Last Revision Date:

Wednesday, July 21, 2004

Sheet

2

Mouse

of

Rev

0A

36

5

4

3

2

1

GPIO FUNCTION

VT8237 GPIO Function Define

D D

PIN NAME Function define

GPO0 (VSUS33)

GPO1/SUSA#(VSUS33)

GPO2/SUSB#(VSUS33)

GPO3/SUSST1#(VSUS33)

GPO4/SUSCLK(VSUS33)

GPO5/CPUSTP#

GPO6/PCISTP#

GPO7/SLP#

GPO8/GPI8/IPBIN0

GPO9/GPI9/IPBIN1

C C

GPO10/GPI10/IPBRDFR

GPO11/GPI11/IPBRDCK

GPO12/GPI12/IPBOUT0

GPO13/GPI13/IPBOUT1

GPO14/GPI14/IPBTDFR

GPO15/GPI15/IPBTDCK

GPO16/SA16/STRAP

GPO17/SA17/STRAP

GPO18/SA18/STRAP

B B

GPO19/SA19/STRAP

GPO20/GPI20
/ACSDIN2/PCS0#/EI

GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#

GPO22/GPI22/IOR#

GPO23/GPI23/IOW#

GPO24/GPI24/GPIOA

GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2

(VSUS33)
GPO27/GPI27/SMBCK2

(VSUS33)
GPO28/GPI28/

APICD0/APICCS#
GPO29/GPI29/

A A

APICD1/APICACK#

GPO30/GPI30/GPIOD

GPO31/GPI31/GPIOE

Default
Function

GPO0

SUSA#

SUSB#

SUSST1#

SUSCLK

CPUSTP#

PCISTP#

GPO7

GPI8

GPI9

GPI10

GPI11

GPI12

GPI13

GPI14

GPI15

SA16

SA17

SA18

SA19

GPI20

GPI21

GPI22

GPI23

GPI24

GPI25

SMBDT2

SMBCK2

SUSLED ( Power LED )

5V_STR Control on S5

SUSB#

SUSST#

NA

NA

NA

NA

NA

JBAT1

NA

NA

CPUFAN CTL for LEGEND

SFAN CTL for LEGEND

BIOS_WP for LEGEND

NA

LDT Freq Strapping Bit0

LDT Freq Strapping Bit1

LDT Width (Low=8 Bit)

Fast Command (Low=Disable)

NA

NA

NA

NA

NA

NA

SMBDATA2/Slave SMBUS

SMBCLK2/Slave SMBUS

CLEAR_CMOS#

NA

GPI30

GPI31

5

NA

NA

4

Pull up / down

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

As GPI

As GPI
As GPO:H=>can flash(default)

As GPO:L=>can't flash

Pull up to VCC3

Pull up to VCC3

Pull down to GND

Pull down to GND

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

PIN NAME

GPI1 (VSUS33)
GPI2/EXTSMI#

(VSUS33)
GPI3/RING#

(VSUS33)
GPI4/LID#

(VSUS33)
GPI5/BATLOW#

(VSUS33)

GPI6/PME#

GPI7/SMBALRT#
GPI16/INTRUDER#

(VBAT)

GPI17/CPUMISS

GPI18/AOLGP1/THRM#

PCI Routing

DEVICES

PCI SLOT 1

PCI SLOT 2

PCI SLOT 3

PCI SLOT 2

(MEDION 2nd)

1394

3

INT#

INT#A
INT#B
INT#C
INT#D

INT#B
INT#C
INT#D
INT#A

INT#C
INT#D
INT#A
INT#B

Default

GPI0

GPI1

EXTSMI#

RING#

LID#

BATLOW#

NA Pull up to VBATGPI0 (VBAT)

ATADET0=>Detect IDE1 ATA100/66

EXTSMI#

RING#

ATADET1=>Detect IDE2 ATA100/66

Clear Password

PCI_PME#

GPI7

INTRUDER#

CPUMISS

AOLGP1

NA

NA

NA

THRM#

IORDY

IDSEL

AD16

AD17

AD18

AD19 PCICLK4INT#A

AD25INT#D 1394_PCLK

REQ#/GNT#

PREQ#1
PGNT#1

PREQ#2
PGNT#2

PREQ#3
PGNT#3

PREQ#4
PGNT#4

PREQ#5
PGNT#5

2

CLOCK

PCICLK1

PCICLK2

PCICLK3

Pull up / downFunction defineFunction

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VBAT

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VCC3NAGPI19/IORDY

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

GPIO Spec.

MS-7102

Last Revision Date:

Thursday, July 22, 2004

Sheet

3 36

1

Rev

0A

of

5

DDR_VREF routed as 40~50 mils
trace wide , Space>25 mils

DDR_VREF<8>

VDD_25_SUS

Bottom Side

DDR_VREF

R72 15RST
R73 15RST

MD[63..0]<10>

MEMDM[7..0]<10>

-MDQS[7..0]<10>

5

C455

X_102P/BOT

AMD DG=34.8 OHM

D D

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

C C

B B

A A

MEMZN
MEMZP

MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

MEMDM7
MEMDM6
MEMDM5
MEMDM4
MEMDM3
MEMDM2
MEMDM1
MEMDM0

-MDQS7

-MDQS6

-MDQS5

-MDQS4

-MDQS3

-MDQS2

-MDQS1

-MDQS0

AE13

AG12

D14
C14

A16
B15
A12
B11
A17
A15
C13
A11
A10

C11

AC1
AC3

AC2
AD1
AE1
AE3
AG3

AJ4

AE2

AF1

AH3

AJ3
AJ5
AJ6

AJ7
AH9
AG5
AH5

AJ9

AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16

A13

AA1
AG1
AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

C43
X_102P

B9
C7
A6

A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2

M1
W1
W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

VTT_SENSE

MEMVREF1
MEMZN

MEMZP

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

VTT_DDR_SUS

MEMORY INTERFACE

U7B

VTT_A

VTT_B

MEMRESET_L

MEMCKEA
MEMCKEB

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

RSVD_MEMADDA15
RSVD_MEMADDA14

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

RSVD_MEMADDB15
RSVD_MEMADDB14

MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10

MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

4

VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4

4

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

AG10
AE8

AE7
D10

C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

VTT_DDR_SUS

MCKE0
MCKE1

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4

MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

-MCS3

-MCS2

-MCS1

-MCS0

-MSRASA

-MSCASA

MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

X_1u_B

MCKE0 <8,9>
MCKE1 <8,9>

MEMCLK_H[7..0] <8,9>
MEMCLK_L[7..0] <8,9>

-MCS3 <8,9>

-MCS2 <8,9>

-MCS1 <8,9>

-MCS0 <8,9>

-MSRASA <8,9>

-MSCASA <8,9>

-MSWEA <8,9>
MEMBANKA1 <8,9>

MEMBANKA0 <8,9>

MAA[13..0] <8,9>

-MSRASB <8,9>

-MSCASB <8,9>

-MSWEB <8,9>
MEMBANKB1 <8,9>

MEMBANKB0 <8,9>

MAB[13..0] <8,9>

VDD_25_SUS

C456

3

C462

X_1u_B

3

Bottom Side

X_1u_B

C457

X_1u_B

CADIP[0..15]<11>

CLKIP1<11>

CLKIN1<11>

CLKIP0<11>

CLKIN0<11>

VLDT0

CTLIP0<11>
CTLIN0<11>

X_1u_B

C469

R56 49.9RST
R46 49.9RST

C475

VDD_12_A

CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0

CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3

CADIP1
CADIP0

CTLIP1
CTLIN1

2

Bottom Side

U7A

N12-7540010-F02

D29

VLDT0_A6

D27

VLDT0_A5

D25

VLDT0_A4

C28

VLDT0_A3

C26

VLDT0_A2

B29

VLDT0_A1

B27

VLDT0_A0

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

2

WIDTH 200MILS, AS CLOSE AS POSSIBLE TO THE
PROCESSOR AND THEN AS 20MILS TRACES IN THE
PIN FILED

VDD_12_A

C476

X_0.22u/BOT

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0

HYPER TRANSPORT - LINK0

L0_CTLOUT_L0

Title

Size Document Number Rev

Date: Sheet of

VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0

MSI

C204

C147

X_0.22u

224P

VLDT0_B PINS SHOULD BE CONNECTED TO A
SIGNAL 4.7UF CAPACITOR ROUTED WITH A 100
MILS WIDE TRACE

AH29
AH27
AG28
AG26
AF29
AE28
AF25

N26

CADON15

N27
L25

CADON14

M25
L26

CADON13

L27
J25

CADON12

K25
G25

CADON11

H25
G26

CADON10

G27
E25

CADON9

F25
E26

CADON8

E27
N29

CADON7

P29
M28

CADON6

M27
L29

CADON5

M29
K28

CADON4

K27
H28

CADON3

H27
G29

CADON2

H29
F28

CADON1

F27
E29

CADON0

F29

CLKOP1

J26

CLKON1

J27

CLKOP0

J29

CLKON0

K29
N25

P25

CTLOP0

P28

CTLON0

P27

C212

X_0.22u

CADOP15
CADOP14
CADOP13
CADOP12
CADOP11
CADOP10
CADOP9
CADOP8
CADOP7
CADOP6
CADOP5
CADOP4
CADOP3
CADOP2CADIP2
CADOP1
CADOP0

C211

224P

VLDT0

475P/1206/16V

MICRO-STAR

K8 DDR & HT

MS-7102

1

C228

224P

VLDT0 <5>

C82

CADOP[0..15] <11>
CADON[0..15] <11>CADIN[0..15]<11>

CLKOP1 <11>
CLKON1 <11>
CLKOP0 <11>
CLKON0 <11>

CTLOP0 <11>
CTLON0 <11>

1

0.22uf

4 36Friday, July 23, 2004

C146

C75

X_0.22uf

0A

5

4

3

2

1

VCCA_PLL trace length from the VR1 to the PGA must be 0.75".

Place al filters close to the PGA.

Keep all power and signal trce away from the VR1.

D D

LAYOUT: Route VDDA trace approx. 50 mils wide
(use 2x25 mil traces to exit ball field) and 500 mils

VDDA_25

long.

FB1 180nH/1210

CPU_VDDA_25

Place a cut in the GND plane around the VCCA_PLL regulator circuit.

VCC2_5

C61

C65
475P/0805

3900P

C54

0.22uf

R185

C299
106P/1206

Near SB

1K

THRMTRIP# <30>

AH25

C44
X_102P

CPU_GD<30>

C C

-LDTSTOP

PS_OUT#<28,30>

B B

HDT Connectors

DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI

NC_AJ18
NC_C21

NC_AG17
NC_C19

A A

NC_D18
NC_D20
NC_B19

NC_AH18
NC_AG18

PS_OUT#

R39 X_56
R40 X_1K

RN36 X_56-8P4R

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

R36 X_1K
R37 X_1K

5

R58

Q14
X_NDS7002AS

1 2
3 4
5 6
7 8

VCC2_5

1K

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

VCC2_5

RN3
1K-8P4R

1K-8P4R
RN37

VLDT0

VLDT0<4>

R55 44.2RST
R51 44.2RST

8/28 AMD CHANGE THE PULL-UP POWER

VDD_25_SUS

4

C72
102P

C31

X_102P

C66

102P

VDD_25_SUS

VDDIO_SENSE

-CPURST<28>

-LDTSTOP<11,18>

COREFB_H<29>

Differential , "10:10:5:10:10".

Near CPU in 0.5" .

COREFB_L<29>

CPUCLK0_H<7>

CPUCLK0_L<7>

C63 3900P

C68 3900P

VTT_DDR_SUS

VCC2_5

3

CPU_GD

L0_REF1
L0_REF0

R50

R41 820
R47 820

R71 1K
R70 1K

VDDIO_SENSE

169RST

RN4

1 2

3 4

5 6

7 8

NC_AJ23
NC_AH23

DBRDY

TMS
TCK
TRST_L
TDI

NC_C18
NC_A19

NC_AE23
NC_AF23
NC_AF22
NC_AF21

X_1K-8P4R

CLKIN_H

CLKIN_L

VDDA1

AJ25

VDDA2

AF20

RESET_L

AE18

PWROK

AJ27

LDTSTOP_L

AF27

L0_REF1

AE26

L0_REF0

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AJ21

CLKIN_H

AH21

CLKIN_L

AJ23

NC_AJ23

AH23

NC_AH23

AE24

NC_AE24

AF24

NC_AF24

C16

VTT_A5

AG15

VTT_B5

AH17

DBRDY

C15

NC_C15

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

C18

NC_C18

A19

NC_A19

A28

KEY1

AJ28

KEY0

AE23

NC_AE23

AF23

NC_AF23

AF22

NC_AF22

AF21

NC_AF21

C1

FREE29

J3

FREE31

R3

FREE33

AA2

FREE35

D3

FREE1

AG2

FREE37

B18

FREE4

AH1

FREE38

AE21

FREE41

C20

FREE7

AG4

FREE11

C6

FREE12

AG6

FREE13

AE9

FREE14

AG9

FREE40

123456789101112131415

U7C

THERMTRIP_L

THERMDA
THERMDC

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

G_FBCLKOUT_H

G_FBCLKOUT_L

DBREQ_L

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

NC_AF18

RSVD_SCL
RSVD_SDA

FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25

123456789101112131415

FREE27

2

VID4
VID3
VID2
VID1
VID0

TDO

THRMTRIP#

A20

THERMDA_CPU

A26
A27

AG13
AF14
AG14
AF15
AE15

AG18
AH18
AG17
AJ18

AH19
AJ19

AE19
D20

C21
D18
C19
B19

A22

AF18

D22
C22

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

16

16

VTIN_GND

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

FBCLKOUT_H

R52

80.6RST

FBCLKOUT_L

Zdiff = 80 ohm

DBREQ_L
NC_D20

NC_C21
NC_D18
NC_C19
NC_B19

TDO

VID0
VID2
VID1
VID3

VID4

MSI

Title

Size Document Number Rev

Date: Sheet of

THERMDA_CPU <25,26>

VID[4..0]

VID[4..0] <29>

LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )

8/28 AMD CHANGE THE PULL-UP POWER

VDD_25_SUS

R77 1K

RN2

7 8
5 6
3 4
1 2

X_8P4R-4.7K

R28 X_4.7K

MICRO-STAR

K8 HDT & MISC

MS-7102

1

VCC2_5

VTIN_GND <25,26>

R351

X_0R

C42
104P

5 36Friday, July 23, 2004

Bottom
side

C30

X_475P/0805

0A

5

4

3

2

1

U7E

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205

171819

VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

20

GND

20

GROUND

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2

VCORE VDD_25_SUS

K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17

AC15

AB14

AA15

AB16

AA17
AC17
AE17

AB18
AD18
AG19

AC19
AA19

AB20
AD20

AA21
AC21

AB22
AD22

AA23
AC23

AB24
AD24
AH24
AE25

GND

H18
B20
E21
H22

J23

H24

F26

V10
G13
K14
Y14

G15

J15

H16
K16
Y16

G17

J17

F18
K18
Y18

E19
G19

J19

F20
H20
K20
M20
P20
T20
V20
Y20

G21

J21

L21
N21
R21
U21
W21

F22
K22
M22
P22
T22
V22
Y22

E23
G23

L23
N23
R23
U23
W23

B24
D24

F24
K24
M24
P24
T24
V24
Y24

K26
P26
V26

U7D

L7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

N7

VDD10

L9

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD39
VDD38
VDD37
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92

POWER

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50

VDDIO6

VDD96
VDD97
VDD98

VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133

VDD93

VDD94

VDD95

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

4

B2

VSS1

AH20

VSS3

AB21

VSS4

W22

VSS5

M23

VSS6

L24

VSS7

AG25

VSS8

AG27

VSS9

D D

C C

B B

A A

D2

VSS10

AF2

VSS11

W6

VSS12

Y7

VSS13

AA8

VSS14

AB9

VSS15

AA10

VSS16

J12

VSS17

B14

VSS18

Y15

VSS19

AE16

VSS20

J18

VSS21

G20

VSS22

R20

VSS23

U20

VSS24

W20

VSS25

AA20

VSS26

AC20

VSS27

AE20

VSS28

AG20

VSS29

AJ20

VSS30

D21

VSS31

F21

VSS32

H21

VSS33

K21

VSS34

M21

VSS35

P21

VSS36

T21

VSS37

V21

VSS38

Y21

VSS39

AD21

VSS40

AG21

VSS41

B22

VSS42

E22

VSS43

G22

VSS44

J22

VSS45

L22

VSS46

N22

VSS47

R22

VSS48

U22

VSS49

AG29

VSS50

AA22

VSS51

AC22

VSS52

AG22

VSS53

AH22

VSS54

AJ22

VSS55

D23

VSS56

F23

VSS57

H23

VSS58

K23

VSS59

P23

VSS60

T23

VSS61

V23

VSS62

Y23

VSS63

AB23

VSS64

AD23

VSS65

AG23

VSS66

E24

VSS67

G24

VSS68

J24

VSS69

N24

VSS70

R24

VSS71

U24

VSS72

W24

VSS73

AA24

VSS74

AC24

VSS75

AG24

VSS76

AJ24

VSS77

B25

VSS78

C25

VSS79

B26

VSS80

D26

VSS81

H26

VSS82

M26

VSS83

T26

VSS84

Y26

VSS85

AD26

VSS86

AF26

VSS87

AH26

VSS88

C27

VSS89

B28

VSS90

D28

VSS91

G28

VSS92

F15

VSS187

H15

VSS188

AB17

VSS206

AD17

VSS207

B16

VSS208

G18

VSS209

AA18

VSS210

AC18

VSS211

D19

VSS212

F19

VSS213

H19

VSS214

K19

VSS215

Y19

VSS216

AB19

VSS217

AD19

VSS218

AF19

VSS219

J20

VSS220

L20

VSS221

N20

VSS222

GND

171819

GNDGNDGND

5

EMI

LAYOUT: Place 1 capacitor every 1-1.5"

VCORE

along VDD_CORE perimiter.

103P

C52

C117

X_6.8pF

LAYOUT: Place 6 EMI capsalong bottom right side of Clawhammer, 2 in middle
of HT link, and 12 along

LAYOUT: Locate close to
Clawhammer socket.

VTT_DDR_SUS

+

C253
X_100u-16V

VCORE

LAYOUT: Place beside processor.

VDD_25_SUS

C262

VDD_25_SUS VDD_25_SUS

C57

X_475P/0805

105P

C111

GND

bottom left side of Claw-

VCORE

C460

C465

X_6.8pf_B

X_6.8pf_B

12

+

EC12
EL470/10V-3.5

C51

C471

0.22uf

0.22uf

0.22uf_B

BOTTOM SIDE BOTTOM SIDE

C148

C190

475P/0805

X_475P/0805

GND

hammer.

C458

C470

X_6.8pf_B

X_6.8pf_B

VTT_DDR_SUS

12

+

C50

0.22uf

0.22uf_B

GND

BOTTOM SIDE

C454

X_475P/0805

GND

475P/0805

C473

C461

X_6.8pf_B

12

+

CT14
X_ELS10/16V-B

GND

VDD_25_SUS

C463

X_6.8pf_B

BOTTOM SIDE

LAYOUT: Place one 1210 10uF capacitor
on each end of the VTT island.

CT1
X_ELS10/16V-B

C175

C453

0.22uf

C256

3

C459

X_6.8pf_B

VTT_DDR_SUS

C127
X_104P

GND

VCORE

C104

C98

104P

104P

C472

C467

X_6.8pf_B

X_6.8pf_B

X_6.8pf_B

GND

LAYOUT: Place 1000pF capacitors

CPU

Place on inside of CPU Cavity ( 5 * 0.22uF/0603
X7R high-freq decoupling Cap. )

VCORE

C101
X_0.22u

C95

X_0.22u

C108

0.22u

C466
X_0.22u_B

BOTTOM SIDE

C102

0.22u

C116

X_0.22u

between VRM & CPU.

RECOMMEND 4 PLACEDIN TOP SOCKET CAVITY
AND 2 ON THE BOTTOM DIRECTLY UNDER SOCKET CAVITY

106P/1206

C106

X_106P/1206

C186

C173

C207

C242

C270

C34

X_104P

X_104P

X_104P

X_104P

X_104P

GND

C141
X_104P

C135
X_104P

C85
X_104P

C129
X_104P

2

C115
X_104P

X_104P

C56
X_104P

Title

Size Document Number Rev

Date: Sheet of

C113

106P/1206

C38
X_104P

MSI

X_106P/1206

C114

C105

VCOREVCORE

C468

C92
106P/1206

106P/1206_B

MICRO-STAR

K8 POWER & GND

MS-7102

1

6 36Thursday, July 22, 2004

C464
106P/1206_B

0A

5

VCC3

C345

Clock Synthesizer

D D

CLKVCC3

C334 104P

CLKVCC3

C328 104P

VCC3_CLK

R242 10K
C355 104P

CLKVCC3

C346 104P

CLKVCC3

C356 104P

C354 X_104P

C C

CLKVCC3

C361 104P

CLKVCC3

C347 104P

CLKVCC3

C494 X_104P

VCC3_CLK

C341 104P

B B

46
47

2
5

32
33

9

10

16
15

19
20

29
30

27
38

39
35

34
43

42

ICS950403

U15

VDD_46
VSS_47

VDD_2
VSS_5

PD
VSSF

VDD_9
VSS_10

VDD_16
VSS_15

VDD_19
VSS_20

VDD_29
VSS_30

VSS_27
VDD_38

VSS_39
VDD_35

VSS_34
VDDA

VSSA

FS0/REF0
FS1/REF1
FS2/REF2

XIN

XOUT

FS3/48MHZ

ModeB/PCI33_HT66_1

PCI33_HT66_2
PCI33_HT66_3

PCI33_10

PCI33_0
PCI33_1
PCI33_2
PCI33_3

PCI33_F
PCI33_4
PCI33_5

24_48MHZ/SEL

SDATA

SCLK

CPUT_0

CPUC_0

CPUT_1

CPUC_1

ModeA/PCI33_HT66SEL

PCICLK6

RESET

1
48
45

3
4

31
7

8
11
12
13
14
17
18

23
21
22

28
26

25
41

40
37

36

6
24
44

104P

FS0
FS1
FS2

CLKX1
CLKX2

FS3
HT_66_0

HT_66_1
HT_66_2

SEL_24
SMBDATA1

SMBCLK1

> 0.5 inches

-SEL_66
SPREAD

RN78 8P4R-33

R194 10K
R214 33

4

FB21 120S/0805

R189 22
R193 22
R198 22
R209 22

X1 14.318MHZ

R244 33

RN73 8P4R-33

7

8

5

6

3

4

1

2

7

8

5

6

3

4

1

2

7

RN83 8P4R-33

8

5

6

3

4

1

2

R250 33

R236 15RST
R240 15RST

Close to Driver side

CLKVCC3

C357
104P

GUICLK
SB_OSC14
AUD_CLK
APICCLK

22PC332

22PC333

VCLK
GCLK_SLOT

GCLK_NB
PCICLK6
PCICLK1
PCICLK2

PCICLK3
SB_PCLK

SIO48M

SMBDATA1 <8,17,18,30>
SMBCLK1 <8,17,18,30>

CPUCLK0_H
CPUCLK0_L

FP_RST# <28,30>

C350
475P/0805

GUICLK <12>
SB_OSC14 <17>
AUD_CLK <21>
APICCLK <18>

USBCLK_SB <16>

VCLK <18>

GCLK_SLOT <14>
GCLK_NB <12>
PCICLK6 <25>
PCICLK1 <19>
PCICLK2 <19>

PCICLK3 <19>
SB_PCLK <18>

SIO48M <25>

CPUCLK0_H <5>
CPUCLK0_L <5>

3

CPUCLK0_H
CPUCLK0_L

SEL_24

FS3
FS2
FS1
FS0

FS3
FS2
FS1
FS0

HT_66_0

VCLK

GCLK_NB

USBCLK_SB
SIO48M
SB_OSC14
APICCLK

SB_PCLK
PCICLK3

PCICLK2

PCICLK6
PCICLK1

C351 X_5P
C352 X_5P

R253 10K

R243 10K
R203 X_10K
R190 X_10K
R188 X_10K

R245 X_10K
R202 10K
R197 10K
R192 10K

R191 10K

C335 X_10P

C340 X_10P

C362 10P
C365 10P
C319 X_10P
C337 X_10P

1 2
3 4
5 6
7 8

C349 X_10P
C353 X_10P

2

ModeA ModeB Pin6 Pin7

CLKVCC3

0 0

0

1
1 1

1

0

HTTCLK0

HTTCLK0

HTTCLK0
HTTCLK0

SER_24 Pin28

24MHz

1

48MHz

0

CN19
X_8P4C-10P

ICS:ModeA/ModeB=0/1

Pin8 Pin11
HTTCLK1

HTTCLK1

HTTCLK2

HTTCLK2

PCICLK7 PCICLK8
HTTCLK1

PCICLK8

1

PCICLK9

HTTCLK3

PCICLK9
PCICLK9

For RealTek RTM360-803

(1)

CLKVCC3

FB22

Input Configuration

FS2

FS1FS2

0 0 01

0

1

1

1 0

0
0
0
0

A A

0
0
0

0111
0 0

1

0

0

10 168.00

0

0

0

0 0
0

0 0

Clock Generator Output

FS0

CPU (MHz)

150

11 1

200.40

166.70

133.50

1

202
0
1

133.90

100.90

5

PCI33 (MHz)

33.33

33.33

33.33

33.33

36.56100.20

30.00
X1/6
X1/6

33.63

PCI33_HT66 (MHz)

33.33 or 66.66

33.33 or 66.66

33.33 or 66.66

33.33 or 66.66

73.12

60.00
X1/6
X1/3

67.27

4

Comment

Normal Hammer operation
Reserved
Athlon compatible
Athlon compatible
ICS OverClock
ICS UnderClock
Bypass mode
Bypass mode
Tri-state mode

3

(2)

VCLK

stuff C494 & C354(at U8.20 & U8.34)(3)

2

VCC3_CLK

X_120S/0805

CP11

X_COPPER

R201 X_10K

RealTek:ModeA/ModeB=0/0

*c494 reserved at solder side

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

N o. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Clock Synthesizer

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

1

7 36

of

Rev

0A

5

R141 4.7K

DR_MD[63..0]

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP1

-MSWEA
DDR_VREF

C29
X_102P

2
4
6

8
94
95
98
99
12
13
19
20

105
106
109
110

23
24
28
31

114
117
121
123

33
35
39
40

126
127
131
133

53
55
57
60

146
147
150
151

61
64
68
69

153
155
161
162

72
73
79
80

165
166
170
171

83
84
87
88

174
175
178
179

90
63

1

9

101
102

DR_MD[63..0]<9,10>

D D

C C

B B

VDD_25_SUS

-MSWEA<4,9>

Place 104p Cap. near the DIMM

VDD_25_SUS

VDD_25_SUS

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDDQ0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VDDQ1

VSS7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

WP(NC)
WE#

VREF
NC2

NC3

SLAVE ADDRESS = 1010000B

NC4

VSS0

3111826344250586674818993

4

SYSTEM MEMORY

104

112

128

136

143

156

164

172

1801582

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

184

PIN

DDR DIMM

SOCKET

CK1#(CK0#)

NC(RESET#)

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

100

116

124

132

139

145

152

160

176

VDDID

VDDQ15

FETEN

A10_AP

CK0(DU)
CK0#(DU)
CK1(CK0)

CK2(DU)
CK2#(DU)

VSS21

184

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

A11
A12
A13

BA0
BA1
BA2
SCL

SDA

SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

157
158
71
163

5
14
25
36
56
67
78
86
47

167
48

43
41
130
37
32
125
29
122
27
141
118
115
103

59
52
113
92
91
181
182
183

44
45
49
51
134
135
142
144

16
17
137
138
76
75

173
10

MCKE0

21

MCKE1

111

-MSCASA

65

-MSRASA

154

DR_MEMDM0

97

DR_MEMDM1

107

DR_MEMDM2

119

DR_MEMDM3

129

DR_MEMDM4

149

DR_MEMDM5

159

DR_MEMDM6

169

DR_MEMDM7

177
140

DDR1
DDR400-CH

-MCS0

-MCS1

-DR_MDQS0

-DR_MDQS1

-DR_MDQS2

-DR_MDQS3

-DR_MDQS4

-DR_MDQS5

-DR_MDQS6

-DR_MDQS7

MAA13
MAA0

MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12

SMBCLK1
SMBDATA1

MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7

3

-MCS0 <4,9>

-MCS1 <4,9>

-DR_MDQS0 <9,10>

-DR_MDQS1 <9,10>

-DR_MDQS2 <9,10>

-DR_MDQS3 <9,10>

-DR_MDQS4 <9,10>

-DR_MDQS5 <9,10>

-DR_MDQS6 <9,10>

-DR_MDQS7 <9,10>

MAA[13..0]

MAA[13..0] <4,9>

MEMBANKA0 <4,9>
MEMBANKA1 <4,9>

SMBCLK1 <7,17,18,30>
SMBDATA1 <7,17,18,30>

MEMCLK_H5 <4,9>
MEMCLK_L5 <4,9>
MEMCLK_H0 <4,9>
MEMCLK_L0 <4,9>
MEMCLK_H7 <4,9>
MEMCLK_L7 <4,9>

MCKE0 <4,9>
MCKE1 <4,9>

-MSCASA <4,9>

-MSRASA <4,9>

Place 104p and 1000p Cap.
near the DIMM

DR_MEMDM[7..0]

VDD_25_SUS

DR_MEMDM[7..0] <9,10>

R142 4.7K

-MSWEB<4,9>

C39
104P

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP2

-MSWEB
DDR_VREF

2

VDD_25_SUS

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDDQ0

VDDQ1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VDDQ2

VSS8

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

SLAVE ADDRESS = 1010001B

102

NC4

VSS0

VSS1

3111826344250586674818993

104

112

128

136

143

156

164

172

1801582

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

FETEN

A10_AP

184

PIN

DDR DIMM

SOCKET

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC(RESET#)

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

100

116

124

132

139

145

152

160

176

VDDID

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

A11
A12
A13

BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

184

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

157
158
71
163

-DR_MDQS0

5

-DR_MDQS1

14

-DR_MDQS2

25

-DR_MDQS3

36

-DR_MDQS4

56

-DR_MDQS5

67

-DR_MDQS6

78

-DR_MDQS7

86
47

167
48

43
41
130
37
32
125
29
122
27
141
118
115
103

59
52
113
92
91
181
182
183

44
45
49
51
134
135
142
144

MEMCLK_H4

16

MEMCLK_L4

17

MEMCLK_H1

137

MEMCLK_L1

138

MEMCLK_H6

76

MEMCLK_L6

75
173

10
21

111
65
154

DR_MEMDM0

97

DR_MEMDM1

107

DR_MEMDM2

119

DR_MEMDM3

129

DR_MEMDM4

149

DR_MEMDM5

159

DR_MEMDM6

169

DR_MEMDM7

177
140

DDR2
DDR400-CH

1

-MCS2

-MCS3

MAB13
MAB0

MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12

SMBCLK1
SMBDATA1

MCKE0
MCKE1

-MSCASB

-MSRASB

-MCS2 <4,9>

-MCS3 <4,9>

MAB[13..0] <4,9>

MEMBANKB0 <4,9>
MEMBANKB1 <4,9>

VDD_25_SUS

MEMCLK_H4 <4,9>
MEMCLK_L4 <4,9>
MEMCLK_H1 <4,9>
MEMCLK_L1 <4,9>
MEMCLK_H6 <4,9>
MEMCLK_L6 <4,9>

-MSCASB <4,9>

-MSRASB <4,9>

R34
1KST

A A

R44
1KST

C45
X_104P

DDR_VREF

C46
104P

DDR_VREF <4>

5

MSI

Title

Size Document Number Rev

4

3

2

Date: Sheet of

MICRO-STAR

DDR

MS-7102

1

8 36Wednesday, July 21, 2004

0A

5

DDR Terminations

4

3

2

1

VTT_DDR_SUS VTT_DDR_SUS

4

DR_MD44
DR_MD40
DR_MD39
DR_MD35

DR_MD38
DR_MD34

DR_MEMDM4

-DR_MDQS4
DR_MD37
DR_MD33

DR_MD36

DR_MD32

MAB10
MAB0
MAA10
MAA0

MAA1
MAB1
MAB2
MAA2

DR_MD31
DR_MD27
DR_MD30
DR_MD26

MAB3
MAA3
DR_MEMDM3
MAA4

-DR_MDQS3
DR_MD25
MAB4
MAA6

DR_MD29
DR_MD28
MAA5
MAA8

DR_MD24
MAB6
MAB5
DR_MD19

DR_MD19

D D

DR_MD59
DR_MD63
DR_MD58
DR_MD62

-DR_MDQS7
DR_MEMDM7
DR_MD57
DR_MD61

DR_MD56
DR_MD60
DR_MD51
DR_MD55

C C

B B

-MSCASA<4,8>

-MSCASB<4,8>

-MSRASA<4,8>

-MSRASB<4,8>

A A

DR_MD50
DR_MD54

-DR_MDQS6
DR_MEMDM6

MAA13
MAB13
DR_MD53
DR_MD52

DR_MD49
DR_MD48
DR_MD47
DR_MD46

DR_MD43
DR_MD42
DR_MEMDM5

-DR_MDQS5

-MCS0

-MCS0<4,8>

-MCS2

-MCS2<4,8>

-MCS1

-MCS1<4,8>

-MCS3

-MCS3<4,8>

-MSCASA
DR_MD41

-MSCASB

-MSWEB

-MSWEB<4,8>

-MSRASA

-MSRASB

-MSWEA

-MSWEA<4,8>
DR_MD45

The Processor pins and resistor
are less than 1" in length.

MEMCLK_H5
MEMCLK_H4
MEMCLK_H7
MEMCLK_H6
MEMCLK_H1
MEMCLK_H0

5

RN66 47-8P4R

7 8
5 6
3 4
1 2

RN63 47-8P4R

7 8
5 6
3 4
1 2

RN61 47-8P4R

7 8
5 6
3 4
1 2

RN59 47-8P4R

7 8
5 6
3 4
1 2

RN57 47-8P4R

7 8
5 6
3 4
1 2

RN54 47-8P4R

7 8
5 6
3 4
1 2

RN50 47-8P4R

7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8

RN49 47-8P4R
RN47 47-8P4R

7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8

RN45 47-8P4R

R61 120RST
R59 120RST
R75 120RST
R74 120RST
R63 120RST
R64 120RST

MEMCLK_L5
MEMCLK_L4
MEMCLK_L7
MEMCLK_L6
MEMCLK_L1
MEMCLK_L0

MEMBANKA0<4,8>

MEMBANKB0<4,8>

MEMBANKB1<4,8>
MEMBANKA1<4,8>

VTT_DDR_SUS

RN43 47-8P4R

7 8
5 6
3 4
1 2

RN42 47-8P4R

7 8
5 6
3 4
1 2

RN40 47-8P4R

7 8
5 6
3 4
1 2

RN38 47-8P4R

7 8
5 6
3 4
1 2

RN35 47-8P4R

7 8
5 6
3 4
1 2

RN34 47-8P4R

7 8
5 6
3 4
1 2

RN32 47-8P4R

7 8
5 6
3 4
1 2

RN31 47-8P4R

7 8
5 6
3 4
1 2

RN30 47-8P4R

7 8
5 6
3 4
1 2

RN28 47-8P4R

7 8
5 6
3 4
1 2

RN26 47-8P4R

7 8
5 6
3 4
1 2

-MCS2

-MCS2<4,8>

DR_MD23
MAA7
MAA9
MAA11

MAA12
DR_MD22
MAB8
MAB7

DR_MD18

MAB9

DR_MEMDM2

MAB11

DR_MD21

-DR_MDQS2

DR_MD17

MAB12

DR_MD16

DR_MD20

MCKE0<4,8>
MCKE1<4,8>

DR_MD11

DR_MD10

DR_MD15

DR_MD14

DR_MEMDM1

DR_MD13

-DR_MDQS1

DR_MD12

DR_MD9

DR_MD8

DR_MD3

DR_MD7

DR_MD6
DR_MD2

-DR_MDQS0

DR_MEMDM0

DR_MD1

DR_MD5

DR_MD4

DR_MD0

DR_MEMDM[7..0]<8,10>

MEMCLK_L[7..0]<4,8>

MEMCLK_H[7..0]<4,8>

-DR_MDQS[7..0]<8,10>

3

RN24 47-8P4R

7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8

RN22 47-8P4R
RN20 47-8P4R

7 8
5 6
3 4
1 2

RN18 47-8P4R

7 8
5 6
3 4
1 2

RN15 47-8P4R

7 8
5 6
3 4
1 2

RN13 47-8P4R

7 8
5 6
3 4
1 2

RN11 47-8P4R

7 8
5 6
3 4
1 2

RN10 47-8P4R

7 8
5 6
3 4
1 2

RN7 47-8P4R

7 8
5 6
3 4
1 2

RN5 47-8P4R

7 8
5 6
3 4
1 2

DR_MD[63..0]<8,10>

MAB[13..0]<4,8>
MAA[13..0]<4,8>

DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_MEMDM[7..0]

MEMCLK_L[7..0]
MEMCLK_H[7..0]

-DR_MDQS[7..0]

2

-MSCASB<4,8>

-MSCASA<4,8>

-MSRASB<4,8>

-MSRASA<4,8>

MEMBANKB1<4,8>

MEMBANKA1<4,8>

MEMBANKB0<4,8>

MEMBANKA0<4,8>

-MCS3

-MCS3<4,8>
MAB13

MAA13

MAB12
MAA12
MAB11
MAA11

MAB1
MAA1

MAB3
MAA3
MAB2
MAA2

MAB6

MAA6
MAB4
MAA4

MAB8
MAA8
MAB5
MAA5

MAA0

MAA10

MAB0
MAB10

-MSCASB

-MCS0

-MCS0<4,8>

-MSCASA

-MCS1

-MCS1<4,8>

MAA9
MAB9
MAB7
MAA7

-MSRASB

-MSRASA

-MSWEB

-MSWEB<4,8>

-MSWEA

-MSWEA<4,8>

MCKE1<4,8>

MCKE0<4,8>

MSI

Title

Size Document Number Rev

Date: Sheet of

CN18

12
34
56
78

X_8P4C-22P
CN4

12
34
56
78

X_8P4C-22P
CN13

12
34
56
78

X_8P4C-22P
CN12

12
34
56
78

X_8P4C-22P
CN11

12
34
56
78

X_8P4C-22P
CN9

12
34
56
78

X_8P4C-22P
CN14

12
34
56
78

X_8P4C-22P
CN17

12
34
56
78

X_8P4C-22P
CN6

12
34
56
78

X_8P4C-22P
CN16

12
34
56
78

X_8P4C-22P
CN15

12
34
56
78

X_8P4C-22P
CN3

12
34
56
78

X_8P4C-22P

MICRO-STAR

DDR Terminations Part 1

MS-7102

9 36Wednesday, July 21, 2004

1

0A

5

4

3

2

1

LAYOUT: Place on backside,

DDR Terminations

D D

C C

B B

-MDQS[7..0]<4>

-DR_MDQS[7..0]<8,9>
DR_MD[63..0]<8,9>

MD[63..0]<4>

MEMDM[7..0]<4>

DR_MEMDM[7..0]<8,9>

RN6 10-8P4R

MD0

1 2

MD4

3 4

MD5

5 6

MD1

7 8

RN8 10-8P4R

MEMDM0 DR_MEMDM0

1 2

-MDQS0

3 4

MD2

5 6

MD6

7 8

RN9 10-8P4R

MD7

1 2

MD3

3 4

MD8

5 6

MD9

7 8

RN12 10-8P4R

MD12

1 2

-MDQS1 -DR_MDQS1

3 4

MEMDM1 DR_MEMDM1

5 6

MD13 DR_MD13

7 8

RN14 10-8P4R

MD14

1 2

MD15

3 4

MD10

5 6

MD11

7 8

RN21 10-8P4R

MD21 DR_MD21

1 2

MEMDM2 DR_MEMDM2

3 4

MD18 DR_MD18

5 6

MD22 DR_MD22

7 8

RN17 10-8P4R

MD20

1 2

MD16

3 4

-MDQS2

5 6

MD17

7 8

RN25 10-8P4R

MD23

1 2

MD19 DR_MD19

3 4

MD24

5 6

MD28 DR_MD28

7 8

RN29 10-8P4R

MD29

1 2

MD25

3 4

-MDQS3

5 6

MEMDM3 DR_MEMDM3

7 8

DR_MD0
DR_MD4
DR_MD5
DR_MD1

-DR_MDQS0
DR_MD2
DR_MD6

DR_MD7
DR_MD3
DR_MD8
DR_MD9

DR_MD12

DR_MD14
DR_MD15
DR_MD10
DR_MD11

DR_MD20
DR_MD16

-DR_MDQS2
DR_MD17

DR_MD23
DR_MD24

DR_MD29
DR_MD25

-DR_MDQS3

-MDQS[7..0]

-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]

RN33 10-8P4R

MD26

1 2

MD30

3 4

MD27

5 6

MD31

7 8

RN39 10-8P4R

MD32

1 2

MD36

3 4

MD33

5 6

MD37

7 8

RN41 10-8P4R

-MDQS4 -DR_MDQS4

1 2

MEMDM4 DR_MEMDM4

3 4

MD34 DR_MD34

5 6

MD38 DR_MD38

7 8

RN44 10-8P4R

MD35 DR_MD35

1 2

MD39

3 4

MD40

5 6

MD44

7 8

RN48 10-8P4R

MD45 DR_MD45

1 2

MD41

3 4

-MDQS5 -DR_MDQS5

5 6

MEMDM5 DR_MEMDM5

7 8

RN51 10-8P4R

MD42 DR_MD42

1 2

MD43

3 4

MD46 DR_MD46

5 6

MD47

7 8

RN55 10-8P4R

MD48 DR_MD48

1 2

MD49

3 4

MD52 DR_MD52

5 6

MD53 DR_MD53

7 8

RN58 10-8P4R

MEMDM6

1 2

-MDQS6

3 4

MD54

5 6

MD50 DR_MD50

7 8

RN60 10-8P4R

MD55

1 2

MD51

3 4

MD60

5 6

MD56 DR_MD56

7 8

RN62 10-8P4R

MD61

1 2

MD57

3 4

MEMDM7 DR_MEMDM7

5 6

-MDQS7 -DR_MDQS7

7 8

RN65 10-8P4R

MD62 DR_MD62

1 2

MD58

3 4

MD63

5 6

MD59

7 8

DR_MD26
DR_MD30
DR_MD27
DR_MD31

DR_MD32
DR_MD36
DR_MD33
DR_MD37

DR_MD39
DR_MD40
DR_MD44

DR_MD41

DR_MD43
DR_MD47

DR_MD49

DR_MEMDM6

-DR_MDQS6
DR_MD54

DR_MD55
DR_MD51
DR_MD60

DR_MD61
DR_MD57

DR_MD58
DR_MD63
DR_MD59

evenly spaced around VTT fill.

VDD_25_SUS

VTT_DDR_SUS

C60

X_0.22uF

C168

X_0.22uF

C70

X_0.22uF

C257

X_0.22uF

C58

X_0.22uF

VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS

C86

X_1u
C78

1u
C90

1u

C134

1u

C94

X_1u
C99

1u

VTT_DDR_SUS

1u

C40

C18

1u

C83

X_1u

C76

C89

VTT_DDR_SUS

1u

1u

C37

VTT_DDR_SUS

1u

X_1u

C159

LAYOUT: Locate close to Clawhammer socket.

VTT_DDR_SUS

C47

C10

C170

X_1u

X_1u

C71

C177

C107

1u
C112

X_1u

C73

1u
C130

X_1u

C119

1u

C263

X_1u

C122

1u

1u

C97

C91

X_1u

1u

X_1u

C187

C194

C126

X_1u
C27

1u
C41

X_1u
C142

1u
C156

X_1u
C162

1u
C171

X_1u

1u

1u

C109

1u

X_1u

C202

C103

C208

X_1u

1u

C128

C216

1u

X_1u

C133

C221

X_1u

1u

LAYOUT: Place alternating caps to GND and VDD_2.5_SUS

C121

C230

C69

0.22uf

475P/0805

GND

C49

C269

X_1u

1u

C138

C261

VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS

C225

X_1u

C235

1u

C243

X_1u

C247

1u

C258

X_1u

C55

1u

1u

X_1u

C151

GND

C23

X_1u

X_1u

GND

1u

X_1u

1u

X_1u

X_1u

1u

1u

X_1u

C179

C191

C197

C203

C210

C219

1u

C64

X_1u

C124

1u

X_1u

C238

C245

in a single line along VTT island.

VDD_25_SUS

C163

C278

X_104P

X_104P

C279

X_104P

C234

X_104P

X_104P

VTT_DDR_SUS VCC3 VCC2_5 VCC

A A

EMI request @930715

C205

C62

C15

X_104P

X_104P

VCC3

C403

C501
X_104P

X_104P

GND

5

solder side

C499
X_104P

VDD_25_SUS

GND

C152
X_104P

C166
X_104P

4

C110
X_104P

C174
X_104P

C125
X_104P

C96
X_104P

C77
X_104P

C193
X_104P

C206
X_104P

VTT_DDR_SUS

3

C155
475P/0805

LAYOUT: Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs (both sides).

VTT_DDR_SUS

102P

102P

C268

C167
475P/0805

C259

C196
X_475P/0805

C118

C32

0.22uf

X_102P

GND

C33

X_475P/0805

GND

C283
475P/0805

2

VTT_DDR_SUS

C144

0.22uf

GND

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR

DDR Terminations Part 2

MS-7102

10 36Thursday, July 22, 2004

1

0A

A

AVDD2

A10

A24

A25

A26A9B10

T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
J24
J22
G24

M26
L24

F24
R26

P25
N26
M25
K25
J26
H25
G26
R23
P22
N23
M22
K22
J23
H22
G23

L26
L23

F25
B11

A12
D25

D26
C26

U24
U25
U26
V21
V22
V23
V24
V25
V26

C22

AVDD2

RCADP0
RCADP1
RCADP2
RCADP3
RCADP4
RCADP5
RCADP6
RCADP7
RCADP8
RCADP9
RCADP10
RCADP11
RCADP12
RCADP13
RCADP14
RCADP15

RCLKP0
RCLKP1

RCTLP
RCADN0

RCADN1
RCADN2
RCADN3
RCADN4
RCADN5
RCADN6
RCADN7
RCADN8
RCADN9
RCADN10
RCADN11
RCADN12
RCADN13
RCADN14
RCADN15

RCLKN0
RCLKN1

RCTLN
LDTRST

LDTSTP
RPCOMP

RNCOMP
RTCOMP

VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT

AGND2

C21

A23

From Claw Hammer

4 4

CADOP[0..15]<4>

CLKOP0<4>
CLKOP1<4>

CTLOP0<4>

CADON[0..15]<4>

3 3

CLKON0<4>
CLKON1<4>

CTLON0<4>

-LDTRST<28>

-LDTSTOP<5,18>

2 2

CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15

CLKOP0
CLKOP1

CTLOP0

CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15

CLKON0
CLKON1

CTLON0

-LDTRST

-LDTSTOP
RPCOMP

PNCOMP
RTCOMP

VDD_12_A

VSS

A8

VLDT

VSS

B8

VLDT

VSS

B13

VLDT

VSS

B15

U10A

VLDT

VSS

B17

VLDT

VSS

B19

B23

VLDT

VSS

B21

B24

B25

VLDT

VLDT

VSS

VSS

B22C8D8

B26B9C10

VLDT

VLDT

VSS

VSS

D6

VLDT

VSS

D12

C11

VLDT

VSS

D14

C23

VLDT

VSS

D16

C24

VLDT

VSS

D18

B

C25C9D10

VLDT

VLDT

VSS

VSS

D20

E5E6E8F7F8

VLDT

VSS

D11

VLDT

VSS

D22

VLDT

VSS

D23

VLDT

VSS

D24D9E10

VLDT

VLDT

VSS

VSS

F13

F12

VLDT

VSS

F14

E11

VLDT

VSS

F17

E21

VLDT

VSS

F18

E22

VLDT

VSS

F26

E23

E24E9F10

VLDT

VLDT

VSS

VSS

G25H1H23

VDD_12_A

VLDT

VLDT

VLDT

VSS

VSS

VSS

F11

F15

VLDT

VSS

J18

F16

VLDT

VSS

J2

F19

VLDT

VSS

J3

F20

VLDT

VSS

J21

F21

VLDT

VSS

J25

F22

VLDT

VSS

K4G1K10

F23

VLDT

VSS

C

K8T800/K8M800 HT Interface

G21

VLDT

VSS

K11

G22

VLDT

VSS

K12

H21

VLDT

VSS

K13

J10

VLDT

VSS

K14

J11

VLDT

VSS

K15

J12

VLDT

VSS

K16

J13

VLDT

VSS

K17

J14

VLDT

VSS

K23H2L10

J15

VLDT

VSS

J16

J17

VLDT

VLDT

TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8

TCADP9
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15

TCLKP0

TCLKP1

TCADN0

TCADN1

TCADN2

TCADN3

TCADN4

TCADN5

TCADN6

TCADN7

TCADN8

TCADN9
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15

TCLKN0

TCLKN1

VSS

VSS

L11

L12

K18

K21

VLDT

VLDT

TCTLP

TCTLN

VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT

VSS

VSS

L13

L14

L18

VLDT

VSS

L15

VLDT

VSS

CADIP0

B12

CADIP1

A13

CADIP2

B14

CADIP3

A15

CADIP4

A17

CADIP5

B18

CADIP6

A19

CADIP7

B20

CADIP8

E12

CADIP9

D13

CADIP10

E14

CADIP11

D15

CADIP12

D17

CADIP13

E18

CADIP14

D19

CADIP15

E20

CLKIP0

B16

CLKIP1

E16

CTLIP0

A21

CADIN0

C12

CADIN1

A14

CADIN2

C14

CADIN3

A16

CADIN4

A18

CADIN5

C18

CADIN6

A20

CADIN7

C20

CADIN8

E13

CADIN9

C13

CADIN10

E15

CADIN11

C15

CADIN12

C17

CADIN13

E19

CADIN14

C19

CADIN15

D21

CLKIN0

C16

CLKIN1

E17

CTLIN0

A22

VDD_12_A

L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23

K8T800/K8M800

To Claw Hammer

CADIP[0..15] <4>

CLKIP0 <4>
CLKIP1 <4>

CTLIP0 <4>

CADIN[0..15] <4>

CLKIN0 <4>
CLKIN1 <4>

CTLIN0 <4>

D

E

For K8M800 Only

CP3

AVDD2

C181
102P

C180
105P

VDD3

FB6
X_80S

1 2

For K8T800(BOM)

1)U10--->U10_K8T

2)Remove C180,C181

BOTTOM SIDE

C478 X_104P/B
C184 104P

PNCOMP
RTCOMP
RPCOMP

VDD_12_A

Around NB

VDD_12_A

R93 49.9RST
R86 100RST
R85 49.9RST

(1)K8T800 Ver:CD(VT8385)

=>B01-0838505-V01

1 1

A

(2)K8M800 Ver:CD(VT8380)

=>B01-K8M8005-V01

B

Title

Size Document Number Rev

C

C

D

Date: Sheet of

{OrgName}

NORTH BRIDGE K8M800 (HT)

MS-7102

11 36Thursday, July 22, 2004

E

0A

A

B

K8T800/K8M800 AGP 8X ,V-Link, Misc. Control

C

D

E

VDDQ

C226

AF18
AD18
AE18

AF17
AD17
AD16
AE16

AF16

AF14
AD14
AD13
AE13

AF13
AD12

AF12
AE12
AD10
AE10

AF10

AD9

AE9
AD8

AD7
AE6
AD5

AE4
AD4

AD15

AF11
AD11

AC7

AF15
AE15

AE7

AC9
AC10
AC14
AC11
AC12
AC16

AD6

AC1

AA3
AC15

AC2

AC3

AD1

AD2

AD3

AE3

AE1

AA2

AA1

AB1

AC13

AC6

AC4

AC5

AF9
AF8

AF6

AF5
AF4

AF7

A11

AF2

AF3

AF1

Y1

V1
W1

Y2

104P

GD0/FPD10
GD1/FPD11
GD2/FPDVICLK
GD3/FPD09
GD4/FPD08
GD5/FPD07
GD6/FPD06
GD7/FPD05
GD8/FPDVIDET
GD9/FPDVIHS
GD10/FPD01
GD11/FPD23
GD12/FPD00
GD13/FPD22
GD14/FPD21
GD15/FPD20
GD16/FPD18
GD17/FPD17
GD18/FPD16
GD19/FPDE
GD20/FPD14
GD21/FPCLK
GD22/FPD13
GD23/FPD15
GD24/DVP1D09
GD25
GD26/DVP1D10
GD27
GD28/DVP1D07
GD29/DVP1D06
GD30/DVP1D08
GD31/DVP1D04

GCBE0/FPD03
GCBE1/SB_DA
GCBE2/FPD19
GCBE3/DVP1D11

ADSTB0S/FPD02
ADSTB0F/FPD04

ADSTB1S/FPDET
ADSTB1F/FPD12

GFRAME/FPHS
GIRDY/SB_CK
GTRDY
GDEVSEL/FPVS
GSTOP/FPDVICLK_N
GPAR/FPDVIVS
RBF
WBF/FPCLK_N
GREQ/DVI_DDCCK
GGNT/DVI_DDCDA
GSERR/FPDVIDE

GCLK
SBA0/DVP1VS

SBA1/DVP1DE
SBA2/DVP1D00
SBA3/DVP1HS
SBA4/DVP1D05
SBA5/DVP1D03
SBA6/DVP1CLK
SBA7/DVP1CLK_N

SB_STBS/DVP1D02
SB_STBF/DVP1D01

ST0
ST1/DVP1DET
ST2

AGPPCOMP
AGPNCOMP

AGPVREF0
AGPVREF1

AGP8XDET
DBIL

DBIH

VSSQQ

VSS

VSS

T1

R13

R14

R15

VSS

R12

VSS

U1

VCCQQ

VSS

R11

VSS

VCC4/NC

VSS

VSS

VCC4/NC

VSS

4 4

GAD[0..31]<14>

3 3

GC/BE#[3..0]<14>

AD_STBS0<14>
AD_STBF0<14>

AD_STBS1<14>
AD_STBF1<14>

GFRAME<14>

GIRDY<14>

GTRDY<14>

GDEVSEL<14>

GSTOP<14>

GPAR<14>

RBF<14>
WBF<14>

GREQ<14>

2 2

1 1

GGNT<14>

GSERR<14>

GCLK_NB<7>

SBA[7..0]<14>

SB_STBS<14>
SB_STBF<14>

AGPVREF_GC<14>

AGP8XDET#<14>

DBIL<14>

DBIH<14>

GAD0
GAD1
GAD2
GAD3 VLAD2
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GC/BE#0
GC/BE#1
GC/BE#2
GC/BE#3

AD_STBS0
AD_STBF0

AD_STBS1
AD_STBF1

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

SB_STBS
SB_STBF

ST0

ST0<14>

ST1

ST1<14>

ST2

ST2<14>

AGPPCOMP
AGPNCOMP

AGPVREF_GC

DBIL
DBIH

A

M5K8M9L8N9P9R9

N5

VCC4/NC

VCC4/NC

VCC4/NC

VSS

VSS

VSS

P17

P23R1R2R3R4R5R10

B

VCC4/NC

VCC4/NC

VCC4/NC

VSS

VSS

VSS

P15

P16

VDD3

L5K9L9

VCC4/NC

VSS

P13

P14

J9

VCC4/NC

VCC4/NC

VCC4/NC

VSS

VSS

VSS

P11

P12

VCC4/NC

VCC4/NC

VCC4/NC

VSS

VSS

VSS

N25P5P10

VCC4/NC

VCC4/NC

VSS

VSS

N16

N17

VCC4/NC

VCC4/NC

VSS

VSS

N14

N15

VCC4/NC

VCC4/NC

VSS

VSS

N12

N13

G2G3G4G5H3H4H5J4J5

VCC4/NC

VCC4/NC

VSS

VSS

N10

N11

F4

VCC4/NC

VCC4/NC

VSS

VSS

M21

M23

F3

M17

F1K5E4E2E3F6F2F5E1

D1

U10B

VD0
VD1

VCC4/NC

VCC4/NC

VCC4/NC

VCC4/NC

VCC4/NC

VCC4/NC

VCC4/NC

TVCLKIN/DVP0DET/NC

TVCLK/DVP0DCLK/NC

VSS

M16

VCC4/NC

VPAR

UPSTB
UPSTB

DNSTB
DNSTB

UPCMD
DNCMD

LVREF

LCOMPP

PWRGD
PCIRST
TESTIN

SUSTAT

DEBUG

AR/NC
AG/NC
AB/NC

RSET/NC
HSYNC/NC
VSYNC/NC

XIN/NC

INTA/NC

BISTIN/NC

SPCLK1/NC
SPCLK2/NC

SPD1/NC

SPD2/NC

TVD00/DVP0D00/NC
TVD01/DVP0D01/NC
TVD02/DVP0D02/NC
TVD03/DVP0D03/NC
TVD04/DVP0D04/NC
TVD05/DVP0D05/NC
TVD06/DVP0D06/NC
TVD07/DVP0D07/NC
TVD08/DVP0D08/NC
TVD09/DVP0D09/NC
TVD10/DVP0D10/NC
TVD11/DVP0D11/NC

TVDE/DVP0DE/NC
TVHS/DVP0HS/NC
TVVS/DVP0VS/NC

GPO0/NC
GPOUT/NC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

M10

L25

M11

M12

M13

M14

M15

K8T800/K8M800

VD2
VD3
VD4
VD5
VD6
VD7

VBE

VSS

L17

C

VSS

AGPVREF_GC

VLAD0

AD20

VLAD1

AD21
AF24

VLAD3

AE24

VLAD4

AE19

VLAD5

AF20

VLAD6

AD24

VLAD7

AF25
AE21

AF19
AE23

AF23
AF22

AD22
AF26

AD23

LVREF_NB

AF21
AD19

LCOMPP

AE26
AD25

TESTIN

AC26
AD26

DEBUG

AC17

B3
A3
A2

RSET

C4
A1
B1

C6
E7

R87

D3

1K

P2
C2
P1
C1

J1
K2
K3
L4
K1
L2
L3
M4
L1
M2
M3
M1

P4
N1
N4
N3

P3

N2
D2

VSS

L16

VLAD[0..7] <18>

VBE0# <18>
VPAR <18>

UPSTB <18>
UPSTB# <18>

DNSTB <18>
DNSTB# <18>

UPCMD <18>
DNCMD <18>

C248
X_102P

PWROK_NB# <17>

PCIRST1# <25,30>

SUSST# <17>

R126 X_10K
R130 10K

ARR
AGG
ABB

R94 100RST

HSYNC <15>
VSYNC <15>

GUICLK <7>
PIRQ#A <14,16,19>

DDCCLK <15>
DDCDATA <15>

VCC2_5

R144
3KST

VCC2_5

90.9 Ohm
R11-909AT13-Y01

For K8M800.

C267
104P

LVREF_NB

R143
1KST

K8M/T800 both will be 0.625V

C266
104P

=>2.5x(1/4)=0.625V

LAYOUT: Place caps as close NB as possible

TESTIN

AGPNCOMP
AGPPCOMP

LCOMPP

R133 60.4RST
R129 60.4RST

R134 360RST

ARR
AGG
ABB

EMI request closed to NB@930715

For K8M800 Only

Title

Size Document Number Rev

Custom

D

Date: Sheet of

BOTTOM SIDE

C493 105P/B
C282 105P

VDDQ

C192
X_22P

C199
X_22P

1
3
5
7

VCC2_5

C251
104P

For V-Link Current Return Path
Close to NB

C195

C198

X_22P

X_22P

C200
X_22P

R352

0/0805/B

2
4

RN52

6

8P4R-0

8

VCC2_5

AR <15>
AG <15>
AB <15>

R138 4.7K

For K8M800 Only

FB11

30S

FB10

30S

FB9

30S

HSYNC
VSYNC

BOTTOM SIDE

VCC3 VDD3

Note: When use K8T800, this
power circuit for analog
power should be NOPOPed.

For K8T800(BOM)
Remove R352,RN52

{OrgName}

NORTH BRIDGE K8M800 (AGP & VLINK)

MS-7102

E

C265
104P

C241

C260

104P

104P

12 36Friday, July 23, 2004

0A

A

VSUSNB

AVDD1

C244
X_102P

RGBPLL

4 4

GND_RGBPLL
RGBPLL

GND_RGBPLL
DAC_PLL

GND_DAC
DAC_PLL

3 3

2 2

1 1

GND_DAC

VDD

A

AC25

AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21

W15
W16
W17
W18

W21
W22
W23
W24
W25
W26
AB2
AB3
AB4
AB5
AB6

AB9
AB10
AB15

E25
E26

V14
V15
V16
V17

R16
R17
R21
R25
T10
T11
T12
T13
T14
T15
T16
T17
U10
U11
U12
U13
U14
U15
U16
U17

D5
A5
C5
B5

A6
B6

B2
C3
D4

A4
B4

A7
D7

B7
C7

V5

W5

U10C

VSUS15/VSUS25

AVDD1
AGND1

VCCPLL1/NC
VCCPLL2/NC
GNDPLL1/NC
GNDPLL2/NC

VCCPLL3/NC
GNDPLL3/NC

DACVDD/NC
GNDDAC1/NC
GNDDAC2/NC

VCCRGB/NC
GNDRGB/NC

NC
NC

VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2

VSS/NC
VSS/NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

K8T800/K8M800

VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1
VCC1

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AA4
AA5
AB11
AB12
AB13
AB14
AB7
AB8
M8
N8
T2
T3
T4
T5
T8
T9
U2
U3
U4
U5
U8
U9
V10
V11
V12
V13
V2
V3
V4
V8
V9
W2
W3
W4
W9
Y3
Y4
Y5

AA21
AA22
AA23
AA24
AA25
AA26
AB21
AB22
AB23
AB24
AB25
AB26
F9
H10
H11
H12
H15
H16
H8
H9
J8
K19
L19
M19
P8
R19
R8
T19
U19
V18
V19
W10
W11
W12
W13
W14
W19
Y20
Y21
Y22
Y23
Y24
Y25
Y26

AB16
AC8
AC22
AC23
AC24
AE2
AE5
AE8
AE11
AE14
AE17
AE20
AE22
AE25

VDDQ

VDD

B

K8T800/K8M800 Power and Ground Connections

VCC2_5

C482 X_102P/BOT

VDD

C491 X_102P/BOT
C483 X_104P/BOT
C487 X_104P/BOT

LAYOUT : Popualte caps on the bottom side of NB.

C490 X_104P/BOT
C488 X_104P/BOT
C486 X_104P/BOT

For K8M800 Only

VDD

VDD3

VDD3

Note: When use K8T800,
these power circuit for
GFX analog power should
be NOPOPed.

B

FB7
X_80S

1 2

1 2

FB8
X_80S

1 2

1 2

FB5
X_80S

1 2

RGBPLL

CP6

CP8

GND_RGBPLL

DAC_PLL

CP7

CP5

GND_DAC

CP4

C

VDD_12_A

C485 X_0.22u/B
C484 X_475P/1206/B
C481 X_0.22u/BOTC489 X_104P/BOT

C492 X_0.22u/BOT

C479 X_0.22u/BOT

LAYOUT: Place caps on the bottom of NB

VDDQ

For K8T800(BOM)

C185
102P

C183
102P

AVDD1

C172
102P

C189
105P

C188
105P

C182
105P

C

CB8
105P/0805

CB25
X_102P/BOT

BOTTOM SIDE

BOTTOM SIDE

CB26
X_102P/BOT

Remove C185,C189,CB8
Remove C183,C188
Remove C172,C182

D

Title

Size Document Number Rev

Custom

D

Date: Sheet of

{OrgName}

NORTH BRIDGE K8M800 (POWER/GND)

MS-7102

E

13 36Thursday, July 22, 2004

E

0A

5

4

3

2

1

+12VP

VDDQ

VCC3

AGP8XDET_GC#

GGNT
ST1

WBF
SBA1

SBA3
SB_STBS

SBA5
SBA7

GAD30
GAD28

GAD26
GAD24

AD_STBS1
GC/BE#3

GAD22
GAD20

GAD18
GAD16

GFRAME

GTRDY
GSTOP

GPAR
GAD15

GAD13
GAD11

GAD9
GC/BE#0

AD_STBS0
GAD6

GAD4
GAD2

GAD0
AGPVREF_GC

3

PIRQ#A <12,16,19>
PCIRST# <16,30>
GGNT <12>GREQ<12>

DBIH <12>
WBF <12>

SB_STBS <12>

AD_STBS1 <12>

GFRAME <12>GIRDY<12>

GTRDY <12>
GSTOP <12>

GPAR <12>

AD_STBS0 <12>

AGPVREF_GC <12>

AGP8XDET_GC#

1 : 4X
0 : 8X

7 8

RN67D
8P4R-4.7K

B

C313
X_33P

8P4R-4.7K

VDDQ
VCC3
3VDUAL
VCC5
VCC12

RN67B

C

Q25
2N3904S

E

GAD[0..31]<12>

SBA[7..0]<12>

GC/BE#[3..0]<12>

VDDQ

C317

105P

Add-in Card Power

Imax

2.0A

6.0A

0.75A

2.0A

1.0A

VDDQ

+12VP

34

2

12

DS

Q23
NDS7002AS

G

R146
200RST

GAD[0..31]
SBA[7..0]
GC/BE#[3..0]

VDDQ

C312

C327

104P

104P

C280

105P

105P

V_Min V_MaxVUnits

1.425 1.575

3.15 3.45

3.15 3.45VV

4.75 5.25

11.4 12.6

RN67A
8P4R-4.7K

GPERR

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

C320

AGP PRO Slot

MS-7102

V
V

Last Revision Date:

Friday, July 23, 2004

Sheet

14 36

1

Rev

0A

of

AGP PRO
Connector

D D

C311
104P

PIRQ#B<16,19>

ST0<12> ST1 <12>
ST2<12>

RBF<12>

DBIL<12>

SB_STBF<12>

3VDUAL

AD_STBF1<12>

GDEVSEL<12>

GSERR<12>

AD_STBF0<12>

VDDQ

R183

3.32KST
R182

1.47KST

R184

1.02KST

5

GCLK_SLOT<7>

C C

B B

4X : 0.75V
8X : 0.35V

A A

VREF_CG

C314
105P

GREQ
ST0

ST2
RBF

DBIL
SBA0

SBA2
SB_STBF

SBA4
SBA6

GAD31
GAD29

GAD27
GAD25

AD_STBF1
GAD23

GAD21
GAD19

GAD17
GC/BE#2

GIRDY

GDEVSEL
GPERR
GSERR

GC/BE#1
GAD14

GAD12
GAD10

GAD8
AD_STBF0

GAD7
GAD5

GAD3
GAD1

VREF_CG

DS

VCC3

G

Q31
NDS7002AS

VDDQ

VCC

AGP1

B1

-OVRCNT

B2

5V

B3

5V

B4

USB+

B5

GND

B6

-INTB

B7

CLK

B8

-REQ

B9

3.3V

B10

ST0

B11

ST2

B12

-RBF

B13

GND

B14

RESERVED

B15

SBA0

B16

3.3V

B17

SBA2

B18

SB_STB

B19

GND

B20

SBA4

B21

SBA6

B22

RSVD/KEY

B23

GND/KEY

B24

AUX3V/KEY

B25

3.3V/KEY

B26

AD31

B27

AD29

B28

3.3V

B29

AD27

B30

AD25

B31

GND

B32

AD_STB1

B33

AD23

B34

VDDQ

B35

AD21

B36

AD19

B37

GND

B38

AD17

B39

C/-BE2

B40

VDDQ

B41

-IRDY

B42

AUX3V/KEY

B43

GND/KEY

B44

RSVD/KEY

B45

3.3V/KEY

B46

-DEVSEL

B47

VDDQ

B48

-PERR

B49

GND

B50

-SERR

B51

C/-BE1

B52

VDDQ

B53

AD14

B54

AD12

B55

GND

B56

AD10

B57

AD8

B58

VDDQ

B59

AD_STB0

B60

AD7

B61

GND

B62

AD5

B63

AD3

B64

VDDQ

B65

AD1

B66

VREF_CG

AGP8X-R

VCC3

+12VP

R137

RN67C
8P4R-4.7K

5 6

AGP8XDET_GC#

4.7K

DS

Q22
NDS7002AS

G

1 : 4X
0 : 8X 1 : 4X

4

R136
10K

12V

-TYPEDET

RESERVED

USB-

GND

-INTA

-RST

-GNT

3.3V
ST1

RESERVED

-PIPE
GND

-WBF

SBA1

3.3V

SBA3

-SB_STB
GND

SBA5
SBA7

RSVD/KEY

GND/KEY

RSVD/KEY

3.3V/KEY

AD30
AD28

3.3V

AD26
AD24

GND

-AD_STB1
C/-BE3

VDDQ
AD22
AD20

GND
AD18
AD16
VDDQ

-FRAME

RSVD/KEY

GND/KEY

RSVD/KEY

3.3V/KEY

-TRDY

-STOP

-PME
GND
PAR

AD15
VDDQ
AD13
AD11

GND
AD9

C/-BE0

VDDQ

-AD_STB0
AD6
GND
AD4
AD2

VDDQ

AD0

VREF_GC

AGP8XDET#

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

0 : 8X

AGP8XDET# <12>

AB
AG
AR

A

D5

3

3

7

1

1

8

2

2

6

4 5

4 5

DN006S

7

VCC

8

VVSYNC

6

VHSYNC

B

C

D

E

VCC

For K8T800(BOM)

F1

C139
33P

1.1A-microSMD110-S

POLY SWITCH

CB5

16

X_104P

6
1
7
2
8
3
9
4

10

5

17

JVGA1

11
12
13
14
15

4 4

C150
X_22P

FB4 30S
FB3 30S
FB2 30S

C140
X_22P

C157
33P

C149
33P

AR<12>
AG<12> DDCDATA <12>
AB<12>

R69

R76
75

R68

75

C158

75

X_22P

R80

1.8K

VCC

R81

1.8K

DDCCLK <12>

YCN15F-003-1

Trace Note:

1.The 5V traces should be 20 mils to VGA/DFP

Remove all part of the page

3 3

2 2

HSYNC<12>

VSYNC<12>

VVSYNC

VHSYNC

1
2

VCC

147

VCC

10

9

R79 22

R78 22

U8A

3

ACT08DR_SOIC14

147

U8C

8

ACT08DR_SOIC14

VHSYNC

VVSYNC

C164

C160

15P

15P

PLACE CLAMPING COMPONENT AND LEVEL
SHIFT CIRCUIT CLOSE TO VGA
CONNECTOR

147

U8B

4
5

6

ACT08DR_SOIC14

147

U8D

13
12

11

ACT08DR_SOIC14

1 1

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

A

B

C

D

http://www.msi.com.tw

VGA Connector

MS-7102

Last Revision Date:

Thursday, July 22, 2004

Sheet

15 36

E

Rev

0A

of

A

B

C

D

E

VCC3

AD[31..0]<19>

4 4

3 3

C_BE#[3..0]<19>

2 2

1 1

AD[31..0]

C_BE#[3..0]

FRAME#<19>

DEVSEL#<19>

IRDY#<19>

TRDY#<19>

STOP#<19>

SERR#<19>

PAR<19>

PERR#<19>

PCIRST#<14,30>

PIRQ#A<12,14,19>
PIRQ#B<14,19>
PIRQ#C<19>
PIRQ#D<19>
GPIO12<20>
GPIO13<20>
GPIO14<26>

PREQ#1<19>
PREQ#2<19>
PREQ#3<19>
PREQ#4<19>

PGNT#1<19>
PGNT#2<19>
PGNT#3<19>
PGNT#4<19>

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C_BE#0
C_BE#1
C_BE#2
C_BE#3

FRAME#
DEVSEL#
IRDY#
TRDY#
STOP#
SERR#
PAR
PERR#

PCIRST#

PIRQ#A
PIRQ#B
PIRQ#C
PIRQ#D
GPIO12
GPIO13
GPIO14
PIRQ#H

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
PGNT#5

H9

H10

H12J8K8L8M8N8P8R8R19

GND

GND

E8

GND

F25

GND

H23

VCC33

GND

J21

H11

VCC33

VCC33

VCC33

VCC33

GND

GND

USBGND

J25B2A17

A13

VCC33

USBGND

A15

G2

AD0

J4

AD1

J3

AD2

H3

AD3

F1

AD4

G1

AD5

H4

AD6

F2

AD7

E1

AD8

G3

AD9

E3

AD10

D1

AD11

G4

AD12

D2

AD13

D3

AD14

F3

AD15

K3

AD16

L3

AD17

K2

AD18

K1

AD19

M4

AD20

L2

AD21

N4

AD22

L1

AD23

M2

AD24

M1

AD25

P4

AD26

N3

AD27

N2

AD28

N1

AD29

P1

AD30

P2

AD31

E2

CBE0

C1

CBE1

L4

CBE2

M3

CBE3

J1

FRAME

H2

DEVSEL

J2

IRDY

H1

TRDY

K4

STOP

C2

SERR

F4

PAR

C3

PERR

R1

PCIRST

A4

INTA

B4

INTB

B5

INTC

C4

INTD

D4

INTE

E4

INTF

A3

INTG

B3

INTH

A5

REQ0

B6

REQ1

C5

REQ2

D5

REQ3

P3

REQ4

R3

REQ5

A6

GNT0

D6

GNT1

C6

GNT2

E5

GNT3

R4

GNT4

R2

GNT5

GND

GND

A1A2B1

VCC33

VCC33

VCC33

USBGND

USBGND

USBGND

A19

A21

VCC33

VCC33

USBGND

USBGND

B13

B15

T8

VCC33

VCC33

USBGND

USBGND

B17

B19

T19

U8

VCC33

VCC33

USBGND

USBGND

B21

C13

U19V8V19

VCC33

VCC33

USBGND

USBGND

C14

C15

C16

V21W9W10

VCC33

VCC33

VCC33

USBGND

USBGND

USBGND

C17

C18

C19

W11

W17

W18

VCC33

VCC33

VCC33

USBGND

USBGND

USBGND

C20

C21

D13

W19

W21

Y21

VCC33

VCC33

VCC33

USBGND

USBGND

USBGND

D15

D17

D19

W8

VCC33

VCC33

USBGND

USBGND

USBGND

D21

E13

E15

USBGND

USBGND

USBGND

E17

E19

USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD
USBVDD

USBSUS25

PLLVDDA
PLLVDDA

PLLGNDA
PLLGNDA

USBOC0
USBOC1
USBOC2
USBOC3
USBOC4
USBOC5
USBOC6
USBOC7

USBCLK

USB REXT

UDPWREN

KBCK/KA20G

KBDT/KBRC

MSCK/IRQ1

MSDT/IRQ12

USBGND

USBGND

USBGND

E21

H13

H15

H14

USBP0+
USBP0­USBP1+
USBP1­USBP2+
USBP2­USBP3+
USBP3­USBP4+
USBP4­USBP5+
USBP5­USBP6+
USBP6­USBP7+
USBP7-

UDPWR

USBGND

USBGND

USBGND

H16

H17

U18A

A22
B22
C22
D22
E22
F22
J13
J14
J15
J16
J17
J18

C24

A23
B23

D23
C23

E20
D20
A20
B20
E18
D18
A18
B18
D16
E16
A16
B16
D14
E14
A14
B14

C26
D24
B26
C25
B24
A24
A26
A25

E23
B25
D26

D25

W3
V1
W1
W2

USBGND

VT8237

H18

3VDUAL

+

CB18
104P

EC30
X_ELS10/16-B

C370

104P

near SB

CB17
104P

VSUS2_5

VCC2_5

CB14

CB16

105P

104P

USBP0
USBN0
USBP1
USBN1
USBP2
USBN2
USBP3
USBN3
USBP4
USBN4
USBP5
USBN5
USBP6
USBN6
USBP7
USBN7

USB_OC#1

USB_OC#4

USBCLK_SB

USBREXT

R252 10K RN95

R255

5.11KST

KBCLK# <27>
KBDAT# <27>
MSCLK# <27>
MSDAT# <27>

R258
820

PLOCK#<19>

USBP0 <24>
USBN0 <24>
USBP1 <24>
USBN1 <24>
USBP2 <24>
USBN2 <24>
USBP3 <24>
USBN3 <24>
USBP4 <24>
USBN4 <24>
USBP5 <24>
USBN5 <24>
USBP6 <24>
USBN6 <24>
USBP7 <24>
USBN7 <24>

USB_OC#1 <24>

USB_OC#4 <24>

USBCLK_SB <7>

DEVSEL#
TRDY# PIRQ#C
IRDY#
FRAME#

SERR#
PERR#
STOP#
PLOCK#

PREQ#0
PREQ#5

VCC3

PGNT#5
PGNT#0

R296 2.7K
R280 2.7K

8P4R-2.7K

1 2
3 4
5 6
7 8

RN96

8P4R-2.7K

1 2
3 4
5 6
7 8

R284 2.7K
R319 2.7K

VT8237
B01-0823715-V01

A

B

C

D

VCC3

104PCB10
104PCB23
104PCB20
104PCB19
X_104P/BCB27

BOTTOM SIDE

VCC VCC

PIRQ#D
PIRQ#B

PIRQ#A

GPIO12
PIRQ#H
GPIO14
GPIO13

RN97

8P4R-2.7K

1 2
3 4
5 6
7 8

RN99

8P4R-2.7K

1 2
3 4
5 6
7 8

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

N o. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

VT8237 Part 1

MS-7102

Last Revision Date:

Sheet

E

Rev

Thursday, July 22, 2004

16 36

of

0A

A

J9

J10

J11

K9L9J12

PDD[15..0]<22>

4 4

3 3

2 2

VCC2_5

1 1

PDD[15..0] PDD0

PDREQ<22>

PDDACK#<22>

PDIOR#<22>
PDIOW#<22>
PIORDY<22>
PDCS#1<22>
PDCS#3<22>

PDA0<22>
PDA1<22>
PDA2<22>

IRQ14<22>

SDREQ<22>

SDDACK#<22>

SDIOR#<22>
SDIOW#<22>
SIORDY<22>
SDCS#1<22>
SDCS#3<22>

SDA0<22>
SDA1<22>
SDA2<22>

IRQ15<22>

STXP_1
STXN_1

SRXN_1
SRXP_1

STXP_2
STXN_2

SRXN_2
SRXP_2

CP13

12

FB24 X_80S

12

SDD[15..0]

near chipset

VT8237

C397
104P

SDD[15..0]<22>

Using external PHY

PDREQ
PDDACK#
PDIOR#
PDIOW#
PIORDY
PDCS#1
PDCS#3
PDA0
PDA1
PDA2
IRQ14

SDDACK#

SDIOR#
SDIOW#
SIORDY

SDCS#1

SDCS#3

C378
104P

R249 360RST

103PC395
103PC393

122PC396
122PC394

103PC384
103PC381

122PC385
122PC382

near chipset

+2.5VSATA

C383CP14
105P

A

SDREQ

SDA0
SDA1
SDA2

IRQ15

SIDEVREF
SIDECOMP

STXP1
STXN1

SRXN1
SRXP1

STXP2
STXN2

SRXN2
SRXP2

PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8

PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

CM2
475P/0805

GNDSATA

AA22

Y24
AA26
AA25
AB26
AC26
AC23
AD25
AD26
AC24
AC25
AB24
AB23
AA24

Y26
AA23

Y23

V24

W26

Y25

Y22

V22

V23

W23

V25

W24

AD24
AC20

AB20
AC21
AE18
AF18
AD18
AD19
AF19
AE20
AF20
AD20
AE21
AF21
AD21
AD22
AF22

AD17
AD23
AF23
AE23
AF17
AF25
AF26
AF24
AC22
AE24
AE26

AC19
AB21
AB13

AC13
AF13

AE13
AB15

AC15
AF15

AE15

W12
W13
W14
W15
W16

AC17
AC11
AB17
AB11

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

PDDREQ
PDDACK
PDIOR
PDIOW
PDRDY
PDCS1
PDCS3
PDA0
PDA1
PDA2
IRQ14

SDD0/TBC1
SDD1/VALID
SDD2
SDD3/RXD2
SDD4/RXD3
SDD5/RXD4
SDD6/RBC0
SDD7/RBC1
SDD8/RXD5
SDD9/RXD6
SDD10/RXD7
SDD11/RXD8
SDD12/RXD9
SDD13/TXD0
SDD14/TXD1
SDD15/TXD2

SDDRQ/RXD1
SDDACK/TBC0
SDIOR/TXD4
SDIOW/TXD3
SDRDY/RXD0
SDCS1/TXD8
SDCS3/TXD9
SDA0/TXD6
SDA1/TXD5
SDA2/TXD7
IRQ15

SVREF
SCOMPP
STXP1

STXN1
SRXN1

SRXP1
STXP2

STXN2
SRXN2

SRXP2
VDDATS

VDDATS
VDDATS
VDDATS
VDDATS

VDDAS
VDDAS
VDDAS
VDDAS

VDD

GNDATS

AB14

AC14

VDD

VDD

GNDATS

GNDATS

AD12

AD13

VDD

VDD

VDD

GNDATS

GNDATS

GNDATS

AD14

AD15

L18

VDD

GNDATS

AD16

B

M9

M18N9N18P9P18R9R18T9T18U9U18V9V10

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

GNDATS

GNDATS

GNDATS

GNDATS

GNDATS

GNDATS

GNDAS

GNDAS

GNDAS

AF14

AE12

AE14

AE16

AF12

AF16

AC16

AC12

AB16

AB12

B

VDD

VDD

GNDAS

V11

V12

VDD

VDD

VDD

VDD

GND

GND

GND

F6F7J5K5P5

V13

V14

VDD

GND

V15

VDD

GND

R5

V16

VDD

GND

L11

3VDUALVCC2_5

AA4

AB4

AB5

AB6

V17

V18

VDD

VDD

VDD

VSUS33

VSUS33

VSUS33

ACSDIN3/SLP_BTN

AOLGP/THRM

GPIOA/Strap1
GPIOB/Strap2
GPIOC/Strap0
GPIOD/Strap3

GND

GND

GND

GND

GND

GND

GND

L13

L14

L15

L16

M11

L12

M12

PDDACK#

VT8237

1 - Disable external SATA PHY

PDCS#1

VT8237

SATA master/slave mode
1 - Disable 0 - Enable

VSUS2_5

T4

U4

VSUS33

VSUS25

ACBITCLK

ACSDIN0
ACSDIN1
ACSDIN2

ACSYNC

ACSDO
ACRST

BATLOW
CPUMISS

SUSST1

EXTSMI

SMBALRT

PWRBTN

PWROK
CLKRUN
CPUSTP

PCISTP

INTRUDER

SUSCLK
SMBCK1

SMBDT1
SMBCK2

SMBDT2

SUSA
SUSB
SUSC

GPO0
GPO1

SERIRQ

SPKR

TEST
VDDA0
GNDA0

SREXT

SXO/Strap4

SXI/Strap5

VDDA33
GNDA33

GND

GND

GND

M13

M14

M15

U18B

VSUS25

T1
U3
V2
U1
V3
T2
U2
T3

W4

PME

V4
Y1
Y2

RING

Y3
Y4
AA1
AB1
AC1

LID

AD2
AF1
AB7
AC7
AD6

AE1
AB3
AC4

AB2
AC3

AD1
AA2

AD3
AF2

AE2

GPI0

AC2

GPI1

AA3
AE3
AE5
AD5
AF5
AC6

AD9
AF8
AB8

OSC

AF9

TPO

AE9
AC10
AB10
AD11
AE10
AF10
AE11
AF11
W5

GND

V5

GND

M16

GND

N11

GND

N12

GND

N13

GND

N14

GND

N15

GND

N16

GND

GND

GND

K18

VT8237

R235 10K

R216 10K
R215 X_10K

C

VCC2_5

105P/BC496
105P/BC495
104PCB15
105P/BCB28

CM1 475P/0805

AC_BITCLK
AC_SDIN0
AC_SDIN1
AC_SDIN2

AC_SDIN3
ACSYNC
ACSDO
ACRST

PCI_PME#

CLEAR_PWD#

CPUMISS

RI#

SUSST#

THRM#

EXTSMI#
SMBALRT#

ATADET1

PWRBTN#_S

PWROK_NB#

CLKRUN#

CPUSTP#
PCISTP#

INTRUDER

SUSCLK

SMBCLK1

SMBDATA1

SMBCLK2

SMBDATA2

SUSA#

SUSB#

SUSC#

GPI0

ATADET0

SUSLED

GPO1 PCISTP#

GPIOA

GPIOB

GPIOC

GPIOD

SERIRQ

SPKR

SB_OSC14

TPO

TEST

1 2

SREXT

SXO

SXI
VDDA33

1 2

C

VCC3

VCC3

1
3
5
7

CP26

AC_SYNC

2

AC_SDOUT

4

AC_RST#

6

RN104

8

8P4R-22

PCI_PME# <19,25>
CLEAR_PWD#

RI# <28>
SUSST# <12>
THRM# <25>

ATADET1 <22>
PWROK_NB# <12>

SMBCLK1 <7,8,18,30>
SMBDATA1 <7,8,18,30>

SUSB# <30>
SUSC# <30>

ATADET0 <22>

SERIRQ <25>
SPKR <28>
SB_OSC14 <7>

VCC2_5

C497
105P/B

CP25

R277

5.9KST

C400
104P

C409
15P

FB25 X_80S

1 2

CP15

SXO
SXI

X3

1 2

YCRY25H

STXP_1
STXN_1

SRXN_1
SRXP_1

AC_BITCLK <21>
AC_SDIN0 <21>

AC_SYNC <21>
AC_SDOUT <21>
AC_RST# <21>

VCC3

C408
15P

SATA2

8
1
2

3
4
5

6
7
9

SATACONN

C277
X_47P

D

VT8237

*"ACSYNC" => LPC FWH Command

0 - Enable FWH
1 - Disable FWH(Default)

ACSYNC

R297 4.7K

GPI0

INTRUDER

AC_SDIN0
AC_SDIN2
AC_SDIN1
AC_SDIN3

TEST

CLKRUN#

SUSA#

SUSLED
SUSCLK
EXTSMI#
CPUMISS
RI#

SUSST#
THRM#

PCI_PME#
PWROK_NB#
PWBTIN#
GPO1
SMBALRT#

SUSB#
SUSC#
ATADET0
SPKR
SERIRQ
CPUSTP#

TPO

SMBCLK2
SMBDATA2
SMBDATA1
SMBCLK1

C271
X_47P

STXP_2
STXN_2

SRXN_2
SRXP_2

D

R334 1M
R335 1M

7
5
3
1

R322 4.7K
R302 4.7K

R306 4.7K

R318 X_4.7K

R310 X_4.7K
R320 X_4.7K
R298 X_4.7K

R321 4.7K

8
6
4
2

8
6
4
2

1
3
5
7
1
3
5
7
1
3
5
7

1
3
5
7

7
5
3
1

RN103
8P4R-2.7K

SATA1

8
1
2

3
4
5

6
7
9

VCC3

RN105
8P4R-4.7K

2
4

RN107

6

8P4R-4.7K

8
2
4

RN106

6

8P4R-4.7K

8
2
4

RN108

6

8P4R-4.7K

8

2
4
6
8

SATACONN

3VDUAL

VCC3

*"SA[17:16]" => LDT Frequency
0 0 - 200MHz (Default)
01 - 400MHz
10 - 600MHz
11 - 800MHz

*"SA18" => LDT Width

0 - 8-Bit (Default)
1 - 16-Bit

*"SA19" => Fast command

VBAT

3VDUAL

VCC3

RN94
8P4R-4.7K

0 - Disable (Default)
1 - Enable

GPIOD
GPIOC
GPIOA
GPIOB

K8M800 should be concren with
VD[0,1,2,5,6,7]

K8T800 should be concren with
VD[0,1,2,3,5,6,7]

Strapping

VCC3

*"PDA1/SDA1" => External loop test mode

0 - Disable (Default)
1 - Enable

R246 1K

*"PDA2/SDA2" => ROMSIP Select

0 - Disable
1 - Enable(Default)

R247 X_1K

VCC3

R241 1K

*"-SDCS3" => Test Mode Select

0 - Disable (Default)
1 - Enable

R228 1K

1
3
5
7

Reserved only : should not populated

VCC3

PWRBTN#_S

R225 X_1K
R248 1K

ACSDO

R295 4.7K

0/1:Enable/disable auto reboot

R301
100

C428
X_104P

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

VT8237 Part 1

MS-7102

E

(VD[2])

(VD[3])

RN100
8P4R-4.7K

2
4
6
8

VT8237

PWBTIN#

Last Revision Date:
Sheet

E

(VD[1:0])

SA17

(VD[1])

SA18

(VD[2])

SA16

(VD[0])

SA19

(VD[3])

(VD[5])

PDA1

VT8237

(VD[6])

PDA2

VT8237

(VD[7])

PDCS#3

VT8237

PDA0

VT8237

(VD[4])

PWBTIN# <28>

Rev

0A

Wednesday, July 21, 2004

17 36

of

A

N21

N22

N23

N24

N25

N26

P22

P23

P24

P25

VCCVK

VCCVK

GND

GND

R13

R12

VCCVK

VCCVK

GND

GND

R15

R14

P26

VCCVK

VCCVK

GND

GND

R16

R21

L21

K21

VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VD8
VD9
VD10
VD11
VD12
VD13
VD14
VD15

VBE
UPCMD

DNCMD
UPSTB

UPSTB
DNSTB

DNSTB

VPAR
VLREF
VCOMPP
VCLK

VIOUT
VIIN

LAD0
LAD1
LAD2
LAD3

LFRM
LREQ0
LREQ1

PWRGD
RSMRST

VBAT
RTCX1
RTCX2

L23

VCCVK

P11

VCCVK

VCCVK

GND

GND

P12

P13

VCCVK

VCCVK

GND

GND

P14

P15

VCCVK

VCCVK

GND

GND

P16

R11

VLAD[0..7]

4 4

VBE0#<12>

UPCMD<12>
DNCMD<12>

UPSTB<12>

UPSTB#<12>

VCLK<7>

DNSTB<12>

DNSTB#<12>

R230
360RST

3 3

VPAR<12>

VLAD0
VLAD1
VLAD2
VLAD3
VLAD4
VLAD5
VLAD6
VLAD7

VBE0#
UPCMD

DNCMD
UPSTB

UPSTB#
DNSTB

DNSTB#

VPAR
VLREF_SB
VCOMPP_SB
VCLK

H25
G26
K26

J23

F26
G25
K22
K24
E24
G23

L26

L25
E26
E25

L24
M26

G24
K23

K25

J26

J24
H26

H24

F24
H22

J22

L22

F23
G22

LPC_AD0<25>
LPC_AD1<25>
LPC_AD2<25>
LPC_AD3<25>

2 2

LPC_FRAME#<25>

LPC_REQ#<25>

ALL_PWRGD<28,30>

RSMRST#<30>

solder side

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

LPC_FRAME#

LPC_REQ#

ALL_PWRGD

RSMRST#

VBAT

X_103PC500

X1

AD8
AF7
AE7
AD7

AF6
AE6
AE8

AC5
AD4

C419X_103P

AF4
AE4
AF3

X2

1 2
3 4

C429
10P

YCRY32.768C

1 1

Y2

C433
10P

A

B

M24

M21

M22

M23

M25

L19

M19

N19

P19AA21

VCCVK

VCCVK

VCCVK

VCCVK

VCCVK

VCCVK

VCCVK

VCCVK

VCCVK

VCCVKGND

GND

GND

GND

GND

GND

GND

T11

T12

T13

GND

T14

T15

T16

W22

GND

W25

GND

GND

AB19

GND

AB22

AB25

For K8T800(BOM)

1)R204--->R354

2)R229--->R355

B

VSUS2_5

GND

GND

GND

AC18

AE17

D12

E12

MIISUS25

MIISUS25

GND

GND

AE19

AE22

AE25

GND

AA9

3VDUALVCC2_5

D9

GND

AB18

MIIVCC

GND

T21

E11E9E10

MCRS

MIIVCC

MIIVCC

MIIVCC

MTXENA

MTXD0
MTXD1
MTXD2
MTXD3

MTXCLK

MRXER

MRXCLK

MRXDV

MRXD0
MRXD1
MRXD2
MRXD3

MDCK

PHYRST

RAMVCC

RAMGND

IGNNE

STPCLK

DPSLP
VGATE

VIDSEL

VRDSLP

AGPBZ/GPI6

PCICLK

APICCLK

APICD0/APICCS

APICD1/APICACK

PLLVCC
PLLGND

GND

GND

GND

AA10

K19

MCOL

MDIO

EECS
EEDO

EEDI

EECK

FERR
A20M

INIT

INTR

NMI
SMI

SLP

GHI

U18C

A11
B11

C11
A10
B10
B9
A9
C10

D10
C9
D8
C8
B8
A8
C7

A7
B7

D7
D11

B12
A12
C12

E7

E6
U24

U26
T24
R26
T25
T26
U25
R24
V26
R22
P21

AC9
AC8
AB9
AD10

R23
U23
R25

T23
T22
U22

VT8237

C

MII_CRS
MII_COL

MTXEN
MTXD0

RN92D

MTXD1

RN92C 5 6

MTXD2

RN92A

MTXD3

RN92B 3 4

MII_TXCLK
MII_RXER

MII_RXCLK
MII_RXDV

MII_RXD0
MII_RXD1
MII_RXD2
MII_RXD3

MMDC

MMDIO
MMRST#

MII_EECS#

MII_EEDO

MII_EEDI

MII_EECK

+2.5VRAM

GND_RAM

FERR#
A20M#
IGNNE#
CPUINIT#
INTR
NMI_SB
SMI#
STPCLK#
SLP#
GHI#
DPSLP#

VGATE
VIDSEL
VRDSLP
AGPBZ#

SB_PCLK

APICCLK
CLEAR_CMOS#

APICD1#
+2.5VSBPLL
GND_SBPLL

VLREF_SB:

VCC2_5

R204

4.87KST 104P

VLREF_SB

665RST

C

JI2C

SMBDATA1

SM_DATA

SM_CLK

GND
KEY

5VSB

YJ1X5-1

R272 33

7 8
1 2

R274 33
R278 33

R283 33

1 2

1
2

SMBCLK1

3
4
5

MII_CRS <23>
MII_COL <23>

MII_RXER <23>
MII_RXCLK <23>
MII_RXDV <23>
MII_RXD0 <23>
MII_RXD1 <23>
MII_RXD2 <23>
MII_RXD3 <23>

MII_EECS# <23>
MII_EEDO <23>
MII_EEDI <23>
MII_EECK <23>

CP27

5VSB

MII_TXEN

MII_TXD0
MII_TXD2

MII_TXD3

MII_MDIO

R273 2.2

CB21

MII_MDC

MII_RST#

SMBDATA1 <7,8,17,30>
SMBCLK1 <7,8,17,30>

8P4R-33

MII_TXEN <23>
MII_TXD0 <23>
MII_TXD1 <23>
MII_TXD2 <23>
MII_TXD3 <23>
MII_TXCLK <23>

MII_MDC <23>
MII_MDIO <23>

MII_RST# <23>

R550 should be
populate for VT8237CD

VCC2_5

ALL_PWRGD

VGATE

-LDTSTOP <5,11>

R294
X_1K

SATAACT# <28>

SB_PCLK <7>
APICCLK <7>

CLEAR_CMOS#

CP10

12

CB12

104P

FB20 X_80S

VCC2_5

12

CP9

K8M800 will be 0.3V(R204/R229=4.87KRST/665RST)
K8M800 will be 0.3V(R204/R229=3KRST/410RST)
K8T800 will be 0.625V(R204/R229=3KRST/1KRST)

=>2.5x(0.665/5.535)=0.30V

=>2.5x(0.41/3.41)=0.30V

=>2.5x(01/4)=0.625V

C336

C348R229
104P

Impact VGA Display.

vdd/4=0.625volt

D

MII Lan

MMDIO

MII_EEDIMII_TXD1
MTXEN

IGNNE#
A20M#
INTR
SMI#

CPUINIT#
NMI_SB
STPCLK#

NOTEBOOK SIGNALS

5VSB

VBAT1
YBA3V

D

R293 X_4.7K
R292 4.7K

104P CB13

R281 1.5K

R271 X_10K
R263 10K

R221 10K

FERR#
SLP#

APICD1#
APICCLK

DPSLP#
GHI#

AGPBZ#
VIDSEL

VRDSLP

R224
1K

R212
3K

R282 4.7K

R205 4.7K

R239
1K

VCC3

Signal Pin# Function Description

A12

EEDI Eliminate

External LAN
EEPROM

L: Disable. Use external EEPROM
H: Enable. Do not use external
EEPROM
Default setting: Disable

VCC3

3VDUAL

VCC3

VT8237

*"EEDI" => Eliminate Lan EEPROM
0/1:Disable/Enable

RN74

1 2
3 4
5 6
7 8

VCC3

X_8P4R-680(OPT)

RN77

1 2
3 4
5 6
7 8

X_8P4R-680(OPT)

R207 1K
R208 X_4.7K

R206 330
R231 X_4.7K105P

R234 4.7K
R238 4.7K

R276 4.7K

2

LEGEND SPEC:

VBAT

C360
475P

12

D9
BAT54C

3

C359

X_106P/1206

R254
1K

3
1

JBAT1

YJ103

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

N o. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

VT8237 Part 1

MS-7102

E

JBAT1(2-3):Normal
JBAT1(1-2):Clear CMOS

VBAT

Last Revision Date:

Friday, July 23, 2004

Sheet

18 36

E

of

Rev

0A

5

PCI Connectors

VCC3

VCCVCC

D D

PIRQ#B<14,16>

PIRQ#D<16>

PCICLK1<7>

C C

IRDY#<16>

DEVSEL#<16>

PLOCK#<16>

PERR#<16>
SERR#<16>

B B

-12V

PIRQ#B PIRQ#C
PIRQ#D

PCICLK1
PREQ#1
AD31

AD29
AD27

AD25
C_BE#3

AD23
AD21

AD19
AD17

C_BE#2
IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD7
AD5

AD3

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

B1
B2
B3
B4
B5
B6
B7
B8
B9

PCI1

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RSVD2
PRSNT2#
GND
GND
RSVD5
GND
CLK
GND
REQ#
+5V
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3#
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V
ACK64#
+5V
+5V

YSLOT120

TRST#

+12V

TMS

INTA#

INTC#
RSVD1
RSVD3

GND
GND

RSVD4

RST#
GNT#

GND

RSVD6

AD30
+3.3V
AD28
AD26

GND

AD24

IDSEL#

+3.3V
AD22
AD20

GND
AD18
AD16
+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR
AD15
+3.3V
AD13
AD11

GND

AD9

C/BE0#

+3.3V

AD6

AD4

GND

AD2

AD0

REQ64#

TDI
+5V

+5V
+5V

+5V

+5V
+5V

+5V

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

IDSEL= AD16
INT#= A, B, C, D

VCC3

+12VP

PIRQ#A

3VDUAL

PCIRST2#
PGNT#1
PCI_PME#

AD30
AD28

AD26
AD24

AD16
AD22

AD20
AD18

AD16
FRAME#
TRDY#
STOP#

PAR
AD15

AD13
AD11

AD9

C_BE#0AD8
AD6

AD4
AD2

AD0AD1

3VDUAL

C_BE#[3..0]<16>

4

AD[31..0]<16>

C310
X_104P

AD[31..0]

C_BE#[3..0]

PIRQ#A <12,14,16>
PIRQ#C <16>

PCIRST2#<30>

PCI_PME# <17,25>

FRAME# <16>
TRDY# <16>
STOP# <16>

PAR <16>

3

VCC3

VCC VCC

-12V

PIRQ#C
PIRQ#A

PCICLK2

PCICLK2<7>

PREQ#2
AD31

AD29
AD27

AD25
C_BE#3

AD23
AD21

AD19
AD17

C_BE#2
IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD8
AD7

AD5
AD3

AD1

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

B1
B2
B3
B4
B5
B6
B7
B8
B9

PCI2

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RSVD2
PRSNT2#
GND
GND
RSVD5
GND
CLK
GND
REQ#
+5V
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3#
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V
ACK64#
+5V
+5V

YSLOT120

TRST#

+12V

TMS

+5V
INTA#
INTC#

+5V

RSVD1

+5V

RSVD3

GND
GND

RSVD4

RST#

+5V
GNT#

GND

RSVD6

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL#

+3.3V

AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR
AD15

+3.3V

AD13
AD11

GND

AD9

C/BE0#

+3.3V

AD6
AD4

GND

AD2
AD0
+5V

REQ64#

+5V
+5V

VCC3

+12VP

A1
A2
A3
A4

TDI

A5

PIRQ#B

A6

PIRQ#D

A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

3VDUAL

PCIRST2#
PGNT#2
PCI_PME#

AD30
AD28

AD26
AD24

AD17
AD22

AD20
AD18

AD16
FRAME#
TRDY#
STOP#

PAR
AD15

AD13
AD11

AD9

C_BE#0
AD6

AD4
AD2

AD0

IDSEL= AD17
INT#= B, C, D, A

2

3VDUAL

C398
X_104P

VCC

-12V

PIRQ#D
PIRQ#B

PCICLK3<7>

PCICLK3
PREQ#3
AD31

AD29
AD27

AD25
C_BE#3

AD23
AD21

AD19
AD17

C_BE#2
IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD8
AD7

AD3
AD1

B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49

B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62

B1
B2
B3
B4
B5
B6
B7
B8
B9

PCI3

-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RSVD2
PRSNT2#
GND
GND
RSVD5
GND
CLK
GND
REQ#
+5V
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3#
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2#
GND
IRDY#
+3.3V
DEVSEL#
GND
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
GND
AD12
AD10
GND

AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+5V
ACK64#
+5V
+5V

YSLOT120

TRST#

+12V

TMS

+5V
INTA#
INTC#

+5V

RSVD1

+5V

RSVD3

GND

GND

RSVD4

RST#

+5V
GNT#

GND

RSVD6

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL#

+3.3V

AD22
AD20

GND

AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

AD9

C/BE0#

+3.3V

AD6

AD4

GND

AD2

AD0

+5V

REQ64#

+5V

+5V

1

VCC3VCC3

VCC

+12VP

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

PIRQ#C
PIRQ#A

3VDUAL

PCIRST2#
PGNT#3
PCI_PME#

AD30
AD28

AD26
AD24

AD18
AD22

AD20
AD18

AD16
FRAME#
TRDY#
STOP#

PAR
AD15

AD13
AD11

AD9

C_BE#0
AD6

AD4AD5
AD2

AD0

IDSEL= AD18
INT#= C, D, A, B

RN98

PGNT#2
PGNT#3
PGNT#4

1 2
3 4
5 6
7 8

PGNT#1<16> PREQ#1<16>
PGNT#2<16>

A A

PGNT#3<16> PREQ#3<16>

5

8P4R-2.7K

PREQ#1PGNT#1
PREQ#2

PREQ#2<16>

PREQ#3
PREQ#4

PREQ#4<16>PGNT#4<16>

4

RN93

7 8
5 6
3 4
1 2

8P4R-2.7K

VCCVCC3

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

3

2

http://www.msi.com.tw

PCI Connector 1 & 2 & 3

MS-7102

Last Revision Date:
Sheet

1

Wednesday, July 21, 2004

19 36

Rev

0A

of

FAN

5

4

+12V

3

2

1

D

Q7

P3055LS

D D

C6

0.1u

1
2
3
4
5
6
7

U4

FAN1_IN
FAN2_IN
VCC12
C1
C2
CHRPMP
GND

83391TS

FAN1_DRV
FAN1_SEN
FAN2_DRV
FAN2_SEN
FAN3_DRV
FAN3_SEN

FAN3_IN

14
13
12
11
10
9
8

FAN1_SEN
FAN2_SEN

CPUFAN_OUT<25>
SYSFAN_OUT<25>

C C

B B

+12V

CPUFAN_OUT
SYSFAN_OUT

C7 0.1u

C17

0.1u

G

C26
X_103P

R21 10KST

R14

6.49KST

C25
X_103P

R83 10KST

R84

6.49KST

S

+

EC7
ELS10/16V

Q19

4 5
3
2
1

N-FDS4410_SO8

+

EC10
ELS10/16V

6
7
8

R20
X_0/0805

C28
X_102p

R90
X_0/0805

CPU FAN

R15

4.7K

CPUFAN1

3
2
1

D1x3-WH-SN

+12V

SYSTEM FAN

R92

4.7K

CHSFAN1

3
2
1

D1x3-WH-SN

R22 27K

CPUFAN2

4
3
2
1

X_D1x4

R88

R89

27K

CHSFAN2

4
3
2
1

X_D1x4

10K

R27 10K

CPUFAN_IN <25>

GPIO12 <16>

SYSFAN_IN <25>

GPIO13 <16>

A A

Micro Star Restricted Secret

Title

Document Number

5

4

3

2

FAN

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

20 36

1

Rev

0A

of

AC655 AC97 CODEC

X_22P

BIT_CLK

C402

EMI request closed to ALC655@930715

C418
103P

AUD_CLK<7>

AC_SDOUT<17>
AC_BITCLK<17>

AC_SDIN0<17>
AC_SYNC<17>

AC_RST#<17>

R291
X_10K

R279 22
C404 21
10P

AUDIO CODE CD IN HEADERS

JCD1

CDL

4
3

CDGND

CD IN

2
1

CD-D1x4-BK-SBTJ

CDR

Onboard Header for Lenovo

FMIC_IN

R337 1K

C448

E_102P

SPEAKER_R
SPEAKER_L

VCC3

R325

R290
X_10K

4.7K

C422 104P

XTL_OUT

R287

C399

10

104P

BIT_CLK

R275
33

R3291K
R3301K
R3311K

R326

4.7K
C440

X_475P/0805

SPEAKER_R
SPEAKER_L

H2X4(8)_black

C441 102P
C442 102P

VCC3

R266X_47K
R265X_47K
R264X_47K

+5VR

JAUDIO1

1 2
3 4
5
7

C388
105P
C387
105P
C386
105P

6

R305

0

4847464544424140394338

NC

1

DVDD1

2

XTL_IN

3

XTL_OUT

4

DVSS1

5

SDATA_OUT

6

BIT_CLK

7

DVSS2

8

SDATA_IN

9

DVDD2

10

SYNC

11

RESET#

12

PC_BEEP

PHONE

1314151617181920212223

JD2_LINEIN
JD1_LINEOUT

12
12
12

LINE_OUTR
LINE_OUTL

NC

TEST6

TEST5

AUXL

AUXR

CDLX
CDGNDX
CDRX

TEST4

TEST1

AVSS2

VIDEOL

VIDEOR

TEST2

DACOUTR

CDL

CDGND

CDR

JD0_MICIN

37

AVDD2

DACOUTL

MIC1

MIC2

C391

1 2

105P/0805

1 2

105P/0805

C392

LOUTR

LOUTL

MONO

VRDA
VRAD

AFILT2
AFILT1

VREF

AVSS1
AVDD1

LINL

LINR

U19
ALC655

24

VREF_OUT

VREF_OUT

BOTTOM SIDE

CB24

104P

1 2

LINE_ROUT

36

LINE_LOUT

35
34

NC
NC

NC

C430
105P

33
32

31
30

29

VREF_OUT

28
27
26

25

+5VR

CB22
104P

1 2

C389 105P/0805

C390 105P/0805

R267 33K
R268 33K 1 2

D111N4148S

R262 4.7K

A C

MIC2

R269 1K

D101N4148S

A C

1 2

12

C380

R269 Reserved for

X_103P

ALC650
BASS/CENTER

DECOUPLING CAPACITOR

1 2

1 2

FB28
X_0

+5VR

FMIC

CT15
X_105P/0805

1 2

R261 4.7K

1 2

R270
1K

C358
E_104P

12

C407
104P

CP17
CP281 2
CP12
CP241 2

EC33
ELS10/16-B

+

EC34
ELS10/16-B

12

C414
104P

+5VR

LINE_R

LINE_L

MIC2_IN

MIC_IN

R156
X_33K

X_33K

R285

VREF_OUT

X_4.7K

FB26 X_80S1 2

+

FB27 X_80S

1 2

R304
1K

R289
X_4.7K

12
12

12

C417
102P

JD2_LINEIN

FB17

1 2

FB18

1 2

FB13

1 2

FB14

1 2

JD0_MICIN

C250
X_104P

12

C420
102P

80S

80S

80S

80S

PGND

FMIC

FMIC_INXTL_IN

12

C421
105P

R233 0

C339

X_475P/0805

C289

E_560P

C285
102P

R232 0

C338

X_475P/0805

12

C423
105P

+12V

R200 10K

C288
E_560P

C286
102PR157

FB23

1 2

SPEAKER_R
SPEAKER_L

12

C424
X_473P

R199 10K

80S

10
11
12
13
18
16

14

C377
104P

+

EC27

X_10U/16V/S

AUDIO CODE REGULATORS

U16
YLT1087S-0.8A

3 2

VIN VOUT

ADJ

1

R259
100RST

R260
300RST

+

EC26

ELS10/16-B

+5VR

C374
X_104P

SPEAKER OUT JACK

JD1_LINEOUT

LINE_OUTR

LINE_OUTL

J1C

Line-In

Top

PJ1X3-BGR

J1A

1
2

Mic

4
5
3

Bottom

PJ1X3-BGR

R327
X_33K
R328
X_33K

R150 0

C290

X_475P/0805

FB16

1 2

FB15

1 2
12
12

C415X_22P

X_YCRY24.576

C406X_22P

80S

80S

X2

R149 10K

C284
E_560P

C287
E_560P

6
7
8

9
17
15

XTL_IN

R286
X_1M

XTL_OUT

N54-13F0031-F02

J1B

Line-Out

Middle

PJ1X3-BGR

Line_IN

Line_OUT

MIC_IN

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR

AC'97 AUDIO

MS-7102

21 36Friday, July 23, 2004

0A

5

ATA 33/66/100 Connector

PRIMARY IDE CONN.

R148

D D

C C

B B

HDDRST#<30>

IDEACTP#<28>

IDEACTS#<28>

HDDRST#

33

PDD_7
PDD_6
PDD_5
PDD_4
PDD_3
PDD_2
PDD_1
PDD_0

PDREQ_R
PDIOW#_R
PDIOR#_R
PIORDY_R
PDDACK#_R
IRQ14_R
PDA1_R
PDA0_R PDA2_R
PDCS#1_R
IDEACTP#

IDE1

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

YJ220-Y-1

Blue color

SECONDARY IDE CONN .

R147

HDDRST#

33

SDD_7
SDD_6
SDD_5
SDD_4 SDD_11
SDD_3 SDD_12
SDD_2
SDD_1 SDD_14
SDD_0 SDD_15

SDREQ_R
SDIOW#_R
SDIOR#_R
SIORDY_R
SDDACK#_R
IRQ15_R
SDA1_R
SDA0_R
SDCS#1_R
IDEACTS#

IDE2

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40

YJ220-Y-1

White color

PDD_8
PDD_9
PDD_10
PDD_11
PDD_12
PDD_13
PDD_14
PDD_15

ATADET0_R
PDCS#3_R

SDD_8
SDD_9
SDD_10

SDD_13

ATADET1_R
SDA2_R
SDCS#3_R

4

R127 470R

R97 470R

C431
X_473P

RESVD

C427
X_473P

RESVD

3

PDD[15..0]<17>

SDD[15..0]<17>

PDD[15..0]

SDD[15..0]

SDA0<17>
SDA2<17>

IRQ14<17>

SDIOW#<17>

SDDACK#<17>

IRQ15<17>

SDA1<17>

SDCS#1<17>
SDCS#3<17>

SDIOR#<17>

SIORDY<17>

SDREQ<17>

SDA0 SDA0_R
SDA2
PDD9
IRQ14

SDIOW# SDIOW#_R
SDDACK# SDDACK#_R
IRQ15
SDA1 SDA1_R

SDD12 SDD_12
SDD14 SDD_14
SDD15
SDIOR# SDIOR#_R

SDD7 SDD_7
SDD8 SDD_8
SDD9 SDD_9
SDD13 SDD_13

SDD4 SDD_4
SDD6 SDD_6
SDD10 SDD_10
SDD11 SDD_11

SIORDY SIORDY_R
SDD5 SDD_5
SDD0 SDD_0

SDREQ
SDD2 SDD_2
SDD1 SDD_1
SDD3

RN85

12

SDA2_R

34

PDD_9

56

IRQ14_R

78

8P4R-22
RN86

12
34

IRQ15_R

56
78

8P4R-22

SDCS#1

R256 22

SDCS#3

R257 22 R226 22

RN87

8P4R-22

RN88

8P4R-22

RN89

8P4R-22

RN91

8P4R-22

RN90

8P4R-22

SDCS#1_R
SDCS#3_R

12
34

SDD_15

56
78

12
34
56
78

12
34
56
78

12
34
56
78

SDREQ_R

12
34
56

SDD_3

78

2

PDREQ<17>

PDIOR#<17>

PIORDY<17>

PDDACK#<17>

PDIOW#<17>

PDCS#1<17>
PDCS#3<17>

PDA2<17>
PDA0<17>
PDA1<17>

ATADET1<17>
ATADET0<17>

PDREQ PDREQ_R
PDIOR# PDIOR#_R
PIORDY PIORDY_R
PDDACK#

PDD14
PDD15 PDD_15
PDD0
PDIOW#

PDCS#1

R227 22

PDCS#3

PDD12 PDD_12
PDD2 PDD_2
PDD13 PDD_13
PDD1

PDD4
PDD11
PDD3

PDD7
PDD6 PDD_6

PDD5 PDD_5

PDA2
PDA0
PDA1

ATADET1
ATADET0

RN79

8P4R-22

R300 X_22
R299 X_22

RN80

8P4R-22
RN81

8P4R-22

RN75

8P4R-22
RN82

8P4R-22
RN84

8P4R-22

1

12
34
56

PDDACK#_R

78

PDD_14

12
34

PDD_0

56

PDIOW#_R

78

PDCS#1_R
PDCS#3_R

12
34
56

PDD_1

78

PDD_10PDD10

12

PDD_4

34

PDD_11

56

PDD_3

78

PDD_7

12

PDD_8PDD8

34
56
78

78

PDA2_R

56

PDA0_R

34

PDA1_R

12

ATADET1_R
ATADET0_R

VCC

PIORDY_R

SIORDY_R

A A

IDEACTP#

IDEACTS#

IRQ14_R
IRQ15_R

R100 4.7K

R115 4.7K

R91 10K

R82 10K

R95 4.7K
R96 4.7K

5

PDREQ_R

SDREQ_R

PDD_7

SDD_7

ATADET0_R

ATADET1_R

R213 5.6K

R122 5.6K

R251 4.7K

R145 4.7K

R307 15K

R308 15K

4

Micro Star Restricted Secret

Title

Document Number

3

2

ATA 33/66/100 Connector

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

22 36

1

Rev

0A

of

5

4

3V_LAN

3

2

1

Fast Ethernet 1-Port PHY

C218

ACT_LED

RDC
RX­TDC

RX+
TX­TX+

SP_100

3V_LAN

17
18

9
13
10
14
11
15
12
16
19
20

C229
X_0.1u

close to LAN_USB1

PGND

LAN_USB1B

AMBER+
AMBER-

NC
NC

RDN

NC

NC
RDP
TDN
TDP

GREEN+
GREEN-

USB+LANtransform

C292
103P

3V_LAN

C291

104P

3V_LAN

FB12
60S

C220
10000p

2 1

RDC

TDC

C223
10000p

ACT_LED
SP_100

C237
1000P

1 2

close to LAN_USB1

10000p

PGND

TX-

R155 49.9RST

32
33

40
41

26
27
28
29

25
37
34
30

46

45

TX+
RX-

RX+

RX­RX+

TX­TX+

ACT_LED
SP_100

R176 6.49KST

C302

XI

X_106P/0805

XO

R154 49.9RST
R153 49.9RST

R152 49.9RST

R175 X_10K
R174 X_10K
R173 10K
R172 10K

MII_RST# <18>

Y1

25MHZ

C329
16P

C246 should not be
populate for VT8237CD

C315
16P

3V_LAN

D D

31

38

42

474824

13

7

MII_TXD0<18>
MII_TXD1<18>
MII_TXD2<18>
MII_TXD3<18>
MII_TXEN<18>

C C

MII_MDC<18>

MII_TXD0
MII_TXD1
MII_TXD2
MII_TXD3
MII_TXEN

TXCLK
RXD0

RXD1
RXD2
RXD3
RXDV
RXER

RXCLK
CRS

COL
MII_MDC
MDIO

17

TXD0

18

TXD1

19

TXD2

20

TXD3

16

TXEN

14

TXER

15

TXC

6

RXD0/PHYAD4

5

RXD1/PHYAD3

4

RXD2/PHYAD2

3

RXD3/PHYAD1

9

RXDV/BYPOSC

11

RXER/ISO

10

RXC

22

CRS/RPTR

21

COL/SYMB

2

MDC

1

MDIO

VDD

VDD

VDDC

VDDOSC

GNDRX

GNDOSC

GND

GNDC

GND

35

43

44

23

12

8

VDDTX

VDDRX

VDDPLL

LED0/TEST#

LED1/SPD100

LED2/DUPLEX

LED3/NWAYEN

INT#/PHYAD0

SD/FXEN

GNDPLL

GNDTXC

GNDTX

36

39

U14

RX-

RX+

TX-

TX+

REXT

PD#

RST#

XI

XO

VT6103

MII_RXD3<18>
MII_RXD2<18>
MII_RXD1<18>
MII_RXD0<18>

B B

A A

MII_RXDV<18>

MII_RXCLK<18>

MII_RXER<18>

MII_TXCLK<18>

MII_COL<18>
MII_CRS<18>

MII_MDIO<18>

5

MII_RXD3
MII_RXD2
MII_RXD1
MII_RXD0

MII_RXDV
MII_RXCLK

MII_RXER

MII_TXCLK
MII_COL

MII_CRS

MII_MDIO MDIO

1
3

RN76
8P4R-33

5
7

R237 33
R218 33

R219 33

R220 33
R222 33

R223 33

R217 33

RXD3

2
4

RXD2
RXD1

6

RXD0

8

FB19

RXDV
RXCLK

RXER

TXCLK
COL

CRS

MII_EEDI<18>

MII_EECK<18>

MII_EECS#<18>

4

3VDUAL

MII_EEDI
MII_EECK
MII_EECS#

80S

EEPROM

U17

3

DI

2

SK

1

CS

6 7

NC NC

93C46S

DO
VCC
GND

C343
104P

3

3V_LAN

C344
104P

C342
104P

C304
104P

C303
104P

C249
104P

EC21
104P

C301
104P

Signal Pin# Function Description

EEDI A12

MII_EEDO

4
8
5

MII_EEDO <18>

VCC3

Eliminate
External LAN
EEPROM

W/i external EEPROM:Stuff U17,R263 ;RemoveR271
W/o external EEPROM:stuff R271;Remove U17,R263

L: Disable. Use external EEPROM
H: Enable. Do not use external
EEPROM
Default setting: Disable

2

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

Fast Ethernet / 1-Port PHY

Micro Star Restricted Secret

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

23 36

1

Rev

0A

of

5

POWER CIRCUIT FOR USB PORT 0,1,2,3

FS2

2.6A_miniSMDM260

5V_STR

D D

C C

USBN3<16>

USBP3<16>

B B

USBN2<16>

USBP2<16>

USB_OC#1<16>

USBN1<16>

USBP1<16>

USBN0<16>

USBP0<16>

USBN1

USBP1

USBN0

USBP0

USBN3

USBP3

USBN2

USBP2

47K

C379
104P

R99
56K

1 2

1 2

1 2

1 2

SVCC0

+

EC11

C201

EL470/10V-3.5

X_105PR98

PGND

NEAR USB CONNECTOR

L6

X_90ohm_0805

4 3

L7

X_90ohm_0805

4 3

L8

X_90ohm_0805

4 3

L9

X_90ohm_0805

4 3

REAR USB PORT

USB_D1­USB_D1+

USB_D0­USB_D0+

USB_D3­USB_D3+

USB_D2­USB_D2+

4

SVCC0

USB1

PGND

5
6
7
8
1
2
3
4

DOWN

USBx2-D8-BK

CP22 12
CP23 1 2
CP21 1 2

UP

11

12
9

10

PGND

SVCC0

LAN_USB1A

5
6
7
8

UP

1
2
3
4

DOWN

USB+LANtransform

21
22
23
24
25
26
27
28

PGND

PGND

3

2

POWER CIRCUIT FOR USB PORT 4,5,6,7

SVCC1

C444

C443

X_105P

X_104P

FRONT USB CONNECTOR

USB_OC#4<16>

5V_STR1

F2

2.6A_miniSMDM260

R314
47K

C373
104P

R315
56K

FRONT USB PORT

FRONT PANEL USB CONNECTOR FOR USB PORT 4,5

USBN5

USBN5<16>
USBP5<16>

USBN4<16>
USBP4<16>

USBP5

USBN4

USBP4

FRONT PANEL USB CONNECTOR FOR USB PORT 6,7

USBN7

USBN7<16>
USBP7<16>

USBN6<16>
USBP6<16>

USBP7

USBN6

USBP6

43

12

L13
X_90ohm_0805

L12
X_90ohm_0805

4 3

1 2

L15

X_90ohm_0805

4 3

1 2

L14

X_90ohm_0805

4 3

1 2

USB_D5­USB_D5+

USB_D4-

USB_D4+

NEAR USB
CONNECTOR

USB_D7­USB_D7+

USB_D6­USB_D6+

NEAR USB
CONNECTOR

INTEL USB 2.0
(White)

SVCC1

JUSB2

1 2
3 4
5 6
7 8

N31-2051131-C09

N31-2051121-H06

INTEL USB 2.0
(White)

SVCC1

JUSB1

1 2
3 4
5 6
7 8

N31-2051131-C09

N31-2051121-H06

+

EC35
EL470/10V-3.5

10

10

SVCC1
USB_D5­USB_D5+

OC#

SVCC1
USB_D7­USB_D7+

OC#

1

8P4R-15K

USBP4
USBN4
USBN5
USBP5

USBN0
USBP0
USBN1
USBP1

USBP2
USBN2
USBP3
USBN3

USBP6
USBN6
USBP7
USBN7

LEGEND Front USB Header

SVCC1

SVCC1
USB_D5­USB_D5+

OC#

LEGEND Front USB Header

SVCC1

SVCC1
USB_D7­USB_D7+

OC# SVCC1

RN102

1 2
3 4
5 6
7 8

8P4R-15K

RN46

1 2
3 4
5 6
7 8

8P4R-15K

RN53

1 2
3 4
5 6
7 8

8P4R-15K

RN101

1 2
3 4
5 6
7 8

JUSB4

1 2
3

6

5

8

9 10

X_H2X5(4)(7)_black

JUSB3

1 2
3

6

5

8

9 10

X_H2X5(4)(7)_black

USB_D4+
USB_D4­SVCC1

USB_D6+
USB_D6-

A A

5

4

OC# USB_OC#4

R317 0

R316 X_0

For Intel SPEC=>stuff R317(default)
For LEGEND SPEC=>stuff R316

3

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

N o. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

2

http://www.msi.com.tw

Rear USB Port

MS-7102

Last Revision Date:
Sheet

Friday, July 23, 2004

24 36

1

Rev

0A

of

5

4

3

2

1

Super I/O

XA5
XA4
XA3
XA2
XA1
XA0

XD7
XD6
XD5
XD4
XD3
XD2
XD1
XD0

VCC3

LPC_REQ#<18>

RTSA#
SOUTB
SOUTA
DTRA#

103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128

U11

XA5/GP35
XA4/GP34
XA3/GP33
XA2/GP32
XA1/GP31
XA0GP30
VCC
ROMCS#/GP52
MEMR#/GP51
MEMW#/GP50
XD7/GP27
XD6/GP26
XD5/GP25
XD4/GP24
XD3/GP23
XD2/GP22
XD1/GP21
XD0/GP20
DRVDEN0
INDEX#
MO#
DS#
DIR#
STEP#
WD#
WE#

TRACK0#
WP#
RDDATA#
HEAD#
DSKCHG#

SIO48M<7>

PCICLK6<7>

C252
104P

R121 X_4.7K
R288 4.7K

R110 X_4.7K

VCC3

R140

X_4.7K

SERIRQ<17>

LPC_FRAME#<18>

4

R117 4.7K
R105 X_4.7K
R108 4.7K

XA[17..0]

ROMCS#<26>

MEMW#<26>

C276
X_33P

MEMR#<26>

R109 4.7K

ROMCS#
MEMR#
MEMW#

DRVDEN0

INDEX#
MOA#
DSA#
DIR#
STEP#
WRDATA#
WE#

D D

XA[17..0]<26>

C C

VCC

C413
104P

FDD1

XD[7..0]

1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34

YJ217-C-1

C275

X_33P

XD[7..0]<26>

B B

FLOPPY DISK HEADER

VCC3

A A

VCC3

RN64

1

2

3

4

5

6

7

8

X_8P4R-4.7K
R135 X_4.7K

5

LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0

LPC_FRAME#

VCC VCC

IRTX/SOUTB

Power-on strap, enable 48MHz

RTSA#

IRTX/SOUTB

XA6

XA10

XA11

XA12

XA13

XA8

XA9

100

GP41/XA9

GP40/XA8

GP37/XA7

WP#

RDATA#

HEAD#

C254
X_47p

GP45/XA13

GP44/XA12

GP43/XA11

GP42/XA10

DSKCHG#

IOCLK#

VSS

LPCCLK

XA14

C239

XA7

101

102

GP36/XA6

TRAK0#

12345678910111213141516171819202122232425262728293031323334353637

LPC_AD3<18>
LPC_AD2<18>
LPC_AD1<18>
LPC_AD0<18>

PCIRST1#<12,30>

L: CFAD=2E H: CFAD=4E
L: 24MHZ H: 48MHZ

SOUTA

L: ISA ROM H: NO ISA ROM

DTRA#

L: PNP Default H: PNP No Default

XA18 <26>

XA18

XA15

XA16

XA17

GP55/XA18

GP54/XA17

GP53/XA16

GP47/XA15

GP46/XA14

GP56/MDI/VID0

GP57/MDO/VID1

GP10/GPSA1/VID2

SIO

W83687THF

LDRQ#

SERIRQ

3VCC

LAD3

LAD2

LAD1

LAD0

LFRAME#

X_10p

BEEP

SYSFANIN

SMI#/OVT#

GP17/GPY2

GP16/GPX2

GP15/GPY1

GP14/GPX1

GP13/GPSB2/VID5

GP12/GPSA2/VID4

GP11/PLED/GPSB1/VID3

LRESET#

SLCTPEBUSY

ACK#

PD7

PD6

PD5

PD4

PD3

AVCC

AUXFANIN

CPUFANIN

SYSFANOUT

PD2

PD1

PD0

SLIN#

3

NC

CPUD-

AUXFANOUT

CPUFANOUT

INIT#

ERR#

AFD#

VCC

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

BEEP <26>

6566676869707172737475767778798081828384858687888990919293949596979899

VTIN

VREF

CPUIN

SYSIN

CPUVCORE

CASEOPEN#

GP60/RSMRST#

GP61/PWROK

XA19/GP62
GP63/PSIN

PSOUT#/GP64/PSOUT#

GP65/RIB#/RSTOUT1

GP66/DCDB#/RSTOUT2#

IRTX/SOUTB

RTSB#/PWRCTL#

CTSB#/GP67

SOUTA/PENROM#

DTRA#/PNPCSV

STB#

CTSA#

DSRA#

HEFRAS/RTSA#

38

L10

PD[7..0]

301S

R132 22

VIN1
VIN2
VIN3

VBAT

PME#

VSB

IRRX/SINB

DTRB#
DSRB#

RIA#

DCDA#

SINA

21

RACK# <27>
RBUSY <27>
RPE <27>
RSLCT <27>

SYSFAN_IN <20>
CPUFAN_IN <20>
VAVCC <26>

SYSFAN_OUT <20>
CPUFAN_OUT <20>

V_GND
VTIN2 <26>

THERMDA_CPU <5,26>
VREF <26>

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50

SOUTB

49
48

DTRB#

47

RTSB#

46

DSRB#

45

CTSB#

44
43
42
41
40
39

RTSA# <27>
DSRA# <27>
CTSA# <27>

RSTB# <27>

RAFD# <27>
RERR# <27>
RINIT# <27>
RSLIN# <27>
PD[7..0] <27>

THRM# <17>

RIB#
DCDB#

SINB

VCC

C232
104P

VCCP <26>
+12VIN <26>

-12VIN <26>
+3.3VIN <26>

RIB# <27>
DCDB# <27>

SOUTB <27>
SINB <27>
DTRB# <27>
RTSB# <27>
DSRB# <27>
CTSB# <27>

RIA# <27>
DCDA# <27>
SOUTA <27>
SINA <27>
DTRA# <27>

2

V_GND

5VSB

R104 1M

C214
105P

R128

X_0

R124

0

C227 X_3300p

3300p

VBAT

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

Legend Front IR Header

SINB
SOUTB

VTIN_GND <5,26>

THERMDA_CPUVTIN_GND

PCI_PME# <17,19>

Distribute near the VCC
power pin of the LPC

VCC

C274
104P

Micro Star Restricted Secret

Winbond W697HF

MS-7102

C213
475P

Last Revision Date:
Sheet

1

JIR1

1

1

3

3

4

4

5

5

IR

VBAT

Friday, July 23, 2004

25 36

of

Rev

0A

5

4

3

2

1

Hardware Monitor

SYSTEM ROM

SYSTEM Thermal

D D

VREF

R118

10KST

VTIN_GND<5,25>

SMD

RT2

YT103SC-1N

VTIN_GND

VTIN2 <25>

R125

X_0

XA[17..0]<25> XD[7..0] <25>

CPU Thermal

R119

VREF

30KST

R107 X_0

VREF

VTIN_GND

+12VIN <25>

-12VIN <25>

VREF <25>

VTIN_GND <5,25>

VCC

VCORE

C C

VCC3

+12V

-12V

R111 10KST

R103 10KST
R106 28KST
R102 232KST

VCCP <25>
+3.3VIN <25>

R101
56KST

R112 10KST

L11
X_08S/0805

1 2

THERMDA_CPU

RESVD

21

CP16

THERMDA_CPU <5,25>

VAVCC

VAVCC <25>

C412
104P

XA[17..0]

XA0
XA1
XA2
XA3
XA4
XA5
XA6
XA7
XA8
XA9
XA10
XA11
XA12
XA13
XA14
XA15
XA16
XA17

XA18

XA18<25> MEMR# <25>

R196 0

R195

VCC

X_4.7K

R343

GPIO14<16>

1K

U12

12

A0

11

A1

10

A2

9

A3

8

A4

7

A5

6

A6

5

A7

27

A8

26

A9

23

A10

25

A11

4

A12

28

A13

29

A14

3

A15

2

A16

30

A17

1 22

A18 CE#

BIOS-SOCKET

C446
102p

R180

1K

BIOS_WP1

1
2

D1x2

VCC

OE#

PGM#

GND

D0
D1
D2
D3
D4
D5
D6
D7

B

C307

X_5p

13
14
15
17
18
19
20
21

32

24
31
16

XD0
XD1
XD2
XD3
XD4
XD5
XD6
XD7

R187 1K

C

Q29
2N3904S

E

MEMW#

C331
104P

ROMCS#
MEMR#

MEMW# <25>

XD[7..0]

VCC

When Socket was removed,
populate CB11

CB11
X_475P/0805

ROMCS# <25>

VCC

B B

XD3
XD2
XD1
XD0
XD7
XD6
XD5
XD4

ROMCS#
MEMR#

VCC

A A

BEEP<25>

5

4

3

R313
10K

C

B

Q33
2N3904S

E

ALARM <28>

2

Title

Document Number

MICRO-STAR INT'L

N o. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

MEMW#

Micro Star Restricted Secret

Hardware Monitor

MS-7102

RN69

8P4R-4.7K

7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2

RN70

8P4R-4.7K

7 8
5 6
3 4
1 2

RN68

8P4R-4.7K

Last Revision Date:
Sheet

1

VCC

Friday, July 23, 2004

26 36

of

Rev

0A

5

LPT / COM PORTS

1
3
5
7
1
3
5
7

RN23
8P4R-33

RN19
8P4R-33

2
4
6
8
2
4
6
8

RERR#

RACK#
RBUSY
RPE
RSLCT

RINIT#
RSLIN#
RSTB#
RAFD#

PRND0
PRND1
PRND2
PRND3
PRND4
PRND5
PRND6
PRND7PD7

RERR#<25>

RACK#<25>

D D

C C

B B

RBUSY<25>

RSLIN#<25>

RAFD#<25>

PD[7..0]<25>

For EMI

RSLCT
RPE
RBUSY
RACK#

RERR#
RAFD#
RSTB#
RSLIN#

PRND0
PRND1
PRND2
PRND3

PRND4
PRND5
PRND6
PRND7

RINIT#

RPE<25>

RSLCT<25>

RINIT#<25>
RSTB#<25>

PD0

21
43
65
87

21
43
65
87

21
43
65
87

21
43
65
87

PD1
PD2
PD3
PD4
PD5
PD6

CN5
8P4C-180P

CN10
8P4C-180P

CN8
8P4C-180P

CN7
8P4C-180P

C120
180P

PD[7..0]

KBGND

Keyboard/Mouse Ports

MSDAT#<16>
MSCLK#<16>

KBDAT#<16>
KBCLK#<16>

MSDAT#

A A

KBDAT#
MSCLK#
KBCLK#

5

MSDAT#
MSCLK#

KBDAT#
KBCLK#

RN1

1 2
3 4
5 6
7 8

8P4R-2.2K

KBVCC

R65 4.7K

PRND7
PRND6
PRND5
PRND4

PRND3
PRND2
PRND1
PRND0

KBGND

RSTB#
PRND0
PRND1 RINIT#
PRND2
PRND3
PRND4
PRND5
PRND6
PRND7
RACK#
RBUSY
RPE
RSLCT

1
2
3
4
5
6
7
8

9
10
11
12
13

EMI reques Add 120ohm bead in
L2000~L2003@930715

L1 121S21

R6
330

21

21

L3 121S

L2 121S21
L4 121S

KBGND

DIS,EMI/ESD protection for
I/O,INPAQ/VPORT0603181KV12,180p,12V,10%

51

14
15
16
17
18
19
20
21
22
23
24
25
48

52

XKBCLK1
XMSCLK1
XKBDAT1
XMSDAT1

4

1
2
3
4
6
7
8
9510
1
2
3
4
6
7
8
9510

RAFD#
RERR#

RSLIN#

LPT1
N51-25F0041-F02

KBGND

XMSDAT1

XMSCLK1

XKBDAT1
XKBCLK1

C20 180P
C16 180P
C12 180P
C9 180P

4

D4

AC

VCC

1N4148S

RN16
10P8R-4.7K

RN27
10P8R-4.7K

C48

X_104P

-12V

STACKED PS2 CONNECTOR

JKBMS1

7

8
11
12

MS

1

2

5

6

KB

YMD12P-1

KBGND

RTSA#<25>
DTRA#<25>
SOUTA<25>

10

9
4

3

VCC

NRIA#
NCTSA#
NDSRA#
NSINA
NDCDA#

RTSA#
DTRA#
SOUTA

C416

104P

NRTSA
NDSRA#
NCTSA#
NRIA#

SERIAL PORT 2

NDCDB#
NSOUTB

NRTSB
NRIB#

KBGND KBGND

1 2

CP2

KBGND

3

20

16
15
13
11

D3
1N4148S

CN1

21
43
65
87

X_8P4C/180P

KBGND

COM2 HEADER

JCOM1

1 2
3 4
5 6
7 8
9

D2x5-1:5-WH

Black

KBVCC

C4
X_39P

5V_STR

3

2

RIA# <25>
CTSA# <25>
DSRA# <25>
SINA <25>
DCDA# <25>

L5 X_80S

CP112

U5

VCC

2

RIN1

3

RIN2

4

RIN3

7

RIN4

9

RIN5
DIN1

DIN2
DIN3
GND

75232-1

-12VC +12VC

ROUT1
ROUT2
ROUT3
ROUT4
ROUT5

DOUT1
DOUT2
DOUT3

+12V

NDCDA#
NSOUTA
NSINA
NDTRA

1

V+

19
18
17
14
12

5
6
8
10

V-

X_8P4C/180P

+12VC

RIA#
CTSA#
DSRA#
SINA
DCDA#

NRTSA
NDTRA
NSOUTA

-12VC

D2
1N4148S

C145

104P

CN2

21
43
65
87 CP20 1 2

KBGND

VCC

NRIB#
NCTSB# CTSB#
NDSRB#
NSINB
NDCDB#

RTSB#
DTRB#
SOUTB

D12
1N4148S

C425

104P

NRTSB
NDSRB#
NCTSB# NSINB
NRIB#

EX_8P4C-180P

KBVCC

+

C22

EC6

X_105P

X_EL470/10V-3.5

C3
X_104P

NSINB
NDTRB
NDSRB#
NCTSB#

1.1A_microSMD110
FS1

POLY SWITCH

RTSB#<25>
DTRB#<25>
SOUTB<25>

KBGND

2

CN21

21
43
65
87

20

2
3
4
7
9

16
15
13
11

-12VC

U20

VCC
RIN1
RIN2
RIN3
RIN4
RIN5

DIN1
DIN2
DIN3
GND

75232-1

PGND2

NDCDA#
NSINA
NSOUTA
NDTRA

C93
X_104P

1 2

CP18

CP19 1 2

1

V+

19

ROUT1

18

ROUT2

17

ROUT3

14

ROUT4

12

ROUT5

5

DOUT1

6

DOUT2

8

DOUT3

10

V-

+12V-12V

C439

NDCDB#
NSOUTB

NDTRB

EX_8P4C-180P

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

N o. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

1

6

2

7

3

8

4

9

5

COM1
COM-D9-GN

11 10

KBGND

KBGND

+12VC

RIB#
DSRB#

SINB
DCDB#

NRTSB
NDTRB
NSOUTB

-12VC

D15
1N4148S

104P

CN20

21
43
65
87

PGND2

LPT / COM Port

MS-7102

1

NDSRA#
NRTSA
NCTSA#
NRIA#

RIB# <25>
CTSB# <25>
DSRB# <25>
SINB <25>
DCDB# <25>

+12VC

2 1

Last Revision Date:

Friday, July 23, 2004

Sheet

1

Bottom side

L16

X_80S/0805

CP2912

27 36

of

Rev

0A

5

4

3

2

1

FRONT PANEL

LEGEND FRONT PANEL-M

VCC

R350 330

FRISW

3
2
1

R348

330

HDD+
SUS_LED
PWR_LED SPK1
DPLED3
PWRSW+
PWRSW-

R332

330

1
2
3
4
5
6

JLEG1

HDD+
GNDL
SLED2
PLED1
PWSW+
PWSW-

NC7

D2x7-1:7-BK

HDD-

SPEAKER

BUZ+

BUZ-

VCCSPK

RESET

GNDR

HDDLED

8
9
10
11
12

FP_RST#

13
14

R323 4.7K

C438

0.1u

VCC

FP_RST# <7,30>

5VSB

D D

5VSB

LEGEND POWER SWITCH

Independent Power Switch Header

PWRSW+

5VSB

C C

C451
X_0.1u

D1x3-WH-SN(N32-1030221)

ALARM<26>

R303 2.2K

SPKR<17>

PLED2<30>

PLED1<30>

Low Active

B

Q35

2N3904S

C450
X_1u_0805

5VSB5VSB

R345
1K

CE

R340
10K

PWBTIN# <17>

C445
1u_0805

3VDUAL

R333

C449

X_10K

PWRSW+

PWRSW+ PWBTIN#

R342 X_0

X_0.1u

B B

R347

22

R349

8.2K

Q39

2N3904S

C452
X_1u-0805

R346
1K

4.5V

PWBTIN

CE

B

R344
X_10K

R312 220
R311 220

Q32
2N3904S

Dual Color LED Block

PLED2

R341 4.7K Q38

PLED1

R336 4.7K

HDDLED

2N3904S

Q34
2N3904S

D14
1N4148S

SUS_LED

PWR_LED

A C

3

C436

X_180P

D13
BAT54A

1 2

ESD Protect

C437

0.1u

VCC

SPK1

BUZZER-SAT1205-85dB-D

SATAACT# <18>
IDEACTP# <22>

IDEACTS# <22>

BZ1

JWOL

3
2
1

D1x3-WH-HSNO

Wake on LAN

5VSB

R338 4.7K

C447

0.1u

R339

2.2K

RI#

C

Q37

B

2N3904S

E

POWER OK Circuits

RI# <17>

VCC2_5

VCC2_5

R23

CE

VCC3

C255

104P

VCC

5VSB
+12V

VCC

R139

4.7K

PW_OK

PW_OK <30>

C246
104P

4

ALL_PWRGD<18,30>

-LDTRST<11>

R9 X_10K

R25 10K

3

3.3V

3.3V
GND

GND
GND

5V_SB

12V

VCC3

1
2
3
4

5V

5
6

5V

7
8
9
10

JWR1

11

3.3V

-12V

A A

PS_OUT#<5,30>

VCC3 VCC

C81

104P

PS_OUT#

-5V

VCC

C154

104P

5

12
13
14
15
16
17
18
19
20

-12V
GND
PS_ON
GND
GND
GND

-5V
5V
5V

ATX-PCON

PW_OK

1K

CE

Q4
X_2N3904S

B

Ic=200mA
Vebo=6V
Vceo=40V

CE

Q3
2N3904S

B

Ic=200mA
Vebo=6V
Vceo=40V

Q2
2N3904S

B

Ic=200mA
Vebo=6V

Vceo=40V

R26

0

R24
1K

C24
X_102P

-CPURST <5>

2

PSON#

PS_OUT#

PW_OK

EN_DDR

EN_VDDA_25

EN_VCORE

PG_VCORE

EN_VDD_12_A

CPU_GD

ALL_PWRGD

Power On Sequence.

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

Power OK Circuits

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

28 36

1

Rev

0A

of

5

4

3

2

1

K8 Voltage Regular Module

CHOK3 1.1uH/25A

+12VP

D D

VCC

C8

22PC36

COREFB_L<5>

PG_VCORE

C35 562P

R32
1KST

VDIFF
IDROOP

COREFB_H<5>

X_104P

VID4
VID3
VID2
VID1
VID0

COMP
FB_ISL

FS_ISL

U3
ISL6569CB

I32-6569B02-I11

24

EN

3

VID4

4

VID3

5

VID2

6

VID1

7

VID0

22

PGOOD

23

FS/DIS

9

COMP

10

FB

12

VDIFF

11

IDROOP

R5

4.7K

VCC

R33
270K

VCORE_EN#

C13

R30 10KST

VID[4..0]<5>

R31
0

R8
10K

VCORE
GND

R18 154KST

COMP1

R43 51RST
R42 51RST

VCORE_EN#<30>

PG_VCORE<30>

C C

X_104P

VCC

Droop Compensation

R7

0/0805

16

VCC

18

GND

15

GND

1

GND

20

PWM1

21

ISEN1

19

PWM2

17

ISEN2

8

OFS

2

OVP

13

VSEN

14

RGND

OFS : Voltage up offset
, 1K Ohm =10mV

C123
X_39p/50V

ISEN1

ISEN2

OFS

+

CT5

EL1500/16V

VCC

D1

X_1N5817

CB1
105P/0805

R1 3KST

R2 3KST

R29
0

Offset Adjustment

CT9
EL1500/16V

+12VP

R12

5.1/0805

CB2
105P/0805-25V

+12VP

R16

5.1/0805

CB3
105P/0805-25V

VDD_12_VRM

CT7
EL1500/16V

VDD_P0

PWM1

VDD_P1

PWM2

C137

CT2
EL1500/16V

475P/1206/16V

U2A
HIP6602B

I33-6602B03-I11

14

VCC

U_G1

BOOT1

PHASE1

3

GND

1

PWM1

L_G1

U2B

5 9

PVCC U_G2

BOOT2

PHASE2

6

PGND

2

PWM2

L_G2

HIP6602B

C100
475P/1206/16V

PBT1

U_G1

12
11

R3
10

13

L_G1 L_G1A

4

PBT2

10

R4
10

8

L_G2

7

BOOT1

C1
104P

BOOT2

C2
104P

R67

2.2/0805

R62
0/0805

R60

2.2/0805

R13
0/0805

CB6
105P/0805

DS

U_G1A

G

Q17

PHASE1

U_G2AU_G2

PHASE2

L_G2A L_G2A

09N03/DPACK

DS

DS

G

DS

G

Q15
06N03G

CB4
105P/0805

Q13
09N03/DPACK

Q12
06N03

R66

R57

3.3

C131
102P

3.3

C87
102P

L_G1A

VCORE

CHOK2

DS

0.8u-20%

Q16
06N03G

CHOK1

DS

0.8u-20%

Q6
06N03

G

0.8V~1.55V/42A

VCORE

R619 ORIGNAL 154KST R11-1543T13-Y01

POWER FREQENCY ADIUSTING

B B

VID4 VID3 VID2 VID1 VID0 Vout
1 1 1 1 0 0.800
1 1 1 0 1 0.825
1 1 1 0 0 0.850
1 1 0 1 1 0.875
1 1 0 1 0 0.900
1 1 0 0 1 0.925
1 1 0 0 0 0.950

R11-0304T13-Y01300KRST

VID4 VID3 VID2 VID1 VID0 Vout
0 1 1 1 0 1.200
0 1 1 0 1 1.225

CT3

1500U/6.3V

CT11
1500U/6.3V

0 1 1 0 0 1.250
0 1 0 1 1 1.275
0 1 0 1 0 1300
0 1 0 0 1 1.325
0 1 0 0 0 1.350

CT4
1500U/6.3V

CT12
1500U/6.3V

CT6
1500U/6.3V

CT13
1500U/6.3V

CT8
1500U/6.3V

CT10
1500U/6.3V

0 0 1 1 1 1.3751 0 1 1 1 0.975
1 0 1 1 0 1.000
1 0 1 0 1 1.025
1 0 1 0 0 1.050
1 0 0 1 1 1.075
1 0 0 1 0 1.100

A A

1 0 0 0 1 1.125
1 0 0 0 0 1.150
0 1 1 1 1 1.175

0 0 1 1 0 1.400

0 0 1 0 1 1.425

0 0 1 0 0 1.450

0 0 0 1 1 1.475

0 0 0 1 0 1.500

0 0 0 0 1 1.525

0 0 0 0 0 1.550

1 1 1 1 1 Shutdown

+12VP

104P

C165

60MIL

JPW1

3

12V

4

12V

ATX12V-NPEG

GND

GND

1

2

VCC

R35

R53 X_2KRST

X_4.64KST

X_2.8KRST

X_1.82KST

R54

R45

Near to Vcore Input-Chock ( CHOK1 )

5

4

3

3
2

5
6

RT1

X_YT472S-1N

2

VCC

U6A
X_LM393_#A

I72-LM39303-T07

84

+

1

-

U6B
X_LM393_#A

I72-LM39303-T07

84

+

7

-

Q9

X_2N7002S

Q8

X_2N7002S

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

R19

X_270KST

R17

X_300KST

VCC

C53
X_104P

FS_ISL

Micro Star Restricted Secret

K8 CORE POWER

MS-7102

Last Revision Date:

Thursday, July 22, 2004

Sheet

29 36

1

of

Rev

0A

8

Pin 47 Difinition

MS6 VERSION: RAC

3VSB MODE SELECT

3VSB MODE

DUAL MOSFET(Q1) PULL LOW

SINGLE MOSFET

MS6 VERSION: RBF

VAGP SEQUENCE MODE SELECT

VAGP SEQUENCE MODE

VAGP ON BEFORE PWR_OK L TO H

D D

VAGP ON AFTER PWR_OK L TO H

EXTERNAL PWM OR LINEAR REGULATOR

C C

PIN 47

PULL HIGH

PIN 47
PULL LOW
PULL HIGH

VDIMM LINEAR OR PWM SELECT

VDIMM MODE

LINEAR REGULATOR

FRONT PANEL RESET BUTTON
PCIRST# INPUT

PCIRST# BUFFER OUTPUT

EXTRAM(PIN 48)

PCI SOLT PCIRST# BUFFER OUTPUT

VDDA_25

VDDA_25 To CPU
Copper trace
width > 50mils
.

B

R178 4.7K

SUSB#<17>

B B

A A

To CPU Copper trace width > 250mils , Fill
island behind DIMM > 400mils .

DDR_VTT 1. 25V

V1.0

3VDUAL

U1

7
6
5

W83310DS
C5
C0.1U16Y

ENABLE
VCNTL
BOOT_SEL

VREF1

VOUT

VINVREF2

GND

GND

VDD_25_SUS

18
2
3
4
9

7

PLED1<28>

PLED2<28>

PULL LOW
PULL HIGH

PCIRST1#

C293
X_22P

FP_RST#<7,28>

PCIRST#<14,16>
HDDRST#<22>
PCIRST1#<12,25>

PG_VCORE<29>

VCORE_EN#<29>

1.25VREF<31>
PCIRST2#<19>

VDDA_25

CLOSE TO CHIP

5VSB

R165

4.7K

PS_IN#

PS_OUT#<5,28>

CE

Q26
2N3904S

Ic=200mA
Vebo=6V
Vceo=40V

DDR TERMINATION

R11

100RST
R10
100RST

VTT_DDR_SUS

12

12

+

EC1

+

EC16

1000U/6.3V

1000U/6.3V

Q28

2N3904S

5VSB

Q27

2N3904S

VCC3

R324

4.7K

VCC3

EC19

CD100U16EL11

5VSB

C14
C0.1U16Y

CD1000U6.3EL11.5

6

5VSB

5VSB

R163
158_1%

R166

X_1K

R170

3VDLDEC#

4.7K

5VSB

R151
158_1%

R161

4.7K

VCC3

VCC

R160

R158

330

330

R159
22

VCC

12

+

C294 475P/0805

C411 104P

R169
1K

C79
104P

5VSB

DDR AND DDR II VOLT SELECT

DDRTYPE

DDR1
DDR2

VDD_25_SUS

+

12

EC9

RAC:R48 Remove, R49=0 Ohm(R11-0000013-Y01)
RBF:R48=100 Ohm, R49=100 Ohm(R11-0101T13-Y01)

R167

10K

R162

1K

EXTRAM

R164

X_10K

1
2
3
4
5
6
7
8

9
10
11
12

C295 104P

5VSB

R179 X_4.7K
R181 4.7K

PULL LOW
PULL HIGH

+

12

EC8

X_CD1000U6.3EL11.5

C300
X_102P

FP_RST#
PCIRST#
HDD_RST#
DEV_RST#
VDD_GD
VDD_EN

1.25VREF
VCC5
SLOT_RST#
VCC3

2.5VDDA
AGND0

C305 474P-X7R

VDIMM

2.5V

1.8V

3VDIMM

DS

R48 100RST

48

I2C_CLK

RSMRST#

I2C_DATA

CPU_PWGD

CHIP_PWGD

PLED1/EXTRAM

PLED0/3VDLDEC#

PSIN#

PSOUT#

MEMBTSS5VSB

DDRTYPE

VDIMM_LSEN

1314151617181920212223

C306
104P

Q10

N-P45N02LD_TO252

G

5

VCC2_5

VCC3

R177

R38

4.7K

4.7K

C298

5VSB

X_102P

C308

C0.1U16Y

U13

3738394041424344454647

S3#

S5#

GND

5VSB

PWR_OK

CHRPMP

AGND1

5VUSB_DRV

5V_DRV
VAGP_DRV
VAGP_SEN

WD_DET

1.2VLDT_DRV

1.2VLDT_SEN
TMP_FAULT#

VDIMM_LDRV

VDIMM_HSEN

VDIMM_HDRV

3VSB_SEN

3VSB_DRV

MS-6(RBF)(B07-00MS624-W03)

24

C318

36

C1

35

C2

C0.1U16X

34
33
32
31
30
29
28
27
26
25

WATCHING DOG TIMER SELECT

WD_DET

PULL HIGH

3VDUAL

Q5

N-APM2054N_SOT89

R49

100RST

5V_DRV

1234

G

DS

Q11

N-AP40N03H/J_TO252

VCC3

3VDIMM

4

LINEAR MODE

THESE OUTPUT AND INPUT PIN MUST
BE PULL HIGH

CPU PWR_GD OUTPUT
CHIP PWR_GD OUTPUT
I2C BUS
I2C BUS
CONNECT TO SOUTH BRIDGE RSMRST# SIGNAL
SOUTH BRIDGE POWER CONTROL(SLP_S4# OR SUSB#) SIGNAL
SOUTH BRIDGE POWER CONTROL(SLP_S3# OR SUSC#) SIGNAL
ATX POWER OK INPUT

VDIMM_HSEN
VREF(PIN 21)

C309

3VDUAL

X_102P

12

+

5VSB_DRV
5V_DRV

R186
10K

12

+

EC4

CPU_GD <5>
ALL_PWRGD <18,28>
SMBCLK1 <7,8,17,18>
SMBDATA1 <7,8,17,18>
RSMRST# <18>
SUSC# <17>
SUSB# <17>
PW_OK <28>

CHARGE PUMP
VOLTAGE

9VSB

OUTPUT

C323

105P/0805

THRMTRIP# <5>

TIMER

OFFPULL LOW
ON

THE VDIMM_HSEN IN
LINEAR MODE

DDRTYPE
DDR 2.0V
DDR II 1.7V

CD1000U6.3EL11.5

3VDUAL

Q18

8

1

7

2
3

VCC

VCC

C322 X_102P

C321 X_102P

VCC2_5

V1.0A

G

+

EC13
1000U/6.3V

3VDUAL

12

+

EC2

EC28

1000U/6.3V

X_CD470U10EL11.5

6

4 5

NN-P07D03LV_SO8

Q36

8

1

7

2
3

6

4 5

NN-P07D03LV_SO8

D

Q20
P3055LD

S

Routed as pour to
CPU width >
250mils .

DUAL MODE

THIS MODE SELECT BY
PIN 47 PULL LOW

3VSB REGULATE BY 5VSB AND VCC3

VCC3

1

5V_DRV

2
3

3VSB_DRV

4 5

NN-P07D03LV_SO8

R309

10K

5VSB

5VSB

5V_STR1

G

VDD_12_A

Q1

3

C432
105P

+

5V_STR

EC5
X_1000U/6.3V

VCC3

D

Q30
X_P3055LD

VDDQ

S

VDDQ

+

EC25
1000U/6.3V

VDD_12_A

5VSB
8
7
6

+

EC22
EL470/10V-3.5

RSMRST# <18>

5V_DUAL

VCC2_5

C209
X_104P

2

1

M icro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan

8

7

6

5

4

3

http://www.msi.com.tw

2

ACPI POWER CONTOLLER (MS-6)

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

1

30 36

of

Rev

0A

System Voltage Regulator

9VSB

R114

1KST

R123

499RST

U9A

84

LM358_#B

3

+

2

-

R113
1KST

9VSB

U9B

84

LM358_#B

5

+

6

-

R131
100RST

133RST

R120
1K

1.25VREF<30>

1.25VREF

103P

C222

K8M800 used only

R116

1.25VREF

1K

C224

X_103P

VCC3

D

Q24
P3055LS

G

1

S

+

EC17
EL470/10V-3.5

VDD=VCC1_5

VCC2_5

D

Q21
P3055LS

7

G

S

VDD

+

C240

105P/0805

EC14
EL470/10V-3.5

EC29

+

X_1000U/6.3V

Dual Layout Footprint

VCC2_5

VCC2_5=1.25X(R113+R114)/R114

K8T800 used only

Bottom side

K8M800 used only

VCC2_5

3VDUAL

A C

7

8

5

6

3

4

1

2

VDD=VCC1_5

VDDVDDQ

7

8
6
4
2

RN71

5

8P4R-0

3
1

D6

1N4001S

VDD=VCC2_5

VDD

RN56
X_8P4R-0

R353
X_0/0805/B

R168
X_0
R171
X_0

VT8235 Suspend 2.5V power

1

2

A C

D7
X_1N4148S

D8
SC431

4
6
8

RN72
8P4R-220

VSUSNB

3 1

R210
100RST

2

R211
499RST

104P

VSUS2_5

+

EC20
470u/10VC296

3
5
7

K8M800=1.5V
=>1.24x(1+100/499)=1.5v

For K8T800(BOM)

1)RN72--->RN109(0R)

2)Remove D8,R210,R211

3)Stuff RN56

4)Remove Q21,C224,R123,R131,C240,EC14

VSUSNB

K8T800=2.5V
K8M800=1.5V

+

EC23
X_470u/10V

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

System Voltage Regulators

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

31 36

of

Rev

0A

5

4

3

2

1

BULK / Decopuling

D D

CPU

Place on inside of CPU Cavity ( 5 *

0.22uF/0603 X7R high-freq decoupling
Cap. )

VCORE

C67
104P

C C

B B

VCORE

C480

X_104P/BOT

VCORE

X_104P/BOT

VDD_25_SUS

C161
104P

VDDQ

X_104P

VDDQ

C316

105P/0805

VCC2_5

104P

VCC2_5

C169

C281

C363

C59
104P

C272

104P

C231

105P/0805

C297
X_104P

C474
X_104P/BOT

VDD_12_A

C176
X_104P/BOT

C153
X_104P

C477

X_104P/BOT

VCC3

C273

104P

K8M800

C330

C236
105P

104P

C215
X_104P

DDR

C364
X_104P

For EMI

VCC3

C405

C325

X_104P

X_104P

VCC3

C434
X_104P

VCC

SYSTEM

5VSB VCC

C178

104P

VCC3

C88

C372

104P

104P

C367
104P

CB7
X_104P

C11

104P

C326
104P

C371
X_104P

CB9
X_104P

C217

VCC3

C401
104P

VCC

C410
X_104P

C366
X_104P

C369
104P

C375

104P

C136
104P

C143
X_104P

C264
X_104P

C376
X_104P

VCC

+

VCC3

C426
X_104P
C74
X_104P
C84
X_104P

EC3

EL470/10V-3.5

VTT_DDR_SUSVDD_25_SUS

C21

X_104P

EC32
X_1000U/6.3V

+

VDD_25_SUS

VCC3

+

EC15
X_EL100/16V-2.5

VSUS2_5

EC18

+

1000U/6.3V

12

+

EC31

ELS10/16-B

+

EC24

X_1000U/6.3V

C368

C324

105P/0805

A A

5

4

105P/0805

C233

X_105P/0805

3VDUAL

3

C498
X_104P/BOT

+12V -12V

C19
104P

C80
104P

VCC3

-5V

C132

C435

104P

X_104P

VCC

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

2

http://www.msi.com.tw

BULK / Decopuling

MS-7102

Last Revision Date:
Sheet

1

Friday, July 23, 2004

32 36

Rev

0A

of

5

K8 CPU Power

4

NB & SB & AGP Power

3

2

1

Other Power

DDR SideCPU Side

K8 Vcore ->
"VCORE" (42A)

D D

VDDA_2.5 Power ->
"VDDA_25" (0.11A)

DDR Power ->
"VDD_25_SUS"
(9.5A)

DDR-VTTPower ->

HT Power ->
"VDD_12_A"&"VLDT0"

"VTT_DDR_SUS"
(5.21A)

NB & SB Core-Power

-> "VCC2_5" (?A)

NB & SB Core-Suspend
Power -> "VSUS2_5" (?A)

NB AGP8X Power ->
"VDDQ" (1.5A)

5VDU

3VDU

DDR_3VDUAL

9VSB

(2A)

ATX Power
Supply

VSUS2_5

-> SB

C C

+5VSB

5VDUAL 3VDUAL

VCC

P3VA ->
For 1394

Charge Pump

-> 9VSB

B B

+12V

VCORE ->
K8 CPU

+5VR ->
Audio

DDR_25_SUS

-> DDR

DDR_3VDUAL

VDDA_25 ->
K8 CPU(I/O)

VCC3

VDDQ

A A

-12V

5

-> AGP

VCC2_5 ->
NB & SB
( VLINK )

4

VDD_12_A

-> HT

3

VTT_DDR_SUS

-> DDR

2

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

Power Generation

MS-7102

Last Revision Date:

Wednesday, July 21, 2004

Sheet

1

33 36

of

Rev

0A

5

4

3

2

1

X_FM

X_FM

X_FM

X_FM

FM8

X

FM11

X

FM1

X

FM18

X

X_FM

X_FM

X_FM

X_FM

FM6

X

FM12

X

FM23

X

FM5

X

X_FM

X_FM

X_FM

X_FM

FM21

X

FM9

X

FM22

X

FM24

X

X_FM

X_FM

X_FM

X_FM

FM16

X

FM13

X

X_FM

X_FM

FM15

X

X_FM

FM3

X

X_FM

MH6

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

MH5

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

MH3

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

FM20

X

FM4

X

9

9

9

X_FM

X_FM

FM14

FM7

X

X

X_FM

VCC

T2

1
2

X_YJ102

Impedance Test

T1

1
2

X_YJ102

X_FM

MH2

5
6
7
8

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

5
6
7
8

MH7

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

5
6
7
8

9

9

MH8

5
6
7
8

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

5
6
7
8

9

MH4
X_150 Drill / 300 Pad

MH1

5
6
7
8

X_150 Drill / 300 Pad

1
2
3

(NPTH)

4

5
6
7
8

1
2
3

(NPTH)

4

5
6
7
8

PGND

9

9

FM10

X

D D

FM19

X

FM2

X

C C

FM17

X

B B

KBGND

Micro Star Restricted Secret

A A

Title

Screw Hole&FMark

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

5

4

3

http://www.msi.com.tw

2

MS-7102

Last Revision Date:
Sheet

Wednesday, July 21, 2004

34 36

of

Rev

0A

1

5

MS-7102 VER:0A

1.Page#5:Reserved R666 for THERMDC@070893

2.Page#7:Co-lay SCH for ICS-950403 & RTM360-803@070893

3.Page#11:AVDD2 source change from VCC3 to VDD3@070893

4.Page#12:Add VCC3 to VDD3 SCH for K8M800@070893

5.Page#13:DAC_PLL & AVDD1 source change from VCC3 to VDD3 for K8M800@070893

6.Page#16:Add GPIO12~GPIO14 to FAN & BIOS_WP for LEGEND@070893

7.Page#17:Add RI# for WOL for LEGEND@070893

8.Page#18:Add JI2C & JBAT1 SCH for LEGEND@070893

D D

9.Page#20:Add FAN SCH for LEGEND(ref-7078-100)@070893

10.Page#21:Add ALC655 SCH for LEGEND(ref-6741-100)@070893

11.Page#23:Change LAN connecter with transform(ref-7061-100)@070893

12.Page#24:Co-lay front USB Header with Intel & LEGEND(default is Intel)(ref-6555-40A)@070893

13.Page#25:Change SIO from W83697HF to W83687THF)(ref-7078-100)@070893

14.Page#26:Reserved R667,R669,R670 & change R15 to 0R;Vcore & VCC3 add R671 & R672 to SIO(ref-7078-100)@070893
Add BIOS_WP1 SCH for LEGEND@070893

15.Page#27:Add JCOM2 SCH for LEGEND@070893

17.Page#28:Add JLEG1 & FRISW & JWOL SCH for LEGEND@070893

18.Page#31:Add VDD=VCC2_5 SCH for K8T800 SCHforLEGEND@070893

19.Page#24:JUSB3.9 & JUSB4.9 pin change to GND ; JUSB2000/JUSB2001.9 pin modify to USB_OC#4 @0714

20.Page#27:Remove CN2000 & Add C2495~C2498 & remove L27,CP28@0714

21.Page#28:Remove JGLED1,R695 & Q87.C change from PWBTIN# to PWBTIN @0714

22.Page#26:Remove R15,VTIN1 & modify "THERMDA_CPU" to SIO(U16.67) directly @0714

23.Page#20:GPIO12/GPIO13 disconnect from CPUFAN_IN/SYSFAN_IN@0714

24.Page#24:JUSB200.10pin/JUSB2001.10 pin modify to USB_OC#4@0714

25.Page#28:Remove R123 and Add R2361 & R2362@0714

26.Page#18:Reserved C2499 closed to U2018 ; C2500 closed to JBAT1@0714

27.Page#17:Remove R2317;connect "GPO1" to RN2105.5 pin@0714

C C

28.Page#12:Reserve LC filter( B30ohm + 22P ) in AR/AG/AB near N.B ; Reserve 22P in HSYNC/VSYNC for EMI @0715

29.Page#10:Reserve 104p*7 in VDD_25_SUS and GND for EMI @0715

30.Page#21:Reserve 22p in AC_BITCLK for EMI @0715

31.Page#27:Add 120ohm bead in L2000~L2003 for EMI @0715

32.Page#27:PGND2 for JCOM2 @0716

33.Page#6:C2450 change footprint to "C0805MSB" at Botton side @0716

34.Page#24:Add R2363,R2364 for JUSB about Intel & LEGEND SPEC@0716

35.Page#22:Reserved R2365,R2366 closed to IDE@0716

36.Page#25:Add C2521,R2367,R2368 closed to SIO(U16)@0716

37.Page#26:Change R670 to VTIN_GND@0716

38.Page#10,25,32:Remove C394,C212,C2420,C2428,C2507 for EMI@0720

39.Page#All:Rename@0721

40.Page#10:Reserved C501 for EMI@0721

--->modify from 7054-0B@07/08/2004

Reserve 104p*1 in VDD_25_SUS and VTT_DDR_SUS for EMI @0715
Reserve 104p*3 in VDD_25_SUS and VCC3 for EMI @0715
Reserve 104p*1 in VDD_25_SUS and VCC2_5 for EMI @0715
Reserve 104p*2 in VDD_25_SUS and VCC for EMI @0715

4

3

2

1

B B

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

History

MS-7102

1

Last Revision Date:
Sheet

Rev

0A

Wednesday, July 21, 2004

35 36

of

5

4

3

2

1

Q13_HS

D D

TO252MOS_Heatsink

E31-0500261-K08

MOS_Heatsink

JBAT1(2-3)

YJUMPER-MG

LEGEND SPEC:

C C

JBAT1 Clear CMOS
1 - 2
2 - 3

U10_K8T

Clear CMOS
Normal

Q17_HS

TO252MOS_Heatsink

E31-0500261-K08

*

E31-0400070-K08

BIOS_WP1(1)

YJUMPER-M

LEGEND SPEC:

BIOS WRITE PROTECT

U10_NBHS

JAUDIO1(3-6)

LEGEND SPEC:

LEGEND AUDIO

L2_JC-D2x2-GN

VBAT1_1

YSKTBT

PCB1

PCB

P01-710200A-G37

U12_Flash

WINBOND/W29C040P-70B,5V

For K8T800(BOM)

K8T800

R354
3KST

R355
1KST

K8T800

1

2
3
5
7

RN109

4

8P4R-0

6

8

Micro Star Restricted Secret

Title

Manual Parts

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

5

4

3

http://www.msi.com.tw

2

MS-7102

Last Revision Date:
Sheet

Friday, July 23, 2004

36 36

of

1

Rev

0A

B B

A A