MSI MS-7102 Schematics

5

4

3

2

1

Version 0A

MS-7102

VIA (R) K8T800(8385)/K8M800(8380) / VT8237 Chipset
AMD PGA 754 Processor Schematics

D D

*AMD PGA 754 Processor
*VIA K8T800/K8M800 / VT8237 Chipset

(DDR 400 / AGP 8X / VLink 8X)
*Winbond 83687THF-VF LPC I/O
*VT6103 PHY 10 / 100
*AC'97 Codec ALC655 Codec
*USB 2.0 support (integrated into VT8237)
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 3
*DDR DIMM * 2

C C

K8T800

8237CD

4MB ROM

B B

Orcad Config ERP BOM

SMT5010
SMT5020

07/21/2004 Update

?
?
?

DIP

Total

?

Function Description

Create
Date.

Title Page

Cover Sheet 1
Block Diagram

Clock Synthesizer 7
System Memory

DDR DIMM 1 & 2 8
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T800/K8M800(HT)

VGA Connector
SB VT8237
PCI Connectors 1 & 2 & 3
FAN
AC97 Codec &

Audio Connector
ATA 66/100/133
VT6103 PHY 10/100
Front & Rear USB Port
LPC I/O W83687THF & Floppy
Hardware monitor/Fan/BIOS
Keyboard/Mouse & I/O Ports.
ACPI Power (MS6)
K8 Vcore power
PowerOK Circuit

/Front Panel
BULK / Decoupling
Power Generation
Manual Parts
History

2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket

9
10
11,12,13
14AGP SLOT 8X
15
16,17,18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

A A

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan

5

4

3

2

http://www.msi.com.tw

Cover Sheet

MS-7102

1

Last Revision Date:
Sheet

Rev

0A

Wednesday, July 21, 2004

1 36

of

5

Block Diagram

4

3

2

1

CPUCLK+ & CPUCLK-(100/133/166/200)

D D

HCLK+ & HCLK-(100/133/166/200) / GCLK(66)

AMD K8

Socket 754

HyperTransfer

SYSTEM CLOCK
Synthesizer

AGPCLK(66)

A

AGP 8X /Fast Write

C C

G
P

VIA

K8T800

DDR400

R,G,B,HSYNC,VSYNC

DDR * 2

VGA Connector

K8M800

VCLK(66) / OSC(14) / PCISB(33) / USBCLK(48) / APICCLK(14)

10/100 BaseT
Lan

B B

PCI 2

PCI 1

PCI 3

PCICLK[0~2]

PCI33

MII Interface

PCI Bus

AC'97 Link

VIA

VT8237

VLINK

Dual ATA
100/133

VT8237 S-ATA

IDE Slot
==>ATA66,100,133 *2

SATA Connector

SATA x2

LPC BUS

USB

A A

AC_14(14)

SIOPCLK(33)/SIO48M(48)

5

Onboard AC'97
Codec

4

Dual USB 1.1 OHCI
/2.0 EHCI 8 Ports
==> Front-Port *2 ,
Back-Port *2

3

SUPER I/O
W83687THF

X BUS

ROM Floopy Parallel Serial

Title

Document Number

2

Micro Star Restricted Secret

Block Diagram

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-7102

1

Keyboard

Last Revision Date:

Wednesday, July 21, 2004

Sheet

2

Mouse

of

Rev

0A

36

5

4

3

2

1

GPIO FUNCTION

VT8237 GPIO Function Define

D D

PIN NAME Function define

GPO0 (VSUS33)

GPO1/SUSA#(VSUS33)

GPO2/SUSB#(VSUS33)

GPO3/SUSST1#(VSUS33)

GPO4/SUSCLK(VSUS33)

GPO5/CPUSTP#

GPO6/PCISTP#

GPO7/SLP#

GPO8/GPI8/IPBIN0

GPO9/GPI9/IPBIN1

C C

GPO10/GPI10/IPBRDFR

GPO11/GPI11/IPBRDCK

GPO12/GPI12/IPBOUT0

GPO13/GPI13/IPBOUT1

GPO14/GPI14/IPBTDFR

GPO15/GPI15/IPBTDCK

GPO16/SA16/STRAP

GPO17/SA17/STRAP

GPO18/SA18/STRAP

B B

GPO19/SA19/STRAP

GPO20/GPI20
/ACSDIN2/PCS0#/EI

GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#

GPO22/GPI22/IOR#

GPO23/GPI23/IOW#

GPO24/GPI24/GPIOA

GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2

(VSUS33)
GPO27/GPI27/SMBCK2

(VSUS33)
GPO28/GPI28/

APICD0/APICCS#
GPO29/GPI29/

A A

APICD1/APICACK#

GPO30/GPI30/GPIOD

GPO31/GPI31/GPIOE

Default
Function

GPO0

SUSA#

SUSB#

SUSST1#

SUSCLK

CPUSTP#

PCISTP#

GPO7

GPI8

GPI9

GPI10

GPI11

GPI12

GPI13

GPI14

GPI15

SA16

SA17

SA18

SA19

GPI20

GPI21

GPI22

GPI23

GPI24

GPI25

SMBDT2

SMBCK2

SUSLED ( Power LED )

5V_STR Control on S5

SUSB#

SUSST#

NA

NA

NA

NA

NA

JBAT1

NA

NA

CPUFAN CTL for LEGEND

SFAN CTL for LEGEND

BIOS_WP for LEGEND

NA

LDT Freq Strapping Bit0

LDT Freq Strapping Bit1

LDT Width (Low=8 Bit)

Fast Command (Low=Disable)

NA

NA

NA

NA

NA

NA

SMBDATA2/Slave SMBUS

SMBCLK2/Slave SMBUS

CLEAR_CMOS#

NA

GPI30

GPI31

5

NA

NA

4

Pull up / down

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

As GPI

As GPI
As GPO:H=>can flash(default)

As GPO:L=>can't flash

Pull up to VCC3

Pull up to VCC3

Pull down to GND

Pull down to GND

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

Pull up to VCC3

PIN NAME

GPI1 (VSUS33)
GPI2/EXTSMI#

(VSUS33)
GPI3/RING#

(VSUS33)
GPI4/LID#

(VSUS33)
GPI5/BATLOW#

(VSUS33)

GPI6/PME#

GPI7/SMBALRT#
GPI16/INTRUDER#

(VBAT)

GPI17/CPUMISS

GPI18/AOLGP1/THRM#

PCI Routing

DEVICES

PCI SLOT 1

PCI SLOT 2

PCI SLOT 3

PCI SLOT 2

(MEDION 2nd)

1394

3

INT#

INT#A
INT#B
INT#C
INT#D

INT#B
INT#C
INT#D
INT#A

INT#C
INT#D
INT#A
INT#B

Default

GPI0

GPI1

EXTSMI#

RING#

LID#

BATLOW#

NA Pull up to VBATGPI0 (VBAT)

ATADET0=>Detect IDE1 ATA100/66

EXTSMI#

RING#

ATADET1=>Detect IDE2 ATA100/66

Clear Password

PCI_PME#

GPI7

INTRUDER#

CPUMISS

AOLGP1

NA

NA

NA

THRM#

IORDY

IDSEL

AD16

AD17

AD18

AD19 PCICLK4INT#A

AD25INT#D 1394_PCLK

REQ#/GNT#

PREQ#1
PGNT#1

PREQ#2
PGNT#2

PREQ#3
PGNT#3

PREQ#4
PGNT#4

PREQ#5
PGNT#5

2

CLOCK

PCICLK1

PCICLK2

PCICLK3

Pull up / downFunction defineFunction

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VBAT

Pull up to 3VDUAL

Pull up to 3VDUAL

Pull up to VCC3NAGPI19/IORDY

Micro Star Restricted Secret

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

GPIO Spec.

MS-7102

Last Revision Date:

Thursday, July 22, 2004

Sheet

3 36

1

Rev

0A

of

5

DDR_VREF routed as 40~50 mils
trace wide , Space>25 mils

DDR_VREF<8>

VDD_25_SUS

Bottom Side

DDR_VREF

R72 15RST
R73 15RST

MD[63..0]<10>

MEMDM[7..0]<10>

-MDQS[7..0]<10>

5

C455

X_102P/BOT

AMD DG=34.8 OHM

D D

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

C C

B B

A A

MEMZN
MEMZP

MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

MEMDM7
MEMDM6
MEMDM5
MEMDM4
MEMDM3
MEMDM2
MEMDM1
MEMDM0

-MDQS7

-MDQS6

-MDQS5

-MDQS4

-MDQS3

-MDQS2

-MDQS1

-MDQS0

AE13

AG12

D14
C14

A16
B15
A12
B11
A17
A15
C13
A11
A10

C11

AC1
AC3

AC2
AD1
AE1
AE3
AG3

AJ4

AE2

AF1

AH3

AJ3
AJ5
AJ6

AJ7
AH9
AG5
AH5

AJ9

AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16

A13

AA1
AG1
AH7

AH13

A14

AB1

AJ2

AJ8

AJ13

C43
X_102P

B9
C7
A6

A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2

M1
W1
W3

W2

Y1

R1

A7

C2

H1

T1

A8

D1

J1

VTT_SENSE

MEMVREF1
MEMZN

MEMZP

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

VTT_DDR_SUS

MEMORY INTERFACE

U7B

VTT_A

VTT_B

MEMRESET_L

MEMCKEA
MEMCKEB

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

RSVD_MEMADDA15
RSVD_MEMADDA14

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

RSVD_MEMADDB15
RSVD_MEMADDB14

MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10

MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

4

VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4

4

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

AG10
AE8

AE7
D10

C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

VTT_DDR_SUS

MCKE0
MCKE1

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4

MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

-MCS3

-MCS2

-MCS1

-MCS0

-MSRASA

-MSCASA

MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

X_1u_B

MCKE0 <8,9>
MCKE1 <8,9>

MEMCLK_H[7..0] <8,9>
MEMCLK_L[7..0] <8,9>

-MCS3 <8,9>

-MCS2 <8,9>

-MCS1 <8,9>

-MCS0 <8,9>

-MSRASA <8,9>

-MSCASA <8,9>

-MSWEA <8,9>
MEMBANKA1 <8,9>

MEMBANKA0 <8,9>

MAA[13..0] <8,9>

-MSRASB <8,9>

-MSCASB <8,9>

-MSWEB <8,9>
MEMBANKB1 <8,9>

MEMBANKB0 <8,9>

MAB[13..0] <8,9>

VDD_25_SUS

C456

3

C462

X_1u_B

3

Bottom Side

X_1u_B

C457

X_1u_B

CADIP[0..15]<11>

CLKIP1<11>

CLKIN1<11>

CLKIP0<11>

CLKIN0<11>

VLDT0

CTLIP0<11>
CTLIN0<11>

X_1u_B

C469

R56 49.9RST
R46 49.9RST

C475

VDD_12_A

CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0

CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3

CADIP1
CADIP0

CTLIP1
CTLIN1

2

Bottom Side

U7A

N12-7540010-F02

D29

VLDT0_A6

D27

VLDT0_A5

D25

VLDT0_A4

C28

VLDT0_A3

C26

VLDT0_A2

B29

VLDT0_A1

B27

VLDT0_A0

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

2

WIDTH 200MILS, AS CLOSE AS POSSIBLE TO THE
PROCESSOR AND THEN AS 20MILS TRACES IN THE
PIN FILED

VDD_12_A

C476

X_0.22u/BOT

L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0

L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0

HYPER TRANSPORT - LINK0

L0_CTLOUT_L0

Title

Size Document Number Rev

Date: Sheet of

VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0

MSI

C204

C147

X_0.22u

224P

VLDT0_B PINS SHOULD BE CONNECTED TO A
SIGNAL 4.7UF CAPACITOR ROUTED WITH A 100
MILS WIDE TRACE

AH29
AH27
AG28
AG26
AF29
AE28
AF25

N26

CADON15

N27
L25

CADON14

M25
L26

CADON13

L27
J25

CADON12

K25
G25

CADON11

H25
G26

CADON10

G27
E25

CADON9

F25
E26

CADON8

E27
N29

CADON7

P29
M28

CADON6

M27
L29

CADON5

M29
K28

CADON4

K27
H28

CADON3

H27
G29

CADON2

H29
F28

CADON1

F27
E29

CADON0

F29

CLKOP1

J26

CLKON1

J27

CLKOP0

J29

CLKON0

K29
N25

P25

CTLOP0

P28

CTLON0

P27

C212

X_0.22u

CADOP15
CADOP14
CADOP13
CADOP12
CADOP11
CADOP10
CADOP9
CADOP8
CADOP7
CADOP6
CADOP5
CADOP4
CADOP3
CADOP2CADIP2
CADOP1
CADOP0

C211

224P

VLDT0

475P/1206/16V

MICRO-STAR

K8 DDR & HT

MS-7102

1

C228

224P

VLDT0 <5>

C82

CADOP[0..15] <11>
CADON[0..15] <11>CADIN[0..15]<11>

CLKOP1 <11>
CLKON1 <11>
CLKOP0 <11>
CLKON0 <11>

CTLOP0 <11>
CTLON0 <11>

1

0.22uf

4 36Friday, July 23, 2004

C146

C75

X_0.22uf

0A

5

4

3

2

1

VCCA_PLL trace length from the VR1 to the PGA must be 0.75".

Place al filters close to the PGA.

Keep all power and signal trce away from the VR1.

D D

LAYOUT: Route VDDA trace approx. 50 mils wide
(use 2x25 mil traces to exit ball field) and 500 mils

VDDA_25

long.

FB1 180nH/1210

CPU_VDDA_25

Place a cut in the GND plane around the VCCA_PLL regulator circuit.

VCC2_5

C61

C65
475P/0805

3900P

C54

0.22uf

R185

C299
106P/1206

Near SB

1K

THRMTRIP# <30>

AH25

C44
X_102P

CPU_GD<30>

C C

-LDTSTOP

PS_OUT#<28,30>

B B

HDT Connectors

DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI

NC_AJ18
NC_C21

NC_AG17
NC_C19

A A

NC_D18
NC_D20
NC_B19

NC_AH18
NC_AG18

PS_OUT#

R39 X_56
R40 X_1K

RN36 X_56-8P4R

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

R36 X_1K
R37 X_1K

5

R58

Q14
X_NDS7002AS

1 2
3 4
5 6
7 8

VCC2_5

1K

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

VCC2_5

RN3
1K-8P4R

1K-8P4R
RN37

VLDT0

VLDT0<4>

R55 44.2RST
R51 44.2RST

8/28 AMD CHANGE THE PULL-UP POWER

VDD_25_SUS

4

C72
102P

C31

X_102P

C66

102P

VDD_25_SUS

VDDIO_SENSE

-CPURST<28>

-LDTSTOP<11,18>

COREFB_H<29>

Differential , "10:10:5:10:10".

Near CPU in 0.5" .

COREFB_L<29>

CPUCLK0_H<7>

CPUCLK0_L<7>

C63 3900P

C68 3900P

VTT_DDR_SUS

VCC2_5

3

CPU_GD

L0_REF1
L0_REF0

R50

R41 820
R47 820

R71 1K
R70 1K

VDDIO_SENSE

169RST

RN4

1 2

3 4

5 6

7 8

NC_AJ23
NC_AH23

DBRDY

TMS
TCK
TRST_L
TDI

NC_C18
NC_A19

NC_AE23
NC_AF23
NC_AF22
NC_AF21

X_1K-8P4R

CLKIN_H

CLKIN_L

VDDA1

AJ25

VDDA2

AF20

RESET_L

AE18

PWROK

AJ27

LDTSTOP_L

AF27

L0_REF1

AE26

L0_REF0

A23

COREFB_H

A24

COREFB_L

B23

CORE_SENSE

AE12

VDDIOFB_H

AF12

VDDIOFB_L

AE11

VDDIO_SENSE

AJ21

CLKIN_H

AH21

CLKIN_L

AJ23

NC_AJ23

AH23

NC_AH23

AE24

NC_AE24

AF24

NC_AF24

C16

VTT_A5

AG15

VTT_B5

AH17

DBRDY

C15

NC_C15

E20

TMS

E17

TCK

B21

TRST_L

A21

TDI

C18

NC_C18

A19

NC_A19

A28

KEY1

AJ28

KEY0

AE23

NC_AE23

AF23

NC_AF23

AF22

NC_AF22

AF21

NC_AF21

C1

FREE29

J3

FREE31

R3

FREE33

AA2

FREE35

D3

FREE1

AG2

FREE37

B18

FREE4

AH1

FREE38

AE21

FREE41

C20

FREE7

AG4

FREE11

C6

FREE12

AG6

FREE13

AE9

FREE14

AG9

FREE40

123456789101112131415

U7C

THERMTRIP_L

THERMDA
THERMDC

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

G_FBCLKOUT_H

G_FBCLKOUT_L

DBREQ_L

NC_D20
NC_C21
NC_D18
NC_C19
NC_B19

NC_AF18

RSVD_SCL
RSVD_SDA

FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25

123456789101112131415

FREE27

2

VID4
VID3
VID2
VID1
VID0

TDO

THRMTRIP#

A20

THERMDA_CPU

A26
A27

AG13
AF14
AG14
AF15
AE15

AG18
AH18
AG17
AJ18

AH19
AJ19

AE19
D20

C21
D18
C19
B19

A22

AF18

D22
C22

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

16

16

VTIN_GND

VID4
VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

FBCLKOUT_H

R52

80.6RST

FBCLKOUT_L

Zdiff = 80 ohm

DBREQ_L
NC_D20

NC_C21
NC_D18
NC_C19
NC_B19

TDO

VID0
VID2
VID1
VID3

VID4

MSI

Title

Size Document Number Rev

Date: Sheet of

THERMDA_CPU <25,26>

VID[4..0]

VID[4..0] <29>

LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )

8/28 AMD CHANGE THE PULL-UP POWER

VDD_25_SUS

R77 1K

RN2

7 8
5 6
3 4
1 2

X_8P4R-4.7K

R28 X_4.7K

MICRO-STAR

K8 HDT & MISC

MS-7102

1

VCC2_5

VTIN_GND <25,26>

R351

X_0R

C42
104P

5 36Friday, July 23, 2004

Bottom
side

C30

X_475P/0805

0A

5

4

3

2

1

U7E

VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205

171819

VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99

20

GND

20

GROUND

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2

VCORE VDD_25_SUS

K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17

AC15

AB14

AA15

AB16

AA17
AC17
AE17

AB18
AD18
AG19

AC19
AA19

AB20
AD20

AA21
AC21

AB22
AD22

AA23
AC23

AB24
AD24
AH24
AE25

GND

H18
B20
E21
H22

J23

H24

F26

V10
G13
K14
Y14

G15

J15

H16
K16
Y16

G17

J17

F18
K18
Y18

E19
G19

J19

F20
H20
K20
M20
P20
T20
V20
Y20

G21

J21

L21
N21
R21
U21
W21

F22
K22
M22
P22
T22
V22
Y22

E23
G23

L23
N23
R23
U23
W23

B24
D24

F24
K24
M24
P24
T24
V24
Y24

K26
P26
V26

U7D

L7

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9

N7

VDD10

L9

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19
VDD20
VDD21
VDD22
VDD23
VDD24
VDD25
VDD26
VDD27
VDD28
VDD29
VDD30
VDD31
VDD32
VDD33
VDD34
VDD35
VDD36
VDD39
VDD38
VDD37
VDD40
VDD41
VDD42
VDD43
VDD44
VDD45
VDD46
VDD47
VDD48
VDD49
VDD50
VDD51
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
VDD59
VDD60
VDD61
VDD62
VDD63
VDD64
VDD65
VDD66
VDD67
VDD68
VDD69
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
VDD77
VDD78
VDD79
VDD80
VDD81
VDD82
VDD83
VDD84
VDD85
VDD86
VDD87
VDD88
VDD89
VDD90
VDD91
VDD92

POWER

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50

VDDIO6

VDD96
VDD97
VDD98

VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133

VDD93

VDD94

VDD95

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

4

B2

VSS1

AH20

VSS3

AB21

VSS4

W22

VSS5

M23

VSS6

L24

VSS7

AG25

VSS8

AG27

VSS9

D D

C C

B B

A A

D2

VSS10

AF2

VSS11

W6

VSS12

Y7

VSS13

AA8

VSS14

AB9

VSS15

AA10

VSS16

J12

VSS17

B14

VSS18

Y15

VSS19

AE16

VSS20

J18

VSS21

G20

VSS22

R20

VSS23

U20

VSS24

W20

VSS25

AA20

VSS26

AC20

VSS27

AE20

VSS28

AG20

VSS29

AJ20

VSS30

D21

VSS31

F21

VSS32

H21

VSS33

K21

VSS34

M21

VSS35

P21

VSS36

T21

VSS37

V21

VSS38

Y21

VSS39

AD21

VSS40

AG21

VSS41

B22

VSS42

E22

VSS43

G22

VSS44

J22

VSS45

L22

VSS46

N22

VSS47

R22

VSS48

U22

VSS49

AG29

VSS50

AA22

VSS51

AC22

VSS52

AG22

VSS53

AH22

VSS54

AJ22

VSS55

D23

VSS56

F23

VSS57

H23

VSS58

K23

VSS59

P23

VSS60

T23

VSS61

V23

VSS62

Y23

VSS63

AB23

VSS64

AD23

VSS65

AG23

VSS66

E24

VSS67

G24

VSS68

J24

VSS69

N24

VSS70

R24

VSS71

U24

VSS72

W24

VSS73

AA24

VSS74

AC24

VSS75

AG24

VSS76

AJ24

VSS77

B25

VSS78

C25

VSS79

B26

VSS80

D26

VSS81

H26

VSS82

M26

VSS83

T26

VSS84

Y26

VSS85

AD26

VSS86

AF26

VSS87

AH26

VSS88

C27

VSS89

B28

VSS90

D28

VSS91

G28

VSS92

F15

VSS187

H15

VSS188

AB17

VSS206

AD17

VSS207

B16

VSS208

G18

VSS209

AA18

VSS210

AC18

VSS211

D19

VSS212

F19

VSS213

H19

VSS214

K19

VSS215

Y19

VSS216

AB19

VSS217

AD19

VSS218

AF19

VSS219

J20

VSS220

L20

VSS221

N20

VSS222

GND

171819

GNDGNDGND

5

EMI

LAYOUT: Place 1 capacitor every 1-1.5"

VCORE

along VDD_CORE perimiter.

103P

C52

C117

X_6.8pF

LAYOUT: Place 6 EMI capsalong bottom right side of Clawhammer, 2 in middle
of HT link, and 12 along

LAYOUT: Locate close to
Clawhammer socket.

VTT_DDR_SUS

+

C253
X_100u-16V

VCORE

LAYOUT: Place beside processor.

VDD_25_SUS

C262

VDD_25_SUS VDD_25_SUS

C57

X_475P/0805

105P

C111

GND

bottom left side of Claw-

VCORE

C460

C465

X_6.8pf_B

X_6.8pf_B

12

+

EC12
EL470/10V-3.5

C51

C471

0.22uf

0.22uf

0.22uf_B

BOTTOM SIDE BOTTOM SIDE

C148

C190

475P/0805

X_475P/0805

GND

hammer.

C458

C470

X_6.8pf_B

X_6.8pf_B

VTT_DDR_SUS

12

+

C50

0.22uf

0.22uf_B

GND

BOTTOM SIDE

C454

X_475P/0805

GND

475P/0805

C473

C461

X_6.8pf_B

12

+

CT14
X_ELS10/16V-B

GND

VDD_25_SUS

C463

X_6.8pf_B

BOTTOM SIDE

LAYOUT: Place one 1210 10uF capacitor
on each end of the VTT island.

CT1
X_ELS10/16V-B

C175

C453

0.22uf

C256

3

C459

X_6.8pf_B

VTT_DDR_SUS

C127
X_104P

GND

VCORE

C104

C98

104P

104P

C472

C467

X_6.8pf_B

X_6.8pf_B

X_6.8pf_B

GND

LAYOUT: Place 1000pF capacitors

CPU

Place on inside of CPU Cavity ( 5 * 0.22uF/0603
X7R high-freq decoupling Cap. )

VCORE

C101
X_0.22u

C95

X_0.22u

C108

0.22u

C466
X_0.22u_B

BOTTOM SIDE

C102

0.22u

C116

X_0.22u

between VRM & CPU.

RECOMMEND 4 PLACEDIN TOP SOCKET CAVITY
AND 2 ON THE BOTTOM DIRECTLY UNDER SOCKET CAVITY

106P/1206

C106

X_106P/1206

C186

C173

C207

C242

C270

C34

X_104P

X_104P

X_104P

X_104P

X_104P

GND

C141
X_104P

C135
X_104P

C85
X_104P

C129
X_104P

2

C115
X_104P

X_104P

C56
X_104P

Title

Size Document Number Rev

Date: Sheet of

C113

106P/1206

C38
X_104P

MSI

X_106P/1206

C114

C105

VCOREVCORE

C468

C92
106P/1206

106P/1206_B

MICRO-STAR

K8 POWER & GND

MS-7102

1

6 36Thursday, July 22, 2004

C464
106P/1206_B

0A

5

VCC3

C345

Clock Synthesizer

D D

CLKVCC3

C334 104P

CLKVCC3

C328 104P

VCC3_CLK

R242 10K
C355 104P

CLKVCC3

C346 104P

CLKVCC3

C356 104P

C354 X_104P

C C

CLKVCC3

C361 104P

CLKVCC3

C347 104P

CLKVCC3

C494 X_104P

VCC3_CLK

C341 104P

B B

46
47

2
5

32
33

9

10

16
15

19
20

29
30

27
38

39
35

34
43

42

ICS950403

U15

VDD_46
VSS_47

VDD_2
VSS_5

PD
VSSF

VDD_9
VSS_10

VDD_16
VSS_15

VDD_19
VSS_20

VDD_29
VSS_30

VSS_27
VDD_38

VSS_39
VDD_35

VSS_34
VDDA

VSSA

FS0/REF0
FS1/REF1
FS2/REF2

XIN

XOUT

FS3/48MHZ

ModeB/PCI33_HT66_1

PCI33_HT66_2
PCI33_HT66_3

PCI33_10

PCI33_0
PCI33_1
PCI33_2
PCI33_3

PCI33_F
PCI33_4
PCI33_5

24_48MHZ/SEL

SDATA

SCLK

CPUT_0

CPUC_0

CPUT_1

CPUC_1

ModeA/PCI33_HT66SEL

PCICLK6

RESET

1
48
45

3
4

31
7

8
11
12
13
14
17
18

23
21
22

28
26

25
41

40
37

36

6
24
44

104P

FS0
FS1
FS2

CLKX1
CLKX2

FS3
HT_66_0

HT_66_1
HT_66_2

SEL_24
SMBDATA1

SMBCLK1

> 0.5 inches

-SEL_66
SPREAD

RN78 8P4R-33

R194 10K
R214 33

4

FB21 120S/0805

R189 22
R193 22
R198 22
R209 22

X1 14.318MHZ

R244 33

RN73 8P4R-33

7

8

5

6

3

4

1

2

7

8

5

6

3

4

1

2

7

RN83 8P4R-33

8

5

6

3

4

1

2

R250 33

R236 15RST
R240 15RST

Close to Driver side

CLKVCC3

C357
104P

GUICLK
SB_OSC14
AUD_CLK
APICCLK

22PC332

22PC333

VCLK
GCLK_SLOT

GCLK_NB
PCICLK6
PCICLK1
PCICLK2

PCICLK3
SB_PCLK

SIO48M

SMBDATA1 <8,17,18,30>
SMBCLK1 <8,17,18,30>

CPUCLK0_H
CPUCLK0_L

FP_RST# <28,30>

C350
475P/0805

GUICLK <12>
SB_OSC14 <17>
AUD_CLK <21>
APICCLK <18>

USBCLK_SB <16>

VCLK <18>

GCLK_SLOT <14>
GCLK_NB <12>
PCICLK6 <25>
PCICLK1 <19>
PCICLK2 <19>

PCICLK3 <19>
SB_PCLK <18>

SIO48M <25>

CPUCLK0_H <5>
CPUCLK0_L <5>

3

CPUCLK0_H
CPUCLK0_L

SEL_24

FS3
FS2
FS1
FS0

FS3
FS2
FS1
FS0

HT_66_0

VCLK

GCLK_NB

USBCLK_SB
SIO48M
SB_OSC14
APICCLK

SB_PCLK
PCICLK3

PCICLK2

PCICLK6
PCICLK1

C351 X_5P
C352 X_5P

R253 10K

R243 10K
R203 X_10K
R190 X_10K
R188 X_10K

R245 X_10K
R202 10K
R197 10K
R192 10K

R191 10K

C335 X_10P

C340 X_10P

C362 10P
C365 10P
C319 X_10P
C337 X_10P

1 2
3 4
5 6
7 8

C349 X_10P
C353 X_10P

2

ModeA ModeB Pin6 Pin7

CLKVCC3

0 0

0

1
1 1

1

0

HTTCLK0

HTTCLK0

HTTCLK0
HTTCLK0

SER_24 Pin28

24MHz

1

48MHz

0

CN19
X_8P4C-10P

ICS:ModeA/ModeB=0/1

Pin8 Pin11
HTTCLK1

HTTCLK1

HTTCLK2

HTTCLK2

PCICLK7 PCICLK8
HTTCLK1

PCICLK8

1

PCICLK9

HTTCLK3

PCICLK9
PCICLK9

For RealTek RTM360-803

(1)

CLKVCC3

FB22

Input Configuration

FS2

FS1FS2

0 0 01

0

1

1

1 0

0
0
0
0

A A

0
0
0

0111
0 0

1

0

0

10 168.00

0

0

0

0 0
0

0 0

Clock Generator Output

FS0

CPU (MHz)

150

11 1

200.40

166.70

133.50

1

202
0
1

133.90

100.90

5

PCI33 (MHz)

33.33

33.33

33.33

33.33

36.56100.20

30.00
X1/6
X1/6

33.63

PCI33_HT66 (MHz)

33.33 or 66.66

33.33 or 66.66

33.33 or 66.66

33.33 or 66.66

73.12

60.00
X1/6
X1/3

67.27

4

Comment

Normal Hammer operation
Reserved
Athlon compatible
Athlon compatible
ICS OverClock
ICS UnderClock
Bypass mode
Bypass mode
Tri-state mode

3

(2)

VCLK

stuff C494 & C354(at U8.20 & U8.34)(3)

2

VCC3_CLK

X_120S/0805

CP11

X_COPPER

R201 X_10K

RealTek:ModeA/ModeB=0/0

*c494 reserved at solder side

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

N o. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

Clock Synthesizer

MS-7102

Last Revision Date:

Friday, July 23, 2004

Sheet

1

7 36

of

Rev

0A

5

R141 4.7K

DR_MD[63..0]

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP1

-MSWEA
DDR_VREF

C29
X_102P

2
4
6

8
94
95
98
99
12
13
19
20

105
106
109
110

23
24
28
31

114
117
121
123

33
35
39
40

126
127
131
133

53
55
57
60

146
147
150
151

61
64
68
69

153
155
161
162

72
73
79
80

165
166
170
171

83
84
87
88

174
175
178
179

90
63

1

9

101
102

DR_MD[63..0]<9,10>

D D

C C

B B

VDD_25_SUS

-MSWEA<4,9>

Place 104p Cap. near the DIMM

VDD_25_SUS

VDD_25_SUS

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDDQ0

VSS1

VSS2

VSS3

VSS4

VSS5

VSS6

VDDQ1

VSS7

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

WP(NC)
WE#

VREF
NC2

NC3

SLAVE ADDRESS = 1010000B

NC4

VSS0

3111826344250586674818993

4

SYSTEM MEMORY

104

112

128

136

143

156

164

172

1801582

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

184

PIN

DDR DIMM

SOCKET

CK1#(CK0#)

NC(RESET#)

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

100

116

124

132

139

145

152

160

176

VDDID

VDDQ15

FETEN

A10_AP

CK0(DU)
CK0#(DU)
CK1(CK0)

CK2(DU)
CK2#(DU)

VSS21

184

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

A11
A12
A13

BA0
BA1
BA2
SCL

SDA

SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

157
158
71
163

5
14
25
36
56
67
78
86
47

167
48

43
41
130
37
32
125
29
122
27
141
118
115
103

59
52
113
92
91
181
182
183

44
45
49
51
134
135
142
144

16
17
137
138
76
75

173
10

MCKE0

21

MCKE1

111

-MSCASA

65

-MSRASA

154

DR_MEMDM0

97

DR_MEMDM1

107

DR_MEMDM2

119

DR_MEMDM3

129

DR_MEMDM4

149

DR_MEMDM5

159

DR_MEMDM6

169

DR_MEMDM7

177
140

DDR1
DDR400-CH

-MCS0

-MCS1

-DR_MDQS0

-DR_MDQS1

-DR_MDQS2

-DR_MDQS3

-DR_MDQS4

-DR_MDQS5

-DR_MDQS6

-DR_MDQS7

MAA13
MAA0

MAA1
MAA2
MAA3
MAA4
MAA5
MAA6
MAA7
MAA8
MAA9
MAA10
MAA11
MAA12

SMBCLK1
SMBDATA1

MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7

3

-MCS0 <4,9>

-MCS1 <4,9>

-DR_MDQS0 <9,10>

-DR_MDQS1 <9,10>

-DR_MDQS2 <9,10>

-DR_MDQS3 <9,10>

-DR_MDQS4 <9,10>

-DR_MDQS5 <9,10>

-DR_MDQS6 <9,10>

-DR_MDQS7 <9,10>

MAA[13..0]

MAA[13..0] <4,9>

MEMBANKA0 <4,9>
MEMBANKA1 <4,9>

SMBCLK1 <7,17,18,30>
SMBDATA1 <7,17,18,30>

MEMCLK_H5 <4,9>
MEMCLK_L5 <4,9>
MEMCLK_H0 <4,9>
MEMCLK_L0 <4,9>
MEMCLK_H7 <4,9>
MEMCLK_L7 <4,9>

MCKE0 <4,9>
MCKE1 <4,9>

-MSCASA <4,9>

-MSRASA <4,9>

Place 104p and 1000p Cap.
near the DIMM

DR_MEMDM[7..0]

VDD_25_SUS

DR_MEMDM[7..0] <9,10>

R142 4.7K

-MSWEB<4,9>

C39
104P

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP2

-MSWEB
DDR_VREF

2

VDD_25_SUS

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

VDDQ0

VDDQ1

VSS2

VSS3

VSS4

VSS5

VSS6

VSS7

VDDQ2

VSS8

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

SLAVE ADDRESS = 1010001B

102

NC4

VSS0

VSS1

3111826344250586674818993

104

112

128

136

143

156

164

172

1801582

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

VDDQ15

FETEN

A10_AP

184

PIN

DDR DIMM

SOCKET

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC(RESET#)

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

VSS21

100

116

124

132

139

145

152

160

176

VDDID

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

A11
A12
A13

BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

184

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

157
158
71
163

-DR_MDQS0

5

-DR_MDQS1

14

-DR_MDQS2

25

-DR_MDQS3

36

-DR_MDQS4

56

-DR_MDQS5

67

-DR_MDQS6

78

-DR_MDQS7

86
47

167
48

43
41
130
37
32
125
29
122
27
141
118
115
103

59
52
113
92
91
181
182
183

44
45
49
51
134
135
142
144

MEMCLK_H4

16

MEMCLK_L4

17

MEMCLK_H1

137

MEMCLK_L1

138

MEMCLK_H6

76

MEMCLK_L6

75
173

10
21

111
65
154

DR_MEMDM0

97

DR_MEMDM1

107

DR_MEMDM2

119

DR_MEMDM3

129

DR_MEMDM4

149

DR_MEMDM5

159

DR_MEMDM6

169

DR_MEMDM7

177
140

DDR2
DDR400-CH

1

-MCS2

-MCS3

MAB13
MAB0

MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12

SMBCLK1
SMBDATA1

MCKE0
MCKE1

-MSCASB

-MSRASB

-MCS2 <4,9>

-MCS3 <4,9>

MAB[13..0] <4,9>

MEMBANKB0 <4,9>
MEMBANKB1 <4,9>

VDD_25_SUS

MEMCLK_H4 <4,9>
MEMCLK_L4 <4,9>
MEMCLK_H1 <4,9>
MEMCLK_L1 <4,9>
MEMCLK_H6 <4,9>
MEMCLK_L6 <4,9>

-MSCASB <4,9>

-MSRASB <4,9>

R34
1KST

A A

R44
1KST

C45
X_104P

DDR_VREF

C46
104P

DDR_VREF <4>

5

MSI

Title

Size Document Number Rev

4

3

2

Date: Sheet of

MICRO-STAR

DDR

MS-7102

1

8 36Wednesday, July 21, 2004

0A

5

DDR Terminations

4

3

2

1

VTT_DDR_SUS VTT_DDR_SUS

4

DR_MD44
DR_MD40
DR_MD39
DR_MD35

DR_MD38
DR_MD34

DR_MEMDM4

-DR_MDQS4
DR_MD37
DR_MD33

DR_MD36

DR_MD32

MAB10
MAB0
MAA10
MAA0

MAA1
MAB1
MAB2
MAA2

DR_MD31
DR_MD27
DR_MD30
DR_MD26

MAB3
MAA3
DR_MEMDM3
MAA4

-DR_MDQS3
DR_MD25
MAB4
MAA6

DR_MD29
DR_MD28
MAA5
MAA8

DR_MD24
MAB6
MAB5
DR_MD19

DR_MD19

D D

DR_MD59
DR_MD63
DR_MD58
DR_MD62

-DR_MDQS7
DR_MEMDM7
DR_MD57
DR_MD61

DR_MD56
DR_MD60
DR_MD51
DR_MD55

C C

B B

-MSCASA<4,8>

-MSCASB<4,8>

-MSRASA<4,8>

-MSRASB<4,8>

A A

DR_MD50
DR_MD54

-DR_MDQS6
DR_MEMDM6

MAA13
MAB13
DR_MD53
DR_MD52

DR_MD49
DR_MD48
DR_MD47
DR_MD46

DR_MD43
DR_MD42
DR_MEMDM5

-DR_MDQS5

-MCS0

-MCS0<4,8>

-MCS2

-MCS2<4,8>

-MCS1

-MCS1<4,8>

-MCS3

-MCS3<4,8>

-MSCASA
DR_MD41

-MSCASB

-MSWEB

-MSWEB<4,8>

-MSRASA

-MSRASB

-MSWEA

-MSWEA<4,8>
DR_MD45

The Processor pins and resistor
are less than 1" in length.

MEMCLK_H5
MEMCLK_H4
MEMCLK_H7
MEMCLK_H6
MEMCLK_H1
MEMCLK_H0

5

RN66 47-8P4R

7 8
5 6
3 4
1 2

RN63 47-8P4R

7 8
5 6
3 4
1 2

RN61 47-8P4R

7 8
5 6
3 4
1 2

RN59 47-8P4R

7 8
5 6
3 4
1 2

RN57 47-8P4R

7 8
5 6
3 4
1 2

RN54 47-8P4R

7 8
5 6
3 4
1 2

RN50 47-8P4R

7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8

RN49 47-8P4R
RN47 47-8P4R

7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8

RN45 47-8P4R

R61 120RST
R59 120RST
R75 120RST
R74 120RST
R63 120RST
R64 120RST

MEMCLK_L5
MEMCLK_L4
MEMCLK_L7
MEMCLK_L6
MEMCLK_L1
MEMCLK_L0

MEMBANKA0<4,8>

MEMBANKB0<4,8>

MEMBANKB1<4,8>
MEMBANKA1<4,8>

VTT_DDR_SUS

RN43 47-8P4R

7 8
5 6
3 4
1 2

RN42 47-8P4R

7 8
5 6
3 4
1 2

RN40 47-8P4R

7 8
5 6
3 4
1 2

RN38 47-8P4R

7 8
5 6
3 4
1 2

RN35 47-8P4R

7 8
5 6
3 4
1 2

RN34 47-8P4R

7 8
5 6
3 4
1 2

RN32 47-8P4R

7 8
5 6
3 4
1 2

RN31 47-8P4R

7 8
5 6
3 4
1 2

RN30 47-8P4R

7 8
5 6
3 4
1 2

RN28 47-8P4R

7 8
5 6
3 4
1 2

RN26 47-8P4R

7 8
5 6
3 4
1 2

-MCS2

-MCS2<4,8>

DR_MD23
MAA7
MAA9
MAA11

MAA12
DR_MD22
MAB8
MAB7

DR_MD18

MAB9

DR_MEMDM2

MAB11

DR_MD21

-DR_MDQS2

DR_MD17

MAB12

DR_MD16

DR_MD20

MCKE0<4,8>
MCKE1<4,8>

DR_MD11

DR_MD10

DR_MD15

DR_MD14

DR_MEMDM1

DR_MD13

-DR_MDQS1

DR_MD12

DR_MD9

DR_MD8

DR_MD3

DR_MD7

DR_MD6
DR_MD2

-DR_MDQS0

DR_MEMDM0

DR_MD1

DR_MD5

DR_MD4

DR_MD0

DR_MEMDM[7..0]<8,10>

MEMCLK_L[7..0]<4,8>

MEMCLK_H[7..0]<4,8>

-DR_MDQS[7..0]<8,10>

3

RN24 47-8P4R

7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8

RN22 47-8P4R
RN20 47-8P4R

7 8
5 6
3 4
1 2

RN18 47-8P4R

7 8
5 6
3 4
1 2

RN15 47-8P4R

7 8
5 6
3 4
1 2

RN13 47-8P4R

7 8
5 6
3 4
1 2

RN11 47-8P4R

7 8
5 6
3 4
1 2

RN10 47-8P4R

7 8
5 6
3 4
1 2

RN7 47-8P4R

7 8
5 6
3 4
1 2

RN5 47-8P4R

7 8
5 6
3 4
1 2

DR_MD[63..0]<8,10>

MAB[13..0]<4,8>
MAA[13..0]<4,8>

DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_MEMDM[7..0]

MEMCLK_L[7..0]
MEMCLK_H[7..0]

-DR_MDQS[7..0]

2

-MSCASB<4,8>

-MSCASA<4,8>

-MSRASB<4,8>

-MSRASA<4,8>

MEMBANKB1<4,8>

MEMBANKA1<4,8>

MEMBANKB0<4,8>

MEMBANKA0<4,8>

-MCS3

-MCS3<4,8>
MAB13

MAA13

MAB12
MAA12
MAB11
MAA11

MAB1
MAA1

MAB3
MAA3
MAB2
MAA2

MAB6

MAA6
MAB4
MAA4

MAB8
MAA8
MAB5
MAA5

MAA0

MAA10

MAB0
MAB10

-MSCASB

-MCS0

-MCS0<4,8>

-MSCASA

-MCS1

-MCS1<4,8>

MAA9
MAB9
MAB7
MAA7

-MSRASB

-MSRASA

-MSWEB

-MSWEB<4,8>

-MSWEA

-MSWEA<4,8>

MCKE1<4,8>

MCKE0<4,8>

MSI

Title

Size Document Number Rev

Date: Sheet of

CN18

12
34
56
78

X_8P4C-22P
CN4

12
34
56
78

X_8P4C-22P
CN13

12
34
56
78

X_8P4C-22P
CN12

12
34
56
78

X_8P4C-22P
CN11

12
34
56
78

X_8P4C-22P
CN9

12
34
56
78

X_8P4C-22P
CN14

12
34
56
78

X_8P4C-22P
CN17

12
34
56
78

X_8P4C-22P
CN6

12
34
56
78

X_8P4C-22P
CN16

12
34
56
78

X_8P4C-22P
CN15

12
34
56
78

X_8P4C-22P
CN3

12
34
56
78

X_8P4C-22P

MICRO-STAR

DDR Terminations Part 1

MS-7102

9 36Wednesday, July 21, 2004

1

0A

5

4

3

2

1

LAYOUT: Place on backside,

DDR Terminations

D D

C C

B B

-MDQS[7..0]<4>

-DR_MDQS[7..0]<8,9>
DR_MD[63..0]<8,9>

MD[63..0]<4>

MEMDM[7..0]<4>

DR_MEMDM[7..0]<8,9>

RN6 10-8P4R

MD0

1 2

MD4

3 4

MD5

5 6

MD1

7 8

RN8 10-8P4R

MEMDM0 DR_MEMDM0

1 2

-MDQS0

3 4

MD2

5 6

MD6

7 8

RN9 10-8P4R

MD7

1 2

MD3

3 4

MD8

5 6

MD9

7 8

RN12 10-8P4R

MD12

1 2

-MDQS1 -DR_MDQS1

3 4

MEMDM1 DR_MEMDM1

5 6

MD13 DR_MD13

7 8

RN14 10-8P4R

MD14

1 2

MD15

3 4

MD10

5 6

MD11

7 8

RN21 10-8P4R

MD21 DR_MD21

1 2

MEMDM2 DR_MEMDM2

3 4

MD18 DR_MD18

5 6

MD22 DR_MD22

7 8

RN17 10-8P4R

MD20

1 2

MD16

3 4

-MDQS2

5 6

MD17

7 8

RN25 10-8P4R

MD23

1 2

MD19 DR_MD19

3 4

MD24

5 6

MD28 DR_MD28

7 8

RN29 10-8P4R

MD29

1 2

MD25

3 4

-MDQS3

5 6

MEMDM3 DR_MEMDM3

7 8

DR_MD0
DR_MD4
DR_MD5
DR_MD1

-DR_MDQS0
DR_MD2
DR_MD6

DR_MD7
DR_MD3
DR_MD8
DR_MD9

DR_MD12

DR_MD14
DR_MD15
DR_MD10
DR_MD11

DR_MD20
DR_MD16

-DR_MDQS2
DR_MD17

DR_MD23
DR_MD24

DR_MD29
DR_MD25

-DR_MDQS3

-MDQS[7..0]

-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]

RN33 10-8P4R

MD26

1 2

MD30

3 4

MD27

5 6

MD31

7 8

RN39 10-8P4R

MD32

1 2

MD36

3 4

MD33

5 6

MD37

7 8

RN41 10-8P4R

-MDQS4 -DR_MDQS4

1 2

MEMDM4 DR_MEMDM4

3 4

MD34 DR_MD34

5 6

MD38 DR_MD38

7 8

RN44 10-8P4R

MD35 DR_MD35

1 2

MD39

3 4

MD40

5 6

MD44

7 8

RN48 10-8P4R

MD45 DR_MD45

1 2

MD41

3 4

-MDQS5 -DR_MDQS5

5 6

MEMDM5 DR_MEMDM5

7 8

RN51 10-8P4R

MD42 DR_MD42

1 2

MD43

3 4

MD46 DR_MD46

5 6

MD47

7 8

RN55 10-8P4R

MD48 DR_MD48

1 2

MD49

3 4

MD52 DR_MD52

5 6

MD53 DR_MD53

7 8

RN58 10-8P4R

MEMDM6

1 2

-MDQS6

3 4

MD54

5 6

MD50 DR_MD50

7 8

RN60 10-8P4R

MD55

1 2

MD51

3 4

MD60

5 6

MD56 DR_MD56

7 8

RN62 10-8P4R

MD61

1 2

MD57

3 4

MEMDM7 DR_MEMDM7

5 6

-MDQS7 -DR_MDQS7

7 8

RN65 10-8P4R

MD62 DR_MD62

1 2

MD58

3 4

MD63

5 6

MD59

7 8

DR_MD26
DR_MD30
DR_MD27
DR_MD31

DR_MD32
DR_MD36
DR_MD33
DR_MD37

DR_MD39
DR_MD40
DR_MD44

DR_MD41

DR_MD43
DR_MD47

DR_MD49

DR_MEMDM6

-DR_MDQS6
DR_MD54

DR_MD55
DR_MD51
DR_MD60

DR_MD61
DR_MD57

DR_MD58
DR_MD63
DR_MD59

evenly spaced around VTT fill.

VDD_25_SUS

VTT_DDR_SUS

C60

X_0.22uF

C168

X_0.22uF

C70

X_0.22uF

C257

X_0.22uF

C58

X_0.22uF

VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS

C86

X_1u
C78

1u
C90

1u

C134

1u

C94

X_1u
C99

1u

VTT_DDR_SUS

1u

C40

C18

1u

C83

X_1u

C76

C89

VTT_DDR_SUS

1u

1u

C37

VTT_DDR_SUS

1u

X_1u

C159

LAYOUT: Locate close to Clawhammer socket.

VTT_DDR_SUS

C47

C10

C170

X_1u

X_1u

C71

C177

C107

1u
C112

X_1u

C73

1u
C130

X_1u

C119

1u

C263

X_1u

C122

1u

1u

C97

C91

X_1u

1u

X_1u

C187

C194

C126

X_1u
C27

1u
C41

X_1u
C142

1u
C156

X_1u
C162

1u
C171

X_1u

1u

1u

C109

1u

X_1u

C202

C103

C208

X_1u

1u

C128

C216

1u

X_1u

C133

C221

X_1u

1u

LAYOUT: Place alternating caps to GND and VDD_2.5_SUS

C121

C230

C69

0.22uf

475P/0805

GND

C49

C269

X_1u

1u

C138

C261

VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS

C225

X_1u

C235

1u

C243

X_1u

C247

1u

C258

X_1u

C55

1u

1u

X_1u

C151

GND

C23

X_1u

X_1u

GND

1u

X_1u

1u

X_1u

X_1u

1u

1u

X_1u

C179

C191

C197

C203

C210

C219

1u

C64

X_1u

C124

1u

X_1u

C238

C245

in a single line along VTT island.

VDD_25_SUS

C163

C278

X_104P

X_104P

C279

X_104P

C234

X_104P

X_104P

VTT_DDR_SUS VCC3 VCC2_5 VCC

A A

EMI request @930715

C205

C62

C15

X_104P

X_104P

VCC3

C403

C501
X_104P

X_104P

GND

5

solder side

C499
X_104P

VDD_25_SUS

GND

C152
X_104P

C166
X_104P

4

C110
X_104P

C174
X_104P

C125
X_104P

C96
X_104P

C77
X_104P

C193
X_104P

C206
X_104P

VTT_DDR_SUS

3

C155
475P/0805

LAYOUT: Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs (both sides).

VTT_DDR_SUS

102P

102P

C268

C167
475P/0805

C259

C196
X_475P/0805

C118

C32

0.22uf

X_102P

GND

C33

X_475P/0805

GND

C283
475P/0805

2

VTT_DDR_SUS

C144

0.22uf

GND

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR

DDR Terminations Part 2

MS-7102

10 36Thursday, July 22, 2004

1

0A

A

AVDD2

A10

A24

A25

A26A9B10

T26
P24
P26
M24
K24
K26
H24
H26
R24
R22
N24
N22
L22
J24
J22
G24

M26
L24

F24
R26

P25
N26
M25
K25
J26
H25
G26
R23
P22
N23
M22
K22
J23
H22
G23

L26
L23

F25
B11

A12
D25

D26
C26

U24
U25
U26
V21
V22
V23
V24
V25
V26

C22

AVDD2

RCADP0
RCADP1
RCADP2
RCADP3
RCADP4
RCADP5
RCADP6
RCADP7
RCADP8
RCADP9
RCADP10
RCADP11
RCADP12
RCADP13
RCADP14
RCADP15

RCLKP0
RCLKP1

RCTLP
RCADN0

RCADN1
RCADN2
RCADN3
RCADN4
RCADN5
RCADN6
RCADN7
RCADN8
RCADN9
RCADN10
RCADN11
RCADN12
RCADN13
RCADN14
RCADN15

RCLKN0
RCLKN1

RCTLN
LDTRST

LDTSTP
RPCOMP

RNCOMP
RTCOMP

VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT

AGND2

C21

A23

From Claw Hammer

4 4

CADOP[0..15]<4>

CLKOP0<4>
CLKOP1<4>

CTLOP0<4>

CADON[0..15]<4>

3 3

CLKON0<4>
CLKON1<4>

CTLON0<4>

-LDTRST<28>

-LDTSTOP<5,18>

2 2

CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15

CLKOP0
CLKOP1

CTLOP0

CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15

CLKON0
CLKON1

CTLON0

-LDTRST

-LDTSTOP
RPCOMP

PNCOMP
RTCOMP

VDD_12_A

VSS

A8

VLDT

VSS

B8

VLDT

VSS

B13

VLDT

VSS

B15

U10A

VLDT

VSS

B17

VLDT

VSS

B19

B23

VLDT

VSS

B21

B24

B25

VLDT

VLDT

VSS

VSS

B22C8D8

B26B9C10

VLDT

VLDT

VSS

VSS

D6

VLDT

VSS

D12

C11

VLDT

VSS

D14

C23

VLDT

VSS

D16

C24

VLDT

VSS

D18

B

C25C9D10

VLDT

VLDT

VSS

VSS

D20

E5E6E8F7F8

VLDT

VSS

D11

VLDT

VSS

D22

VLDT

VSS

D23

VLDT

VSS

D24D9E10

VLDT

VLDT

VSS

VSS

F13

F12

VLDT

VSS

F14

E11

VLDT

VSS

F17

E21

VLDT

VSS

F18

E22

VLDT

VSS

F26

E23

E24E9F10

VLDT

VLDT

VSS

VSS

G25H1H23

VDD_12_A

VLDT

VLDT

VLDT

VSS

VSS

VSS

F11

F15

VLDT

VSS

J18

F16

VLDT

VSS

J2

F19

VLDT

VSS

J3

F20

VLDT

VSS

J21

F21

VLDT

VSS

J25

F22

VLDT

VSS

K4G1K10

F23

VLDT

VSS

C

K8T800/K8M800 HT Interface

G21

VLDT

VSS

K11

G22

VLDT

VSS

K12

H21

VLDT

VSS

K13

J10

VLDT

VSS

K14

J11

VLDT

VSS

K15

J12

VLDT

VSS

K16

J13

VLDT

VSS

K17

J14

VLDT

VSS

K23H2L10

J15

VLDT

VSS

J16

J17

VLDT

VLDT

TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8

TCADP9
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15

TCLKP0

TCLKP1

TCADN0

TCADN1

TCADN2

TCADN3

TCADN4

TCADN5

TCADN6

TCADN7

TCADN8

TCADN9
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15

TCLKN0

TCLKN1

VSS

VSS

L11

L12

K18

K21

VLDT

VLDT

TCTLP

TCTLN

VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT

VSS

VSS

L13

L14

L18

VLDT

VSS

L15

VLDT

VSS

CADIP0

B12

CADIP1

A13

CADIP2

B14

CADIP3

A15

CADIP4

A17

CADIP5

B18

CADIP6

A19

CADIP7

B20

CADIP8

E12

CADIP9

D13

CADIP10

E14

CADIP11

D15

CADIP12

D17

CADIP13

E18

CADIP14

D19

CADIP15

E20

CLKIP0

B16

CLKIP1

E16

CTLIP0

A21

CADIN0

C12

CADIN1

A14

CADIN2

C14

CADIN3

A16

CADIN4

A18

CADIN5

C18

CADIN6

A20

CADIN7

C20

CADIN8

E13

CADIN9

C13

CADIN10

E15

CADIN11

C15

CADIN12

C17

CADIN13

E19

CADIN14

C19

CADIN15

D21

CLKIN0

C16

CLKIN1

E17

CTLIN0

A22

VDD_12_A

L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23

K8T800/K8M800

To Claw Hammer

CADIP[0..15] <4>

CLKIP0 <4>
CLKIP1 <4>

CTLIP0 <4>

CADIN[0..15] <4>

CLKIN0 <4>
CLKIN1 <4>

CTLIN0 <4>

D

E

For K8M800 Only

CP3

AVDD2

C181
102P

C180
105P

VDD3

FB6
X_80S

1 2

For K8T800(BOM)

1)U10--->U10_K8T

2)Remove C180,C181

BOTTOM SIDE

C478 X_104P/B
C184 104P

PNCOMP
RTCOMP
RPCOMP

VDD_12_A

Around NB

VDD_12_A

R93 49.9RST
R86 100RST
R85 49.9RST

(1)K8T800 Ver:CD(VT8385)

=>B01-0838505-V01

1 1

A

(2)K8M800 Ver:CD(VT8380)

=>B01-K8M8005-V01

B

Title

Size Document Number Rev

C

C

D

Date: Sheet of

{OrgName}

NORTH BRIDGE K8M800 (HT)

MS-7102

11 36Thursday, July 22, 2004

E

0A