MSI MS-7097 Schematics

Cover Sheet 1
Block Diagram
GPIO
History
Intel mPGA478B CPU - Signals
Intel LGA775 CPU - Power 6

1

2
3
4
5

MS(7097)

Intel (R) 865P (GMCH) + ICH5 Chipset
Intel LGA775 Processor

CPU:

Version
100

Intel LGA775

Intel LGA775 CPU - GND
Intel Springdale - Host Signals
Intel Springdale - Memory Signals
Intel Springdale - AGP
DDR DIMM 1,2
PCB Holes
ICH5(1)

A A

ICH5(2)
Clock & FWH & FDD
LPC I/O -W83627THF
AC97 Audio
AGP 4X/8X Slot & FAN
PCI Slots 1 & 2
PCI Slots 3 & 4
ATA33/66/100 IDE & Video Connectors
USB Connectors
ACPI controller

7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

System Chipset:

Intel 865P - GMCH (North Bridge)
Intel ICH5 (South Bridge)

On Board Chipset:

BIOS -- FWH EEPROM
AC'97 Codec -- ALC655
LPC Super I/O -- W83627THF
LAN --RTL8100C/8110S
CLOCK

--ICS952620

Main Memory:

DDR * 2 (Max 2GB)

Expansion Slots:

PCI SLOT * 4

PWM:

Controller:
RT8800B

ATX & Front Panel
VRM 25
EMI parts 26
RTL8100C/8110S
LAN Connector

24

27
28

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

1

Date: Sheet of

COVER SHEET

MS-7097

1 29Friday, August 27, 2004

100

1

RT880B
2-Phase PWM

AGP 1.5V

4X/8X

Connector

IDE Primary

UltraDMA 33/66/100

IDE Secondary

A A

USB Port 0

Intel LGA775 Processor

FSB

Springdale

HUB

Link

ICH5

64bit DDR
Channel 1

64bit DDR
Channel 2

2 DDR
DIMM
Modules

PCI CNTRL

PCI ADDR/DATA

PCI Slot 1

PCI Slot 2

Block Diagram

RTL8100C/8110S

PCI Slot 3

PCI Slot 4

USB Port 1

USB Port 2

USB

LPC Bus

USB Port 3

USB Port 4

SATA

LPC SIO

USB Port 5

Winbond
83627THF

USB Port 6

USB Port 7

AC'97 Codec

AC'97 Link

Flash

Keyboard

Mouse

Floopy Parallel Serial

1

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

BLOCK DIAGRAM

MS-7097

2 29Wednesday, August 18, 2004

100

1

ICH5

GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23

I

PREQ#B

I

PREQ#B

I

PIRQ#E

I

PIRQ#F

I

PIRQ#G

I

PIRQ#H

I

GPI6

I

GPI7

I

CSA_PME#

I

OC4#

I

OC5#

I

SIO_SMI#

I

EXTSMI#

I

SIO_PME#

I OC#6

OC#7

I

PGNT#A

O
O

PGNT#B

O GPO18

BIOS_WP#

O
O

GPO20
O GPO21
OD
O

GPO23

GPIO 24 I/O GPIO24

FunctionTypeGPIO Pin

GPIO 25 I/O

A A

*

GPIO 27
GPIO 28
GPIO 32
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48
GPIO 49

LAN_DISABLE#

I/O

GPIO27
I/O GPIO28
I/O

GPIO32
I/O

GPIO33
I/O

GPIO34
I

GPI41

I
O PGNT#4

CPUPWRGD

OD

Power well

MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN

default output
default output
default output
default output
default output
default output
default output

PCI Config.

DEVICE

INTA#
INTB#

PCI_REQ#0PCI Slot 1

PCI_GNT#0
INTC#
INTD#

PCI Slot 2

INTB#
INTC#

PCI_REQ#1 AD17 PCICLK1

PCI_GNT#1
INTD#
INTA#

PCI Slot 3 PCI_REQ#2 AD18

INTC#
INTD#

PCI_GNT#2
INTA#
INTB#
INTD#

PCI_REQ#3PCI Slot 4 AD19
INTA# PCI_GNT#3
INTB#
INTC#

PCI Slot 5

INTB#
INTC#

PCI_REQ#4 AD21 PCICLK4

PCI_GNT#4
INTD#
INTA#

IDSEL

AD16

DDR DIMM Config.

DEVICE

DIMM 1 MCLK_A0/MCLK_A0#

DIMM 2

1010000B

1010001B

CLOCKADDRESS

MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#

CLOCKREQ#/GNT#

PCICLK0

PCICLK2

PCICLK3

CLK GEN PIN OUTMCP1 INT Pin

13 (PCI_CLK0)

14 (PCI_CLK1)

15 (PCI_CLK2)

16 (PCI_CLK3)

19 (PCI_CLK4)

FWH

Function

GPI 0 PD_DET
GPI 1

*

GPI 3

*

TypeGPIO Pin

I
I

SD_DET

I

Pull down through 1K ohms (unused)GPI 2
Pull down through 1K ohms (unused)

I

Pull down through 1K ohms (unused)GPI 4

I

PCI RESET DEVICE

Signals

PCIRST#1

HD_RST#

Springdale,LAN,FWH, Super I/O
PCI slot 1-3, AGP slotPCIRST#2
Primary, Scondary IDE

Target

MSI

Title

Size Document Number Rev

1

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

General Purpose Spec

MS-7097

3 29Wednesday, August 18, 2004

100

8

7

6

5

4

3

2

1

93/06/29

1.Create MS7097 ver:0A circuit.

D D

93/08/26

1.Add R213 for PICCLK6 enable.

2.Modified VRM circuit.

3.Swap LAN LED TX_RX and LINK100 signal.

4.Modified HDD LED pull up to VCC5.

6.Change USB2 and USB3 to JUSB1 and JUSB2.

7.Modified VRM choke to 40A.

8.Add 1.1A polyfuse on front USB.

9.Remove RN21.

10.Swap CPU and system fan on super IO pin out.

11.Modified Audio quality issue.

93/10/05

C C

Page23

Page23,29

Page25
Page 16

1.Reserved S3 remove circuit.

2.Add USB power select jumper.

3.Add two DIP high side mos in VRM.

4.USE GP30 SIO pin92 to strapping S3 en/disable.

93/10/20

Page22
Page22
Page25

1.Change common choke footprint.

2.Reserved protection diode for USB ports.

3.Change VRM choke footprint.

B B

A A

MSI

Title

Size Document Number Rev

8

7

6

5

4

3

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

HISTORY

MS-7097

2

4 29Wednesday, October 20, 2004

1

100

8

7

6

5

4

3

2

1

MCH_GTLREF 8

VCC3

R73
110R1%

R80

61.9R1%

2
4
6
8

V_FSB_VTT

VTT_OUT_RIGHT

H_BPM#3
H_BPM#5
H_BPM#1
H_BPM#0
H_TDI
H_BPM#2
H_BPM#4
H_TDO

H_TMS
H_TCK
H_TRST#

AN3

DBR#

D14#

D13#

B12D8C11

AN4

AN5

AN6

RSVD

RSVD

VSS_SENSE

VCC_SENSE

D12#

D11#

D10#

D9#

B10

A11

A10A7B7B6A5C6A4C5B4

R45 X_1KR

TP2

AJ3

AK3

AM5

AM7

VID7#

ITP_CLK1

ITP_CLK0

D8#

D7#

D6#

D5#

D4#

VID5

VID4

VID3

AL4

AK4

AL6

VID6#

VID5#

VID4#

VID_SELECT

GTLREF_SEL

LINT0/INTR

D3#

D2#

D1#

VID2

AM3

VID3#

GTLREF0
GTLREF1

PCREQ#

TESTHI12
TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1#
BCLK0#

COMP5
COMP4
COMP3
COMP2
COMP1
COMP0

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

LINT1/NMI

D0#

ZIF-SOCK775-15u

CPU SIGNAL BLOCK

D D

HDBI#[0..3]8

H_IERR#6

FERR#6,14

STPCLK#14

HDBI#0
HDBI#1
HDBI#2
HDBI#3

H_EDRDY

HINIT#14,15

HDBSY#8
HDRDY#8

HTRDY#8

C C

HADS#8

HLOCK#8

HBNR#8

HIT#8

HITM#8

HBPRI#8

HDEFER#8

CPU_TMPA16
VTIN_GND16

TRMTRIP#6,14

H_PROCHOT#6,8

IGNNE#14

SMI#14

A20M#14

SLP#14

H_TDI
H_TDO
H_TMS
H_TRST#
H_TCK

C25 X_C0.1U25Y

B B

R47 X_1KR

H_FSBSEL06,15
H_FSBSEL16,15
H_FSBSEL26

CPU_BOOTVTT_OUT_RIGHT

H_PWRGD6,14

H_CPURST#6,8

HD#[0..63]8

HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54

A8
G11
D19
C20

F2
AB2
AB3

R3

M3
AD3

P3

H4

B2

C1

E3

D2

C3

C2

D4

E4

G8

G7
AD1

AF1
AC1
AG1
AE1
AL1
AK1

M2
AE8
AL2

N2

P2

K3

L2
AH2

N5
AE6

C9
G10
D16
A20

Y1

V2
AA2

G29
H30
G30

N1
G23
B22

A22
A19
B19
B21
C21
B18
A17
B16
C18

HA#[3..31]8

U5A

DBI0#
DBI1#
DBI2#
DBI3#

EDRDY#
IERR#
MCERR#
FERR#/PBE#
STPCLK#
BINIT#
INIT#
RSP#

DBSY#
DRDY#
TRDY#

ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#

TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#

RSVD
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5

BOOTSELECT
LL_ID0
LL_ID1

BSEL0
BSEL1
BSEL2

PWRGOOD
RESET#
D63#

D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

B15

D53#

HA#31

AJ6

AJ5

AH5

AH4

AG5

AG4

AG6

AF4

AF5

AB4

AC5

AB5

AA5

AD6

AA4Y4Y6W6AB6W5V4V5U4U5T4U6T5R4M4L4M5P6L5

A35#

A34#

A33#

A32#

A31#

A30#

A29#

A28#

A27#

A26#

A25#

A24#

A23#

A22#

A21#

A20#

A19#

A18#

A17#

A16#

A15#

A14#

A13#

A12#

A11#

D52#

D51#

D50#

D49#

D48#

D47#

D46#

D45#

D44#

D43#

D42#

D41#

D40#

D39#

D38#

D37#

D36#

D35#

D34#

D33#

D32#

D31#

D30#

D29#

D28#

D27#

D26#

D25#

C14

C15

A14

D17

D20

G22

D22

E22

G21

F21

E21

F20

E19

E18

F18

F17

G17

G18

E16

E15

G16

G15

D24#

F15

G14

F14

G13

E13

D13

F12

F11

HA#5

HA#6

HA#7

HA#8

HA#9

A9#

A8#

A7#

A6#

A10#

D23#

D22#

D21#

D20#

D19#

D10

E10D7E9F9F8G9D11

A5#

D18#

HA#3

HA#4

AC2

A4#

A3#

D17#

D16#

D15#

C12

HA#10

HA#11

HA#12

HA#13

HA#14

HA#15

HA#16

HA#17

HA#18

HA#19

HA#20

HA#21

HA#22

HA#23

HA#24

HA#25

HA#26

HA#27

HA#28

HA#29

HA#30

VID1

AL5

VID2#

VID1#

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

RSVD
RSVD

RS2#
RS1#
RS0#

AP1#
AP0#
BR0#

DP3#
DP2#
DP1#
DP0#

VID0

AM2

VID0#

ICH_RST# 14,24

AN7
H1
H2
H29

AG3
AF2
AG2
AD2
AJ1
AJ2

G5
J6
K6
M6
J5
K4

H_TESTHI12

W2

H_TESTHI11

P1

H_TESTHI10

H5

H_TESTHI9

G4

H_TESTHI8

G3
F24
G24
G26
G27
G25
F25
W3
F26
AK6
G6

G28
F28

A3
F5
B3

U3
U2
F3
T2
J2
R1
G2
T1
A13

J17
H16
H15
J16

AD5
R6
C17
G19
E12
B9
A16
G20
G12
C8
L1
K1

H_BPM#5
H_BPM#4
H_BPM#3
H_BPM#2
H_BPM#1
H_BPM#0

H_PCREQ#
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

H_TESTHI2_7
H_TESTHI1
H_TESTHI0
RSVD_AK6
RSVD_G6

HRS#2
HRS#1
HRS#0

H_COMP5
H_COMP4
H_COMP3
H_COMP2
H_COMP1
H_COMP0

VCCP

+12V

TP1

CPU_GTLREF

TP8

GTLREF_SEL

CPU_GTLREF 6

TP9

GTLREF_SEL

R89
10KR

R74
619R1%

G

DS

N-2N7002_SOT23

VCC3

HREQ#[0..4] 8

R90
249R1%

RN6 8P4R-62R

1 2
3 4
5 6
7 8

R64 62R

VTT_OUT_LEFT

G

N-2N7002_SOT23

V_FSB_VTT

R85 62R
R48 62R
R81 X_62R
R17 X_62R
R57 X_62R RN2

CPU_CLK# 15
CPU_CLK 15

HRS#[0..2] 8

TP4
TP3

R51 X_60.4R1%
R60 X_60.4R1%
R53 100R1%
R66 100R1%
R50 60.4R1%
R97 60.4R1%

TP6
TP12
TP7
TP5

HADSTB#1 8
HADSTB#0 8
HDSTBP#3 8
HDSTBP#2 8
HDSTBP#1 8
HDSTBP#0 8
HDSTBN#3 8
HDSTBN#2 8
HDSTBN#1 8
HDSTBN#0 8
NMI 14
INTR 14

VTT_OUT_RIGHT 6

H_BR#0 6,8

VTT_OUT_LEFT 6

C41

X_C0.1U25Y

VID325
VID125
VID425
VID225
VID025
VID525

PLACE RESISTORS OUTSIDE SOCKET
CAVITY IF NO ROOM FOR VARIABLE
RESISTOR DON'T PLACE

VID3
VID1
VID4
VID2
VID0
VID5

VTT_OUT_RIGHT

C36 C0.1U25Y
C38 C0.1U25Y

PLACE BPM TERMINATION NEAR CPU

H_EDRDY

R67 680R

H_PCREQ#

R59 680R

Q12

DS

Q13

H_TESTHI0

X_8P4R-680R

1
3
5
7

R27 X_680R
R28 X_680R

RN3 8P4R-51R

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

RN4 8P4R-51R

R44 X_49.9R1%
R43 X_49.9R1%
R42 49.9R1%

A A

8

HD#53

MSI

Title

Size Document Number Rev

7

6

5

4

3

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

Intel LGA775 CPU - Signals

2

MS-7097

5 29Wednesday, October 06, 2004

1

100

HD#0

HD#1

HD#2

HD#3

HD#4

HD#5

HD#6

HD#7

HD#8

HD#9

HD#10

HD#11

HD#12

HD#13

HD#14

HD#15

HD#16

HD#17

HD#18

HD#19

HD#20

HD#21

HD#22

HD#23

HD#24

HD#25

HD#26

HD#27

HD#28

HD#29

HD#30

HD#31

HD#32

HD#33

HD#34

HD#35

HD#36

HD#37

HD#38

HD#39

HD#40

HD#41

HD#42

HD#43

HD#44

HD#45

HD#46

HD#47

HD#48

HD#49

HD#50

HD#51

HD#52

8

VCCP

AG21

AG19

AG18

AG15

AG14

AG12

AG11

AF9

AF8

AF22

AF21

AF19
AF18
AF15
AF14
AF12
AF11

AE9
AE23
AE22
AE21
AE19
AE18
AE15
AE14
AE12
AE11

AD8
AD30
AD29
AD28
AD27
AD26
AD25
AD24
AD23

AC8
AC30
AC29
AC28
AC27
AC26
AC25
AC24
AC23

AB8

AA8

VCCP

U5B

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Y28

Y29

Y30

Y8

W30W8Y23

Y24

Y25

Y26

Y27

VCCP

D D

C C

AG22

W29

VCC

VCC

AG25

VCC

VCC

W28

AG26

VCC

VCC

W27

AG27

VCC

VCC

W26

AG28

W25

VCC

VCC

AG29

VCC

VCC

W24

7

AG30

VCC

VCC

W23

6

AH27

AH26

AH25

AH22

AH21

AH19

AH18

AH15

AH14

AH12

AH11

AG9

AG8

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U26

U27

U28

U29

U30U8V8

VCC

VCC

AH28

AH29

AH30

AH8

AH9

AJ11

AJ12

AJ14

AJ15

AJ18

AJ19

AJ21

AJ22

AJ25

AJ26

AJ8

AJ9

AK11

AK12

AK14

AK15

AK18

AK19

AK21

AK22

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

U24

U25

T24

T25

T26

T27

T28

T29

T30T8U23

N24

N25

N26

N27

N28

N29

N30N8P8R8T23

M24

M25

M26

M27

M28

M29

M30M8N23

VCC

VCC

AK25

M23

VCC

VCC

AK26

VCC

VCC

5

AK8

AK9

AL11

AL12

AL14

AL15

AL18

AL19

AL21

AL22

AL25

AL26

AL29

AL30

AL8

AL9

AM11

AM12

AM14

AM15

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

J29

J30J8J9

K23

K24

K25

K26

K27

K28

K29

K30K8L8

J22

J23

J24

J25

J26

J27

J28

VCC

VCC

AM18

J21

VCC

VCC

AM19

VCC

VCC

J20

AM21

VCC

VCC

J19

AM22

VCC

VCC

J18

AM25

VCC

VCC

J15

AM26

VCC

VCC

J14

4

AM29

J13

VCC

VCC

AM30

VCC

VCC

J12

AM8

J11

AM9

VCC

VCC

J10

AN11

AN12

AN14

AN15

AN18

AN19

VCC

VCC

VCC

VCC

VCC

VCC

VTT_OUT_RIGHT

VTT_OUT_LEFT

RSVD/VTT_PKGSENSE

VCC

VCC

VCC

VCC

VCC

VCC

AN25

AN26

AN29

AN30

AN8

AN9

AN21

AN22

VCC

VCC

VCC

VCC-IOPLL

VTTPWRGD

VTT_SEL

VCC

HS1

123

HS2

VCCA
VSSA
RSVD

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

HS3

HS4

4

H_VCCA

A23

H_VSSA

B23
D23

H_VCCA

C23

A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
B30
C25
C26
C27
C28
C29
C30
D25
D26
D27
D28
D29
D30

VTT_PWG

AM6

VTT_OUT_RIGHT

AA1

VTT_OUT_LEFT

J1
F27

F29

ZIF-SOCK775-15u

3

V_FSB_VTT

R84 X_1KR

VTT_SEL

VCC3

0
1

TEJ/PSC

RSVD

2

V_FSB_VTT

1

C96 C10U10Y0805
C90 C10U10Y0805
C100 X_C10U10Y0805

CAPS FOR FSB GENERIC

PLACE COMPONENTS AS CLOSE AS POSSIBLE TO PROCESSOR SOCKET
TRACE WIDTH TO CAPS MUST BE SMALLER THAN 12MILS

VTT_OUT_RIGHT

VTT_OUT_LEFT CPU_GTLREF

B B

A A

GTLREF VOLTAGE SHOULD BE

0.67*VTT = 0.8V

VTT_OUT_LEFT5

VTT_OUT_RIGHT5

VTT_OUT_LEFT

8

R58 49.9R1%

R63 X_49.9R1%

R62
100R1%

PLACE AT CPU END OF ROUTE

R56 62R
R54 100R
R68 62R

V_FSB_VTT

R55 62R
R52 62R
R46 62R

C47

C48

C220P50N

C0.1U25Y

H_CPURST#
H_PWRGD
H_BR#0

H_PROCHOT#VTT_OUT_RIGHT

R30 120R

PLACE AT ICH END OF ROUTE

TRMTRIP#
FERR#
H_IERR#

7

H_CPURST# 5,8
H_PWRGD 5,14
H_BR#0 5,8

TRMTRIP# 5,14
FERR# 5,14
H_IERR# 5

CPU_GTLREF 5

6

V_FSB_VTT

L1 X_10U100m_0805

CP5

X_COPPER

VID_GD#23,25H_PROCHOT# 5,8

FSBSEL RESISTOR CAN BE REMOVED IF ONLY TEJAS
AND CEDAR MILL ARE SUPPORTED

V_FSB_VTT

RN21

1
3
5
7

X_8P4R-470R

5

H_FSBSEL1

2
4

H_FSBSEL2

6

H_FSBSEL0

8

4

VTT_OUT_RIGHT

VCC5_SB

R39
1KR

R38 10KR

H_FSBSEL1 5,15
H_FSBSEL2 5

H_FSBSEL0 5,15

C91

X_C1U10Y

R29 680R

VTT_OUT_LEFT

R36
X_680R

3

C93

C10U10Y1206

1.25V VTT_PWRGOOD

VTT_PWG

Q7

N-MMBT3904_SOT23

H_VCCA

C92

X_C10U10Y1206

H_VSSA

C31

X_C1U10Y

MICRO-STAR INt'L CO., LTD.

MSI

Title

Size Document Number Rev

Date: Sheet of

2

Intel LGA775 CPU - Power

MS-7097

6 29Wednesday, October 06, 2004

1

100

8

7

6

5

4

3

2

1

TP11

TP13

TP14

AC4

AE3

AE4D1D14

U5C

RSVD

RSVD

RSVD

AE29

VSS

AE30

VSS

RSVD

VSS

VSS

VSS

AE5

AE7

AF10

AF13

D D

C C

AA23
AA24
AA25
AA26
AA27
AA28
AA29

AA30

AB23
AB24
AB25
AB26
AB27
AB28
AB29
AB30

AE10
AE13
AE16
AE17

AE20
AE24
AE25
AE26
AE27
AE28

A12

VSS

A15

VSS

A18

VSS

A2

VSS

A21

VSS

A24

VSS

A6

VSS

A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AA3

VSS
VSS

AA6

VSS

AA7

VSS

AB1

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

AB7

VSS

AC3

VSS

AC6

VSS

AC7

VSS

AD4

VSS

AD7

VSS
VSS
VSS
VSS
VSS

AE2

VSS
VSS
VSS
VSS
VSS
VSS
VSS

TP10

E23

E24E5E6E7F23F6B13J3N4P5V1W1Y3Y7Y5Y2W7W4V7V6V30V3V29

VSS

VSS

VSS

VSS

VSS

AG20

VSS

AG23

VSS

AG24

VSS

VSS

VSS

VSS

VSS

VSS

AG7

AH1

AH10

AH13

RSVD

VSS

AF16

RSVD

VSS

AF17

RSVD

VSS

AF20

RSVD

VSS

AF23

RSVD

VSS

AF24

RSVD

VSS

AF25

RSVD

VSS

AF26

RSVD

VSS

AF27

RSVD

VSS

AF28

VSS

AF29

VSS

AF3

RSVD

VSS

AF30

RSVD

VSS

AF6

RSVD

VSS

AF7

VSS

AG10

RSVD

VSS

AG13

RSVD

VSS

AG16

RSVD

VSS

AG17

VSS

AH16

VSS

VSS

AH17

VSS

VSS

AH20

VSS

VSS

VSS

VSS

AH23

V28

VSS

VSS

AH24

V27

V26

VSS

VSS

VSS

VSS

AH3

AH6

V25

V24

V23U7U1T7T6T3R7R5R30

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AH7

AJ10

AJ13

AJ16

AJ17

AJ20

AJ23

VSS

VSS

AJ24

VSS

VSS

AJ27

VSS

VSS

AJ28

VSS

VSS

AJ29

VSS

VSS

R29

AJ30

VSS

VSS

H17

H18

H19

H20

H21

H22

H23

H24

H25

H26

H27

H28

VSS

VSS

L26

VSS

VSS

AM13

L25

VSS

VSS

AM16

L24

VSS

VSS

AM17

L23K7K5

VSS

VSS

AM20

AM23

VSS

VSS

VSS

VSS

AM24

K2

AM27

R28

R27

R26

R25

R24

R23R2P7P4P30

P29

P28

P27

P26

P25

P24

P23N7N6N3M7M1L7L6L30L3L29

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AJ4

AJ7

AK10

AK13

AK16

AK17

AK2

AK20

AK23

AK24

AK27

AK28

AK29

AK30

VSS

AK5

AK7

AL10

AL13

AL16

AL17

AL20

VSS

VSS

AL23

VSS

VSS

AL24

VSS

VSS

AL27

VSS

VSS

AL28

VSS

VSS

L28

L27

VSS

VSS

VSS

VSS

VSS

VSS

AL3

AL7

AM1

AM10

VSS

VSS

VSS

VSS

AM28

AM4

VSS

VSS

VSS

H3H6H7H8H9J4J7

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

AN1

AN10

AN13

AN16

AN17

AN2

AN20

AN23

AN24

AN27

AN28B1B11

VSS

VSS

B14

ZIF-SOCK775-15u

H14

VSS

H13

VSS

H12

VSS

H11

VSS

H10

VSS

G1

VSS

F7

VSS

F4

VSS

F22

VSS

F19

VSS

F16

VSS

F13

VSS

F10

VSS

E8

VSS

E29

VSS

E28

VSS

E27

VSS

E26

VSS

E25

VSS

E20

VSS

E2

VSS

E17

VSS

E14

VSS

E11

VSS

D9

VSS

D6

VSS

D5

VSS

D3

VSS

D24

VSS

D21

VSS

D18

VSS

D15

VSS

D12

VSS

C7

VSS

C4

VSS

C24

VSS

C22

VSS

C19

VSS

C16

VSS

C13

VSS

C10

VSS

B8

VSS

B5

VSS

B24

VSS

B20

VSS

B17

VSS

B B

A A

MSI

Title

Size Document Number Rev

8

7

6

5

4

3

Date: Sheet of

MICRO-STAR INt'L CO., LTD.

Intel LGA775 CPU - GND

2

MS-7097

7 29Wednesday, October 06, 2004

1

100

8

HA#[3..31]5

D D

HADSTB#05
HADSTB#15

H_BR#05,6

C C

HBPRI#5

HBNR#5

HLOCK#5

HADS#5

HREQ#[0..4]5

HIT#5

HITM#5

HDEFER#5

HTRDY#5
HDBSY#5

HDRDY#5

HRS#[0..2]5

MCH_CLK15

MCH_CLK#15

MS5_POK14,23
H_CPURST#5,6

B B

PCIRST#116,23,27

ICH_SYNC#

H_PROCHOT#5,6

R106 20R1%

BSEL0_SPG
BSEL1_SPG

BSEL0_SPG15
BSEL1_SPG15

MCH_GTLREF

0.63*Vccp

R120 X_200R1%

V_FSB_VTT

NEXT
GMCH

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HRS#0
HRS#1
HRS#2

HRCOMP
HSWING

VCCA_FSB

D26
D30

L23
E29
B32
K23
C30
C31

J25
B31
E30
B33

J24
F25
D34
C32
F28
C34

J27

G27

F29
E28
H27
K24
E32
F31

G30

J26

G26

B30
D28

B24
B26

B28
E25
F27
B29

J23

L22
C29

J21
K21

E23

L21
D24

E27

G24
G22

C27
B27

B7
C7

AE14

E8

AK4

AJ8

L20

L13

L12
E24
C25
F23

C116
C0.1U25Y

C113 C0.1U25Y

VCCA_DPLL

U6A

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

HAD_STB0#
HAD_STB1#

BREQ0#
BPRI#

BNR#
HLOCK#
ADS#
HREQ0#

HREQ1#
HREQ2#
HREQ3#
HREQ4#

HIT#
HITM#
DEFER#

HTRDY#
DBSY#
DRDY#

RS0#
RS1#
RS2#

HCLKP
HCLKN

PWROK
CPURST#

RSTIN#
ICH_SYNC#

PROCHOT#

BSEL0
BSEL1

HDRCOMP
HDSWING
HDVREF

V_FSB_VTT

A A

HSWING MCH_GTLREF

R121

1/4*Vccp

C115
C10000P50Y5

8

300R1%

R103
100R

7

B3

A31

VCCA_FSB

VCCA_DPLL

VSS

VSS

C10

C8

7

B4

VCCA_FSB

VSS

C12

C14

VCC_AGP

J6J7J8J9K6K7K8K9L6L7L9

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

C16

VSS

C18

C20

C22

C24

C26

C28D1D11

D9

VCC

VSS

VCC

VSS

6

N11N9P10

P11

R11

T16

T17

T18

T19

U16

U17

U20

V16

V18

V20

W16

VCC

VSS

W19

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

F18

F20

F22

F24

F14

F16E1F10

F12

N10

M10

M11M8M9

L10

L11

VCC

VCC

VCC

VCC

VSS

VSS

D13

D15

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

D17

VSS

D19

D21

D23

D25

D27

D29

D31

D33

VCC

VSS

T20

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

D35

F3F5F8

E3

F1

VCC

VSS

W20

F26

VCC

VSS

5

Y16

Y17

Y18

Y19

Y20

A3

A33

A35B2B25

B34C1C23

NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

G31

G35

H5

G28

VSS

VSS

VSS

VSS

H12

H14

H16H2H20

H18

H8

H9

4

V_FSB_VTT

C35

E26

M31

AF13

AF23

AJ12

AN1

AP2

AR3

AR33

AR35

A7A9A11

A13

A16

A20

VSS

A23

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

K11

K12

K14

K16

K18

K20

K22

R25

NC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

H22

H24

H26

H30

H33

J10

J12

VSS

J14

J16

J18

J20

J22

J28

J32

J35

A25

VSS

VSS

K25

VSS

VSS

A27

A29

VSS

VSS

K27

K29

D5D6D7E6E7

A32

C4

VSS

VSS

VSS

VSS

VSS

VSS

VSS

K33

L24M3M6

L25

L26

VTT

VSS

VTT

VTT

VSS

VSS

L35

L31

F7

A4A5A6B5B6C5C6

VTT

VTT

VTT

VSS

VSS

VSS

M26

M27

VTT

VSS

3

VTT_FSB1

C128 C0.47U16Y

VTT_FSB2

C123 C0.47U16Y

A15

A21

VTT

VTT

VTT

VTT

VTT

VTT

VTT_FSB

VTT_FSB

HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

DINV_0#
DINV_1#
DINV_2#
DINV_3#

HD_STBP0#
HD_STBN0#

HD_STBP1#
HD_STBN1#

HD_STBP2#
HD_STBN2#

HD_STBP3#
HD_STBN3#

VSS

VSS

VSS

VSS

VSS

RG82865PE-A2

M28

M30

M33N1N4

{Priority}

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#

HD#0

B23

HD#1

E22

HD#2

B21

HD#3

D20

HD#4

B22

HD#5

D22

HD#6

B20

HD#7

C21

HD#8

E18

HD#9

E20

HD#10

B16

HD#11

D16

HD#12

B18

HD#13

B17

HD#14

E16

HD#15

D18

HD#16

G20

HD#17

F17

HD#18

E19

HD#19

F19

HD#20

J17

HD#21

L18

HD#22

G16

HD#23

G18

HD#24

F21

HD#25

F15

HD#26

E15

HD#27

E21

HD#28

J19

HD#29

G14

HD#30

E17

HD#31

K17

HD#32

J15

HD#33

L16

HD#34

J13

HD#35

F13

HD#36

F11

HD#37

E13

HD#38

K15

HD#39

G12

HD#40

G10

HD#41

L15

HD#42

E11

HD#43

K13

HD#44

J11

HD#45

H10

HD#46

G8

HD#47

E9

HD#48

B13

HD#49

E14

HD#50

B14

HD#51

B12

HD#52

B15

HD#53

D14

HD#54

C13

HD#55

B11

HD#56

D10

HD#57

C11

HD#58

E10

HD#59

B10

HD#60

C9

HD#61

B9

HD#62

D8

HD#63

B8

HDBI#0

C17

HDBI#1

L17

HDBI#2

L14

HDBI#3

C15
B19

C19
L19

K19
G9

F9
D12

E12

2

HD#[0..63] 5

HDBI#[0..3] 5

HDSTBP#0 5
HDSTBN#0 5

HDSTBP#1 5
HDSTBN#1 5

HDSTBP#2 5
HDSTBN#2 5

HDSTBP#3 5
HDSTBN#3 5

U9_H1

_

V_FSB_VTT

C136
C0.1U25Y

1

VCC3

I=30mA

VCCA_FSB

C144
C0.1U25Y

I=35mA

ESR is 0.1mohm to GMCH

VCCA_DPLL

C146
X_0R

6

CP19

X

CP8

R130 X_220R

X

VCC_AGP

VCC_AGP

5

V_FSB_VTT

R117
100R1%

R104
210R1%

C114
C0.1U25Y

C109
X_C220P16X0402

CAPS SHOULD BE PLACED NEAR MCH PIN

4

MCH_GTLREF 5

3

ICH_SYNC#

MSI

Title

Size Document Number Rev

Date: Sheet of

2

R178

X_220R

MICRO-STAR INt'L CO., LTD.

Intel Springdale - CPU Signals

MS-7097

8 29Wednesday, October 06, 2004

1

100

8

MCS_A#011
MCS_A#111

D D

MRAS_A#11
MCAS_A#11

MWE_A#11

MA_A[0..12]11

MBA_A011
MBA_A111

C C

MDQM_A[0..7]11

MDQS_A[0..7]11

MCLK_A011

MCLK_A#011

MCLK_A111

MCLK_A#111

MCLK_A211

MCLK_A#211

B B

C10000P50Y5C204
C10000P50Y5C189

C10000P50Y5C208
C0.1U25YC110

MDQ_A[0..63]11 MCKE_A[0..1] 11

AA34

W34

AC33

AB34

MA_A0

AJ34

MA_A1

AL33

MA_A2

AK29

MA_A3

AN31

MA_A4

AL30

MA_A5

AL26

MA_A6

AL28

MA_A7

AN25

MA_A8

AP26

MA_A9

AP24

MA_A10

AJ33

MA_A11

AN23

MA_A12

AN21

AL34
AM34
AP32
AP31
AM26

AE33
AH34

MDQM_A0

AP12

MDQM_A1

AP16

MDQM_A2

AM24

MDQM_A3

AP30

MDQM_A4

AF31

MDQM_A5

W33

MDQM_A6

M34

MDQM_A7
MDQS_A0

AN11

MDQS_A1

AP15

MDQS_A2

AP23

MDQS_A3

AM30

MDQS_A4

AF34

MDQS_A5
MDQS_A6

M32

MDQS_A7

AK32
AK31

AP17
AN17

AK33
AK34

AM16

AL16

XRCOMP

AK9

XCOMPH

AN9

XCOMPL
XVREF

C107 X_C2.2U6.3Y

A A

8

7

MDQ_A3

MDQ_A4

AN13

AM10

SDQ_A2

SDQ_A3

MDQ_A6

MDQ_A5

AL10

AL12

SDQ_A4

SDQ_A5

MDQ_A8

MDQ_A7

AP13

AP14

SDQ_A6

SDQ_A7

MDQ_A9

MDQ_A10

AM14

AL18

SDQ_A8

SDQ_A9

MDQ_A11

AP19

SDQ_A10

MDQ_A1

MDQ_A2

MDQ_A0

AP10

AP11

U6B

SCS_A0#

Y31

SCS_A1#

Y32

SCS_A2#
SCS_A3#

SRAS_A#

Y34

SCAS_A#

AM12

SDQ_A0

SDQ_A1

SWE_A#

SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12

SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5

SBA_A0
SBA_A1

SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6

H32

SDM_A7
SDQS_A0

SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4

V34

SDQS_A5
SDQS_A6

H31

SDQS_A7

SMDCLK_A0
SMDCLK_A0#

SMDCLK_A1
SMDCLK_A1#

N33

SMDCLK_A2

N34

SMDCLK_A2#
SMDCLK_A3

SMDCLK_A3#
SMDCLK_A4

SMDCLK_A4#

P31

SMDCLK_A5

P32

SMDCLK_A5#

SMXRCOMP
SMXCOMPVOH

AL9

SMXCOMPVOL

E34

SMVREF_A

VCC_DDR

VCC_DDR

E35

AA35

R35

VCC_DDR

VCC_DDR

VCC_DDR

AR15

AR21

AL6

VCC_DDR

VCC_DDR

VCC_DDR

AM1

AM2

AL7

VCC_DDR

VCC_DDR

AN8

AP3

C106 C0.47U16Y
C121 C0.22U16Y

VCC_DDR

C126 C10000P50Y5
C164 C0.22U16Y
C167 C0.1U25Y

VCC_DDR_C3
VCC_DDR_C2

values still need verification

XRCOMP

R155 42.2R1%
R171 42.2R1%

YRCOMP XCOMPH

R116 42.2R1%
R109 42.2R1%

7

VCC_DDR_C3

6

MDQ_A17

MDQ_A14

MDQ_A15

MDQ_A12

MDQ_A13

MDQ_A16

AL14

AN15

AP18

AM18

AP22

AM22

SDQ_A11

SDQ_A12

SDQ_A13

SDQ_A14

SDQ_A15

SDQ_A16

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

VCC_DDR

AR4

AR5

AP4

AP5

AP6

AP7

VCC_DDR VCC_DDR

AA35AA33

MDQ_A24

MDQ_A21

MDQ_A23

MDQ_A29

MDQ_A25

MDQ_A30

MDQ_A33

MDQ_A20

MDQ_A22

MDQ_A18

MDQ_A19

AL24

AN27

AP21

AL22

AP25

AP27

AP28

AP29

SDQ_A17

SDQ_A18

SDQ_A19

SDQ_A20

SDQ_A21

SDQ_A22

SDQ_A23

SDQ_A24

VCC_DDR

VCC_DDR

VCC_DDR

SDQ_B0

SDQ_B1

SDQ_B2

SDQ_B3

AR7

AR31

AJ10

AE15

AL11

AE16

AL8

MDQ_B2

MDQ_B0

MDQ_B3

MDQ_B4

MDQ_B1

XCOMPL YCOMPL

R168 31.6KR1%
R177 10.2KR1%

R145 10.2KR1%
R144 31.6KR1%

6

MDQ_A27

MDQ_A26

AP33

AM33

SDQ_A25

SDQ_A26

SDQ_A27

SDQ_B4

SDQ_B5

SDQ_B6

AF12

AK11

MDQ_B5

MDQ_B6

MDQ_A28

AM28

AN29

SDQ_A28

SDQ_A29

SDQ_B7

SDQ_B8

AG12

AE17

MDQ_B8

MDQ_B7

MDQ_A31

AM31

AN34

SDQ_A30

SDQ_A31

SDQ_B9

SDQ_B10

AL13

AK17

MDQ_B9

MDQ_B10

MDQ_A32

MDQ_A34

AH32

AG34

AF32

SDQ_A32

SDQ_A33

SDQ_B11

SDQ_B12

AL17

AK13

AJ14

MDQ_B11

MDQ_B12

MDQ_B13

MDQ_A36

MDQ_A35

AD32

AH31

SDQ_A34

SDQ_A35

SDQ_B13

SDQ_B14

AJ16

AJ18

MDQ_B15

MDQ_B14

VCC_DDR

MDQ_A37

MDQ_A38

AG33

AE34

SDQ_A36

SDQ_A37

SDQ_A38

SDQ_B15

SDQ_B16

SDQ_B17

AE19

AE20

MDQ_B17

MDQ_B16

MDQ_A40

MDQ_A39

MDQ_A41

AD34

AC34

AB31

SDQ_A39

SDQ_A40

SDQ_B18

SDQ_B19

AG23

AK23

AL19

MDQ_B20

MDQ_B18

MDQ_B19

YCOMPH

5

MDQ_A43

MDQ_A42

V32

V31

SDQ_A41

SDQ_A42

SDQ_A43

SDQ_B20

SDQ_B21

SDQ_B22

AK21

AJ24

MDQ_B22

MDQ_B21

R33

5

MDQ_A45

MDQ_A46

MDQ_A44

AD31

AB32

U34

SDQ_A44

SDQ_A45

SDQ_B23

SDQ_B24

AE22

AK25

AH26

MDQ_B23

MDQ_B24

MDQ_B25

MDQ_A47

U33

SDQ_A46

SDQ_B25

AG27

MDQ_B26

MDQ_A49

MDQ_A52

MDQ_A48

MDQ_A53

MDQ_A51

MDQ_A50

T34

T32

K34

K32

T31

P34

SDQ_A47

SDQ_A48

SDQ_A49

SDQ_A50

SDQ_A51

SDQ_A52

SDQ_B26

SDQ_B27

SDQ_B28

SDQ_B29

SDQ_B30

SDQ_B31

AF27

AJ26

AJ27

AD25

AF28

AE30

MDQ_B31

MDQ_B27

MDQ_B30

MDQ_B28

MDQ_B29

MDQ_B32

R102 31.6KR1%
R100 10.2KR1%

R108 10.2KR1%
R101 31.6KR1%

MDQ_A55

MDQ_A54

L34

L33

SDQ_A53

SDQ_A54

SDQ_A55

SDQ_B32

SDQ_B33

SDQ_B34

AC27

AC30

MDQ_B33

MDQ_B34

MDQ_A57

MDQ_A56

MDQ_A58

J33

H34

E33

SDQ_A56

SDQ_A57

SDQ_B35

SDQ_B36

Y29

AE31

AB29

MDQ_B35

MDQ_B37

MDQ_B36

VCC_DDR_C2

MDQ_A59

MDQ_A60

F33

K31

SDQ_A58

SDQ_A59

SDQ_A60

SDQ_B37

SDQ_B38

SDQ_B39

AA26

AA27

MDQ_B38

MDQ_B39

R35

MDQ_A61

MDQ_A62

J34

G34

SDQ_A61

SDQ_B40

AA30

W30

MDQ_B40

MDQ_B41

4

MDQ_A63

F34

SDQ_A62

SDQ_A63

SDQ_B41

SDQ_B42

SDQ_B43

U27

T25

MDQ_B43

MDQ_B42

4

MCKE_A1

MCKE_A0

AL20

AN19

AM20

SCKE_A0

SCKE_A1

SDQ_B44

SDQ_B45

AA31

V29

U25

MDQ_B44

MDQ_B45

MDQ_B46

AP20

SCKE_A2

SCKE_A3

SDQ_B46

SDQ_B47

SDQ_B48

R27

P29

MDQ_B47

MDQ_B48

AC26

AB25

AC25

VCCA_DDR

VCCA_DDR

VCCA_DDR

SDQ_B49

SDQ_B50

SDQ_B51

R30

K28

L30

MDQ_B51

MDQ_B49

MDQ_B50

VCCA_DDR

AN4

AL35

VCC_DDR

VCCA_DDR

SDQ_B52

SDQ_B53

SDQ_B54

R31

R26

P25

MDQ_B53

MDQ_B52

MDQ_B54

C0.1U25Y

C0.1U25YC133

AM3

AN5

AM5

VCC_DDR

VCC_DDR

SDQ_B55

SDQ_B56

L32

K30

H29

MDQ_B55

MDQ_B56

MDQ_B57

VCCA_DDR

AM6

AM7

AM8

VCC_DDR

VCC_DDR

VCC_DDR

SDQ_B57

SDQ_B58

SDQ_B59

F32

G33

N25

MDQ_B59

MDQ_B58

MDQ_B60

C153

VCC_DDR

AN2

AN6

AN7

VCC_DDR

VCC_DDR

VCC_DDR

SDQ_B60

SDQ_B61

SDQ_B62

M25

J29

G32

MDQ_B63

MDQ_B62

MDQ_B61

3

N35

N32

VSS

VSS

VCC_DDR

SDQ_B63

SCKE_B0

SCKE_B1

AK19

AF19

MCKE_B0

MCKE_B1

VCCA_DDR

CP9 X

3

P3P6P8

SCS_B0#

VSS

VSS

VSS

SCS_B1#
SCS_B2#
SCS_B3#

SRAS_B#
SCAS_B#

SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8

SMAA_B9
SMAA_B10
SMAA_B11
SMAA_B12

SMAB_B1

SMAB_B2

SMAB_B3

SMAB_B4

SMAB_B5

SDQS_B0

SDQS_B1

SDQS_B2

SDQS_B3

SDQS_B4

SDQS_B5

SDQS_B6

SDQS_B7

SCMDCLK_B0

SCMDCLK_B0#

SCMDCLK_B1

SCMDCLK_B1#

SCMDCLK_B2

SCMDCLK_B2#

SCMDCLK_B3

SCMDCLK_B3#

SCMDCLK_B4

SCMDCLK_B4#

SCMDCLK_B5

SCMDCLK_B5#

SMYRCOMP

SMYCOMPVOH
SMYCOMPVOL

SMVREF_B

SCKE_B2

SCKE_B3

RG82865PE-A2

AG19

AE18

{Priority}

Its current is 5.1A.

U26
T29
V25
W25

W26
W31

W27

SWE_B#

AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20

AE27
AD26
AL29
AL27
AE23

Y25

SBA_B0

AA25

SBA_B1

AG11

SDM_B0

AG15

SDM_B1

AE21

SDM_B2

AJ28

SDM_B3

AC31

SDM_B4

U31

SDM_B5

M29

SDM_B6

J31

SDM_B7

AF15
AG13
AG21
AH27
AD29
U30
L27
J30

AG29
AG30

AF17
AG17

N27
N26

AJ30
AH29

AK15
AL15

N31
N30

AA33
R34

R33
AP9

MCKE_B[0..1] 11MDQ_B[0..63]11

Solder side.

CB10 X_C1U16Y0805
CB11 X_C1U16Y0805

2

MCS_B#0 11
MCS_B#1 11

MRAS_B# 11
MCAS_B# 11

MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12

MWE_B# 11

MA_B[0..12] 11

VCC_DDR

CB3 X_C1U16Y0805
CB7 X_C1U16Y0805
CB6 X_C1U16Y0805

MBA_B0 11
MBA_B1 11

MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7

MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7

YRCOMP
YCOMPH

YCOMPL

MDQM_B[0..7] 11

MDQS_B[0..7] 11

MCLK_B0 11
MCLK_B#0 11

MCLK_B1 11
MCLK_B#1 11

MCLK_B2 11
MCLK_B#2 11

C10000P50Y5C122
C10000P50Y5C119

C10000P50Y5C105
C0.1U25YC176

YVREF

MSI

VCC_AGP

Title

Size Document Number Rev

Date: Sheet of

2

R156 150R1%
R173 150R1%
C205 X_C2.2U6.3Y

MICRO-STAR INt'L CO., LTD.

Intel Springdale - Memory Signals

MS-7097

VCC_DDR

1

100

9 29Wednesday, October 06, 2004

1