MSI MS-6756 Schematics
1
Cover Sheet 1
Block Diagram
GPIO
Intel mPGA478B CPU - Signals
2
3
4
5Intel mPGA478B CPU - Power
Intel Springdale - Host Signals
Intel Springdale - Memory Signals
Intel Springdale - AGP & LAN Signals
DDR DIMM 1,2
82547EI/82562EX-1
82547EI/82562EX-2
Intel ICH5 - PCI & IDE & AC97 Signals
Intel ICH5 - Other Signals
A A
CY28404 & FWH & FDD
6
7
8
9
10
11
12
13
14
15LPC I/O -W83627HF
AC97 Audio
AGP 4X/8X Slot
PCI Slots 1 & 2 & 3
ATA33/66/100 IDE & Video Connectors
USB Connectors
16
17
18
19
20
21W83302 ACPI controller
ATX & Front Panel
22
MS(6756)
Intel (R) Springdale (GMCH) + ICH5 Chipset
Intel Northwood & Prescott mPGA478B Processor
CPU:
Intel Northwood/Prescott
System Chipset:
Intel Springdale - GMCH (North Bridge)
Intel ICH5 (South Bridge)
On Board Chipset:
BIOS -- FWH EEPROM
AC'97 Codec -- ALC202A/ALC650
LPC Super I/O -- W83627SF
LAN --82547EI/83562EX
CLOCK -- Cypress CY28404
Main Memory:
DDR * 2 (Max 2GB)
Expansion Slots:
PCI2.3 SLOT * 3
Intersil PWM:
Controller: Intersil 6556B
Driver: Intersil 6601B,6602B
Version 0A
VRM 10
ADM1027 FAN Control
Manual Part
23
24
25
MICRO-STAR INt'L CO., LTD.
MSI
Title
Size Document Number Rev
Date: Sheet
1
星期五, 一月
10, 2003
COVER SHEET
MS-6756
125
0A
of
8
D D
7
6
5
4
3
2
1
Jumper Setting & Connector Setting
PCB
Q7-Q11
Q15-Q16
Q20-Q21
P01-675600A-D05
BAT1_X
BAT-B-CR2032-P-3V-220mAh
C C
B B
JBAT1(1-2)
JC-D2-GN
JAUD1(5-6)
JC-D2-GN
BIOS-1
JC-D2-GN
JAUD1(3-4)
JC-D2-GN
_
K-R+1 60.4
5
6
7
8
1
2
3
4
_
U900
5
6
7
UP
8
1
2
3
DOWN
4
LTP1_A
9
10
11
12
D2x5-1:2-YL
_
1011
1
6
2
7
3
8
4
9
5
COM-D9-GN
9
10
11
12
U9-HS
U20_1
SST-512K*8-33MHz-PLCC32
_
U5_1
JMCH1
_
D1x3-BK
JMCH2
D1x3-BK
K-R+2 60.4
A A
Title
Manual Part
Size Document Number Rev
MS-6756 0A
Custom
Date: Sheet
星期一, 一月
8
7
6
5
4
3
2
13, 2003
of
126
1
1
VRM 10
Intersil 6556
Intel mPAG478B Processor
Block Diagram
3-Phase PWM
FSB
AGP 1.5V
4X/8X
Connector
Analog
Video
Out
Kenai II
/
Kinnereth R
IDE Primary
CSA
LCI
UltraDMA 33/66/100
Springdale
64bit DDR
Channel 1
64bit DDR
Channel 2
HUB
Link
2 DDR
DIMM
Modules
(1+1)
PCI CNTRL
PCI Slot 1
PCI Slot 2
PCI Slot 3
IDE Secondary
ICH5
A A
USB Port 0
PCI ADDR/DATA
USB Port 1
USB Port 2
USB
LPC Bus
USB Port 3
USB Port 4
LPC SIO
USB Port 5
Winbond
83627HF
USB Port 6
USB Port 7
ALC202A
AC'97 Codec
Serial ATA 0
Serial ATA 1
AC'97 Link
Serial ATA
Flash
Keyboard
Mouse
Floopy Parallel Serial
1
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
BLOCK DIAGRAM
10, 2003
MS-6756
星期五, 一月
225
of
0A
1
ICH5
FunctionTypeGPIO Pin
I
GPIO 0
GPIO 1
GPIO 2
GPIO 3
GPIO 4
GPIO 5
GPIO 6
GPIO 7
GPIO 8
GPIO 9
GPIO 10
GPIO 11
GPIO 12
GPIO 13
GPIO 14
GPIO 15
GPIO 16
GPIO 17
GPIO 18
GPIO 19
GPIO 20
GPIO 21
GPIO 22 GPO22
GPIO 23
PREQ#B
I
PREQ#B
I
PIRQ#E
I
PIRQ#F
I
PIRQ#G
PIRQ#H
I
I
GPI6
I
GPI7
I
CSA_PME#
I
OC4#
I
OC5#
I
SIO_SMI#
I
LAN_WAKE#
I
SIO_PME#
I OC#6
OC#7
I
PGNT#A
O
PGNT#B
O
O GPO18
O
BIOS_WP#
O
GPO20
O GPO21
OD
O
GPO23
GPIO 24 I/O GPIO24
GPIO 25 I/O
A A
*
GPIO 27
GPIO 28
GPIO 32
GPIO 33
GPIO 34
GPIO 40 PREQ#4
GPIO 41
GPIO 48
GPIO 49
LAN_DISABLE#
GPIO27
I/O
I/O GPIO28
GPIO32
I/O
GPIO33
I/O
GPIO34
I/O
I
I
GPI41
O PGNT#4
OD
CPUPWRGD
Power well
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
RESUME
RESUME
RESUME
RESUME
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
default output
default output
default output
default output
default output
default output
default output
PCI Config.
DEVICE
INTA#
INTB#
PCI_REQ#0PCI Slot 1
PCI_GNT#0
INTC#
INTD#
PCI Slot 2
INTB#
INTC#
PCI_REQ#1 AD17 PCICLK1
PCI_GNT#1
INTD#
INTA#
PCI Slot 3 PCI_REQ#2 AD18
INTC#
INTD#
PCI_GNT#2
INTA#
INTB#
IDSEL
AD16
DDR DIMM Config.
DEVICE
DIMM 1 MCLK_A0/MCLK_A0#
DIMM 2
1010000B
1010001B
CLOCKADDRESS
MCLK_A1/MCLK_A1#
MCLK_A2/MCLK_A2#
MCLK_B0/MCLK_B0#
MCLK_B1/MCLK_B1#
MCLK_B2/MCLK_B2#
PCI RESET DEVICE
Signals
PCIRST#1
HD_RST#
Springdale,LAN,FWH, Super I/O
PCI slot 1-3, AGP slotPCIRST#2
Primary, Scondary IDE
Target
CLOCKREQ#/GNT#
PCICLK0
PCICLK2
CLK GEN PIN OUTMCP1 INT Pin
13 (PCI_CLK0)
14 (PCI_CLK1)
15 (PCI_CLK2)
FWH
TypeGPIO Pin
GPI 0 PD_DET
GPI 1
*
GPI 3
*
Function
I
I
SD_DET
Pull down through 1K ohms (unused)GPI 2
I
Pull down through 1K ohms (unused)
I
Pull down through 1K ohms (unused)GPI 4
I
MSI
Title
Size Document Number Rev
1
Date: Sheet
MICRO-STAR INt'L CO., LTD.
General Purpose Spec
10, 2003
MS-6756
星期五, 一月
0A
of
325
8
7
6
5
4
3
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1
CPU SIGNAL BLOCK
HA#[3..31]6
HA#17
A18#
D33#
M23
HA#16
A17#
D32#
H25
HA#15
A16#
D31#
A15#
D30#
K23
HA#14
A14#
D29#
J24
HA#12
HA#13
A13#
D28#
L22
M21
HA#11
A12#
D27#
H24
HA#25
HA#27
HA#30
HA#26
HA#29
HA#31
A35#
D50#
HA#28
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
U24
U26
T23
T22
T25
T26
R24
R25
P24
R21
D D
CPU1A
HDBI#[0..3]6
FERR#13
STPCLK#13
HINIT#13,14
HDBSY#6
HDRDY#6
HTRDY#6
HADS#6
HLOCK#6
HBNR#6
HITM#6
HBPRI#6
C C
B B
HDEFER#6
CPU_TMPA25
VTIN_GND25
TRMTRIP#13
PROCHOT#6
IGNNE#13
A20M#13
BOOT24
BSEL014
BSEL114
CPU_GD13
CPURST#6
HD#[0..63]6
HDBI#0
HDBI#1
HDBI#2
HDBI#3
HIT#6
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
PROCHOT#
SMI#13
SLP#13
BOOT
CPU_GD
CPURST#
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
E21
DBI0#
G25
DBI1#
P26
DBI2#
V21
DBI3#
AC3
IERR#
V6
MCERR#
B6
FERR#
Y4
STPCLK#
AA3
BINIT#
W5
INIT#
AB2
RSP#
H5
DBSY#
H2
DRDY#
J6
TRDY#
G1
ADS#
G4
LOCK#
G2
BNR#
F3
HIT#
E3
HITM#
D2
BPRI#
E2
DEFER#
C1
TDI
D5
TDO
F7
TMS
E6
TRST#
D4
TCK
B3
THERMDA
C4
THERMDC
A2
THERMTRIP#
AF26
GND/SKTOCC#
C3
PROCHOT#
B2
IGNNE#
B5
SMI#
C6
A20M#
AB26
SLP#
A22
RESERVED0
A7
RESERVED1
AE21
RESERVED2
AF24
RESERVED3
AF25
RESERVED4
AD1
BOOTSELECT
AE26
OPTIMIZED/COMPAT#
AD6
BSEL0
AD5
BSEL1
AB23
PWRGOOD
AB25
RESET#
AA24
D63#
AA22
D62#
AA25
D61#
Y21
D60#
Y24
D59#
Y23
D58#
W25
D57#
Y26
D56#
W26
D55#
V24
D54#
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
D53#
D52#
D51#
V22
U21
V25
U23
HA#24
A25#
D40#
N25
HA#23
A24#
D39#
N26
HA#22
A23#
D38#
M26
HA#21
A22#
D37#
N23
HA#20
A21#
D36#
M24
HA#19
A20#
D35#
P21
HA#18
A19#
D34#
N22
HA#10
A11#
D26#
G26
A10#
D25#
HA#9
L21
A9#
D24#
HA#8
D26
A8#
D23#
HA#7
F26
A7#
D22#
HA#6
E25
HA#5
A6#
D21#
HA#4
HA#3
AE25A5A4
AD26
A5#
A4#
A3#
DBR#
VSS_SENSE
VCC_SENSE
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
F24
F23
G23
E24
H22
D25
J21
D23
C26
H21
G22
AC26
ITP_CLK1
ITP_CLK0
D10#
D9#
D8#
B25
C24
AD2
C23
VID2
VID4
VID3
VID5
AE1
AE2
AE3
AD3
VID5#
VID4#
VID3#
VID2#
VIDPWRGD
D7#
D6#
D5#
D4#
D3#
B24
D22
C21
A25
VID1
VID0
AE4
AE5
VID1#
VID0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
COMP1
COMP0
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D2#
D1#
D0#
PGA-S478-GD10-F02
A23
B22
B21
CRITICAL
VCC_SENSE 24
VSS_SENSE 24
VID_GD 21,24
VID[0..5] 24
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
DP3#
DP2#
DP1#
DP0#
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
BPM#5
BPM#4
BPM#3
BPM#2
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI2
TESTHI1
TESTHI0
HRS#2
HRS#1
HRS#0
HBR#0
COMP1
COMP0
C116 220p
VIDPWRGD DC Specifications
GTLREF 6
HREQ#[0..4] 6
VCCP
CPU_CLK# 14
CPU_CLK 14
HRS#[0..2] 6
HBR#0 6
HADSTB#1 6
HADSTB#0 6
HDSTBP#3 6
HDSTBP#2 6
HDSTBP#1 6
HDSTBP#0 6
HDSTBN#3 6
HDSTBN#2 6
HDSTBN#1 6
HDSTBN#0 6
NMI 13
INTR 13
Min MaxTyp
0.9
0.3
VIL
VIH
It must rout to the enable pin of PWM and CK-409.
VIDGD to Vccp delay time is from 1ms to 10ms.
VIDGD rising time is 150ns.
X7R
16V
R69 62
R137 62
R93 62
R97 62
R102 62 R92 680
R87 62
R78 62
R106 61.9
R109 61.9
CPU GTL REFERNCE VOLTAGE BLOCK
GTLREF
X7R X7R
C147
0.1u
16V
0.63*Vccp
C197
0.1u
CPU ITP BLOCK
ITP_TDI
ITP_TRST#
ITP_TMS
ITP_TDO
ITP_TCK
R76 150
R104 39
R77 75
R81 27R82 62
R142
200
R153
169
VCCP
VCCP
VTTVCCP
R189
200
HD#1
HD#6
HD#4
HD#3
HD#5
HD#7
HD#8
HD#52
HD#53
HD#50
HD#51
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#40
HD#41
HD#38
HD#39
HD#36
HD#37
HD#35
HD#34
HD#33
HD#32
HD#31
HD#30
HD#29
HD#27
HD#28
HD#26
HD#25
HD#23
HD#24
HD#22
HD#21
HD#20
HD#19
HD#17
HD#18
HD#16
HD#15
HD#14
HD#13
HD#12
HD#11
HD#9
HD#10
HD#2
HD#0
CPU STRAPPING RESISTORS
A A
8
7
BPM#4
R91 62
BPM#5
R83 62
BPM#2 CPU_GD
R80 62
BPM#3
R95 62
BPM#1
R89 62
BPM#0
R85 62
VCCP
6
ALL COMPONENTS CLOSE TO CPU
5
PROCHOT#
HBR#0
CPURST#
R140 62
R75 300
R101 220
R86 62
VCCP
MSI
Title
Size Document Number Rev
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel mPGA478B - Signals
13, 2003
MS-6756
星期一, 一月
2
425
1
0A
of
8
7
6
5
4
3
2
1
D15
D17
VCC
VCC
VSS
VSS
E7E9F10
D19D7D9
VCC
VSS
F12
VCC
VSS
F14
E10
VCC
VSS
F16
VCC_VID
E12
VCC
VCC
VSS
VSS
F18F2F22
C33
1u
E14
E16
E18
VCC
VCC
VCC
VSS
VSS
VSS
F25F5F8
VCC_VID21
CPU VOLTAGE BLOCK
VID Voltage is from 1.14V to 1.32V.
It is derived from 3.3V.
It should be able to source 150mA.
D D
VCCP
A10
A12
A14
A16
A18
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
CPU1B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
B23
VSS
B26B4B8
VSS
VSS
VSS
VCC
VSS
VSS
C11
C13
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
AA1
VSS
AA11
VSS
AA13
VSS
AA15
VSS
AA17
VSS
AA19
VSS
AA23
C C
B B
AA26
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AC22
AC25
AA4
AA7
AA9
AB3
AB6
AB8
AC2
AC5
AC7
AC9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10
VSS
AD12
VSS
AD14
VSS
AD16
VSS
AD18
VSS
AD21
VSS
AD23
AD4
VSS
AD8
VSS
AE11
VSS
VSS
AE13
AE15
VSS
VSS
AE17
VSS
AE19
VSS
AE22
VSS
AE24
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
AF19
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
C15
C17C2C19
C22
C25C5C7C9D12
It drives the power logic of BSEL[1:0] and VID[5:0].
VID to VIDGD delay time is from 1ms to 10ms.
VID to VIDGD deassertion time is 1ms for max.
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D14
D16
D18
D20
D21D3D24D6D8E1E11
VCC
VSS
C10
C12
C14
C16
C18
C20C8D11
D13
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E13
E15
E17
E19
E23
E4
E26
E20E8F11
VCC
VCC
VSS
VSS
Near processor
F13
F15
VCC
VCC
VCC
VSS
VSS
VSS
G21G6G24
G3H1H23
1.2V 150mA
C41
0.1u
F17
F19
F9
VCC
VCC
VCC
VSS
VSS
VSS
H26H4J2
VSS
AF4
VCC-VID
VSS
AF3
VSS
J22
AD20
VCC-VIDPRG
VSS
VSS
J25J5K21
AE23
VCCA
VSSA
VCC-IOPLL
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PGA-S478-GD10-F02
CRITICAL
AD22
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24
C42
X_1u
X_1u
It support DC current if 100mA.
CPU_IOPLL
C46
C43
22u-1206
10V
VSSA
The ESL is less than 5nH, and the ESR is less than 0.3ohm.
L2 10u
L3 10u
C38
X_10u-1206
10V
DC voltage drop should
be less than 70mV.
VCCP
CPU DECOUPLING CAPACITORS
VCCP
A A
Place these caps within socket cavity Place these caps within south side of processor
VCCP VCCP VCCP VCCPVCCP VCCP
C93
10u-1206
C89
10u-1206
C85
10u-1206
C77
10u-1206
C72
10u-1206
C67
10u-1206
C94
10u-1206
C90
10u-1206
C86
10u-1206
C78
10u-1206
C73
10u-1206
C68
10u-1206
C24
10u-1206
C12
X_10u-1206
C21
X_10u-1206
C29
10u-1206
C16
X_10u-1206
C8
X_10u-1206
C23
10u-1206
C13
X_10u-1206
C15
X_10u-1206
C27
10u-1206
C10
X_10u-1206
C25
10u-1206
Place these caps within north side of processor
8
7
6
C22
X_10u-1206
C14
X_10u-1206
C11
X_10u-1206
C26
10u-1206
C28
10u-1206
C9
X_10u-1206
C118
X_10u-1206
C119
X_10u-1206
C120
X_10u-1206
C121
X_10u-1206
C122
X_10u-1206
5
C117
X_10u-1206
MSI
Title
Size Document Number Rev
4
3
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel mPGA478B - Power
13, 2003
MS-6756
星期一, 一月
2
525
1
0A
of
8
VCCA_FSB
C143 0.1u
VCCA_DPLL
AE14
D26
D30
C30
C31
D34
C32
C34
G27
H27
G30
G26
D28
C29
D24
G24
G22
C27
AK4
C25
L23
E29
B32
K23
J25
B31
E30
B33
J24
F25
F28
J27
F29
E28
K24
E32
F31
J26
B30
B24
B26
B28
E25
F27
B29
J23
L22
J21
K21
E23
L21
E27
B27
B7
C7
E8
AJ8
L20
L13
L12
E24
F23
U10A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
HAD_STB0#
HAD_STB1#
BREQ0#
BPRI#
BNR#
HLOCK#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HIT#
HITM#
DEFER#
HTRDY#
DBSY#
DRDY#
RS0#
RS1#
RS2#
HCLKP
HCLKN
PWROK
CPURST#
RSTIN#
ICH_SYNC#
PROCHOT#
BSEL0
BSEL1
HDRCOMP
HDSWING
HDVREF
HA#[3..31]4
D D
HADSTB#04
HADSTB#14
HBR#04
C C
HBPRI#4
HBNR#4
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HLOCK#4
HADS#4
HREQ#[0..4]4
HIT#4
HITM#4
HDEFER#4
HTRDY#4
HDBSY#4
HDRDY#4
HRS#[0..2]4
MCH_CLK14
MCH_CLK#14
CPURST#4
B B
PCIRST#110,15,21
PROCHOT#4
BSEL0_SPG14
BSEL1_SPG14
R162 20
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
MS5_POK
ICH_SYNC#
HRCOMP
HSWING
GTLREF4
7
B3
A31
B4
VCCA_FSB
VCCA_DPLL
VSS
VSS
C12
C10
C8
VCCA_FSB
VSS
C14
VCC_AGP
J6J7J8J9K6K7K8K9L6L7L9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C16
C18
C20
C22
C24
C26
C28D1D11
D9
VCC
VSS
VCC
VSS
6
N11N9P10
P11
R11
T16
T17
T18
T19
U16
U17
U20
V16
V18
V20
W16
N10
M10
M11M8M9
L10
L11
VCC
VCC
VCC
VCC
VCC
VSS
VSS
D13
D15
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D17
D19
D21
D23
D25
D27
D29
D31
D33
T20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
D35
F3F5F8
E3
F1
E1
F10
W19
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
F18
F20
F22
F24
F14
F16
F12
VCC
VSS
W20
F26
VCC
VSS
5
Y16
Y17
Y18
Y19
Y20
A3
A33
A35B2B25
B34C1C23
C35
E26
M31
AF13
AF23
AJ12
R25
NCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
G31
G35
G28
VSS
VSS
VSS
H12
H14
H16H2H20
H5
H18
H8
H9
VSS
NC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
H22
H24
H26
H30
H33
J10
J12
J14
J16
AN1
J18
VSS
4
VTT
AP2
AR3
AR33
AR35
A7A9A11
A13
A16
A20
A23
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
J20
J22
J28
J32
J35
K11
K12
K14
K16
K18
K20
K22
D5D6D7E6E7
A25
A27
A29
A32
C4
VTT
VTT
VSS
VSS
VSS
VSS
K25
K27
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
K33
K29
L24
L25
L26
L35
L31
VTT
VSS
M3M6M26
VTT
VSS
F7
VTT
VSS
3
A4A5A6B5B6C5C6
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
M27
M28
M30
M33N1N4
VTT
VTT
HD_STBP0#
HD_STBN0#
HD_STBP1#
HD_STBN1#
HD_STBP2#
HD_STBN2#
HD_STBP3#
HD_STBN3#
VSS
SpringDale
CRITICAL
VTT_FSB1
VTT_FSB2
A15
A21
HD0#
HD1#
HD2#
HD3#
VTT_FSB
VTT_FSB
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
DINV_0#
DINV_1#
DINV_2#
DINV_3#
C179 0.47u
C165 0.47u
B23
E22
B21
D20
B22
D22
B20
C21
E18
E20
B16
D16
B18
B17
E16
D18
G20
F17
E19
F19
J17
L18
G16
G18
F21
F15
E15
E21
J19
G14
E17
K17
J15
L16
J13
F13
F11
E13
K15
G12
G10
L15
E11
K13
J11
H10
G8
E9
B13
E14
B14
B12
B15
D14
C13
B11
D10
C11
E10
B10
C9
B9
D8
B8
C17
L17
L14
C15
B19
C19
L19
K19
G9
F9
D12
E12
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HDBI#0
HDBI#1
HDBI#2
HDBI#3
2
HD#[0..63] 4
HDBI#[0..3] 4
HDSTBP#0 4
HDSTBN#0 4
HDSTBP#1 4
HDSTBN#1 4
HDSTBP#2 4
HDSTBN#2 4
HDSTBP#3 4
HDSTBN#3 4
1
VCC3
VCCP
A A
X7R
C191
0.01u
HSWING
C149
0.01u
X7R
16V
8
1/4*Vccp
R186
301
R150
100
7
0.1u
VCCA_FSB
I=35mA
VCCA_DPLL
C208
C205
0.1u
ESR is 0.1mohm to GMCH
EC26
100u
6
+
EC24
100u
L7 100nH
+
FSB
DPLL
R198 0L5 0.82u
R200 1
VCC_AGP
VCC_AGP
5
I=30mA
ICH_SYNC# MS5_POK ICH_PWROK
0
10
00
1
111
0
0
0
MS5_POK10,21
4
ICH_SYNC#
MS5_POK
VCC3
Q45 X_2N3904S
Q47 X_2N3904S
R383 X_220
R331 0
R333
3
X_220
R332
X_1K
ICH_PWROK 13
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Springdale - CPU Signals
13, 2003
MS-6756
星期一, 一月
2
625
of
1
0A
8
MCS_A#09
MCS_A#19
D D
MRAS_A#9
MCAS_A#9
MWE_A#9
MA_A[0..12]9
MBA_A09
MBA_A19
C C
MDQM_A[0..7]9
MDQS_A[0..7]9
MCLK_A09
MCLK_A#09
MCLK_A19
MCLK_A#19
MCLK_A29
MCLK_A#29
B B
0.01uC269
0.01uC263
0.01uC270
0.1uC136
C135 2.2u
MDQ_A[0..63]9 MCKE_A[0..1] 9
U10B
AA34
SCS_A0#
Y31
SCS_A1#
Y32
SCS_A2#
W34
SCS_A3#
AC33
SRAS_A#
Y34
SCAS_A#
AB34
SWE_A#
MA_A0
AJ34
AL33
AK29
AN31
AL30
AL26
AL28
AN25
AP26
AP24
AJ33
AN23
AN21
AL34
AM34
AP32
AP31
AM26
AE33
AH34
AP12
AP16
AM24
AP30
AF31
W33
M34
H32
AN11
AP15
AP23
AM30
AF34
M32
H31
AK32
AK31
AP17
AN17
N33
N34
AK33
AK34
AM16
AL16
AK9
AN9
V34
P31
P32
AL9
E34
SMAA_A0
SMAA_A1
SMAA_A2
SMAA_A3
SMAA_A4
SMAA_A5
SMAA_A6
SMAA_A7
SMAA_A8
SMAA_A9
SMAA_A10
SMAA_A11
SMAA_A12
SMAB_A1
SMAB_A2
SMAB_A3
SMAB_A4
SMAB_A5
SBA_A0
SBA_A1
SDM_A0
SDM_A1
SDM_A2
SDM_A3
SDM_A4
SDM_A5
SDM_A6
SDM_A7
SDQS_A0
SDQS_A1
SDQS_A2
SDQS_A3
SDQS_A4
SDQS_A5
SDQS_A6
SDQS_A7
SMDCLK_A0
SMDCLK_A0#
SMDCLK_A1
SMDCLK_A1#
SMDCLK_A2
SMDCLK_A2#
SMDCLK_A3
SMDCLK_A3#
SMDCLK_A4
SMDCLK_A4#
SMDCLK_A5
SMDCLK_A5#
SMXRCOMP
SMXCOMPVOH
SMXCOMPVOL
SMVREF_A
MA_A1
MA_A2
MA_A3
MA_A4
MA_A5
MA_A6
MA_A7
MA_A8
MA_A9
MA_A10
MA_A11
MA_A12
MDQM_A0
MDQM_A1
MDQM_A2
MDQM_A3
MDQM_A4
MDQM_A5
MDQM_A6
MDQM_A7
MDQS_A0
MDQS_A1
MDQS_A2
MDQS_A3
MDQS_A4
MDQS_A5
MDQS_A6
MDQS_A7
XRCOMP
XCOMPH
XCOMPL
XVREF
C144 0.47u
C162 0.22u
C170 0.01u
C234 0.22u
MDQ_A1
MDQ_A0
AP10
AP11
SDQ_A0
E35
7
MDQ_A4
MDQ_A2
MDQ_A3
AM12
AN13
SDQ_A1
SDQ_A2
SDQ_A3
VCC_DDR
VCC_DDR
VCC_DDR
AA35
R35
MDQ_A6
MDQ_A5
AM10
AL10
AL12
SDQ_A4
SDQ_A5
VCC_DDR
VCC_DDR
AR15
AR21
AL6
MDQ_A8
MDQ_A7
MDQ_A9
AP13
AP14
AM14
SDQ_A6
SDQ_A7
SDQ_A8
VCC_DDR
VCC_DDR
VCC_DDR
AM1
AM2
AL7
MDQ_A11
MDQ_A10
MDQ_A12
AL18
AP19
AL14
SDQ_A9
SDQ_A10
SDQ_A11
VCC_DDR
VCC_DDR
VCC_DDR
AN8
AP3
AP4
VCC_DDR
MDQ_B[0..63]9
MDQ_A14
MDQ_A15
MDQ_A13
AN15
AP18
AM18
SDQ_A12
SDQ_A13
SDQ_A14
VCC_DDR
VCC_DDR
VCC_DDR
AP5
AP6
AP7
MDQ_A16
MDQ_A17
MDQ_A18
AP22
AM22
AL24
SDQ_A15
SDQ_A16
SDQ_A17
VCC_DDR
VCC_DDR
VCC_DDR
AR4
AR5
AR7
MDQ_A20
MDQ_A21
MDQ_A19
AN27
AP21
AL22
SDQ_A18
SDQ_A19
SDQ_A20
VCC_DDR
VCC_DDR
AR31
AJ10
MDQ_B0
6
MDQ_A22
MDQ_A23
AP25
AP27
SDQ_A21
SDQ_A22
SDQ_A23
SDQ_B0
SDQ_B1
SDQ_B2
AE15
AL11
MDQ_B2
MDQ_B1
MDQ_A24
MDQ_A25
AP28
AP29
SDQ_A24
SDQ_A25
SDQ_B3
SDQ_B4
AE16
AL8
MDQ_B3
MDQ_B4
MDQ_A27
MDQ_A26
AP33
AM33
SDQ_A26
SDQ_B5
AF12
AK11
MDQ_B5
MDQ_B6
MDQ_A28
MDQ_A29
AM28
AN29
SDQ_A27
SDQ_A28
SDQ_A29
SDQ_B6
SDQ_B7
SDQ_B8
AG12
AE17
MDQ_B8
MDQ_B7
MDQ_A31
MDQ_A30
AM31
AN34
SDQ_A30
SDQ_A31
SDQ_B9
SDQ_B10
AL13
AK17
MDQ_B9
MDQ_B10
MDQ_A32
MDQ_A33
AH32
AG34
SDQ_A32
SDQ_A33
SDQ_B11
SDQ_B12
AL17
AK13
MDQ_B12
MDQ_B11
MDQ_A35
MDQ_A34
AF32
AD32
SDQ_A34
SDQ_A35
SDQ_B13
SDQ_B14
AJ14
AJ16
MDQ_B14
MDQ_B13
MDQ_A36
MDQ_A37
AH31
AG33
SDQ_A36
SDQ_A37
SDQ_B15
SDQ_B16
AJ18
AE19
MDQ_B15
MDQ_B16
MDQ_A39
MDQ_A38
AE34
AD34
SDQ_A38
SDQ_A39
SDQ_B17
SDQ_B18
AE20
AG23
MDQ_B18
MDQ_B17
MDQ_A41
MDQ_A40
AC34
AB31
SDQ_A40
SDQ_A41
SDQ_B19
SDQ_B20
AK23
AL19
MDQ_B19
MDQ_B20
MDQ_A43
MDQ_A42
V32
V31
SDQ_A42
SDQ_A43
SDQ_B21
SDQ_B22
AK21
AJ24
MDQ_B21
MDQ_B22
MDQ_A44
MDQ_A45
AD31
AB32
SDQ_A44
SDQ_A45
SDQ_B23
SDQ_B24
AE22
AK25
MDQ_B23
MDQ_B24
5
MDQ_A46
MDQ_A47
U34
U33
SDQ_A46
SDQ_A47
SDQ_B25
SDQ_B26
AH26
AG27
MDQ_B26
MDQ_B25
MDQ_A48
MDQ_A49
T34
T32
SDQ_A48
SDQ_A49
SDQ_B27
SDQ_B28
AF27
AJ26
MDQ_B28
MDQ_B27
MDQ_A51
MDQ_A50
K34
K32
SDQ_A50
SDQ_A51
SDQ_B29
SDQ_B30
AJ27
AD25
MDQ_B30
MDQ_B29
MDQ_A53
MDQ_A52
T31
P34
SDQ_A52
SDQ_A53
SDQ_B31
SDQ_B32
AF28
AE30
MDQ_B31
MDQ_B32
MDQ_A54
MDQ_A55
L34
L33
SDQ_A54
SDQ_A55
SDQ_B33
SDQ_B34
AC27
AC30
MDQ_B34
MDQ_B33
MDQ_A56
MDQ_A57
J33
H34
SDQ_A56
SDQ_A57
SDQ_B35
SDQ_B36
Y29
AE31
MDQ_B36
MDQ_B35
MDQ_A58
MDQ_A59
E33
F33
SDQ_A58
SDQ_A59
SDQ_B37
SDQ_B38
AB29
AA26
MDQ_B38
MDQ_B37
MDQ_A60
MDQ_A61
K31
J34
SDQ_A60
SDQ_B39
AA27
AA30
MDQ_B40
MDQ_B39
MDQ_A62
MDQ_A63
G34
F34
SDQ_A61
SDQ_A62
SDQ_A63
SDQ_B40
SDQ_B41
SDQ_B42
W30
U27
MDQ_B41
MDQ_B43
MDQ_B42
MCKE_A0
MCKE_A1
AL20
SCKE_A0
SDQ_B43
SDQ_B44
T25
AA31
MDQ_B44
MDQ_B45
AN19
AM20
SCKE_A1
SCKE_A2
SDQ_B45
SDQ_B46
V29
U25
MDQ_B47
MDQ_B46
4
AP20
AB25
SCKE_A3
SDQ_B47
SDQ_B48
R27
P29
R30
MDQ_B49
MDQ_B48
AC26
AC25
AL35
VCCA_DDR
VCCA_DDR
VCCA_DDR
VCCA_DDR
SDQ_B49
SDQ_B50
SDQ_B51
SDQ_B52
K28
L30
R31
MDQ_B52
MDQ_B51
MDQ_B50
VCCA_DDR
AN4
AM3
VCC_DDR
VCC_DDR
SDQ_B53
SDQ_B54
SDQ_B55
R26
P25
L32
MDQ_B54
MDQ_B53
MDQ_B55
MDQ_B56
0.1uC200
AN5
AM5
AM6
VCC_DDR
VCC_DDR
SDQ_B56
SDQ_B57
K30
H29
F32
MDQ_B57
MDQ_B58
VCC_DDR
AM7
AM8
VCC_DDR
VCC_DDR
VCC_DDR
SDQ_B58
SDQ_B59
SDQ_B60
G33
N25
MDQ_B59
MDQ_B61
MDQ_B60
AN2
AN6
AN7
VCC_DDR
VCC_DDR
SDQ_B61
SDQ_B62
M25
J29
G32
MDQ_B63
MDQ_B62
N35
N32
VSS
VCC_DDR
SDQ_B63
SCKE_B0
AK19
AF19
MCKE_B0
MCKE_B1
3
P3P6P8
VSS
VSS
VSS
VSS
SMAA_B10
SMAA_B11
SMAA_B12
SCMDCLK_B0
SCMDCLK_B0#
SCMDCLK_B1
SCMDCLK_B1#
SCMDCLK_B2
SCMDCLK_B2#
SCMDCLK_B3
SCMDCLK_B3#
SCMDCLK_B4
SCMDCLK_B4#
SCMDCLK_B5
SCMDCLK_B5#
SMYRCOMP
SMYCOMPVOH
SMYCOMPVOL
SMVREF_B
SCKE_B1
SCKE_B2
SCKE_B3
SpringDale
AG19
AE18
CRITICAL
SCS_B0#
SCS_B1#
SCS_B2#
SCS_B3#
SRAS_B#
SCAS_B#
SWE_B#
SMAA_B0
SMAA_B1
SMAA_B2
SMAA_B3
SMAA_B4
SMAA_B5
SMAA_B6
SMAA_B7
SMAA_B8
SMAA_B9
SMAB_B1
SMAB_B2
SMAB_B3
SMAB_B4
SMAB_B5
SBA_B0
SBA_B1
SDM_B0
SDM_B1
SDM_B2
SDM_B3
SDM_B4
SDM_B5
SDM_B6
SDM_B7
SDQS_B0
SDQS_B1
SDQS_B2
SDQS_B3
SDQS_B4
SDQS_B5
SDQS_B6
SDQS_B7
Its current is 5.1A.
U26
T29
V25
W25
W26
W31
W27
AG31
AJ31
AD27
AE24
AK27
AG25
AL25
AF21
AL23
AJ22
AF29
AL21
AJ20
AE27
AD26
AL29
AL27
AE23
Y25
AA25
AG11
AG15
AE21
AJ28
AC31
U31
M29
J31
AF15
AG13
AG21
AH27
AD29
U30
L27
J30
AG29
AG30
AF17
AG17
N27
N26
AJ30
AH29
AK15
AL15
N31
N30
AA33
R34
R33
AP9
MCKE_B[0..1] 9
MA_B0
MA_B1
MA_B2
MA_B3
MA_B4
MA_B5
MA_B6
MA_B7
MA_B8
MA_B9
MA_B10
MA_B11
MA_B12
MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQS_B0
MDQS_B1
MDQS_B2
MDQS_B3
MDQS_B4
MDQS_B5
MDQS_B6
MDQS_B7
YRCOMP
YCOMPH
YCOMPL
YVREF
MCS_B#0 9
MCS_B#1 9
MRAS_B# 9
MCAS_B# 9
MWE_B# 9
MA_B[0..12] 9
MBA_B0 9
MBA_B1 9
MDQM_B[0..7] 9
MDQS_B[0..7] 9
MCLK_B0 9
MCLK_B#0 9
MCLK_B1 9
MCLK_B#1 9
MCLK_B2 9
MCLK_B#2 9
0.01uC160
0.01uC159
0.01uC132
0.1uC262
2
R291 150
R286 150
C268 2.2u
6.3V
1
VCC_DDR
C241 0.1u
VCC_DDR_C3
XRCOMP
YRCOMP
7
VCC_DDR_C2
R290 42.2
R287 42.2
R180 42.2
R161 42.2
values still need verification
XCOMPL
VCC_DDR
VCC_DDR_C3
XCOMPH
AA35AA33
6
R289 30.1K
R283 10K
R251 10K
R252 30.1K
VCC_DDR
VCC_DDR
YCOMPL
R33
YCOMPH
R34
5
R143 30.1K
R145 10K
R166 10K
R146 30.1K
VCC_DDR_C2
R35
VCCA_DDR
0.1u
4
C239
L10 1uH
+
EC29
100u
ALE
VCC_AGP
3
MSI
Title
Size Document Number Rev
Date: Sheet
MICRO-STAR INt'L CO., LTD.
Intel Springdale - Memory Signals
13, 2003
MS-6756
星期一, 一月
2
725
0A
of
1
A A
8
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