MSI MS-6707 Schematics
5
MS-6707 VER:0A uATX
*AMD PGA 754 Processor
*VIA K8T400M / VT8235 Chipset
D D
(DDR 333 / AGP 8X / VLink 8X)
*Winbond 83697HF-VF LPC I/O
*VT6103 Fast Ethernet 10 / 100
*AC97 AL650 Codec
*USB 2.0 support (integrated into VT8235)
*Jump Less support
*AGP SLOT * 1 ( 8X )
C C
*PCI SLOT * 3
*DDR DIMM * 2
B B
4
Title Page
Cover Sheet 1
Block Diagram
Clock Synthesizer 7
System Memory
DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T400M(HT)
K8 Vcore power
AGP SLOT 8X
SB VT8235
PCI Connectors 1 & 2 & 3
1394a Controller
AC97 Codec
Audio Connector
ATA 66/100
Front USB Port
Rear USB Port
LPC I/O W83697HF & Floppy 28
Hardware monitor
Keyboard/Mouse Port/BIOS
LPT/COM Port
ACPI Power
PowerOK Circuit
Front Panel
BULK / Decoupling
Power Generation
Manual Parts
History
DDR DIMM 1 & 2 8
3
2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket
9
10
11,12,13
14
15
16,17,18
19,20
21
22
23
24
25LAN PHY / Connector
26
27
29
30
31
32
33,34
35
36
37
38
39
2
1
A A
Micro Star Restricted Se cret
Title
Document Number
5
4
3
2
1
Cover Sheet
MS-6707
5
Block Diagram
4
3
2
1
AMD K8
D D
A
AGP 8X /Fast Write
C C
PCI 1
PCI 2
B B
PCI 3
1394a
G
P
P
R
O
PCI Bus
AC'97 Link
MII
Socket 754
HT
VIA
K8T400M
VLINK
VIA
VT8235
Dual ATA
100/133
DDR
DDR * 2
IDE Slot
==>ATA66,100,133 *2
LPC BUS
USB
Onboard AC'97
Codec
A A
Dual USB 1.1 OHCI
/2.0 EHCI 6 Ports
10/100 BaseT
PHY
5
4
==> Front-Port *1 ,
Back-Port *2
3
SUPER I/O
W83697HF
X BUS
ROM Floopy Parallel Serial
2
Micro Star Restricted Se cret
Title
Document Number
Keyboard
Mouse
Block Diagram
MS-6707
1
5
4
3
2
1
GPIO FUNCTION
VT8235 GPIO Function Define
D D
PIN NAME Function define
GPO0 (VSUS33)
GPO1/SUSA#(VSUS33)
GPO2/SUSB#(VSUS33)
GPO3/SUSST1#(VSUS33)
GPO4/SUSCLK(VSUS33)
GPO5/CPUSTP#
GPO6/PCISTP#
GPO7/SLP#
GPO8/GPI8/IPBIN0
GPO9/GPI9/IPBIN1
C C
GPO10/GPI10/IPBRDFR
GPO11/GPI11/IPBRDCK
GPO12/GPI12/IPBOUT0
GPO13/GPI13/IPBOUT1
GPO14/GPI14/IPBTDFR
GPO15/GPI15/IPBTDCK
GPO16/SA16/STRAP
GPO17/SA17/STRAP
GPO18/SA18/STRAP
GPO19/SA19/STRAP
B B
GPO20/GPI20
/ACSDIN2/PCS0#/EI
GPO21/GPI21/ACSDIN3
/PCS1#/SLPBTN#
GPO22/GPI22/IOR#
GPO23/GPI23/IOW#
GPO24/GPI24/GPIOA
GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2
(VSUS33)
GPO27/GPI27/SMBCK2
(VSUS33)
GPO28/GPI28/
APICD0/APICCS#
GPO29/GPI29/
A A
APICD1/APICACK#
GPO30/GPI30/GPIOD
GPO31/GPI31/GPIOE
Default
Function
GPO0
SUSA#
SUSB#
SUSST1#
SUSCLK
CPUSTP#
PCISTP#
GPO7
GPI8
GPI9
GPI10
GPI11
GPI12
GPI13
GPI14
GPI15
SA16
SA17
SA18
SA19
GPI20
GPI21
GPI22
GPI23
GPI24
GPI25
SMBDT2
SMBCK2
SUSLED ( Power LED )
NA
SUSB#
SUSST#
CTL_PLED1# ( Power LED )
NA
NA
NA
JPWD1
JBAT1
HWID1
HWID3
ROMLOCK
NA
HWID0
HWID1
LDT Freq Strapping Bit0
LDT Freq Strapping Bit1
LDT Width (Low=8 Bit)
Fast Command (Low=Disable)
NA
NA
NA
NA
NA
NA
SMBDATA2/Slave SMBUS
SMBCLK2/Slave SMBUS
NA
NA
GPI30
GPI31
5
NA
NA
4
Pull up / down
Pull up to 3VDUAL
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull down to GND
Pull down to GND
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
Pull up to VCC3
PIN NAME
GPI1 (VSUS33)
GPI2/EXTSMI#
(VSUS33)
GPI3/RING#
(VSUS33)
GPI4/LID#
(VSUS33)
GPI5/BATLOW#
(VSUS33)
GPI6/PME#
GPI7/SMBALRT#
GPI16/INTRUDER#
(VBAT)
GPI17/CPUMISS
GPI18/AOLGP1/THRM#
PCI Routing
DEVICES
PCI SLOT 1
PCI SLOT 2
PCI SLOT 3
PCI SLOT 2
(MEDION 2nd)
3
INT#
INT#A
INT#B
INT#C
INT#D
INT#B
INT#C
INT#D
INT#A
INT#C
INT#D
INT#A
INT#B
Default
GPI0
GPI1
EXTSMI#
RING#
LID#
BATLOW#
GPI7
INTRUDER#
CPUMISS
AOLGP1
IORDY
IDSEL
AD16
AD17
AD18
AD19 PCICLK4INT#A
NA Pull up to VBATGPI0 (VBAT)
ATADET0=>Detect IDE1 ATA100/66
EXTSMI#
RING#
ATADET1=>Detect IDE2 ATA100/66
NA
PCI_PME#
NA
NA
NA
THRM#
REQ#/GNT#
PREQ#1
PGNT#1
PREQ#2
PGNT#2
PREQ#3
PGNT#3
CLOCK
PCICLK1
PCICLK2
PCICLK3
PREQ#4
PGNT#4
Title
Document Number
MICRO-STAR INT'L
No. 69, Li-De St, Jung-He City,
CO.,LTD.
Taipei Hsien, Taiwan
2
http://www.msi.com.tw
Pull up / downFunction defineFunction
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VBAT
Pull up to 3VDUAL
Pull up to 3VDUAL
Pull up to VCC3NAGPI19/IORDY
Micro Star Restricted Secret
GPIO Spec.
MS-6707
Last Revision Date:
Sheet
1
星期一, 九月
09, 2002
3 39
of
Rev
0A
5
4
3
2
1
VREF routed as 40~50 mils trace wide ,
Space>25 mils
D D
DDR_VREF8
VDD_25_SUS
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
DDR_VREF
R108 44.2RST
R114 44.2RST
MD[63..0]10
C C
B B
MEMDM[7..0]10
A A
-MDQS[7..0]10
5
C52
X_102P
MEMZN
MEMZP
MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0
MEMDM7
MEMDM6
MEMDM5
MEMDM4
MEMDM3
MEMDM2
MEMDM1
MEMDM0
-MDQS7
-MDQS6
-MDQS5
-MDQS4
-MDQS3
-MDQS2
-MDQS1
-MDQS0
VTT_SENSE 32
AE13
AG12
D14
C14
A16
B15
A12
B11
A17
A15
C13
A11
A10
B9
C7
A6
C11
A9
A5
B5
C5
A4
E2
E1
A3
B3
E3
F1
G2
G1
L3
L1
G3
J2
L2
M1
W1
W3
AC1
AC3
W2
Y1
AC2
AD1
AE1
AE3
AG3
AJ4
AE2
AF1
AH3
AJ3
AJ5
AJ6
AJ7
AH9
AG5
AH5
AJ9
AJ10
AH11
AJ11
AH15
AJ15
AG11
AJ12
AJ14
AJ16
R1
A13
A7
C2
H1
AA1
AG1
AH7
AH13
T1
A14
A8
D1
J1
AB1
AJ2
AJ8
AJ13
VTT_SENSE
MEMVREF1
MEMZN
MEMZP
MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0
MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0
U8B
RSVD_MEMADDA15
RSVD_MEMADDA14
RSVD_MEMADDB15
RSVD_MEMADDB14
MEMORY INTERFACE
VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4
MEMRESET_L
MEMCKEA
MEMCKEB
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H3
MEMCLK_L3
MEMCLK_H2
MEMCLK_L2
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0
MEMRASA_L
MEMCASA_L
MEMWEA_L
MEMBANKA1
MEMBANKA0
MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10
MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0
MEMRASB_L
MEMCASB_L
MEMWEB_L
MEMBANKB1
MEMBANKB0
MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10
MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0
MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0
4
D17
A18
B17
C17
AF16
AG16
AH16
AJ17
AG10
AE8
AE7
D10
C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4
D8
C8
E8
E7
D6
E6
C4
E5
H5
D4
G5
K3
H3
E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5
H4
F5
F4
L5
J5
E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3
N3
N1
U3
V1
N2
P1
U1
U2
VTT_DDR_SUS
MCKE0
MCKE1
MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4
MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0
-MCS3
-MCS2
-MCS1
-MCS0
-MSRASA
-MSCASA
MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0
MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0
-MCS[3..0]
-MSRASA 8,9
-MSCASA 8,9
-MSWEA 8,9
MEMBANKA1 8,9
MEMBANKA0 8,9
MAA[13..0] 8,9
-MSRASB 8,9
-MSCASB 8,9
-MSWEB 8,9
MEMBANKB1 8,9
MEMBANKB0 8,9
MAB[13..0] 8,9
MCKE0 8,9
MCKE1 8,9
MEMCLK_H[7..0] 8,9
MEMCLK_L[7..0] 8,9
-MCS[3..0] 8,9
VDD_12_A
CADIP[0..15]11
CADIN15
CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9
CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3
CADIN2
CADIN1
CADIN0
CLKIP111
CLKIN111
CLKIP011
CLKIN011
VLDT0
R63 49.9RST
CTLIP011
CTLIN011
3
R60 49.9RST
CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP1
CADIP0
CTLIP1
CTLIN1
VDD_12_A
D29
D27
D25
C28
C26
B29
B27
T25
R25
U27
U26
V25
U25
W27
W26
AA27
AA26
AB25
AA25
AC27
AC26
AD25
AC25
T27
T28
V29
U29
V27
V28
Y29
W29
AB29
AA29
AB27
AB28
AD29
AC29
AD27
AD28
Y25
W25
Y27
Y28
R27
R26
T29
R29
C444
C138
X0.22u/BOT
0.22u
U8A
N12-7540010-A10
VLDT0_A6
VLDT0_A5
VLDT0_A4
VLDT0_A3
VLDT0_A2
VLDT0_A1
VLDT0_A0
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKIN_H0
L0_CLKIN_L0
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLIN_H0
L0_CTLIN_L0
HYPER TRANSPORT - LINK0
2
C182
X0.22u
C180
C140
X0.22u
0.22u
VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1
L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CTLOUT_H1
L0_CTLOUT_L1
L0_CTLOUT_H0
L0_CTLOUT_L0
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
C192
0.22u
CADOP15
CADON15
CADOP14
CADON14
CADOP13
CADON13
CADOP12
CADON12
CADOP11
CADON11
CADOP10
CADON10
CADOP9
CADON9
CADOP8
CADON8
CADOP7
CADON7
CADOP6
CADON6
CADOP5
CADON5
CADOP4
CADON4
CADOP3
CADON3
CADOP2CADIP2
CADON2
CADOP1
CADON1
CADOP0
CADON0
CLKOP1
CLKON1
CLKOP0
CLKON0
CTLOP0
CTLON0
C139
0.22u
VLDT0
4.7U/0805
VLDT0 5
C59
CADOP[0..15] 11
CADON[0..15] 11CADIN[0..15]11
CLKOP1 11
CLKON1 11
CLKOP0 11
CLKON0 11
CTLOP0 11
CTLON0 11
C181
0.22u
AH29
AH27
AG28
AG26
AF29
AE28
AF25
N26
N27
L25
M25
L26
L27
J25
K25
G25
H25
G26
G27
E25
F25
E26
E27
N29
P29
M28
M27
L29
M29
K28
K27
H28
H27
G29
H29
F28
F27
E29
F29
J26
J27
J29
K29
N25
P25
P28
P27
M icro Star Restricted Secret
K8 DDR & HT
MS-6707
Last Revision Date:
星期二, 九月
10, 2002
Sheet
4 39
1
Rev
0A
of
5
4
3
VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".
2
1
Place al filters close to the PGA.
Keep all power and signal trce away from
the VR1.
Place a cut in the GND plane around the
D D
LAYOUT: Route VDDA trace approx.
50 mils wide (use 2x25 mil traces to
exit ball field) and 500 mils long.
VDDA_25
FB1 180nH/1210
CPU_VDDA_25
C65
4.7u/0805
C58
3300p
VCCA_PLL regulator circuit.
C55
0.22u
VCC2_5
R163
Near SB/VT8235
Q24
X2N3904S
1K
R164
X4.7K
VCC2_5
THRM# 17,28
AH25
C51
X_102P
CPU_GD34
C C
-LDTSTOP
PS_ON#A34
PS_ON#A
R66
Q6
2N7002S
VCC2_5
1K
Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length
VLDT0
VLDT04
8/28 AMD CHANGE THE PULL-UP POWER
R64 44.2RST
R61 44.2RST
C62
102P
C63
102P
VDD_25_SUS
HDT Connectors
B B
DBREQ_L
DBRDY
TMS
TCK
TRST_L
TDI
NC_AJ18
NC_AH18
NC_AG18
NC_AG17
NC_C19
A A
NC_D18
NC_D20
NC_B19
NC_C21
5
R55 1K
R56 1K
1 2
3 4
5 6
7 8
RN37 8P4R-1K
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
R111 1K
VCC2_5
RN4
8P4R-1K
8P4R-1K
RN49
4
-CPURST34
-LDTSTOP11,16
COREFB_H14
COREFB_L14
Differential , "10:10:5:10:10" .
CPUCLK0_H7
Near CPU in 0.5" .
CPUCLK0_L7
3
L0_REF1
L0_REF0
VDDIO_SENSE32
C61 3900P/X7R
C64 3900P/X7R
R57 820
R58 820
VTT_DDR_SUS
VCC2_5
CPU_GD
VDDIO_SENSE
169RST
R62
R113 1K
R105 1K
5 6
7 8
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
DBRDY
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
NC_AE23
NC_AF23
NC_AF22
NC_AF21
RN3
8P4R-1K
1 2
3 4
AJ25
AF20
AE18
AJ27
AF27
AE26
AE12
AF12
AE11
AJ21
AH21
AJ23
AH23
AE24
AF24
C16
AG15
AH17
C15
C18
AJ28
AE23
AF23
AF22
AF21
AG2
AH1
AE21
C20
AG4
AG6
AG9
A23
A24
B23
E20
E17
B21
A21
A19
A28
C1
J3
R3
AA2
D3
B18
C6
AE9
VDDA1
VDDA2
RESET_L
PWROK
LDTSTOP_L
L0_REF1
L0_REF0
COREFB_H
COREFB_L
CORE_SENSE
VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE
CLKIN_H
CLKIN_L
NC_AJ23
NC_AH23
NC_AE24
NC_AF24
VTT_A5
VTT_B5
DBRDY
NC_C15
TMS
TCK
TRST_L
TDI
NC_C18
NC_A19
KEY1
KEY0
NC_AE23
NC_AF23
NC_AF22
NC_AF21
FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40
U8C
THERMTRIP_L
THERMDA
THERMDC
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
G_FBCLKOUT_H
G_FBCLKOUT_L
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
NC_AF18
RSVD_SCL
RSVD_SDA
FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27
2
A20
A26
A27
AG13
VID4
AF14
VID3
AG14
VID2
AF15
VID1
AE15
VID0
AG18
AH18
AG17
AJ18
AH19
AJ19
AE19
D20
C21
D18
C19
B19
A22
TDO
AF18
D22
C22
B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
THERMTRIP_CPU_L
THERMDA_CPU
VID4
VID3
VID2
VID1
VID0
NC_AG18
NC_AH18
NC_AG17
NC_AJ18
FBCLKOUT_H
R65
80.6RST
FBCLKOUT_L
Zdiff = 80 ohm
DBREQ_L
NC_D20
NC_C21
NC_D18
NC_C19
NC_B19
TDO
THERMDA_CPU 29
VID[4..0] 14
LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )
8/28 AMD CHANGE THE PULL-UP POWER
VDD_25_SUS
R118 1K
RN6
VID0
7 8
VID2
5 6
VID1
3 4
VID3
1 2
8P4R-4.7K
VID4
R59 4.7K
M icro Star Restricted Secret
K8 HDT & MISC
MS-6707
Last Revision Date:
Sheet
1
星期二, 九月
VCC2_5
10, 2002
5 39
of
C50
104P
Rev
0A
5
4
3
2
1
U8E
B2
VSS1
AH20
VSS3
AB21
VSS4
W22
VSS5
M23
VSS6
L24
VSS7
AG25
VSS8
AG27
VSS9
AA10
AE16
G20
R20
U20
W20
AA20
AC20
AE20
AG20
AJ20
D21
H21
M21
AD21
AG21
G22
N22
R22
U22
AG29
AA22
AC22
AG22
AH22
AJ22
D23
H23
AB23
AD23
AG23
G24
N24
R24
U24
W24
AA24
AC24
AG24
AJ24
C25
D26
H26
M26
AD26
AF26
AH26
C27
D28
G28
H15
AB17
AD17
G18
AA18
AC18
D19
H19
AB19
AD19
AF19
N20
D2
VSS10
AF2
VSS11
W6
VSS12
Y7
VSS13
AA8
VSS14
AB9
VSS15
VSS16
J12
VSS17
B14
VSS18
Y15
VSS19
VSS20
J18
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
F21
VSS32
VSS33
K21
VSS34
VSS35
P21
VSS36
T21
VSS37
V21
VSS38
Y21
VSS39
VSS40
VSS41
B22
VSS42
E22
VSS43
VSS44
J22
VSS45
L22
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
F23
VSS57
VSS58
K23
VSS59
P23
VSS60
T23
VSS61
V23
VSS62
Y23
VSS63
VSS64
VSS65
VSS66
E24
VSS67
VSS68
J24
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
B25
VSS78
VSS79
B26
VSS80
VSS81
VSS82
VSS83
T26
VSS84
Y26
VSS85
VSS86
VSS87
VSS88
VSS89
B28
VSS90
VSS91
VSS92
F15
VSS187
VSS188
VSS206
VSS207
B16
VSS208
VSS209
VSS210
VSS211
VSS212
F19
VSS213
VSS214
K19
VSS215
Y19
VSS216
VSS217
VSS218
VSS219
J20
VSS220
L20
VSS221
VSS222
GROUND
5
D D
C C
B B
A A
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205
L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17
VCORE
GNDGND
AC15
H18
H22
H24
G13
AB14
G15
AA15
H16
AB16
G17
AA17
AC17
AE17
AB18
AD18
AG19
G19
AC19
AA19
H20
M20
AB20
AD20
G21
N21
R21
U21
W21
AA21
AC21
M22
AB22
AD22
G23
N23
R23
U23
W23
AA23
AC23
D24
M24
AB24
AD24
AH24
AE25
U8D
L7
VDD1
VDD2
VDD3
B20
VDD4
E21
VDD5
VDD6
J23
VDD7
VDD8
F26
VDD9
N7
VDD10
L9
VDD11
V10
VDD12
VDD13
K14
VDD14
Y14
VDD15
VDD16
VDD17
J15
VDD18
VDD19
VDD20
K16
VDD21
Y16
VDD22
VDD23
VDD24
J17
VDD25
VDD26
VDD27
VDD28
F18
VDD29
K18
VDD30
Y18
VDD31
VDD32
VDD33
VDD34
E19
VDD35
VDD36
VDD39
VDD38
J19
VDD37
F20
VDD40
VDD41
K20
VDD42
VDD43
P20
VDD44
T20
VDD45
V20
VDD46
Y20
VDD47
VDD48
VDD49
VDD50
J21
VDD51
L21
VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58
F22
VDD59
K22
VDD60
VDD61
P22
VDD62
T22
VDD63
V22
VDD64
Y22
VDD65
VDD66
VDD67
E23
VDD68
VDD69
L23
VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76
B24
VDD77
VDD78
F24
VDD79
K24
VDD80
VDD81
P24
VDD82
T24
VDD83
V24
VDD84
Y24
VDD85
VDD86
VDD87
VDD88
VDD89
K26
VDD90
P26
VDD91
V26
VDD92
POWER
VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50
VDDIO6
VDD96
VDD97
VDD98
VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133
VDD93
VDD94
VDD95
VDD_25_SUS
E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4
N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28
4
VCORE
EMI
LAYOUT: Place 1 capacitor every 1-1.5"
VCORE
along VDD_CORE perimiter.
C30
LAYOUT: Plac e 6 EMI capsalong bottom right side of Clawhammer, 2 in middle
of HT link, and 12 along
VDD_25_SUS
VDD_25_SUS
C112
C109
X_6.8pF
C106
X_6.8pF
GND
X_6.8pF
C117
X_6.8pF
X_6.8pF
bottom left side of Claw-
VCORE
C440
C436
C432
X_6.8pF/BOT
X_6.8pF/BOT
C430
X_6.8pF/BOT
LAYOUT: Place beside processor.
C56
C229
0.22u
C123
4.7u/0805
C80
0.22u
C156
4.7u/0805
GND
C152
0.22u
4.7u/0805
C164
C150
0.22u
VDD_25_SUS
C221
3
C434
X_6.8pF/BOT
0.22u
C141
GND
C104
{nopop}
X_0.22uF
GND
hammer.
C442
X_6.8pF/BOT
0.22u
{nopop}
X_0.22uF
C431
C433
{nopop}
X_6.8pF/BOT
C439
{nopop}
X_6.8pF/BOT
X_6.8pF/BOT
X_6.8pF/BOT
GND
LAYOUT: Place beside DDR slots.
VDD_25_SUS
C74
C130
{nopop}
X_0.22uF
GND
VDD_25_SUS
C115
4.7u/0805
GND
VCORE
C441
{nopop}
X_6.8pF/BOT
C103
LAYOUT: Place 1000pF capacitors
between VR M & CPU.
{nopop}
X_0.22uF
C174
4.7u/0805
2
102P
C114
GND
102P
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
K8 POWER & GND
MS-6707
Last Revision Date:
星期二, 九月
Sheet
1
10, 2002
6 39
of
Rev
0A
5
4
3
2
1
Clock Synthesizer
D D
C C
CLKVCC3
C289 104P
CLKVCC3
C284 104P
CLKVCC3
C314 104P
CLKVCC3
C297 104P
CLKVCC3
C315 104P
CLKVCC3
C320 104P
CLKVCC3
C298 104P C309 X_5P
CLKVCC3
CLKVCC3
C296 104P
U22
46
VDD_46
47
VSS_47
2
VDD_2
5
VSS_5
32
VDDF
33
VSSF
9
VDD_9
10
VSS_10
16
VDD_16
15
VSS_15
19
VDD_19
20
VSS_20
29
VDD_29
30
VSS_30
27
VSS_27
38
VDD_38
39
VSS_39
35
VDD_35
34
VSS_34
43
VDDA
42
VSSA
CY28330
FS0/REF0
FS1/REF1
FS2/REF2
XOUT
48MHZ
PCI33_HT66_0
PCI33_HT66_1
PCI33_HT66_2
PCI33_0
PCI33_1
PCI33_2
PCI33_3
PCI33_F
PCI33_4
PCI33_5
24_48MHZ/SEL
SDATA
SCLK
CPUT_0
CPUC_0
CPUT_1
CPUC_1
PCI33_HT66SEL
PCISTOP
SPREADNC
VCC3
FS0
1
FS1
48
FS2
45
3
CLKX1
XIN
CLKX2
4
31
HT_66_0
7
HT_66_1
8
HT_66_2
11
13
14
17
18
23
FS3
21
22
SEL_24
28
SMBDATA1
26
SMBCLK1
25
41
40
37
36
-SEL_66
6
24
SPREAD
4412
FB4 X_120S/0805
CP8
C301
104P
X_COPPER
R234 22
R239 22
R255 22
RN70
R278 33
7 8
5 6
3 4
1 2
8P4R-22
R270 22
R274 22
RN77 8P4R-22
7 8
5 6
3 4
1 2
R289 22
R281 33
R271 15RST C312 X_5P
R275 15RST
R237 10K
R257 X_10K
C319
39P
SB_OSC14
AUD_CLK
APICCLK
C285 10P
X1 14.318MHZ
C286 10P
PCISTP#
CLKVCC3
C313
4.7u/0805
USBCLK_SB48MHz
VCLK
GCLK_SLOT
GCLK_NB
PCICLK6
PCICLK4
PCICLK1
PCICLK2
PCICLK3
PCICLK5
1394_PCLK
SIO48M
SMBDATA1 8,17
SMBCLK1 8,17
CPUCLK0_H
CPUCLK0_L
PCISTP# 17
SB_OSC14 17
AUD_CLK 22
APICCLK 16
USBCLK_SB 18
VCLK 16
GCLK_SLOT 15
GCLK_NB 12
PCICLK6 28
PCICLK4 19
PCICLK1 19
PCICLK2 19
PCICLK3 20
PCICLK5 16
1394_PCLK 21
SIO48M 28
CPUCLK0_H 5
CPUCLK0_L 5
VCLK
GCLK_SLOT
GCLK_NB
USBCLK_SB
SIO48M
SB_OSC14
APICCLK
PCICLK5
PCICLK3
PCICLK2
PCICLK1
PCICLK4
PCICLK6
1394_PCLK
CPUCLK0_H
CPUCLK0_L
SEL_24
FS3
FS0
FS2
FS1
FS0
FS2
FS1
FS3
CN23
7 8
5 6
3 4
1 2
X_8P4C-10P
C317 X_10P
C322 X_10P
C283 X_10P
C294 X_10P
CN24
1 2
3 4
5 6
7 8
X_8P4C-10P
C311 X_10P
C308 X_10P
C329 X_10P
R284 10K
R285 X10K
R233 X10K
R243 X10K
R232 X10K
R235 10K
R242 10K
R238 10K
R286 10K
CLKVCC3
B B
A A
Input Conf iguration
FS0
FS1
FS2
1
1
1
1
1
0
1
0
1 -
0
1
0
0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X 24 or 48100,133.33,166.66,200
PCI_HT#
1
X
X
0
1
X
0
X
1
X
0
1
1
0
1
X
0
X
0
X
1
X
X
X
X
0
X
X
0
1
X
X
1
5
PCISTOP#
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
Clock Generator Output
24_48SEL#
X
X
X
X
CPU (MHz)
200
166.66
133.330
100
X
X
X
X
X
X
X
1
0
X
X
X
- X1 input
X1 input
Hi-Z
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200
100,133.33,166.66,200X
X
4
PCI33 (MHz)
33.33
33.33
33.33
33.33
-
PCI33_HT66 (MHz)
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
33.33 or 66.66
-
X1/6
X1/6
Hi-Z
33.33
33.33
33.33 24
33.33
0
33.33
0
33.33
X1/6
X1/3
Hi-Z
66.66
33.33
33.33 or 66.66
33.33 or 66.66
66.66
66.66
0
33.33
3
24_48 (MHz)
24 or 48
24 or 48
24 or 48
24 or 48
-
0
0
Hi-Z
24 or 48
24 or 48
48
24 or 48
24 or 48
24 or 48
14.318 (MHz)
14.318
14.318
14.318
14.318
-X
0
0
Hi-Z
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
Comment
Normal Hammer operation
Reserved
Athlon compatible
Athlon compatible
Reserved
Reserved
Bypass mode
Bypass mode
Tri-state mode
33.33 vs. 66.66 MHz output select
33.33 vs. 66.66 MHz output select
24 vs. 48 MHz output select
24 vs. 48 MHz output select
PCISTOP vs. 33.33/66.66 MHz selects
PCISTOP vs. 33.33/66.66 MHz selects
PCISTOP vs. 33.33/66.66 MHz selects
PCISTOP vs. 33.33/66.66 MHz selects
2
Micro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
Clock Synthesizer
MS-6707
Last Revision Date:
星期二, 九月
Sheet
1
10, 2002
7 39
of
Rev
0A
5
VDD_25_SUS
DDR_VREF
DR_MD[63..0]
R173 4.7K
-MSWEA4,9
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP1
-MSWEA
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
90
63
1
9
101
102
DR_MD[63..0]9,10
D D
C C
B B
Place 104p Cap. near the DIMM
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
WP(NC)
WE#
VREF
NC2
NC3
SLAVE ADDRESS = 1010000B
NC4
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
3111826344250586674818993
4
104
112
128
136
143
156
164
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
184
PIN
DDR DIMM
SOCKET
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
100
116
124
132
139
145
SYSTEM MEMORY
172
1801582
184
VDDID
VDDSPD
VDDQ13
VDDQ14
152
VSS19
160
VDDQ15
A10_AP
CK0(DU)
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2(DU)
CK2#(DU)
NC(RESET#)
VSS20
VSS21
176
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
157
158
71
163
5
14
25
36
56
67
78
86
47
MAA13
167
MAA0
48
MAA1
43
MAA2
41
MAA3
130
MAA4
37
MAA5
32
MAA6
125
MAA7
29
MAA8
122
MAA9
27
MAA10
141
MAA11
118
MAA12
115
103
59
52
113
SMBCLK1
92
SMBDATA1
91
181
182
183
44
45
49
51
134
135
142
144
MEMCLK_H4
16
MEMCLK_L4
17
MEMCLK_H1
137
MEMCLK_L1
138
MEMCLK_H6
76
MEMCLK_L6
75
173
10
MCKE0
21
MCKE1
111
-MSCASA
65
-MSRASA
154
DR_MEMDM0
97
DR_MEMDM1
107
DR_MEMDM2
119
DR_MEMDM3
129
DR_MEMDM4
149
159
DR_MEMDM6
169
DR_MEMDM7
177
140
DDR1
DDRDIMM_184
-MCS0
-MCS1
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
-MCS0 4,9
-MCS1 4,9
-DR_MDQS0 9,10
-DR_MDQS1 9,10
-DR_MDQS2 9,10
-DR_MDQS3 9,10
-DR_MDQS4 9,10
-DR_MDQS5 9,10
-DR_MDQS6 9,10
-DR_MDQS7 9,10
MAA[13..0]
MEMBANKA0 4,9
MEMBANKA1 4,9
SMBCLK1 7,17
SMBDATA1 7,17
MEMCLK_H4 4,9
MEMCLK_L4 4,9
MEMCLK_H1 4,9
MEMCLK_L1 4,9
MEMCLK_H6 4,9
MEMCLK_L6 4,9
MCKE0 4,9
MCKE1 4,9
-MSCASA 4,9
-MSRASA 4,9
DR_MEMDM[7..0]
3
MAA[13..0] 4,9
VDD_25_SUS
Place 104p and 1000p
Cap. near the DIMM
DR_MEMDM[7..0] 9,10
R175 4.7K
-MSWEB4,9
C43
104P
DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63
WP2
-MSWEB
DDR_VREF
C31
1000P
2
VDD_25_SUS
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VDDQ2
VSS8
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
SLAVE ADDRESS = 1010001B
102
NC4
VSS0
VSS1
3111826344250586674818993
104
112
128
136
143
156
164
172
1801582
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
184
PIN
DDR DIMM
SOCKET
CK0#(DU)
CK1(CK0)
CK1#(CK0#)
CK2#(DU)
NC(RESET#)
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
100
116
124
132
139
145
152
160
176
184
VDDID
CS0#
CS1#
CS2#
CS3#
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
FETEN
A10_AP
A11
A12
A13
BA0
BA1
BA2
SCL
SDA
SA0
SA1
SA2
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0(DU)
CK2(DU)
NC5
CKE0
CKE1
CAS#
RAS#
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
VDDSPD
157
158
71
163
5
14
25
36
56
67
78
86
47
167
48
A0
43
A1
41
A2
130
A3
37
A4
32
A5
125
A6
29
A7
122
A8
27
A9
141
118
115
103
59
52
113
92
91
181
182
183
44
45
49
51
134
135
142
144
16
17
137
138
76
75
173
10
21
111
65
154
97
107
119
129
149
159
169
177
140
DDR2
DDRDIMM_184
1
-MCS2
-MCS3
-DR_MDQS0
-DR_MDQS1
-DR_MDQS2
-DR_MDQS3
-DR_MDQS4
-DR_MDQS5
-DR_MDQS6
-DR_MDQS7
MAB13
MAB0
MAB1
MAB2
MAB3
MAB4
MAB5
MAB6
MAB7
MAB8
MAB9
MAB10
MAB11
MAB12
SMBCLK1
SMBDATA1
MEMCLK_H5
MEMCLK_L5
MEMCLK_H0
MEMCLK_L0
MEMCLK_H7
MEMCLK_L7
MCKE0
MCKE1
-MSCASB
-MSRASB
DR_MEMDM0
DR_MEMDM1
DR_MEMDM2
DR_MEMDM3
DR_MEMDM4
DR_MEMDM5DR_MEMDM5
DR_MEMDM6
DR_MEMDM7
-MCS2 4,9
-MCS3 4,9
MAB[13..0] 4,9
MEMBANKB0 4,9
MEMBANKB1 4,9
VDD_25_SUS
MEMCLK_H5 4,9
MEMCLK_L5 4,9
MEMCLK_H0 4,9
MEMCLK_L0 4,9
MEMCLK_H7 4,9
MEMCLK_L7 4,9
-MSCASB 4,9
-MSRASB 4,9
VDD_25_SUS
A A
R54
1KST
R52
1KST
C48
104P
DDR_VREF
C32
104P
5
DDR_VREF 4
M icro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
4
3
2
http://www.msi.com.tw
System Memory : DDR DIMM 1
MS-6707
Last Revision Date:
星期二, 九月
Sheet
1
10, 2002
8 39
Rev
0A
of
5
4
3
2
1
DDR Terminations
VTT_DDR_SUS VTT_DDR_SUS
D D
DR_MD59
DR_MD63
DR_MD58
DR_MD62
-DR_MDQS7
DR_MEMDM7
DR_MD57
DR_MD61
DR_MD56
DR_MD60
DR_MD51
DR_MD55
DR_MD50
C C
B B
DR_MD54
-DR_MDQS6
DR_MEMDM6
MAA13
MAB13
DR_MD53
DR_MD52
DR_MD49
DR_MD48
DR_MD47
DR_MD46
DR_MD43
DR_MD42
DR_MEMDM5
-DR_MDQS5
-MCS0
-MCS04,8
-MCS2
-MCS24,8
-MCS3
-MCS34,8
-MCS1
-MCS14,8
-MSCASA
-MSCASA4,8
DR_MD41
-MSWEB
-MSWEB4,8
-MSCASB
-MSCASB4,8
DR_MD45
-MSWEA
-MSWEA4,8
-MSRASA
-MSRASA4,8
-MSRASB
-MSRASB4,8
DR_MD44
R174 47
RN66 8P4R-47
7 8
5 6
3 4
1 2
RN63 8P4R-47
7 8
5 6
3 4
1 2
RN60 8P4R-47
7 8
5 6
3 4
1 2
RN57 8P4R-47
7 8
5 6
3 4
1 2
RN56 8P4R-47
7 8
5 6
3 4
1 2
RN54 8P4R-47
7 8
5 6
3 4
1 2
RN52 8P4R-47
7 8
5 6
3 4
1 2
RN50 8P4R-47
7 8
5 6
3 4
1 2
RN47 8P4R-47
7 8
5 6
3 4
1 2
RN46 8P4R-47
7 8
5 6
3 4
1 2
MEMBANKA04,8
MEMBANKB04,8
MEMBANKB14,8
MEMBANKA14,8
DR_MD40
DR_MD39
DR_MD35
DR_MD38
DR_MD34
DR_MEMDM4
-DR_MDQS4
DR_MD37
DR_MD33
DR_MD36
DR_MD32
MAB10
MAB0
MAA10
MAA0
MAA1
MAB1
MAB2
MAA2
DR_MD31
DR_MD27
DR_MD30
DR_MD26
MAB3
MAA3
DR_MEMDM3
MAA4
-DR_MDQS3
DR_MD25
MAB4
MAA6
DR_MD29
DR_MD28
MAA5
MAA8
DR_MD24
MAB6
MAB5
DR_MD19
VTT_DDR_SUS
RN43 8P4R-47
7 8
5 6
3 4
1 2
RN41 8P4R-47
7 8
5 6
3 4
1 2
RN36 8P4R-47
7 8
5 6
3 4
1 2
RN33 8P4R-47
7 8
5 6
3 4
1 2
RN31 8P4R-47
7 8
5 6
3 4
1 2
RN30 8P4R-47
7 8
5 6
3 4
1 2
RN29 8P4R-47
7 8
5 6
3 4
1 2
RN27 8P4R-47
7 8
5 6
3 4
1 2
RN25 8P4R-47
7 8
5 6
3 4
1 2
RN24 8P4R-47
7 8
5 6
3 4
1 2
RN22 8P4R-47
7 8
5 6
3 4
1 2
DR_MD23
MAA7
MAA9
MAA11
MAA12
MAB7
MAB8
DR_MD22
DR_MD18
MAB9
DR_MEMDM2
MAB11
DR_MD21
-DR_MDQS2
DR_MD17
MAB12
DR_MD16
DR_MD20
MCKE04,8
MCKE14,8
DR_MD11
DR_MD10
DR_MD15
DR_MD14
DR_MEMDM1
DR_MD13
-DR_MDQS1
DR_MD12
DR_MD9
DR_MD8
DR_MD3
DR_MD7
DR_MD2
DR_MD6
-DR_MDQS0
DR_MEMDM0
DR_MD1
DR_MD5
DR_MD4
DR_MD0
RN20 8P4R-47
7 8
5 6
3 4
1 2
RN19 8P4R-47
7 8
5 6
3 4
1 2
RN17 8P4R-47
7 8
5 6
3 4
1 2
RN15 8P4R-47
7 8
5 6
3 4
1 2
RN13 8P4R-47
7 8
5 6
3 4
1 2
RN11 8P4R-47
7 8
5 6
3 4
1 2
RN9 8P4R-47
7 8
5 6
3 4
1 2
RN7 8P4R-47
7 8
5 6
3 4
1 2
RN5 8P4R-47
7 8
5 6
3 4
1 2
RN2 8P4R-47
7 8
5 6
3 4
1 2
-MSCASB4,8
-MSCASA4,8
-MSRASB4,8
-MSRASA4,8
MEMBANKB14,8
MEMBANKA14,8
MEMBANKB04,8
MEMBANKA04,8
-MCS2
-MCS24,8
-MCS3
-MCS34,8
MAB13
MAA13
MAB12
MAA12
MAB11
MAA11
MAB1
MAA1
MAB3
MAA3
MAB2
MAA2
MAB6
MAA6
MAB4
MAA4
MAB8
MAA8
MAA5
MAB5
MAA0
MAA10
MAB0
MAB10
-MSCASB
-MCS0
-MCS04,8
-MSCASA
-MCS1
-MCS14,8
MAA9
MAB9
MAB7
MAA7
-MSRASB
-MSRASA
-MSWEA
-MSWEA4,8
-MSWEB
-MSWEB4,8
MCKE14,8
MCKE04,8
CN20
8P4C-22P
CN4
8P4C-22P
CN11
8P4C-22P
CN10
8P4C-22P
CN8
8P4C-22P
CN6
8P4C-22P
CN13
8P4C-22P
CN19
8P4C-22P
CN5
8P4C-22P
CN18
8P4C-22P
CN16
8P4C-22P
CN2
8P4C-22P
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
12
34
56
78
A A
M icro Star Restricted Secret
MEMCLK_H5
MEMCLK_H4
MEMCLK_H7
MEMCLK_H6
MEMCLK_H1
MEMCLK_H0
5
R85 120RST
R80 120RST
R110 120RST
R109 120RST
R96 120RST
R97 120RST
MEMCLK_L5
MEMCLK_L4
MEMCLK_L7
MEMCLK_L1
MEMCLK_L0
MEMCLK_L[7..0]4,8
MEMCLK_H[7..0]4,8
-DR_MDQS[7..0]8,10
4
MEMCLK_L[7..0]
MEMCLK_H[7..0]MEMCLK_L6
-DR_MDQS[7..0]
3
DR_MD19
DR_MD[63..0]8,10
MAB[13..0]4,8
MAA[13..0]4,8
DR_MEMDM[7..0]8,10
DR_MD[63..0]
MAB[13..0]
MAA[13..0]
DR_MEMDM[7..0]
2
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
DDR Terminations Bank 0
MS-6707
Last Revision Date:
星期二, 九月
Sheet
1
10, 2002
9 39
Rev
0A
of
5
4
3
2
1
LAYOUT: Place on backside,
DDR Terminations
D D
C C
B B
RN8 8P4R-10
MD0
1 2
MD4
3 4
MD5
5 6
MD1
7 8
RN10 8P4R-10
MEMDM0 DR_MEMDM0
1 2
-MDQS0
3 4
MD2
5 6
MD6
7 8
RN12 8P4R-10
MD7
1 2
MD3
3 4
MD8
5 6
MD9
7 8
RN14 8P4R-10
MD12
1 2
-MDQS1 -DR_MDQS1
3 4
MEMDM1 DR_MEMDM1
5 6
MD13 DR_MD13
7 8
RN16 8P4R-10
MD14
1 2
MD15
3 4
MD10
5 6
MD11
7 8
RN21 8P4R-10
MD21 DR_MD21
1 2
MEMDM2 DR_MEMDM2
3 4
MD18 DR_MD18
5 6
MD22 DR_MD22
7 8
RN18 8P4R-10
MD20
1 2
MD16
3 4
-MDQS2
5 6
MD17
7 8
RN23 8P4R-10
MD23
1 2
MD19 DR_MD19
3 4
MD24
5 6
MD28 DR_MD28
7 8
RN26 8P4R-10
MD29
1 2
MD25
3 4
-MDQS3
5 6
MEMDM3 DR_MEMDM3
7 8
DR_MD0
DR_MD4
DR_MD5
DR_MD1
-DR_MDQS0
DR_MD2
DR_MD6
DR_MD7
DR_MD3
DR_MD8
DR_MD9
DR_MD12
DR_MD14
DR_MD15
DR_MD10
DR_MD11
DR_MD20
DR_MD16
-DR_MDQS2
DR_MD17
DR_MD23
DR_MD24
DR_MD29
DR_MD25
-DR_MDQS3
RN28 8P4R-10
MD26
1 2
MD30
3 4
MD27
5 6
MD31
7 8
RN40 8P4R-10
MD32
1 2
MD36
3 4
MD33
5 6
MD37
7 8
RN42 8P4R-10
-MDQS4 -DR_MDQS4
1 2
MEMDM4 DR_MEMDM4
3 4
MD34 DR_MD34
5 6
MD38 DR_MD38
7 8
RN45 8P4R-10
MD35 DR_MD35
1 2
MD39
3 4
MD40
5 6
MD44
7 8
RN48 8P4R-10
MD45
1 2
MD41
3 4
-MDQS5 -DR_MDQS5
5 6
MEMDM5 DR_MEMDM5
7 8
RN51 8P4R-10
MD42 DR_MD42
1 2
MD43
3 4
MD46 DR_MD46
5 6
MD47
7 8
RN53 8P4R-10
MD48 DR_MD48
1 2
MD49
3 4
MD52 DR_MD52
5 6
MD53 DR_MD53
7 8
RN55 8P4R-10
MEMDM6
1 2
-MDQS6
3 4
MD54
5 6
MD50 DR_MD50
7 8
RN58 8P4R-10
MD55
1 2
MD51
3 4
MD60
5 6
MD56 DR_MD56
7 8
RN62 8P4R-10
MD61
1 2
MD57
3 4
MEMDM7 DR_MEMDM7
5 6
-MDQS7 -DR_MDQS7
7 8
RN64 8P4R-10
MD62 DR_MD62
1 2
MD58
3 4
MD63
5 6
MD59
7 8
DR_MD26
DR_MD30
DR_MD27
DR_MD31
DR_MD32
DR_MD36
DR_MD33
DR_MD37
DR_MD39
DR_MD40
DR_MD44
DR_MD45
DR_MD41
DR_MD43
DR_MD47
DR_MD49
DR_MEMDM6
-DR_MDQS6
DR_MD54
DR_MD55
DR_MD51
DR_MD60
DR_MD61
DR_MD57
DR_MD58
DR_MD63
DR_MD59
evenly spaced around VTT fill.
VDD_25_SUS
VTT_DDR_SUS
C45
X_0.22uF
{nopop}
C177
X_0.22uF
{nopop}
C227
X_0.22uF
{nopop}
C226
X_0.22uF
{nopop}
C47
X_0.22uF
{nopop}
VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS
C44
104P
C57
104P
C68
104P
C71
104P
C78
104P
C85
104P
VTT_DDR_SUS
C40
C49
104P
VTT_DDR_SUS
104P
C155
C151
104P
104P
C60
C159
104P
104P
C70
C161
104P
104P
C75
C167
C93
104P
C101
104P
C110
104P
C118
104P
C121
104P
C125
104P
C129
104P
104P
104P
C81
C170
LAYOUT: Locate close to Clawh ammer socket.
VTT_DDR_SUS
C53
4.7U/1206
C132
104P
C134
104P
C142
104P
C149
104P
C153
104P
C157
104P
C160
104P
C96
104P
104P
C88
C173
104P
104P
C178
104P
104P
C107
C184
104P
104P
C113
C188
104P
104P
C119
C196
104P
104P
C124
C203
GND
C165
104P
C169
104P
C172
104P
C176
104P
C183
104P
C186
104P
C193
104P
104P
104P
C126
C210
C16
0.22u
VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS
C200
104P
C207
104P
C213
104P
C215
104P
C218
104P
C223
104P
104P
104P
C131
C214
104P
104P
C133
C216
104P
104P
C137
C219
104P
104P
C147
GND
C225
104P
104P
LAYOUT: Place alternating caps to GND and VDD_2.5_SUS
GND
in a single line along VTT island.
LAYOUT: Add 100pF and 1000pF on VTT fill near
Clawhammer and near DIMMs (both sides).
VTT_DDR_SUS
100P
C66
C206
4.7u/0805
0.22u
C39
GND
C34
4.7u/0805
102P
GND
C241
4.7u/0805
2
C233
C175
4.7u/0805
102P
C232
5
-MDQS[7..0]
-DR_MDQS[7..0]
DR_MD[63..0]
MD[63..0]
MEMDM[7..0]
DR_MEMDM[7..0]
VTT_DDR_SUS
C143
4.7u/0805
4
3
-MDQS[7..0]4
-DR_MDQS[7..0]8,9
A A
DR_MD[63..0]8,9
MD[63..0]4
MEMDM[7..0]4
DR_MEMDM[7..0]8,9
VTT_DDR_SUS
0.22u
C148
GND
M icro Star Restricted Secret
Title
Document Number
MICRO-STAR INT'L
CO.,LTD.
No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw
DDR Terminations Bank 1
MS-6707
Last Revision Date:
星期二, 九月
Sheet
1
10, 2002
10 39
of
Rev
0A
A
B
C
D
E
VDD_12_A
K8T400M HT Interface
A10
A24
A25
A26A9B10
From Claw Hammer
4 4
CADOP[15:0]4
CLKOP04
CLKOP14
CTLOP04
CADON[15:0]4
3 3
CLKON04
CLKON14
CTLON04
-LDTRST34
-LDTSTOP5,16
2 2
CADOP0
CADOP1
CADOP2
CADOP3
CADOP4
CADOP5
CADOP6
CADOP7
CADOP8
CADOP9
CADOP10
CADOP11
CADOP12
CADOP13
CADOP14
CADOP15
CLKOP0
CLKOP1
CTLOP0
CADON0
CADON1
CADON2
CADON3
CADON4
CADON5
CADON6
CADON7
CADON8
CADON9
CADON10
CADON11
CADON12
CADON13
CADON14
CADON15
CLKON0
CLKON1
CTLON0
-LDTRST
-LDTSTOP
RPCOMP
PNCOMP
RTCOMP
VDD_12_A
C22
AVDD2
T26
RCADP0
P24
RCADP1
P26
RCADP2
M24
RCADP3
K24
RCADP4
K26
RCADP5
H24
RCADP6
H26
RCADP7
R24
RCADP8
R22
RCADP9
N24
RCADP10
N22
RCADP11
L22
RCADP12
J24
RCADP13
J22
RCADP14
G24
RCADP15
M26
RCLKP0
L24
RCLKP1
F24
RCTLP
R26
RCADN0
P25
RCADN1
N26
RCADN2
M25
RCADN3
K25
RCADN4
J26
RCADN5
H25
RCADN6
G26
RCADN7
R23
RCADN8
P22
RCADN9
N23
RCADN10
M22
RCADN11
K22
RCADN12
J23
RCADN13
H22
RCADN14
G23
RCADN15
L26
RCLKN0
L23
RCLKN1
F25
RCTLN
B11
LDTRST
A12
LDTSTP
D25
RPCOMP
D26
RNCOMP
C26
RTCOMP
U24
VLDT
U25
VLDT
U26
VLDT
V21
VLDT
V22
VLDT
V23
VLDT
V24
VLDT
V25
VLDT
V26
VLDT
AGND2
C21
A23
VLDT
VSS
A8
VLDT
VSS
B8
VLDT
VSS
B13
VLDT
VSS
B15
VLDT
VSS
B17
B23
VLDT
VSS
B19
B24
B25
VLDT
VLDT
VSS
VSS
B21
B22C8D8
B26B9C10
VLDT
VLDT
VSS
VSS
D6
VLDT
VSS
C11
VLDT
VSS
D12
C23
VLDT
VSS
D14
C24
VLDT
VSS
D16
C25C9D10
VLDT
VLDT
VSS
VSS
D18
D20
D11
D22
VLDT
VLDT
VLDT
VLDT
VSS
VSS
VSS
VSS
E5E6E8F7F8
D23
D24D9E10
VLDT
VSS
VLDT
VSS
F12
VLDT
VSS
F13
E11
VLDT
VSS
F14
E21
VLDT
VSS
F17
E22
VLDT
VSS
F18
E23
VLDT
VSS
F26
E24E9F10
VLDT
VLDT
VSS
VSS
G25H1H23
VLDT
VSS
F11
VLDT
VSS
F15
VLDT
VSS
F16
VLDT
VSS
J2
F19
VLDT
VSS
J3
F20
VLDT
VSS
J21
F21
VLDT
VSS
J25
F22
VLDT
VSS
K4G1K10
F23
VLDT
VSS
G21
VLDT
VSS
K11
G22
VLDT
VSS
K12
H21
VLDT
VSS
K13
J10
VLDT
VSS
K14
J11
VLDT
VSS
K15
J12
VLDT
VSS
K16
J13
VLDT
VSS
K17
J14
VLDT
VSS
K23H2L10
J15
VLDT
VSS
J16
VLDT
VSS
L11
J17
VLDT
TCADP10
TCADP11
TCADP12
TCADP13
TCADP14
TCADP15
TCADN10
TCADN11
TCADN12
TCADN13
TCADN14
TCADN15
VSS
L12
K18
K21
VLDT
VLDT
TCADP0
TCADP1
TCADP2
TCADP3
TCADP4
TCADP5
TCADP6
TCADP7
TCADP8
TCADP9
TCLKP0
TCLKP1
TCTLP
TCADN0
TCADN1
TCADN2
TCADN3
TCADN4
TCADN5
TCADN6
TCADN7
TCADN8
TCADN9
TCLKN0
TCLKN1
TCTLN
VSS
VSS
L13
L14
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VLDT
VSS
L18
L15
J18
VLDT
VSS
L16
U14A
VLDT
B12
A13
B14
A15
A17
B18
A19
B20
E12
D13
E14
D15
D17
E18
D19
E20
B16
E16
A21
C12
A14
C14
A16
A18
C18
A20
C20
E13
C13
E15
C15
C17
E19
C19
D21
CLKIN0
C16
E17
A22
L21
M18
N18
N21
P18
P21
R18
T18
T21
T22
T23
T24
T25
U18
U21
U22
U23
VSS
K8M400/K8T400M
CADIP0
CADIP1
CADIP2
CADIP3
CADIP4
CADIP5
CADIP6
CADIP7
CADIP8
CADIP9
CADIP10
CADIP11
CADIP12
CADIP13
CADIP14
CADIP15
CLKIP0
CLKIP1
CTLIP0
CADIN0
CADIN1
CADIN2
CADIN3
CADIN4
CADIN5
CADIN6
CADIN7
CADIN8
CADIN9
CADIN10
CADIN11
CADIN12
CADIN13
CADIN14
CADIN15
CLKIN1
CTLIN0
VDD_12_A
To Claw Hammer
CADIP[15:0] 4
CLKIP0 4
CLKIP1 4
CTLIP0 4
CADIN[15:0] 4
CLKIN0 4
CLKIN1 4
CTLIN0 4
PNCOMP
RTCOMP
RPCOMP
VDD_12_A
C163 104P
C166 104P
Around NB
VDD_12_A
R128 49.9RST
R120 100RST
R127 49.9RST
1 1
Title
Size Document Number Rev
C
A
B
C
D
Date: Sheet of
MS-6707
NORTH BRIDGE K8T400M (HT)
10, 2002
MS-6707
星期二, 九月
E
11 39
0A
A
B
K8T400M AGP 8X ,V-Link, Misc. Control
VDDQ
C
D
E
4 4
GAD[31:0]15
3 3
GC/BE#015
GC/BE#115
GC/BE#215
GC/BE#315
AD_STBS015
AD_STBF015
AD_STBS115
AD_STBF115
GFRAME15
GIRDY15
GTRDY15
GDEVSEL15
GSTOP15
GPAR15
RBF15
WBF15
GREQ15
2 2
GGN T15
GSERR15
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
AD_STBS0
AD_STBF0
AD_STBS1
AD_STBF1
GCLK_NB7
SBA015
SBA115
SBA215
SBA315
SBA415
SBA515
SBA615
SBA715
SB_STBS15
SB_STBF15
AGPVREF_GC15
1 1
AGP8XDET#15
SB_STBS
SB_STBF
ST015
ST115
ST215
AGPPCOMP
AGPNCOMP
AGPVREF_GC
DBIL
DBIL15
DBIH
DBIH15
A
AF18
GD0/DVOBHSYNC
AD18
GD1/DVOBVSYNC
AE18
GD2/DVOBD1
AF17
GD3/DVOBD0
AD17
GD4/DVOBD3
AD16
GD5/DVODB2
AE16
GD6/DVOBD5
AF16
GD7/DVOBD4
AF14
GD8/DVOBD6
AD14
GD9/DVOBD9
AD13
GD10/DVOBD8
AE13
GD11/DVOBD11
AF13
GD12/DVOBD10
AD12
GD13/DVOBCCLKINT
AF12
GD14/DVOBFLDSTL
AE12
GD15/MDDC_DATA
AD10
GD16/DVOCVSYNC
AE10
GD17/DVOCHSYNC
AF10
GD18/DVOCBLANK#
AD9
GD19/DVOCD0
AF9
GD20/DVOCD1
AF8
GD21/DVOCD2
AE9
GD22/DVOCD3
AD8
GD23/DVOCD4
AF6
GD24/DVOCD7
AD7
GD25/DVOCD6
AE6
GD26/DVOCD9
AD5
GD27/DVOCD8
AF5
GD28/DVOCD11
AF4
GD29/DVOCD10
AE4
GD30/DVOBCINTR#
AD4
GD31/DVOCFLDSTL
AD15
GBE0/DVOBD7
AF11
GBE1/DVOBBLANK#
AD11
GBE2
AC7
GBE3/DVOCD5
AF15
AD_STBS0/DVOBCLK#
AE15
AD_STBF0/DVOBCLK
AF7
AD_STBS1/DVOCCLK#
AE7
AD_STBF1/DVOCCLK
AC9
GFRAME/MDVI_DATA
AC10
GIRDY/MI2CCLK
AC14
GTRDY/MDVI_CLK
AC11
GDEVSEL/MI2CDATA
AC12
GSTOP/MDDC_CLK
AC16
GPAR
AD6
RBF
AC1
WBF
Y1
GREQ
AA3
GGNT
AC15
GSERR
A11
GCLK
AC2
SBA0/ADDID0
AC3
SBA1/ADDID1
AD1
SBA2/ADDID2
AD2
SBA3/ADDID3
AF2
SBA4/ADDID4
AD3
SBA5/ADDID5
AE3
SBA6/ADDID6
AF3
SBA7/ADDID7
AE1
SB_STBS
AF1
SB_STBF
AA2
ST0
AA1
ST1
AB1
ST2
V1
AGPPCOMP
W1
AGPNCOMP
AC13
AGPVREF0
AC6
AGPVREF1
Y2
AGP8XDET
AC4
DBIL
AC5
DBIH
VSSQQ
T1
R15
VSS
R14
VSS
R13
U1
VSS
R12
VCCQQ
VSS
VSS
R11
VCC3/NC
VSS
VSS
N5
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
M5K8M9L8N9P9R9
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
P16
P17
P23R1R2R3R4R5R10
B
L5K9L9
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
P13
P14
P15
J9
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
P11
P12
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
N17
N25P5P10
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
N14
N15
N16
F6F2F5E1F4
G2G3G4G5H3H4H5J4J5
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
N11
N12
N13
F3
VCC3/NC
VCC3/NC
VCC3/NC
VSS
VSS
VSS
M21
M23
N10
F1K5E4E2E3
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
VCC3/NC
DVID0/TVD0/NC
DVID1/TVD1/NC
DVID2/TVD2/NC
DVID3/TVD3/NC
DVID4/TVD4/NC
DVID5/TVD5/NC
DVID6/TVD6/NC
DVID7/TVD7/NC
DVID8/TVD8/NC
DVID9/TVD9/NC
DVID10/TVD10/NC
DVID11/TVD11/NC
DVIDET/TVCKI/NC
DVIDE/TVBL/NC
DVIHS/TVHS/NC
DVIVS/TVVS/NC
DVICLK/TVCLK/NC
VSS
VSS
VSS
VSS
VSS
M14
M15
M16
M17
M13
D1
VCC3/NC
VCC3/NC
VCC3/NC
VPAR
UPSTB
UPSTB
DNSTB
DNSTB
UPCMD
DNCMD
LVREF
LCOMPP
PWRGD
PCIRST
TESTIN
SUSTAT
DEBUG
AR/NC
AG/NC
AB/NC
RSET/NC
HSYNC/NC
VSYNC/NC
XIN/NC
INTA/NC
BISTIN/NC
SPCLK1/NC
SPCLK2/NC
SPD1/NC
SPD2/NC
GOP0/NC
GPOUT/NC
VSS
VSS
VSS
M10
M11
M12
K8M400/K8T400M
VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7
VBE
VSS
VSS
VSS
L17
L25
C
U14B
AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25
AE21
AF19
AE23
AF23
AF22
AD22
AF26
AD23
AF21
AD19
AE26
AD25
AC26
AD26
AC17
B3
A3
A2
C4
A1
B1
C6
E7
D3
P2
C2
P1
C1
J1
K2
K3
L4
K1
L2
L3
M4
L1
M2
M3
M1
P4
N1
N4
N3
P3
N2
D2
LVREF_NB
LCOMPP
TESTIN
DEBUG
VLAD0 16
VLAD1 16
VLAD2 16
VLAD3 16
VLAD4 16
VLAD5 16
VLAD6 16
VLAD7 16
VBE0# 16
VPAR 16
UPSTB 16
UPSTB# 16
DNSTB 16
DNSTB# 16
UPCMD 16
DNCMD 16
C209
X_102P
PWROK_NB# 17
PCIRST1# 16,28
SUSST# 17
R160 X10K
R154 10K
VCC2_5
AGPVREF_GC
C462 X104P/BOT
C243 105P
LAYOUT: Place caps as close NB as possible
TESTIN
R166 4.7K
VCC2_5
VDDQ
AGPNCOMP
AGPPCOMP
LCOMPP
R161 60.4RST
R156 60.4RST
R165 360RST
VCC2_5
R150
3KST
C197
104P
LVREF_NB
R155
1KST
Title
Size Document Number Rev
C
D
Date: Sheet of
MS-6707
NORTH BRIDGE K8T400M (AGP & VLINK)
星期二, 九月
10, 2002
C202
104P
MS-6707
E
12 39
0A
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