MSI MS-6706 Schematics
8
7
6
5
4
3
2
1
Cover Sheet
Block Diagram
D D
MAIN CLOCK GEN & DDR CLOCK BUFFER
mPGA478-B INTEL CPU Sockets
MS-6706
VERSION:0A
SIS 645DX CHIPSET
Willamette/Northwood 478pin mPGA-B Processor Schematics
SIS 645/650 NORTH BRIDGE
DDR SLOT
DDR TERMINATOR
SIS 961A SOUTH BRIDGE
AGP SLOT
CPU:
C C
Willamette/Northwood mPGA-478B Processor
PCI SLOTS
LAN CONTROLLER
System Brookdale Chipset:
SIS 645DX (North Bridge)
+961B (South Bridge)
On Board Chipset:
LPC Super I/O -- W83697HF
RJ45 CONNECTOR
IDE CONNECTOR
USB CONNECTOR
AC'97 CODEC
AUDIO CONNECTOR
1
2
3
4 - 5
6 - 9
10
11
12 - 14
15
16
17
18
19
20
21
22
Expansion Slots:
B B
AGP2.0 SLOT * 1
PCI2.2 SLOT* 3
CNR & FAN
LPC I/O(W83697HF)
PARALLEL & SERIAL PORT
VRM 9.X
ACPI CONTROLLER
ATX POWER CON & VGA CON
FRONT PANEL
Decoupling Capacitor
History
A A
MICRO-STAR INT'L CO.,LTD.
Title
COVER PAGE
Size Document Number Rev
MS-6706 0A
8
7
6
5
4
3
Date: Sheet
2
23
24
25
26
27
28
29
30
31
of
132Monday, May 13, 2002
1
5
4
3
2
1
System Block Diagram
D D
GPIO_0
GPIO_1
GPIO_2
SOCKET-478
GPIO_3 EXTSMI#
GPIO_4 Pull-Down
GPIO_5 PREQ#5(Pull-Up)
GPIO_6
GPI_7 RESUME Pull-Down
Host Bus
Support Dual Monitor
AGP SLOT
AGP SLOT
DDR SDRAM
SSTL-2 Termination
(Only for DDR)
SIS645DX
DIMM 1 DIMM 2
C C
Rtt
GPI_8 RING
GPI_9
GPI_10
GPIO_11
GPIO_13
GPIO_14
GPIO_15
GPIO_16
GPIO_17
GPIO_18
GPIO_19
Support Max to six-PCI Devices
Lan
PCI SLOT 3 PCI SLOT 2 PCI SLOT 1
SiS961B
IDE 1
B B
IDE 2
KEYBOARD
/MOUSE
PS/2
HyperZip
512 MB
LPC Bus
Audio Codec
CNR
USB 0
USB 1
AC'97
USB 2
USB 3
Analog In
Analog Out
GPIO_20
GPIO Table on SIS961
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
MAIN
I/O
I
RESUME
I RESERVED
RESUME
I
RESUME
I/O RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
I/O
RESUME
Pull-Down
Pull-Down
THERM#
PGNT#5(Pull-Up)
Pull-Down
RESERVED
Pull-DownGPIO_12 I/O RESUME
Flash Rom protection H: Disable, L: Enable
LAN_WAKE#
KBDAT
KBCLK
MSDAT
MSCLK
SMBCLK
SMBDAT
FAN1FAN
Legacy
ROM
A A
5
2
FAN CONTROL
IR/CIR
LPC Super I/O
GAME/MIDIGPIOs
4
VOLTAGE MONITOR
TEMPERATURE MONITOR
SERIAL PARALLEL FLOPPY
MICRO-STAR INT'L CO.,LTD.
Title
System Block Diagram
Size Document Number Rev
MS-6706 0A
3
2
Date: Sheet
1
of
232Thursday, May 09, 2002
5
VCC3
R228
10K
NPN-MBT3904LT1-S-SOT23
CB72
0.1u
CP18
X_COPPER
CB168
CB165
0.1u
0.1u
VCC3
R235
10K
Q27
CP3 X_COPPER
L14
X_80_0805
CB71
0.01u
L40
X_80_0805
D D
CE6
10u
C C
B B
10u
VCC2.5V
CE1
VCCP
+
VCC3
CE7
10u
CB185
0.1u
CB166
0.1u
VCC3
R229
10K
Q26
NPN-MBT3904LT1-S-SOT23
VCC3
CB183
0.1u
CB68
0.1u
CB159
0.1u
CB189
CB169
0.1u
0.1u
R234
CP17 X_COPPER
L37
X_80_0805
CBVDD
CB78
0.1u
CB170
0.1u
0.1u
CB80
0.1u
CB174
CB181
1000p
CB190
0.1u
475
4
Main Clock Generator
U14
ICS-ICS952001AF-SSOP48
1
VDDREF
11
VDDZ
13
VDDPCI
19
VDDPCI
28
VDD48
29
VDDAGP
42
VDDCPU
48
VDDSD
12
PCI_STOP#
45
CPU_STOP#
5
VSSREF
8
VSSZ
18
VSSPCI
24
VSSPCI
25
VSS48
32
VSSAGP
41
VSSCPU
46
VSSSD
33
PD#/VTT_PWRGD
38
IREF
36
VDDA
CB167
1000p
37
VSSA
XIN
6
14M-32pf-HC49S-D
C149
27p
Y1
CPUCLK0
CPUCLK#0
CPUCLK1
CPUCLK#1
SDCLK
AGPCLK0
AGPCLK1
ZCLK0
ZCLK1
PCICLK_F0/FS3
PCICLK_F1/FS4
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
REF0/FS0
REF1/FS1
REF2/FS2
24_48M/MULTISEL
SCLK
SDATA
XOUT
7
C144
27p
3
40
39
44
43
47
31
30
9
10
FS3 96XPCLK
14
FS4 SIOPCLK
15
16
17
20
21
22
23
FS0
2
FS1
3
FS2
4
27
48M
26
MULTISEL
35
34
R238
R239
R242
R243
R241
R247
R248
R298
R299
RN84 33
7 8
5 6
3 4
1 2
RN85 33
7 8
5 6
3 4
1 2
R290
R294
R295
R296
R245
R246
2
CPUCLK0
33
CPUCLK-0
33
CPUCLK1
33
CPUCLK-1
33
SDCLK
33
AGPCLK0
22
AGPCLK1
33
ZCLK0
22
ZCLK1
22
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
REFCLK0
33
REFCLK1
33
APICCLK
33
REFCLK2
X_33
UCLK48M
22
SIO48M
22
SMBCLK
SMBDAT
VCC3
R300 2.7K
R301 X_2.7K
R308 X_2.7K
R278 X_2.7K
R316 2.7K
FS4 FS3 FS2 FS1 FS0 CPU SDRAM ZCLK AGP PCI
0000
CPUCLK0 4
CPUCLK-0 4
CPUCLK1 6
CPUCLK-1 6
SDCLK 7
AGPCLK0 6
AGPCLK1 15
ZCLK0 8
ZCLK1 12
96XPCLK 12
SIOPCLK 24
PCICLK1 16
PCICLK2 16
PCICLK3 16
PCICLK4 16
PCICLK5 17
REFCLK0 8
REFCLK1 13
APICCLK 13
REFCLK2 21
UCLK48M 14
SIO48M 24
SMBCLK 10,13,27
SMBDAT 10,13,27
F0~F4 intern a l P ul l- Down 120K
FS0
FS1
FS3
001111
MULTISEL
R297
R317
100 100
100133
MULTISEL inter na l Pu ll -U p 120K
R244 X_4.7K
R236 X_4.7K
BSEL0 4
FS2
10K
FS4
10K
6666666633
33
VCC3
CPUCLK0
CPUCLK-0
CPUCLK1
CPUCLK-1
SDCLK
AGPCLK0
AGPCLK1
ZCLK0
ZCLK1
PCICLK2
PCICLK1
SIOPCLK
96XPCLK
PCICLK5
PCICLK4
PCICLK3
APICCLK
REFCLK0
REFCLK1
REFCLK2
UCLK48M
SIO48M
SMBCLK
SMBDAT
1
R232
R233
R230
R231
CN15 10p
CN16 10p
DDRCLK0
DDRCLK1
DDRCLK2
DDRCLK3
DDRCLK8
DDRCLK7
49.9
49.9
49.9
49.9
C132 10p_0603
C135 10p_0603
C136 47p
C179 10p_0603
C180 10p_0603
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
C177 X_10p_0603
C160 X_10p_0603
C176 X_10p_0603
C178 X_10p_0603
C133 10p_0603
C134 10p_0603
C114 X_10p
C117 X_10p
C62 10p_0603
C63 10p_0603
C59 10p_0603
C51 10p_0603
C49 10p_0603
C47 10p_0603
U4
CP4 X_COPPER
VCC2.5V
A A
L15
X_80_0805
5
CE2
+
10u
FWDSDCLKO7
CB75
0.1u
CB79
0.01u
SMBCLK
SMBDAT
FWDSDCLKO
CBVDD
R88
R64 0
0
ICS-ICS93722BF-SSOP28
3
VDD
12
VDD
23
VDD
10
AVDD
7
SCLK
22
SDATA
8
CLK_IN
20
FB_IN
9
NC
18
NC
21
NC
4
6
GND
111528
GND
GND
GND
Clock Buffer (DDR)
R82
2
CLK0
CLK1
CLK2
CLK3
CLK4
CLK5
CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5
FB_OUT
R83
4
R85
13
R71
17
R69
24
R67
26
R81
1
R84
5
R86
14
R72
16
R68
25
R66
27
R70
19
DDRCLK0
0
DDRCLK1
0
DDRCLK2
0
DDRCLK3
0
DDRCLK8
0
DDRCLK7
0
DDRCLK-0
0
DDRCLK-1
0
DDRCLK-2
0
DDRCLK-3
0
DDRCLK-8
0
DDRCLK-7
0
FB_OUT
22
C50
10p_0603
3
VCC3
DDRCLK[0..8]
DDRCLK-[0..8]
C238 0.1u
C239 0.1u
DDRCLK[0..8] 10
DDRCLK-[0..8] 10
2
MICRO-STAR INT'L CO.,LTD.
Title
MAIN CLOCK GEN & BUFFER
Size Document Number Rev
MS-6706 0A
Date: Sheet
DDRCLK-0
DDRCLK-1
DDRCLK-2
DDRCLK-3
DDRCLK-8
DDRCLK-7
1
C61 10p_0603
C64 10p_0603
C60 10p_0603
C52 10p_0603
C48 10p_0603
C46 10p_0603
of
332Wednesday, May 22, 2002
8
7
6
5
4
3
2
1
CPU GTL REFERNCE VOLTAGE BLOCK
VCCP
Length < 1.5inch.
CPU SIGNAL BLOCK
HDBI#0
HDBI#1
HDBI#2
HDBI#3
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
CPU_TMPA
THERMTRIP#
PROCHOT#
IGNNE#
SMI#
A20M#
CPUSLP#
CPU_GD
CPURST#
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
HA#[3..31]6
AF26
AB26
AE21
AF24
AF25
AB23
AB25
AA24
AA22
AA25
W25
W26
AC3
AA3
AB2
AD2
AD3
AD6
AD5
E21
G25
P26
V21
V6
B6
Y4
W5
H5
H2
G1
G4
G2
F3
E3
D2
E2
C1
D5
F7
E6
D4
B3
C4
A2
C3
B2
B5
C6
A22
A7
Y21
Y24
Y23
Y26
V24
U2A
DBI0#
DBI1#
DBI2#
DBI3#
IERR#
MCERR#
FERR#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
J6
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
BSEL0
BSEL1
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
HA#22
HA#25
HA#23
HA#26
HA#27
HA#28
HA#30
HA#29
HA#31
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
D53#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
V22
U21
V25
U23
U24
U26
T23
T22
T25
T26
R24
R25
P24
R21
HD#47
HD#46
HD#45
HD#44
HD#42
HD#43
HD#41
HD#40
HD#53
7
HD#51
HD#52
HD#50
HD#49
HD#48
HA#24
A25#
D40#
N25
HD#39
A24#
D39#
N26
HD#38
A23#
D38#
M26
HD#37
HA#21
A22#
D37#
N23
HD#36
HA#20
A21#
D36#
HD#35
M24
HA#19
A20#
D35#
P21
HD#34
HA#18
A19#
D34#
N22
HD#33
HA#17
A18#
D33#
M23
HD#32
HA#16
A17#
D32#
H25
HD#31
6
HA#15
A16#
D31#
K23
HD#30
HA#14
A15#
D30#
J24
HD#29
HA#13
A14#
D29#
L22
HD#28
HA#12
A13#
D28#
M21
HD#27
HA#11
A12#
D27#
H24
HD#26
HA#10
A11#
D26#
G26
HD#25
A10#
D25#
HA#8
HA#9
A9#
D24#
L21
D26
HD#23
HD#24
HA#7
A8#
D23#
F26
HD#22
HA#6
A7#
D22#
E25
HD#21
HA#5
A6#
D21#
F24
HD#20
HA#4
A5#
D20#
F23
HD#19
HA#3
A4#
D19#
G23
HD#18
A3#
D18#
AE25A5A4
DBR#
Differential
Host Data
Strobes
D17#
D16#
D15#
D14#
E24
H22
D25
J21
D23
HD#14
HD#16
HD#15
HD#17
HD#13
AD26
AC26
ITP_CLK1
VSS_SENSE
VCC_SENSE
D13#
D12#
D11#
D10#
C26
H21
G22
B25
HD#9
HD#10
HD#11
HD#12
5
VID4
ITP_CLK0
D9#
D8#
D7#
C24
C23
HD#6
HD#8
HD#7
AE1
B24
VID3
AE2
VID4#
D6#
D22
HD#5
VID2
AE3
VID3#
D5#
C21
HD#4
VID1
AE4
VID2#
D4#
A25
HD#3
VID0
AE5
VID1#
VID0#
TESTHI12
TESTHI11
TESTHI10
LINT1/NMI
LINT0/INTR
D3#
D2#
A23
B22
HD#2
HD#1
GTLREF3
GTLREF2
GTLREF1
GTLREF0
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
COMP1
COMP0
DP3#
DP2#
DP1#
DP0#
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
D1#
D0#
B21
HD#0
VID[0..4] 26
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
PGA-S478-F02
GTLREF1
GTLREF2
BPM#5
BPM#4
BPM#1
BPM#0
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
R60 56
R42 56
R20 56
R7 56
R59 56
RS#2
RS#1
RS#0
R31 49.9
R65 49.9
4
VCCP
CPUCLK-0 3
CPUCLK0 3
RS#[0..2] 6
HBR#0 6
* Short trace
HADSTB#1 6
HADSTB#0 6
HDSTBP#3 6
HDSTBP#2 6
HDSTBP#1 6
HDSTBP#0 6
HDSTBN#3 6
HDSTBN#2 6
HDSTBN#1 6
HDSTBN#0 6
NMI 13
INTR 13
HREQ#[0..4] 6
3
D D
HDBI#[0..3]6
FERR#13
STPCLK#13
HINIT#13
HDBSY#6
HDRDY#6
HTRDY#6
HADS#6
HD#[0..63]6
100 MHz
133 MHz
8
HLOCK#6
HBNR#6
HIT#6
HITM#6
HBPRI#6
HDEFER#6
CPU_TMPA24
VTIN_GND24
PROCHOT#13
IGNNE#13
SMI#13
A20M#13
CPUSLP#13
FSB
BSEL03
CPU_GD6
CPURST#6
C C
Trace : 10
mil width
10mil
space
R61 X_33
BSEL0
0
1
B B
A A
GTLREF1
Length < 1.5inch.
GTLREF2
Every pin put one 220pF cap near it.
Trace Width 15mils, Space 15mils.
Keep the voltage dividers within 1.5 inches of the
first GTLREF Pin
ITP_TMS
ITP_TDO
ITP_TCK
CPU STRAPPING RESISTORS
2/3*Vccp
C34
C33
220p
220p
2/3*Vccp
C21
C22
220p
220p
CPU ITP BLOCK
R22 39
R23 75
R25 680
CLOSED TO SOCKET478
PROCHOT#
CPU_GD
HBR#0
CPURST#
THERMTRIP#
BPM#0
BPM#1
BPM#4
BPM#5
ITP_TDI
ITP_TRST#
CPU_GD
CPURST#
CPUSLP#
CLOSED TO SOCKET478
STPCLK#
CPUSLP#
SMI#
HINIT#
FERR#
A20M#
INTR
NMI
IGNNE#
Title
Size Document Number Rev
Date: Sheet
R11 62
R62 62
R39 49.9
R63 49.9
R41 62
R16 49.9
R17 49.9
R19 49.9
R18 49.9
R40 150
R24 150
R10 56
R5 56
R6 56
R12 56
R21 62
RN2
7 8
5 6
3 4
1 2
56
MICRO-STAR INT'L CO.,LTD.
mPGA478 CPU-1
MS-6706 0A
2
R57
49.9
C40
R58
1u
100
VCCP
R9
X_49.9-1%
R8
X_100-1%
VCCP
VCCP
VCCP
VCCP
X_1000p-0805C53
X_1000p-0805C44
X_0.022uC9
VCCP
VCCP
of
432Tuesday, May 21, 2002
1
8
7
6
5
4
3
2
1
VCC
VSS
VCC
VSS
F13
VCC
VSS
G21G6G24
F15
F17
VCC
VCC
VSS
VSS
G3H1H23
F19
VCC
VSS
VCC_VID
F9
VCC
VSS
VSS
AF4
VCC-VID
VSS
H26H4J2
AF3
VSS
AE23
VCC-VIDPRG
VSS
VSS
J22
J25J5K21
VCC-IOPLL
VSS
AD20
VSS
VCCA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PGA-S478-F02
AD22
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24
C42
X_10u-1206
C39
X_10u-1206
C41
22u-1206
L13 4.7u-10%
L12 4.7u-10%
C38
22u-1206
VCCP
CPU VOLTAGE BLOCK
VCCP
D D
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AB10
AB12
AB14
C C
AB16
AB18
AB20
AB21
AB24
AC11
AC13
AC15
AC17
AC19
AC22
AC25
D10
A11
A13
A15
A17
A19
A21
A24
A26
AA1
AA4
AA7
AA9
AB3
AB6
AB8
AC2
AC5
AC7
AC9
AD1
A10
A12
A14
A16
A18
A20A8AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19B7B9
C10
C12
C14
C16
C18
C20C8D11
D13
D15
D17
D19D7D9
E10
E12
E14
E16
E18
U2B
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A3
VSS
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD10
AD12
AD14
AD16
AD18
AD21
AD4
AD23
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B23
B20
B26B4B8
C11
C13
C15
C17C2C19
C22
C25C5C7C9D12
D14
D16
D18
D20
D21D3D24D6D8E1E11
E13
E15
E17
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E19
E23
E7E9F10
E4
E26
E20E8F11
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F12
F14
F16
F18F2F22
F25F5F8
B B
CPU DECOUPLING CAPACITORS
VCCP
CB18
10u-1206
CB21
10u-1206
CB24
10u-1206
CB30
10u-1206
CB35
10u-1206
CB40
10u-1206
CB45
10u-1206
CB48
A A
10u-1206
CB51
10u-1206
CB23
10u-1206
PLACE CAPS WITHIN CPU CAVITY
8
7
VCCP
CB20
10u-1206
CB31
10u-1206
CB29
10u-1206
CB36
10u-1206
CB46
10u-1206
CB49
10u-1206
CB50
10u-1206
CB41
10u-1206
CB27
10u-1206
VCCP
CB32
10u-1206
CB37
10u-1206
CB43
10u-1206
CB28
10u-1206
CB33
10u-1206
CB38
10u-1206
CB44
10u-1206
MICRO-STAR INT'L CO.,LTD.
Title
mPGA478 CPU-2
Size Document Number Rev
MS-6706 0A
6
5
4
3
Date: Sheet
2
of
532Tuesday, May 21, 2002
1
5
4
3
2
1
AAD[0..31]
SBA[0..7]
C1XAVSS
C1XAVDD
C4XAVSS
C4XAVDD
HVREF
HPCOMP
HNCOMP
HNCVREF
ST0
ST1
ST2
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
AAD8
AAD9
AAD10
AAD11
AAD12
AAD13
AAD14
AAD15
AAD16
AAD17
AAD18
AAD19
AAD20
AAD21
AAD22
AAD23
AAD24
AAD25
AAD26
AAD27
AAD28
AAD29
AAD30
AAD31
SBA7
SBA6
SBA5
SBA4
SBA3
SBA2
SBA1
SBA0
D D
AC/BE#3
AC/BE#2
AC/BE#1
AC/BE#0
AREQ#
AGNT#
AFRAME#
AIRDY#
ATRDY#
ADEVSEL#
ASERR#
ASTOP#
APAR
RBF#
WBF#
PIPE#
AGP8XDET
ADBIH
ADBIL
SB_STB
SB_STB#
AD_STB0
AD_STB#0
AD_STB1
AD_STB#1
AGPCLK
A1XAVDD
A1XAVSS
A4XAVDD
A4XAVSS
AGPVREF
HDSTBN#3
HDSTBN#2
HDSTBN#1
HDSTBN#0
HDSTBP#3
HDSTBP#2
HDSTBP#1
HDSTBP#0
DBI#3
DBI#2
DBI#1
A27
H27
R25
HDBI#2
HDBI#1
HDBI#0
CT17
X_10u_0805
DBI#0
U6A
F6
F3
H4
K5
C9
A6
G2
G1
G3
G4
H5
H1
H3
E8
F8
D9
D10
B3
C4
B5
A4
K1
L1
C1
D1
B10
M1
B9
A9
B8
A8
M3
M2
F20
F23
K24
P24
F21
F24
L24
N25
SIS645DX
ACBE#1
ACBE#0HDEFER#
ADEVSEL#
APAR
ADSTB0
ADSTB1
ADSTB#1
AGPCLK0
AGPRCOMP
A1XAVDD
A1XAVSS
A4XAVDD
A4XAVSS
HDSTBN#3
HDSTBN#2
HDSTBN#1
HDSTBN#0
HDSTBP#3
HDSTBP#2
HDSTBP#1
HDSTBP#0
HDBI#[0..3] 4
2
AH25
AJ25
AH27
AJ27
U21
T21
P21
N21
J17
B20
B19
A19A7F9B7M6M5M4L3L6L4K6L2K3J3K4J2J6J4J1H6F4F1G6E3F5E2E4E1D3D4C2F7C3E6B2D5D6A3D7C5A5C6D8
CPUCLK13
CPUCLK-13
HDEFER#4
HLOCK#4
HTRDY#4
CPURST#4
CPU_GD4
HBPRI#4
RS#[0..2]4
HADS#4
HITM#4
HIT#4
HDRDY#4
HDBSY#4
HBNR#4
C C
HREQ#[0..4]4
HA#[3..31]4
B B
A A
HREQ#[0..4]
HA#[3..31]
VCCP
VCCP VCCP
R111
75
R108
150
5
CPUCLK1 ACBE#3
CPUCLK-1 ACBE#2
HLOCK#
HTRDY# AREQ#
CPURST# AGNT#
CPU_GD AFRAME#
HBPRI# AIRDY#
HBR#0 ATRDY#
HBR#04
RS#[0..2]
HADS#
HITM# RBF#
HIT# WBF#
HDRDY# PIPE#
HDBSY#
HBNR#
HREQ#4
HREQ#3
HREQ#2 SBSTB
HREQ#1 SBSTB#
HREQ#0
HADSTB#1 ADSTB#0
HADSTB#0
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
HA#5
HA#4
HA#3
HNCOMP
Rds-on(n) = 10 ohm
HNCVERF = 1/3 VCCP
Rds-on(p) = 56 ohm
HPCVERF = 2/3 VCCP
HD#[0..63]4
CB105
0.01u
CB98
0.01u
place this capacitor
under 650 solder side
R106
R94
110
HADSTB#14
HADSTB#04
20
AJ26
CPUCLK
AH26
CPUCLK#
U26
DEFER#
U24
HLOCK#
V26
HTRDY#
C20
CPURST#
D19
CPUPWRGD
T27
BPRI#
U25
W26
W28
W29
W24
W25
AD24
AA24
AF26
AE25
AH28
AD26
AG29
AE26
AF28
AC24
AG28
AE29
AD28
AC25
AD27
AE28
AF27
AB24
AB26
AC28
AC26
AC29
AA26
AB28
AB27
AA25
AA29
AA28
BREQ0#
T24
RS#2
T26
RS#1
U29
RS#0
V28
ADS#
T28
HITM#
U28
HIT#
DRDY#
V24
DBSY#
V27
BNR#
HREQ#4
HREQ#3
HREQ#2
HREQ#1
Y27
HREQ#0
HASTB#1
HASTB#0
HA#31
HA#30
HA#29
HA#28
HA#27
HA#26
HA#25
HA#24
HA#23
HA#22
HA#21
HA#20
HA#19
HA#18
HA#17
HA#16
HA#15
HA#14
HA#13
HA#12
HA#11
HA#10
HA#9
HA#8
HA#7
HA#6
Y26
HA#5
Y24
HA#4
Y28
HA#3
HD#63
HD#62
HD#61
HD#60
B21
F19
A21
E19
HD#63
HD#62
HD#61
HD#60
HD#59
R98
150
R102
75
4
RS#2 ASERR#
RS#1 ASTOP#
RS#0
HD#[0..63]
HVREF
CB93
0.1u
HVREF0
HVREF1
HVREF2
C4XAVSS
C4XAVDD
HVREF3
C1XAVSS
C1XAVDD
HOST
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
HD#53
HD#52
HD#51
HD#50
D22
D20
B22
C22
B23
A23
D21
F22
D24
D23
HD#58
HD#57
HD#56
HD#55
HD#54
HD#53
HD#52
HD#51
HD#50
HD#49
CB88
0.01u
HNCVREF
CB90
0.01u
ST0
ST1
ST2
AAD0
AAD1
AAD2
AAD3
AAD4
AAD5
AAD6
AAD7
HVREF4
HPCOMP
HNCOMP
HNCOMPVREF
AAD8
650-1
HD#49
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#34
HD#33
HD#32
C24
B24
E25
E23
D25
A25
C26
B26
B27
D26
B28
E26
F28
G25
F27
F26
G24
H24
HD#48
HD#47
HD#46
HD#45
HD#44
HD#43
HD#42
HD#41
HD#40
HD#39
HD#38
HD#37
HD#36
HD#35
HD#33
HD#32
HD#34
COST DOWN
CB83
0.01u
X_COPPER_0
L17
0
CP5
1 2
C1XAVDD
C1XAVSS
AAD9
HD#31
G29
J26
HD#31
HD#30
AAD10
AAD11
HD#30
HD#29
G26
HD#29
AAD12
AAD13
HD#28
HD#27
J25
H26
HD#28
HD#27
VCC3
CT16
X_10u_0805
AAD14
HD#26
G28
H28
HD#26
HD#25
AAD15
HD#25
J24
HD#24
3
AAD16
AAD17
HD#24
HD#23
K28
HD#23
AAD18
HD#22
J29
HD#22
HD#21
AAD19
HD#21
K27
AAD20
HD#20
J28
HD#20
HD#19
AAD21
HD#19
M24
AAD22
HD#18
L26
HD#18
HD#17
AAD23
AAD24
HD#17
HD#16
K26
L25
HD#16
C4XAVDD
C4XAVSS
L28
HD#15
AAD25
AAD26
AAD27
AAD28
AAD29
AGP
HD#15
HD#14
HD#13
HD#12
HD#11
M26
P26
L29
N24
HD#14
HD#13
HD#12
HD#11
AAD30
HD#10
N26
M27
HD#9
HD#10
AAD31
HD#9
HD#8
N28
HD#8
P27
HD#7
SBA7
HD#7
HD#6
SBA6
HD#6
N29
CB82
0.01u
SBA5
SBA4
SBA3
HD#5
HD#4
HD#3
R24
R28
M28
P28
HD#5
HD#4
HD#3
HD#2
L16
80
CP6
1 2
X_COPPER_0
SBA2
HD#2
HD#1
R26
C7
SBA1
HD#1
R29
HD#0
SBA0
AGPRCOMP
AGPVSSREF
HD#0
E21
HDBI#3
VCC3
ACBE#[0..3]
ST[0..2]
ADSTB[0..1]
ADSTB#[0..1]
AREQ# 15
AGNT# 15
AFRAME# 15
AIRDY# 15
ATRDY# 15
ADEVSEL# 15
ASERR# 15
ASTOP# 15
SBSTB 15
SBSTB# 15
AGPCLK0 3
AVREFGC
HDSTBN#3 4
HDSTBN#2 4
HDSTBN#1 4
HDSTBN#0 4
HDSTBP#3 4
HDSTBP#2 4
HDSTBP#1 4
HDSTBP#0 4
APAR 15
RBF# 15
WBF# 15
PIPE# 15
AAD[0..31] 15
SBA[0..7] 15
ACBE#[0..3] 15
ST[0..2] 15
ADSTB[0..1] 15
ADSTB#[0..1] 15
VDDQ
R145
60.4
VCC3
VCC3
CT23
X_10U_0805
CT25
X_10u_0805
1
AVREFGC 15
632Tuesday, May 21, 2002
of
C94
0.01u
COST DOWN
CB123
0.1u
L27
0
CB121
0.01u
1 2
X_COPPER_0
L28
80
CB127
0.01u
CP12
1 2
X_COPPER_0
CP11
A1XAVDD
A1XAVSSHPCOMP
A4XAVDD
CB125
0.1u
A4XAVSS
MICRO-STAR INT'L CO.,LTD.
Title
SIS645/650-1
Size Document Number Rev
MS-6706 0A
Date: Sheet
5
4
3
2
1
MA7
MA8
MA5
MA6
RN250
D D
Rs place close to DIMM1
MA14
MA13
MA9
RN220
U6B
RMD1 MD1 MD0
RMD5 MD5 MD1
RMD4 MD4 MD2
RMD0 MD0 MD3
RMD6 MD6 MD4
RMD2 MD2 MD5
RDQM0 DQM0 MD6
RDQS0 DQS0 MD7
RMD9 MD9 DQM0
RMD8 MD8 DQS0
RMD7 MD7 MD8
RMD3 MD3 MD9 MA2
RMD11 MD11 MD10
RMD10 MD10 MD11
RMD15 MD15 MD12
RMD14 MD14 MD13
RDQM1 DQM1 MD14 MA7
RMD13 MD13 MD15 MA8
RDQS1 DQS1 DQM1
RMD12 MD12 DQS1 MA10 RMA10
RMD21 MD21 MD16 MA11 RMA11
C C
B B
A A
RMD17 MD17 MD17 MA12 RMA12
RMD16 MD16 MD18 MA13
RMD20 MD20 MD19 MA14
RMD22 MD22 MD20
RMD18 MD18 MD21 SRAS# RSRAS#
RDQM2 DQM2 MD22 SCAS# RSCAS#
RDQS2 DQS2 MD23 SWE# RSWE#
RMD28 MD28 DQM2
RMD24 MD24 DQS2
RMD23 MD23 MD24
RMD19 MD19 MD25
RMD31 MD31 MD26
RMD27 MD27 MD27
RMD30 MD30 MD28
RMD26 MD26 MD29
RDQM3 DQM3 MD30
RDQS3 DQS3 MD31
RMD25 MD25 DQM3
RMD29 MD29 DQS3
RMD37 MD37 MD32 CKE0
RMD33 MD33 MD33 CKE1
RMD36 MD36 MD34 CKE2
RMD32 MD32 MD35 CKE3
RMD38 MD38 MD36
RMD34 MD34 MD37
RDQM4 DQM4 MD38
RDQS4 DQS4 MD39
RMD44 MD44 DQM4
RMD40 MD40 DQS4
RMD35 MD35 MD40 SDCLK
RMD39 MD39 MD41
RDQS5 DQS5 MD42 FWDSDCLKO
RDQM5 DQM5 MD43
RMD41 MD41 MD44
RMD45 MD45 MD45
RMD47 MD47 MD46
RMD43 MD43
RMD42 MD42 DQS5
RMD55 MD55 MD48
RDQS6 DQS6 MD49
RMD54 MD54 MD50
RDQM6 DQM6 MD51 DDRAVDD
RMD53 MD53 MD52
RMD52 MD52 MD53
RMD49 MD49
RMD48 MD48 MD55
RMD56 MD56 DQM6
RMD60 MD60 DQS6 DDRVREFA
RMD51 MD51 MD56 DDRVREFB
RMD50 MD50 MD57
RMD62 MD62
RDQM7 DQM7 MD59 DDRAVDD
RMD57 MD57
RMD61 MD61 MD61
RMD63 MD63
RMD58 MD58
RDQS7 DQS7
RN5
10
RN7
10
RN9
10
RN13
10
RN11
10
RN18
10
RN20
10
RN26
10
RN32
10
RN29
10
RN41
10
RN43
10
RN45
10
RN48
10
RN51
RN56
10
RN53
10
RN60
10
RN63
10
RN66
10
10
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8
AJ23
MD0
AG22
MD1
AH21
MD2
AJ21
MD3
AD23
MD4
AE23
MD5
AF22
MD6
AF21
MD7
AD22
DQM0
AH22
DQS0/CSB#0
AD21
MD8
AG20
MD9
AE19
MD10
AF19
MD11
AE21
MD12
AD20
MD13
AD19
MD14
AH19
MD15
AF20
DQM1
AH20
DQS1/CSB#1
AF18
MD16
AG18
MD17
AH17
MD18
AD16
MD19
AD18
MD20
AD17
MD21
AF17
MD22
AJ17
MD23
AE17
DQM2
AH18
DQS2/CSB#2
AD14
MD24
AG14
MD25
AJ13
MD26
AE13
MD27
AJ15
MD28
AF14
MD29
AD13
MD30
AF13
MD31
AH13
DQM3
AH14
DQS3/CSB#3
AD10
MD32
AH10
MD33
AE9
MD34
AD8
MD35
AG10
MD36
AF10
MD37
AH9
MD38
AF9
MD39
AD9
DQM4
AJ9
DQS4/CSB#4
AH5
MD40
AG4
MD41
AE5
MD42
AH3
MD43
AG6
MD44
AF6
MD45
AF5
AH4
AE4
AD6
AE2
AC5
AG2
AG1
AC6
AD4
AB6
AD3
AA6
AB3
AC4
AE1
AD2
AC1
AB4
AC2
AF4
AJ3
AF3
AF2
MD46
MD47
DQM5
DQS5/CSB#5
MD48
MD49
MD50
MD51
MD52
MD53
MD54
MD55
DQM6
DQS6/CSB#6
MD56
MD57
MD58
MD59
MD60
MD61
MD62
MD63
DQM7
DQS7/CSB#7
MD47RMD46 MD46
DQM5 SDAVDD
MD54
MD58
MD60
MD62RMD59 MD59
MD63
DQM7
DQS7
650-2
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
SRAS#
SCAS#
SWE#
CS#0
CS#1
CS#2
CS#3
CS#4
CS#5
CKE0
CKE1
CKE2
CKE3
CKE4
CKE5
S3AUXSW#
SDCLK
FWDSDCLKO
SDRCLKI
SDAVDD
SDAVSS
DDRAVDD
DDRAVSS
DDRVREFA
DDRVREFB
DRAM_SEL
AH11
AF12
AH12
AG12
AD12
AH15
AF15
AH16
AE15
AD15
AF11
AG8
AJ11
AG16
AF16
AH8
AJ7
AH7
AE7
AF7
AH6
AJ5
AF8
AD7
AB2
AA4
AB1
Y6
AA5
Y5
Y4
<---
AA3
--->
AD11
AE11
Y1
Y2
AA1
AA2
AJ19
AH2
R157 4.7K
W3
R133
CS-0
CS-1
CS-2
CS-3
MA0
MA1
MA3
MA4
MA5
MA6
MA9
SIS645DX
RMA7
78
RMA8
56
RMA5
34
RMA6
12
78
RMA14
56
RMA13
34
RMA9
12
Rs place close to DIMM1
R76 0
12
34
56
78
RN360
R77
R93 0
R87 0
R99 0
R107 0
R103 0
0
RN49 0
CKE: Open Drain
S3AUXSW#
R215 4.7K
33
C88
10p_0603
HI: DDR
DDRAVSS
RMA0
RMA1
RMA2
RMA3
RMA4
78
56
34
12
VCC3SBY
FWDSDCLKO 3
RMD[0..63]
RDQM[0..7]
RDQS[0..7]
RMA[0..14]
RCS-[0..3]
CKE[0..3]
RCS-0
RCS-2
RCS-1
RCS-3
S3AUXSW# 27
SDCLK 3
SDAVSS
RSRAS# 10,11
RSCAS# 10,11
RSWE# 10,11
SDAVDD
CB135
0.1u
RMD[0..63] 10,11
RDQM[0..7] 10,11
RDQS[0..7] 10,11
RMA[0..14] 10,11
RCS-[0..3] 10,11
CKE[0..3] 10
DDRVREFA
DDRVREFB
CB141
0.1u
CB136
0.01u
CB100
0.01u
CB103
0.01u
CB129
0.01u
CB128
0.01u
CB142
0.01u
L29
80
VCCM
R110
150
R114
150
VCCM
R141
150
R140
150
VCC3
L30
80
VCC3VCC3SBY
MICRO-STAR INT'L CO.,LTD.
Title
SIS645/650-2
Size Document Number Rev
MS-6706 0A
5
4
3
2
Date: Sheet
1
of
732Tuesday, May 21, 2002
5
4
3
2
1
NOTE: This p a ge is for univ ersal PCB design( suitable for both 645 or 650)
NB Hardware Trap Table
0
DLLEN#
DRAM_SEL
D D
ZAD[0..15]12
ZSTB[0..1]12
ZSTB-[0..1]12
C C
VCC1_8
B B
ZAD[0..15]
ZSTB[0..1]
ZSTB-[0..1]
CB140
R156
0.1u
150
R151
150
ZVREF
CB139
0.1u
VSSZCMP
Z1XAVSS
Z4XAVSS
TRAP0
TRAP1
CSYNC
RSYNC
LSYNC
ZCLK0
ZCLK03
ZUREQ12
ZDREQ12
ZUREQ
ZDREQ
ZSTB0
ZSTB-0
ZSTB1
ZSTB-1
ZAD0
ZAD1
ZAD2
ZAD3
ZAD4
ZAD5 INTA#
ZAD6
ZAD7
ZAD8 CSYNC
ZAD9 RSYNC
ZAD10 LSYNC
ZAD11
ZAD12
ZAD13 VCOMP
ZAD14 VRSET
ZAD15 VVBWN ENTEST
ZVREF
VDDZCMP
ZCMP_N
ZCMP_P DACAVSS1
Z1XAVDD DCLKAVSS
enable PLL disable PLL
SDR DDR
normal NB debug mode
TV selection, NTSC/PAL(0/1) 0
enable VB
enable VGA interface
enable panel link
U6C
SIS645DX
V3
ZCLK
U6
ZUREQ
U1
ZDREQ
T3
ZSTB0
T1
ZSTB#0
P1
ZSTB1
P3
ZSTB#1
T4
ZAD0
R3
ZAD1
T5
ZAD2
T6
ZAD3
R2
ZAD4
R6
ZAD5
R1
ZAD6
R4
ZAD7
P4
ZAD8
N3
ZAD9
P5
ZAD10
P6
ZAD11
N1
ZAD12
N6
ZAD13
N2
ZAD14
N4
ZAD15
U3
ZVREF
V5
VDDZCMP
U4
ZCMP_N
U2
ZCMP_P
V6
VSSZCMP
W1
Z1XAVDD
W2
Z4XAVDD ECLKAVSS
Z1XAVSS
V2
Z4XAVDD
V1
Z4XAVSS
PCIRST1#
PCIRST1#24,27
PWRGD13,27
AUXOK13
PWRGD
AUXOK
1
HyperZip
650-3
PCIRST#
PWROK
AUXOK
Y3W4W6
VGA
Stereo
Glass
TRAP1
D11
TRAP1
TRAP0
E10
Default
1(DDR)
TESTMODE2
TESTMODE1
TESTMODE0
A10
F11
C11
0
0
0
1
0
DLLEN#
E11
F10
ENTEST
ENTEST
embedded pull-low
(30~50K Ohm)
yes
yes
yes
C15
VOSCI
A12
ROUT
B13
GOUT
A13
BOUT
F13
HSYNC
E13
VSYNC
D13
VGPIO0
D12
VGPIO1
B11
INT#A
E12
CSYNC
A11
RSYNC
F12
LSYNC
E14
VCOMP
D14
VRSET
F14
VVBWN
B12
DACAVDD1
C12
DACAVSS1
C13
DACAVDD2
C14
DACAVSS2
B15
DCLKAVDD
A15
DCLKAVSS
B14
ECLKAVDD
A14
ECLKAVSS
for 650 only
RSYNC
TRAP1
CSYNC
LSYNC
REFCLK0
DACAVDD1 PWRGD
DACAVSS1
DACAVDD1
DCLKAVDD
ECLKAVDD
R144 4.7K
R137 4.7K
R171 4.7K
R170 4.7K
REFCLK0 3
INTA# 12,15,16
CSYNC 15
RSYNC 15
LSYNC 15
AUXOK
VCC3
R136 4.7K
C99 0.1u
C215 0.1u
VCC3
COST DOWN
L33
0
VCC3
A A
5
L32
0
COST DOWN
C93
0.1u
0.1u
C96
Z1XAVDD
Z1XAVSS
Z4XAVDD
Z4XAVSS
VCC1_8
4
L31
0
COST DOWN
C97
0.1u
R153 56
R152 56
VDDZCMP
ZCMP_N
ZCMP_P
VSSZCMP
3
DCLKAVDD
DCLKAVSS
ECLKAVDD
ECLKAVSS
CB108
0.1u
L22 80
CB111
0.1u
L24 X_80_0603
L19
80
CP8
1 2
X_COPPER_0
X_80_0603
CP9
1 2
X_COPPER_0
VCC3
CE3
X_10u_0805
L21
VCC3
CE4
X_10u_0805
2
VVBWN
DACAVDD1
DACAVSS1
CB97
CB92
0.1u
80
CP10
VRSETVCOMP
VCC1_8
L25X_80_0603
CE5
X_10u_0805
R120
130
1
0.1u
L26
CB118
1 2
0.1u
X_COPPER_0
MICRO-STAR INT'L CO.,LTD.
Title
SIS645/650
Size Document Number Rev
MS-6706 0A
Date: Sheet
of
832Tuesday, May 21, 2002
5
4
3
2
1
VCCP VCC1_8 VCC3
H21
H22
J16
J20
J21
J22
K16
K17
K18
K19
K20
K21
L20
M20
N20
P20
R20
R21
T20
U20
V20
W20
Y20
Y21
AA20
AA21
AA22
AB21
AB22
L12
L14
L15
L16
L18
M11
M19
N11
P19
R11
T19
U11
V19
W11
W13
W15
W17
P11
U17
IVDD
VSS
U18
IVDD
VSS
J14
IVDD
PVDDZ
VSS
VSS
VSS
VSS
V12
V13
V14
V15
V16
VCCP
AD5
AE10
AE12
AE14
AE16
AE18
AE20
AE22
W18
AA10
AA13
AA14
AA15
AA16
AA17
AB13
AB17
A16
VTT
A17
A18
B16
B17
B18
C16
C17
C18
D15
D16
D17
D18
E15
E16
E17
E18
F15
F16
F17
F18
AB5
AE6
AE8
V10
V11
Y10
Y12
Y14
Y16
Y18
Y19
AA8
AA9
AB8
AB9
K11
K13
L10
N10
P10
R10
T10
T11
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
Y9
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
E5
VDDQ
E7
VDDQ
E9
VDDQ
G5
VDDQ
J5
VDDQ
L5
VDDQ
H8
VDDQ
H9
VDDQ
J8
VDDQ
J9
VDDQ
J10
VDDQ
J13
VDDQ
K9
VDDQ
VDDQ
VDDQ
VDDQ
N9
VDDQ
VDDQ
N5
VDDZ
R5
VDDZ
U5
VDDZ
W5
VDDZ
P9
VDDZ
VDDZ
R9
VDDZ
VDDZ
T9
VDDZ
VDDZ
VDDZ
PVDDP
PVDDP
PVDDP
PVDDP
PVDDP
PVDDP
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
L17
L19
N19
R19
U19
W19
M12
M13
M14
M15
M16
M17
M18
N12
N13
N14
N15
N16
N17
N18
P12
P13
P14
P15
P16
VCC1_8
4
VTT
650-4
Power
VSS
VSS
VSS
VSS
VSS
VSS
VSS
P17
P18
R12
R13
R14
R15
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
R16
R17
R18
T12
T13
T14
T15
T16
T17
T18
U12
U13
U14
U15
U16
D D
VCCM
C C
VDDQ
B B
VCC1_8
A A
5
J15
OVDD
VSS
V17
K15
OVDD
VSS
V18
K10
OVDD
VSS
3
K12
PVDD
B25
K14
PVDD
VSS
C28
M10
PVDD
VSS
C29
PVDD
VSS
VCC3SBY
W10
Y11
PVDDM
VSS
VSS
D27
D28
E28
Y13
PVDDM
PVDDM
VSS
VSS
E29
Y15
Y17
PVDDM
VSS
AF23
AF24
PVDDM
VSS
VSS
AF25
AUX1.8
AUX3.3
VSS
AG24
AG26
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AH23
VSS
AH24
U6D
U10
U9
A20
A22
A24
A26
C19
C21
C23
C25
C27
E20
E22
E24
F25
H25
K25
M25
P25
T25
V25
Y25
AB25
AD25
E27
G27
J27
L27
N27
R27
U27
W27
AA27
AC27
AE27
D29
F29
H29
K29
M29
P29
T29
V29
Y29
AB29
AD29
AF29
AE24
AG25
B4
B6
C8
C10
D2
F2
H2
K2
P2
T2
V4
AD1
AF1
AC3
AE3
AG3
AG5
AG7
AG9
AG11
AG13
AG15
AG17
AG19
AG21
AG23
AJ4
AJ6
AJ8
AJ10
AJ12
AJ14
AJ16
AJ18
AJ20
AJ22
AJ24
AG27
SIS645DX
VCC3SBY
VCC1_8SBY
VCC3SBY
VCCP
CB101
1u
CB99
1u
CB62
1u
CB95
1u
VDDQ
CB134
0.1u
CB137
0.1u
CB133
0.1u
CB132
0.1u
Place these capacitors under 635 solder side
X_0.1u
X_0.1u
CB207
X_0.1u
VCC1_8
X_1u-0805
X_1u-0805
X_1u-0805
X_1u-0805
2
VCCP
CB202
CB204
CB203
X_0.1u
CB216
CB213
CB205
CB210
CB152
1u
CB200
0.1u
VCCM
VCCM
VCC3
CB104
1u
CB182
0.1u
CB187
0.1u
CB106
0.1u
CB84
0.1u
CB57
0.1u
CB107
0.1u
CT21
10u_0805
CT24
10u_0805
17 CAPS
CB206
X_0.1u
CB209
X_0.1u
CB215
X_0.1u
CB212
X_0.1u
MICRO-STAR INT'L CO.,LTD.
Title
Size Document Number Rev
Date: Sheet
VCC1_8SBY
CB143
0.1u
CB94
VCC3SBY
VDDQ
1u
CB122
0.1u
CB217
X_0.1u
CB218
X_0.1u
CB214
X_0.1u
1
CB138
0.1u
CB112
0.1u
VCC3
CB211
X_0.1u
CB208
X_0.1u
SIS645/650-4
MS-6706 0A
of
932Tuesday, May 21, 2002
5
4
3
2
1
RMD[0..63]7,11
RMA[0..14]7,11
RDQM[0..7]7,11
D D
RDQS[0..7]7,11
NOTE:
VDDID IS A TRAP ON THE DIMM
MODULE TO INDICATE:
VDDID
OPEN
GND
MEMORY MUX TABLE:
SDR
CS0
CS1
CS2
CS3
CS4
CS5 CS5
CSB0
CSB1
CSB2
CSB3
C C
CSB4
CSB5
CSB6
CSB7
DDRVREF GEN. & DECOUPLING
VCCM
R33
75
R30
75
B B
A A
CB5
0.01u
CB3
0.01u
CB6
0.1u
5
RMA[0..14] RMA[0..14]
RDQM[0..7] RDQM[0..7]
VCCM
RDQS[0..7] RDQS[0..7]
DIMM1
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VREF
VDDID
VSS
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
WP
SCL
SDA
SA0
SA1
SA2
VSS
VDDQ
VSS
15223054627796
VDDQ
RMD0
2
RMD1
4
RMD2
6
RMD3
8
RMD4
94
RMD5
95
RMD6
98
RMD7
99
RMD8
12
RMD9
13
RMD10
19
RMD11
20
RMD12
105
RMD13
106
RMD14
109
RMD15
110
RMD16
23
RMD17
24
RMD18
28
RMD19
31
RMD20
114
RMD21
117
RMD22
121
RMD23
123
RMD24
33
RMD25
35
RMD26
39
RMD27
40
RMD28
126
RMD29
127
RMD30
131
RMD31
133
RMD32
53
RMD33
55
RMD34
57
RMD35
60
RMD36
146
RMD37
147
RMD38
150
RMD39
151
RMD40
61
RMD41
64
RMD42
68
RMD43
69
RMD44
153
RMD45
155
RMD46
161
RMD47
162
RMD48
72
RMD49
73
RMD50
79
RMD51
80
RMD52
165
RMD53
166
RMD54
170
RMD55
171
RMD56
83
RMD57
84
RMD58
87
RMD59
88
RMD60
174
RMD61
175
RMD62
178
RMD63
179
DDRVREF DDRVREF
1
82
90
92
SMBDAT
91
181
182
183
VSS
DIMM-D184-BK
3111826344250586674818993
104
112
128
136
143
156
164
172
180738467085108
VDD
VDD
VDD
VDD
VDD
VDD
VSS
4
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
124
132
139
145
152
160
120
VDD
148
VDD
168
VDD
184
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
97
107
119
129
149
159
169
177
140
5
14
25
36
56
67
78
86
47
44
45
49
51
134
135
142
144
9
10
101
102
173
167
154
65
63
157
158
71
163
21
111
137
16
76
138
17
75
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC
NC(RESET#)
NC
NC
NC
NC(FETEN)
RAS#
CAS#
WE#
S0#
S1#
NC(S2#)
NC(S3#)
CKE0
CKE1
CK0
CK1
CK2
CK0#
CK1#
CK2#
176
REQUIRED POWER
VDD=VDDQ
VDD!=VDDQ
DDR
CS0
CS1
CS2
CS3
CS4
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
VCCM VCCM
RMA0 RMD4
RMA1 RMD5
RMA2 RMD6
RMA3 RMD7
RMA4 RMD8
RMA5 RMD9
RMA6 RMD10
RMA7 RMD11
RMA8 RMD12
RMA9 RMD13
RMA10 RMD14
RMA13 RMD15
RMA14 RMD16
RMA11 RMA11 RMD19
RMA12 RMA12 RMD20
RDQM0 RMD23
RDQM1 RMD24
RDQM2 RMD25
RDQM3 RMD26
RDQM4 RMD27
RDQM5 RMD28
RDQM6 RMD29
RDQM7 RMD30
RDQS0 RMD33
RDQS1 RMD34
RDQS2 RMD35
RDQS3 RMD36
RDQS4 RMD37
RDQS5 RMD38
RDQS6 RMD39
RDQS7 RMD40
DDRVREF
CB4
0.01u
RSRAS# RSRAS# RMD59
RSRAS#7,11
RSCAS# RSCAS# RMD60
RSCAS#7,11
RSWE# RSWE# RMD61
RSWE#7,11
RCS-0 RCS-2 RMD63
RCS-1 RCS-3
CKE0 WP CKE2
CKE1 SMBCLK CKE3
DDRCLK1
DDRCLK8
DDRCLK2
DDRCLK-1
DDRCLK-8
DDRCLK-2
RCS-[0..3]7,11
DDRCLK[0..8]3
DDRCLK-[0..8]3
RCS-[0..3]
CKE[0..3]
CKE[0..3]7
DDRCLK[0..8]
DDRCLK-[0..8]
116
VDDQ
VSS
100
VDDQ
VSS
VDDQ
VSS
VDDQ
VDDQ
VDDQ
addr =
1010000b
VSS
VSS
VSS
VDDQ
VSS
RMD[0..63]
VCCM
DIMM2
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VREF
VDDID
VSS
VDDQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
WP
SCL
SDA
SA0
SA1
SA2
VSS
VDDQ
VSS
15223054627796
VDDQ
2
4
6
8
94
95
98
99
12
13
19
20
105
106
109
110
23
24
28
31
114
117
121
123
33
35
39
40
126
127
131
133
53
55
57
60
146
147
150
151
61
64
68
69
153
155
161
162
72
73
79
80
165
166
170
171
83
84
87
88
174
175
178
179
1
82
90
92
91
181
182
183
VSS
DIMM-D184-BK
3111826344250586674818993
RMD0
RMD1
RMD2
RMD3
RMD17
RMD18
RMD21
RMD22
RMD31
RMD32
RMD41
RMD42
RMD43
RMD44
RMD45
RMD46
RMD47
RMD48
RMD49
RMD50
RMD51
RMD52
RMD53
RMD54
RMD55
RMD56
RMD57
RMD58
RMD62
R149 4.7K
WP
SMBCLK
SMBDAT
DIMM DECOUPLING
VCCM VCCM
CB14
0.1u
CB76
0.1u
CB56
0.1u
CB131
0.1u
CB119
0.1u
CB91
0.1u
CB66
0.1u
CB25
0.1u
CB85
0.1u
VCCM
SMBCLK 3,13,27
SMBDAT 3,13,27
VCCM
CB19
0.1u
CB39
0.1u
CB109
0.1u
CB69
0.1u
CB115
0.1u
104
112
128
136
143
156
164
172
180738467085108
VDD
VDD
VDD
VDD
VDD
VDD
120
VDD
148
VDD
168
VDD
184
RMA0
RMA1
RMA2
RMA3
RMA4
RMA5
RMA6
RMA7
RMA8
RMA9
RMA10
RMA13
RMA14
RDQM0
RDQM1
RDQM2
RDQM3
RDQM4
RDQM5
RDQM6
R73 8.2KR75 8.2K
RDQM7
RDQS0
RDQS1
RDQS2
RDQS3
RDQS4
RDQS5
RDQS6
RDQS7
DDRCLK0
DDRCLK7
DDRCLK3
DDRCLK-0
DDRCLK-7
DDRCLK-3
48
43
41
130
37
32
125
29
122
27
141
118
115
103
59
52
113
97
107
119
129
149
159
169
177
140
5
14
25
36
56
67
78
86
47
44
45
49
51
134
135
142
144
9
10
101
102
173
167
154
65
63
157
158
71
163
21
111
137
16
76
138
17
75
VDDSPD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
BA0
BA1
BA2
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
NC
NC(RESET#)
NC
NC
NC
NC(FETEN)
RAS#
CAS#
WE#
S0#
S1#
NC(S2#)
NC(S3#)
CKE0
CKE1
CK0
CK1
CK2
CK0#
CK1#
CK2#
VSS
176
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
116
124
132
139
145
152
160
VDDQ
VDDQ
addr =
1010001b
VSS
VSS
100
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VCCM
CKE3
CKE2
CKE0
CKE1
3
RN16
1 2
3 4
5 6
7 8
470
2
MICRO-STAR INT'L CO.,LTD.
Title
DDR1 & DDR2
Size Document Number Rev
MS-6706 0A
Date: Sheet
1
of
10 32Tuesday, May 21, 2002
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