MSI MS-6702 Schematics 00B

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Title Page

MS-6702 VER:0B ATX

*AMD PGA 754 K8-Processor (DDR 333)

D D

*VIA K8T400M / VT8235 Chipset

(AGP 8X / VLink 8X)
*Winbond 83697HF-VF LPC I/O
*VT6306 1394a OHCI Link Layer Controller
*BCM 5702 Giga/100/10 Bit LAN Support
*PDC20376 Serial ATA Controller
*USB 2.0 support (integrated into VT8235)
*Vcore Jumpless support
*ALC650/CMI9760 6 channel S/W Audio

C C

*DDR DIMM * 3
*AGP SLOT * 1 ( 8X )
*PCI SLOT * 6

B B

Note :

B = Support Blue-Tooth Header .
C = Support ICS950402 Clock-Gen .
F = Support BroadCom 10/100 bit LAN BCM4401 .
G = Support BroadCom Giga-bit LAN BCM5702 .
H = Support VIA-1394 VT6306 .
M = Support MS1_#2 PCI Arbitor .
S = Support Promise Serial-ATA PDC20375 .

A A

Cover Sheet 1
Block Diagram

Clock Synthesizer & MS1 7
System Memory

DDR Terminations R & C
DDR Damping R & Bypass Cap.
NB VIA K8T400M/VER:0.4 (HT)
K8 Vcore
AGP SLOT 8X
VT8235
PCI Connectors * 6
BUCK Cap. / DLED
ALC650/CMI9760 6 channel S/W Audio
Serial ATA Controller PDC20375
IDE ATA 66/100 Connectors * 2
1394 Controller VT6306
SATA & 1394 POWER
Front USB Port *1 & Blue-Tooth
Rear USB Port *2
LPC I/O W83697HF & Floppy
Hardware monitor & FAN
BIOS ROM & Com Port Wake-Up
Keyboard/Mouse Connectors
LPT/COM Port
Giga-Bit LAN BCM5702
CPU Vcore Setting
AMD CPU Thermal Protection
ACPI Power & Power-Good Circuit
Power OK Sequence (GAL) & Front Panel
Decoupling Cap.
PCI Clock Diagram
Power Sequence
History 47

DDR DIMM 1 & 2 & 3 8,9

2
3GPIO SPEC
4,5,6AMD K8 -> 754 PGA Socket

10
11
12,13,14
15
16
17,18,19
20,21,22
23
24
25,26
27
28
29
30
31
32
33
34
35
36
37
38
39
40,41
42,43
44
45
46

1. Modify Circuit 6702-0A_0822-91.DSN 08/22/91-> Layout Finished ( Gerber-Out Version ).

1. Modify Circuit 6702-0A_0827A-91.DSN 08/27/91-> Release NEW BOM of ES-BOM for Standar d
( 6702-A20 ).

2. Modify Circuit 6702-0A_1001-91.DSN 10/01/91-> After Pilot-Run ( Didn't release ECR ) .

1. Modify Circuit 6702-0B_1108-91.DSN 11/08/91=> VER:0A -> OB : Modify H/W issue & K8-CPU
& NB-K8T400M & Change H/W Audio to S/W Audio ( Gerber-Out Version ) .

2. Creat new BOM for MS6702/VER:0B , 6702-0B_1108A-91.dsn 11/08/91 .

"6702-A20" ES BOM -> 6702-0A_OPT-A_GA3S => Support Giga-Bit LAN + H/W A udio + VIA1394 + SATA
"6702-A??" ES BOM -> 6702-0A_OPT-B_1A3S => Support 10/100 MBit LAN + H/W Audio + VIA1394 + SATA

Layout Gerber-Out 0822-91

Release ES-BOM

Modify MS6702/VER:0B 10/04/2002

Micro Star Restricted Se cret

MS6702-0B_1108A-91.DSN
Kevin Chen EXT:1793

5

4

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Title

Document Number

1

Cover Sheet

MS-6702

5

Block Diagram

4

3

2

1

D D

AMD K8 Socket 754

HT

A

AGP 8X /Fast Write

C C

G
P

VIA
K8T400M

DDR

DDR * 3 (DIMM2 & 3 Shared )

P
R

6 PCI Slots

B B

1394
Front-Port *2 ,
Back-Port *1

1394 Host
Controller
VT6306

O

PCI-33

AC97 => S/W Audio
ALC650 / 6 channel

AC97

VT8235

VLINK

Dual ATA
100/133

LPC BUS

IDE Slot
==>ATA66,100,133 *2

Serial ATA & IDE
RAID Controller
PDC20375

USB

SUPER I/O
W83697HF

ROM

X BUS

A A

Serial Port *2 ,
IDE Port *1

5

Giga Bit LAN
BCM5702

4

Dual USB 1.1 OHCI
/2.0 EHCI 6 Ports
==> Front-Port *1 ,
Back-Port *2

3

Support *1 Blue-Tooth
Connector ( Share
with USB-Port *1 )

Micro Star Restricted Se cret

Title

Document Number

2

Block Diagram

MS-6702

1

5

4

3

2

1

GPIO FUNCTION

VT8233 GPIO Function Define

PIN NAME

D D

GPO0 (VSUS33)

GPO1/SUSA#(VSUS33)

GPO2/SUSB#(VSUS33)

GPO3/SUSST1#(VSUS33)

GPO4/SUSCLK(VSUS33)

GPO5/CPUSTP#

GPO6/PCISTP#

GPO7/SLP#

GPO8/GPI8/IPBIN0

GPO9/GPI9/IPBIN1

C C

GPO10/GPI10/IPBRDFR

GPO11/GPI11/IPBRDCK

GPO12/GPI12/IPBOUT0

GPO13/GPI13/IPBOUT1

GPO14/GPI14/IPBTDFR

GPO15/GPI15/IPBTDCK

GPO16/SA16/STRAP

GPO17/SA17/STRAP

GPO18/SA18/STRAP

GPO19/SA19/STRAP

B B

GPO20/GPI20

/ACSDIN2/PCS0#/EI

GPO21/GPI21/ACSDIN3

/PCS1#/SLPBTN#

GPO22/GPI22/IOR#

GPO23/GPI23/IOW#

GPO24/GPI24/GPIOA

GPO25/GPI25/GPIOC
GPO26/GPI26/SMBDT2

(VSUS33)
GPO27/GPI27/SMBCK2

(VSUS33)
GPO28/GPI28/

APICD0/APICCS#
GPO29/GPI29/

A A

APICD1/APICACK#

GPO30/GPI30/GPIOD

GPO31/GPI31/GPIOE

5

SBGPO0 ( GLAN_EN )

SUSLED ( Power LED )

SUSB#

SUSST#

CTL_PLED1# ( Power LED )

NA (Exteranl Pull up to VCC3)

SBGPO6 ( 1394_EN )

GNT#5

SBGPO8 ->Vcore Setting ( Hi=CPU
Default , Low=Manual )

NA

SVID0

( Vcore Adjusting )

SVID1 ( Vcore Adjusting )

ROMLOCK

SVID2 ( Vcore Adjusting )

SVID3 ( Vcore Adjusting )

SVID4 ( Vcore Adjusting )

LDT Freq Strapping Bit0

LDT Freq Strapping Bit1

LDT Width (Low=8 Bit)

Fast Command (Low=Disable)

NA

(Exteranl Pull down to GND)

NA

(Exteranl Pull down to GND)

NA

NA

DLED1

DLED2

SMBDATA2/Slave SMBUS

SMBCLK2/Slave SMBUS

NA

NA

DLED3

DLED4

PIN NAME Function defineFunction define

GPI0

GPI1

GPI2/EXTSMI#

GPI3/RING#

GPI4/LID#

GPI5/BATLOW#

GPI6/PME#

GPI7/REQ#5

GPI16/INTRUDER#

GPI17/CPUMISS

GPI18/AOLGP1/THRM#

GPI19/IORDY

4

(Exteranl Pull up to VBAT)NA

ATADET0=>Detect IDE1 ATA100/66

EXTSMI#

RING#

ATADET1=>Detect IDE2 ATA100/66

(Exteranl Pull up to 3VDUAL)

NA

PCI_PME#

(Exteranl Pull up to 3VDUAL)

NA

(Exteranl Pull up to VBAT)

NA

(Exteranl Pull up to 3VDUAL)

NA

THRM#

(Exteranl Pull up to VCC3)NA

3

PCI Routing

DEVICES

PCI SLOT 1

PCI SLOT 2

PCI SLOT 3

PCI SLOT 4

PCI SLOT 5

PCI SLOT 6

CM8738 INT#C

Giga-Bit
LAN

MS1 #1

SETIAL ATA INT#B AD24 SATAPCLK ->

1394 INT#D AD25 1394_PCLK ->

MS1 #2 ( PREQ#5 )

INT#

INT#A
INT#B
INT#C
INT#D

INT#B
INT#C
INT#D
INT#A

INT#C
INT#D
INT#A
INT#B

INT#D
INT#A
INT#B
INT#C

INT#B
INT#C
INT#D
INT#A

INT#A
INT#B
INT#C
INT#D

INT#A AD26

2

W/O MS1 -> Green Color

W/ MS1 -> Red Color

IDSEL

AD16

AD17

AD18

AD19

AD21

AD20

AD23

REQ#/GNT#

PREQ#1
PGNT#1

PREQ#2

( PREQ#9 )

PGNT#2

( PGNT#9 )

PREQ#3
PGNT#3

PREQ#4
PGNT#4

PREQ#5

( PREQ#10 )

PGNT#5

( PGNT#10 )

PREQ#7
PGNT#7

PREQ#8
PGNT#8

PREQ#1
PGNT#1

PREQ#0
PGNT#0

( PREQ#2 )
( PGNT#2 )

( PREQ#11 )
( PGNT#11 )

( PGNT#5 )

Title

Document Number

MICRO-STAR INT'L

No. 69, Li-De St, Jung-He City,

CO.,LTD.

Taipei Hsien, Taiwan
http://www.msi.com.tw

CLOCK

PCICLK1 ->
( R_PCICLK0 )

PCICLK2 ->
( R_PCICLK1 )

PCICLK3 ->
( R_PCICLK2 )

PCICLK4 ->
( R_PCICLK3 )

PCICLK5 ->
( R_PCICLK4 )

PCICLK6 ->
( R_PCICLK5 )

AUD_PCLK ->
( R_PCICLK9 )

GLAN_PCLK ->
( R_PCICLK10 )

MS1_PCLK ->
( R_PCICLKF )

( R_PCICLK13 )

( R_PCICLK12 )
MS2_PCLK ->

( R_PCICLKF )

Micro Star Restricted Secret

GPIO Spec.

MS-6702

Last Revision Date:

星期五, 十一月

Sheet

3 48

1

Rev

0B

08, 2002

of

5

4

3

2

1

VREF routed as 40~50 mils trace wide ,

Space>25 mils

C62

C63

102P

R120 44.2RST
R126 44.2RST

MD[63..0]11

DM[8..0]11

-MDQS[8..0]11

104P

MEMZN
MEMZP

MD63
MD62
MD61
MD60
MD59
MD58
MD57
MD56
MD55
MD54
MD53
MD52
MD51
MD50
MD49
MD48
MD47
MD46
MD45
MD44
MD43
MD42
MD41
MD40
MD39
MD38
MD37
MD36
MD35
MD34
MD33
MD32
MD31
MD30
MD29
MD28
MD27
MD26
MD25
MD24
MD23
MD22
MD21
MD20
MD19
MD18
MD17
MD16
MD15
MD14
MD13
MD12
MD11
MD10
MD9
MD8
MD7
MD6
MD5
MD4
MD3
MD2
MD1
MD0

DM8
DM7
DM6
DM5
DM4
DM3
DM2
DM1
DM0

-MDQS8

-MDQS7

-MDQS6

-MDQS5

-MDQS4

-MDQS3

-MDQS2

-MDQS1

-MDQS0

5

VREF_DDR_CLAW

D D

VDD_25_SUS

Place near CPU in 1" ,

Routed => 5:10/Trace:Space ,

Same Length

C C

B B

A A

AE13

AG12

D14
C14

C13

C11

AC1
AC3

AC2
AD1

AG3

AH3

AH9
AG5
AH5

AJ10

AH11

AJ11

AH15

AJ15

AG11

AJ12
AJ14
AJ16

AG1
AH7

AH13

AJ13

A16
B15
A12
B11
A17
A15

A11
A10

B9

C7

A6
A9

A5
B5

C5

A4
E2
E1
A3
B3
E3

F1
G2
G1

L3

L1
G3

J2

L2
M1

W1
W3

W2

Y1

AE1
AE3

AJ4
AE2
AF1

AJ3
AJ5
AJ6
AJ7

AJ9

R1

A13

A7
C2
H1

AA1

T1

A14

A8
D1

J1

AB1
AJ2
AJ8

VTT_SENSE 40

VTT_SENSE

MEMVREF1
MEMZN

MEMZP

MEMDATA63
MEMDATA62
MEMDATA61
MEMDATA60
MEMDATA59
MEMDATA58
MEMDATA57
MEMDATA56
MEMDATA55
MEMDATA54
MEMDATA53
MEMDATA52
MEMDATA51
MEMDATA50
MEMDATA49
MEMDATA48
MEMDATA47
MEMDATA46
MEMDATA45
MEMDATA44
MEMDATA43
MEMDATA42
MEMDATA41
MEMDATA40
MEMDATA39
MEMDATA38
MEMDATA37
MEMDATA36
MEMDATA35
MEMDATA34
MEMDATA33
MEMDATA32
MEMDATA31
MEMDATA30
MEMDATA29
MEMDATA28
MEMDATA27
MEMDATA26
MEMDATA25
MEMDATA24
MEMDATA23
MEMDATA22
MEMDATA21
MEMDATA20
MEMDATA19
MEMDATA18
MEMDATA17
MEMDATA16
MEMDATA15
MEMDATA14
MEMDATA13
MEMDATA12
MEMDATA11
MEMDATA10
MEMDATA9
MEMDATA8
MEMDATA7
MEMDATA6
MEMDATA5
MEMDATA4
MEMDATA3
MEMDATA2
MEMDATA1
MEMDATA0

MEMDQS17
MEMDQS16
MEMDQS15
MEMDQS14
MEMDQS13
MEMDQS12
MEMDQS11
MEMDQS10
MEMDQS9
MEMDQS8
MEMDQS7
MEMDQS6
MEMDQS5
MEMDQS4
MEMDQS3
MEMDQS2
MEMDQS1
MEMDQS0

U7B

RSVD_MEMADDA15
RSVD_MEMADDA14

RSVD_MEMADDB15
RSVD_MEMADDB14

MEMORY INTERFACE

VTT_A4
VTT_A1
VTT_A2
VTT_A3
VTT_B1
VTT_B2
VTT_B3
VTT_B4

MEMRESET_L

MEMCKEA
MEMCKEB

MEMCLK_H7

MEMCLK_L7

MEMCLK_H6

MEMCLK_L6

MEMCLK_H5

MEMCLK_L5

MEMCLK_H4

MEMCLK_L4

MEMCLK_H3

MEMCLK_L3

MEMCLK_H2

MEMCLK_L2

MEMCLK_H1

MEMCLK_L1

MEMCLK_H0

MEMCLK_L0

MEMCS_L7
MEMCS_L6
MEMCS_L5
MEMCS_L4
MEMCS_L3
MEMCS_L2
MEMCS_L1
MEMCS_L0

MEMRASA_L
MEMCASA_L

MEMWEA_L

MEMBANKA1
MEMBANKA0

MEMADDA13
MEMADDA12
MEMADDA11
MEMADDA10

MEMADDA9
MEMADDA8
MEMADDA7
MEMADDA6
MEMADDA5
MEMADDA4
MEMADDA3
MEMADDA2
MEMADDA1
MEMADDA0

MEMRASB_L
MEMCASB_L

MEMWEB_L

MEMBANKB1
MEMBANKB0

MEMADDB13
MEMADDB12
MEMADDB11
MEMADDB10

MEMADDB9
MEMADDB8
MEMADDB7
MEMADDB6
MEMADDB5
MEMADDB4
MEMADDB3
MEMADDB2
MEMADDB1
MEMADDB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

4

D17
A18
B17
C17
AF16
AG16
AH16
AJ17

AG10
AE8

AE7
D10

C10
E12
E11
AF8
AG8
AF10
AE10
V3
V4
K5
K4
R5
P5
P3
P4

D8
C8
E8
E7
D6
E6
C4
E5

H5
D4
G5

K3
H3

E13
C12
E10
AE6
AF3
M5
AE5
AB5
AD3
Y5
AB4
Y3
V5
T5
T3
N5

H4
F5
F4

L5
J5

E14
D12
E9
AF6
AF4
M4
AD5
AC5
AD4
AA5
AB3
Y4
W5
U5
T4
M3

N3
N1
U3
V1
N2
P1
U1
U2

VTT_DDR_SUS

MCKE0
MCKE1

MEMCLK_H7
MEMCLK_L7
MEMCLK_H6
MEMCLK_L6
MEMCLK_H5
MEMCLK_L5
MEMCLK_H4
MEMCLK_L4

MEMCLK_H1
MEMCLK_L1
MEMCLK_H0
MEMCLK_L0

-MCS3

-MCS2

-MCS1

-MCS0

-MSRASA

-MSCASA

MAA13
MAA12
MAA11
MAA10
MAA9
MAA8
MAA7
MAA6
MAA5
MAA4
MAA3
MAA2
MAA1
MAA0

MAB13
MAB12
MAB11
MAB10
MAB9
MAB8
MAB7
MAB6
MAB5
MAB4
MAB3
MAB2
MAB1
MAB0

MEMCHECK7
MEMCHECK6
MEMCHECK5
MEMCHECK4
MEMCHECK3
MEMCHECK2
MEMCHECK1
MEMCHECK0

MCKE0 8,9,10
MCKE1 8,9,10

MEMCLK_H[7..0]

MEMCLK_L[7..0]

-MCS[3..0]

-MSRASA 8,10

-MSCASA 8,10

-MSWEA 8,10
MEMBANKA1 8,10

MEMBANKA0 8,10

MAA[13..0] 8,10

-MSRASB 8,9,10

-MSCASB 8,9,10

-MSWEB 8,9,10
MEMBAKB1 8,9,10

MEMBAKB0 8,9,10

MAB[13..0] 8,9,10

MEMCHECK[7..0] 11

-MCS[3..0] 8,9,10

MEMCLK_H[7..0] 8,9,10
MEMCLK_L[7..0] 8,10

CLKIP112

CLKIN112

CLKIP012

CLKIN012

CTLIP012
CTLIN012

3

CADIP[0..15]12

VLDT0

VDD_12_A

VDD_12_A

R86 49.9RST
R80 49.9RST

CADIP15

CADIN15

CADIP14

CADIN14

CADIP13

CADIN13

CADIP12

CADIN12

CADIP11

CADIN11

CADIP10

CADIN10

CADIP9

CADIN9

CADIP8

CADIN8

CADIP7

CADIN7

CADIP6

CADIN6

CADIP5

CADIN5

CADIP4

CADIN4

CADIP3

CADIN3
CADIN2

CADIP1

CADIN1

CADIP0

CADIN0

C171

X_0.22u

CTLIP1
CTLIN1

C160

0.22u

U7A

N12-7540010-A10

D29

VLDT0_A6

D27

VLDT0_A5

D25

VLDT0_A4

C28

VLDT0_A3

C26

VLDT0_A2

B29

VLDT0_A1

B27

VLDT0_A0

T25

L0_CADIN_H15

R25

L0_CADIN_L15

U27

L0_CADIN_H14

U26

L0_CADIN_L14

V25

L0_CADIN_H13

U25

L0_CADIN_L13

W27

L0_CADIN_H12

W26

L0_CADIN_L12

AA27

L0_CADIN_H11

AA26

L0_CADIN_L11

AB25

L0_CADIN_H10

AA25

L0_CADIN_L10

AC27

L0_CADIN_H9

AC26

L0_CADIN_L9

AD25

L0_CADIN_H8

AC25

L0_CADIN_L8

T27

L0_CADIN_H7

T28

L0_CADIN_L7

V29

L0_CADIN_H6

U29

L0_CADIN_L6

V27

L0_CADIN_H5

V28

L0_CADIN_L5

Y29

L0_CADIN_H4

W29

L0_CADIN_L4

AB29

L0_CADIN_H3

AA29

L0_CADIN_L3

AB27

L0_CADIN_H2

AB28

L0_CADIN_L2

AD29

L0_CADIN_H1

AC29

L0_CADIN_L1

AD27

L0_CADIN_H0

AD28

L0_CADIN_L0

Y25

L0_CLKIN_H1

W25

L0_CLKIN_L1

Y27

L0_CLKIN_H0

Y28

L0_CLKIN_L0

R27

L0_CTLIN_H1

R26

L0_CTLIN_L1

T29

L0_CTLIN_H0

R29

L0_CTLIN_L0

Close to CPU

VDD_25_SUS

R60

X_1KST

R63

X_1KST

C221

C162

0.22u

0.22u

C230

0.22u

HYPER TRANSPORT - LINK0

VREF routed as 40~50 mils trace wide ,
Space>25 mils

C60
X_104P

C47
X_104P

C48

105P/0805

2

C237

0.22u

VLDT0_B6
VLDT0_B5
VLDT0_B4
VLDT0_B3
VLDT0_B2
VLDT0_B1
VLDT0_B0

L0_CADOUT_H15

L0_CADOUT_L15

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H0

L0_CADOUT_L0
L0_CLKOUT_H1

L0_CLKOUT_L1

L0_CLKOUT_H0

L0_CLKOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

R75

0

VREF_DDR_CLAW

C64
X_104P

Title
Document Number

C169

C161

X_0.22u

0.22u

AH29
AH27
AG28
AG26
AF29
AE28
AF25

CADOP15

N26

CADON15

N27

CADOP14

L25

CADON14

M25

CADOP13

L26

CADON13

L27

CADOP12

J25

CADON12

K25

CADOP11

G25

CADON11

H25

CADOP10

G26

CADON10

G27

CADOP9

E25

CADON9

F25

CADOP8

E26

CADON8

E27

CADOP7

N29

CADON7

P29

CADOP6

M28

CADON6

M27

CADOP5

L29

CADON5

M29

CADOP4

K28

CADON4

K27

CADOP3

H28

CADON3

H27

CADOP2CADIP2

G29

CADON2

H29

CADOP1

F28

CADON1

F27

CADOP0

E29

CADON0

F29

CLKOP1

J26

CLKON1

J27

CLKOP0

J29

CLKON0

K29
N25

P25

CTLOP0

P28

CTLON0

P27

MEM_VREF 8

M icro Star Restricted Secret

K8 DDR & HT

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6702

C222

X_0.22u

VLDT0

VLDT0 5

CADOP[0..15] 12
CADON[0..15] 12CADIN[0..15]12

CLKOP1 12
CLKON1 12
CLKOP0 12
CLKON0 12

CTLOP0 12
CTLON0 12

Last Revision Date:

星期五, 十一月

Sheet

1

C69

4.7u/0805

08, 2002

4 48

of

Rev

0B

5

4

3

VCCA_PLL trace length from the VR1 to the
PGA must be 0.75".

2

1

Place al filters close to the PGA.

Keep all power and signal trce away from
the VR1.

Place a cut in the GND plane around the

D D

LAYOUT: Route VDDA trace approx. 50 mils wide (use 2x25 mil

VDDA_25

traces to exit ball field) and 500 mils long.

FB1 180nH/1210

CPU_VDDA_25

C52

10u/1206

C39

X_0.22u

C74

4.7u/0805

C72

0.22u

VCCA_PLL regulator circuit.

C73
3300p

VCC2_5

R141

Near SB/VT8235

R308 X_0

Q41
2N3904S

1K

R316

4.7K

R307 0

VCC2_5

THRMTRIP_EN# 42
THRM# 18,32

AH25

C46
X_102P

CPU_GD42

C C

-LDTSTOP

PS_ON#A42

PS_ON#A

R91

Q18
2N7002S

VCC2_5

1K

Place near CPU in 1" ,
Routed => 5:10/Trace:Space ,
Same Length

VLDT0

VLDT04

R62 0

R87 44.2RST
R83 44.2RST

C76
102P

C77

102P

VCC2_5

HDT Test Port Signal .

VCC2_5

R130
1K

R135
1K

R131
1K

R125
1K

R139
1K

R70
1K

5

R134
1K

R119
1K

R61
1K

R118
1K

R71
1K

Reserved for test

R137
1K

4

DBREQ_L
DBRDY
TCK
TMS
TDI
TRST_L
TDO

NC_AG18

NC_AH18
NC_AG17
NC_AJ18
NC_D18
NC_B19
NC_C19
NC_D20
NC_C21

VDD_25_SUS

R138
1K

R76
1K

B B

A A

-CPURST42

-LDTSTOP12,17

COREFB_H15

COREFB_L15

Differential , "10:10:5:10:10" .

CPUCLK0_H7

Near CPU in 0.5" .

CPUCLK0_L7

3

L0_REF1
L0_REF0

VDDIO_SENSE40

C75 3900P/X7R

C78 3900P/X7R

R74 820
R64 820

VTT_DDR_SUS

VCC2_5

R52
1K

CPU_PWROK

VDDIO_SENSE

169RST

R85

R133 1K
R124 1K

R73

R53

1K

1KR607 X

NC_AJ23
NC_AH23

DBRDY

TMS
TCK
TRST_L
TDI

NC_C18

NC_A19

NC_AE23
NC_AF23
NC_AF22
NC_AF21

R69
1K

CLKIN_H

CLKIN_L

AJ25
AF20

AE18
AJ27

AF27
AE26

AE12
AF12
AE11

AJ21

AH21

AJ23

AH23

AE24
AF24

C16

AG15

AH17

C15

C18

AJ28
AE23

AF23
AF22
AF21

AG2
AH1

AE21

C20
AG4

AG6
AG9

A23
A24
B23

E20
E17
B21
A21

A19
A28

C1

J3

R3

AA2

D3

B18

C6

AE9

VDDA1
VDDA2

RESET_L
PWROK
LDTSTOP_L

L0_REF1
L0_REF0

COREFB_H
COREFB_L
CORE_SENSE

VDDIOFB_H
VDDIOFB_L
VDDIO_SENSE

CLKIN_H
CLKIN_L

NC_AJ23
NC_AH23

NC_AE24
NC_AF24

VTT_A5
VTT_B5

DBRDY
NC_C15
TMS

TCK
TRST_L
TDI

NC_C18
NC_A19
KEY1

KEY0
NC_AE23

NC_AF23
NC_AF22
NC_AF21

FREE29
FREE31
FREE33
FREE35
FREE1
FREE37
FREE4
FREE38
FREE41
FREE7
FREE11
FREE12
FREE13
FREE14
FREE40

U7C

THERMTRIP_L

THERMDA

THERMDC

NC_AG18
NC_AH18
NC_AG17

NC_AJ18

G_FBCLKOUT_H

G_FBCLKOUT_L

DBREQ_L

NC_D20
NC_C21
NC_D18
NC_C19

NC_B19

NC_AF18

RSVD_SCL
RSVD_SDA

FREE26
FREE28
FREE30
FREE32
FREE34
FREE36
FREE10
FREE18
FREE19
FREE42
FREE24
FREE25
FREE27

2

A20
A26

A27
AG13

VID4

AF14

VID3

AG14

VID2

AF15

VID1

AE15

VID0

AG18
AH18
AG17
AJ18

AH19
AJ19

AE19
D20

C21
D18
C19
B19

A22

TDO

AF18

D22
C22

B13
B7
C3
K1
R2
AA3
F3
C23
AG7
AE22
C24
A25
C9

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

THERMTRIP_CPU_L
THERMDA_CPU

THERMDC_CPU
VID4

VID3
VID2
VID1
VID0

NC_AG18
NC_AH18
NC_AG17
NC_AJ18

FBCLKOUT_H

R88

80.6RST

FBCLKOUT_L

Zdiff = 80 ohm

DBREQ_L
NC_D20

NC_C21
NC_D18
NC_C19
NC_B19

TDO

THERMDA_CPU 39

R123 0

VID[4..0] 38

LAYOUT: Route
FBCLKOUT_H/L differentially
with 20/8/5/8/20 spacing and
trace width. ( In CPU
breakout => routed 5:5:5 )

M icro Star Restricted Secret

K8 HDT & MISC

MS-6702

Last Revision Date:

Sheet

1

星期五, 十一月

08, 2002

5 48

of

Rev

0B

5

4

3

2

1

C611

X_6.8pF/BACK

X_6.8pF/BACK

C92

X_4.7u/0805

C129
224P

C126
224P

EMI

C614

C609

X_6.8pF/BACK

C3

0.22u

X_0.22u

C132
224P

C130
224P

C606

X_6.8pF/BACK

C123

4.7u/0805

C135
224P

C133
224P

C612

X_6.8pF/BACK

C150

4.7u/0805

C139
224P

C137
224P

C600

X_6.8pF/BACK

GND

C159

4.7u/0805

C122
224P

C140
224P

C620

X_6.8pF/BACK

VDD_25_SUS VTT_DDR_SUS

C172

0.22u

C174

X_0.22u

C617

{nopop}

X_6.8pF/BACK

C199

GND

2

{nopop}

X_6.8pF/BACK

C56

X_0.22u

{nopop}

C284

X_0.22u

{nopop}

0.22u

C615

C608

{nopop}

X_6.8pF/BACK

X_6.8pF/BACK

VDD_25_SUS

C1

GND

C605

{nopop}

0.22u

{nopop}

X_6.8pF/BACK

GND

{nopop}

C603

{nopop}

X_6.8pF/BACK

Micro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

K8 POWER & GND

MS-6702

Last Revision Date:

星期五, 十一月

Sheet

1

08, 2002

6 48

of

Rev

0B

U7E

B2

VSS1

AH20

VSS3

AB21

VSS4

W22

VSS5

M23

VSS6

L24

VSS7

AG25

VSS8

AG27

VSS9

AA10

AE16

G20
R20
U20

W20

AA20

AC20

AE20

AG20

AJ20

D21
H21
M21

AD21
AG21

G22

N22
R22
U22

AG29

AA22
AC22
AG22
AH22

AJ22

D23
H23

AB23
AD23
AG23

G24
N24

R24
U24

W24

AA24
AC24
AG24

AJ24

C25
D26

H26
M26

AD26

AF26
AH26

C27
D28

G28
H15

AB17
AD17

G18

AA18
AC18

D19
H19

AB19
AD19

AF19

N20

D2

VSS10

AF2

VSS11

W6

VSS12

Y7

VSS13

AA8

VSS14

AB9

VSS15
VSS16

J12

VSS17

B14

VSS18

Y15

VSS19
VSS20

J18

VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31

F21

VSS32
VSS33

K21

VSS34
VSS35

P21

VSS36

T21

VSS37

V21

VSS38

Y21

VSS39
VSS40
VSS41

B22

VSS42

E22

VSS43
VSS44

J22

VSS45

L22

VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56

F23

VSS57
VSS58

K23

VSS59

P23

VSS60

T23

VSS61

V23

VSS62

Y23

VSS63
VSS64
VSS65
VSS66

E24

VSS67
VSS68

J24

VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77

B25

VSS78
VSS79

B26

VSS80
VSS81
VSS82
VSS83

T26

VSS84

Y26

VSS85
VSS86
VSS87
VSS88
VSS89

B28

VSS90
VSS91
VSS92

F15

VSS187
VSS188
VSS206
VSS207

B16

VSS208
VSS209
VSS210
VSS211
VSS212

F19

VSS213
VSS214

K19

VSS215

Y19

VSS216
VSS217
VSS218
VSS219

J20

VSS220

L20

VSS221
VSS222

GROUND

5

D D

C C

B B

A A

VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
VSS183
VSS184
VSS185
VSS186
VSS189
VSS190
VSS191
VSS192
VSS194
VSS195
VSS196
VSS197
VSS198
VSS199
VSS223
VSS201
VSS202
VSS203
VSS204
VSS205

L28
R28
W28
AC28
AF28
AH28
C29
F2
H2
K2
M2
P2
T2
V2
Y2
AB2
AD2
AH2
B4
AH4
B6
G6
J6
L6
N6
R6
U6
AA6
AC6
AH6
F7
H7
K7
M7
P7
T7
V7
AB7
AD7
B8
G8
J8
L8
N8
R8
U8
W8
AC8
AH8
F9
H9
K9
M9
P9
T9
V9
Y9
AD9
B10
G10
J10
L10
N10
R10
U10
W10
AC10
AH10
F11
H11
K11
Y11
AB11
AD11
B12
G12
AA12
AC12
AH12
F13
H13
K13
Y13
AB13
AD13
AF17
G14
J14
AA14
AC14
AE14
D16
E15
K15
AB15
AD15
AH14
E16
G16
J16
AA16
AC16
AE29
AJ26
E18
F17
H17
K17
Y17

LAYOUT: Place 1 capacitor every 1-1.5"

VCORE

along VDD_CORE perimiter.

C54

VCORE

GNDGND

AC15

H18

H22
H24

G13

AB14

G15

AA15

H16

AB16

G17

AA17

AC17

AE17

AB18
AD18
AG19

G19

AC19

AA19

H20
M20

AB20
AD20

G21

N21
R21
U21

W21

AA21
AC21

M22

AB22
AD22

G23
N23

R23
U23

W23

AA23
AC23

D24

M24

AB24
AD24
AH24

AE25

U7D

L7

VDD1
VDD2
VDD3

B20

VDD4

E21

VDD5
VDD6

J23

VDD7
VDD8

F26

VDD9

N7

VDD10

L9

VDD11

V10

VDD12
VDD13

K14

VDD14

Y14

VDD15
VDD16
VDD17

J15

VDD18
VDD19
VDD20

K16

VDD21

Y16

VDD22
VDD23
VDD24

J17

VDD25
VDD26
VDD27
VDD28

F18

VDD29

K18

VDD30

Y18

VDD31
VDD32
VDD33
VDD34

E19

VDD35
VDD36
VDD39
VDD38

J19

VDD37

F20

VDD40
VDD41

K20

VDD42
VDD43

P20

VDD44

T20

VDD45

V20

VDD46

Y20

VDD47
VDD48
VDD49
VDD50

J21

VDD51

L21

VDD52
VDD53
VDD54
VDD55
VDD56
VDD57
VDD58

F22

VDD59

K22

VDD60
VDD61

P22

VDD62

T22

VDD63

V22

VDD64

Y22

VDD65
VDD66
VDD67

E23

VDD68
VDD69

L23

VDD70
VDD71
VDD72
VDD73
VDD74
VDD75
VDD76

B24

VDD77
VDD78

F24

VDD79

K24

VDD80
VDD81

P24

VDD82

T24

VDD83

V24

VDD84

Y24

VDD85
VDD86
VDD87
VDD88
VDD89

K26

VDD90

P26

VDD91

V26

VDD92

POWER

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO7
VDDIO8

VDDIO9
VDDIO10
VDDIO11
VDDIO12
VDDIO13
VDDIO14
VDDIO15
VDDIO16
VDDIO17
VDDIO18
VDDIO19
VDDIO20
VDDIO21
VDDIO22
VDDIO23
VDDIO24
VDDIO25
VDDIO26
VDDIO27
VDDIO28
VDDIO29
VDDIO30
VDDIO31
VDDIO32
VDDIO33
VDDIO34
VDDIO35
VDDIO36
VDDIO37
VDDIO38
VDDIO39
VDDIO40
VDDIO41
VDDIO42
VDDIO43
VDDIO44
VDDIO45
VDDIO46
VDDIO47
VDDIO48
VDDIO49
VDDIO50

VDDIO6

VDD96
VDD97
VDD98

VDD99
VDD100
VDD101
VDD102
VDD103
VDD104
VDD105
VDD106
VDD107
VDD108
VDD109
VDD110
VDD111
VDD112
VDD113
VDD114
VDD115
VDD116
VDD117
VDD118
VDD119
VDD120
VDD121
VDD122
VDD123
VDD124
VDD125
VDD126
VDD127
VDD128
VDD129
VDD130
VDD131
VDD132
VDD133

VDD93

VDD94

VDD95

VDD_25_SUS

E4
G4
J4
L4
N4
U4
W4
AA4
AC4
AE4
D5
AF5
F6
H6
K6
M6
P6
T6
V6
Y6
AB6
AD6
D7
G7
J7
AA7
AC7
AF7
F8
H8
AB8
AD8
D9
G9
AC9
AF9
F10
AD10
D11
AF11
F12
AD12
D13
AF13
F14
AD14
F16
AD16
D15
R4

N28
U28
AA28
AE27
R7
U7
W7
K8
M8
P8
T8
V8
Y8
J9
N9
R9
U9
W9
AA9
H10
K10
M10
P10
T10
Y10
AB10
G11
J11
AA11
AC11
H12
K12
Y12
AB12
J13
AA13
AC13
H14
AB26
E28
J28

4

VCORE

C180

LAYOUT: Place 6 EMI caps along bot tom right side of Clawhammer,
2 in middle of HT link, and 12 along bottom left side of Claw-hammer.

VCORE VCORE

C619

Place between DIMN1 & 2

VDD_25_SUS

VDD_25_SUS

C87

X_6.8pF

C616

X_6.8pF/BACK

C88
104P

C113

{nopop}

X_0.22u

C86

X_6.8pF

GND

C610

X_6.8pF/BACK

C2
104P

C148

X_4.7u/0805

VCORE

X_6.8pF

C604

C607

X_6.8pF/BACK

C181
104P

X_6.8pF/BACK

C249
104P

C601

X_6.8pF/BACK

C287
104P

GND

LAYOUT: Place beside processor.

C168

C187

C232

{nopop}

X_0.22u

X_4.7u/0805

X_0.22u

In CPU.

C125

C119

224P

224P

C136

C120

224P

224P

3

5

VCC3 VCC3

MSI PCI-Clock delay about 150pS from
PCI clock-input to PCI clock-output .

FRAME#

FRAME#17,20,21,22,25,28,37

STOP#

STOP#17,20,21,22,25,28,37

PREQ#0

PREQ#017

PGNT#0

PGNT#017

PREQ#6

PREQ#620

PGNT#6

PGNT#620

PREQ#7

PREQ#722

D D

VCC3

C768

C769

X_104P

X_104P

FRAME#17,20,21,22,25,28,37

VCC3

C C

C770
X_104P

C771
X_104P

PREQ#1128

PGNT#1128

PGNT#7

PGNT#722

PREQ#8
PGNT#8

VCC3

FRAME#
STOP#

STOP#17,20,21,22,25,28,37

MS2_GNT#
PREQ#9

PGNT#9
PREQ#10

PGNT#10
PREQ#11
PGNT#11

U33

1

FRAME#

2

STOP#

3

SYSREQ#

4

SYSGNT#

5

PCIREQ1#

6

VSS

7

PCIGNT1#

8

PCIREQ2#

9

VCC

10

PCIGNT2#

11

PCIREQ3#

12

PCIGNT3#

13

VC3A

14 15

VC5A VC5B

MS1

B07-00MS102-E18

MSI PCI-Clock delay about 150pS from
PCI clock-input to PCI clock-output .

U26

1

FRAME#

2

STOP#

3

SYSREQ#

4

SYSGNT#

5

PCIREQ1#

6

VSS

7

PCIGNT1#

8

PCIREQ2#

9

VCC

10

PCIGNT2#

11

PCIREQ3#

12

PCIGNT3#

13

VC3A

14 15

VC5A VC5B

M_MS1

B07-00MS102-E18

Reserved for VT8235

PCICLKI
RESET#

PCLCLK0

PCICLK1
PCICLK2

PCICLK3
PCICLK4

AVCC
PCICLKI
RESET#

AVSS

PCLCLK0

PCICLK1

VCC
PCICLK2
PCICLK3
PCICLK4

VC3B

AVCC

AVSS

VC3B

VSS

VSS

VCC

28
27
26
25
24

VSS

23
22
21
20
19
18
17

VSS

16

28
27
26
25
24
23
22
21
20
19
18
17
16

without MS-1

VCC3

RN88

8P4R-4.7K

PGNT#1
PGNT#2
PGNT#3
PGNT#4

PGNT#0
PGNT#5

PREQ#1
PREQ#2
PREQ#3
PREQ#4

PREQ#0

PREQ#5

PCIREQ#2
PCIGNT#2
PCIGNT#5
PCIREQ#5

PCIREQ#5
PCIGNT#5
MS2_REQ#
MS2_GNT#

PCIREQ#2
PCIGNT#2
SATA_REQ#
SATA_GNT#

5

1 2
3 4
5 6

7 8

R489 4.7K
R470 4.7K

RN102

8P4R-2.7K

1 2
3 4
5 6
7 8

R488 2.7K
R469 2.7K

PCIREQ#2 20
PCIGNT#2 20
PCIGNT#5 22
PCIREQ#5 22

PCIREQ#5 22
PCIGNT#5 22

PCIREQ#2 20
PCIGNT#2 20
SATA_REQ# 25
SATA_GNT# 25

VCC

PGNT#117,37
PGNT#217
PGNT#317,21
PGNT#417,21

PGNT#517

PREQ#117,37
PREQ#217
PREQ#317,21
PREQ#417,21

B B

A A

PREQ#517

Add when M/B don't install MS1 .

RN94

7 8

PREQ#2
PGNT#2

5 6

PGNT#5

3 4

PREQ#5

1 2

M-X_8P4R-0

Add when M/B install MS1 .

RN90

PREQ#10

7 8

PGNT#10

5 6

PREQ#5

3 4
1 2

PGNT#5

M_8P4R-0
RN93

7 8

PREQ#9

PGNT#9

5 6

PREQ#2

3 4

PGNT#2

1 2

M_8P4R-0

PGNT#9
PREQ#9
PREQ#10
PGNT#10

PGNT#11
PREQ#11

0 0 0 0
0 0 0
0 0 0
0 0
0 0 0
0 0
0 0

0

***

1
1 1
1 1
1 1 1
1 1
1 1 1
1 1 1
1 1 1 1

ModeA ModeB

***

4

C465 104P

MS1_PCLK
PCIRST2#

R_PCICLK7

R456 33

R_PCICLK8

R457 33

R_PCICLK9

R459 33

R_PCICLK11

C466 X_10P

VCC3

C440 104P

MS2_PCLK
PCIRST2#MS2_REQ#

R_PCICLK12

R390 M_22

R_PCICLK13
R_PCICLK14

R_PCICLK15
R_PCICLK16

VCC3

RN89

M_8P4R-4.7K

1 2
3 4
5 6
7 8

R414 M_4.7K
R413 M_4.7K

ICS950402

Strapping CPU

FS0FS2FS3

FS1

1
1
1 1

1
1 1
1 1

1 1 1

0 0 0
0 0
0 0
0

0 0
0

0

0 0

0 1

1 0
1 1

Pin6 Pin7

HTTCLK0

ModeA In

PCICLK7 PCICLK8 PCICLK9 PCICLK10
ModeA In

4

R_PCICLK9

C699 X_10P

PCIRST2# 17,20,21,22

SBPCLK
SIOPCLK

GLAN_PCLKR_PCICLK10

SBPCLK
SIOPCLK

GLAN_PCLK

PCIRST2# 17,20,21,22

1394_PCLK

1 2
3 4
5 6
7 8

CN24
X_8P4C-10P

1394_PCLK

PGNT#6
PREQ#6
PREQ#8
PGNT#8

PGNT#7
PREQ#7

MHz

100.90

133.90

168.00

202.00

100.20

133.50

166.70

200.40

150.00

180.00

210.00

240.00

270.00

233.33

266.67

300.00

HTTCLK1 HTTCLK2 PCICLK10

SBPCLK 17
SIOPCLK 32

GLAN_PCLK 37

CN25

1 2
3 4
5 6
7 8

X_8P4C-10P

1394_PCLK 28

C437 X_10P

RN108

8P4R-4.7K

1 2
3 4
5 6
7 8

R491 4.7K
R490 4.7K

HTT

PCI

MHz

67.27 33.63

66.95

67.20

67.33

66.80

66.75

66.68

66.80

60.00

60.00

70.00

60.00

67.50

66.67

66.67

75.00

MHz

33.48

33.60

33.67

33.40

33.38

33.34

33.40

33.00

33.00

35.00

30.00

33.75

33.33

33.33

37.50

Pin8 Pin11

HTTCLK1 HTTCLK2 HTTCLK3

PCICLK8 PCICLK9 PCICLK10

3

Clock Synthesizer

CLKVCC3

C379 104P

CLKVCC3

C385 104P

CLKVCC3

C389 104P

CLKVCC3

C398 104P

CLKVCC3

C401 104P

CLKVCC3

C374 104P

CLKVCC3

C388 104P

CLKVCC3

C399 104P

CLKVCC3

C410 104P

CLKVDDA

C409 104P

VCC3

VCC3

FB6 X_120S/0805

*** => Default Setting

ModeC Pin24

01PCICLK6

***

PCI_STOP#

3

46
47

32
33

10

16
15

19
20

29
30

27
38

39
35

34
43

42

Only support in ICS950402

CP28
X_COPPER

U22
ICS950402

I11-9504002-I02

VDD_46
VSS_47

2

VDD_2

5

VSS_5

VDDF
VSSF

9

VDD_9
VSS_10

VDD_16
VSS_15

VDD_19
VSS_20

VDD_29
VSS_30

VSS_27
VDD_38

VSS_39
VDD_35

VSS_34
VDDA

VSSA

CLK_RESET#43

C695

4.7u/0805

PCI33_HT66_0
PCI33_HT66_1
PCI33_HT66_2

24_48MHZ/SEL

PCI33_HT66SEL

R315 X_10K

CLKVDDA

2

FS0

1

FS0/REF0
FS1/REF1
FS2/REF2

XOUT

48MHZ

PCI33_0
PCI33_1
PCI33_2
PCI33_3

PCI33_F
PCI33_4
PCI33_5

SDATA

CPUT_0

CPUC_0

CPUT_1

CPUC_1

PCISTOP

SPREADNC

For EMI

VCC3 VCC

"FS0~FS3" are all internal
pull-up via 100K ohm ..

"48MHZ" is "FS3" in ICS950402 ,
But not in cy28330 .

Mode B ( Set Pin 7,8,11 output
clock -> 33 or 66 MHz )

"24_48MHZ/SEL" Freq.-Out select pin
=> Low->48MHz , Hi->24MHz .
( Internal pull-up via 100K ohm )

FS1

48

FS2

45
3

CLKX1

XIN

CLKX2

4

31

HT_66_0

7

HT_66_1

8

HT_66_2

11
13

R_PCICLK0
R_PCICLK1

14

R_PCICLK2

17

R_PCICLK3

18
23

R_PCICLKF

21

R_PCICLK5 SATAPCLK

22

SEL_24

28

SMBDATA1

26

SMBCLK1

25

SCLK

41
40

37
36

6
24

Mode A ( ICS950402 )

4412

R_PCICLK6

VCC3

C421

C422

104P

104P

C424 X_104P

C505 X_104P

FS0
FS2
FS1

48MHZ

HT_66_0

SEL_24

R295 22
R667 22
R313 22

R332 33

RN125 8P4R-22

R645 22
R646 M_22

R341 33

R_CPU_CLK

-R_CPU_CLK

-SEL_66

R304 10K

R_PCICLK5

FB3 X_120S/0805

CP19

X_COPPER

R301 10K
R309 10K
R302 10K

R331 C_10K

R605 C_10K

R348 10K

2

7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2

R604 X_10K
R622 M_22
R647 X_22

CLKVCC3

CLKVCC3

SB_OSC14
AC_14
APICCLK

C375 10P/X7R

X1 14.318MHZ

C376 10P/X7R

VCLK

RN68

GCLK_NB

8P4R-22

GCLK_SLOT
PCICLK1

PCICLK2
PCICLK3
PCICLK4

PCICLK5R_PCICLK4

SIO48M

R326 15RST
R323 15RST

"-SEL_66" Freq.-Out select pin =>
Low->66MHz , Hi->33MHz .
( Internal pull-up via 100K ohm )

C414

C418

39P

4.7u/0805

SB_OSC14 18
AC_14 24
APICCLK 17

USBCLK_SB48MHZ

SMBDATA1 8,9,18,37
SMBCLK1 8,9,18,37

CPUCLK0_H 5
CPUCLK0_L 5

CLKVCC3

PCICLK6

CLKVCC3

C415
104P

Title
Document Number

1

VCLK
GCLK_NB
GCLK_SLOT

USBCLK_SB
SIO48M
SB_OSC14
APICCLK
AC_14

USBCLK_SB 19

VCLK 17
GCLK_NB 13
GCLK_SLOT 16

PCICLK1 20
PCICLK2 20
PCICLK3 21
PCICLK4 21

PCICLK5 22
SATAPCLK 25

SIO48M 32

PCICLK6 22

Mode C ( Set Pin24 -> Low
= PCICLK Out )

R351 22
R347 M_22

PCICLK1
PCICLK2
PCICLK3
PCICLK4

PCICLK5
SATAPCLK

MS1_PCLK
MS2_PCLK
PCICLK6

VCC3

Decoupling Cap for CPU Clock

R_PCICLKF

CPUCLK0_H
CPUCLK0_L

R360 X_10K
R623 C_10K

Micro Star Restricted Secret

Clock Synthesizer

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MS-6702

1

CN22

7 8
5 6
3 4
1 2

X_8P4C-10P

C400 X_10P

C406 X_10P
C370 X_10P
C383 X_10P
C700 X_10P

CN23

7 8
5 6
3 4
1 2

X_8P4C-10P

C392 X_10P
C394 X_10P

C417 X_10P
C408 X_10P
C701 X_10P

Near CK-Gen in 0.5" .

C395 X_5P/X7R
C393 X_5P/X7R

C698 104P

CLKVCC3

MS1_PCLKR_PCICLKF
MS2_PCLK

Last Revision Date:

星期五, 十一月

08, 2002

Sheet

7 48

Rev

0B

of

5

104P

C35

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP1

-MSWEA

DR_MD[63..0]9,10,11

D D

C C

B B

VDD_25_SUS

R220 4.7K

-MSWEA4,10

DDR_VREF

VREF routed as 40~50
mils trace wide ,
Space>25 mils

C29
X_104P

2
4
6

8
94
95
98
99
12
13
19
20

105
106
109
110

23
24
28
31

114
117
121
123

33
35
39
40

126
127
131
133

53
55
57
60

146
147
150
151

61
64
68
69

153
155
161
162

72
73
79
80

165
166
170
171

83
84
87
88

174
175
178
179

90
63

1

9

101
102

Place 104p and 1000p Cap. near the DIMM

Place near the DIMM

VDD_25_SUS

R72
1KST

A A

R66
1KST

C32
104P

C44
105P/0805

VREF routed as 40~50 mils trace wide ,
Space>25 mils

R67
0

DDR_VREF

C26

C20

X_102P

X_104P

5

VDD_25_SUS

738467085

108

VDD0

VDD1

VDD2

VDD3

VDD4

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

WP(NC)
WE#

VREF
NC2

NC3
NC4

VSS0

VSS1

3111826344250586674818993

MEM_VREF 4

DDR_VREF 9

120

148

168223054627796

VDD5

VDD6

VDD7

VSS2

VSS3

VSS4

VDD8

VSS5

VDDQ0

VSS6

4

SYSTEM MEMORY

104

112

128

136

143

156

164

172

1801582

184

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

184

DDR DIMM

SOCKET

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

100

116

124

132

139

DIMM1 SLAVE ADDRESS
= (1010000X)B = A0

4

VDDQ11

VDDQ12

VDDQ13

PIN

VSS17

VSS18

VSS19

145

152

160

VDDID

VDDQ14

VDDQ15

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A10_AP

CK0(DU)

CK0#(DU)

CK1(CK0)

CK1#(CK0#)

CK2(DU)

CK2#(DU)

NC(RESET#)

VSS20

VSS21

DDR1
DDRDIMM_184

176

N13-1840021-F02

CS0#
CS1#
CS2#
CS3#

SCL
SDA

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
A13

BA0
BA1
BA2

SA0
SA1
SA2

3

-MCS0

157
158
71
163

5
14
25
36
56
67
78
86
47

103

MAA0

48

MAA1

43

MAA2

41

MAA3

130

MAA4

37

MAA5

32

MAA6

125

MAA7

29

MAA8

122

MAA9

27

MAA10

141

MAA11

118

MAA12 MAB12

115

MAA13

167
59

52
113

SMBCLK1

92

SMBDATA1

91
181
182
183

DR_CHECK0

44

DR_CHECK1

45

DR_CHECK2

49

DR_CHECK3

51

DR_CHECK4

134

DR_CHECK5

135

DR_CHECK6

142

DR_CHECK7

144

MEMCLK_H5

16

MEMCLK_L5

17

MEMCLK_H0

137

MEMCLK_L0

138

MEMCLK_H7

76

MEMCLK_L7

75
173

10

MCKE0

21

MCKE1

111

-MSCASA

65

-MSRASA

154

DR_DM0

97

DR_DM1

107

DR_DM2

119

DR_DM3

129

DR_DM4

149

DR_DM5

159

DR_DM6

169

DR_DM7

177

DR_DM8

140

-MCS1

-DR_MDQS0

-DR_MDQS1

-DR_MDQS2

-DR_MDQS3

-DR_MDQS4

-DR_MDQS5

-DR_MDQS6

-DR_MDQS7

-DR_MDQS8

MAA[13..0]

-MCS0 4,10

-MCS1 4,10

-DR_MDQS0 9,10,11

-DR_MDQS1 9,10,11

-DR_MDQS2 9,10,11

-DR_MDQS3 9,10,11

-DR_MDQS4 9,10,11

-DR_MDQS5 9,10,11

-DR_MDQS6 9,10,11

-DR_MDQS7 9,10,11

-DR_MDQS8 9,10,11

MAA[13..0] 4,10

MEMBANKA0 4,10
MEMBANKA1 4,10

SMBCLK1 7,9,18,37
SMBDATA1 7,9,18,37

DR_CHECK[7..0] 9,10,11

MEMCLK_H5 4,10
MEMCLK_L5 4,10
MEMCLK_H0 4,10
MEMCLK_L0 4,10
MEMCLK_H7 4,10
MEMCLK_L7 4,10

MCKE0 4,9,10
MCKE1 4,9,10

-MSCASA 4,10

-MSRASA 4,10

VREF routed as 40~50
mils trace wide ,
Space>25 mils

DDR_VREF

VDD_25_SUS

-MSWEB4,9,10

C51
104P

R213 4.7K

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

-MSWEB

C36
X_102P

WP2

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

102

NC4

Place 104p and 1000p Cap. near the DIMM

DR_DM[8..0]

DR_DM[8..0] 9,10,11

3

2

VDD_25_SUS

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VSS0

VSS1

VSS2

VSS3

VSS4

3111826344250586674818993

DIMM2 SLAVE ADDRESS
= (1010001X)B = A2

2

104

112

128

VDD8

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

DDR DIMM

SOCKET

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

100

116

136

143

156

164

172

1801582

VDDQ8

VDDQ9

VDDQ10

VDDQ11

VDDQ12

VDDQ13

VDDQ14

184

PIN

VSS14

VSS15

VSS16

VSS17

VSS18

VSS19

VSS20

124

132

139

145

152

160

176

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

184

VDDID

VDDQ15

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A10_AP

A11
A12
A13

BA0
BA1

BA2
SCL
SDA

SA0

SA1

SA2
CB0

CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0(DU)

CK0#(DU)

CK1(CK0)

CK1#(CK0#)

CK2(DU)

CK2#(DU)

NC5

NC(RESET#)

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VSS21

M icro Star Restricted Secret

1

VDDSPD

-MCS2

157

-MCS3

158
71
163

-DR_MDQS0

5

-DR_MDQS1

14

-DR_MDQS2

25

-DR_MDQS3

36

-DR_MDQS4

56

-DR_MDQS5

67

-DR_MDQS6

78

-DR_MDQS7

86

-DR_MDQS8

47
103

MAB0

48

A0

MAB1

43

A1

MAB2

41

A2

MAB3

130

A3

MAB4

37

A4

MAB5

32

A5

MAB6

125

A6

MAB7

29

A7

MAB8

122

A8

MAB9

27

A9

MAB10

141

MAB11

118
115

MAB13

167

MEMBAKB0

59

MEMBAKB1

52
113

SMBCLK1

92

SMBDATA1

91
181
182
183

DR_CHECK0

44

DR_CHECK1

45

DR_CHECK2

49

DR_CHECK3

51

DR_CHECK4

134

DR_CHECK5

135

DR_CHECK6

142

DR_CHECK7

144

DIMM2_CK3

16

DIMM2_CK#3

17

DIMM2_CK4

137

DIMM2_CK#4

138

DIMM2_CK5

76

DIMM2_CK#5

75
173

10

MCKE0

21

MCKE1

111

-MSCASB

65

-MSRASB

154

DR_DM0

97

DR_DM1

107

DR_DM2

119

DR_DM3

129

DR_DM4

149

DR_DM5

159

DR_DM6

169

DR_DM7

177

DR_DM8

140

DDR2
DDRDIMM_184

N13-1840021-F02

System Memory : DDR DIMM 1

MS-6702

Last Revision Date:

Sheet

1

-MCS2 4,9,10

-MCS3 4,9,10

MAB[13..0] 4,9,10

MEMBAKB0 4,9,10
MEMBAKB1 4,9,10

VDD_25_SUS

DIMM2_CK3 9
DIMM2_CK#3 9
DIMM2_CK4 9
DIMM2_CK#4 9
DIMM2_CK5 9
DIMM2_CK#5 9

-MSCASB 4,9,10

-MSRASB 4,9,10

星期五, 十一月

8 48

Rev

0B

08, 2002

of

5

SYSTEM MEMORY

VDD_25_SUS

4

3

2

VDD_25_SUS

1

Clock Buffer (DDR)

C183

+

EC60
1000U/6.3V

C184
104P

X_103P

D D

R223 4.7K

C33
104P

DR_MD0
DR_MD1
DR_MD2
DR_MD3
DR_MD4
DR_MD5
DR_MD6
DR_MD7
DR_MD8
DR_MD9
DR_MD10
DR_MD11
DR_MD12
DR_MD13
DR_MD14
DR_MD15
DR_MD16
DR_MD17
DR_MD18
DR_MD19
DR_MD20
DR_MD21
DR_MD22
DR_MD23
DR_MD24
DR_MD25
DR_MD26
DR_MD27
DR_MD28
DR_MD29
DR_MD30
DR_MD31
DR_MD32
DR_MD33
DR_MD34
DR_MD35
DR_MD36
DR_MD37
DR_MD38
DR_MD39
DR_MD40
DR_MD41
DR_MD42
DR_MD43
DR_MD44
DR_MD45
DR_MD46
DR_MD47
DR_MD48
DR_MD49
DR_MD50
DR_MD51
DR_MD52
DR_MD53
DR_MD54
DR_MD55
DR_MD56
DR_MD57
DR_MD58
DR_MD59
DR_MD60
DR_MD61
DR_MD62
DR_MD63

WP3

C58
102P

DR_MD[63..0]8,10,11

C C

B B

VDD_25_SUS

-MSWEB4,8,10

DDR_VREF8

VREF routed as 40~50
mils trace wide ,
Space>25 mils

-MSWEB
DDR_VREF

Place 104p and 1000p Cap. near the DIMM

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

102

NC4

VSS0

VSS1

VSS2

VSS3

VSS4

3111826344250586674818993

104

112

128

VDD8

VDDQ0

VDDQ1

VDDQ2

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

DDR DIMM

SOCKET

VSS5

VSS6

VSS7

VSS8

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

100

116

136

143

156

164

VDDQ9

VDDQ10

VDDQ11

184

PIN

VSS15

VSS16

VSS17

124

132

139

145

172

1801582

VDDQ12

VDDQ13

VSS18

VSS19

152

160

VDDID

VDDQ14

VDDQ15

A10_AP

CK0(DU)

CK0#(DU)

CK1(CK0)

CK1#(CK0#)

CK2(DU)

CK2#(DU)

NC(RESET#)

VSS20

VSS21

176

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

184

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
A13

BA0
BA1

BA2
SCL
SDA

SA0

SA1

SA2
CB0

CB1
CB2
CB3
CB4
CB5
CB6
CB7

-MCS3

157

-MCS2

158
71
163

-DR_MDQS0

5

-DR_MDQS1

14

-DR_MDQS2

25

-DR_MDQS3

36

-DR_MDQS4

56

-DR_MDQS5

67

-DR_MDQS6

78

-DR_MDQS7

86

-DR_MDQS8

47
103

MAB0

48

MAB1

43

MAB2

41

MAB3

130

MAB4

37

MAB5

32

MAB6

125

MAB7

29

MAB8

122

MAB9

27

MAB10

141

MAB11

118

MAB12

115

MAB13

167

MEMBAKB0

59

MEMBAKB1

52
113

SMBCLK1

92

SMBDATA1

91
181
182
183

DR_CHECK0

44

DR_CHECK1

45

DR_CHECK2

49

DR_CHECK3

51

DR_CHECK4

134

DR_CHECK5

135

DR_CHECK6

142

DR_CHECK7

144

DIMM3_CK0

16

DIMM3_CK#0

17

DIMM3_CK1

137

DIMM3_CK#1

138

DIMM3_CK2

76

DIMM3_CK#2

75
173

10

MCKE1

21

MCKE0

111

-MSCASB

65

-MSRASB

154
97

107
119
129
149
159
169
177
140

DDR3
DDRDIMM_184

N13-1840021-F02

-MCS3 4,8,10

-MCS2 4,8,10

VDD_25_SUS

DR_DM0
DR_DM1
DR_DM2
DR_DM3
DR_DM4
DR_DM5
DR_DM6
DR_DM7
DR_DM8

-DR_MDQS0 8,10,11

-DR_MDQS1 8,10,11

-DR_MDQS2 8,10,11

-DR_MDQS3 8,10,11

-DR_MDQS4 8,10,11

-DR_MDQS5 8,10,11

-DR_MDQS6 8,10,11

-DR_MDQS7 8,10,11

-DR_MDQS8 8,10,11

MAB[13..0] 4,8,10

MEMBAKB0 4,8,10
MEMBAKB1 4,8,10

SMBCLK1 7,8,18,37
SMBDATA1 7,8,18,37

DR_CHECK[7..0] 8,10,11

MCKE1 4,8,10
MCKE0 4,8,10

-MSCASB 4,8,10

-MSRASB 4,8,10

DR_DM[8..0] 8,10,11

SMBCLK1
SMBDATA1

MEMCLK_H44,10

CP5 X_COPPER

VDD_25_SUS

VDD_25_SUS

L14

X_0/0805

CP6 X_COPPER

L15

X_0/0805

C176
104P

C185
105P/0805

C152
104P

C153
104P

Near U8

AVDD25

0
0

DIMM2_CK3
DIMM3_CK0
DIMM2_CK4

DIMM3_CK1
DIMM3_CK2
DIMM2_CK5

3
12
23

10

7
22

8

20

9
18
21

DIMM2_CK38 DIMM2_CK#3 8

CBVDD

R129
R128

MEMCLK_H4

R624 120RST
R625 120RST
R626 120RST

R627 120RST
R628 120RST
R629 120RST

U8
ICS93722BF-SSOP28

I12-9372202-I02

VDD
VDD
VDD

AVDD

SCLK
SDATA

CLK_IN

FB_IN

NC
NC
NC

GND

111528

6

GND

GND

GND

CLK0
CLK1
CLK2
CLK3
CLK4
CLK5

CLK#0
CLK#1
CLK#2
CLK#3
CLK#4
CLK#5

FB_OUT

DIMM2_CK#3
DIMM3_CK#0
DIMM2_CK#4

DIMM3_CK#1
DIMM3_CK#2
DIMM2_CK#5

BUFF_CK0 DIMM2_CK3

2

BUFF_CK1 DIMM3_CK0

4

BUFF_CK2 DIMM2_CK4

13

BUFF_CK3 DIMM3_CK1

17

BUFF_CK4 DIMM3_CK2

24

BUFF_CK5 DIMM2_CK5

26

BUFF_CK#0 DIMM2_CK#3

1

BUFF_CK#1 DIMM3_CK#0

5

BUFF_CK#2

14

BUFF_CK#3 DIMM3_CK#1

16

BUFF_CK#4 DIMM3_CK#2

25

BUFF_CK#5 DIMM2_CK#5

27

19

R127

CBVDD

C177
104P

AVDD25

DIMM2_CK#4 8DIMM2_CK48

DIMM2_CK#5 8DIMM2_CK58

R116
R115
R113
R630
R631
R632

R117
R114

R112

R633
R634

R635

22

C175

10P/X7R

0
0
0
0
0
0

0
0
0
0
0
0

FB_OUT

DIMM2_CK#4

A A

DIMM3 SLAVE ADDRESS
= (1010010X)B = A4

5

4

3

2

M icro Star Restricted Secret

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

System Memory : DDR DIMM 2

MS-6702

Last Revision Date:

星期五, 十一月

Sheet

1

08, 2002

9 48

of

Rev

0B

5

4

3

2

1

DDR Terminations

VTT_DDR_SUS VTT_DDR_SUS

DR_MD40
DR_MD39
DR_MD35

D D

DR_MD59
DR_MD63
DR_MD58
DR_MD62

-DR_MDQS7
DR_DM7

DR_MD57
DR_MD61

DR_MD56
DR_MD60
DR_MD51
DR_MD55

C C

B B

MEMBANKA04,8

MEMBAKB04,8,9

A A

For DIMM1 Clock

-MCS14,8

-MCS04,8

-MSCASA4,8

-MSWEB4,8,9

-MSRASB4,8,9

-MSRASA4,8

-DR_MDQS6

-DR_MDQS5

DR_MD45

MEMCLK_H5

MEMCLK_H0

DR_MD50
DR_MD54

DR_DM6

MAA13
MAB13
DR_MD53
DR_MD52

DR_MD49
DR_MD48
DR_MD47
DR_MD46

DR_MD43
DR_MD42

DR_DM5

-MCS1

-MCS0

-MSCASA
DR_MD41

-MSWEB

-MSRASB
DR_MD44

-MSRASA

RN67 8P4R-47

7 8
5 6
3 4
1 2

RN65 8P4R-47

7 8
5 6
3 4
1 2

RN63 8P4R-47

7 8
5 6
3 4
1 2

RN61 8P4R-47

7 8
5 6
3 4
1 2

RN59 8P4R-47

7 8
5 6
3 4
1 2

RN57 8P4R-47

7 8
5 6
3 4
1 2

RN55 8P4R-47

7 8
5 6
3 4
1 2

RN53 8P4R-47

7 8
5 6
3 4
1 2

RN52 8P4R-47

7 8
5 6
3 4
1 2

RN50 8P4R-47

7 8
5 6
3 4
1 2

R99 120RST
R122 120RST
R107 120RST

5

MEMBAKB14,8,9

For DIMM2 Clock

MEMCLK_L5

MEMCLK_L7MEMCLK_H7
MEMCLK_L0

DR_MD38

DR_MD34
DR_DM4

-DR_MDQS4
DR_MD37

DR_MD33
DR_MD36
DR_MD32

DR_CHECK7
DR_CHECK3
DR_CHECK6
DR_CHECK2

DR_DM8

-DR_MDQS8
DR_CHECK1
DR_CHECK0

DR_CHECK5
DR_CHECK4
DR_MD31
DR_MD27

MAA1
MAB1
MAA2
MAB2

MAA3
MAA4
MAB4
MAA6

DR_MD30
MAB3
DR_MD26
DR_DM3

-DR_MDQS3
DR_MD25
DR_MD29
DR_MD28

MAB6
MAB5
MAA5
MAA8

MEMCLK_H4
MEMCLK_H6
MEMCLK_H1

C702
X_10P

C703
X_10P

4

VTT_DDR_SUS

RN48 8P4R-47

7 8
5 6
3 4
1 2

RN46 8P4R-47

7 8
5 6
3 4
1 2

RN45 8P4R-47

7 8
5 6
3 4
1 2

RN44 8P4R-47

7 8
5 6
3 4
1 2

RN41 8P4R-47

7 8
5 6
3 4
1 2

RN37 8P4R-47

7 8
5 6
3 4
1 2

RN33 8P4R-47

7 8
5 6
3 4
1 2

RN30 8P4R-47

7 8
5 6
3 4
1 2

RN29 8P4R-47

7 8
5 6
3 4
1 2

RN28 8P4R-47

7 8
5 6
3 4
1 2

RN26 8P4R-47

7 8
5 6
3 4
1 2

R97 120RST
R121 120RST

R106 120RST
C704
X_10P

C705
X_10P

C706
X_10P

DR_MD24
DR_MD19
DR_MD23
MAA7

DR_DM2
MAA9
MAA11
MAA12

MAB8
DR_MD22
MAB7
DR_MD18

MAB9
MAB11
DR_MD21

-DR_MDQS2

DR_MD17
MAB12

DR_MD16
DR_MD20

DR_MD11
DR_MD10
DR_MD15
DR_MD14

DR_DM1
DR_MD13

-DR_MDQS1
DR_MD12

DR_MD9
DR_MD8

DR_MD3
DR_MD7

DR_MD6
DR_MD2
DR_DM0

-DR_MDQS0

DR_MD1
DR_MD5
DR_MD4
DR_MD0

MAB10
MAB0
MAA10
MAA0

C707
X_10P

MEMCLK_L4
MEMCLK_L6
MEMCLK_L1

RN24 8P4R-47

7 8
5 6
3 4
1 2

RN22 8P4R-47

7 8
5 6
3 4
1 2

RN21 8P4R-47

7 8
5 6
3 4
1 2

RN19 8P4R-47

7 8
5 6
3 4
1 2

RN17 8P4R-47

7 8
5 6
3 4
1 2

RN15 8P4R-47

7 8
5 6
3 4
1 2

RN12 8P4R-47

7 8
5 6
3 4
1 2

RN10 8P4R-47

7 8
5 6
3 4
1 2

RN9 8P4R-47

7 8
5 6
3 4
1 2

RN8 8P4R-47

7 8
5 6
3 4
1 2

RN126 8P4R-47

7 8
5 6
3 4
1 2

3

-MCS2

-MCS24,8,9

-MCS3

-MCS34,8,9
MAB13

MAA13

VTT_DDR_SUS

MCKE04,8,9
MCKE14,8,9

-MCS3

-MCS34,8,9

-MCS2

-MCS24,8,9

-MSCASB

-MSCASB4,8,9

-MSWEA

-MSWEA4,8

DR_DM[8..0]8,9,11MEMBANKA14,8

MEMCLK_L[7..0]4,8

MEMCLK_H[7..0]4,8,9

-DR_MDQS[8..0]8,9,11

DR_MD[63..0]8,9,11

MAB[13..0]4,8,9
MAA[13..0]4,8

DR_CHECK[7..0]8,9,11

R648 47
R649 47

RN127 8P4R-47

7 8
5 6
3 4
1 2

DR_DM[8..0]

MEMCLK_L[7..0]
MEMCLK_H[7..0]

-DR_MDQS[8..0]

DR_MD[63..0]
MAB[13..0]
MAA[13..0]

DR_CHECK[7..0]

2

MEMBAKB14,8,9

MEMBANKA14,8

MEMBAKB04,8,9

MEMBANKA04,8

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

MAB12
MAA12
MAB11
MAA11

MAB1
MAA1

MAB3

MAA3
MAB2
MAA2

MAB6

MAA6
MAB4
MAA4

MAB8
MAA8
MAA5
MAB5

MAA0

MAA10

MAB0
MAB10

-MSCASB

-MSCASB4,8,9

-MCS0

-MCS04,8

-MSCASA

-MSCASA4,8

-MCS1

-MCS14,8

MAA9
MAB9
MAB7
MAA7

-MSRASB

-MSRASB4,8,9

-MSRASA

-MSRASA4,8

-MSWEA

-MSWEA4,8

-MSWEB

-MSWEB4,8,9

MCKE14,8,9

MCKE04,8,9

M icro Star Restricted Secret

DDR Terminations Bank 0

MS-6702

Last Revision Date:

星期五, 十一月

Sheet

1

CN21

8P4C-22P
CN6

8P4C-22P
CN11

8P4C-22P
CN10

8P4C-22P
CN8

8P4C-22P
CN9

8P4C-22P
CN15

8P4C-22P
CN19

8P4C-22P
CN7

8P4C-22P
CN18

8P4C-22P
CN17

8P4C-22P
CN3

8P4C-22P

08, 2002

10 48

of

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

12
34
56
78

Rev

0B

5

MEMCHECK7 DR_CHECK7

DDR Terminations

-MDQS0 -DR_MDQS0

D D

C C

B B

MEMCHECK[7..0]4

A A

DR_CHECK[7..0]8,9,10

R657 10

RN11 8P4R-10

MD0

1 2

MD4

3 4

MD5

5 6

MD1

7 8

RN13 8P4R-10

DM0

1 2
3 4

MD6 DR_MD6

5 6

MD7 DR_MD7

7 8

RN16 8P4R-10

1 2

MD8 DR_MD8

3 4

MD9 DR_MD9

5 6
7 8

MD15

R658 10

RN18 8P4R-10

-MDQS1

1 2

MD13 DR_MD13
DM1
MD14 DR_MD14

-DR_MDQS[8..0]8,9,10

3 4
5 6
7 8

RN23 8P4R-10

1 2

MD17

3 4

MD21 DR_MD21

5 6

DM2

7 8

MD18

R659 10

RN20 8P4R-10

MD10

1 2
3 4

MD20 DR_MD20

5 6

MD16 DR_MD16

7 8

RN25 8P4R-10

1 2

MD23 DR_MD23

3 4
5 6

MD24

7 8

RN27 8P4R-10

1 2

MD29

3 4
5 6

-MDQS3

7 8

RN32 8P4R-10

MD26

1 2
3 4

MD27

5 6

MD31 DR_MD31

7 8

-MDQS[8..0]4

DR_MD[63..0]8,9,10

MD[63..0]4

DR_DM[8..0]8,9,10

DM[8..0]4

-MDQS[8..0]

-DR_MDQS[8..0]
DR_MD[63..0]

MD[63..0]

MEMCHECK[7..0]

DR_CHECK[7..0]

DR_DM[8..0]

DM[8..0]

5

DR_MD0
DR_MD4
DR_MD5
DR_MD1

DR_DM0
DR_MD2MD2

DR_MD3MD3

DR_MD12MD12

DR_MD15

-DR_MDQS1
DR_DM1

-DR_MDQS2-MDQS2
DR_MD17

DR_DM2

DR_MD18

DR_MD10
DR_MD11MD11

DR_MD22MD22
DR_MD19MD19

DR_MD24

DR_MD28MD28
DR_MD29
DR_MD25MD25

-DR_MDQS3

DR_MD26
DR_MD30MD30
DR_MD27

-MDQS4 -DR_MDQS4

MD42

MD50
MD55

MD56
MD61 DR_MD61
MD57 DR_MD57

DM7

-MDQS7
MD62 DR_MD62
MD58

MD63

MEMCHECK5
MEMCHECK0
MEMCHECK1

-MDQS8

DM8
MEMCHECK2 DR_CHECK2
MEMCHECK6
MEMCHECK3

MEMCHECK4

DM3

4

MD38

R661 10

RN42 8P4R-10

1 2
3 4
5 6
7 8

RN47 8P4R-10

1 2
3 4

DM4

5 6

MD34 DR_MD34

7 8

R662 10
RN49 8P4R-10

MD35 DR_MD35

1 2

MD39 DR_MD39

3 4
5 6

MD44 DR_MD44

7 8

RN51 8P4R-10

1 2

MD41 DR_MD41

3 4

-MDQS5 -DR_MDQS5

5 6

DM5 DR_DM5

7 8

RN54 8P4R-10

MD43

1 2

MD46 DR_MD46

3 4

MD47 DR_MD47

5 6
7 8

RN58 8P4R-10

1 2
3 4

MD53 DR_MD53

5 6
7 8

MD51

R663 10

RN60 8P4R-10

1 2
3 4
5 6
7 8

RN62 8P4R-10

1 2
3 4
5 6
7 8

RN64 8P4R-10

1 2
3 4
5 6
7 8

R707 10

R664 10

RN34

1 2
3 4
5 6
7 8

8P4R-10

RN38

1 2
3 4
5 6
7 8

8P4R-10

R665 10

R660 10

4

DR_MD38

DR_MD32MD32
DR_MD36MD36
DR_MD33MD33

DR_MD37MD37
DR_DM4

DR_MD42

DR_MD40MD40

DR_MD45MD45

DR_MD43

DR_MD48MD48

DR_MD49MD49
DR_MD52MD52

DR_DM6DM6

DR_MD51

-DR_MDQS6-MDQS6
DR_MD54MD54
DR_MD50
DR_MD55

DR_MD60MD60
DR_MD56

DR_DM7

-DR_MDQS7
DR_MD58

DR_MD59MD59

DR_MD63

DR_CHECK5
DR_CHECK0
DR_CHECK1

-DR_MDQS8

DR_DM8

DR_CHECK6
DR_CHECK3

DR_DM3

DR_CHECK4

3

2

LAYOUT: Place on backside,
evenly spaced around VTT fill.

VDD_25_SUS VDD_25_SUS

VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS VDD_25_SUS

VTT_DDR_SUS

C49

VTT_DDR_SUS

C173

VTT_DDR_SUS

0.22uC79

VTT_DDR_SUS

X_102PC289

3

VTT_DDR_SUS VTT_DDR_SUS

C216

X_0.2 2u

{nopop}

C257

X_0.2 2u

{nopop}

C285

X_0.2 2u

{nopop}

C288

X_0.2 2u

{nopop}

C37

104P
C53

104P

C68

104P
C81

104P

C85

104P

C91

104P
C97

104P

C104

104P
C111

104P

C118

104P
C128

104P

C138

104P

C145

104P

C149

104P

C28

X_0.2 2u

{nopop}

C15

X_0.2 2u

{nopop}

C31

X_0.2 2u

{nopop}

C11

X_0.2 2u

{nopop}

C65

X_0.2 2u

{nopop}

C154

104P
C156

104P
C163

104P

C170

104P

C178

104P

C186

104P

C192

104P

LAYOUT: Place one 1210 10uF
capacitor on each end of the
VTT island.

C200

104P

C208

104P

C212

104P

C215

104P

C223

104P

C231

104P

C238

104P

LAYOUT: Place alternating caps to GND and VDD_2.5_SUS in a single line along VTT island.

104P

104P

C67

4.7u/0805

X_100PC295

C59

C182

C292

X_4.7u/0805

104P

104P

X_0.22uC61

C71

C189

C66

C90

C83

104P

104P

C197

4.7u/0805

X_100PC258

C239

X_4.7u/0805

C93

104P

104P

104P

C209

104P

C206

LAYOUT: Locate close to
Clawhammer socket.

102PC27

C16

X_4.7u/0805

X_0.22uC229

C217

4.7u/0805

104P

104P

104P

C100

104P

104P

C213

X_100PC12

X_100PC17

X_102PC25

X_0.22uC14

GND

102PC190

0.22uC165
C164

C220

4.7u/0805

GND

104P

C114

C226

104P

104P

C233

104P

2

C121

104P

C107

C131

C242

104P

104P

C141

C252

104P

C146

104P

C263

Title
Document Number

C155

104P

104P

C151

104P

104P

C266

C270

M icro Star Restricted Secret

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

1

LAYOUT: Locate close
to Clawhammer socket.

VTT_DDR_SUS

+

EC61

1000U/6.3V

VTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUSVTT_DDR_SUS

C248

104P

C259

104P

C265

104P

C268

104P

C272

104P

C281

104P

C157

C274

104P

104P

C167

GND

104P

104P

C282

GND

MS-6702

Last Revision Date:

星期五, 十一月

Sheet

1

104P

104P

DDR Terminations Bank 1

+

EC62
1000U/6.3V

GND

08, 2002

11 48

of

Rev

0B

A

B

C

K8T400M HT Interface

D

E

Reserved

VAVDD2

C203

VDD_12_A

H17

H18

NC_H17

NC_H18

TCADP15
TCADN15
TCADP14
TCADN14
TCADP13
TCADN13
TCADP12
TCADN12
TCADP11
TCADN11
TCADP10
TCADN10

TCADP9
TCADN9
TCADP8
TCADN8
TCADP7
TCADN7
TCADP6
TCADN6
TCADP5
TCADN5
TCADP4
TCADN4
TCADP3
TCADN3
TCADP2
TCADN2
TCADP1
TCADN1
TCADP0
TCADN0

TCLKP1
TCLKN1
TCLKP0
TCLKN0

TCTLP
TCTLN

RNCOMP
RTCOMP
RPCOMP

LDTRST

LDTSTOP

C22C21

AVDD2AVSS2

E20
D21
D19
C19
E18
E19
D17
C17
D15
C15
E14
E15
D13
C13
E12
E13
B20
C20
A19
A20
B18
C18
A17
A18
A15
A16
B14
C14
A13
A14
B12
C12

E16
E17
B16
C16

A21
A22

D26
C26
D25

B11
A12

VAVDD2

U10A
X_K8T400M_#A

???

CADIN15

CADIN14
CADIN13
CADIN12
CADIN11
CADIN10
CADIN9

CADIN8
CADIN7
CADIN6
CADIN5
CADIN4
CADIN3

CADIN2
CADIN1

CADIN0

CLKIP1
CLKIN1
CLKIP0
CLKIN0

CTLIP0
CTLIN0

PNCOMP
RTCOMP
RPCOMP

-LDTRST

-LDTSTOP

To Claw Hammer

CADIP15
CADIP14
CADIP13
CADIP12
CADIP11
CADIP10
CADIP9
CADIP8
CADIP7
CADIP6
CADIP5
CADIP4
CADIP3
CADIP2
CADIP1
CADIP0

CLKIP1 4
CLKIN1 4
CLKIP0 4
CLKIN0 4

CTLIP0 4
CTLIN0 4

-LDTRST 42

-LDTSTOP5,17

CADIN[15:0] 4
CADIP[15:0] 4

PNCOMP
RTCOMP

RPCOMP

4 4

A10

A24

A25

A26

B10

B24

B26

C10

C24

C25

A9

B9

VLDT

VLDT

VLDT

VLDT

VLDT

VLDT

RCADP15
RCADN15
RCADP14
RCADN14
RCADP13
RCADN13
RCADP12
RCADN12
RCADP11
RCADN11
RCADP10
RCADN10
RCADP9
RCADN9
RCADP8
RCADN8
RCADP7
RCADN7
RCADP6
RCADN6
RCADP5
RCADN5
RCADP4
RCADN4
RCADP3
RCADN3
RCADP2
RCADN2
RCADP1
RCADN1
RCADP0
RCADN0

RCLKP1
RCLKN1
RCLKP0
RCLKN0

RCTLP
RCTLN

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VLDT

From Claw Hammer

J10

CADON[15:0]4
CADOP[15:0]4

3 3

2 2

CADOP15

CADOP14

CADOP13
CADOP12
CADOP11
CADOP10
CADOP9
CADOP8
CADOP7
CADOP6
CADOP5
CADOP4
CADOP3
CADOP2
CADOP1
CADOP0

CLKOP14
CLKON14
CLKOP04
CLKON04

CTLOP04
CTLON04

CADON15
CADON14
CADON13
CADON12
CADON11
CADON10
CADON9
CADON8
CADON7
CADON6
CADON5
CADON4
CADON3
CADON2
CADON1
CADON0

CLKOP1
CLKON1
CLKOP0
CLKON0

CTLOP0
CTLON0

G24
G23

J22

H22

J24
J23

L22
K22
N22

M22

N24
N23
R22
P22
R24
R23
H26

G26

H24
H25
K26

J26
K24
K25

M24
M25

P26
N26
P24
P25
T26
R26

L24

L23

M26

L26

F24
F25

J18
F13
F18
K12
K13
K14
K15
K16
K17

B23

VLDT

VLDT

B25

VLDT

VLDT

C9

VLDT

C11D9D10

VLDT

VLDT

VLDT

C23

VLDT

VLDT

VLDT

D22

D23

D11E9E10

VLDT

VLDT

VLDT

VLDT

D24

VLDT

VLDT

VLDT

E11

VLDT

E21

VLDT

E22

VLDT

E23

VLDT

E24

VLDT

F10

VLDT

F11

VLDT

F15

VLDT

F16

VLDT

F19

VLDT

F20

VLDT

F21

VLDT

F22

VLDT

F23

VLDT

G21

VLDT

G22

VLDT

H21

VLDT

J11

VLDT

J12

VLDT

J13

VLDT

J14

VLDT

J15

VLDT

VLDT

H14

H13

NC_H13

NC_H14

VAGND2

C205 104P
C204 104P

C641 X_104P/BACK

C644 X_104P/BACK

Decoupling capacitors
at NB BGA Area (On
Solder Layer)

R152 49.9RST
R140 100RST
R151 49.9RST

X_103P

VDD_12_A

Around NB

VDD_12_A

VDD_12_A

NC_K8

K8

NC_L8

L8

NC_J19

N19

J19

NC_P19

NC_N19

NC_P2

P19

P2

NC_P3

P3

NC_P4

P4

J16

VLDT

J17

VLDT

K18

VLDT

K21

VLDT

L18

VLDT

L21

VLDT

M18

VLDT

N18

VLDT

N21

VLDT

P18

VLDT

P21

VLDT

R18

VLDT

T18

VLDT

T21

VLDT

T22

VLDT

T23

VLDT

T24

VLDT

T25

VLDT

U18

VLDT

U21

VLDT

U22

VLDT

U23

VLDT

U24

VLDT

U25

VLDT

U26

VLDT

V21

VLDT

V22

VLDT

V23

VLDT

V24

VLDT

V25

VLDT

V26

VLDT

K10

VSS

K11

VSS

L10

VSS

M10

VSS

N10

VSS

P10

VSS

R10

VSS

VSS

VSS

T10

U10

VDD_12_A

VAGND2

1 1

Title

Size Document Number Rev

C

A

B

C

D

Date: Sheet of

MS-6702

NORTH BRIDGE K8T400M/VER:0.4 (HT)

星期五, 十一月

08, 2002

MS-6702

E

12 48

0B

A

K8T400M AGP 8X ,V-Link, Misc. Control

VCC2_5

4 4

GAD0

GAD[31:0]16

3 3

SBA016
SBA116
SBA216
SBA316
SBA416
SBA516
SBA616
SBA716

GC/BE#016
GC/BE#116
GC/BE#216
GC/BE#316

AD_STBF016
AD_STBS016
AD_STBF116
AD_STBS116

SB_STBF16

2 2

SB_STBS16

GFRAME16

GTRDY16

GDEVSEL16

GSERR16

AGP8XDET#16

AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1

SB_STBF
SB_STBS

DBIH

DBIH16

DBIL

DBIL16

GIRDY16

GSTOP16

GPAR16

RBF16

WBF16

GREQ16

GGNT16

ST016
ST116
ST216

GCLK_NB7

AGPVREF_GC16

1 1

AGPVREF_GC

A

AF18

GAD1

AD18

GAD2

AE18

GAD3

AF17

GAD4

AD17

GAD5

AD16

GAD6

AE16

GAD7

AF16

GAD8

AF14

GAD9

AD14

GAD10

AD13

GAD11

AE13

GAD12

AF13

GAD13

AD12

GAD14

AF12

GAD15

AE12

GAD16

AD10

GAD17

AE10

GAD18

AF10

GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

AD15

AF11

AD11

AE15

AF15

AC10

AC14

AC11

AC12

AC16

AC15

AGPPCOMP
AGPNCOMP AGPPCOMP

AC13

U1T2T3T4T5T8T9U2U3U4U5U8U9V2V3

M8

VDD
VDD
VDD

GD0
GD1
GD2
GD3
GD4
GD5
GD6
GD7
GD8
GD9
GD10
GD11
GD12
GD13
GD14
GD15
GD16
GD17
GD18
GD19
GD20
GD21
GD22
GD23
GD24
GD25
GD26
GD27
GD28
GD29
GD30
GD31

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

C/BE0
C/BE1
C/BE2
C/BE3

AD_STBF0
AD_STBS0
AD_STBF1
AD_STBS1

SB_STBF
SB_STBS

DBIH
DBIL

GFRAME
GIRDY
GTRDY
GDEVSEL
GSTOP
GPAR
RBF
WBF
GREQ
GGNT
GSERR
AGP8XDET

ST0
ST1
ST2

GCLK
AGPPCOMP

AGPNCOMP

AGPVREF0
AGPVREF1

VCCQQ

N8

VCC1

VCC1

W14
W13
W12

AD9
AF9
AF8
AE9
AD8
AF6
AD7
AE6
AD5
AF5
AF4
AE4
AD4

AC2
AC3
AD1
AD2
AF2
AD3
AE3
AF3

AC7

AE7
AF7

AF1
AE1

AC5
AC4

AC9

AD6
AC1

Y1

AA3

Y2

AA2
AA1
AB1

A11

V1

W1

AC6

VCC1

VCC1

VCC1

VCC1

VSSQQ

T1

VCC1

VCC1

VSS

P5R1R2R3R4

A8

VCC1

VCC1

VSS

VSS

VCC1

VSS

VCC1

VCC1

VSS

VSS

R5

B

VCC1

VSS

R21

B

VCC1

VCC1

VSS

VSS

V4V5V8

VCC1

VCC1

VSS

VSS

W21

V9

W22

V10

VCC1

VCC1

VSS

VSS

W23

V11

W24

V12

VCC1

VSS

W25

VDDQ

V13W2W3

VCC1

VCC1

VSS

VSS

AB2

W26

VCC1

VSS

AB3

W4W5W9

VCC1

VCC1

VSS

VSS

AB4

VCC1

VSS

AB5

Y3Y4Y5

VCC1

VSS

AB6

AB9

VCC1

VCC1

VSS

VSS

AB10

AA4

VCC1

VSS

AB15

AA5

VCC1

VSS

AB16

AB7

AC8

AB8

VCC1

VCC1

VSS

VSS

AC24

AB11

VCC1

VSS

AE2

AB12

VCC1

VSS

AE5

AB13

VCC1

VSS

AE8

AB14

VCC1

VSS

AE11

VSS

AE14

VSS

AE17

VSS

AE20

VSS

AE22

VSS

AE25

C

AVSS1

E26

C

VSUS2_5

E25

AVDD1

PWRGD

RESET

TESTIN

SUSST

VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2
VCC2

VPAR

LVREF

LCOMPP

UPCMD
DNCMD

DNSTB
DNSTB

UPSTB
UPSTB

DEBUG

PIPE#

RSVD3
RSVD0
RSVD2
RSVD6
RSVD5

NC_M5

NC_N1
NC_N2
NC_N3
NC_N4
NC_N5
NC_P1

NC_L5

NC_W8

NC_Y8
NC_Y9

NC_Y10

VAGND1

VAVDD1

AC25

VSUS25

VD0
VD1
VD2
VD3
VD4
VD5
VD6
VD7

VBE

U10B
X_K8T400M_#A

???

AE26
AD25
AC26

TESTIN

AD26

V14
V15
V16
V17
W15
W16
W17
W18
AB17
AB18
AB19
AB20
AC18
AC19
AC20
AC21

AD20
AD21
AF24
AE24
AE19
AF20
AD24
AF25

AE21
AF19

LVREF_NB

AF21

LCOMPP

AD19

AF26
AD23

AF22
AD22

AE23
AF23

AC17
M1
L3

L4
M2
M3
M4

M5
N1
N2
N3
N4
N5
P1
L5
W8
Y8
Y9
Y10

C262
X_102P

VCC2_5

DEBUG

PWROK_NB# 18

SUSST# 18

VLAD0 17
VLAD1 17
VLAD2 17
VLAD3 17
VLAD4 17
VLAD5 17
VLAD6 17
VLAD7 17

VBE0# 17
VPAR 17

UPCMD 17
DNCMD 17

DNSTB 17
DNSTB# 17

UPSTB 17
UPSTB# 17

R180 10K

D

Near NB.

C708
X_102P

The voltage level of
LVREF_NB is

0.625V

D

E

Reserved

VAVDD1

VAGND1

PCIRST# 16,17,32

VCC2_5

R176
3KST

R181
1KST

LAYOUT: Place caps on the bottom of NB

C650 X_104P/BACK
C643 X_104P/BACK
C648 X_104P/BACK
C653 X_104P/BACK
C657 X_104P/BACK
C639 X_104P/BACK
C647 X_104P/BACK
C658 X_104P/BACK
C642 X_104P/BACK
C640 X_104P/BACK

VDDQ

AGPVREF_GC

C652 X_104P/BACK
C656 X_104P/BACK
C651 X_104P/BACK
C663 X_104P/BACK
C671 X_104P/BACK

C307 104P
C297 105P/0805

LAYOUT: Place caps as close NB as possible

TESTIN
VPAR

AGPNCOMP

LCOMPP

Title

Size Document Number Rev

C

Date: Sheet of

MS-6702

NORTH BRIDGE K8T400M/VER:0.4 (AGP & VLINK)

星期五, 十一月

08, 2002

R192 4.7K
R205 X_8.2K

R193 60.4RST
R187 60.4RST

R185 360RST

MS-6702

E

C194
X_103P

C246
104P

LVREF_NB

C250
104P

VDDQ

VCC2_5

VDDQ

0B

13 48

A

B

C

D

E

K8T400M Power and Ground Connections

VDD_12_A VDD_12_A

C636 X_0.22u/BACK

C628 X_0.22u/BACK

C629 X_0.22u/BACK
C649 X_0.22u/BACK
C637 X_0.22u/BACK
C625 X_0.22u/BACK
C626 X_0.22u/BACK

D

C630 X_4.7U/0805/BACK

Title

Size Document Number Rev

Custom

Date: Sheet of

MS-6702

NORTH BRIDGE K8T400M/VER:0.4 (POWER/GOUND)

星期五, 十一月

08, 2002

MS-6702

E

14 48

0B

H8
J8
F9
H9
H10
H11
H12
H15
H16
K19
L19
M19
P8
R8
R19
T19
U19
V18
V19
W10
W11
W19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
AA21
AA22
AA23
AA24
AA25
AA26
AB21
AB22
AB23
AB24
AB25
AB26

A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
D5
D7
E1
E2
E3
E4
E7
F1
F2
F3
F4
F5
F6
G2
G3
G4
G5
H3
H4
H5
J1
J4
J5

VCC2_5

VCC2_5

C662 X_104P/BACK
C635 X_104P/BACK
C654 X_104P/BACK
C645 X_104P/BACK
C655 X_104P/BACK
C659 X_102P/BACK
C660 X_102P/BACK
C632 X_102P/BACK
C638 X_102P/BACK
C661 X_102P/BACK

LAYOUT : Popualte caps on the bottom side
of NB.

VDDQ

C241
104P

VDDQ

C350

VDDQ

C352

1U/0805

C283 X_105P/0805
C245 105P/0805

C353
104P

1U/0805

VDDQ

C347

1U/0805

B

C359

X_104P

C373

X_1U/0805

C346
104P

K8T400M

C251

C306
X_104P

105P

C235

C276

1U/0805

1U/0805

VDDQ

C293

104P

C351

X_1U/0805

X_1U/0805/BACK

C

C664

U10C

X_K8T400M_#A

???

VDD

NC_K1

NC_K5

K1

L1

NC_L1

NC_A1
NC_A2
NC_A3
NC_A4
NC_A5
NC_A6
NC_A7
NC_B1
NC_B2
NC_B3
NC_B4
NC_B5
NC_B6
NC_B7
NC_C1
NC_C2
NC_C3
NC_C4
NC_C5
NC_C6
NC_C7
NC_D1
NC_D2
NC_D3
NC_D4
NC_D5
NC_D7
NC_E1
NC_E2
NC_E3
NC_E4
NC_E7
NC_F1
NC_F2
NC_F3
NC_F4
NC_F5

NC_F6
NC_G2
NC_G3
NC_G4
NC_G5

NC_H3

NC_H4

NC_H5

NC_J1
NC_J4
NC_J5

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

A23

VSS

B8

VSS

B13

VSS

B15

VSS

B17

VSS

B19

AC22
AC23

VSS

B21

VSS

B22

VSS

C8

VSS

D6

VSS

D8

VSS

D12

VSS

D14

VSS

D16

VSS

D18

VSS

D20

VSS

E5

VSS

E6

VSS

E8

VSS

F7

VSS

F8

VSS

F12

VSS

F14

VSS

F17

VSS

F26

VSS

G25

VSS

H1

VSS

H23

VSS

J2

VSS

J3

VSS

J21

VSS

J25

VSS
VSS

K23

VSS

L11

VSS

L12

VSS

L13

VSS

L14

VSS

L15

VSS

L16

VSS

L17

VSS

L25

VSS

M11

VSS

M12

VSS

M13

VSS

M14

VSS

M15

VSS

M16

VSS

M17

VSS

M21

VSS

M23

VSS

N11

VSS

N12

VSS

N13

VSS

N14

VSS

N15

VSS

N16

VSS

N17

VSS

N25

VSS

P11

VSS

P12

VSS

P13

VSS

P14

VSS

P15

VSS

P16

VSS

P17

VSS

P23

VSS

R11

VSS

R12

VSS

R13

VSS

R14

VSS

R15

VSS

R16

VSS

R17

VSS

R25

VSS

T11

VSS

T12

VSS

T13

VSS

T14

VSS

T15

VSS

T16

VSS

T17

VSS

U11

VSS

U12

VSS

U13

VSS

U14

VSS

U15

VSS

U16

VSS

U17

VSS
VSS
VSS

G1

VSS

H2

VSS

RSVD4

RSVD1

RSVD7

K2

K3K4K5

L2

A

4 4

3 3

2 2

1 1

5

4

3

2

1

K8 Voltage Regular Module

D D

Q75

EN_VCORE#42

R_VID[4..0]38

C C

D roop Compensation

B B

2N7002S

R21 10K

VCC

PG_VCORE42

R27 10KST

R40
0

VCORE
GND

VID4 VID3 VID2 VID1 VID0 Vout

+12V

VCC

R666

4.7K

VCORE_EN

R22 0
R14 154KST

COMP1

C18 5600p/X7R

22p/X7RC22

R34
1KST

VDIFF

IDROOP

COREFB_H5

R7 51RST
R41 51RST

COREFB_L5

R_VID4

R_VID3
R_VID2
R_VID1
R_VID0

CORE_PG

FS_ISL

COMP
FB_ISL

C218
104P/25V X_39p/50V

C5
X_104P

24

3
4
5
6
7

22
23

9

10

12
11

1 1 1 1 0 0.800
1 1 1 0 1 0.825
1 1 1 0 0 0.850
1 1 0 1 1 0.875
1 1 0 1 0 0.900
1 1 0 0 1 0.925
1 1 0 0 0 0.950

1 0 1 1 0 1.000
1 0 1 0 1 1.025
1 0 1 0 0 1.050
1 0 0 1 1 1.075
1 0 0 1 0 1.100

A A

1 0 0 0 1 1.125
1 0 0 0 0 1.150
0 1 1 1 1 1.175

5

CHOK3 1.1uH/25A

VCC

GND
GND
GND

PWM1

ISEN1

PWM2

ISEN2

OFS
OVP

VSEN

RGND

16
18

15
1
20
21

19
17

8
2
13

14

C195
39p/50V

VDD5_I

ISEN1

ISEN2

OFS

CT13
820u/25V

VCC

R6
0

CB1
105P/0805

R5 3KST

R28 3KST

R51

2.2K

Offset Adjustment

C214

U3
ISL6569CB

I32-6569B02-I11

EN
VID4

VID3
VID2
VID1
VID0
PGOOD

FS/DIS

COMP

FB

VDIFF
IDROOP

VID4 VID3 VID2 VID1 VID0 Vout
0 1 1 1 0 1.200
0 1 1 0 1 1.225
0 1 1 0 0 1.250
0 1 0 1 1 1.275
0 1 0 1 0 1300
0 1 0 0 1 1.325
0 1 0 0 0 1.350
0 0 1 1 1 1.3751 0 1 1 1 0.975
0 0 1 1 0 1.400
0 0 1 0 1 1.425
0 0 1 0 0 1.450
0 0 0 1 1 1.475
0 0 0 1 0 1.500
0 0 0 0 1 1.525
0 0 0 0 0 1.550
1 1 1 1 1 Shutdown

4

VDD_12_VRM

CT12
820u/25V

+12V

R68

5.1/0805

VDD_P0

CB2
105P/0805/X7R/25V

PWM1

+12V

R92

5.1/0805

VDD_P1

CB3
105P/0805/X7R/25V

PWM2

INPUT CAPACITOR SOURCE

1. NCC C94-1521641-N07

2. RUBYCON C94-1521641-R07

3. NICHICON C94-1521641-N10

4. PANASONIC

OUTPUT CAPACITOR SOURCE

1. RUBYCON C94-2220611-R07

2. NCC C94-2220611-N07

3. NICHICON C94-2220611-N10

4. PANASONIC

High Side MOSFET
Main source:
IPB15N03=>D03-15N030B-I14
Second source:
FDB6035AL=>D03-6035ALB-F01
P55N02LS=>D03-55N020B-N03

Low Side MOSFET
Main source:
FDB6670AL=>D03-6670ALB-F01
Second source:
IPB07N03L=> D03-07N031B-I14
SUB85N03-07P=>D03-85N030B-V02

CT10
820u/25V

U4A
HIP6602B_#A

I33-6602B03-I11

14

VCC

3

GND

1

PWM1

U4B

5 9

PVCC U_G2

6

PGND

2

PWM2

HIP6602B_#B

CT8
820u/25V

3

U_G1

BOOT1

PHASE1

L_G1

BOOT2

PHASE2

L_G2

C188

C105

4.7U/1206

4.7U/1206

PBT1

U_G1

12
11

R57

C42

2.2

13

C41

X_103P/X7R

4

10

8

7

104P/X7R

L_G1 L_G1A

PBT2

BOOT2

R58

2.2

C30
104P/X7R

C43
X_103P/X7R

L_G2

R132

2.2/0805

U_G1A

PHASE1

U_G2AU_G2

PHASE2

L_G2A

G

G

BOOT1

R105

2.2/0805

R110
0/0805

R82
0/0805

0.8V~1.55V/42A

MOSFET Heat-Sink

PH1

Mech/HeatSink

+12V

C573

104P/25V

Near to Vcore Input-Chock ( CHOK1 )

PH2

12

12

Mech,HeatSink

60MIL

JPW1

3

12V

4

12V

D2x2

DS

Q25
15N03/D2PACK

DS

Q24
6670ALG

DS

Q20
15N03/D2PACK

DS

Q16
6670ALG

GND

GND

2

CB5
105P/0805/16V

CB4
105P/0805/16V

12

12

1

2

DS

Q71
6670ALG

DS

Q72
6670ALG

VCORE

VCORE

CHOK2

0.8u-20%

CHOK1

0.8u-20%

CT11
2200U/6.3V

CT5
2200U/6.3V

Title
Document Number

MICRO-STAR INT'L
CO.,LTD.

No. 69, Li-De St, Jung-He City,
Taipei Hsien, Taiwan
http://www.msi.com.tw

CT6
2200U/6.3V

CT3
2200U/6.3V

M icro Star Restricted Secret

K8 CORE POWER

CT1
2200U/6.3V

CT7
2200U/6.3V

MS-6702

Last Revision Date:

星期五, 十一月

Sheet

1

CT4
2200U/6.3V

CT9
2200U/6.3V

08, 2002

15 48

of

Rev

0B