MSI MS-6542 Schematics
8
7
6
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Version 0AE2
MS-6542
10/06/2001 Update
D D
Cover Sheet
Block Diagram
Clock ICS950201 & ATA100 IDE CONNECTORS
mPGA478-B INTEL CPU Sockets
INTEL Brookdale MCH845 -- North Bridge
1
2
3
4 - 5
6 - 7
INTEL (R) Brookdale Chipset
Willamette/Northwood 478pin mPGA-B Processor Schematics
CPU:
Willamette/Northwood mPGA-478B Processor
System Brookdale Chipset:
INTEL MCH845 (North Bridge) +
INTEL ICH2 -- South Bridge
LPC I/O -- LPC47M192
C C
AC'97 Codec AD1887 & Connectors
8 - 9
10
11
INTEL ICH2 (South Bridge)
On Board Chipset:
BIOS -- FWH
FWH -- BIOS & Manual
DDR DIMM1&2
AGP SLOT
PCI SLOT 1 & 2 & 3
IO Connectors
USB CONNECTORS & THERMTRIP CIRCUIT
12
13
14
15
16
17
AC'97 Codec -- AD1887
LPC Super I/O -- LPC47M192
Clock Generation -- ICS950201
LAN -- Intel Kinnerith W82562EM
LAN -- 3COM 3C920V1(Dual-layout)
Expansion Slots:
AGP 1.5V SLOT *1
PCI 2.2 SLOT * 4
Front Panel & ATX Connectors & FAN
B B
18
Votlage Regulator
Intersil HIP6301V+HIP6601A/02A-- CPU Power ( VRM9.2 )
LAN Kinnerith
DDR REGULATOR & PCI SLOT 4
LAN 3COM
MANUAL PARTS
GPIO SETTTING
A A
JUMPER SETTING
HISTORY 27
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7
6
19
20
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22
23
24
25
26
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4
3
MSI
Title
Size Document Number Rev
Date: Sheet of
2
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
COVER SHEET
MS-6542
1 27Saturday, November 03, 2001
1
0AE2
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1
VCC12 Power
Supply CONN
FMB1
Willamette/Northwood
Socket (mPGA478-B)
(100MHz)
CK408 Clock
(100MHz)
Scalable Bus
AGP 4X (1.5V)
VGA CONN
C C
4X (66MHz) AGP
MCH: Memory
Controller HUB
HUB Interface
(200 MHz)
DDR DIMM1,2
(14.318MHz)
IDE CONN 1&2
ATA33/ATA66/ATA100
ICH2: I/O
Controller HUB
PCI (33MHz)
PCI Slots 1:4
(48MHz)
USB Port 0:1
AC Link
USB Front Panel
USB Port 2:3
USB Back Panel
4 posrt USE on ICH2
B B
Hardware
Monitor
PS2 Mouse &
Keyboard
LPC Bus
SMC I/O
LPC47M192
Parallel &
Serial
FWH: Firmware HUB
Brookdale Chipset
Floppy Disk
Drive CONN
(33MHz)
(33MHz)
AC '97 Audio
Codec
Line Out
CD-ROM
MIC In
Line In
A A
MSI
Title
Size Document Number Rev
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7
6
5
4
3
Date: Sheet of
2
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
BLOCK DIAGRAM
MS-6542
2 27Saturday, November 03, 2001
1
0AE2
8
CP1 X_COPPER
VCC3
* Put GND copper under Clock Gen.
D D
connect to every GND pin
* 40 mils Trace on Layer 4
with GND copper around
* put close to every power pin
it
FB29 X_80_0805
Rubycon
CB33
0.1u
filtering from 10K~1M
Trace Width 7mils.
Same Group spacing 15mils
*
Different Group spacing 30mils
*
Differentical clock spacing 7mils on itself
*
*
VCC3
CB361
0.1u
C C
R122 220
VCCP
NPN-3904LT1-S-SOT23
+12V
CP2 X_COPPER
FB30 X_80_0805
CB37
0.1u
for good filtering from 10K~1M
R102 1K
VCC3
R513 220R535 4.7K
C401
4.7u-0805
R536
4.7K
Rubycon
X_NPN-3904LT1-S-SOT23
7
CLOCK GENERATOR BLOCK
CB40
0.1u
CB55
0.1u
CB61
0.1u
CB41
0.1u
CB52
0.1u
CB60
0.01u
CB66
0.01u
CB58
0.01u
U7
50
VDDCPU
46
VDDCPU
47
GND
19
VDD3V66
20
GND
32
VDD3V66
31
GND
8
VDDPCI
9
GND
14
VDDPCI
15
GND
1
VDDREF
4
GND
37
VDD48
36
GND
26
VDDA
27
GND
53
CPU_STP#
34
PCI_STP#
25
PD#
28
VTT_PWRGD#
VCC3V
+
CT15
10u
VDDA3V
+
CT20
10u
VCC3V
R729 1K
R103
Q38
X_1K
6
CPUCLK0
CPUCLK0#
CPUCLK1
CPUCLK1#
CPUCLK2
CPUCLK2#
3V66_0
3V66_1
3V66_2
3V66_3
3V66_4
3V66_5
PCICLK_F0
PCICLK_F1
PCICLK_F2
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
REF
48MHz_USB
48MHz_DOT
IREF
GND
MULTSEL0
SCLK
SDATA
ICS950201AF
FS0
FS1
FS2
X1
X2
52
51
49
48
45
44
33
35
21
22
23
24
5
6
7
10
11
12
13
16
17
18
56
2
3
39
38
42
41
43
54
55
40
30
29
*Trace less 0.5"
R83 33
R88 33
R92 33
R94 33
R75 33
R77 33
R514 33
R515 33
R516 33
R517 33
R519 33
R521 33
R518 33
R520 33
R522 33
R524 33
R525 33
R523 33
R71 33
R62 33
32pF
X2 14M-32pf-HC49S-D
R112 33
R97 475
R728 X_1K
R730 10K
R731 1K
FS1
R732 1K
SMB_CLK_MAIN
SMB_DATA_MAIN
5
CPUCLK
CPUCLK#
MCHCLK
MCHCLK#
ITP_CLK
ITP_CLK#
MCH_66
AGPCLK
ICH_66
PCICLK0
PCICLK1
PCICLK2
SIO_PCLK
PCICLK3
LAN_PCLK
ICH_PCLK
FWH_PCLK
ICH_14
SIO_14
22pC93
22pC94
ICH_48
Iref = 2.32mA
VCC3V
MULTSEL0=0 -> 4X Iref
MULTSEL0=1 -> 6X Iref
SMB_CLK_MAIN {10,13,21,23}
SMB_DATA_MAIN {10,13,21,23}
4
CPUCLK {4}
CPUCLK# {4}
MCHCLK {6}
MCHCLK# {6}
ITP_CLK {4}
ITP_CLK# {4}
MCH_66 {6}
AGPCLK {14}
ICH_66 {9}
PCICLK0 {15}
PCICLK1 {15}
PCICLK2 {15}
SIO_PCLK {10}
PCICLK3 {22}
LAN_PCLK {23}
ICH_PCLK {8}
FWH_PCLK {12}
ICH_14 {9}
SIO_14 {10}
ICH_48 {9}
3
Shut Source Termination Resistors
CPUCLK
R86 49.9
CPUCLK#
R91 49.9
MCHCLK
R93 49.9
MCHCLK#
R95 49.9
Trace less 0.2"
49.9ohm for 50ohm M/B impedance
CLOCK STRAPPING RESISTORS
FS1 VCC3V
SMB_CLK_MAIN
SMB_DATA_MAIN
R110 1.5K
R104 X_0
R450 0
FS2 FS1 FS0
0 0 1
0 1 1
R66 4.7K
R63 4.7K
CPU (MHz)
BSEL0 {4}
100 MHz
133 MHz
VCC3
2
1
Pull-Down Capacitors
CPUCLK
CPUCLK#
MCHCLK
MCHCLK#
ITP_CLK
ITP_CLK#
MCH_66
ICH_66
AGPCLK
ICH_PCLK
FWH_PCLK
PCICLK0
PCICLK1
PCICLK2
SIO_PCLK
PCICLK3
ICH_14
SIO_14
LAN_PCLK
ICH_48
used only for EMI issue
X_10pC102
X_10pC105
X_10pC108
X_10pC110
X_10pC95
X_10pC96
X_10pC113
X_10pC114
X_10pC117
X_10pC97
X_10pC98
X_10pC107
X_10pC109
X_10pC111
X_10pC112
X_10pC103
10pC92
10pC90
X_10pC89
10pC469
Trace less 0.2"
Decoupling Capacitors
VCC3V
0.1uCB268Q12
0.1uCB267
0.1uCB266
0.1uCB265
0.1uCB264
PRIMARY IDE BLOCK SECONDARY IDE BLOCK
90D 90D
PRIMAR
HD_RST#
R368 33
B B
A A
PDD[0..7]{9}
PD_DREQ{9}
PD_IOW#{9}
PD_IOR#{9}
PD_IORDY{9}
PD_DACK#{9}
IRQ14{8}
PD_A1{9}
PD_CS#1{9} PD_CS#3 {9}
PD_LED{18}
PCIRST#{8}
PCIRST# PCIRST#
8
PDD7
PDD5
PDD4
PDD3
PDD2
PDD1
PDD0
R354
C242
4.7K
VCC5 VCC5VCC3
220p
RESET BLOCK
1 2
U17A
DM7407-SOIC14
(VCC5_SB) (VCC5_SB)
R332 330
PCIRST#1 {6,10,12,23} PCIRST#2 {14,15,22}
7
CN-BH-D2x20-1:21-BK-A-S3
1
2
3 4
5 6
7 8
91110
13 14
17 18
19
21
23
25
27
29
31
33
35
37
R363
10K
VCC3 VCC3
PDD8
PDD9PDD6
PDD10
PDD11
PDD12
12
PDD13
PDD14
1615
PDD15
22
24
26
R362 470
28
30
32
R316 0
34
36
38
4039
C243
X_4700p
6
ATA100 IDE CONNECTORS
PDD[8..15] {9}
PD_DET {9}
PD_A2 {9}PD_A0{9}
3 4
U17B
DM7407-SOIC14
R96 330
5
PCIRST# HD_RST#
SECON
R338
10K
VCC3
1
3 4
5 6
7 8
91110
13 14
17 18
19
21
23
25
27
29
31
33
35
37
CN-BH-D2x20-1:21-BK-A-S3
2
SDD8
SDD9
SDD10
SDD11
SDD12
12
SDD13
SDD14
1615
SDD15
22
24
26
28
R337 470
30
32
34
R318 0
36
38
4039
C229
X_4700p
MSI
Title
Clock ICS950201 & ATA100 IDE CONNECTORS
Size Document Number Rev
Date: Sheet of
2
HD_RST#
R344 33
SDD[0..7]{9}
SD_DREQ{9}
SD_IOW#{9}
SD_IOR#{9}
SD_IORDY{9}
SD_DACK#{9}
IRQ15{8}
SD_A1{9}
SD_A0{9}
SD_CS#1{9} SD_CS#3 {9}
SD_LED{18}
5 6
U17C
DM7407-SOIC14
(VCC5_SB)
4
SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0
R355
4.7K
R306 1K
VCC5
C228
220p
3
* Trace Width : 5mils
* Trace Spacing : 7mils
* Length(longest)-Length(shortest)<0.5"
* Trace Length less than 5"
SDD[8..15] {9}
SD_DET {9}
SD_A2 {9}
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
MS-6542
3 27Wednesday, November 07, 2001
1
0AE2
8
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1
CPU SIGNAL BLOCK
VCCPS+ {20}
VID0
AE5
VID0#
GTLREF3
GTLREF2
GTLREF1
GTLREF0
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
TESTHI12
TESTHI11
TESTHI10
TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
BCLK1#
BCLK0#
COMP1
COMP0
ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#
LINT1/NMI
LINT0/INTR
D2#
D1#
D0#
A23
B22
B21
HD#0
HD#2
HD#1
VCCPS- {20}
ITP_CLK# {3}
ITP_CLK {3}
VID[0..4] {10,20}
RS2#
RS1#
RS0#
AP1#
AP0#
BR0#
DP3#
DP2#
DP1#
DP0#
SOCKET478
AA21
AA6
F20
F6
AB4
AA5
Y6
AC4
AB5
AC6
H3
J3
J4
K5
J1
AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24
AF23
AF22
F4
G5
F1
V5
AC1
H6
P1
L24
L25
K26
K25
J26
R5
L5
W23
P23
J23
F21
W22
R22
K22
E22
E5
D1
GTLREF1
GTLREF2
BPM#5
BPM#4
BPM#3
BPM#2
HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0
R127 4.7K
R136 4.7K
R129 4.7K
R135 4.7K
HRS#2
HRS#1
HRS#0
R144 49.9RST
R145 49.9RST
HREQ#[0..4] {6}
VCCP
CPUCLK# {3}
CPUCLK {3}
HRS#[0..2] {6}
HBR#0 {6}
* Short trace
HADSTB#1 {6}
HADSTB#0 {6}
HDSTBP#3 {6}
HDSTBP#2 {6}
HDSTBP#1 {6}
HDSTBP#0 {6}
HDSTBN#3 {6}
HDSTBN#2 {6}
HDSTBN#1 {6}
HDSTBN#0 {6}
NMI {8}
INTR {8}
HA#[3..31]{6}
HA#8
HA#22
HA#25
HA#23
HA#26
HA#27
HA#28
HA#30
HA#29
D D
HDBI#[0..3]{6}
VCCP
FERR#{8}
STPCLK#{8}
HINIT#{8}
HDBSY#{6}
HDRDY#{6}
HTRDY#{6}
HADS#{6}
HLOCK#{6}
HBNR#{6}
HITM#{6}
C C
B B
HBPRI#{6}
HDEFER#{6}
CPU_TMPA{10}
VTIN_GND{10}
TRMTRIP#{17}
PROCHOT#{9}
IGNNE#{8}
HSMI#{8}
A20M#{8}
SLP#{8}
BSEL0{3,14}
CPU_GD{9}
CPURST#{6}
HD#[0..63]{6}
HDBI#0
HDBI#1
HDBI#2
HDBI#3
R537 62
HINIT#
HIT#{6}
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK
TRMTRIP#
CPU_GD
CPURST#
HD#63
HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54
G25
AC3
AA3
AB2
AF26
AB26
AD2
AD3
AE21
AF24
AF25
AD6
AD5
AB23
AB25
AA24
AA22
AA25
W25
W26
E21
P26
V21
V6
B6
Y4
W5
H5
H2
J6
G1
G4
G2
F3
E3
D2
E2
C1
D5
F7
E6
D4
B3
C4
A2
C3
B2
B5
C6
A22
A7
Y21
Y24
Y23
Y26
V24
U10A
DBI0#
DBI1#
DBI2#
DBI3#
IERR#
MCERR#
FERR#
STPCLK#
BINIT#
INIT#
RSP#
DBSY#
DRDY#
TRDY#
ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#
TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#
RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6
BSEL0
BSEL1
PWRGOOD
RESET#
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
V22
HD#53
HA#31
AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
D52#
D51#
D50#
D49#
D48#
D47#
D46#
D45#
D44#
D43#
D42#
D41#
U21
V25
U23
U24
U26
T23
T22
HD#48
HD#47
HD#51
HD#50
HD#46
HD#49
HD#52
D40#
T25
T26
R24
R25
P24
R21
HD#41
HD#45
HD#42
HD#44
HD#43
HD#40
HA#18
HA#24
A24#
A23#
D39#
D38#
N25
N26
HD#39
HD#38
M26
HD#37
A22#
D37#
N23
HA#16
HA#21
HA#20
HA#19
HA#17
A21#
A20#
A19#
A18#
A17#
A16#
D36#
D35#
D34#
D33#
D32#
D31#
M24
P21
N22
M23
H25
HD#32
HD#34
HD#31
HD#35
HD#33
HD#36
HA#9
HA#5
HA#4
HA#14
HA#10
HA#15
HA#11
HA#13
HA#12
A15#
A14#
A13#
A12#
A11#
A10#
D30#
D29#
D28#
D27#
D26#
D25#
K23
J24
L22
M21
H24
G26
HD#29
HD#26
HD#30
HD#28
HD#25
HD#27
HA#3
HA#7
HA#6
ITP_DBR#
AE25A5A4
AD26
A9#
A8#
A7#
A6#
A5#
A4#
A3#
DBR#
ITP_CLK1
VCC_SENSE
VSS_SENSE
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
D15#
D14#
D13#
D12#
D11#
L21
D26
F26
E25
F24
F23
G23
E24
H22
HD#19
HD#23
HD#24
HD#16
HD#22
HD#20
HD#18
HD#21
HD#17
D10#
D25
J21
D23
C26
H21
G22
HD#10
HD#14
HD#15
HD#11
HD#12
HD#13
AC26
ITP_CLK0
D9#
D8#
B25
C24
HD#8
HD#9
VID1
VID2
VID4
VID3
AE1
AE2
AE3
AE4
VID4#
VID3#
VID2#
VID1#
D7#
D6#
D5#
D4#
D3#
C23
B24
D22
C21
A25
HD#5
HD#4
HD#3
HD#7
HD#6
CPU GTL REFERNCE VOLTAGE BLOCK
C135
220p
C136
2/3*Vccp
C129
220p
C128 R116
GTLREF1
Every pin put one 220pF cap near it.
Trace Width 15mils, Space 15mils.
Keep the voltage divider within
1.5" of the GETREF pin.
GTLREF2
CPU ITP BLOCK
CB178
0.1u
CB177
0.1u
C118
1u-0805220p
C404
X_1u-0805
CB176
0.1u
VCCP
VCCP
VCCP
R115
49.9
100220p
R215
X_49.9
R727
X_100
A A
BPM#4
BPM#5
BPM#2
BPM#3
8
R133 49.9RST
R130 49.9RST
R531 49.9RST
R532 49.9RST
VCCP
7
CPU STRAPPING RESISTORS
ITP_TDI
ITP_TDO
ITP_TMS
ITP_TCK
ITP_TRST#
R177 150 R141 62
R220 75
R216 39
R218 27
R139 680
6
ALL COMPONENTS CLOSE TO CPU
VCCP VCCP
ITP_DBR#
R109 X_0
R214 X_150
5
ITP_GD {18}
VCC3
PROCHOT#
CPU_GD
HBR#0
CPURST#
TRMTRIP#
HINIT#
4
R131 300
R176 49.9RST
R114 49.9RST
R175 62
R429 300
3
ALL COMPONENTS CLOSE TO CPU
MSI
Title
Size Document Number Rev
Date: Sheet of
mPGA478-B INTEL CPU SOCKET Part1
2
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
MS-6542
4 27Wednesday, November 07, 2001
1
0AE2
8
7
6
5
4
3
2
1
CPU VOLTAGE BLOCK
VCCP
D D
C C
B B
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
XX11
XX12
XX13
XX14
XX15
VSS
AD10
VSS
VSS
AD12
VSS
VSS
VSS
VSS
AD14
XX16X1X2X3X4
VSS
VSS
AD16
AD18
U10B
D10
VSS
A11
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A24
VSS
A26
VSS
A3
VSS
A9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AD21
VSS
VSS
AD23
VSS
VSS
AD4
VSS
VSS
AD8
VSS
VSS
AE11
VSS
AE13
VSS
A10
AE15
VCC
VSS
A12
AE17
VCC
VSS
A14
AE19
VCC
VSS
A16
VCC
VSS
AE22
A18
A20A8AA10
VCC
VCC
VSS
VSS
AE24
AE26
AE7
VCC
VSS
AE9
VCC
VSS
AA12
AF1
VCC
VSS
AA14
AF10
VCC
VSS
AA16
AF12
VCC
VSS
AA18
AF14
VCC
VSS
AA8
AF16
VCC
VSS
AB11
AF18
VCC
VSS
AB13
AF20
VCC
VSS
AB15
AF6
VCC
VSS
AB17
AF8
VCC
VSS
AB19
B10
VCC
VSS
AB7
B12
VCC
VSS
AB9
B14
VCC
VSS
AC10
B16
VCC
VSS
AC12
B18
VCC
VSS
AC14
B20
VCC
VSS
AC16
B23
AC18
VCC
VCC
VSS
VSS
B26B4B8
AC8
VCC
VSS
AD11
VCC
VSS
AD13
C11
VCC
VSS
AD15
C13
VCC
VSS
AD17
C15
AD19
VCC
VSS
C17C2C19
AD7
VCC
VSS
VCC
VSS
AD9
AE10
VCC
VSS
C22
AE12
AE14
AE16
AE18
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
C25C5C7C9D12
AE20
VCC
VSS
VCC
VSS
AE6
D14
AE8
VCC
VSS
D16
AF11
AF13
AF15
AF17
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
D18
D20
D21D3D24D6D8E1E11
VCC
VSS
AF19
VCC
VSS
AF2
VCC
VSS
AF21
VCC
VSS
AF5
VCC
VSS
AF7
VCC
VSS
AF9
E13
VCC
VSS
B11
B13
B15
B17
B19B7B9
C10
C12
C14
C16
C18
C20C8D11
D13
D15
D17
D19D7D9
E10
E12
E14
E16
E18
E20E8F11
F13
F15
F17
F19
F9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E15
E17
E19
E23
E7E9F10
F12
F14
F16
E4
E26
F18F2F22
F25F5F8
G21G6G24
VSS
VSS
G3H1H23
VSS
VSS
VSS
H26H4J2
VSS
VSS
J22
VSS
VSS
J25J5K21
VSS
VSS
XX1
VSS
XX2
VSS
XX3
AF4
VCC-VID
VSS
VSS
XX4
AF3
VCC-VIDPRG
VSS
VSS
XX5
XX6
XX7
AD20
AE23
VCC-IOPLL
VSS
VSS
VSS
XX8
XX9
XX10
VCCA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SOCKET478
AD22
Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24
VCC_VID {19}
C121
22u-1206
L1 4.7uH-1206
L2 4.7uH-1206
C122
22u-1206
VCCP
CPU DECOUPLING CAPACITORS
WITHIN CPU
VCCP VCCP VCCPVCCP VCCPVCCP VCCP
CB124
10u-1206
CB112
10u-1206/S
CB127
10u-1206
CB125
10u-1206
CB126
10u-1206
CB79
A A
10u-1206
CB150
10u-1206
CB153
10u-1206
CB147
10u-1206
CB152
10u-1206
CB78
10u-1206
CB77
10u-1206
CB76
10u-1206
CB151
10u-1206
CB128
10u-1206
CB154
10u-1206
CB155
10u-1206
CB149
10u-1206
CB148
10u-1206
CB156
10u-1206
CB81
10u-1206
CB82
10u-1206
CB83
10u-1206
CB72
10u-1206
CB75
10u-1206
CB73
10u-1206
CB74
10u-1206
CB80
10u-1206
CB65
0.1u
CB92
0.1u
CB49
0.1u
CB59
0.1u
CB28
0.1u
CB29
0.1u
CB31
0.1u
CB69
0.1u
CB30
0.1u
CB117
0.1u
CB68
0.1u
PLACE CAPS WITHIN CPU CAVITY
8
7
6
5
4
VCCP
PLACE CAPS
WITHIN CPU
CAVITY
SOLDER
CB260
10u-1206/S
CB261
10u-1206/S
CB262
10u-1206/S
CB263
10u-1206/S
CB114
10u-1206/S
CB115
10u-1206/S
CB113
10u-1206/S
3
Solder side
CAVITY
+
CT39
150u-2.5V
+
CT41
150u-2.5V
+
CT68
150u-2.5V/S
+
CT67
150u-2.5V/S
MSI
Title
Size Document Number Rev
Date: Sheet of
2
Power Zone decoupling caps
C99 0.1u
C258 X_0.1u
VCCP
C257 X_0.1u
VCCP
C259 X_0.1u
VCCP
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
mPGA478-B INTEL CPU Part2
MS-6542
5 27Saturday, November 03, 2001
VCC5VCCP
VCC5
0AE2
1
5
HA#[3..31]{4} HD#[0..63] {4}
* Length must be matched
within +/-0.1"of the Strobe
Signals
D D
HBR#0{4}
HBNR#{4}
HBPRI#{4}
HLOCK#{4}
HADS#{4}
HREQ#[0..4]{4}
C C
HIT#{4}
HITM#{4}
HDEFER#{4}
HTRDY#{4}
HRS#[0..2]{4}
HDBSY#{4}
HDRDY#{4}
HADSTB#0{4}
HADSTB#1{4}
HDSTBN#0{4}
HDSTBP#0{4}
HDSTBN#1{4}
HDSTBP#1{4}
HDSTBN#2{4}
HDSTBP#2{4}
HDSTBN#3{4}
HDSTBP#3{4}
B B
HDBI#[0..3]{4}
MCHCLK{3}
MCHCLK#{3}
HL[0..5]{8}
HL_STB{8}
HL_STB#{8}
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HRS#0
HRS#1
HRS#2
HDBI#0
HDBI#1
HDBI#2
HDBI#3
R150 24.9
R138 24.9
HL0
HL1
HL2
HL3
HL4
HL5
VCCP
HL[10..0]
20mils
A A
15mils
20mils
* Max Length : 8"
* Length must be matched within +/- 0.1"
of the Strobe Signals
Others
HL[0:10]
HL[0:10]
Others
5
AD4
AD3
AE6
AE7
AE11
AD11
AC15
AC16
AD5
AG4
AH9
AD15
AC2
AC13
M26
M25
AA9
AB8
AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20
AG19
AG21
AG23
AJ19
AJ21
AJ23
T4
T5
T3
U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3
K4
M4
M3
L3
L5
K3
J2
M5
J3
L2
H4
N5
G2
M6
L7
V7
W3
Y7
W5
V3
U6
T7
R7
U5
U2
Y5
Y3
Y4
U7
W2
W7
W6
V5
V4
R5
N6
J8
K8
P25
P24
N27
P23
N25
N24
M8
U8
U11A
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
BR0#
BNR#
BPRI#
HLOCK#
ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HIT#
HITM#
DEFER#
HTRDY#
RS0#
RS1#
RS2#
DBSY#
DRDY#
HAD_STB0#
HAD_STB1#
HD_STBN0#
HD_STBP0#
HD_STBN1#
HD_STBP1#
HD_STBN2#
HD_STBP2#
HD_STBN3#
HD_STBP3#
DBI0#
DBI1#
DBI2#
DBI3#
BCLK
BCLK#
H_RCOMP0
H_RCOMP1
HI0
HI1
HI2
HI3
HI4
HI5
HI_STB
HI_STB#
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Brookdale_MCH
HOST
HUB LINK
POWER
4
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
66IN
RSTIN#
CPURST#
H_VREF0
H_VREF1
H_VREF2
H_VREF3
H_VREF4
H_SWNG0
H_SWNG1
HI10
HI_REF
HL_RCOMP
VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8
RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
NC0
NC1
4
3
HD#0
AA2
HD#1
AB5
HD#2
AA5
HD#3
AB3
HD#4
AB4
HD#5
AC5
HD#6
AA3
HD#7
AA6
HD#8
AE3
HD#9
AB7
HD#10
AD7
HD#11
AC7
HD#12
AC6
HD#13
AC3
HD#14
AC8
HD#15
AE2
HD#16
AG5
HD#17
AG2
HD#18
AE8
HD#19
AF6
HD#20
AH2
HD#21
AF3
HD#22
AG3
HD#23
AE5
HD#24
AH7
HD#25
AH3
HD#26
AF4
HD#27
AG8
HD#28
AG7
HD#29
AG6
HD#30
AF8
HD#31
AH5
HD#32
AC11
HD#33
AC12
HD#34
AE9
HD#35
AC9
HD#36
AE10
HD#37
AD9
HD#38
AG9
HD#39
AC10
HD#40
AE12
HD#41
AF10
HD#42
AG11
HD#43
AG10
HD#44
AH11
HD#45
AG12
HD#46
AE13
HD#47
AF12
HD#48
AG13
HD#49
AH13
HD#50
AC14
HD#51
AF14
HD#52
AG14
HD#53
AE14
HD#54
AG15
HD#55
AG16
HD#56
AG17
HD#57
AH15
HD#58
AC17
HD#59
AF16
HD#60
AE15
HD#61
AH17
HD#62
AD17
HD#63
AE16
P22
J27
AE17
HVREF
M7
R8
Y8
AB11
AB17
HSWNG
AA7
AD13
HL6
L28
HI6
HI7
HI8
HI9
L27
M27
N28
M24
P26
P27
L25
L29
M22
N23
N26
B19
C5
C8
C23
C26
D12
F26
H27
K23
K25
AD26
AD27
HL7
HL8
HL9
HL10
HUB_MREF
R163 40.2
VCC1_8
MCH_66 {3}
PCIRST#1 {3}
CPURST# {4}
VCC1_8
HL[6..10] {8}
VCC_AGP
MEM_STR
3
VTT1
VTT2
VTT_GND1
VTT_GND2
W22
W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23
AG29
AJ25
G29
AD12
AD14
AD16
AD19
AD22
AE1
AE4
AE18
AE20
AE29
AF5
AF7
AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25
AG1
AG18
AG20
AG22
AH19
AH21
AH23
AJ11
AJ13
AJ15
AJ17
AJ27
R22
R29
U22
U26
N14
N16
P13
P15
P17
R14
R16
T15
U14
U16
T13
T17
A5
A9
A13
A17
A21
A25
C1
C29
D7
D11
D15
D19
D23
D25
F6
F10
F14
F18
F22
G1
G4
H8
H10
H12
H14
H16
H18
H20
H22
H24
J5
J7
K6
K22
K24
K26
L23
U13
U17
AJ3
AJ5
AJ7
AJ9
U11C
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Brookdale_MCH
POWER
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
A3
A7
A11
A15
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J26
J29
K5
K7
K27
L1
L4
L6
L8
L22
L24
L26
M23
N1
N4
N8
N13
N15
N17
N22
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10
2
Title
Size Document Number Rev
Date: Sheet of
MCH REFERENCE BLOCK
VTT1
VTT_GND1
VTT2
VTT_GND2
Place 1 Cap. as Close as possible to
every pin of MCH
Trace width use 15 mils and 15mils space
HVREF
C130
0.1u
Place 1 Cap. as Close as possible to
every pin of MCH
Trace width use 15 mils and 15mils space
Place 0.01uF Cap. as Close as possible to MCH
Trace width use 15 mils and 15mils space
Solder side
HSWNG
C140
HUB_MREF
CB94
0.1u/S
CB103
0.1u/S
C137 C131
0.01u
C138
0.01u
C142
MCH Trace Decoupling Capacitors
VCCP VCCP VCC1_8
CB46
0.1u
CB47
0.1u
CB45
0.1u
ADDRESS DATA MCH & ICH2
MSI
Brookdale MCH-1 (HOST)
1
L3 4.7uH-1206/S
C124
22u-1206/S
L4 4.7uH-1206/S
C125
22u-1206/S
R137
301
C127 R143
0.01u
0.1u
C120
0.01u
C132 R159
C141
0.01u
0.01u
VCC1_8
C173
0.01u/S
C143
C145
0.1u/S
0.1u/S
CB48
0.1u
CB42
0.1u
CB44
0.1u
CB43
0.1u
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
MS-6542
1
VCCP
VCCP
6 27Saturday, November 03, 2001
150
R157
49.9
100
R161
150/S
R160
150/S0.01u/S
VCC_AGP
VCC_AGP
C315
1u/S
Solder side
C144
0.1u0.01u
CB182
0.1u
CB188
0.1u
0AE2
5
4
3
2
1
DCLK0# {13}
DCLK0 {13}
DCLK3# {13}
DCLK3 {13}
DCLK1# {13}
DCLK1 {13}
DCLK4# {13}
DCLK4 {13}
DCLK2 {13}
DCLK2# {13}
DCLK5# {13}
DCLK5 {13}
MSBS0 {13}
MSBS1 {13}
SCB7 {12,13}
SCB3 {12,13}
SCB6 {12,13}
SCB1 {12,13}
SCB0 {12,13}
SCB5 {12,13}
SCB4 {12,13}
SCB2 {12,13}
MRAS# {12,13}
MCAS# {12,13}
MWE# {12,13}
0.1uC133
VCC_AGP
DDR SERIAL RESISTORS
DDRMD[0..63]{12,13}
DDRMAA[0..12] {12,13}
SDQS[0..8] {12,13}
MEM_STR
CB374
0.1u
CB377
0.1u
CB378
0.1u
CB376
0.1u
CB379
0.1u
CB372
0.1u
CB375
0.1u
CB373
0.1u
Place between
DIMMs
VCC1_8
AGPREF
VCC_AGP
CB120
1u-0805/S
CB106
0.1u/S
2
MSI
Title
Size Document Number Rev
Date: Sheet of
DDRMD0
DDRMD4
DDRMD5
DDRMD1
DDRMD6
DDRMD2
DDRMD7
DDRMD3
DDRMD8
DDRMD12
DDRMD9
DDRMD13
DDRMD14
DDRMD15
DDRMD10
DDRMD11
DDRMD20
DDRMD16
DDRMD17
DDRMD21
DDRMD18
DDRMD22
DDRMD19
DDRMD23
DDRMD24
DDRMD28
DDRMD25
DDRMD29
DDRMD26
DDRMD30
DDRMD27
DDRMD31
DDRMD32
DDRMD36
DDRMD37
DDRMD33
DDRMD34
DDRMD38
DDRMD39
DDRMD35
DDRMD44
DDRMD40
DDRMD45 MDQ45
DDRMD41
DDRMD42
DDRMD46
DDRMD43
DDRMD47
DDRMD54
DDRMD50
DDRMD55
DDRMD51
DDRMD48
DDRMD49
DDRMD52
DDRMD53
DDRMD62
DDRMD58
DDRMD63
DDRMD59
DDRMD60
DDRMD61
DDRMD56
DDRMD57
Power Zone decoupling caps
0.1u/SC247
0.1uC246
VCC5
0.1uC123
Brookdale MCH-2 (DDR)
RNS1 331 2
3 4
5 6
7 8
RNS3 331 2
3 4
5 6
7 8
RNS5 33
1 2
3 4
5 6
7 8
RNS7 33
1 2
3 4
5 6
7 8
RNS8 331 2
3 4
5 6
7 8
RNS9 331 2
3 4
5 6
7 8
RNS10 331 2
3 4
5 6
7 8
RNS11 33
1 2
3 4
5 6
7 8
RNS12 33
1 2
3 4
5 6
7 8
RNS13 331 2
3 4
5 6
7 8
R717 33
R718 33
R719 33
R720 33
RNS16 331 2
3 4
5 6
7 8
RNS18 33
1 2
3 4
5 6
7 8
RNS19 33
1 2
3 4
5 6
7 8
RNS20 331 2
3 4
5 6
7 8
RNS21 331 2
3 4
5 6
7 8
VCC_AGP
VCC_AGP
MICRO-STAR
VCC5 VCC3
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
MS-6542
7 27Saturday, November 03, 2001
1
MDQ0
MDQ4
MDQ5
MDQ1
MDQ6
MDQ2
MDQ7
MDQ3
MDQ8
MDQ12
MDQ9
MDQ13
MDQ14
MDQ15
MDQ10
MDQ11
MDQ20
MDQ16
MDQ17
MDQ21
MDQ18
MDQ22
MDQ19
MDQ23
MDQ24
MDQ28
MDQ25
MDQ29
MDQ26
MDQ30
MDQ27
MDQ31
MDQ32
MDQ36
MDQ37
MDQ33
MDQ34
MDQ38
MDQ39
MDQ35
MDQ44
MDQ40
MDQ41
MDQ42
MDQ46
MDQ43
MDQ47
MDQ54
MDQ50
MDQ55
MDQ51
MDQ48
MDQ49
MDQ52
MDQ53
MDQ62
MDQ58
MDQ63
MDQ59
MDQ60
MDQ61
MDQ56
MDQ57
0.1uC82
0.1uC190
0.1uC100
0.1uC101
0AE2
MDQ0
MDQ1
MDQ2
MDQ3
MDQ4
MDQ5
MDQ6
MDQ7
MDQ8
D D
C C
Trace
lengh must
equal 1".
B B
GAD[0..31]{14}
A A
GC_BE#[0..3]{14}
MDQ9
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
MDQ32
MDQ33
MDQ34
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
R183 0
GAD0
GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31
GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3
5
G28
G27
AA28
AB25
AB27
AA27
AB26
AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24
AA23
F27
C28
E28
H25
F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10
C9
D8
E8
E11
B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E5
C3
D3
F4
F3
B2
C2
E2
G5
G3
H3
R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26
Y23
V25
V23
Y25
U11B
SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63
RD_CLKIN
RD_CLKO
G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31
G_C/BE0#
G_C/BE1#
G_C/BE2#
G_C/BE3#
Brookdale_MCH
DDR
AGP
SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8
SMA9
SMA10
SMA11
SMA12
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7
SCKE0
SCKE1
SCKE2
SCKE3
SCS0#
SCS1#
SCS2#
SCS3#
SCK0
SCK0#
SCK1
SCK1#
SCK2
SCK2#
SCK3
SCK3#
SCK4
SCK4#
SCK5
SCK5#
SBS0
SBS1
SRAS#
SCAS#
SWE#
SM_RCOMP
SD_REF0
SD_REF1
G_FRAME#
G_IRDY#
G_TRDY#
G_DEVSEL#
G_STOP#
G_PAR
G_REQ#
G_GNT#
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
SB_STB
SB_STB#
ST0
ST1
ST2
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
PIPE#
RBF#
WBF#
AGPREF
G_RCOMP
TESTIN#
E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22
F26
C26
C23
B19
D12
C8
C5
E3
E15
C16
D16
B15
C14
B17
C17
C15
D14
G23
E22
H23
F23
E9
F7
F9
E7
E14
F15
J24
G25
G6
G7
G15
G14
E24
G24
H5
F5
G12
G13
F11
G8
G11
J28
J9
J21
Y24
W27
W24
W28
W23
W25
AG24
AH25
AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25
AF27
AF26
AG25
AF24
AG26
R24
R23
AC27
AC28
AF22
AE22
AE23
AA21
AD25
H26
4
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MSDQS0
MSDQS1
MSDQS2
MSDQS3
MSDQS4
MSDQS5
MSDQS6
MSDQS7
MSDQS8
MSCB0
MSCB1
MSCB2
MSCB3
MSCB4
MSCB5
MSCB6
MSCB7
MSCKE0
MSCKE1
MSCKE2
MSCKE3
MSCS0#
MSCS1#
MSCS2#
MSCS3#
MSCK0
MSCK0#
MSCK1
MSCK1#
MSCK2
MSCK2#
MSCK3
MSCK3#
MSCK4
MSCK4#
MSCK5
MSCK5#
SBS0
SBS1
RAS#
CAS#
WE#
R182
30.1RSTX_10pC159
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
ST0
ST1
ST2
CB118 0.1u
R147 40.2
C317 0.1u
DDR_VREF
C316 0.1u/S
C302 0.1u/S
GFRAME# {14}
GIRDY# {14}
GTRDY# {14}
GDEVSEL# {14}
GSTOP# {14}
GPAR {14}
GREQ# {14}
GGNT# {14}
SB_STB {14}
SB_STB# {14}
GAD_STB0 {14}
GAD_STB#0 {14}
GAD_STB1 {14}
GAD_STB#1 {14}
PIPE# {14}
RBF# {14}
WBF# {14}
AGPREF {14}
MSCKE[0..3] {12,13}
MSCS0# {12,13}
MSCS1# {12,13}
MSCS2# {13}
MSCS3# {13}
VTT_DDR
Less then 1"
Solder side
SBA[0..7] {14}
ST[0..2] {14}
MSCK0#
RNS2 0
MSCK0
MSCK3#
MSCK3
MSCK1#
MSCK1
MSCK4#
MSCK4
MSCK2
MSCK2#
MSCK5#
MSCK5
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA8
MA10
MSDQS0
MSDQS1
MSDQS2
MSDQS3
MSDQS4
MSDQS5
MSDQS6
MSDQS7
MSDQS8
SBS0 MSBS0
SBS1 MSBS1
MSCB7
MSCB3
MSCB6
MSCB1
MSCB0
MSCB5
MSCB4
MSCB2 SCB2
RAS#
CAS#
WE#
MA7
MA9
MA11
7 8
5 6
3 4
1 2
RNS4 0
7 8
5 6
3 4
1 2
RNS6 01 2
3 4
5 6
7 8
R675 10
R676 10
R677 10
R678 10
R679 10
R680 10
R681 10
R683 10
R685 10
R687 10
R688 10
R689 10
R690 10
R691 10
R692 10
R693 10
R694 10
R695 10
R696 10
R697 10
R699 10
RNS15 101 2
3 4
5 6
7 8
RNS17 101 2
3 4
5 6
7 8
R698 10
R721 10
R722 10
R723 10
RNS22 101 2
3 4
5 6
7 8
DDRMAA0
DDRMAA1
DDRMAA2
DDRMAA3
DDRMAA4
DDRMAA5
DDRMAA6
DDRMAA7
DDRMAA8
DDRMAA9
DDRMAA10
DDRMAA11
DDRMAA12MA12
MCH DECOUPLING CAPACITOR
VCC1_8
CB163
100p/S
CB167
10p
3
DCLK0#
DCLK0
DCLK3#
DCLK3
DCLK1#
DCLK1
DCLK4#
DCLK4
DCLK2
DCLK2#
DCLK#5
DCLK5
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
SCB7
SCB3
SCB6
SCB1
SCB0
SCB5
SCB4
MRAS#
MCAS#
MWE#
DDRMAA7
DDRMAA9
DDRMAA11
C134 1u-0805
Put MCH845 solder side
ICH2 PCI / HUB LINK / CPU / LAN / INTERRUPT SIGNALS
ICH2 SMI# SIGNAL
VCC1_8
D10D2E5
K19
L19P5V9
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
VCC1.8
GND1
GND2
GND3
GND4
GND5
A1A2A10B1B2B3B9
E14
GND6
AD[0..31]{15,22,23}
C_BE#[0..3]{15,22,23}
DEVSEL#{15,22,23}
FRAME#{15,22,23}
IRDY#{15,22,23}
TRDY#{15,22,23}
STOP#{15,22,23}
PAR{15,22,23}
PLOCK#{15,22}
SERR#{15,22,23}
PERR#{15,22,23}
PME#{14,15,22,23}
VCC3
ICH_PCLK{3}
PCIRST#{3,17}
EE_EECS{21}
EE_DIN{21}
EE_DOUT{21}
EE_SHCLK{21}
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
C_BE#0
C_BE#1
C_BE#2
C_BE#3
GP0
R568 10K
EE_EECS
EE_DIN
EE_DOUT
EE_SHCLK
AA4
AB4
AB3
AA5
AB5
AA6
AA8
AB8
AB9
W10
AA10
AA3
AB6
AA9
AB7
AA7
W11
AA15
Y4
W5
W4
Y5
Y3
W6
W3
Y6
Y2
Y1
V2
V1
U4
W9
U3
Y9
U2
U1
T4
Y10
T3
Y8
V3
W8
V4
W1
W2
W7
Y7
Y15
M3
L2
F4
G4
H3
H4
J1
K4
K3
J4
J3
U16A
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
CBE#0
CBE#1
CBE#2
CBE#3
DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PLOCK#
SERR#
PERR#
PME#
GPIO0/REQA#
GPIO16/GNTA#
PCICLK
PCIRST#
NC12
NC13
NC14
NC15
NC16
EE_CS
EE_DIN
EE_DOUT
EE_SHCLK
VCC1.8
VCC3
E15
E16
E17
E18
F18
G18
H18
J18
P18
R18R5T5U5V5V6V7V8V14
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
VCC3
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
B10C2C3C4C9D5D6D7D8D9E6E7E8E9J9
GND19
VCC3
VCC3
GND20
GND21
VCC3
VCC3
GND22
GND23
J10
VCC3
GND24
J11
J12
VCC1_8SB
V15
V16H5J5
VCCSUS1_8
VCCSUS1_8
GND25
GND26
GND27
J13
J14K9K10
A22
VCCSUS1_8
VCCSUS1_8
VCCSUS1_8
GND28
GND29
GND30
GND31
K11
K12
K13
B21
B22C1D1D3E1E2E3
GND68
GND69
GND70
GND71
GND32
GND33
GND58
GND59
K14J2K1
AA1
AA2
E4
NC5
NC6
NC8
NC9
CPUSLP#
NC10
NC11
NC17
FERR#
IGNNE#
STPCLK#
A20GATE
HL_STB
HL_STB#
HLCOMP
HUBREF
PIRQA#
PIRQB#
PIRQC#
PIRQD#
APICCLK
APICD0
APICD1
SERIRQ
REQ0#
REQ1#
REQ2#
REQ3#
LAN_CLK
LAN_RSTSYNC
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
GND62
GND63
GND64
GND65
INT-82801BA-C0(SL5PN)
AB1
AB2
AB21
REQ4#
GNT0#
GNT1#
GNT2#
GNT3#
GNT4#
GND67
GND66
GPIO1/REQB#/REQ5#
GPIO17/GNTB#/GNT5#
GND60
GND61
AA21
AA22
A20M#
INIT#
INTR
NMI
SMI#
RCIN#
HL10
HL11
IRQ14
IRQ15
SMI#
R264 33
C191
100pC193
R297 62
R304 8.2K
R267 10K
R271 10K
R223 2.7K
R567 X_10K
R303 10K
R310 10K
C187
0.1u
D11
A12
FERR#
R22
A11
C12
C11
B11
SMI#
B12
C10
KB_RST#
B13
A20GATE#
C13
HL0
A4
HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3
B4
P1
P2
P3
N4
F21
C16
N20
P22
N19
N21
R2
R3
T1
AB10
P4
L3
M2
M1
R4
T2
R1
L4
G3
H2
G2
G1
H1
F3
F2
F1
A21
AB22
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10
R240 40.2
HUB_IREF
APICCLK
APIC_D0
APIC_D1
SERIRQ
PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5
PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4
ELAN_CLK
ELAN_SYNC
ELAN_RXD0
ELAN_RXD1
ELAN_RXD2
ELAN_TXD0
ELAN_TXD1
ELAN_TXD2
A20M# {4}
SLP# {4}
FERR# {4}
IGNNE# {4}
HINIT# {4,12}
INTR {4}
NMI {4}
STPCLK# {4}
KB_RST# {10}
A20GATE# {10}
HL[0..10] {6}
This resistor less than 0.5"
from ICH use 15 mils trace
HL_STB {6}
HL_STB# {6}
VCC1_8
INTA# {14,15,22}
INTB# {14,15,22}
INTC# {15,22}
INTD# {15,22}
IRQ14 {3}
IRQ15 {3}
SERIRQ {10}
PREQ#0 {15}
PREQ#1 {15}
PREQ#2 {15}
PREQ#3 {15,22}
PREQ#4 {15,23}
PREQ#5 {15}
PGNT#0 {15}
PGNT#1 {15}
PGNT#2 {15}
PGNT#3 {22}
PGNT#4 {23}
ELAN_CLK {21}
ELAN_SYNC {21}
ELAN_RXD0 {21}
ELAN_RXD1 {21}
ELAN_RXD2 {21}
ELAN_TXD0 {21}
ELAN_TXD1 {21}
ELAN_TXD2 {21}
ICH2 STRAPPING RESISTORS
FERR#
SERIRQ
KB_RST#
A20GATE#
GP0
EE_DOUT
APIC_D0
APIC_D1
APICCLK
ICH2 REFERENCE VOLTAGE
HUB_IREF
C182
0.01u
C183
0.1u
HSMI# {4}
VCC1_8
VCCP
VCC3
VCC3
VCC3
R241
150
R245
1500.01u
VCC3
CB210
CB186
0.1u 0.01u
0.1u 0.01u
Place one 0.1U/0.01U pair in each corner and
2 on opposite sides close to ICH2 if it fit
0.1u
CB184
0.1u
CB105
0.1u/S
ICH2 DECOUPLING CAPACITORS
VCC1_8
CB161
CB64CB214
CB203
0.1u
Distribute near the 1.8V
power pin of the ICH2
CB411
0.1u
CB412
0.1u
VCC1_8SB
CB180
CB202
0.1u
0.1u
Distribute near the VCC1_8SB
Power pin of the ICH2
Place Cap. as Close as possible to ICH2
Trace width use 15 mils and 15mils space
MSI
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
Brookdale ICH2 PCI
MS-6542
8 27Saturday, November 03, 2001
0AE2
PWR_GD{18}
ICH_VRM_GD{17}
PWRBTN#{18}
10/05/'01 Update
RSM_GD{21}
SMB_DATA_RSM{15,21,22}
SMB_CLK_RSM{15,21,22}
INTRUDER#{18}
AC_RST#{11}
AC_SYNC{11}
AC_BCLK{11}
AC_SDOUT{11}
AC_SDIN0{11}
SIO_PME#{10}
GPI_ESUPPORT#{18}
GPI_INTRUD_CABLE#{18}
LAD0/FWH0{10,12}
LAD1/FWH1{10,12}
LAD2/FWH2{10,12}
LAD3/FWH3{10,12}
LFRAME#/FWH4{10,12}
VCC3_SB
CB193
0.1u
ICH2 ASIC / RTC / AC'97 / GPIO / LPC / USB / IDE SIGNALS
THRM#{10}
SLP_S3#{18,19}
SLP_S5#{19}
CPU_GD{4}
RING#{10}
SUSCLK{10}
ICH_66{3}
ICH_14{3}
ICH_48{3}
SPKR{10,18}
LDRQ#{10}
USBP0+{17}
USBP0-{17}
USBP1+{17}
USBP1-{17}
USBP2+{17}
USBP2-{17}
USBP3-{17}
OC#2{17}
OC#1{17,18}
THRM#
PWR_GD
RING#
RSMRST#
R774
RSM_GD
0
SMB_DATA_RSM
SMB_CLK_RSM
SMB_ALERT
SMB_CLK_RSM
SMB_DATA_RSM
INTRUDER#
RTCRST#
VBIAS
RTCX1
RTCX2
AC_BCLK
AC_SDIN0
AC_SDIN1
SPKR
SIO_PME#
GPI_ESUPPORT#
CLEAR_RTC
GPI_INTRUD_CABLE#
PSWD
R261 X_10K
U16B
AA13
THRM#
W16
SLP_S3#
AB18
SLP_S5
R20
PWROK
A13
CPUPWRGD
B15
VRMPWRGD
W21
PWRBTN#
AA17
RI#
R21
RSMRST#
Y16
RSM_PWROK
Y17
SUSSTAT#
AA18
SUSCLK
AA16
SMBDATA
AB16
SMBCLK
AB17
GPIO11/SMBALERT#
U19
SMLINK0
V20
SMLINK1
T19
INTRUDER#
T20
RTCRST#
T21
VBIAS
U22
RTCX1
T22
RTCX2
D4
CLK66
M19
CLK14
P20
CLK48
V22
AC_RST#
P19
AC_SYNC
R19
AC_BITCLK
P21
AC_SDOUT
Y22
AC_SDIN0
W22
AC_SDIN1
N22
SPKR
W14
GPIO12
AB15
GPIO13
L1
GPIO21
B14
GPIO22
A14
GPIO23
AB14
GPIO27
AA14
GPIO28
Y12
LAD0/FWH0
W12
LAD1/FWH1
AB13
LAD2/FWH2
AB12
LAD3/FWH3
AA12
FS0
Y13
LDRQ0#
W13
LDRQ1#
AB11
LFRAME#/FWH4
W17
USBP0+
Y18
USBP0-
AB19
USBP1+
AA19
USBP1-
W18
USBP2+
Y19
USBP2-
AB20
USBP3+
AA20
USBP3-
W19
OC0#
Y20
OC1#
Y21
OC2#
W20
OC3#
ICH2 DECOUPLING CAPACITOR
CB191
0.1u
VCC5_SB VCC5_SBRTC_VCC
CB199
0.1u
VCCP
CB181
0.1u
Distribute near the VCC3_SB power pin of the ICH
RTC_VCC
GND34
GND35
L9
L10
CB213
1u
GND36
L11
U21
VCCRTC
GND37
GND38
L12
L13
VCC3_SB
T18
U18
VCC3SUS1
GND39
GND40
L14M9M10
F5G5V17
VCC3SUS2
VCC3SUS4
VCC3SUS5
VCC3SUS6
GND41
GND42
GND43
GND44
M11
M12
M13
V18
VCC3SUS7
GND45
GND46
M14N9N10
GND47
VCCP VCC5_SB
D12
D13
V19K2M20
VCPU_IO1
VCPU_IO2
GND48
GND49
GND50
GND51
GND52
N11
N12
N13
N14P9P10
CB201
0.1u
1N5817-S-DO-241AC
VCC5REF1
VCC5REF2
VCC5REF_SUS
GPIO2/PIRQE#
GPIO3/PIRQF#
GPIO4/PIRQG#
GPIO5/PIRQH#
GND53
GND54
GND55
GND56
GND57
P11
P12
P13
P14
PDCS1#
SDCS1#
PDCS3#
SDCS3#
PDA0
PDA1
PDA2
SDA0
SDA1
SDA2
PDDREQ
SDDREQ
PDDACK#
SDDACK#
PDIOR#
SDIOR#
PDIOW#
SDIOW#
PIORDY
SIORDY
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
TP0
GPIO6
GPIO7
GPIO8
GPIO18
GPIO19
GPIO20
GPIO24
GPIO25
VCC5_SBVCC3_SB
* Put a GND Plane under X'TAL
R391
R401
X_1K
VCC5VCC3
E21
C15
E19
D15
F20
F19
E22
A16
D16
B16
G22
B18
F22
B17
G19
D17
G21
C17
G20
A17
H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20
D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18
U20
N3
N2
N1
M4
Y11
AA11
Y14
A15
D14
C14
V21
W15
CB179
0.1u
R302
1K
0.1u
CB212
PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15
SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15
BATLOW#
PD_DET
SD_DET
SIO_SMI#
ENET_DIS
PSWD
PD_CS#1 {3}
SD_CS#1 {3}
PD_CS#3 {3}
SD_CS#3 {3}
PD_A0 {3}
PD_A1 {3}
PD_A2 {3}
SD_A0 {3}
SD_A1 {3}
SD_A2 {3}
PD_DREQ {3}
SD_DREQ {3}
PD_DACK# {3}
SD_DACK# {3}
PD_IOR# {3}
SD_IOR# {3}
PD_IOW# {3}
SD_IOW# {3}
PD_IORDY {3}
SD_IORDY {3}
PDD[0..15] {3}
SDD[0..15] {3}
INTE# {15}
INTF# {15}
INTG# {15}
INTH# {15,23}
PD_DET {3}
SD_DET {3}
SIO_SMI# {10}USBP3+{17}
INT-82801BA-C0(SL5PN)
GPO_ESUPP_LED# {18}
ENET_DIS {21}
R571 4.7K
R572
8.2K
VCC3
J_PSWD
1
1
D1x2-BK
2
2
J_PSWD Clear PSWD
Open
Normal
Clear PSWD
*
1 - 2
D3
0
R392
X_3K
PROCHOT BLOCK
VCCP
X_NPN-3904LT1-S-SOT23
PROCHOT#{4}
INTRUDER#
PD_IORDY
SD_IORDY
THRM#
PD_DET
SD_DET
AC_SDIN0
AC_SDIN1
RSMRST#
SPKR
PWR_GD
VCC3_SB
* Please put this block close ICH2
D5
1N4148-S-LL34
R500
1K
R352 300K
R387
X_20M
0.047uC241
R663 22M
R662 2.2M
R298 X_10M R309 10M
R373
X_5.6M
BAT1
THRM#
R256 4.7K
D6
1N5817-S-DO-241AC
R353 1K
Q21
ICH2 STRAPPING RESISTORS
R293 10K
R299 4.7K
R274 4.7K
R263 10K
R315 10K
R317 10K
R374 10K
R375 10K
R273 10K
R292 X_10K
R305 8.2K
RTC_VCC
VCC3
RESUME RESET CIRCUIT BLOCK
R244 100K
2.2u-0805
5 6
U15C
MSI
74LCX14-SOIC14
(VCC3_SB)
C186
Title
Size Document Number Rev
Date: Sheet of
RTC_VCC
C232
0.047u
C211
15p
SMB_CLK_RSM
BATLOW#
SMB_DATA_RSM
SMB_ALERT
SIO_SMI#
SIO_PME#
ENET_DIS
RING#
9 8
U15D
Brookdale ICH2 Other
RTC BLOCK
JBAT1 Clear CMOS
1 - 2
2 - 3
Note : If pop R570 then
non-pop JBAT1, vice versa.
R372
R570
1K
0
RTC_VCC
X3
32K-12.5pf-CSA-309-D
+-30PPM
32pF
JBAT Clear CMOS
Open
Normal
1 - 2
Clear CMOS
CLEAR_RTC
1
1
2
2
R534
1K
1 2
3 4
5 6
7 8
R275 4.7K
R265 4.7K
R266 4.7K
R411 4.7K
R269 8.2K
R664
X_10K
MICRO-STAR
H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih
MS-6542
Normal
Clear CMOS
1
2
3
*
JBAT
D1x2-BK
RN18
4.7K
RSMRST#
9 27Thursday, November 08, 2001
*
JBAT1
X_D1x3-BK
RTCRST#
VBIAS
RTCX1
RTCX2
C212
15p
VCC3_SB
VCC3_SB
0AE2
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