MSI MS-6542 Schematics

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Version 0AE2

MS-6542

10/06/2001 Update

D D

Cover Sheet
Block Diagram
Clock ICS950201 & ATA100 IDE CONNECTORS
mPGA478-B INTEL CPU Sockets
INTEL Brookdale MCH845 -- North Bridge

1
2

3
4 - 5
6 - 7

INTEL (R) Brookdale Chipset
Willamette/Northwood 478pin mPGA-B Processor Schematics

CPU:

Willamette/Northwood mPGA-478B Processor

System Brookdale Chipset:

INTEL MCH845 (North Bridge) +

INTEL ICH2 -- South Bridge
LPC I/O -- LPC47M192

C C

AC'97 Codec AD1887 & Connectors

8 - 9

10

11

INTEL ICH2 (South Bridge)

On Board Chipset:

BIOS -- FWH

FWH -- BIOS & Manual
DDR DIMM1&2
AGP SLOT
PCI SLOT 1 & 2 & 3
IO Connectors
USB CONNECTORS & THERMTRIP CIRCUIT

12

13

14

15

16

17

AC'97 Codec -- AD1887
LPC Super I/O -- LPC47M192
Clock Generation -- ICS950201
LAN -- Intel Kinnerith W82562EM
LAN -- 3COM 3C920V1(Dual-layout)

Expansion Slots:

AGP 1.5V SLOT *1
PCI 2.2 SLOT * 4

Front Panel & ATX Connectors & FAN

B B

18

Votlage Regulator
Intersil HIP6301V+HIP6601A/02A-- CPU Power ( VRM9.2 )
LAN Kinnerith
DDR REGULATOR & PCI SLOT 4
LAN 3COM
MANUAL PARTS
GPIO SETTTING

A A

JUMPER SETTING
HISTORY 27

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7

6

19

20

21

22

23

24

25

26

5

4

3

MSI

Title

Size Document Number Rev

Date: Sheet of

2

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

COVER SHEET

MS-6542

1 27Saturday, November 03, 2001

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0AE2

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1

VCC12 Power
Supply CONN

FMB1

Willamette/Northwood
Socket (mPGA478-B)

(100MHz)

CK408 Clock

(100MHz)

Scalable Bus

AGP 4X (1.5V)
VGA CONN

C C

4X (66MHz) AGP

MCH: Memory

Controller HUB

HUB Interface

(200 MHz)

DDR DIMM1,2

(14.318MHz)

IDE CONN 1&2

ATA33/ATA66/ATA100

ICH2: I/O

Controller HUB

PCI (33MHz)

PCI Slots 1:4

(48MHz)

USB Port 0:1

AC Link

USB Front Panel

USB Port 2:3
USB Back Panel

4 posrt USE on ICH2

B B

Hardware
Monitor

PS2 Mouse &
Keyboard

LPC Bus

SMC I/O
LPC47M192

Parallel &
Serial

FWH: Firmware HUB

Brookdale Chipset

Floppy Disk
Drive CONN

(33MHz)

(33MHz)

AC '97 Audio

Codec

Line Out

CD-ROM

MIC In

Line In

A A

MSI

Title

Size Document Number Rev

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Date: Sheet of

2

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

BLOCK DIAGRAM

MS-6542

2 27Saturday, November 03, 2001

1

0AE2

8

CP1 X_COPPER

VCC3

* Put GND copper under Clock Gen.

D D

connect to every GND pin
* 40 mils Trace on Layer 4
with GND copper around
* put close to every power pin

it

FB29 X_80_0805

Rubycon

CB33

0.1u
filtering from 10K~1M

Trace Width 7mils.
Same Group spacing 15mils

*

Different Group spacing 30mils

*

Differentical clock spacing 7mils on itself

*
*

VCC3

CB361

0.1u

C C

R122 220

VCCP

NPN-3904LT1-S-SOT23

+12V

CP2 X_COPPER

FB30 X_80_0805

CB37

0.1u

for good filtering from 10K~1M

R102 1K

VCC3

R513 220R535 4.7K
C401

4.7u-0805

R536

4.7K

Rubycon

X_NPN-3904LT1-S-SOT23

7

CLOCK GENERATOR BLOCK

CB40

0.1u

CB55

0.1u

CB61

0.1u

CB41

0.1u

CB52

0.1u

CB60

0.01u

CB66

0.01u

CB58

0.01u

U7

50

VDDCPU

46

VDDCPU

47

GND

19

VDD3V66

20

GND

32

VDD3V66

31

GND

8

VDDPCI

9

GND

14

VDDPCI

15

GND

1

VDDREF

4

GND

37

VDD48

36

GND

26

VDDA

27

GND

53

CPU_STP#

34

PCI_STP#

25

PD#

28

VTT_PWRGD#

VCC3V

+

CT15
10u

VDDA3V

+

CT20
10u

VCC3V

R729 1K

R103

Q38

X_1K

6

CPUCLK0

CPUCLK0#

CPUCLK1

CPUCLK1#

CPUCLK2

CPUCLK2#

3V66_0
3V66_1
3V66_2
3V66_3
3V66_4
3V66_5

PCICLK_F0
PCICLK_F1
PCICLK_F2

PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6

REF

48MHz_USB

48MHz_DOT

IREF

GND

MULTSEL0

SCLK

SDATA

ICS950201AF

FS0
FS1
FS2

X1
X2

52
51
49
48
45
44

33
35
21
22
23
24

5
6
7
10
11
12
13
16
17
18

56
2
3

39
38

42
41

43
54
55
40

30
29

*Trace less 0.5"

R83 33
R88 33
R92 33
R94 33
R75 33
R77 33

R514 33
R515 33
R516 33
R517 33

R519 33
R521 33
R518 33
R520 33
R522 33
R524 33
R525 33
R523 33

R71 33
R62 33

32pF

X2 14M-32pf-HC49S-D

R112 33

R97 475

R728 X_1K
R730 10K
R731 1K

FS1

R732 1K

SMB_CLK_MAIN
SMB_DATA_MAIN

5

CPUCLK
CPUCLK#
MCHCLK
MCHCLK#
ITP_CLK
ITP_CLK#

MCH_66
AGPCLK
ICH_66

PCICLK0
PCICLK1
PCICLK2
SIO_PCLK
PCICLK3
LAN_PCLK
ICH_PCLK
FWH_PCLK

ICH_14
SIO_14

22pC93

22pC94

ICH_48

Iref = 2.32mA

VCC3V

MULTSEL0=0 -> 4X Iref
MULTSEL0=1 -> 6X Iref

SMB_CLK_MAIN {10,13,21,23}
SMB_DATA_MAIN {10,13,21,23}

4

CPUCLK {4}
CPUCLK# {4}
MCHCLK {6}
MCHCLK# {6}
ITP_CLK {4}
ITP_CLK# {4}

MCH_66 {6}
AGPCLK {14}
ICH_66 {9}

PCICLK0 {15}
PCICLK1 {15}
PCICLK2 {15}
SIO_PCLK {10}
PCICLK3 {22}
LAN_PCLK {23}
ICH_PCLK {8}
FWH_PCLK {12}

ICH_14 {9}
SIO_14 {10}

ICH_48 {9}

3

Shut Source Termination Resistors

CPUCLK

R86 49.9

CPUCLK#

R91 49.9

MCHCLK

R93 49.9

MCHCLK#

R95 49.9

Trace less 0.2"

49.9ohm for 50ohm M/B impedance

CLOCK STRAPPING RESISTORS

FS1 VCC3V

SMB_CLK_MAIN
SMB_DATA_MAIN

R110 1.5K
R104 X_0
R450 0

FS2 FS1 FS0

0 0 1
0 1 1

R66 4.7K

R63 4.7K

CPU (MHz)

BSEL0 {4}

100 MHz
133 MHz

VCC3

2

1

Pull-Down Capacitors

CPUCLK
CPUCLK#
MCHCLK
MCHCLK#
ITP_CLK
ITP_CLK#
MCH_66
ICH_66
AGPCLK
ICH_PCLK
FWH_PCLK
PCICLK0
PCICLK1
PCICLK2

SIO_PCLK
PCICLK3
ICH_14
SIO_14
LAN_PCLK
ICH_48

used only for EMI issue

X_10pC102
X_10pC105
X_10pC108
X_10pC110
X_10pC95
X_10pC96
X_10pC113
X_10pC114
X_10pC117
X_10pC97
X_10pC98
X_10pC107
X_10pC109
X_10pC111

X_10pC112
X_10pC103
10pC92
10pC90
X_10pC89
10pC469

Trace less 0.2"

Decoupling Capacitors

VCC3V

0.1uCB268Q12

0.1uCB267

0.1uCB266

0.1uCB265

0.1uCB264

PRIMARY IDE BLOCK SECONDARY IDE BLOCK

90D 90D

PRIMAR

HD_RST#

R368 33

B B

A A

PDD[0..7]{9}

PD_DREQ{9}

PD_IOW#{9}

PD_IOR#{9}
PD_IORDY{9}
PD_DACK#{9}

IRQ14{8}

PD_A1{9}

PD_CS#1{9} PD_CS#3 {9}

PD_LED{18}

PCIRST#{8}

PCIRST# PCIRST#

8

PDD7
PDD5

PDD4
PDD3
PDD2
PDD1
PDD0

R354

C242

4.7K

VCC5 VCC5VCC3

220p

RESET BLOCK

1 2

U17A
DM7407-SOIC14
(VCC5_SB) (VCC5_SB)

R332 330

PCIRST#1 {6,10,12,23} PCIRST#2 {14,15,22}

7

CN-BH-D2x20-1:21-BK-A-S3

1

2
3 4
5 6
7 8
91110

13 14
17 18

19
21
23
25
27
29
31
33
35
37

R363
10K

VCC3 VCC3

PDD8
PDD9PDD6
PDD10
PDD11
PDD12

12

PDD13
PDD14

1615

PDD15

22

24

26

R362 470

28

30

32

R316 0

34

36

38

4039

C243
X_4700p

6

ATA100 IDE CONNECTORS

PDD[8..15] {9}

PD_DET {9}
PD_A2 {9}PD_A0{9}

3 4

U17B
DM7407-SOIC14

R96 330

5

PCIRST# HD_RST#

SECON

R338
10K

VCC3

1
3 4
5 6
7 8

91110
13 14
17 18

19
21
23
25
27
29
31
33
35
37

CN-BH-D2x20-1:21-BK-A-S3

2

SDD8
SDD9
SDD10
SDD11
SDD12

12

SDD13
SDD14

1615

SDD15

22
24
26
28

R337 470
30
32
34

R318 0
36
38
4039

C229
X_4700p

MSI

Title

Clock ICS950201 & ATA100 IDE CONNECTORS

Size Document Number Rev

Date: Sheet of

2

HD_RST#

R344 33

SDD[0..7]{9}

SD_DREQ{9}

SD_IOW#{9}

SD_IOR#{9}
SD_IORDY{9}
SD_DACK#{9}

IRQ15{8}
SD_A1{9}
SD_A0{9}

SD_CS#1{9} SD_CS#3 {9}

SD_LED{18}

5 6

U17C
DM7407-SOIC14
(VCC5_SB)

4

SDD7
SDD6
SDD5
SDD4
SDD3
SDD2
SDD1
SDD0

R355

4.7K

R306 1K

VCC5

C228
220p

3

* Trace Width : 5mils
* Trace Spacing : 7mils
* Length(longest)-Length(shortest)<0.5"
* Trace Length less than 5"

SDD[8..15] {9}

SD_DET {9}
SD_A2 {9}

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

3 27Wednesday, November 07, 2001

1

0AE2

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CPU SIGNAL BLOCK

VCCPS+ {20}

VID0

AE5

VID0#

GTLREF3
GTLREF2
GTLREF1
GTLREF0

BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#

REQ4#
REQ3#
REQ2#
REQ1#
REQ0#

TESTHI12
TESTHI11
TESTHI10

TESTHI9
TESTHI8
TESTHI7
TESTHI6
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0

BCLK1#
BCLK0#

COMP1
COMP0

ADSTB1#
ADSTB0#
DSTBP3#
DSTBP2#
DSTBP1#
DSTBP0#
DSTBN3#
DSTBN2#
DSTBN1#
DSTBN0#

LINT1/NMI

LINT0/INTR

D2#

D1#

D0#

A23

B22

B21

HD#0

HD#2

HD#1

VCCPS- {20}
ITP_CLK# {3}
ITP_CLK {3}
VID[0..4] {10,20}

RS2#
RS1#
RS0#

AP1#
AP0#
BR0#

DP3#
DP2#
DP1#
DP0#

SOCKET478

AA21
AA6
F20
F6

AB4
AA5
Y6
AC4
AB5
AC6

H3
J3
J4
K5
J1

AD25
A6
Y3
W4
U6
AB22
AA20
AC23
AC24
AC20
AC21
AA2
AD24

AF23
AF22

F4
G5
F1

V5
AC1
H6

P1
L24

L25
K26
K25
J26

R5
L5
W23
P23
J23
F21
W22
R22
K22
E22

E5
D1

GTLREF1
GTLREF2

BPM#5
BPM#4
BPM#3
BPM#2

HREQ#4
HREQ#3
HREQ#2
HREQ#1
HREQ#0

R127 4.7K
R136 4.7K

R129 4.7K

R135 4.7K

HRS#2
HRS#1
HRS#0

R144 49.9RST
R145 49.9RST

HREQ#[0..4] {6}

VCCP

CPUCLK# {3}
CPUCLK {3}

HRS#[0..2] {6}

HBR#0 {6}

* Short trace

HADSTB#1 {6}
HADSTB#0 {6}
HDSTBP#3 {6}
HDSTBP#2 {6}
HDSTBP#1 {6}
HDSTBP#0 {6}
HDSTBN#3 {6}
HDSTBN#2 {6}
HDSTBN#1 {6}
HDSTBN#0 {6}

NMI {8}
INTR {8}

HA#[3..31]{6}

HA#8

HA#22

HA#25

HA#23

HA#26

HA#27

HA#28

HA#30

HA#29

D D

HDBI#[0..3]{6}

VCCP

FERR#{8}

STPCLK#{8}

HINIT#{8}

HDBSY#{6}

HDRDY#{6}

HTRDY#{6}

HADS#{6}

HLOCK#{6}

HBNR#{6}

HITM#{6}

C C

B B

HBPRI#{6}

HDEFER#{6}

CPU_TMPA{10}

VTIN_GND{10}
TRMTRIP#{17}

PROCHOT#{9}

IGNNE#{8}

HSMI#{8}
A20M#{8}

SLP#{8}

BSEL0{3,14}

CPU_GD{9}

CPURST#{6}

HD#[0..63]{6}

HDBI#0
HDBI#1
HDBI#2
HDBI#3

R537 62

HINIT#

HIT#{6}

ITP_TDI
ITP_TDO
ITP_TMS
ITP_TRST#
ITP_TCK

TRMTRIP#

CPU_GD
CPURST#
HD#63

HD#62
HD#61
HD#60
HD#59
HD#58
HD#57
HD#56
HD#55
HD#54

G25

AC3

AA3
AB2

AF26

AB26

AD2

AD3
AE21
AF24
AF25

AD6

AD5
AB23
AB25
AA24

AA22
AA25

W25
W26

E21
P26

V21

V6
B6
Y4

W5

H5
H2

J6

G1
G4
G2

F3

E3
D2
E2

C1
D5

F7

E6
D4
B3
C4
A2

C3
B2
B5
C6

A22

A7

Y21
Y24
Y23

Y26
V24

U10A

DBI0#
DBI1#
DBI2#
DBI3#

IERR#
MCERR#
FERR#
STPCLK#
BINIT#
INIT#
RSP#

DBSY#
DRDY#
TRDY#

ADS#
LOCK#
BNR#
HIT#
HITM#
BPRI#
DEFER#

TDI
TDO
TMS
TRST#
TCK
THERMDA
THERMDC
THERMTRIP#
GND/SKTOCC#
PROCHOT#
IGNNE#
SMI#
A20M#
SLP#

RESERVED0
RESERVED1
RESERVED2
RESERVED3
RESERVED4
RESERVED5
RESERVED6

BSEL0
BSEL1

PWRGOOD
RESET#
D63#

D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#

D53#

V22

HD#53

HA#31

AB1Y1W2V3U4T5W1R6V2T4U3P6U1T2R3P4P3R2T1N5N4N2M1N1M4M3L2M6L3K1L6K4K2

A35#

A34#

A33#

A32#

A31#

A30#

A29#

A28#

A27#

A26#

A25#

D52#

D51#

D50#

D49#

D48#

D47#

D46#

D45#

D44#

D43#

D42#

D41#

U21

V25

U23

U24

U26

T23

T22

HD#48

HD#47

HD#51

HD#50

HD#46

HD#49

HD#52

D40#

T25

T26

R24

R25

P24

R21

HD#41

HD#45

HD#42

HD#44

HD#43

HD#40

HA#18

HA#24

A24#

A23#

D39#

D38#

N25

N26

HD#39

HD#38

M26

HD#37

A22#

D37#

N23

HA#16

HA#21

HA#20

HA#19

HA#17

A21#

A20#

A19#

A18#

A17#

A16#

D36#

D35#

D34#

D33#

D32#

D31#

M24

P21

N22

M23

H25

HD#32

HD#34

HD#31

HD#35

HD#33

HD#36

HA#9

HA#5

HA#4

HA#14

HA#10

HA#15

HA#11

HA#13

HA#12

A15#

A14#

A13#

A12#

A11#

A10#

D30#

D29#

D28#

D27#

D26#

D25#

K23

J24

L22

M21

H24

G26

HD#29

HD#26

HD#30

HD#28

HD#25

HD#27

HA#3

HA#7

HA#6

ITP_DBR#

AE25A5A4

AD26

A9#

A8#

A7#

A6#

A5#

A4#

A3#

DBR#

ITP_CLK1

VCC_SENSE

VSS_SENSE

D24#

D23#

D22#

D21#

D20#

D19#

D18#

D17#

D16#

D15#

D14#

D13#

D12#

D11#

L21

D26

F26

E25

F24

F23

G23

E24

H22

HD#19

HD#23

HD#24

HD#16

HD#22

HD#20

HD#18

HD#21

HD#17

D10#

D25

J21

D23

C26

H21

G22

HD#10

HD#14

HD#15

HD#11

HD#12

HD#13

AC26

ITP_CLK0

D9#

D8#

B25

C24

HD#8

HD#9

VID1

VID2

VID4

VID3

AE1

AE2

AE3

AE4

VID4#

VID3#

VID2#

VID1#

D7#

D6#

D5#

D4#

D3#

C23

B24

D22

C21

A25

HD#5

HD#4

HD#3

HD#7

HD#6

CPU GTL REFERNCE VOLTAGE BLOCK

C135
220p

C136

2/3*Vccp

C129
220p

C128 R116

GTLREF1

Every pin put one 220pF cap near it.
Trace Width 15mils, Space 15mils.
Keep the voltage divider within

1.5" of the GETREF pin.

GTLREF2

CPU ITP BLOCK

CB178

0.1u

CB177

0.1u

C118
1u-0805220p

C404

X_1u-0805

CB176

0.1u

VCCP

VCCP

VCCP

R115

49.9

100220p

R215

X_49.9

R727

X_100

A A

BPM#4
BPM#5
BPM#2
BPM#3

8

R133 49.9RST
R130 49.9RST
R531 49.9RST
R532 49.9RST

VCCP

7

CPU STRAPPING RESISTORS

ITP_TDI
ITP_TDO
ITP_TMS

ITP_TCK
ITP_TRST#

R177 150 R141 62
R220 75
R216 39

R218 27
R139 680

6

ALL COMPONENTS CLOSE TO CPU

VCCP VCCP

ITP_DBR#

R109 X_0
R214 X_150

5

ITP_GD {18}
VCC3

PROCHOT#
CPU_GD
HBR#0
CPURST#
TRMTRIP#
HINIT#

4

R131 300
R176 49.9RST
R114 49.9RST
R175 62
R429 300

3

ALL COMPONENTS CLOSE TO CPU

MSI

Title

Size Document Number Rev

Date: Sheet of

mPGA478-B INTEL CPU SOCKET Part1

2

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

4 27Wednesday, November 07, 2001

1

0AE2

8

7

6

5

4

3

2

1

CPU VOLTAGE BLOCK

VCCP

D D

C C

B B

AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26

AA4

AA7

AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24

AB3

AB6

AB8
AC11
AC13
AC15
AC17
AC19

AC2
AC22
AC25

AC5

AC7

AC9

AD1

XX11

XX12

XX13

XX14

XX15

VSS

AD10

VSS

VSS

AD12

VSS

VSS

VSS

VSS

AD14

XX16X1X2X3X4

VSS

VSS

AD16

AD18

U10B

D10

VSS

A11

VSS

A13

VSS

A15

VSS

A17

VSS

A19

VSS

A21

VSS

A24

VSS

A26

VSS

A3

VSS

A9

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

VSS

AD21

VSS

VSS

AD23

VSS

VSS

AD4

VSS

VSS

AD8

VSS

VSS

AE11

VSS

AE13

VSS

A10

AE15

VCC

VSS

A12

AE17

VCC

VSS

A14

AE19

VCC

VSS

A16

VCC

VSS

AE22

A18

A20A8AA10

VCC

VCC

VSS

VSS

AE24

AE26

AE7

VCC

VSS

AE9

VCC

VSS

AA12

AF1

VCC

VSS

AA14

AF10

VCC

VSS

AA16

AF12

VCC

VSS

AA18

AF14

VCC

VSS

AA8

AF16

VCC

VSS

AB11

AF18

VCC

VSS

AB13

AF20

VCC

VSS

AB15

AF6

VCC

VSS

AB17

AF8

VCC

VSS

AB19

B10

VCC

VSS

AB7

B12

VCC

VSS

AB9

B14

VCC

VSS

AC10

B16

VCC

VSS

AC12

B18

VCC

VSS

AC14

B20

VCC

VSS

AC16

B23

AC18

VCC

VCC

VSS

VSS

B26B4B8

AC8

VCC

VSS

AD11

VCC

VSS

AD13

C11

VCC

VSS

AD15

C13

VCC

VSS

AD17

C15

AD19

VCC

VSS

C17C2C19

AD7

VCC

VSS

VCC

VSS

AD9

AE10

VCC

VSS

C22

AE12

AE14

AE16

AE18

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

C25C5C7C9D12

AE20

VCC

VSS

VCC

VSS

AE6

D14

AE8

VCC

VSS

D16

AF11

AF13

AF15

AF17

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

D18

D20

D21D3D24D6D8E1E11

VCC

VSS

AF19

VCC

VSS

AF2

VCC

VSS

AF21

VCC

VSS

AF5

VCC

VSS

AF7

VCC

VSS

AF9

E13

VCC

VSS

B11

B13

B15

B17

B19B7B9

C10

C12

C14

C16

C18

C20C8D11

D13

D15

D17

D19D7D9

E10

E12

E14

E16

E18

E20E8F11

F13

F15

F17

F19

F9

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

E15

E17

E19

E23

E7E9F10

F12

F14

F16

E4

E26

F18F2F22

F25F5F8

G21G6G24

VSS

VSS

G3H1H23

VSS

VSS

VSS

H26H4J2

VSS

VSS

J22

VSS

VSS

J25J5K21

VSS

VSS

XX1

VSS

XX2

VSS

XX3

AF4

VCC-VID

VSS

VSS

XX4

AF3

VCC-VIDPRG

VSS

VSS

XX5

XX6

XX7

AD20

AE23

VCC-IOPLL

VSS

VSS

VSS

XX8

XX9

XX10

VCCA

VSSA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

VSS

SOCKET478

AD22

Y5
Y25
Y22
Y2
W6
W3
W24
W21
V4
V26
V23
V1
U5
U25
U22
U2
T6
T3
T24
T21
R4
R26
R23
R1
P5
P25
P22
P2
N6
N3
N24
N21
M5
M25
M22
M2
L4
L26
L23
L1
K6
K3
K24

VCC_VID {19}

C121
22u-1206

L1 4.7uH-1206
L2 4.7uH-1206

C122
22u-1206

VCCP

CPU DECOUPLING CAPACITORS

WITHIN CPU

VCCP VCCP VCCPVCCP VCCPVCCP VCCP

CB124
10u-1206
CB112
10u-1206/S
CB127
10u-1206
CB125
10u-1206
CB126
10u-1206
CB79

A A

10u-1206
CB150
10u-1206

CB153
10u-1206
CB147
10u-1206

CB152
10u-1206
CB78
10u-1206
CB77
10u-1206
CB76
10u-1206
CB151
10u-1206
CB128
10u-1206

CB154
10u-1206
CB155
10u-1206

CB149
10u-1206
CB148
10u-1206

CB156
10u-1206

CB81
10u-1206
CB82
10u-1206
CB83
10u-1206
CB72
10u-1206
CB75
10u-1206
CB73
10u-1206
CB74
10u-1206
CB80
10u-1206

CB65

0.1u
CB92

0.1u
CB49

0.1u
CB59

0.1u
CB28

0.1u
CB29

0.1u

CB31

0.1u
CB69

0.1u
CB30

0.1u
CB117

0.1u
CB68

0.1u

PLACE CAPS WITHIN CPU CAVITY

8

7

6

5

4

VCCP

PLACE CAPS
WITHIN CPU
CAVITY
SOLDER

CB260
10u-1206/S
CB261
10u-1206/S
CB262
10u-1206/S
CB263
10u-1206/S
CB114
10u-1206/S

CB115
10u-1206/S
CB113
10u-1206/S

3

Solder side

CAVITY

+

CT39
150u-2.5V

+

CT41
150u-2.5V

+

CT68
150u-2.5V/S

+

CT67
150u-2.5V/S

MSI

Title

Size Document Number Rev

Date: Sheet of

2

Power Zone decoupling caps

C99 0.1u
C258 X_0.1u

VCCP

C257 X_0.1u

VCCP

C259 X_0.1u

VCCP

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

mPGA478-B INTEL CPU Part2

MS-6542

5 27Saturday, November 03, 2001

VCC5VCCP
VCC5

0AE2

1

5

HA#[3..31]{4} HD#[0..63] {4}

* Length must be matched
within +/-0.1"of the Strobe
Signals

D D

HBR#0{4}

HBNR#{4}

HBPRI#{4}

HLOCK#{4}

HADS#{4}

HREQ#[0..4]{4}

C C

HIT#{4}

HITM#{4}

HDEFER#{4}

HTRDY#{4}

HRS#[0..2]{4}

HDBSY#{4}

HDRDY#{4}

HADSTB#0{4}
HADSTB#1{4}

HDSTBN#0{4}
HDSTBP#0{4}
HDSTBN#1{4}
HDSTBP#1{4}
HDSTBN#2{4}
HDSTBP#2{4}
HDSTBN#3{4}
HDSTBP#3{4}

B B

HDBI#[0..3]{4}

MCHCLK{3}

MCHCLK#{3}

HL[0..5]{8}

HL_STB{8}

HL_STB#{8}

HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31

HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4

HRS#0
HRS#1
HRS#2

HDBI#0
HDBI#1
HDBI#2
HDBI#3

R150 24.9
R138 24.9

HL0
HL1
HL2
HL3
HL4
HL5

VCCP

HL[10..0]

20mils

A A

15mils

20mils

* Max Length : 8"
* Length must be matched within +/- 0.1"

of the Strobe Signals

Others

HL[0:10]
HL[0:10]

Others

5

AD4
AD3
AE6

AE7
AE11
AD11
AC15
AC16

AD5

AG4

AH9
AD15

AC2
AC13

M26

M25

AA9

AB8
AB18
AB20
AC19
AD18
AD20
AE19
AE21
AF18
AF20

AG19
AG21
AG23

AJ19
AJ21
AJ23

T4
T5
T3

U3
R3
P7
R2
P4
R6
P5
P3
N2
N7
N3

K4
M4
M3

L3
L5

K3

J2

M5

J3

L2
H4
N5

G2

M6

L7
V7

W3

Y7

W5

V3
U6

T7

R7
U5
U2

Y5
Y3
Y4

U7

W2
W7
W6

V5
V4

R5
N6

J8
K8

P25
P24
N27
P23

N25
N24

M8

U8

U11A

HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#

BR0#
BNR#
BPRI#
HLOCK#

ADS#
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#

HIT#
HITM#
DEFER#

HTRDY#
RS0#
RS1#
RS2#

DBSY#
DRDY#

HAD_STB0#
HAD_STB1#

HD_STBN0#
HD_STBP0#
HD_STBN1#
HD_STBP1#
HD_STBN2#
HD_STBP2#
HD_STBN3#
HD_STBP3#

DBI0#
DBI1#
DBI2#
DBI3#

BCLK
BCLK#

H_RCOMP0
H_RCOMP1

HI0
HI1
HI2
HI3
HI4
HI5

HI_STB
HI_STB#

VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT

Brookdale_MCH

HOST

HUB LINK

POWER

4

HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#

HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#

66IN

RSTIN#

CPURST#

H_VREF0
H_VREF1
H_VREF2
H_VREF3
H_VREF4

H_SWNG0
H_SWNG1

HI10

HI_REF

HL_RCOMP

VCC1_8
VCC1_8
VCC1_8
VCC1_8
VCC1_8

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9

NC0
NC1

4

3

HD#0

AA2

HD#1

AB5

HD#2

AA5

HD#3

AB3

HD#4

AB4

HD#5

AC5

HD#6

AA3

HD#7

AA6

HD#8

AE3

HD#9

AB7

HD#10

AD7

HD#11

AC7

HD#12

AC6

HD#13

AC3

HD#14

AC8

HD#15

AE2

HD#16

AG5

HD#17

AG2

HD#18

AE8

HD#19

AF6

HD#20

AH2

HD#21

AF3

HD#22

AG3

HD#23

AE5

HD#24

AH7

HD#25

AH3

HD#26

AF4

HD#27

AG8

HD#28

AG7

HD#29

AG6

HD#30

AF8

HD#31

AH5

HD#32

AC11

HD#33

AC12

HD#34

AE9

HD#35

AC9

HD#36

AE10

HD#37

AD9

HD#38

AG9

HD#39

AC10

HD#40

AE12

HD#41

AF10

HD#42

AG11

HD#43

AG10

HD#44

AH11

HD#45

AG12

HD#46

AE13

HD#47

AF12

HD#48

AG13

HD#49

AH13

HD#50

AC14

HD#51

AF14

HD#52

AG14

HD#53

AE14

HD#54

AG15

HD#55

AG16

HD#56

AG17

HD#57

AH15

HD#58

AC17

HD#59

AF16

HD#60

AE15

HD#61

AH17

HD#62

AD17

HD#63

AE16
P22

J27
AE17

HVREF

M7
R8
Y8
AB11
AB17

HSWNG

AA7
AD13

HL6

L28

HI6
HI7
HI8
HI9

L27
M27
N28
M24

P26
P27
L25

L29
M22
N23
N26

B19
C5
C8
C23
C26
D12
F26
H27
K23
K25

AD26
AD27

HL7
HL8
HL9
HL10

HUB_MREF

R163 40.2

VCC1_8

MCH_66 {3}
PCIRST#1 {3}
CPURST# {4}

VCC1_8

HL[6..10] {8}

VCC_AGP

MEM_STR

3

VTT1
VTT2

VTT_GND1
VTT_GND2

W22

W29
AA22
AA26
AB21
AC29
AD21
AD23
AE26
AF23

AG29

AJ25

G29

AD12
AD14
AD16
AD19
AD22

AE1

AE4
AE18
AE20
AE29

AF5
AF7

AF9
AF11
AF13
AF15
AF17
AF19
AF21
AF25

AG1
AG18
AG20
AG22

AH19
AH21
AH23

AJ11

AJ13

AJ15

AJ17

AJ27

R22
R29
U22
U26

N14
N16
P13
P15
P17
R14
R16
T15
U14
U16
T13
T17

A5

A9
A13
A17
A21
A25

C1
C29

D7
D11
D15
D19
D23
D25

F6
F10
F14
F18
F22

G1
G4

H8
H10
H12
H14
H16
H18
H20
H22
H24

J5
J7

K6
K22
K24
K26

L23

U13
U17

AJ3
AJ5
AJ7
AJ9

U11C

VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5
VCC1_5

VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM
VCCSM

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

Brookdale_MCH

POWER

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

2

A3
A7
A11
A15
A19
A23
A27
D5
D9
D13
D17
D21
E1
E4
E26
E29
F8
F12
F16
F20
F24
G26
H9
H11
H13
H15
H17
H19
H21
J1
J4
J6
J22
J26
J29
K5
K7
K27
L1
L4
L6
L8
L22
L24
L26
M23
N1
N4
N8
N13
N15
N17
N22
N29
P6
P8
P14
P16
R1
R4
R13
R15
R17
R26
T6
T8
T14
T16
T22
U1
U4
U15
U29
V6
V8
V22
W1
W4
W8
W26
Y6
Y22
AA1
AA4
AA8
AA29
AB6
AB9
AB10
AB12
AB13
AB14
AB15
AB16
AB19
AB22
AC1
AC4
AC18
AC20
AC21
AC23
AC26
AD6
AD8
AD10

2

Title

Size Document Number Rev

Date: Sheet of

MCH REFERENCE BLOCK

VTT1

VTT_GND1

VTT2

VTT_GND2

Place 1 Cap. as Close as possible to
every pin of MCH
Trace width use 15 mils and 15mils space

HVREF

C130

0.1u

Place 1 Cap. as Close as possible to
every pin of MCH

Trace width use 15 mils and 15mils space

Place 0.01uF Cap. as Close as possible to MCH
Trace width use 15 mils and 15mils space

Solder side

HSWNG

C140

HUB_MREF

CB94

0.1u/S

CB103

0.1u/S

C137 C131

0.01u

C138

0.01u

C142

MCH Trace Decoupling Capacitors

VCCP VCCP VCC1_8

CB46

0.1u
CB47

0.1u
CB45

0.1u

ADDRESS DATA MCH & ICH2

MSI

Brookdale MCH-1 (HOST)

1

L3 4.7uH-1206/S
C124

22u-1206/S

L4 4.7uH-1206/S
C125

22u-1206/S

R137
301

C127 R143

0.01u

0.1u

C120

0.01u

C132 R159

C141

0.01u

0.01u

VCC1_8

C173

0.01u/S

C143

C145

0.1u/S

0.1u/S

CB48

0.1u
CB42

0.1u
CB44

0.1u
CB43

0.1u

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

1

VCCP

VCCP

6 27Saturday, November 03, 2001

150

R157

49.9

100

R161
150/S

R160
150/S0.01u/S

VCC_AGP

VCC_AGP

C315
1u/S

Solder side

C144

0.1u0.01u

CB182

0.1u
CB188

0.1u

0AE2

5

4

3

2

1

DCLK0# {13}
DCLK0 {13}
DCLK3# {13}
DCLK3 {13}

DCLK1# {13}
DCLK1 {13}
DCLK4# {13}
DCLK4 {13}

DCLK2 {13}
DCLK2# {13}
DCLK5# {13}
DCLK5 {13}

MSBS0 {13}
MSBS1 {13}

SCB7 {12,13}
SCB3 {12,13}
SCB6 {12,13}
SCB1 {12,13}
SCB0 {12,13}
SCB5 {12,13}
SCB4 {12,13}

SCB2 {12,13}

MRAS# {12,13}
MCAS# {12,13}
MWE# {12,13}

0.1uC133

VCC_AGP

DDR SERIAL RESISTORS

DDRMD[0..63]{12,13}

DDRMAA[0..12] {12,13}

SDQS[0..8] {12,13}

MEM_STR

CB374

0.1u
CB377

0.1u
CB378

0.1u
CB376

0.1u
CB379

0.1u
CB372

0.1u
CB375

0.1u
CB373

0.1u

Place between
DIMMs

VCC1_8

AGPREF

VCC_AGP

CB120
1u-0805/S
CB106

0.1u/S

2

MSI

Title

Size Document Number Rev

Date: Sheet of

DDRMD0
DDRMD4
DDRMD5
DDRMD1
DDRMD6
DDRMD2
DDRMD7
DDRMD3
DDRMD8
DDRMD12
DDRMD9
DDRMD13
DDRMD14
DDRMD15
DDRMD10
DDRMD11
DDRMD20
DDRMD16
DDRMD17
DDRMD21
DDRMD18
DDRMD22
DDRMD19
DDRMD23
DDRMD24
DDRMD28
DDRMD25
DDRMD29
DDRMD26
DDRMD30
DDRMD27
DDRMD31
DDRMD32
DDRMD36
DDRMD37
DDRMD33
DDRMD34
DDRMD38
DDRMD39
DDRMD35
DDRMD44
DDRMD40
DDRMD45 MDQ45
DDRMD41
DDRMD42
DDRMD46
DDRMD43
DDRMD47
DDRMD54
DDRMD50
DDRMD55
DDRMD51
DDRMD48
DDRMD49
DDRMD52
DDRMD53
DDRMD62
DDRMD58
DDRMD63
DDRMD59
DDRMD60
DDRMD61
DDRMD56
DDRMD57

Power Zone decoupling caps

0.1u/SC247

0.1uC246

VCC5

0.1uC123

Brookdale MCH-2 (DDR)

RNS1 331 2

3 4
5 6
7 8

RNS3 331 2

3 4
5 6
7 8

RNS5 33

1 2
3 4
5 6
7 8

RNS7 33

1 2
3 4
5 6
7 8

RNS8 331 2

3 4
5 6
7 8

RNS9 331 2

3 4
5 6
7 8

RNS10 331 2

3 4
5 6
7 8

RNS11 33

1 2
3 4
5 6
7 8

RNS12 33

1 2
3 4
5 6
7 8

RNS13 331 2

3 4
5 6

7 8
R717 33
R718 33
R719 33
R720 33

RNS16 331 2

3 4

5 6

7 8

RNS18 33

1 2

3 4

5 6

7 8

RNS19 33

1 2

3 4

5 6

7 8

RNS20 331 2

3 4

5 6

7 8

RNS21 331 2

3 4

5 6

7 8

VCC_AGP

VCC_AGP

MICRO-STAR

VCC5 VCC3

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

7 27Saturday, November 03, 2001

1

MDQ0
MDQ4
MDQ5
MDQ1
MDQ6
MDQ2
MDQ7
MDQ3
MDQ8
MDQ12
MDQ9
MDQ13
MDQ14
MDQ15
MDQ10
MDQ11
MDQ20
MDQ16
MDQ17
MDQ21
MDQ18
MDQ22
MDQ19
MDQ23
MDQ24
MDQ28
MDQ25
MDQ29
MDQ26
MDQ30
MDQ27
MDQ31
MDQ32
MDQ36
MDQ37
MDQ33
MDQ34
MDQ38
MDQ39
MDQ35
MDQ44
MDQ40

MDQ41
MDQ42
MDQ46
MDQ43
MDQ47
MDQ54
MDQ50
MDQ55
MDQ51
MDQ48
MDQ49
MDQ52
MDQ53
MDQ62
MDQ58
MDQ63
MDQ59
MDQ60
MDQ61
MDQ56
MDQ57

0.1uC82

0.1uC190

0.1uC100

0.1uC101

0AE2

MDQ0
MDQ1
MDQ2
MDQ3
MDQ4
MDQ5
MDQ6
MDQ7
MDQ8

D D

C C

Trace
lengh must
equal 1".

B B

GAD[0..31]{14}

A A

GC_BE#[0..3]{14}

MDQ9
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
MDQ32
MDQ33
MDQ34
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63

R183 0

GAD0

GAD1
GAD2
GAD3
GAD4
GAD5
GAD6
GAD7
GAD8
GAD9
GAD10
GAD11
GAD12
GAD13
GAD14
GAD15
GAD16
GAD17
GAD18
GAD19
GAD20
GAD21
GAD22
GAD23
GAD24
GAD25
GAD26
GAD27
GAD28
GAD29
GAD30
GAD31

GC_BE#0
GC_BE#1
GC_BE#2
GC_BE#3

5

G28

G27

AA28
AB25
AB27
AA27
AB26

AB23
AA24
AA25
AB24
AC25
AC24
AC22
AD24

AA23

F27
C28
E28
H25

F25
B28
E27
C27
B25
C25
B27
D27
D26
E25
D24
E23
C22
E21
C24
B23
D22
B21
C21
D20
C19
D18
C20
E19
C18
E17
E13
C12
B11
C10
B13
C13
C11
D10
E10

C9
D8
E8

E11

B9
B7
C7
C6
D6
D4
B3
E6
B5
C4
E5
C3

D3
F4
F3

B2

C2

E2

G5
G3

H3

R27
R28
T25
R25
T26
T27
U27
U28
V26
V27
T23
U23
T24
U24
U25
V24
Y27
Y26

Y23

V25
V23
Y25

U11B

SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63

RD_CLKIN
RD_CLKO

G_AD0
G_AD1
G_AD2
G_AD3
G_AD4
G_AD5
G_AD6
G_AD7
G_AD8
G_AD9
G_AD10
G_AD11
G_AD12
G_AD13
G_AD14
G_AD15
G_AD16
G_AD17
G_AD18
G_AD19
G_AD20
G_AD21
G_AD22
G_AD23
G_AD24
G_AD25
G_AD26
G_AD27
G_AD28
G_AD29
G_AD30
G_AD31

G_C/BE0#
G_C/BE1#
G_C/BE2#
G_C/BE3#

Brookdale_MCH

DDR

AGP

SMA0
SMA1
SMA2
SMA3
SMA4
SMA5
SMA6
SMA7
SMA8

SMA9
SMA10
SMA11
SMA12

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7

SCKE0
SCKE1
SCKE2
SCKE3

SCS0#
SCS1#
SCS2#
SCS3#

SCK0

SCK0#

SCK1

SCK1#

SCK2

SCK2#

SCK3

SCK3#

SCK4

SCK4#

SCK5

SCK5#

SBS0
SBS1

SRAS#
SCAS#

SWE#

SM_RCOMP

SD_REF0
SD_REF1

G_FRAME#

G_IRDY#

G_TRDY#

G_DEVSEL#

G_STOP#

G_PAR

G_REQ#
G_GNT#

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

SB_STB

SB_STB#

ST0
ST1
ST2

AD_STB0

AD_STB0#

AD_STB1

AD_STB1#

PIPE#

RBF#

WBF#

AGPREF

G_RCOMP

TESTIN#

E12
F17
E16
G18
G19
E18
F19
G21
G20
F21
F13
E20
G22

F26
C26
C23
B19
D12
C8
C5
E3
E15

C16
D16
B15
C14
B17
C17
C15
D14

G23
E22
H23
F23

E9
F7
F9
E7

E14
F15
J24
G25
G6
G7
G15
G14
E24
G24
H5
F5

G12
G13

F11
G8
G11

J28
J9

J21
Y24

W27
W24
W28
W23
W25

AG24
AH25

AH28
AH27
AG28
AG27
AE28
AE27
AE24
AE25

AF27
AF26

AG25
AF24
AG26

R24
R23
AC27
AC28

AF22
AE22
AE23

AA21
AD25
H26

4

MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8

MA9
MA10
MA11
MA12

MSDQS0

MSDQS1

MSDQS2

MSDQS3

MSDQS4

MSDQS5

MSDQS6

MSDQS7

MSDQS8

MSCB0

MSCB1

MSCB2

MSCB3

MSCB4

MSCB5

MSCB6

MSCB7

MSCKE0

MSCKE1

MSCKE2

MSCKE3

MSCS0#

MSCS1#

MSCS2#

MSCS3#

MSCK0

MSCK0#

MSCK1

MSCK1#

MSCK2

MSCK2#

MSCK3

MSCK3#

MSCK4

MSCK4#

MSCK5

MSCK5#

SBS0

SBS1

RAS#

CAS#

WE#

R182

30.1RSTX_10pC159

SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7

ST0
ST1
ST2

CB118 0.1u
R147 40.2

C317 0.1u

DDR_VREF

C316 0.1u/S
C302 0.1u/S

GFRAME# {14}
GIRDY# {14}
GTRDY# {14}
GDEVSEL# {14}
GSTOP# {14}
GPAR {14}

GREQ# {14}
GGNT# {14}

SB_STB {14}
SB_STB# {14}

GAD_STB0 {14}
GAD_STB#0 {14}
GAD_STB1 {14}
GAD_STB#1 {14}

PIPE# {14}
RBF# {14}
WBF# {14}

AGPREF {14}

MSCKE[0..3] {12,13}

MSCS0# {12,13}
MSCS1# {12,13}
MSCS2# {13}
MSCS3# {13}

VTT_DDR

Less then 1"

Solder side

SBA[0..7] {14}

ST[0..2] {14}

MSCK0#

RNS2 0
MSCK0
MSCK3#
MSCK3

MSCK1#
MSCK1
MSCK4#
MSCK4

MSCK2
MSCK2#
MSCK5#
MSCK5

MA0
MA1
MA2
MA3
MA4
MA5
MA6

MA8
MA10

MSDQS0
MSDQS1
MSDQS2
MSDQS3
MSDQS4
MSDQS5
MSDQS6
MSDQS7
MSDQS8

SBS0 MSBS0
SBS1 MSBS1

MSCB7
MSCB3
MSCB6
MSCB1
MSCB0
MSCB5
MSCB4

MSCB2 SCB2
RAS#

CAS#
WE#

MA7
MA9
MA11

7 8
5 6
3 4
1 2

RNS4 0

7 8
5 6
3 4
1 2

RNS6 01 2

3 4
5 6
7 8

R675 10
R676 10
R677 10
R678 10
R679 10
R680 10
R681 10

R683 10
R685 10
R687 10
R688 10

R689 10
R690 10
R691 10
R692 10
R693 10
R694 10
R695 10
R696 10

R697 10
R699 10

RNS15 101 2

3 4
5 6
7 8

RNS17 101 2

3 4
5 6
7 8

R698 10
R721 10

R722 10
R723 10

RNS22 101 2

3 4
5 6
7 8

DDRMAA0
DDRMAA1
DDRMAA2
DDRMAA3
DDRMAA4
DDRMAA5
DDRMAA6
DDRMAA7
DDRMAA8
DDRMAA9
DDRMAA10
DDRMAA11
DDRMAA12MA12

MCH DECOUPLING CAPACITOR

VCC1_8

CB163
100p/S
CB167
10p

3

DCLK0#
DCLK0
DCLK3#
DCLK3

DCLK1#
DCLK1
DCLK4#
DCLK4

DCLK2
DCLK2#
DCLK#5
DCLK5

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

SCB7
SCB3
SCB6
SCB1
SCB0
SCB5
SCB4

MRAS#
MCAS#
MWE#

DDRMAA7
DDRMAA9
DDRMAA11

C134 1u-0805

Put MCH845 solder side

ICH2 PCI / HUB LINK / CPU / LAN / INTERRUPT SIGNALS

ICH2 SMI# SIGNAL

VCC1_8

D10D2E5

K19

L19P5V9

VCC1.8

VCC1.8

VCC1.8

VCC1.8

VCC1.8

VCC1.8

GND1

GND2

GND3

GND4

GND5

A1A2A10B1B2B3B9

E14

GND6

AD[0..31]{15,22,23}

C_BE#[0..3]{15,22,23}

DEVSEL#{15,22,23}

FRAME#{15,22,23}

IRDY#{15,22,23}

TRDY#{15,22,23}

STOP#{15,22,23}

PAR{15,22,23}

PLOCK#{15,22}

SERR#{15,22,23}
PERR#{15,22,23}

PME#{14,15,22,23}

VCC3

ICH_PCLK{3}

PCIRST#{3,17}

EE_EECS{21}
EE_DIN{21}
EE_DOUT{21}
EE_SHCLK{21}

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C_BE#0
C_BE#1
C_BE#2
C_BE#3

GP0

R568 10K

EE_EECS
EE_DIN
EE_DOUT
EE_SHCLK

AA4
AB4

AB3
AA5
AB5

AA6

AA8
AB8

AB9

W10

AA10

AA3
AB6

AA9
AB7

AA7

W11

AA15

Y4
W5
W4

Y5

Y3
W6
W3

Y6

Y2

Y1

V2

V1

U4
W9

U3

Y9

U2

U1

T4

Y10

T3

Y8

V3
W8

V4
W1
W2

W7

Y7
Y15

M3

L2

F4

G4

H3

H4

J1

K4

K3

J4
J3

U16A

AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

CBE#0
CBE#1
CBE#2
CBE#3

DEVSEL#
FRAME#
IRDY#
TRDY#
STOP#
PAR
PLOCK#
SERR#
PERR#
PME#

GPIO0/REQA#
GPIO16/GNTA#

PCICLK
PCIRST#
NC12

NC13
NC14
NC15
NC16

EE_CS
EE_DIN
EE_DOUT
EE_SHCLK

VCC1.8

VCC3

E15

E16

E17

E18

F18

G18

H18

J18

P18

R18R5T5U5V5V6V7V8V14

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

VCC3

GND7

GND8

GND9

GND10

GND11

GND12

GND13

GND14

GND15

GND16

GND17

GND18

B10C2C3C4C9D5D6D7D8D9E6E7E8E9J9

GND19

VCC3

VCC3

GND20

GND21

VCC3

VCC3

GND22

GND23

J10

VCC3

GND24

J11

J12

VCC1_8SB

V15

V16H5J5

VCCSUS1_8

VCCSUS1_8

GND25

GND26

GND27

J13

J14K9K10

A22

VCCSUS1_8

VCCSUS1_8

VCCSUS1_8

GND28

GND29

GND30

GND31

K11

K12

K13

B21

B22C1D1D3E1E2E3

GND68

GND69

GND70

GND71

GND32

GND33

GND58

GND59

K14J2K1

AA1

AA2

E4

NC5

NC6

NC8

NC9

CPUSLP#

NC10

NC11

NC17

FERR#

IGNNE#

STPCLK#

A20GATE

HL_STB
HL_STB#
HLCOMP

HUBREF

PIRQA#

PIRQB#

PIRQC#

PIRQD#

APICCLK

APICD0
APICD1

SERIRQ

REQ0#
REQ1#
REQ2#
REQ3#

LAN_CLK

LAN_RSTSYNC

LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2

GND62

GND63

GND64

GND65

INT-82801BA-C0(SL5PN)

AB1

AB2

AB21

REQ4#

GNT0#
GNT1#
GNT2#
GNT3#
GNT4#

GND67
GND66

GPIO1/REQB#/REQ5#

GPIO17/GNTB#/GNT5#

GND60

GND61

AA21

AA22

A20M#

INIT#

INTR

NMI

SMI#

RCIN#

HL10
HL11

IRQ14
IRQ15

SMI#

R264 33

C191

100pC193

R297 62

R304 8.2K

R267 10K
R271 10K

R223 2.7K
R567 X_10K

R303 10K
R310 10K

C187

0.1u

D11
A12

FERR#

R22
A11
C12
C11
B11

SMI#

B12
C10

KB_RST#

B13

A20GATE#

C13

HL0

A4

HL0
HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9

B5
A5
B6
B7
A8
B8
A9
C8
C6
C7
C5
A6
A7
A3

B4
P1

P2
P3
N4

F21
C16
N20
P22
N19
N21

R2
R3
T1
AB10
P4
L3

M2
M1
R4
T2
R1
L4

G3
H2
G2
G1
H1
F3
F2
F1
A21
AB22

HL1
HL2
HL3
HL4
HL5
HL6
HL7
HL8
HL9
HL10

R240 40.2
HUB_IREF

APICCLK
APIC_D0
APIC_D1
SERIRQ

PREQ#0
PREQ#1
PREQ#2
PREQ#3
PREQ#4
PREQ#5

PGNT#0
PGNT#1
PGNT#2
PGNT#3
PGNT#4

ELAN_CLK
ELAN_SYNC
ELAN_RXD0
ELAN_RXD1
ELAN_RXD2
ELAN_TXD0
ELAN_TXD1
ELAN_TXD2

A20M# {4}
SLP# {4}
FERR# {4}
IGNNE# {4}
HINIT# {4,12}
INTR {4}
NMI {4}

STPCLK# {4}
KB_RST# {10}
A20GATE# {10}

HL[0..10] {6}

This resistor less than 0.5"
from ICH use 15 mils trace

HL_STB {6}
HL_STB# {6}

VCC1_8

INTA# {14,15,22}
INTB# {14,15,22}
INTC# {15,22}
INTD# {15,22}

IRQ14 {3}
IRQ15 {3}

SERIRQ {10}
PREQ#0 {15}

PREQ#1 {15}
PREQ#2 {15}
PREQ#3 {15,22}
PREQ#4 {15,23}
PREQ#5 {15}

PGNT#0 {15}
PGNT#1 {15}
PGNT#2 {15}
PGNT#3 {22}
PGNT#4 {23}

ELAN_CLK {21}
ELAN_SYNC {21}
ELAN_RXD0 {21}
ELAN_RXD1 {21}
ELAN_RXD2 {21}
ELAN_TXD0 {21}
ELAN_TXD1 {21}
ELAN_TXD2 {21}

ICH2 STRAPPING RESISTORS

FERR#

SERIRQ

KB_RST#
A20GATE#

GP0
EE_DOUT

APIC_D0
APIC_D1
APICCLK

ICH2 REFERENCE VOLTAGE

HUB_IREF

C182

0.01u

C183

0.1u

HSMI# {4}

VCC1_8

VCCP

VCC3

VCC3

VCC3

R241
150

R245

1500.01u

VCC3

CB210

CB186

0.1u 0.01u

0.1u 0.01u

Place one 0.1U/0.01U pair in each corner and
2 on opposite sides close to ICH2 if it fit

0.1u

CB184

0.1u

CB105

0.1u/S

ICH2 DECOUPLING CAPACITORS

VCC1_8

CB161

CB64CB214

CB203

0.1u

Distribute near the 1.8V
power pin of the ICH2

CB411

0.1u

CB412

0.1u

VCC1_8SB

CB180

CB202

0.1u

0.1u

Distribute near the VCC1_8SB
Power pin of the ICH2

Place Cap. as Close as possible to ICH2
Trace width use 15 mils and 15mils space

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

Brookdale ICH2 PCI

MS-6542

8 27Saturday, November 03, 2001

0AE2

PWR_GD{18}

ICH_VRM_GD{17}

PWRBTN#{18}

10/05/'01 Update

RSM_GD{21}

SMB_DATA_RSM{15,21,22}

SMB_CLK_RSM{15,21,22}

INTRUDER#{18}

AC_RST#{11}
AC_SYNC{11}
AC_BCLK{11}

AC_SDOUT{11}

AC_SDIN0{11}

SIO_PME#{10}

GPI_ESUPPORT#{18}

GPI_INTRUD_CABLE#{18}

LAD0/FWH0{10,12}
LAD1/FWH1{10,12}
LAD2/FWH2{10,12}
LAD3/FWH3{10,12}

LFRAME#/FWH4{10,12}

VCC3_SB

CB193

0.1u

ICH2 ASIC / RTC / AC'97 / GPIO / LPC / USB / IDE SIGNALS

THRM#{10}
SLP_S3#{18,19}
SLP_S5#{19}

CPU_GD{4}

RING#{10}

SUSCLK{10}

ICH_66{3}
ICH_14{3}
ICH_48{3}

SPKR{10,18}

LDRQ#{10}

USBP0+{17}

USBP0-{17}

USBP1+{17}

USBP1-{17}

USBP2+{17}

USBP2-{17}
USBP3-{17}

OC#2{17}
OC#1{17,18}

THRM#

PWR_GD

RING#
RSMRST#

R774

RSM_GD

0

SMB_DATA_RSM
SMB_CLK_RSM
SMB_ALERT
SMB_CLK_RSM
SMB_DATA_RSM
INTRUDER#

RTCRST#
VBIAS
RTCX1
RTCX2

AC_BCLK
AC_SDIN0

AC_SDIN1
SPKR

SIO_PME#
GPI_ESUPPORT#
CLEAR_RTC

GPI_INTRUD_CABLE#

PSWD

R261 X_10K

U16B

AA13

THRM#

W16

SLP_S3#

AB18

SLP_S5

R20

PWROK

A13

CPUPWRGD

B15

VRMPWRGD

W21

PWRBTN#

AA17

RI#

R21

RSMRST#

Y16

RSM_PWROK

Y17

SUSSTAT#

AA18

SUSCLK

AA16

SMBDATA

AB16

SMBCLK

AB17

GPIO11/SMBALERT#

U19

SMLINK0

V20

SMLINK1

T19

INTRUDER#

T20

RTCRST#

T21

VBIAS

U22

RTCX1

T22

RTCX2

D4

CLK66

M19

CLK14

P20

CLK48

V22

AC_RST#

P19

AC_SYNC

R19

AC_BITCLK

P21

AC_SDOUT

Y22

AC_SDIN0

W22

AC_SDIN1

N22

SPKR

W14

GPIO12

AB15

GPIO13

L1

GPIO21

B14

GPIO22

A14

GPIO23

AB14

GPIO27

AA14

GPIO28

Y12

LAD0/FWH0

W12

LAD1/FWH1

AB13

LAD2/FWH2

AB12

LAD3/FWH3

AA12

FS0

Y13

LDRQ0#

W13

LDRQ1#

AB11

LFRAME#/FWH4

W17

USBP0+

Y18

USBP0-

AB19

USBP1+

AA19

USBP1-

W18

USBP2+

Y19

USBP2-

AB20

USBP3+

AA20

USBP3-

W19

OC0#

Y20

OC1#

Y21

OC2#

W20

OC3#

ICH2 DECOUPLING CAPACITOR

CB191

0.1u

VCC5_SB VCC5_SBRTC_VCC

CB199

0.1u

VCCP

CB181

0.1u

Distribute near the VCC3_SB power pin of the ICH

RTC_VCC

GND34

GND35

L9

L10

CB213
1u

GND36

L11

U21

VCCRTC

GND37

GND38

L12

L13

VCC3_SB

T18

U18

VCC3SUS1

GND39

GND40

L14M9M10

F5G5V17

VCC3SUS2

VCC3SUS4

VCC3SUS5

VCC3SUS6

GND41

GND42

GND43

GND44

M11

M12

M13

V18

VCC3SUS7

GND45

GND46

M14N9N10

GND47

VCCP VCC5_SB

D12

D13

V19K2M20

VCPU_IO1

VCPU_IO2

GND48

GND49

GND50

GND51

GND52

N11

N12

N13

N14P9P10

CB201

0.1u

1N5817-S-DO-241AC

VCC5REF1

VCC5REF2

VCC5REF_SUS

GPIO2/PIRQE#

GPIO3/PIRQF#

GPIO4/PIRQG#

GPIO5/PIRQH#

GND53

GND54

GND55

GND56

GND57

P11

P12

P13

P14

PDCS1#
SDCS1#
PDCS3#
SDCS3#

PDA0
PDA1
PDA2
SDA0
SDA1
SDA2

PDDREQ

SDDREQ
PDDACK#
SDDACK#

PDIOR#

SDIOR#
PDIOW#
SDIOW#

PIORDY
SIORDY

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8

PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDD0

SDD1

SDD2

SDD3

SDD4

SDD5

SDD6

SDD7

SDD8

SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

TP0

GPIO6
GPIO7

GPIO8
GPIO18
GPIO19
GPIO20
GPIO24
GPIO25

VCC5_SBVCC3_SB

* Put a GND Plane under X'TAL

R391

R401

X_1K

VCC5VCC3

E21
C15
E19
D15

F20
F19
E22
A16
D16
B16

G22
B18
F22
B17
G19
D17
G21
C17
G20
A17

H19
H22
J19
J22
K21
L20
M21
M22
L22
L21
K22
K20
J21
J20
H21
H20

D18
B19
D19
A20
C20
C21
D22
E20
D21
C22
D20
B20
C19
A19
C18
A18

U20
N3
N2
N1
M4
Y11
AA11
Y14
A15
D14
C14
V21
W15

CB179

0.1u

R302
1K

0.1u
CB212

PDD0
PDD1
PDD2
PDD3
PDD4
PDD5
PDD6
PDD7
PDD8
PDD9
PDD10
PDD11
PDD12
PDD13
PDD14
PDD15

SDD0
SDD1
SDD2
SDD3
SDD4
SDD5
SDD6
SDD7
SDD8
SDD9
SDD10
SDD11
SDD12
SDD13
SDD14
SDD15

BATLOW#

PD_DET
SD_DET
SIO_SMI#

ENET_DIS

PSWD

PD_CS#1 {3}
SD_CS#1 {3}
PD_CS#3 {3}
SD_CS#3 {3}

PD_A0 {3}
PD_A1 {3}
PD_A2 {3}
SD_A0 {3}
SD_A1 {3}
SD_A2 {3}

PD_DREQ {3}
SD_DREQ {3}
PD_DACK# {3}
SD_DACK# {3}
PD_IOR# {3}
SD_IOR# {3}
PD_IOW# {3}
SD_IOW# {3}
PD_IORDY {3}
SD_IORDY {3}

PDD[0..15] {3}

SDD[0..15] {3}

INTE# {15}
INTF# {15}
INTG# {15}
INTH# {15,23}
PD_DET {3}
SD_DET {3}
SIO_SMI# {10}USBP3+{17}

INT-82801BA-C0(SL5PN)

GPO_ESUPP_LED# {18}
ENET_DIS {21}

R571 4.7K

R572

8.2K

VCC3

J_PSWD

1

1

D1x2-BK

2

2

J_PSWD Clear PSWD
Open

Normal
Clear PSWD

*

1 - 2

D3

0

R392
X_3K

PROCHOT BLOCK

VCCP

X_NPN-3904LT1-S-SOT23

PROCHOT#{4}

INTRUDER#

PD_IORDY
SD_IORDY
THRM#

PD_DET
SD_DET

AC_SDIN0
AC_SDIN1

RSMRST#
SPKR
PWR_GD

VCC3_SB

* Please put this block close ICH2

D5
1N4148-S-LL34

R500
1K

R352 300K

R387
X_20M

0.047uC241
R663 22M

R662 2.2M

R298 X_10M R309 10M

R373
X_5.6M

BAT1

THRM#

R256 4.7K

D6
1N5817-S-DO-241AC

R353 1K

Q21

ICH2 STRAPPING RESISTORS

R293 10K

R299 4.7K
R274 4.7K
R263 10K

R315 10K
R317 10K

R374 10K
R375 10K

R273 10K
R292 X_10K
R305 8.2K

RTC_VCC

VCC3

RESUME RESET CIRCUIT BLOCK

R244 100K

2.2u-0805

5 6

U15C

MSI

74LCX14-SOIC14
(VCC3_SB)

C186

Title

Size Document Number Rev

Date: Sheet of

RTC_VCC

C232

0.047u

C211
15p

SMB_CLK_RSM
BATLOW#
SMB_DATA_RSM

SMB_ALERT
SIO_SMI#
SIO_PME#

ENET_DIS
RING#

9 8

U15D

Brookdale ICH2 Other

RTC BLOCK

JBAT1 Clear CMOS
1 - 2
2 - 3

Note : If pop R570 then
non-pop JBAT1, vice versa.

R372

R570

1K

0

RTC_VCC

X3

32K-12.5pf-CSA-309-D

+-30PPM
32pF

JBAT Clear CMOS
Open

Normal

1 - 2

Clear CMOS

CLEAR_RTC

1

1

2

2

R534
1K

1 2
3 4
5 6
7 8

R275 4.7K
R265 4.7K
R266 4.7K

R411 4.7K
R269 8.2K

R664
X_10K

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

Normal
Clear CMOS

1
2
3

*

JBAT
D1x2-BK

RN18

4.7K

RSMRST#

9 27Thursday, November 08, 2001

*

JBAT1
X_D1x3-BK

RTCRST#
VBIAS

RTCX1
RTCX2

C212
15p

VCC3_SB

VCC3_SB

0AE2

LPC SUPER I/O LPC47M192

U13

26

PCIRST#1{3}

SIO_PCLK{3}

SERIRQ{8}

LDRQ#{9}

LFRAME#/FWH4{9,12}

LAD0/FWH0{9,12}
LAD1/FWH1{9,12}
LAD2/FWH2{9,12}
LAD3/FWH3{9,12}

GPI_PCSPKDET#{18}

D_LED1{22}
D_LED2{22}

GPI_LOB0{18}
GPI_LOB1{18}

GPI_FRONT_CABLE#{18}

FNTA_P10{11}

GP20L{12}
D_LED3{22}
D_LED4{22}

PWM{18}
SYS_CTR1{18}
CPU_FAN1{18}
SYS_FAN1{18}

PWR_LED{18}

SUS_LED{18}

SIO_SMI#{9}

SIO_PME#{9}

VID4{4}

SMB_DATA_MAIN{3,13,21,23}

SMB_CLK_MAIN{3,13,21,23}

VID0{4}
VID1{4}
VID2{4}
VID3{4}

VTIN_GND{4}

CPU_TMPA{4}

THRM#{9}

SUSCLK{9}

SIO_14{3}

VCC3

+12V

VCCP

VCC1_8

VCC_AGP

VCC3

VCC5
VCC3

MEM_STR

VCC5
VCC3

R229 8.2K

GPI_PCSPKDET#
GPI_PCSPK_CTR

PWR_LED
SUS_LED
SIO_ADDR

VTIN_GND
CPU_TMPA

THRM#

CB309

0.1u

D1+
D1-

CB307

0.1u

PCI_RESET#

29

PCI_CLK

30

SER_IRQ

25

LDRQ#

24

LFRAME#

27

LPC_PD#

20

LAD0

21

LAD1

22

LAD2

23

LAD3

32

J1B1/GP10

33

J1B2/GP11

34

J2B1/GP12

35

J2B2/GP13

36

JX1/GP14

37

JY1/GP15

38

JX2/GP16

39

JY2/GP17

41

GP20/P17

46

MIDI_IN/GP25

47

MIDI_OUT/GP26

55

FAN_CTL1/GP33

54

FAN_CTL2/GP32

52

FAN_SEN1/GP31

51

FAN_SEN2/GP30

48

LED1/GP60

49

LED2/GP61

45

SYSOPT/GP24

50

IO_SMI#/GP27

17

IO_PME#/GP42

28

DDRC/GP43

103

SDA

104

SCLK

106

VID0

107

VID1

108

VID2

109

VID3

110

+12V_IN/VID4

112

HGND

118

VCCP_IN

119

NC1(+1.8V_IN)

120

NC2(+1.5V_IN)

121

HVCC

113

D0-(XNOR_IN)

114

D0+

115

+5V_IN

116

+3.3V_IN

117

+2.5V_IN

105

A0/RESET#/THERM#(XNOR_OUT)

6

SUSCLK

19

CLK_14M

123

NC3(D1+)

124

NC4(D1-)

44

VREF

53

VCC

65

VCC

93

VCC

101

HGND

125

NC5(HGND)

126

NC6(HGND)

127

HGND

128

HGND

SMSC LPC47M192

DRVDEN0/GP40
DRVDEN1/GP41

DS#1/GP21/P16

MTR#1/GP22/P12

PD0/INDEX#

PD2/WRTPRT#

PD3/RDATA#

PD4/SDKCHG#

SLCT/WGATE#

PE/WDATA#

BUSY/MTR1#

SLCTIN#/STEP#

ERR#/HDSEL#

ALF#/DRVDEN0#

IRRX2/GP34
IRTX2/GP35

RXD2/GP52/IRRX

CTS#2/GP56
DCD#2/GP51
DSR#2/GP54

TXD2/GP53/IRTX

RTS#2/GP55
DTR2#/GP57

KBRST#/GP36

INDEX#

MTR#0

DS#0

DIR#

STEP#

WDATA#
WGATE#
TRACK0#

WP#

RDATA#

HEAD#

DSKCHG#

PD1/TRK0#

PD5

PD6/MTR0#

PD7

ACK#/DS1#

INIT#/DIR#

STB#/DS0#

RI#1

RXD1
CTS#1
DCD#1
DSR#1

TXD1
RTS#1
DTR#1

RI2#/GP50

GA20/GP37

KBDATA

KBCLK

MSDATA

MSCLK

VTR
HVCC
HVCC
HVCC

AGND

GND

GND

GND

GND

1
2
13
3
42
5
43
8
9
10
11
14
15
16
12
4

68

RN17

69

33

70
71
72

RN16

73

33

74
75
77
78
79
80
67
66
81
82
83

61
62

90
84
88
91
86
85
87
89

92
95
99
94
97
96
98
100

64
63
56
57
58
59

18
111
122
102

40
7
31
60
76

7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2

A20GATE#

KB_RST#

FDD_WP#

VCC3

LP_D0
LP_D1
LP_D2
LP_D3
LP_D4
LP_D5
LP_D6
LP_D7

CB303

0.1u

VCC3_SB

DRVDEN0 {16}
DRVDEN1 {16}
INDEX# {16}
MOT_A# {16}
DRV_B# {16}
DRV_A# {16}
MOT_B# {16}
DIR# {16}
STEP# {16}
WT_DT# {16}
WT_EN# {16}
TRACK0# {16}

FDD_WP# {16}
RDATA# {16}
HEAD# {16}
DSKCHG# {16}

LP_D[0..7] {16}
LP_SLCT {16}
LP_PE {16}
LP_BUSY {16}
LP_ACK# {16}
LP_SLIN# {16}
LP_INIT# {16}
LP_ERR# {16}
LP_AFD# {16}
LP_STB# {16}

GP34 {12}
GP35 {12}

RIA# {16}
SINA {16}
CTSA# {16}
DCDA# {16}
DSRA# {16}
SOUTA {16}
RTSA# {16}
DTRA# {16}

RIB# {16}
SINB {16}
CTSB# {16}
DCDB# {16}
DSRB# {16}
SOUTB {16}
RTSB# {16}
DTRB# {16}

A20GATE# {8}
KB_RST# {8}
KBDATA {16}
KBCLK {16}
MSDATA {16}
MSCLK {16}

SIO_ADDR

SIO_ADDR
H: 0x04E
L: 0x02E

(DEFAULT)

LPC I/O STRAPPING RESISTOR

SUS_LED
R206 X_4.7K
R204 4.7K

/N

VCC3

PWR_LED

CPU_TMPA

VTIN_GND

R388 10K
R665 10K

REMOTE TEMPERATURE SENSING ELEMENT

D1+

CB300
2200p

D1-

Q63
NPN-3904LT1-S-SOT23

RING INDECTOR

RING#

RING# {9}

RIA#

1N4148-S-LL34

RIB#

1N4148-S-LL34

D30

D31

R612

4.7K
R611

1K

Q101
NPN-3904LT1-S-SOT23

VCC3_SB

CB301

2200p

H/W Monitor Decoupling Capacitors

LPC I/O DECOUPLING CAPACITORS

VCC3

R775

3.3K

R504 10K U17F DM7407-SOIC14

PC_SPKR{11}

PC_SPKR

NPN-3904LT1-S-SOT23

Q117

GPI_PCSPK_CTR

1312

SPKR

98

U17D DM7407-SOIC14

SPKR {9,18}

VCC3 VCC3 VCC3_SB

CB139

0.1u
CB171

0.1u

+

CT70
470u

CB32

0.1u
CB162

0.1u

CB187

0.1u

+12V VCC3

VCC_AGP

CB380

0.1u

CB385

0.1u

VCCP

CB381

0.1u

CB386

0.1u

CB382

0.1u

MSI

Title

Size Document Number Rev

Date: Sheet of

I/O LPC47M142 & H/W HECETA6

VCC1_8VCC5 MEM_STR

CB383

0.1u

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

10 27Saturday, November 03, 2001

CB384

0.1u

0AE2

8

D D

AC_RST#{9}

AC_SDIN0{9}
AC_SDOUT{9}
AC_SYNC{9}
AC_BCLK{9}

AUX_R

C49 X_1u-0805

AUX_L

C C

C53 X_1u-0805

VCC3

FB9 80_0805

CB3

0.1u

X_IN
X_OUT

AC_RST#

R30 10

AUX_IN1
X_YJ104

4
3
2
1

AUX IN

2.54mm

AMPLIFIER CIRCUIT

LINE_ROUT

C24 X_1u-0805

B B

LINE_LOUT

C17 X_1u-0805 R18 X_47K

R4 X_47K

CB6

0.1u

X_10pC62

PHONE_OUT
AUX_L

AUX_R

CD_L
CD_GND
CD_R

C5 X_1u-0805

C36 X_1u-0805

7

R619 X_10K
R17 X_10K

4847464544424140394338

U2

1

NC

DVDD1

9

DVDD2

4

DVSS1

7

DVSS2

2

XTL_IN

3

XTL_OUT

11

RESET#

8

SDATA_IN

5

SDATA_OUT

10

SYNC

6

BIT_CLK

12

PC_BEEP

PHONE

1314151617181920212223

-12AVR

U1A
X_TI-TL072CDR-SOIC83

+

1

2

-

8 4

R3 X_56K
C11 X_33p

R19 X_56K
C35 X_33p

+12AVR

-12AVR

U1B
X_TI-TL072CDR-SOIC85

+

7

6

-

8 4

+12AVR

+5VR

R15
X_0

NC

AVSS2

TEST6

TEST5

TEST4

TEST1

DACOUTR

AD1887

AUXL

AUXR

VIDEOL

VIDEOR

CDL

CDGND

TEST2

DACOUTL

CDR

L_ROUT

L_LOUT

6

MONO_OUT

37

LOUTR

MONO

AVDD2

LOUTL

VRDA

AFILT2
AFILT1

AVDD1

MIC1

MIC2

LINL

LINR

24

ADI-AD1885
C16 10u-0805

C22 10u-0805

C27 10u-0805

FNTA_P9

VRAD

VREF

AVSS1

+5VR

G

NC
NC

NC

R733
X_0

R576 X_0

36

R577 X_0

35
34

33
32

31
30

29
28
27
25

26

R12 1.5K
C251 1u-0805

FNT_MIC1

1 2

DS

Q109
X_2N7002S

L_ROUT

L_LOUT

CB2

0.1u

VREF_OUT

CB1

0.1u

R6 15K

R9 15K

VREF_OUT

CT61
10u

C32

0.01u

L24

X_300

+5VR

+5VR

LINE_ROUT
LINE_LOUT

+

+

R13 220

5

C10

CT2

0.1u

10u

R7 15K

R10 15K

R2 X_2.2K
R11 2.2K

C23 0.1u

C26
1000p

C414

MIC1

X_1000p

4

AC'97 AUDIO CODE AD1887 CHIPSET

C14
X_0.22u

C3

C7
270p

C4
1u-0805

C15
1000p

C20
1000p

R734 10

+

CT56
220u/16V

R736 10

+

CT57
220u/16V

1u-0805

LINR

LINL

R735

1K

1 2

R528 10

R737

1K

1 2

R529 10

C8

C9

270p

X_0.1u

FB41 300

FB42 300

/N

VREF

MIC1

SPK_R FN_SPK_R

L_ROUT

SPK_L

L_LOUT

SPEAKER_R
MONO_R
MONO_L
SPEAKER_L

LINR

LINL

VREF

MIC1

2
3

5
1

2
3
4
5
1

2
3

5
1

C255 0.1u

L5

1 2

300

L6

1 2

300

FN_SPK_L

3

FB8 X_80-0805

C29

CB4

X_1u-0805

X_0.1u

FB4 X_80-0805

CB16

C18

X_0.1u

X_1u-0805

SPEAKER_R

CN27 1000p

SPEAKER_L

7
5
3
1

LINE_OUT4

LINE_IN

MIC_IN4

VCC5

2

1

AUDIO CODE CRYSTAL CIRCUIT

+12AVR+12V

-12AVR-12V

X_OUT

C54
22p

R27 10M

X1

24M-16pf-HC49S-D

32pF

X_IN

C51
22p

AUDIO CODE REGULATORS

+12V

C37
1u-0805

VR1
L78L05-TO92-100mA

3 1

VIN VOUT

GND

2

C30

1u-0805

+5VR

+CT69

10u

2

1

3

G

O

I

TOP VIEW

CD-IN CONNECTOR

CD_IN1

CD_R

C31 1u-0805

CD_GND

C34 1u-0805

CD_L

C38 1u-0805

R26

4.7K

8
6
4
2

MODEM IN HEADERS

PHONE_OUT

MONO_OUT

C412 1u-0805

C413 1u-0805

R25

4.7K

R21 4.7K
R22 4.7K

R23 4.7K

R24

4.7K

MODEM_IN1
YJ104-BG

YJ104-B

4
3
2
1

CD IN

2.54mm

1
2
3
4

MODEM_IN

2.54mm

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

FB39 80_0805

11 27Wednesday, November 07, 2001

1

0AE2

4.7K

1
2
3
4

R744

MONO_R

MONO_L

U60

SD
BYPASS
+IN

-IN

SSM2211S-SOIC8

R741 20K

12

4

VOUT_B

-V
+V

VOUT_A

C420 0.1u

C421
2700p

C418

0.1u

PC_R

8
7
6
5

PCBEEP

PC_R {18}

+5VR

PC_N {18}

3

DECOUPLING CAPACITOR

FB16 80_0805
C50 0.1u

MSI

Title

AC'97 AUDIO Codec-AD1885 & Amplifer-AD2211

Size Document Number Rev

Date: Sheet of

2

FB5 80_0805
C21 0.1u

R738 20K

FRONT AUDIO CONNECTOR

F_AUDIO

SPK_L
FN_SPK_L
SPK_R

A A

8

FN_SPK_R
FNT_MIC1

VREF
FNTA_P9
FNTA_P10

R743 10K

1
2
3
4
5
6

8
9
10

HT110_520

7

SPK_L
FN_SPK_L
SPK_R
FN_SPK_R
FNT_MIC1

X_1000pC12
X_1000pC13
X_1000pC39
X_1000pC40
X_1000pC41

6

PCBEEP PC_N

R739 20K

R740

20K

PC_SPKR{10}FNTA_P10{10}

5

C415 1u-0805

C416 1u-0805

C417 0.1u

R742 47K

Firware Hub (FWH)

U18

PCIRST#1{3}

GP34{10}

LAD0/FWH0{9,10}
LAD1/FWH1{9,10}
LAD2/FWH2{9,10}

VCC3

F_GPI3
SYSID2
SYSID1
SYSID0
GP34

R314 4.7K

1

VPP

2

RST#

3

FGPI3

4

FGPI2

5

FGPI1

6

FGPI0

7

WP#

TBL#

8

TBL#

9

ID3

10

ID2

11

ID1

12

ID0

13

FWH0

14

FWH1

15

FWH2

16 17

GND FWH3

PLCC32-SMT

FWH DECOUPLING CAPACITORS

PCB OTHER COMPONENT

GND_CP1

61

2

GND_CP4

61

2

Z1

X_AXIS_POINTZ2X_AXIS_POINTZ3X_AXIS_POINTZ4X_AXIS_POINT

Z5

X_AXIS_POINTZ6X_AXIS_POINTZ7X_AXIS_POINTZ8X_AXIS_POINT

GND_CP2

9

3 874

9

3 874

61

5 10

5 10

2

X_BS1

GND_CP3

9

3 874

5 10

9

61

2

3 874

PCB1

D2
u-ATX

P01-654200A-D05

5 10

SIMULATION TRACE

Connect to VCCS

VCC3

Net place on L1
Net place on L4

Connect to GND

J4 X_PIN1*2

J5 X_PIN1*2

VCC

CLK
FGPI4
IC(VIL)

GNDA

VCCA

GND

VCC

INIT#

FWH4

RFU
RFU
RFU
RFU
RFU

VCC3

FWH INIT Signal Voltage Translation Block

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18

VCC3

R336 X_8.2K
R340 X_8.2K

INIT#

CB232

CB231

0.1u

0.1u

DDR TERMINATORS

DDRMAA[0..12]{7,13}

MSCKE[0..3]{7,13}

SCB[0..7]{7,13}

SDQS5{7,13}
MSCS3#{13}
MSCS2#{13}
SDQS4{7,13}

SDQS8{7,13}
SDQS3{7,13}
SDQS2{7,13}
SDQS1{7,13}
SDQS0{7,13}
SDQS7{7,13}

SDQS6{7,13}
MSCS1#{7,13}
MSCS0#{7,13}

MSBS0{13}
MSBS1{13}

MWE#{7,13}

MCAS#{7,13}

MRAS#{7,13}

FWH_PCLK {3}

LFRAME#/FWH4 {9,10}

LAD3/FWH3 {9,10}

CB236

0.1u

DDRMAA12
DDRMAA0
DDRMAA10
DDRMAA1
DDRMAA2
DDRMAA3
DDRMAA4
DDRMAA5
DDRMAA6
DDRMAA8
DDRMAA7
DDRMAA11
DDRMAA9

MSCKE3
MSCKE0
MSCKE2
MSCKE1

SCB7
SCB3
SCB6
SCB2

SCB1
SCB0
SCB5
SCB4

SDQS5
MSCS3#
MSCS2#
SDQS4

SDQS8
SDQS3
SDQS2
SDQS1
SDQS0
SDQS7
SDQS6
MSCS1#
MSCS0#

MSBS0
MSBS1

MWE#
MCAS#
MRAS#

CB237

0.1u

R702 56
R703 56
R704 56
R705 56
R706 56
R707 56
R708 56
R709 56
R710 56
R711 56
R712 56
R713 56
R714 56

RN535 47

1 2
3 4
5 6
7 8

RN536 47

1 2
3 4
5 6
7 8

RN537 47

1 2
3 4
5 6
7 8

RN534 47

1 2
3 4
5 6
7 8

R547 47
R548 47
R549 47
R550 47
R551 47
R552 47
R553 47
R554 47
R555 47

R715 47
R716 47

R556 56
R557 56
R558 56

DDRMD[0..63]{7,13}

VTT_DDR

HINIT#{8}

NPN-3904LT1-S-SOT23

R341 10K

Q30

FWH RESISTORS

F_GPI3

R324 10K

SYSID2

R423 1K

SYSID1

R424 1K

SYSID0

R425 1K

GP34

R312 X_4.7K
R444 4.7K

DDRMD3
DDRMD7
DDRMD2
DDRMD6
DDRMD1
DDRMD5
DDRMD4
DDRMD0
DDRMD13
DDRMD9
DDRMD12
DDRMD8
DDRMD11
DDRMD10
DDRMD15
DDRMD14
DDRMD20
DDRMD21
DDRMD17
DDRMD16
DDRMD19
DDRMD22
DDRMD18
DDRMD23
DDRMD29
DDRMD25
DDRMD28
DDRMD24
DDRMD31
DDRMD27
DDRMD30
DDRMD26
DDRMD35
DDRMD39
DDRMD38
DDRMD34
DDRMD33
DDRMD37
DDRMD36
DDRMD32
DDRMD41
DDRMD45
DDRMD40
DDRMD44
DDRMD47
DDRMD43
DDRMD46
DDRMD42
DDRMD53
DDRMD52
DDRMD49
DDRMD48
DDRMD51
DDRMD55
DDRMD50
DDRMD54
DDRMD57
DDRMD56
DDRMD61
DDRMD60
DDRMD59
DDRMD63
DDRMD58
DDRMD62

VCC3VCC3

R343

8.2K

RN518 471 2

RN519 471 2

RN520 47

RN521 47

RN522 471 2

RN523 471 2

RN524 471 2

RN525 47

RN526 47

RN527 471 2

RN528 471 2

RN529 471 2

RN530 47

RN531 47

RN532 471 2

RN533 471 2

R342
1K

INIT#

Q32

NPN-3904LT1-S-SOT23

VCC3

/N

VCC3

3 4
5 6
7 8

3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

3 4
5 6
7 8

3 4
5 6
7 8

3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

3 4
5 6
7 8

3 4
5 6
7 8

3 4
5 6
7 8
1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

3 4
5 6
7 8

3 4
5 6
7 8

VTT_DDR

VTT_DDR

VTT_DDR

CLOSE TO VTT ISLAND

BIOS Configuration Mode Block

JROM

1
2
3

D1x3-BK

GP35
GP20L

GP20L
GP35

R426 4.7K
R422 4.7K

GP20L {10}
GP35 {10}

VCC3

BIOS Function
1-2 : Normal
2-3 : Configuration Mode
REMOVED : BIOS Recovery

( From FDD )

DDR Decouping Caps

VTT_DDRVTT_DDR

CB335

0.1u
CB332

0.1u
CB331

0.1u
CB334

0.1u
CB333

0.1u
CB336

0.1u
CB315

0.1u
CB311

0.1u
CB314

0.1u
CB312

0.1u
CB319

0.1u
CB318

0.1u
CB320

0.1u
CB316

0.1u
CB317

0.1u
CB327

0.1u
CB323

0.1u

+

CT63
1000u

+

CT64
1000u

CLOSE TO SOCKET

+

CT62
1000u

+

CT65
1000u

MSI

Title

Size Document Number Rev

Date: Sheet of

FWH & MANUAL PART & Terminators

CB421

0.1u
CB422

0.1u
CB423

0.1u
CB424

0.1u
CB425

0.1u
CB426

0.1u
CB427

0.1u
CB428

0.1u
CB429

0.1u
CB430

0.1u
CB431

0.1u
CB432

0.1u
CB433

0.1u
CB434

0.1u
CB435

0.1u

VTT_DDR

MICRO-STAR

MS-6542

MEM_STRVTT_DDRMEM_STR

CB310

0.1u

C379

4.7u-0805

C380

4.7u-0805

C381

4.7u-0805

CB159

4.7u-0805

PLACE AT VTT ISLAND

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

12 27Saturday, November 03, 2001

CB357

0.1u
CB346

0.1u
CB359

0.1u
CB345

0.1u
CB356

0.1u
CB341

0.1u
CB352

0.1u
CB343

0.1u
CB342

0.1u
CB355

0.1u
CB339

0.1u
CB358

0.1u
CB349

0.1u
CB350

0.1u
CB338

0.1u
CB344

0.1u
CB347

0.1u
CB353

0.1u
CB360

0.1u
CB337

0.1u
CB340

0.1u

Top Vtt

Center Vtt

Bottom Vtt

0AE2

8

7

MEM_STR

6

5

4

3

MEM_STR

2

1

SYSTEM MEMORY

738467085

108

120

148

738467085

108

120

148

168223054627796

VDD0

VDD1

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

D D

DDRMD[0..63]{7,12}

C C

B B

MWE#{7,12}

49.9RST

DDR_VREF

A A

49.9RST

MEM_STR

R666

R667

DDRMD0
DDRMD1
DDRMD2
DDRMD3
DDRMD4
DDRMD5
DDRMD6
DDRMD7
DDRMD8
DDRMD9
DDRMD10
DDRMD11
DDRMD12
DDRMD13
DDRMD14
DDRMD15
DDRMD16
DDRMD17
DDRMD18
DDRMD19
DDRMD20
DDRMD21
DDRMD22
DDRMD23
DDRMD24
DDRMD25
DDRMD26
DDRMD27
DDRMD28
DDRMD29
DDRMD30
DDRMD31
DDRMD32
DDRMD33
DDRMD34
DDRMD35
DDRMD36
DDRMD37
DDRMD38
DDRMD39
DDRMD40
DDRMD41
DDRMD42
DDRMD43
DDRMD44
DDRMD45
DDRMD46
DDRMD47
DDRMD48
DDRMD49
DDRMD50
DDRMD51
DDRMD52
DDRMD53
DDRMD54
DDRMD55
DDRMD56
DDRMD57
DDRMD58
DDRMD59
DDRMD60
DDRMD61
DDRMD62
DDRMD63

MWE#

C301
104P

C300
104P

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

SLAVE ADDRESS = 1010000B

NC3

102

NC4

VDD8

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

3111826344250586674818993

Place 104p Cap. near the DIMM

8

7

VDDQ0

VDDQ1

VSS6

VSS7

VDDQ2

VDDQ3

DDR DIMM SOCKET

VSS8

VSS9

104

VDDQ4

VDDQ5

VSS10

VSS11

112

128

VDDQ6

VDDQ7

VSS12

VSS13

100

116

136

143

VDDQ8

VDDQ9

VSS14

VSS15

124

132

6

156

164

VDDQ10

VDDQ11

VSS16

VSS17

139

145

172

1801582

VDDQ12

VDDQ13

VSS18

VSS19

152

160

VDDQ14

VDDQ15

A10_AP

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC(RESET#)

VSS20

VSS21

176

184

VDDID

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

BA0
BA1
BA2
SCL

SDA

SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VDDSPD

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A11
A12
A13

157
158
71
163

SDQS0

5

SDQS1

14

SDQS2

25

SDQS3

36

SDQS4

56

SDQS5

67

SDQS6

78

SDQS7

86

SDQS8

47
167

DDRMAA0

48

DDRMAA1

43

DDRMAA2

41

DDRMAA3

130

DDRMAA4

37

DDRMAA5

32

DDRMAA6

125

DDRMAA7

29

DDRMAA8

122

DDRMAA9

27

DDRMAA10

141

DDRMAA11

118

DDRMAA12

115
103

MSBS0

59

MSBS1

52
113

SMB_CLK_MAIN

92

SMB_DATA_MAIN

91
181
182
183

SCB0

44

SCB1

45

SCB2

49

SCB3

51

SCB4

134

SCB5

135

SCB6

142

SCB7

144

DCLK1

16

DCLK1#

17

DCLK0

137

DCLK0#

138

DCLK2

76

DCLK2#

75
173

10

MSCKE0

21

MSCKE1

111

MCAS#

65

MRAS#

154

MDQM_B0

97

MDQM_B1

107

MDQM_B2

119

MDQM_B3

129

MDQM_B4

149

MDQM_B5

159

MDQM_B6

169

MDQM_B7

177

MDQM_B8

140

DDR0
N13-1840021

7Pcs doupling caps
place between DDR0
and DDR1 sockets

MSCS0# {7,12}
MSCS1# {7,12}

MSBS0 {7,12}
MSBS1 {7,12}

SMB_CLK_MAIN {3,10,21,23}
SMB_DATA_MAIN {3,10,21,23}

SCB[0..7] {7,12}

DCLK1 {7}
DCLK1# {7}
DCLK0 {7}
DCLK0# {7}
DCLK2 {7}
DCLK2# {7}

MSCKE0 {7,12}
MSCKE1 {7,12}
MCAS# {7,12}
MRAS# {7,12}

5

SDQS[0..8] {7,12}

DDRMAA[0..12] {7,12}

MEM_STR

DDR_VREF

CB371

0.1u
CB367

0.1u
CB364

0.1u
CB369

Place 104p Cap. near the DIMM

0.1u
CB370

0.1u
CB366

0.1u
CB368

0.1u

4

DDRMD0
DDRMD1
DDRMD2
DDRMD3
DDRMD4
DDRMD5
DDRMD6
DDRMD7
DDRMD8
DDRMD9
DDRMD10
DDRMD11
DDRMD12
DDRMD13
DDRMD14
DDRMD15
DDRMD16
DDRMD17
DDRMD18
DDRMD19
DDRMD20
DDRMD21
DDRMD22
DDRMD23
DDRMD24
DDRMD25
DDRMD26
DDRMD27
DDRMD28
DDRMD29
DDRMD30
DDRMD31
DDRMD32
DDRMD33
DDRMD34
DDRMD35
DDRMD36
DDRMD37
DDRMD38
DDRMD39
DDRMD40
DDRMD41
DDRMD42
DDRMD43
DDRMD44
DDRMD45
DDRMD46
DDRMD47
DDRMD48
DDRMD49
DDRMD50
DDRMD51
DDRMD52
DDRMD53
DDRMD54
DDRMD55
DDRMD56
DDRMD57
DDRMD58
DDRMD59
DDRMD60
DDRMD61
DDRMD62
DDRMD63

MWE#

C371
104P

VDD0

VDD1

2

DQ0

4

DQ1

6

DQ2

8

DQ3

94

DQ4

95

DQ5

98

DQ6

99

DQ7

12

DQ8

13

DQ9

19

DQ10

20

DQ11

105

DQ12

106

DQ13

109

DQ14

110

DQ15

23

DQ16

24

DQ17

28

DQ18

31

DQ19

114

DQ20

117

DQ21

121

DQ22

123

DQ23

33

DQ24

35

DQ25

39

DQ26

40

DQ27

126

DQ28

127

DQ29

131

DQ30

133

DQ31

53

DQ32

55

DQ33

57

DQ34

60

DQ35

146

DQ36

147

DQ37

150

DQ38

151

DQ39

61

DQ40

64

DQ41

68

DQ42

69

DQ43

153

DQ44

155

DQ45

161

DQ46

162

DQ47

72

DQ48

73

DQ49

79

DQ50

80

DQ51

165

DQ52

166

DQ53

170

DQ54

171

DQ55

83

DQ56

84

DQ57

87

DQ58

88

DQ59

174

DQ60

175

DQ61

178

DQ62

179

DQ63

90

WP(NC)

63

WE#

1

VREF

9

NC2

101

NC3

102

NC4

168223054627796

VDD2

VDD3

VDD4

VDD5

VDD6

VDD7

VDD8

SLAVE ADDRESS = 1010010B

VSS0

VSS1

VSS2

VSS3

VSS4

VSS5

3111826344250586674818993

3

VDDQ0

VDDQ1

VSS6

VSS7

VDDQ2

VSS8

104

112

128

136

143

156

164

172

1801582

184

VDDQ3

VDDQ4

VDDQ5

VDDQ6

VDDQ7

VDDQ8

VDDQ9

VDDQ10

DDR DIMM SOCKET

VSS9

VSS10

VSS11

VSS12

VSS13

VSS14

VSS15

VSS16

100

116

124

132

139

MSI

Title

Size Document Number Rev

Date: Sheet of

VDDQ11

VDDQ12

VSS17

VSS18

145

152

2

VDDQ13

VDDQ14

VDDQ15

NC(RESET#)

VSS19

VSS20

VSS21

160

176

VDDID

CS0#
CS1#
CS2#
CS3#

DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8

FETEN

A10_AP

BA0
BA1
BA2
SCL

SDA

SA0
SA1
SA2

CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7

CK0(DU)
CK0#(DU)
CK1(CK0)

CK1#(CK0#)

CK2(DU)
CK2#(DU)

NC5

CKE0
CKE1
CAS#
RAS#

DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8

VDDSPD

157
158
71
163

5
14
25
36
56
67
78
86
47

167
48

A0

43

A1

41

A2

130

A3

37

A4

32

A5

125

A6

29

A7

122

A8

27

A9

141
118

A11

115

A12

103

A13

59
52
113
92
91
181
182
183

44
45
49
51
134
135
142
144

16
17
137
138
76
75

173
10

21
111
65
154

97
107
119
129
149
159
169
177
140

DDR1
N13-1840021

MICRO-STAR

MS-6542

SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8

DDRMAA0
DDRMAA1
DDRMAA2
DDRMAA3
DDRMAA4
DDRMAA5
DDRMAA6
DDRMAA7
DDRMAA8
DDRMAA9
DDRMAA10
DDRMAA11
DDRMAA12

MSBS0
MSBS1

SMB_CLK_MAIN
SMB_DATA_MAIN

MEM_STR

SCB0
SCB1
SCB2
SCB3
SCB4
SCB5
SCB6
SCB7

DCLK4
DCLK4#
DCLK3
DCLK3#
DCLK5
DCLK5#

MSCKE2
MSCKE3
MCAS#
MRAS#

MDQM_B0
MDQM_B1
MDQM_B2
MDQM_B3
MDQM_B4
MDQM_B5
MDQM_B6
MDQM_B7
MDQM_B8

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6541

13 27Saturday, November 03, 2001

MSCS2# {7,12}
MSCS3# {7,12}

DCLK4 {7}
DCLK4# {7}
DCLK3 {7}
DCLK3# {7}
DCLK5 {7}
DCLK5# {7}

MSCKE2 {7,12}

MSCKE3 {7,12}

1

0AE2

8

7

6

5

4

3

2

1

AGP SIGNAL REFERENCE CIRCUIT

AGP 1.5V 2X/4X SLOT(AGP VER:2.0 COMPLY)

C161
X_470p

1u-0805

VCC_AGP

AGPREF: 10uA

CB158

0.1u

0.1uC422

C423 1u-0805

0.1uC424

C425 1u-0805

AGP TERMINATION RESISTORS

VCC_AGP VCC_AGP

GSTOP#
GPAR
GGNT#

GAD_STB0
GAD_STB1
SB_STB

GPERR#
GSERR#

DDR Straping resistors

ST2
ST1

ST0

ST0 pull down to enable DDR.

CB408 0.1u

VCC3_SBVCC_AGP VCC3+12V

CB389

0.1u
CB394

0.1u

VCC3

CB388

0.1u
CB393
100p

R148 X_6.8K
R155 6.8K
R98 6.8K

R162 X_6.8K
R140 X_6.8K
R125 X_6.8K

R154 6.8K
R158 6.8K

R378 X_2K
R377 X_2K
R393 X_6.8K
R376 2K

VCC5

CB390

0.1u
CB395
100p

VREF_GC

AGPREFAGPREF

BSEL0 {4}

+

CT72
1000u

CB396

0.1u
CB399

0.1u
CB402

0.1u
CB405

0.1u
CB409
100p

D D

INTB#{8}

AGPCLK{3}

GREQ#{7}

ST0{7}
ST2{7}

RBF#{7}

SBA0{7}
SBA2{7}

SB_STB{7}

SBA4{7}
SBA6{7}

C C

B B

GAD31{7}
GAD29{7}

GAD27{7}
GAD25{7}

GAD_STB1{7}

GAD23{7}
GAD21{7}

GAD19{7}
GAD17{7}

GC_BE#2{7}

GIRDY#{7}

GDEVSEL#{7}

GC_BE#1{7}

GAD14{7}
GAD12{7}

GAD10{7}

GAD8{7}

GAD_STB0{7}

GAD7{7}
GAD5{7}

GAD3{7}
GAD1{7}

AGPREF{7}

VCC5 = 60mils trace / 15 mils space

AGP1

B1

-OVRCNT

VCC5

INTB# INTA#
GREQ#

VCC3

RBF#

SB_STB

VCC3_SB

GAD_STB1

VCC_AGP

GIRDY#

GDEVSEL#
GPERR#
GSERR#

GAD_STB0

AGPREF

B2

5V

B3

5V

B4

USB+

B5

GND

B6

-INTB

B7

CLK

B8

-REQ

B9

3.3V

B10

ST0

B11

ST2

B12

-RBF

B13

GND

B14

RESERVED

B15

SBA0

B16

3.3V

B17

SBA2

B18

SB_STB

B19

GND

B20

SBA4

B21

SBA6

B22

RSVD/KEY

B23

GND/KEY

B24

AUX3V/KEY

B25

3.3V/KEY

B26

AD31

B27

AD29

B28

3.3V

B29

AD27

B30

AD25

B31

GND

B32

AD_STB1

B33

AD23

B34

VDDQ

B35

AD21

B36

AD19

B37

GND

B38

AD17

B39

C/-BE2

B40

VDDQ

B41

-IRDY

B42

AUX3V/KEY

B43

GND/KEY

B44

RSVD/KEY

B45

3.3V/KEY

B46

-DEVSEL

B47

VDDQ

B48

-PERR

B49

GND

B50

-SERR

B51

C/-BE1

B52

VDDQ

B53

AD14

B54

AD12

B55

GND

B56

AD10

B57

AD8

B58

VDDQ

B59

AD_STB0

B60

AD7

B61

GND

B62

AD5

B63

AD3

B64

VDDQ

B65

AD1

B66

VREF_CG

AGP-D124-BN_1.5V

-TYPEDET

RESERVED

USB-

GND

-INTA

-RST

-GNT

3.3V
ST1

RESERVED

-PIPE
GND

-WBF

SBA1

3.3V

SBA3

-SB_STB
GND

SBA5
SBA7

RSVD/KEY

GND/KEY

RSVD/KEY

3.3V/KEY
AD30
AD28

3.3V
AD26
AD24

GND

-AD_STB1
C/-BE3

VDDQ

AD22
AD20

GND
AD18
AD16

VDDQ

-FRAME

RSVD/KEY

GND/KEY

RSVD/KEY

3.3V/KEY

-TRDY

-STOP

-PME
GND

PAR

AD15

VDDQ

AD13
AD11

GND

AD9

C/-BE0

VDDQ

-AD_STB0
AD6

GND

AD4
AD2

VDDQ

AD0

VREF_GC

A1

12V

+12V

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66

GGNT#

VCC3

PIPE#
WBF#

SB_STB#

GAD_STB#1

VCC_AGP

GFRAME#

GTRDY#
GSTOP#

GPAR

GAD_STB#0

VREF_GC

INTA#
INTB#

INTA# {8}
PCIRST#2 {3}

GGNT# {7}
ST1 {7}
PIPE# {7}
WBF# {7}

SBA1 {7}
SBA3 {7}

SB_STB# {7}
SBA5 {7}

SBA7 {7}

GAD30 {7}
GAD28 {7}

GAD26 {7}
GAD24 {7}

GAD_STB#1 {7}
GC_BE#3 {7}

GAD22 {7}
GAD20 {7}

GAD18 {7}
GAD16 {7}

GFRAME# {7}

GTRDY# {7}
GSTOP#{7}
PME# {8,15,22}

GPAR {7}
GAD15 {7}

GAD13 {7}
GAD11 {7}

GAD9 {7}
GC_BE#0 {7}

GAD_STB#0 {7}
GAD6 {7}

GAD4 {7}
GAD2 {7}

GAD0 {7}

R188
1K

R1851KC163

NEAR AGP SLOT

GTRDY#

RN33 X_6.8K1 2
GDEVSEL#
GFRAME#
GIRDY#

WBF#
RBF#

PIPE#
GREQ#

GAD_STB#1
GAD_STB#0
SB_STB#

3 4
5 6
7 8

RN34 X_6.8K1 2

3 4
5 6
7 8

R789 X_6.8K

R142 X_6.8K
R164 X_6.8K
R123 X_6.8K

LESS 10MILS STUB TRACE LENGTH MUST BE FOLLOWING.

Place these resistors between PCI and AGP slot

AGP SLOT DECOUPLING CAPACITORS

VCC_AGP

+

CT71
1000u

CB391

0.1u
CB397

0.1u
CB400

0.1u
CB403

0.1u
CB406

0.1u

CB387
100p
CB392
100p
CB398

0.1u
CB401

0.1u
CB404

0.1u

AGP Slot Imax
VCCq 8.0A

A A

8

VCC3 6.0A
VCC12 1.0A
VCC5 2.0A
VCC3_SB ?A

7

MSI

Title

Size Document Number Rev

6

5

4

3

Date: Sheet of

2

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

AGP SLOT

MS-6542

14 27Saturday, November 03, 2001

0AE2

1

8

7

6

5

4

3

2

1

PCI SLOT 1 (PCI VER: 2.2 COMPLY) PCI SLOT 2 (PCI VER: 2.2 COMPLY)

PREQ#1

VCC3

-12V
PCI2

B1

-12V

B2

TCK

B3

GND

B4

TDO

B5

+5V

B6

+5V

B7

INTB#

B8

INTD#

B9

PRSNT#1

B10

RESERVED

B11

PRSNT#2

B12

GND

B13

GND

B14

RESERVED

B15

GND

B16

CLK

B17

GND

B18

REQ#

B19

+5V(I/O)

B20

AD31

B21

AD29

B22

GND

B23

AD27

B24

AD25

B25

+3.3V

B26

C/BE#3

B27

AD23

B28

GND

B29

AD21

B30

AD19

B31

+3.3V

B32

AD17

B33

C/BE#2

B34

GND

B35

IRDY#

B36

+3.3V

B37

DEVSEL#

B38

GND

B39

LOCK#

B40

PERR#

B41

+3.3V

B42

SERR#

B43

+3.3V

B44

C/BE#1

B45

AD14

B46

GND

B47

AD12

B48

AD10

B49

GND

B52

AD8

B53

AD7

B54

+3.3V

B55

AD5

B56

AD3

B57

GND

B58

AD1

B59

+5V(I/O)

B60

ACK64#

B61

+5V

B62

+5V

PCI-D120-WH-SN

TRST#

+12V

TMS

+5V
INTA#
INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT#

GND

RESERVED

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

+3.3
AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

AD9

C/BE#0

+3.3V

AD6
AD4

GND

AD2
AD0

+5V(I/O)

REQ64#

+5V
+5V

+12V

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

PTRST#
PTMS

PTDI
INTB#

INTD#

VCC5

VCC3

VCC3_SB

PCIRST#2

PGNT#1 {8}

PME#
AD30

AD28
AD26

AD24

AD17 AD18

R451 33

AD22
AD20

AD18
AD16

FRAME#
TRDY#
STOP#

SMB_CLK_RSM SMB_CLK_RSM

PAR
AD15

AD13
AD11

AD9

C_BE#0
AD6

AD4
AD2

AD0
REQ#64

-12V
PCI1

B1

PTCK

D D

C C

B B

VCC5

INTB#
INTD#

VCC3

PCICLK0{3}

PREQ#0

AD31{8,22,23}
AD29{8,22,23}

AD27{8,22,23}
AD25{8,22,23}

C_BE#3{8,22,23}

AD23{8,22,23}
AD21{8,22,23}

AD19{8,22,23}
AD17{8,22,23}

C_BE#2{8,22,23}

IRDY#{8,22,23}

DEVSEL#{8,22,23}

PLOCK#{8,22}

PERR#{8,22,23}
SERR#{8,22,23}

C_BE#1{8,22,23}

AD14{8,22,23}
AD12{8,22,23}

AD10{8,22,23}

AD8{8,22,23}
AD7{8,22,23}

AD5{8,22,23}
AD3{8,22,23}

AD1{8,22,23}

ACK#64

-12V

B2

TCK

B3

GND

B4

TDO

B5

+5V

B6

+5V

B7

INTB#

B8

INTD#

B9

PRSNT#1

B10

RESERVED

B11

PRSNT#2

B12

GND

B13

GND

B14

RESERVED

B15

GND

B16

CLK

B17

GND

B18

REQ#

B19

+5V(I/O)

B20

AD31

B21

AD29

B22

GND

B23

AD27

B24

AD25

B25

+3.3V

B26

C/BE#3

B27

AD23

B28

GND

B29

AD21

B30

AD19

B31

+3.3V

B32

AD17

B33

C/BE#2

B34

GND

B35

IRDY#

B36

+3.3V

B37

DEVSEL#

B38

GND

B39

LOCK#

B40

PERR#

B41

+3.3V

B42

SERR#

B43

+3.3V

B44

C/BE#1

B45

AD14

B46

GND

B47

AD12

B48

AD10

B49

GND

B52

AD8

B53

AD7

B54

+3.3V

B55

AD5

B56

AD3

B57

GND

B58

AD1

B59

+5V(I/O)

B60

ACK64#

B61

+5V

B62

+5V

PCI-D120-WH-SN

TRST#

RESERVED

+5V(I/O)

RESERVED

RESERVED

+5V(I/O)

RESERVED

FRAME#

STOP#

SDONE

C/BE#0

+5V(I/O)

REQ64#

+12V

TMS

+5V
INTA#
INTC#

+5V

GND
GND

RST#

GNT#

GND

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

+3.3
AD22
AD20

GND
AD18
AD16

+3.3V

GND

TRDY#

GND

+3.3V

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

AD9

+3.3V

AD6
AD4

GND

AD2
AD0

+5V
+5V

+12V

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

VCC3

R453 33

PTRST#
PTMS

PTDI
INTA#

INTC#

VCC3_SB

PCIRST#2 {3}
PGNT#0 {8}
PME# {8,14,22,23}

AD30 {8,22,23}
AD28 {8,22,23}

AD26 {8,22,23}
AD24 {8,22,23}

AD16

AD22 {8,22,23}
AD20 {8,22,23}

AD18 {8,22,23}
AD16 {8,22,23}

FRAME# {8,22,23}
TRDY# {8,22,23}
STOP# {8,22,23}

SMB_CLK_RSM {9,21,22}
SMB_DATA_RSM {9,21,22}

PAR {8,22,23}
AD15 {8,22,23}

AD13 {8,22,23}
AD11 {8,22,23}

AD9 {8,22,23}

C_BE#0 {8,22,23}
AD6 {8,22,23}

AD4 {8,22,23}
AD2 {8,22,23}

AD0 {8,22,23}

REQ#64

PCICLK1{3}

PTCK

INTC#
INTA#

AD31
AD29

AD27
AD25

C_BE#3
AD23

AD21
AD19

AD17
C_BE#2

IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD8
AD7

AD5
AD3

AD1
ACK#64

PCI SLOT 3 (PCI VER: 2.2 COMPLY)

-12V
PCI3

B1

-12V

B2

TCK

B3

GND

B4

TDO

B5

+5V

B6

+5V

B7

INTB#

B8

INTD#

B9

PRSNT#1

B10

RESERVED

B11

PRSNT#2

B12

GND

B13

GND

B14

RESERVED

B15

GND

B16

CLK

B17

GND

B18

REQ#

B19

+5V(I/O)

B20

AD31

B21

AD29

B22

GND

B23

AD27

B24

AD25

B25

+3.3V

B26

C/BE#3

B27

AD23

B28

GND

B29

AD21

B30

AD19

B31

+3.3V

B32

AD17

B33

C/BE#2

B34

GND

B35

IRDY#

B36

+3.3V

B37

DEVSEL#

B38

GND

B39

LOCK#

B40

PERR#

B41

+3.3V

B42

SERR#

B43

+3.3V

B44

C/BE#1

B45

AD14

B46

GND

B47

AD12

B48

AD10

B49

GND

B52

AD8

B53

AD7

B54

+3.3V

B55

AD5

B56

AD3

B57

GND

B58

AD1

B59

+5V(I/O)

B60

ACK64#

B61

+5V

B62

+5V

PCI-D120-WH-SN

PCICLK2{3}

PTCK

VCC5VCC5

INTD#
INTB#

PREQ#2

AD31
AD29

AD27
AD25

C_BE#3
AD23

AD21
AD19

AD17
C_BE#2

IRDY#
DEVSEL#
PLOCK#

PERR#
SERR#
C_BE#1

AD14
AD12

AD10

AD8
AD7

AD5
AD3

AD1
ACK#64

VCC3

TRST#

+12V

TMS

+5V
INTA#
INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT#

GND

RESERVED

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

+3.3
AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

AD9

C/BE#0

+3.3V

AD6
AD4

GND

AD2
AD0

+5V(I/O)

REQ64#

+5V
+5V

+12V

VCC3

PTRST#
PTMS

PTDI
INTC#

INTA#

VCC5VCC5

PCIRST#2

PME#
AD30

AD28
AD26

AD24

R452 33

AD22
AD20

AD18
AD16

FRAME#
TRDY#
STOP#

SMB_DATA_RSMSMB_DATA_RSM

PAR
AD15

AD13
AD11

AD9

C_BE#0
AD6

AD4
AD2

AD0
REQ#64

VCC3_SB

PGNT#2 {8}

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

IDSEL = AD16 IDSEL = AD17

IDSEL = AD18
MASTER = PREQ2MASTER = PREQ1MASTER = PREQ0

INT : A,B,C,D INT : B,C,D,A INT : C,D,A,B

PCI PULL-UP / DOWN RESISTORS

RN9

8.2K

INTC#PREQ#3

1 2

INTA#

3 4

INTD#

5 6

INTE#

7 8

RN15

8.2K

INTG#

1 2

INTF#

3 4

INTB#

5 6

INTH#

7 8 CB109

VCC3

4

VCC5

+

DEVSEL#

1 2

TRDY#

3 4

IRDY#

5 6

FRAME#

7 8

SERR#

1 2

PERR#

3 4

PLOCK#

5 6

STOP#

A A

7 8

8

VCC5 VCC5 VCC3

RN13

2.7K

RN14

2.7K

PREQ#3{8,22}
PREQ#2{8}
PREQ#1{8}
PREQ#0{8}
PREQ#4{8}
PREQ#5{8}

REQ#64{22}
ACK#64{22}

PTMS{22}
PTDI{22}

PTCK{22}
PTRST#{22}

7

PREQ#2
PREQ#1
PREQ#0
PREQ#4
PREQ#5

REQ#64
ACK#64

PTMS
PTDI

PTCK
PTRST#

RN10 2.7K

1 2
3 4
5 6

7 8
R224 2.7K
R208 2.7K

R156 4.7K
R153 4.7K

R46 4.7K
R47 4.7K

R43 4.7K
R45 4.7K

6

VCC5

INTC#{8}
INTA#{8}
INTD#{8}
INTE#{9}

INTG#{9}
INTF#{9}
INTB#{8}

INTH#{9}

5

PCI SLOT DECOUPLING CAPACITORS

-12V

MSI

Title

Size Document Number Rev

Date: Sheet of

CT10
470u
CB132

0.1u
CB134

0.1u
CB131

0.1u
CB133

0.1u
CB39

0.1u
CB38
100p
CB26
100p
CB25
100p

VCC3

3

+

CT25
1000u
CB50

0.1u
CB86

0.1u
CB96

0.1u

0.1u
CB57

0.1u
CB87
100p
CB110
100p
CB123
100p

CB20

0.1u
CB15

0.1u
C285
X_0.1u

2

+12V

CB17

0.1u
CB21

0.1u

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

PCI SLOT 1&2&3

MS-6542

VCC3_SB

15 27Saturday, November 03, 2001

CB35

0.1u
CB34

0.1u

0AE2

1

8

7

6

5

4

3

2

1

VCC5

C77 X_0.1u

DCDA
RXDA
RIA
CTSA

D41

1N4148-S-LL34

CB304

0.1u

DSRA

D D

DTRA#{10}
RTSA#{10}

SOUTA{10}

-12V

20

2
3
4
7
9

16
15
13
11

CB305

VCC5

-12VR

0.1u

U4

VCC
RIN1
RIN2
RIN3
RIN4
RIN5

DIN1
DIN2
DIN3
GND

X_75232-1

ROUT1
ROUT2
ROUT3
ROUT4
ROUT5

DOUT1
DOUT2
DOUT3

C282 X_0.1u

+12VR

C69 X_0.1u

1

V+

19
18
17
14
12

5
6
8
10

V-

DTRA
RTSA
TXDA

C68 X_0.1u

DCDA# {10}
SINA {10}
RIA# {10}
CTSA# {10}
DSRA# {10}

-12VR

D40

+12V

1N4148-S-LL34

CB308

0.1u

+12VR

CB306

0.1u

PARALLAL PORT

C C

LP_D2

1

SERIAL PORT 1

D1 1N4148-S-LL34

VCC5

LP_SLIN#

LP_SLIN#{10}

LP_D3{10}

LP_INIT#{10}

LP_D[0..7]{10}

LP_SLCT{10}

LP_PE{10}

LP_BUSY{10}

LP_ACK#{10}

LP_ERR#{10}

LP_D1{10}

LP_AFD#{10}

LP_D0{10}

B B

LP_STB#{10}

LP_D3
LP_INIT#
LP_D2
LP_D4
LP_D5
LP_D6
LP_D7

LP_SLCT
LP_PE
LP_BUSY
LP_ACK#
LP_ERR#
LP_D1
LP_AFD#
LP_D0

LP_STB#

1 2
3 4
5 6
7 8
7 8
5 6
3 4
1 2

1 2
3 4
5 6
7 8
1 2
3 4
5 6
7 8

R31 2.2K

RN4

2.2K

RN5

2.2K

RN7

2.2K

RN3

2.2K

LP_INIT#
LP_D3
LP_SLIN#

LP_D4
LP_D5
LP_D6
LP_D7

LP_ACK#
LP_BUSY
LP_PE
LP_SLCT

LP_D0
LP_AFD#
LP_D1
LP_ERR#

LP_STB#

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

33pC48

CN4
220p

CN5
220p

CN6
220p

CN3
220p

+12V

DCDA
RXDA
RIA
DTRA

RTSA
CTSA
TXDA
DSRA

DCDA
RXDA RTSA
TXDA
DTRA

1

2

3

4

5

6

7

8

1

2

3

4

5

6

7

8

LPTB

4749

26
27
28
29
30

DSRA

31
32

CTSA

33

RIA

34

X_LPT-D25-BK-BI
C267 X_0.1u
FB14 X_80_0805

CP3 X_COPPER

LPTA

LP_STB#
LP_D0
LP_D1
LP_D2
LP_D3
LP_D4
LP_D5
LP_D6
LP_D7
LP_ACK#
LP_BUSY
LP_PE
LP_SLCT

51

1

14

2

15

3

16

4

17

5

18

6

19

7

20

8

21

9

22

10

23

11

24

12

25

13

48

52

LPT-D25-BK-BI

FB15 X_80_0805

CN2
X_220p

CN1
X_220p

LP_AFD#
LP_ERR#
LP_INIT#
LP_SLIN#

MSDATA{10}

MSCLK{10}

KBDATA{10}

KBCLK{10}

C333 0.1u

DTRB#{10}
RTSB#{10}

SOUTB{10}

+12VR

FB10 X_600

VCC5

20
DCDB
RXDB
RIB
CTSB
DSRB

16

15

13

11

C336 X_0.1u
FB40 X_80_0805

123456

78

RN1

4.7K

FB21 300
FB18 300

FB20 300
FB19 300

135

7

CN7
X_22p

246

8

/N

U54

VCC

2

RIN1

3

RIN2

4

RIN3

7

RIN4

9

RIN5
DIN1

DIN2
DIN3
GND

75232-1

ROUT1
ROUT2
ROUT3
ROUT4
ROUT5

DOUT1
DOUT2
DOUT3

1

V+

19
18
17
14
12

5
6
8
10

V-

COM_GND

PS2 KEYBOARD & MOUSE CONNECTOR

R20
1K

MS_DT
MS_CK

KB_DT
KB_CK

135

246

7

8

CN28
180p

SERIAL PORT 2

C334

+12VR

0.1u

DTRB
RTSB
TXDB

-12VR

0.1u

C335

CP4 X_COPPER

CP6 X_COPPER

For EMIFor EMI

KBMS1

14

4
6
2

13

1
5
3

15 17

MINIDINx2-D12-ML

VCC5

DCDB# {10}
SINB {10}
RIB# {10}
CTSB# {10}
DSRB# {10}

C372 X_0.1u

For EMI

16

10
12
8
7
11
9

C44

0.1u

DCDB
RXDB
RIB
DTRB

RTSB
CTSB
TXDB
DSRB

DCDB

35

RXDB

36

TXDB

37

DTRB

38
39

FB22 80_0805

C43

C61

33p

0.1u

CP7 X_COPPER

2
4
6
8

2
4
6
8

4650

FS2

1.1A-S
POLY SWITCH

For EMI

1

CN22

3

220p

5
7

1

CN21

3

220p

5
7

LPTC

DSRB

40

RTSB

41

CTSB

42

RIB

43

LPT-D25-BK-BI

VCC5_STR

SGND2KB_GND

FLOPPY CONNECTOR

FDD1

1 2

VCC5

R237 150
R238 150

A A

R239 150
R242 150
R236 150

INDEX#
TRACK0#
FDD_WP#
RDATA#
DSKCHG#

3 4
7 8

9 10
11 12
13 14
15 16
17 18
19
21 22
23 24
25 26
27 28
29 30
31 32
33 34

6

20

FLOPPY

8

7

6

5

4

DRVDEN0 {10}
DRVDEN1 {10}

INDEX# {10}
MOT_A# {10}
DRV_B# {10}
DRV_A# {10}
MOT_B# {10}
DIR# {10}
STEP# {10}
WT_DT# {10}
WT_EN# {10}
TRACK0# {10}
FDD_WP# {10}
RDATA# {10}
HEAD# {10}
DSKCHG# {10}

MSI

Title

I/O CONNECTORS & THERMTRIP CIRCUIT

Size Document Number Rev

3

Date: Sheet of

2

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

16 27Saturday, November 03, 2001

0AE2

1

E

D

C

B

A

THERMTRIP# DELAY CIRCUIT BLOCK

R776 0

VCC3 VCC3VCC3

R432

R431

4 4

NPN-3904LT1-S-SOT23

TRMTRIP#

R435

1K
R777

1K

D51

1N5817-S-DO-241AC

Q53

R430
47K

C270
1u-0805

1K

1K

Q51
PNP-3906LT1-S-SOT23

Q52
NPN-3904LT1-S-SOT23

VCCP_FB {20}

TRMTRIP#

VRM_GD{20}

R433
1K

R436 1K

Q56

NPN-3904LT1-S-SOT23

VCC3

VCC5

VCC5

Q54

NPN-3904LT1-S-SOT23

R437 1K

R434
1K

Q55

PNP-3906LT1-S-SOT23

Q50
X_NPN-3904LT1-S-SOT23

100pC269

ICH_VRM_GD {9}

R438 100K

TRMTRIP#{4}

THERMTRIP# CIRCUIT BLOCK

VCC1_8

R407
1K

R408 1K

TRMTRIP#

R409 1K

NPN-3904LT1-S-SOT23

PCIRST#{8}

Q41

NPN-3904LT1-S-SOT23

NPN-3904LT1-S-SOT23

R410 2.2K

R778

PWRSW {18}

Q47

Q49

1K

FRONT PANEL USB CONNECTOR FOR USB PORT 1,2

3 3

FS1

OC#1

1.5A-miniSMDC200-S

C33

0.1u

VCC5_STR

OC#1{9}

2 2

POWER CIRCUIT FOR USB PORT 1,2

FB7 80_0805

R14

2.7K

R16

5.1K
NEAR USB CONNECTOR

C28
470p

C25
1u-0805

C19
470p

+

CT5
1000u-10V

FB3
600

SVCC1

SGND1

FB6 X_600

135

246

7

8

CN25
X_33p

RN31 15

8
6
4
2

7
5
3
1

USBP2+{9}
USBP2-{9}

USBP3+{9}

R8
1K

/N

USBP3-{9}

NEAR ICH2 LESS THAN 1 INCH

246

135

FB17 120
FB12 120

FB24 120
FB23 120

8

RN2
15K

7

C56

C55

33p

33p

NEAR USB CONNECTOR

C47
33p

SBD2+
SBD2-

SBD3+
SBD3-

SBD2+ {18}
SBD2- {18}

SBD3+ {18}
SBD3- {18}

C52
33p

REAR PANEL USB CONNECTOR FOR USB PORT 3,4

POWER CIRCUIT FOR USB PORT 3,4

SGND2 SGND2

USBP1+
USBP1­USBP0+
USBP0-

RN32 15

8
6
4
2

7
5
3
1

USBP0+{9}

FS10

VCC5_STR

1 1

1.5A-miniSMDC200-S

OC#2 SGND2

C350

0.1u

FB31 80_0805

R402

2.7K

R403

5.1K
NEAR USB CONNECTOR

C352
470p

C351
1u-0805

C353
470p

+

CT31
1000u-10V

FB32
600

SVCC2

R404

SGND2 {16,21}OC#2{9}

1K

USBP0-{9}

USBP1+{9}
USBP1-{9}

* USB Trace width : 9 mils
* USB Trace Spacing : 25 mils
* Differential USB Signlas Trace, Spacing : 18 mils
* USB Power Trace must be 40mils width

E

D

C

USBP0+
USBP0-

USBP1+

USBP1-

135

7

CN26
X_33p

246

8

NEAR ICH2 LESS THAN 1 INCH

CP5 X_COPPER

FB13 X_600
C45 X_0.1u

FB28 120
FB27 120

FB26 120
FB25 120

246

8

RN6
15K

135

7

NEAR USB CONNECTOR

B

C58

C57

33p

33p

MSI

Title

Size Document Number Rev

Date: Sheet of

SBD1+
SBD1-

SVCC2
SBD0­SBD0+

SBD0+

SGND2

SBD0-

SGND2

C59

C60

33p

33p

USB CONNECTORS & THERMTRIP CIRCUIT

JL_U-1

21

1
2
3
4

24 23

L_YUSB-D1

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

17 27Saturday, November 03, 2001

A

22

SVCC2

5

SBD1-

6

SBD1+

7

SGND2

8

SGND2

0AE2

5

CT37
470u

CB238
33p

/N

11

3.3V

3.3V

12

3.3V

-12V

13

GND

GND

14

5V

PSON

15

GND

GND

16

5V

GND

17

GND

GND

18

POK

-5V

19

5VSB

5V

20

12V

5V

POWER

+

CB228

C227

33p

X_1000p

VCC3

-12V

CB240

0.1u

VCC5_SB

D D

SLP_S3#{9}

R181 10K
R178 4.7K

NPN-3904LT1-S-SOT23

CB241
33p

VCC5

CB239

0.1u

Q14

CB244

0.1u

C233
X_1000p

4

1

+

2
3
4
5
6
7
8
9
10

CT36
470u

11 10

CB226
33p

R281 33

CB242
33p

CB229

0.1u

CB230

0.1u

VCC3

CB243
1u-0805

VCC5

CB245
33p

U17E
DM7407-SOIC14
(VCC5_SB)

CB234

0.1u

ITP_GD {4,19}

+

VCC5_SB
+12V

CT33
22u

R286
1K

VCC3

RSTBTN#

R285 1.2K

3

ATX CONNECTOR

U15A

74LCX14-SOIC14

1 2

(VCC3_SB)

C188

2.2u

U15B

74LCX14-SOIC14

3 4

(VCC3_SB)

PWROK# {21}

R247 33

2

PWR_GD {9}

PWR_LED{10}

NPN-3904LT1-S-SOT23

POWER LED

SUS_LED{10}

PNP-3906LT1-S-SOT23

SLEEP LED

R395 1K

R389 1K

C399

0.01u

C400

0.01u

Q42

Q40

1

VCC3_SB

MEM_STR

R396

49.9

R390
150

P_LED

S_LED

SUPER-YEL-2.1V

AUX_LED

1 2

SMT TOP LED

STR_LED

GN-D-2.1V

1 2

520 FRONT PANEL

JFP2

1 2
3
5
7 8

9 10
11 12
13 14
15 16
17 18
19

23 24
25 26
27 28
29 30
31 32
33 34

C433
X_0.1u

VCC5_STR

4
6

20
22

C434
X_0.1u

VCC3_SB

C428
X_0.1u

C435
X_0.1u

C426
X_0.1u

C427
X_0.1u

PWRSW
IDE_LED

C430
X_0.1u

C436
X_0.1u

GPI_LOB1 {10}
GPI_FRONT_CABLE# {10}

SBD2- {17}

SBD3+ {17}

GPO_ESUPP_LED# {9}

GPI_ESUPPORT# {9}
INTRUDER# {9}

GPI_INTRUD_CABLE# {9}
PC_N {11}

C437
X_0.1u

VCC3

VCC3

C C

R745

4.7K

VCC3

+12V

SBD2+{17}

OC#1{9}

SBD3-{17}

GPI_PCSPKDET#{10}

PC_R{11}

B B

R746 0
PWRSW­P_LED
S_LED

C429

X_0.1u

C431

X_0.1u

HEAD2X17_2MM

C432
X_0.1u

VCC5

RSTBTN#

PWM{10}

POWER BUTTON

1312

U15E
74LCX14-SOIC14

R346 10K

C268
X_0.1u

C235
1u-0805

(VCC3_SB)

1110

SYS_CTR1{10}

U15F

PWRBTN#{9}

PWRBTN#
PWRSW

VCC3_SB

74LCX14-SOIC14

R347 4.7K

INTEL FRONT PANEL

R246
330

3
5 6
7

33

9

JFP1

HDD­GNDR PWSW+
RESET
RSVD

X_M_D2x9-2:4.8-BK

HDD+
IDE_LED

R294

CPU FAN

R421 510

SYSTEM FAN1

R371 510

21

PLED1HDD+

4

PLED2

8

PWSW-

CUT

10

+12V +12V

R255

4.7K

G

DS

G

P_LED
S_LED
PWRSW
PWRSW-

R259 1K

DS

Q58
2N7002S

R369 4.7K

R366 1K

Q59
2N7002S

R661
33

33pC245

PWRSW {17}GPI_LOB0{10}

R415 4.7K

D36

1N5817-S-DO-241AC

Q23
PNP-PBSS5140T-SOT23

CT58 10u

+12V

R365 4.7K

D37

1N5817-S-DO-241AC

Q37
PNP-PBSS5140T-SOT23

CT59 10u

BZ1

2 1

R357
10K

1N4148-S-LL34
R333 220
Q27

R417

10K

BUZZER

D4

CB302

0.1u

CPU_FAN1 {10}

SYS_FAN1 {10}

VCC5

R334
220

SPKR{9,10}

+

+

R335 2.2K

NPN-3904LT1-S-SOT23

R416 15K

3

C_FAN1

2

D1x3-WH-SN

1

R364 15K

3

S_FAN1

2

D1x3-WH-SN

1

A A

IDE LED

VCC5

5

R351

10K

NPN-3904LT1-S-SOT23

Q61

IDE_LED

Q62
NPN-3904LT1-S-SOT23

4

MSI

Title

SD_LED {3}PD_LED{3}

3

2

Size Document Number Rev

Date: Sheet of

Front Panel & ATX Connector & FAN

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

1

18 27Wednesday, November 07, 2001

0AE2

8

7

6

5

4

3

2

1

POWER TRANSLATOR

Q35

VCC3_SB

ITP_GD {18}

R172 10K

C170 1u-0805
R446 47

C403 0.022u

VCC5_SB

SPD09N05-S-TO252

VCC5_SB

Q110

NDS7002A-S-SOT23

VCC5_SB

R726 0

VCC2_5

VCC3

D D

VCC1_8

VCC3

C C

VCC_AGP

Q16
SPD09N05-S-TO252

SLP_S3#{9}
SLP_S5#{9}

VCC5_SB

D49
1N4148-S-LL34

D50
1N5817-S-DO-241AC

MEM_STR

Q13
SPD09N05-S-TO252

G7

R439 10

R307 4.7K

R308 4.7K
R171 1K
R180 1K

C168

0.01u

C169

0.1u

U12

4

GATE7

5

VDDQ

24

GATE8

23

1.8V

9

SLP_S3#

10

SLP_S5#

11

USB

12

PCI

13

CAP-

14

CAP+

15

FC

20

GND

SEMTECH SC1544

GATE1

5V_DUAL

GATE2/3

3.3DUAL_PCI
GATE4

TYPDET#

PWR_OK

ENABLE

5V_STB

GATE5

2.5/3.3DUAL
GATE6

FDN337N-S-SOT23

R622 0

18

C402 0.022u

17

R725 0

19
21
22
6
7
8
16
1
2
3

VCC3_SB Main Standby
VCC5_STR

VCC5_STR

Q36

+12V

VCC5
R747
100

C275
X_0.1u

REGULATORS OUTPUT DECOUPLING CAPACITORS

VCC1_8

CT32
1000u

CB170

0.1u
CB164
1u-0805

+

+

CT28

1000u
CB183
100p
CB189
10p

+

VCC3_SBVCC_AGPMEM_STR VCC5_SBVCC5 VCC5_STRVCC3

+

CT26
1000u

CT9
1000u

CB36

0.1u
CB7
1u-0805
CB11

0.1u
CB196

0.1u

CB24

0.1u

+

CT34
1000u

CB10

0.1u
CB235
1u-0805

1.8V/3.3V SEQUENCE CIRCUITCPU VID POWER GOOD BLOCK

VCC3

B B

A A

1V

VCC3_SB

VR2

3 2

CSK-2-SOT23-150mA

Vref=2.5V

R447

5.1K

C286

0.01u

R90
220

CB84

10u-1206

VCC3

VCC5_SB

Q11
NDS7002A-S-SOT23

1.2V/0.1A

R87
1K

Q10
NDS7002A-S-SOT23

6

VCC_VID {5}

VID_GD# {20}

+12V

C106

0.01u

R108
X_1.5K

R124

1.3K

R107

1.05K
3

+

1

2

-

R106
1K

/N

4 8

U8A
YLM358S-SOIC8

R406
1K

+12V

CB71

0.1u R384 0

5

+

6

-

4 8

U8B
YLM358S-SOIC8

R101 10K

7

C104
1u-0805

7

1

8

VCC3

R254
200

R253

NPN-3904LT1-S-SOT23

470

VR5

3 2

LCSK-1,SOT23-3L-100mA

5

R252 200

3K RST

1

2K RST
C470

1000p

R383

2V

R385

S0Power S5S3

Main
Main

123456

78

VCC3

Q28
NPN-2SC5001-S-DPAK
N CHANNEL

MEM_STR

VCC5_SB

CB5

0.1u
CB227
1u-0805

Q20

RN22
X_100

Q29
FDN337N-S-SOT23

+

Standby

Standby

0V
0VMEM_STR

Standby

CT38
1000u

CB9

0.1u
CB8

0.1u
CB160

0.1u

Q19
PNP-3906LT1-S-SOT23
Ic=200mA
Vebo=5V
Vceo=40V

VCC1_8

AGP POWER TRANSLATOR

+12V VCC3VCC5

CB252

0.1u

3

+

1

2

-

U19A

4 8

YLM358S-SOIC8

R386 0

CB254

0.1u

CB255

0.1u

4

CB256

0.1u

VCC3_SB

VCC5_SB

CB248

0.1u

VCC5 Discharge residual voltage on Power Off

VCC5 VCC5_SB

R397

4.7K

R399

4.7K

CB253

0.1u

Q39
FDB6035AL-S-TO263

VCC2_5

+

CT43

1000u

3

1.8V STANDBY POWER TRANSLATOR
(40mils trace / 20 mils space)

VR3
YLT1087S-0.8A

3 2

C196

0.1u

VIN VOUT

ADJ

1

C199

0.01u

R280
432

R279
200

C201
100p

3.3V STANDBY POWER TRANSLATOR
(60mils trace / 20 mils space)

VR4
REG-YLT1084DS-TO252-4.5A

VIN VOUT

CB249

0.1u

R398

4.7K

Q45
NPN-3904LT1-S-SOT23

Title

Size Document Number Rev

Date: Sheet of

MSI

RN20
22

ADJ

DS

G
C250

VCC5

123456

Q43
NDS7002A-S-SOT23

2

R381

CB250

200

100p

R382

3320.1u

78

123456

78

RN21
22

MICRO-STAR

VOLTAGE REGULATOR

MS-6542

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

C195

C200

4.7u-0805

0.1u

VCC3_SB

CB251

0.1u

Q44
NDS7002A-S-SOT23

19 27Saturday, November 03, 2001

1

VCC1_8SB

0AE2

5

4

3

2

1

CB22

0.1u

X_100pC66

R56
15K

C84
5600p

R50
X_0

CHOK1 1.1uH-25A

CB23
33pF

U6

1

VID4

2

VID3

3

VID2

4

VID1

5

VID0

19

PGOOD

6

COMP

7

FB

HIP6301V

R51 0

VCCP

VCC

GND

PWM1

ISEN1

PWM2

ISEN2FS/DIS

PWM3

ISEN3

PWM4

ISEN4

VSEN

R60 3.3

R41 0

R48 3.3

R39 0

R49 3.3

R40 0

C72
1u-0805

C67
1u-0805

C70
1u-0805

DS

DS

DS

DS

DS

DS

G

Q9
IPB15N03LG

CHOK4 1.1uH-25A

Q8
FDB6670AL-S-TO263G

Q3
IPB15N03LG

Q4
FDB6670AL-S-TO263G

Q6
IPB15N03LG

CHOK3 1.1uH-25A

Q5
FDB6670AL-S-TO263

C85
X_0.01u

VCCP

CT16

CT17

1500u-6.3V

1500u-6.3V

CT12
2200u-6.3V

R54
0

CT14
2200u-6.3V

CT11
2200u-6.3V

CT23
2200u-6.3V

CT18
1500u-6.3V

CT19
1500u-6.3V

CT13
2200u-6.3V

CT21
2200u-6.3V

Power Zone decoupling caps

CB259 100p

VCC5

CT4
1500u-16V

VCC5

+12V

R44
0

C71
1u-0805

CT8
1500u-16V

C64
33pF

VCC

20

9
15

R33 3K

16

14

R34 3K

138

11

R35 3K

12

VCC

18
17

10

10101

1.325

00101

1.350

11001

1.375

01001

1.400

10001

1.425

00001

1.450

11110

1.475

01110

1.500

10110

1.525

00110

1.550

R37 0

CB14
1u-0805

CB19
1u-0805

CB12
1u-0805

CT6
1500u-16V

+12V

+12V

R42
0

R36
0

CT7
1500u-16V

U3A

14

VCC

U_G1

BOOT1

PHASE1

3

GND

1

PWM1

L_G1

HIP6602A

U3B

5 9

PVCC U_G2

BOOT2

PHASE2

6

PGND

2

PWM2

L_G2

HIP6602A

U5

6

VCC
PVCC

GND

PWM

U_G

BOOT

PHASE

L_G

7

4

3

HIP6601A/03A

C63

4.7u-1206

12
11

13

C81
X_1000p

4

10

8

C73
X_1000p

7

1
2

8

C78
X_1000p

5

C79

0.1u

C80

0.1u

C76

0.1u

C65

4.7u-1206

+12V

D D

R57
X_15K

C83

C87
15p

VID4
VID3
VID2
VID1
VID0

R32 0

R59 154K

R52
2K

VID[0..4]{4}

R38 10K

VCC3

VRM_GD{17}

C C

VCCPS+{4}

VCCP_FB{17}

VCCPS-{4}

DIS

R61 470K CHOK2 1.1uH-25A

VCC5

R58 X_0

X_5600p

R53 X_0

HIP6301 -- VRM 9.0/9.2
VID4 VID3 VID2 VID1 VID0 VDC(V) VID4 VID3 VID2 VID1 VID0 VDC(V)

1

1 1 1 1
1 1 1 1
1 1 1 1

B B

1 1 11

0

0
1 1 1
1 1
1

0 0

0

1 0 0

1 0 1 1 1

OFF

0

1.100

1.125

1.150

00111

1.175

00

1.200

1

1.225

1.250

1.275

01101

1.300

ATX12V POWER CONNECTOR PWM GOOD

VID3

1

A A

CB18

CB27

4.7u-1206

C75

0.01u

5

+12V

4.7u-1206

JPW1

3

4

D2x2
C74
33p

1

GND

12V

2

GND

12V

VID2
VID1
VID0
VID4

4

2

3

4

5

6

7

8

R55 1K

RN8
1K

D48

RLZ3.3V

+12V

A C

R669
1K-1206

C272

0.1u

VCC3_VID

3

R669 Iz D48

3001k20mA

5mA

ROHM or TEMIC

PHILIPS or VISHAY

VID_GD#{19}

MSI

Title

INTERSIL HIP6301A+HIP6601A/02A - CPU Power

Size Document Number Rev

2

Date: Sheet of

MICRO-STAR

MS-6542

VID PULL-UP RESISTORS

DIS

Q7
NDS7002A-S-SOT23

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

20 27Saturday, November 03, 2001

1

0AE2

8

7

6

5

4

3

2

1

VCC3_SB

L21 80_0805

VCC1

VSS1

VCC2

VSS2

VSS3

VCCP1

VCCP2

VSS4

VSS5

C359
L_104P

VCCA

VSSP1

VCCA2

VSSP2

VSSA

VCCT1

VCCT4

VSSA2

VCCT2

C360
L_104P

D D

C366

C367

ELAN_CLK{8}

C C

ELAN_SYNC{8}
ELAN_RXD0{8}
ELAN_RXD1{8}
ELAN_RXD2{8}
ELAN_TXD0{8}
ELAN_TXD1{8}
ELAN_TXD2{8}

Trace : 30/8/8/30

B B

L_22P

L_22P

1 2

LAN_DIS

C361
L_104P

Y10

L_25MHZ

C363
L_104P

C362
L_104P

VCC3_SB

125364027914171219

46

X1

47

X2

39

LAN_CLK

42

LAN_RSTSYNC

34

LAN_RXD0

35

LAN_RXD1

37

LAN_RXD2

43

LAN_TXD0

44

LAN_TXD1

45 27

LAN_TXD2 LILED#

41

ADV10

30

ISOL_TCK

28

ISOL_TI

29

ISOL_TEX

26

TOUT

21

TESTEN

8131824483338362022

VCCT3

RBIAS100

VSSR1

VSSR2

U56

23

VCCR1

VCCR2

TDP

TDN

RDP

RDN

ACTLED#
SPDLED#

RBIAS10

L_W82562EM

C364
L_104P

C365
L_104P

Place Termination R as close
to 82562EM as possible

TXDP

10

11

15

16

32
31

4

5

R580
100RST

TXDN

RXIP

R581
X_100RST

RXIN

LILED#
ACTLED#
SPEEDLED#

R592 L_549RST

R582 619RST

VCC3_SB

Trace : 8mil Space : 8mil

Space :30mil

Trace : 8mil Space : 8mil

SPEEDLED#{23}

LILED#{23}
ACTLED#{23}

PWROK#{18}

SPEEDLED#

VCC3_SB

LILED#
ACTLED#

SGND2{16,17}

TXDN_C

TXDP_C

3.3K_0603

NDS7002A-S-SOT23

PWROK#

R593

L_330
R594

L_330

SGND2

L22 30

L23 30

FOR EMI

+12V

R588

Q107

R591

10K_0603

25
18

17

20
19

26

JL_U-2

L_YUSB-D1

TXDN

TXDP

27
9

G

10
11
12
13
14

Y

15
16
28

C375

X_102P

MX3N
RXIN
MX2P
TXDN_C
MX3P
MX2N
RXIP
TXDP_C

R609
0

MX3N {23}
RXIN {23}
MX2P {23}

TXDN_C {23}

MX3P {23}
MX2N {23}
RXIP {23}

TXDP_C {23}

17

Green

189

13

10

RX-

14

11

15

12

TX-

RX+

16

TX+

19
20

LAN&USB Layout

SMB_CLK_RSM

Q105
NDS7002A-S-SOT23

SMB_CLK_MAIN
SMB_DATA_RSM

SMB_CLK_RSM {9,15,22}

SMB_CLK_MAIN {3,10,13,23}

SMB_DATA_RSM {9,15,22}

VCC

GND

VCC3_SB

R668

4.7K
8
7

NC

6

NC

5

7

C438

0.01u

10/05/'01 Update

RSM_GD{9}

ENET_DIS{9}

6

R779
X_1K

ENET_DIS

R608 10K

R584
10K

R583

EE_EECS

10K

EE_EECS{8,23}
EE_SHCLK{8,23}
EE_DOUT{8,23}

A A

EE_DIN{8,23}

Remark:
82562EM with 93C66:M33-26N0103-A26

*

82562ET with 93C46:M33-15O0203-A26

8

64WORD W/ 82562ET
256WORD W/ 82562EM

EE_EECS

1
2
3
4

U57

CS
SK
DI
DO

L_93C66S

VCC3_SB

R585
10K

Q108
NPN-3904LT1-S-SOT23

5

LAN_DIS

Q106

NDS7002A-S-SOT23

SMB_DATA_MAIN

MSI

Title

Size Document Number Rev

4

3

Date: Sheet of

2

MICRO-STAR

Kinnerith and LAN Connector

SMB_DATA_MAIN {3,10,13,23}

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

21 27Saturday, November 03, 2001

1

0AE2

8

7

6

5

4

3

2

1

DDR REGULATOR

PCI SLOT 4 (PCI VER: 2.2 COMPLY)

+

CT51
1500U/6.3V

VTT_DDR

C307
104P

PTCK{15}

INTA#{8}

INTC#{8}

PCICLK3{3}
PREQ#3{8,15}

AD31{8,15,23}
AD29{8,15,23}

AD27{8,15,23}
AD25{8,15,23}

C_BE#3{8,15,23}

AD23{8,15,23}
AD21{8,15,23}

AD19{8,15,23}
AD17{8,15,23}

C_BE#2{8,15,23}

IRDY#{8,15,23}

R637 0

C314
104P

C311 102P

R505 100K

CHOK10

1 2

3.3UH

C378 104P

DDRVCC2U19_VCCQ

R502
1K

+

CT50
1500U/6.3V

D D

MEM_STR

C304
104P

DDRVCC1
DDRVCC2

+

CT52
1000u

1

VCC1

16

VCC2

2

PVDD1

15

PVDD2

4

PGND1

13

PGND2

5

AGND1

8

AGND2

9

AGND3

12

AGND4

VL1
VL2

VIN/2

VCCQ

SD

FB

R503 5.1RST
R507 5.1RST

C309

C305

104P

104P

C373
104P

R632
X_10KRST

U52

U19_VL

3
14

U19_VI

7

R631 X_10KRST

10
6

U19_FB U19_FB_C

11

CM8500

C C

D LED

DEVSEL#{8,15,23}

VCC5 VCC5

PLOCK#{8,15}

PERR#{8,15,23}
SERR#{8,15,23}

C_BE#1{8,15,23}

RN539
D_330

1 2

3 4

5 6

7 8

B B

D_LED1{10}
D_LED2{10}
D_LED3{10}
D_LED4{10}

D_LED1
D_LED2
D_LED3
D_LED4

RN541
D_10K

1 2

3 4

5 6

7 8

D_LED

2 1

4 3

D_GN_RD-D-5V-CR-A

LED1

LED2

LED3

56

LED4

78

RN540

D_330

1 2

3 4

5 6

7 8

AD14{8,15,23}
AD12{8,15,23}

AD10{8,15,23}

AD8{8,15,23}
AD7{8,15,23}

AD5{8,15,23}
AD3{8,15,23}

AD1{8,15,23}

ACK#64{15} REQ#64 {15}

VCC5

VCC3

-12V
PCI4

B1

-12V

B2

TCK

B3

GND

B4

TDO

B5

+5V

B6

+5V

B7

INTB#

B8

INTD#

B9

PRSNT#1

B10

RESERVED

B11

PRSNT#2

B12

GND

B13

GND

B14

RESERVED

B15

GND

B16

CLK

B17

GND

B18

REQ#

B19

+5V(I/O)

B20

AD31

B21

AD29

B22

GND

B23

AD27

B24

AD25

B25

+3.3V

B26

C/BE#3

B27

AD23

B28

GND

B29

AD21

B30

AD19

B31

+3.3V

B32

AD17

B33

C/BE#2

B34

GND

B35

IRDY#

B36

+3.3V

B37

DEVSEL#

B38

GND

B39

LOCK#

B40

PERR#

B41

+3.3V

B42

SERR#

B43

+3.3V

B44

C/BE#1

B45

AD14

B46

GND

B47

AD12

B48

AD10

B49

GND

B52

AD8

B53

AD7

B54

+3.3V

B55

AD5

B56

AD3

B57

GND

B58

AD1

B59

+5V(I/O)

B60

ACK64#

B61

+5V

B62

+5V

PCI-D120-WH-SN

IDSEL = AD19
MASTER = PREQ4

TRST#

+12V

TMS

+5V
INTA#
INTC#

+5V

RESERVED

+5V(I/O)

RESERVED

GND
GND

RESERVED

RST#

+5V(I/O)

GNT#

GND

RESERVED

AD30

+3.3V

AD28
AD26

GND

AD24

IDSEL

+3.3
AD22
AD20

GND
AD18
AD16

+3.3V

FRAME#

GND

TRDY#

GND

STOP#

+3.3V

SDONE

SBO#

GND

PAR

AD15

+3.3V

AD13
AD11

GND

AD9

C/BE#0

+3.3V

AD6
AD4

GND

AD2
AD0

+5V(I/O)

REQ64#

+5V
+5V

+12V

A1
A2
A3
A4

TDI

A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49

A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62

VCC3

VCC5

VCC3_SB

R506 33

PTRST# {15}
PTMS {15}

PTDI {15}
INTD# {8}

INTB# {8}

PCIRST#2 {3}
PGNT#3 {8}
PME# {8,14,15,23}

AD30 {8,15,23}
AD28 {8,15,23}

AD26 {8,15,23}
AD24 {8,15,23}

AD19

AD22 {8,15,23}
AD20 {8,15,23}

AD18 {8,15,23}
AD16 {8,15,23}

FRAME# {8,15,23}
TRDY# {8,15,23}
STOP# {8,15,23}
SMB_CLK_RSM {9,15,21}

SMB_DATA_RSM {9,15,21}
PAR {8,15,23}

AD15 {8,15,23}
AD13 {8,15,23}

AD11 {8,15,23}
AD9 {8,15,23}

C_BE#0 {8,15,23}
AD6 {8,15,23}

AD4 {8,15,23}
AD2 {8,15,23}

AD0 {8,15,23}

INT : D,A,B,C

D_NPN-3904LT1-S-SOT23

LEDT4

A A

8

LEDT3
LEDT2
LEDT1

7

C

Q111

B

E

D_NPN-3904LT1-S-SOT23

C

Q112

B

E

6

D_NPN-3904LT1-S-SOT23

C

B

E

Q113

D_NPN-3904LT1-S-SOT23

C

B

E

5

Q114

+

VCC3VCC5

CT73

+

1000u

CB413

0.1u
CB415

0.1u
CB417

0.1u
CB419

0.1u

4

CT74
1000u

CB414

0.1u
CB416

0.1u
CB418

0.1u
CB420

0.1u

Title

MSI

Size Document Number Rev

3

Date: Sheet of

2

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

DDR regulator & PCI4 Slot &D LED

MS-6542

22 27Saturday, November 03, 2001

0AE2

1

A

LVCC3

VCC3_SB

U61

4 4

AD0

AD[0..31]{8,15,22}

PCIRST#1

3 3

2 2

SMB_DATA_MAIN
SMB_CLK_MAIN

C440
X_470p

C_BE#[0..3]{8,15,22}

VCC3_SB

VCC3_SB

C444 L_33P/6

L_25MHZ/30PPM

C445 L_33P/6

PAR
AD20

R765 L_33
LAN_PCLK
INTH#
PCIRST#1
PGNT#4
PREQ#4
FRAME#
IRDY#
TRDY#
DEVSEL#
STOP#
PERR#
SERR#
PME#

SMB_DATA_MAIN
SMB_CLK_MAIN

R771 L_10K

PAR{8,15,22}

LAN_PCLK{3}

INTH#{9}

PCIRST#1{3}

PGNT#4{8}

PREQ#4{8}

FRAME#{8,15,22}

IRDY#{8,15,22}

TRDY#{8,15,22}

DEVSEL#{8,15,22}

STOP#{8,15,22}

PERR#{8,15,22}
SERR#{8,15,22}
PME#{8,15,22}

AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31

C_BE#0
C_BE#1
C_BE#2
C_BE#3

X4

B11

AD0

D11

AD1

C11

AD2

B12

AD3

A12

AD4

C12

AD5

B13

AD6

A14

AD7

C13

AD8

E11

AD9

B14

AD10

E12

AD11

D13

AD12

F11

AD13

E13

AD14

E14

AD15

J12

AD16

J13

AD17

K11

AD18

L12

AD19

K12

AD20

K13

AD21

L11

AD22

L13

AD23

N14

AD24

N13

AD25

P14

AD26

P12

AD27

M11

AD28

N12

AD29

P11

AD30

N11

AD31

D12

/CBEN0

F12

/CBEN1

H13

/CBEN2

M13

/CBEN3

G12

PAR

M12

IDSEL

L8

PCICLK

L9

/INTA

N9

/RST

M9

/GNT

L10

/REQ

J11

/FRAME

H11

/IRDY

G13

/TRDY

H12

/DEVSEL

F14

/STOP

G11

/PERR

F13

/SERR

M8

/PMEN

M7

AUXP

A1

SMBDATA

C3

SMBCLK

G3

/SMBCS

X25HI

G2

X25LO

L_TORNADO_V1_BGA

K1

VDD5VD

VSSPCI1

N10

M2

L2

VDD5VA1

VSSPCI2

M14

H14

P10

VDD5VA2

VSSPCI3

VSSPCI4

D14

A13

L14P8C14

VDDPCI1

VDDPCI2

VSSIO1

VSSPCI5

D2

J2

A11

VDDPCI3

VDDPCI4

VSSIO2

VSSIO3

A10

A7

D1

VDDIO1

VSSX1

VSSIO4

E2

J1

VDDIO2

VSSX2

F2

B10

VDDIO3

VSSX3

H2

A6

VDDIO4

VSSX4

B

H1

E1

G1

VDDX3

VDDX1

VDDX2

3C920V1
PBGA196

VSSX7

VSSX6

VSSX5

VSSX8

K14

N8P7P3

A8

TXVCC3

J14P2P9M4N1

B8

VDDX5

VDDX4

VSSTRAN2

VSSTRAN1

K2

P1

L1

M1

VDDX7

VDDTRAN1

VSSTRAN3

VSSRX1

VSSTX1

N2F1P5

M6

L6

DLLBYP

VDDTRAN2

VSSTX2

VSSX1

F6F7F8F9G6

VCC5

N3

VDDRX1

VDDRX2

VDD5VPCI1

VSSX1

VSSX1

VSSX1

VSSX1

VSSX1

G7G8G9H6H7H8H9J6J7

DLLVCCRXVCC3

N7

G14

VDD5VPCI2

VDD5VPCI3

VSSX1

VSSX1

N5

VDDTX1

VDDLVDET

LD0_POR0
LD1_POR1
LD2_POR2

LD4_POR4
LD6_POR6

LA2_POR10

RXD0_LA6
RXD1_LA7
RXD2_LA8
RXD3_LA9

RXER_LA10
RXDV_LA11

TXD0_LA12
TXD1_LA13
TXD2_LA14
TXD3_LA15

COL_LA16

/ROMCS

/MEMR

/MEMW

EECLK//ACT

DTOEE//100LNK

DFRMEE//10LNK

/SOS2_TXCLK

/SOS3_TXEN
/SOS4_CRS

/SOS5_RXOE

/SOS6_RXCLK

/SOS7_MDCLK

MEDTEST
/GLBTEST

PHYTEST

VSSX1

VSSX1

VSSX1

VSSX1

VSSX1

MDIO

EESEL

TXOP

TXON

RXIP
RXIN

/SOS1

REFR

VSSX1

LD3

LD5
LD7

LA0
LA1

LA3
LA4
LA5

J8

VSSX1

J9

VSSX1

C

R749

L_10K
C439
L_1u

Sets "Standard features"
Sets "SMBus"
Sets "16K EEProm"

B7

LDATA1

C7
B6
D6

LDATA4

C6
C5

LDATA6

A5
B5

A4
D5
B4
C4
A3
A2

C1
D3
E4
E3

F3
G4

R756 X_0

H3

R757 X_0

H4

R762 X_0

J4

R763 X_0

J3
K4

D7
B3
D4

R764 L_10K

B2

EESEL

D9

EECLK

A9

DTOEE

C8

DFRMEE

D8

TXOP

N6

TXON

P6

RFIP

N4

RFIN

P4

SOS1-

M3

SOS2-

L3

SOS3-

L4

SOS4-

K3

SOS5-

F4

SOS6-

C2

SOS7-

B1

M5

L7
C9
B9

VCC3_SB

R753 L_10K

R754 L_10K

R755 L_10K

Traces reserve
for Giga-bit
signals

MDI2P
MDI2N
MDI3P
MDI3N

SOS4­SOS2­SOS3­SOS1­SOS6­SOS5­SOS7-

R772

Place as close

L_1.3K

as possible to
3C920

C450

L_2.2u

RN100 L_1K
7 8
5 6
3 4
1 2
7 8
5 6
3 4
1 2

RN101 L_1K

LVCC3

+

R773

L_330

D

VCC3_SB

DS

R758
L_49.9

R766
L_49.9

RN542
7 8
5 6
3 4
1 2

X_0

SPDLED#

R751
X_330

ACTLED#

Q115
X_2N7002SG

R759
X_49.9

R767
X_49.9

ACTLED# {21}

R760
X_49.9

R761

L_49.9

R769
L_49.9

R768
X_49.9

RXVCC3VCC3_SB VCC3_SB VCC3_SB

C447
L_2.2u

DFRMEE
EESEL
EECLK
DTOEE

DTOEE

TXOP
TXON
RFIN
RFIP
MDI2P
MDI2N
MDI3P
MDI3N

VCC3_SB

TXVCC3 DLLVCC

FB43

L_80_0805
C446
L_2.2u

R748

X_510

R750 X_0

VCC3_SB

C441
L_0.01u

R780 X_0
R781 X_0
R782 X_0
R783 X_0
R784 X_0
R785 X_0
R786 X_0
R787 X_0

C443
L_0.1u

FB44

L_80_0805

EE_DOUT
EE_DIN
EE_EECS
EE_SHCLKSPDLED#

SPEEDLED#

DFRMEE

E

VCC3_SB

G

C442
L_0.1u

Place as close
as possible to
3C920

C448
L_0.01u

EE_DOUT {21}
EE_DIN {21}
EE_EECS {21}
EE_SHCLK {21}

SPEEDLED# {21}

R752
X_330

LILED#

DS

Q116
X_2N7002S

Place as close
as possible to
LAN
connector

TXDP_C {21}
TXDN_C {21}
RXIN {21}
RXIP {21}
MX2P {21}
MX2N {21}
MX3P {21}
MX3N {21}

FB45

L_80_0805
C449
L_2.2u

LILED# {21}

1 1

C451
L_0.01u

C452
L_0.01u

A

C453
L_0.01u

VCC3_SBVCC5

C454

C455

C456

C457

C458

C459

C460

C461

L_0.01u

L_0.01u

L_0.01u

L_0.01u

L_0.01u

L_0.01u

B

L_0.01u

L_0.01u

C462
L_0.01u

LVCC3

C463
L_0.01u

C

C464
L_0.01u

TXVCC3 RXVCC3 DLLVCC

C466

C465
L_0.01u

L_0.01u

C467
L_0.01u

C468
L_0.01u

D

MSI

Title

Size Document Number Rev

Date: Sheet of

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

3COM LAN Connector

MS-6542

E

23 27Saturday, November 03, 2001

0AE2

5

4

3

2

1

POWER MOSFET HEAT SINK

D D

MCH HEAT SINK

C C

B B

12

A A

MSI

MICRO-STAR

MAUNAL PARTS

MS-6542

5

4

3

2

1

ICH2

5

4

3

2

1

GPIO Setting

SIO

GPIO

D D

GPIO0/REQA# GPI0
GPIO16/GNTA# L2 GPIO16
GPIO1/REQB#/REQ5# REQ5#
GPIO17/GNTA#/GNT5# L4
GPIO11/SMBALERT# AB17
GPIO12
GPIO13

C C

GPIO21
GPIO22
GPIO23
GPIO27
GPIO28
GPIO2/PIRQE#
GPIO3/PIRQF#

B B

GPIO4/PIRQG#
GPIO5/PIRQH#
GPIO6
GPIO7
GPIO8
GPIO18 A15

Pin Default

M3

L3

GNT5#

SMBALERT#
W14
AB15
L1
B14
A14
AB14
AA14
N3
N2
N1
M4
Y11
AA11
Y14

SIO_PME#

GPI_ESUPPORT#

CLEAR RTC

NC

NC

GPI_INTRUD_CABLE#

PSWD

PIRQE#

PIRQF#

PIRQG#

PIRQH#

PD_DET

SD_DET

SIO_SMI#

NC

Directory

Input
Output
Input
Output
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output

GPIO

JB11/GP10
JB12/GP11 33
JB21/GP12
JB22/GP13 35
JX1/GP14 36
JY1/GP15
JX2/GP16
JY2/GP17
GP20/P17
MIDI_IN/GP25

MIDI_OUT/GP26
FAN_CTL1/GP33
FAN_CTL2/GP32
FAN_SEN1/GP31
FAN_SEN2/GP30
LED1/GP60
LED2/GP61
SYSOPT/GP24
IO_SMI#/GP27
IO_PME#/GP42
DDRC/GP43

KBRST#/GP36

Pin Default

32

GPI_PCSPKEDT
GPI_PCSPK_CTR

34

D_LED1
D_LED2
GPI_LOB0
GPI_LOB1

37
38

GPI_FRONT_CABLE#

39

FNTA_P10
GP20L

41

D_LED3

46
47

D_LED4

55

PWM

54

SYS_CTR1
CPU_FAN152
FAN_SEN151

48

PWR_LED

49

SUS_LED

45

SIO_SMI#

50
17

SIO_PME#
KB_RST#63 Output

Directory

Output
Output
Output
Output
Input
Output
Output
Output
Input
Output

Output
Output
Output
Input
Input
Output
Output
InputSIO_ADDR
Output
Output
InputGPO_ESUPP_LED#28

GA20/GP37 64 A20GATE# Output
DTR#2/GP57 100 Output
RTS#/GP55 98 Output
TXD2/GP53/IRTX 96 Output
DSR#2/GP54 97 Output
DCD#2/GP51 94 Output
CTS#2/GP56 99 Output
RXD2/GP52/IRRX 95 Output
RI#2/GP50 92 Output
IRTX/GP35 62 GP35
IRRX/GP34 61 GP34

NC
NC
NC
NC
NC
NC
NC
NC

Input
Output

GPIO19

A A

GPIO20

C14 Output

GPIO24 V21
GPIO25

5

NC

NC

ENET_DIS

NC

4

OutputD14

Output
OutputW15

MSI

Title

Size Document Number Rev

3

2

Date: Sheet of

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

GPIO SETTING

MS-6542

1

25 27Saturday, November 03, 2001

0AE2

5

4

3

2

1

Jumper Setting & Connector Setting

D D

Jumper Description Connector Description

BIOS functionJROM

1-2
2-3

REMOVED
JBAT1

1-2

Normal
Configuration Mode

Recovery
Clear CMOS

Normal
Clear CMOS2-3

(Default)

(Default)

JBAT Clear CMOS
J_PSWD Clear Pass word

Rear Connector Description

C C

KBMS1 PS/2 Keyboard and PS/2 mouse

2 Ports USBJL_U

COM1

Serial Port 1

COM2 Serial Port 2

Parallel PortLPT
Audio Line Out Phone JackL_OUT
Audio Line In Phone JackL_IN
Audio Mic In Phone JackMIC_IN

U3 Intel mPGA478-B CPU
IDE1

IDE2

Primary IDE
Secondary IDE

BatteryBAT1
CD_IN1 CDROM Header (ATAPI)
MODEM_IN1 MODEM INPUT
AUX_IN1 AUX INPUT

U10 BIOS
DDR0

DDR1

DDR DIMM1

DDR DIMM2

FloppyFDD1
POWER

ATX Power

ATX12V PowerJPW1

CPU Fan HeaderC_FAN
S_FAN System Fan Header

JFP2

Front Panel

Pin1 GPI_LOB0
Pin2,3,4
Pin5
Pin6

VCC5_STR

VCC3

VCC_SB
Pin7 +12V

VCCP VCC_AGP

CPU

69.0A NOTE40

MCH

2.4A NOTE1 0.2A 2.0A 0 0
ICH2
CY28324
AD1885
FWH -SST
W83627HF
HIP6301
HIP6602A
HIP6601A

DIMM
AGP
PCI
USB
USB HUB
FAN
TTL
AMPLIFIER
OTHER

NOTE1 --- MCH
VCC_AGP

NOTE2 --- DIMM
S0 STATE --- 2.0A * 3 = 6.0A ---> VCC3
S1/S3 STATE --- 200mA * 3 = 600mA ---> VCC3_SB
VCC3_SB --> 600mA*3.3V/5V=396mA --> VCC5_SB

NOTE3 --- ICH2

1.8V

1.8V_LAN 36mA
VCC1_8SB
VCC3
VCC3+562ET
VCC3_SB

VCC3_SB
VCC1_8SB
VCC5_SB

0
0
0
0
0
0
0
0
0

0
0 0 0 0
0
0
0
0
0
0 0 0 0

= VCC1_5 (1.5A) VCC_AGP (0.37A)+

S0Power S3/S4/S5

300mA
45mA

410mA
230mA
25mA

=
=
= VCC3_SB VCC1_8SB+

Pin8 GPI_LOB1

Slot Description

B B

PCI Slot1PCI1
PCI2 PCI Slot2
PCI3 PCI Slot3
PCI4 PCI Slot4

F_AUDIO Description

GNDPin1
Pin2 SPK_L
Pin3 FN_SPK_L
Pin4
Pin5
Pin6

A A

Pin7
Pin8
Pin9
Pin10

5

SPK_R

FN_SPK_R

FNT_MIC1

KEY

VREF

FNTA_9

FNTA_10

4

Pin
9,11,14,16,19,25,29

Pin10
Pin12
Pin13
Pin15
Pin17
Pin18

GND
GPI_FRONT_CABLE#
USB_P2-_R
USB_P2+_R
USB_OC23#
USB_P3+_R

USB_P3-_R
Pin20 ICH_PWRBTN#
Pin21

NC_FP_KEY
Pin22 FNT_HDLED#
Pin23
Pin24
Pin26
Pin27
Pin28
Pin30
Pin31
Pin32
Pin33
Pin34

FNT_GLEDVCC

FNT_ESUPPORT_LED

USB_OC23#

FNT_YLEDVCC

GPI_ESUPPORT#

INTRUDER#

GPI_AUD_PCSPKDET#

GPI_INTRUD_CABLE#

AUD_PCSPK_POS

AUD_PCSPK_NEG

3

2

POWER CONSUMPTION

VCC1_8

VCC3_DIMM VCC3 VCC5

0

0

0
0

NOTE3 NOTE3 NOTE3

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0SC1547

0

0
0

0
0
0
0

S1
100mA
28mA
30mA
5mA
210mA

0.6mA

NOTE20

0
0

0
0
0
0
00

N/A
N/A
7mA
N/A
N/A
N/A

MSI

Title

Size Document Number Rev

Date: Sheet of

0
0
0
0
0
0
0
0
0

0
0

0
0
0
0

0
0

?

21mA 50mA
15mA

0
0
0
0
0
0

6.0A 1.0A8.0A 2.0A

7.6A 5.0A

0
0
0
0

0

JUMPER SEETING

VCC5_SB

0

0
0

0
0
0

0

0
0

0

0

NOTE2

?
0

0

0

0

0

0

0
0
0

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

MS-6542

1

26 27Saturday, November 03, 2001

+12V

0
0
0
0
0 0
0

0
0

0

500mA

0
0
0
0
0

-12V

0
0
0
0
0

0
0
0
0
0
0
0

100mA

0
0
0
0
0
0

0AE2

5

4

3

2

1

Revision Initial ver: 0AE0 on 08/27/'01

Schematic Initial Revision 0AE0 was base on 6542/0AE01 modification.

Revision change list from ver: 0AE0 to ver: 0AE1 on 08/27/2001

1) Add EMI suggestion for Ferrite bead type change. Check EMail for detail.

D D

2) p.7 : Rs change from 33 to 10 ohm, and Rt change from 47 to 56 ohm as Alber of Advance team recommandation.

3) p.10 : Change LPC frm 142 to 192 as PM command for cost down. Removed U9.

4) p.18 : Front Panel should be Intel standard for MSI standard -PM/James.

5) p.19 : VCC3_VID circuit will modify again as Howard mentioned in the review meeting.

6) p.20 : Input E-Cap q'ty change from 4 to 3 pcs as Howard suggestion.

8/14/'01 : dELECT SOME Caps due to PCB space i ssue.
8/15/'01 : Specification change from Flex-ATX to u-ATX FF. Add AGP Slot, POV3 and Inter Speaker support .
8/21/'01 : Specification change, product naming change to 6541 and add GiGaBit for future LAN solution. Wait for further schedule from PM-James.

1) GiGaBit notice : Must check connector(FOXCON) vendor if there's any aolution to support 10/100/1G with same transformer.

9/19/'01 : Specification change

1) Follow Flex-ATX layout file to modify currently 6542 schematics.

9/27/'01 : Revision change to 0AE2

1) Removed ITP port p.4.

C C

2) Clock gen change to ICS 950201 on p.3.

3) 520 Front Panel, Front Audio support.

10/29/'01 : Gerber out
11/3/'01 :

1) P.19 : Add two 4.7K(R307,R308) ohm and pull-down on SLP_S3# and SLP_S5# to previent initial stage fail issue as Check-List mentioned.

2) P.14 : Disable R789 for BOM issue.

B B

A A

MSI

Title

Size Document Number Rev

5

4

3

2

Date: Sheet of

MICRO-STAR

H/W Project Leader : Joey Lee
H/W Project Engineer : Richard Shih

History

MS-6542

1

27 27Saturday, November 03, 2001

0AE2