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MS-6501
Schematics
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Schematics
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user Manual
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MSI MS-6501 Schematics

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Page 1
1
Cover Sheet
Block Diagram
Clock Synthesizer
AMD 762--------North Bridge
DDR DIMM-184
AGP 4X SLOT
PCI Connectors
1
2
3
4,5,6,7PGA462 Socket A CPU0/CPU1
8,9,10,11,12
13,14
15
16,17,18,19
MS-6501 ATX
Last Update xx/xx/2000
CPU:
Version 0A
Dual AMD Socket-462 Processors
20,21AMD 768--------South Bridge
LPC SuperI/O
ATA66/100 Connectors
Parallel / Serial Port
Keyboard & Mouse
22
23
24
25
System Chipset: AMD 762(North Bridge) AMD 768 (South Bridge)
BIOS & FANs 26
A A
USB Conector
AC'97 Codec
Audio/Game Port
DDR Regulator & STR LDO
27
28
29
30
31
Expansion Slots: AGP-Pro SLOT * 1 PCI2.2 PCI/64/66 SLOT * 2 PCI2.2 PCI/32/33 SLOT * 3
LAN
MS-3
VRM
DDR Terminator
IGD4 PCI Strappings
OPUS PCI Strappings
Bypass Capacitors
32
33
34
35
36
37
38
39Mounting Hole
On Board: LAN 82559ER AC97 Codec PC 2 PC
1
Title
Size Document Number Rev Custom Date: Sheet of
MICRO-STAR
Cover Sheet
MS-6501
1 39Tuesday, July 17, 2001
0A
Page 2
1
K7 462-Pin
VRM Clock
AGP PRO 2X/4X
A A
UltraDMA
IDE Primary
33/66/100
Socket Processor
AMD SYSTEM BUS
AMD762 North Bridge
K7 462-Pin Socket Processor
AMD SYSTEM BUS
VTT 1.25V Regulator
4 Register DDR DIMM Modules
PCI CNTRL
PCI ADDR/DATA
Block Diagram
PCI Conn 1
PCI Conn 2
IDE Secondary
USB Port 1
USB Port 2
USB Port 3
USB Port 4
Onboard
AC'97 Codec
USB
PC 2 PC
AC'97 Link
AMD 768 South Bridge
LPC
Super I/O
Keyboard SerialParallel
Mouse
Bus
BIOS
INTEL 82559ER LAN
10/100Mbps Conn.
1
PCI CNTRL
PCI ADDR/DATA
PCI Conn 3
PCI Conn 4
PCI Conn 5
Game ConnFloopy
Title
Size Document Number Rev Custom Date: Sheet of
MICRO-STAR
Block Diagram
MS-6501
2 39Tuesday, July 17, 2001
0A
Page 3
5
* 25 mils Trace on Layer 6 with GND copper around it
* Put close to every power pin
VCC3
D D
C376
0.01u
PCISTP-<21>
CPUSTOP-<21>
FP_RST-<27,33>
C C
100/133-<33,36>
SIO_CLK48<22>
OSC<21>
R335 22-REV R340 22-REV
R295 22
R616 22
C326 10p
FB16 80-0805
C371
0.01u
FB15 80-0805
1 2
VCC3
RN77
10K
1 2
3 4
5 6
7 8
RN68
10K
3 4
5 6
7 8
4
+
C354
0.01u 10u
Y3
14M-16pf-HC49S-D
R298 1M-REV
EC42
4
X1
5
X2
32
PCI_STOP_L
31
CPU_STOP_L
30
PD_L
29
SPREAD_L
28
FS2
2
FS1
1
FS0
24
24MHZ/48MHZ#
35
RSVD2
44
RSVD1
C358 330p
3422189154845
GND
6
VDD
GND
12
VDDSD
VDDREF
GND
GND
21253
C337330p
VDDAGP
VDDPCI1
VDDPCI2
GND
GND
GND
333841
C5380.01u
C339330p
VDD48
CPUCLKT2 CPUCLKC2 CPUCLKT1 CPUCLKC1 CPUCLKT0 CPUCLKC0
SDRAM_OUT
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
PCICLK_F0
SDATA
GND
GND
ICS 9248-153
47
AGP1 AGP0
USB0 SCLK
C5330.01u
U24
C5290.01u
3
2
1
Clock Synthesizer
10u
EC44
+
C5370.01u
C3730.01u
C3720.01u
CPUCLKT2
42
CPUCLKC2
43
CPUCLKT1
39
CPUCLKC1
40
CPUCLKT0
36
CPUCLKC0
37 46
17 16 14 13 11 10 8 7
20 19
23 26
27
PCICLK6 PCICLK5 PCICLK4 PCICLK3
PCICLK2
PCICLK_FB AGP1
AGP0 USB0
R435 33 C564 0.01u
R302 0
RN72 10 1 2 3 4 5 6 7 8
RN75 22
1 2 3 4 5 6 7 8
R671 22
R333 22 R332 22
R336 10 R488 10
CPUCLK2 <8>
CPUCLK-1 <6> CPUCLK1 <6> CPUCLK-0 <4> CPUCLK0 <4>
LANCLK <32> PCLK5 <19> PCLK4 <18> PCLK3 <18> PCLK2 <26>
GCLK1 <15> GCLK0 <11>
USBCLK <21> PC2PCCLK <28> SMBCLK <13,14,21,22,33> SMBDATA <13,14,21,22,33>
Length = X"
Length = X" - 1"
Length = X"
Length = X" - 2.5"
Length = X"
Length = X" Length = X" - 4.5"
(5 mil trace / 20 mil clearance)
(20/5/5/5/20)
(5 mil trace / 20 mil clearance) (5 mil trace / 20 mil clearance)
(5 mil trace / 20 mil clearance)
(5 mil trace / 20 mil clearance) (5 mil trace / 20 mil clearance)
C336
C335
22p
22p
NOPOP
NOPOP
B B
WIDTH/SPACE LENGTH CPUCLK0&CPUCLK0#: CPUCLK1&CPUCLK1#: CPUCLK2&GCLK0 X GCLK1 X-4.5 NBCLK&SBCLK PCICLK GROUP X-2.5
* X MEANS THE SHORTEST LENGTH FOR MAINTAIN PROPAGATION DELAY
* CPUCLK1'S TERMINATION CKT MUST BE PLACED NEAR TO NB
A A
5/20 5 FOR DIFF. PAIR X-1 INCH 5/20 5 FOR DIFF. PAIR X-1 INCH
5/20 5/20 5/20
X
5/20
5
FS2 FS1
0
0
0
0
1
1
1
000
1
1 1
0
0
1 1
4
*Put GND copper under Clock Gen. connect to every GND pin
CPU SDRAM
PCI AGP
FS0
133.3 33.3 66.7
1
95.0
31.67
0
100.99
33.66
115.0
38.33
0
100.7
33.57
1
103.0
34.33
105.0 35.0011 0 60.0
110.0
36.67
63.33
67.33
76.67
67.13
66.6
66.6
CPUCLKT2
CPUCLKC1 CPUCLKT1 CPUCLKC0 CPUCLKT0
SIO_PCLK SBCLK
PCICLK6 PCICLK5 PCICLK4 PCICLK3
AGP1 AGP0 USB0
Close to clock generator
3
C346 20p
CN15 20p 7 8 5 6 3 4 1 2
C845 10p
C846 10p
CN16 10p 7 8 5 6 3 4 1 2
C369 10p
C367 10p
C374 10p
NOPOP NOPOP
NOPOP
NOPOP NOPOP NOPOP
PCICLK_FB
2
R654 10 R655 10
Title
Size Document Number Rev Custom Date: Sheet of
SIO_PCLK <22> SBCLK <21>
MICRO-STAR
Clock Synthesizer
MS-6501
1
3 39Wednesday, July 25, 2001
0A
Page 4
A
B
C
D
E
C319
0.047u
100
RN80
510
VCORE
RN59
4 39Wednesday, July 25, 2001
12 34 56 78
VCORE
78 56 34 12
VCORE
R283 100
R281 100
VCORE
0A
CPU1A
P0_SDATA-0
P0_SDATA-[0..63]<8>
4 4
3 3
P0_DICLK-[0..3]<8>
2 2
P0_DIVAL-<8>
P0_DOCLK-[0..3]<8>
P0_SDATA-1 P0_SDATA-2 P0_SDATA-3 P0_SDATA-4 P0_SDATA-5 P0_SDATA-6 P0_SDATA-7 P0_SDATA-8 P0_SDATA-9 P0_SDATA-10 P0_SDATA-11 P0_SDATA-12 P0_SDATA-13 P0_SDATA-14 P0_SDATA-15 P0_SDATA-16 P0_SDATA-17 P0_SDATA-18 P0_SDATA-19 P0_SDATA-20 P0_SDATA-21 P0_SDATA-22 P0_SDATA-23 P0_SDATA-24 P0_SDATA-25 P0_SDATA-26 P0_SDATA-27 P0_SDATA-28 P0_SDATA-29 P0_SDATA-30 P0_SDATA-31 P0_SDATA-32 P0_SDATA-33 P0_SDATA-34 P0_SDATA-35 P0_SDATA-36 P0_SDATA-37 P0_SDATA-38 P0_SDATA-39 P0_SDATA-40 P0_SDATA-41 P0_SDATA-42 P0_SDATA-43 P0_SDATA-44 P0_SDATA-45 P0_SDATA-46 P0_SDATA-47 P0_SDATA-48 P0_SDATA-49 P0_SDATA-50 P0_SDATA-51 P0_SDATA-52 P0_SDATA-53 P0_SDATA-54 P0_SDATA-55 P0_SDATA-56 P0_SDATA-57 P0_SDATA-58 P0_SDATA-59 P0_SDATA-60 P0_SDATA-61 P0_SDATA-62 P0_SDATA-63
P0_DICLK-0 P0_DICLK-1 P0_DICLK-2 P0_DICLK-3
P0_DIVAL­P0_DOCLK-0
P0_DOCLK-1 P0_DOCLK-2 P0_DOCLK-3
P0_DOVAL­P0_AIN-0
P0_AIN-1 P0_AIN-2
P0_AIN-[2..14]<8>
1 1
P0_AINCLK-<8>
P0_CFWDRST<8> P0_CONNECT<8> P0_PROCRDY<8> P0_SFILLVAL-<8>
P0_AIN-3 P0_AIN-4 P0_AIN-5 P0_AIN-6 P0_AIN-7 P0_AIN-8 P0_AIN-9 P0_AIN-10 P0_AIN-11 P0_AIN-12 P0_AIN-13 P0_AIN-14
P0_CFWDRST P0_CONNECT P0_PROCRDY
P0_SFILLVAL-
AA35
W37 W35
AA33 AE37 AC33 AC37
AA37 AC35
W33
AN33 AE35
AL31 AJ29
AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31
AJ33 AJ21
AL23 AN23 AJ31
Y35 U35 U33 S37 S33
Y37
S35 Q37 Q35 N37 J33 G33 G37 E37 G35 Q33 N33 L33 N35 L37 J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15
E9
A13
C9
A9 C21 A21 E19 C19 C17 A11 A17 A15
J35 E27 E15
C37 A33 C11
SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31 SDATA32 SDATA33 SDATA34 SDATA35 SDATA36 SDATA37 SDATA38 SDATA39 SDATA40 SDATA41 SDATA42 SDATA43 SDATA44 SDATA45 SDATA46 SDATA47 SDATA48 SDATA49 SDATA50 SDATA51 SDATA52 SDATA53 SDATA54 SDATA55 SDATA56 SDATA57 SDATA58 SDATA59 SDATA60 SDATA61 SDATA62 SDATA63
SDATAINCLK0 SDATAINCLK1 SDATAINCLK2 SDATAINCLK3
SDATAINVAL SDATAOUTCLK0
SDATAOUTCLK1 SDATAOUTCLK2 SDATAOUTCLK3
SDTATOUTVAL SADDIN0
SADDIN1 SADDIN2 SADDIN3 SADDIN4 SADDIN5 SADDIN6 SADDIN7 SADDIN8 SADDIN9 SADDIN10 SADDIN11 SADDIN12 SADDIN13 SADDIN14
SADDINCLK CLKFWDRST
CONNECT PROCRDY SFILLVAL
A20M FERR
INTR
IGNNE
RESET STPCLK PWROK
PICCLK PICD0/BYPASSCLK PICD1/BYPASSCLK
COREFB-
COREFB+
CLKIN CLKIN
RSTCLK RSTCLK
K7CLKOUT K7CLKOUT
ANALOG
SYSVREFMODE
VREF_SYS
PLLBYPASS PLLBYPASSCLK PLLBYPASSCLK
PLLMON1 PLLMON2
PLLTEST
SCANCLK1 SCANCLK2
SCANINTEVAL
SCANSHIFTEN
DBRDY DBREQ
FLUSH
TRST
VID0 VID1 VID2 VID3 VID4
FID0 FID1 FID2 FID3
SCHECK0 SCHECK1 SCHECK2 SCHECK3 SCHECK4 SCHECK5 SCHECK6 SCHECK7
SADDOUT0 SADDOUT1 SADDOUT2 SADDOUT3 SADDOUT4 SADDOUT5 SADDOUT6 SADDOUT7 SADDOUT8
SADDOUT9 SADDOUT10 SADDOUT11 SADDOUT12 SADDOUT13 SADDOUT14
SADDOUTCLK
INIT
NMI SMI
ZN ZP
TCK
TDI TDO TMS
R266
AE1 AG1 AJ3 AL1 AJ1 AN3 AG3 AN5 AC1
AE3
N1 N3 N5
AG13 AG11
AN17 AL17
AN19 AL19
AL21 AN21
AJ13 AA5
W5 AC5
AE5 AJ25
AN15 AL15
AN13 AL13 AC3
S1 S5 S3 Q5
AA1 AA3 AL3
Q1 U1 U5 Q3 U3
L1 L3 L5 L7 J7
W1 W3 Y1 Y3
U37 Y33 L35 E33 E25 A31 C13 A19
J1 J3 C7 A7 E5 A5 E7 C1 C5 C3 G1 E1 A3 G5 G3
E3
PGA-D462
A20M­FERR_P0 CPUINIT­INTR IGNNE­NMI CPURST­SMI­STPCLK-
R315 100
APICD0­APICD1-
P0_COREFB­P0_COREFB
P0_CLKOUT P0_CLKOUT-
P0_VREFMODE P0_VREF_SYS
P0_ZN P0_ZP
P0_PLLBP-
P0_PLLMON1 P0_PLLMON2 P0_PLLTEST-
P0_SCANCLK1 P0_SCANCLK2 P0_SINTVAL P0_SSHIFTEN
P0_DBREQ­P0_FLUSH-
P0_CPU_TCK P0_CPU_TDI P0_CPU_TDO P0_CPU_TMS P0_CPU_TRST-
P0_VID0 P0_VID1 P0_VID2 P0_VID3 P0_VID4
P0_FID0 P0_FID1 P0_FID2 P0_FID3
P0_SCHECK-0 P0_SCHECK-1 P0_SCHECK-2 P0_SCHECK-3 P0_SCHECK-4 P0_SCHECK-5 P0_SCHECK-6 P0_SCHECK-7
P0_AOUT-2 P0_AOUT-3 P0_AOUT-4 P0_AOUT-5 P0_AOUT-6 P0_AOUT-7 P0_AOUT-8 P0_AOUT-9 P0_AOUT-10 P0_AOUT-11 P0_AOUT-12 P0_AOUT-13 P0_AOUT-14
CPUCLK0_R CPUCLK-0_R
The farest VCORE and GND
A20M- <6,21> FERR_P0 <21> CPUINIT- <6,21>
INTR <6,21>
IGNNE- <6,21> NMI <6,21>
SMI- <6,21> STPCLK- <6,21>
CPU_PG <6,27>
APICCLK
APICD0- <6,21> APICD1- <6,21>
R293 100
P0_VID0 <33> P0_VID1 <33> P0_VID2 <33> P0_VID3 <33> P0_VID4 <33>
P0_FID0 <33> P0_FID1 <33> P0_FID2 <33> P0_FID3 <33>
P0_AOUTCLK- <8>
10K
A
B
**All CPU interface are 2.5V tolerant**
APICCLK <3,6,21>
P0_COREFB- <34> P0_COREFB <34>
R285 100
AMD use 100ohm
VCORE
VCORE
RN63
78 56 34 12
100
P0_SCHECK-[0..7] <8>
P0_AOUT-[2..14] <8>
C351 4700p-REV
C
CPURST- <6,21>
INTR CPUINIT­NMI SMI-
IGNNE­CPURST­A20M­STPCLK-
P0_PLLMON1 P0_PLLMON2 P0_FLUSH­P0_PLLBP-
P0_AIN-0 P0_AIN-1
P0_DOVAL­P0_SFILLVAL-
CPUCLK0_R
CPUCLK-0_R
CPUCLK-0<3>
CPUCLK0<3>
RN76 7 8 5 6 3 4 1 2
680
RN66 1 2 3 4 5 6 7 8
680
R286 56 R284 56 R314 680 R267 680
R247 680 R253 680
R241 270 R236 270
680pC311
680pC307
P0_DBREQ-
R313 510
P0_PLLTEST-
VCORE
P0_VREFMODE
VCORE
for internal VREFSYS
R280 1K-REV
R282 270
0.5 * VCORE
P0_VREF_SYSP0_CPU_DBRDY
VREFMODE=Low=No voltage scaling
P0_SCANCLK1 P0_SSHIFTEN P0_SINTVAL P0_SCANCLK2
RN79
1 2 3 4 5 6 7 8
10K
VCORE
R276 60.4
21
R274 301
R272 60.4
21
Near socket-A
D
Title
Size Document Number Rev Custom Date: Sheet of
P0_ZN P0_ZP
P0_CLKOUT P0_CLKOUT-
* Trace lengths of CLKOUT and -CLKOUT are between 2" and 3"
MICRO-STAR
SocketA (Part 1)
R305 510
P0_CPU_TCK P0_CPU_TMS P0_CPU_TRST­P0_CPU_TDI
C320
C321
1000p
39p
R279 40.2 R278 40.2
match the transmission line
Push-Pull compensation circuit
MS-6501
E
Page 5
A
VCC3
C253
4 4
39p
2 1
Max 150mA, Design for 100mA
* 25 mils Trace/ 12 mils Space
RN55
7 8 5 6 3 4 1 2
33
C271 39p
2 1
VR6
CSK-2-SOT23-150mA
2.5V
R250 0
C281
0.01u
2
R264
3 1
0-REV
Used when spec. change
C266 39p
2 1
NOPOP
VCCA_PLL trace length from the VR1 to the PGA must be 0.75". Place al filters close to the PGA. Keep all power and signal trce away from the VR1. Place a cut in the GND plane around the VCCA_PLL regulator circuit.
2 1
C291 39p NOPOP
B
R257 10R259 0
C289 39p
2 1
Place inside CPU socket
C
P0_VCCA_PLL1P0_VCCA_PLL
Power Up Strappings :
D
E
AD[3:0] => CPU Clock Multiplier
0000 3 0001 3.5
C272 39p
2 1
0010 4 0011 4.5 0100 5 0101 5.5 0110 6 0111 6.5
1000 7 1001 7.5 1010 8 1011 8.5 1100 9 1101 9.5 1110 10 1111 Reserved
B12B8B4
AJ5
VCC_CORE97
VCC_CORE98
VCC_CORE99
VCC_CORE100
VCC_CORE101
VSS99
VSS100
VSS101
VSS102
VSS103
AM4
AK6
P0_VCCA_PLL
AC7
BP0_CUT BP1_CUT BP2_CUT BP3_CUT
VSS104
AM6
VCC_Z
NC1 NC2 NC3 NC6 NC7 NC8
NC9 NC10 NC11 NC12 NC13 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC42 NC43 NC44 NC45
VSS_Z
AE7
AJ23
VCC_A
0~100 mA,
2.25~2.75V
CPU1B
PGA-D462
AA31 AC31 AE31 AG23 AG25 AG31 AG5 AJ11 AJ15 AJ17 AJ19 AJ27 AL11 AN11 AN9 G11 G13 G27 G29 G31 J31 J5 L31 N31 Q31 S31 S7 U31 U7 W31 W7 Y31 Y5 AG19 G21 AG21 G19
AN27 AL27 AN25 AL25
P0_THERMADA <22> P0_THERMADC <22>
P0_BP0 <33> P0_BP1 <33> P0_BP2 <33> P0_BP3 <33>
The presence pin is only connected to GND through the processor
VCORE
3 3
2 2
1 1
AD30
AD8 AF10 AF28 AF30 AF32
AF6
AF8 AH30
AH8
AK8
AM8
AN7
G25
G17
AG7 AG15 AG29
AO1
AO2
AO3
AO4
XX1
XX2
AJ9 AL9 F30 H10
H28 H30 H32
K30 AJ7
AL7
F8
H6 H8
K8
G9 N7 Y7
VCC_SRAM1 VCC_SRAM2 VCC_SRAM3 VCC_SRAM4 VCC_SRAM5 VCC_SRAM6 VCC_SRAM7 VCC_SRAM8 VCC_SRAM9 VCC_SRAM11 VCC_SRAM13 VCC_SRAM14 VCC_SRAM16 VCC_SRAM17 VCC_SRAM19 VCC_SRAM20 VCC_SRAM21 VCC_SRAM22 VCC_SRAM23 VCC_SRAM24 VCC_SRAM25 VCC_SRAM26 VCC_SRAM27 VCC_SRAM28 VCC_SRAM29 VCC_SRAM30 VCC_SRAM31
KEY4 KEY6 KEY8 KEY10 KEY12 KEY14 KEY16 KEY18
EMI EMI EMI EMI EMI EMI
H12
H16
H20
H24M8P30R8T30V8X30Z8AB30
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
VSS1
VSS2
VSS3
VSS4
VSS5
H14
H18
H22
H26
M30P8R30T8V30X8Z30
VCC_CORE6
VCC_CORE7
VCC_CORE8
VCC_CORE9
VSS6
VSS7
VSS8
VSS9
AF14
AF18
VCC_CORE10
VCC_CORE11
VCC_CORE12
VCC_CORE13
VCC_CORE14
VSS10
VSS11
VSS12
VSS13
VSS14
AB8
AF12
AF16
AF22
AF26
AM34
AK36
VCC_CORE15
VCC_CORE16
VCC_CORE17
VCC_CORE18
VSS15
VSS16
VSS17
VSS18
AF20
AF24
AM36
AK32
AK34
AK30
AK26
AK22
VCC_CORE19
VCC_CORE20
VCC_CORE21
VCC_CORE22
VSS19
VSS20
VSS21
VSS22
AK28
AK24
AK20
AK16
AK18
AK14
AK10
AL5
VCC_CORE23
VCC_CORE24
VCC_CORE25
VCC_CORE26
VSS23
VSS25
VSS26
VSS27
AK12
AK4
AK2
AH36
AH26
AM30
AH22
AH18
VCC_CORE27
VCC_CORE28
VCC_CORE29
VCC_CORE30
VSS28
VSS29
VSS30
VSS31
AM32
AH34
AH32
AH28
AH14
AH10
AH4
AH2
VCC_CORE31
VCC_CORE32
VCC_CORE33
VCC_CORE34
VSS32
VSS33
VSS34
VSS35
AH24
AH20
AH16
AH12
AF36
AF34
AD6
AM26
VCC_CORE35
VCC_CORE36
VCC_CORE37
VCC_CORE38
VSS37
VSS38
VSS39
VSS40
AF4
AF2
AD36
AD34
AD4
AD2
AB36
AB34
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VSS41
VSS42
VSS43
VSS44
AD32
AB6
AB4
AB2
AB32Z6Z4Z2X36
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VSS45
VSS46
VSS47
VSS48
Z36
Z34
Z32X6AM28X4X2
X34
AM22
X32V6V4V2T36
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VSS49
VSS50
VSS51
VSS52
VSS53
V36
V34
T34
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VSS54
VSS55
VSS56
VSS57
V32T6T4T2R36
T32R6R4R2AM18
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VSS58
VSS59
VSS60
VSS61
VSS62
R34
AM24
R32P6P4P2M36
P36
P34
P32M4M6M2K36
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VSS63
VSS64
VSS65
VSS66
M34
K34
K32H4H2
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VSS67
VSS68
VSS69
VSS70
VSS71
M32K6K4K2AM20
AM14
F36
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VSS72
VSS73
VSS74
VSS75
H36
H34
F26
F22
F34
F32
F28
F24
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VSS76
VSS77
VSS78
VSS79
F18
F14
F10F6F4F2AM16
F20
F16
F12
D32
VCC_CORE78
VCC_CORE79
VCC_CORE80
VCC_CORE81
VSS80
VSS81
VSS82
VSS83
D36
D28
AM10
D24
D20
VCC_CORE82
VCC_CORE83
VCC_CORE84
VCC_CORE85
VSS84
VSS85
VSS86
VSS87
D34
D30
D26
D22
D16
D12D8D4D2B36
VCC_CORE86
VCC_CORE87
VCC_CORE88
VCC_CORE89
VSS88
VSS89
VSS90
VSS91
D18
D14
D10D6B34
B32
AM2
B28
VCC_CORE90
VCC_CORE91
VCC_CORE92
VCC_CORE93
VCC_CORE94
VSS92
VSS93
VSS94
VSS95
VSS96
AM12
B30
B26
B22
B24
B20
B16
VCC_CORE95
VCC_CORE96
VSS97
VSS98
B18
B14
B10B6B2
Title
Size Document Number Rev Custom
A
B
C
D
Date: Sheet of
MICRO-STAR
SocketA (Part 2)
MS-6501
E
5 39Wednesday, July 25, 2001
0A
Page 6
A
B
C
D
E
C141
0.047u
100
RN31
510
R484 160R487
VCORE
RN36
6 39Wednesday, July 25, 2001
12 34 56 78
0.01u
VCORE
VCORE
78 56 34 12
VCORE
C608
R112 100
R117 100
0A
CPU2A
P1_SDATA-0
P1_SDATA-[0..63]<9>
4 4
3 3
P1_DICLK-[0..3]<9>
2 2
P1_DIVAL-<9>
P1_DOCLK-[0..3]<9>
P1_SDATA-1 P1_SDATA-2 P1_SDATA-3 P1_SDATA-4 P1_SDATA-5 P1_SDATA-6 P1_SDATA-7 P1_SDATA-8 P1_SDATA-9 P1_SDATA-10 P1_SDATA-11 P1_SDATA-12 P1_SDATA-13 P1_SDATA-14 P1_SDATA-15 P1_SDATA-16 P1_SDATA-17 P1_SDATA-18 P1_SDATA-19 P1_SDATA-20 P1_SDATA-21 P1_SDATA-22 P1_SDATA-23 P1_SDATA-24 P1_SDATA-25 P1_SDATA-26 P1_SDATA-27 P1_SDATA-28 P1_SDATA-29 P1_SDATA-30 P1_SDATA-31 P1_SDATA-32 P1_SDATA-33 P1_SDATA-34 P1_SDATA-35 P1_SDATA-36 P1_SDATA-37 P1_SDATA-38 P1_SDATA-39 P1_SDATA-40 P1_SDATA-41 P1_SDATA-42 P1_SDATA-43 P1_SDATA-44 P1_SDATA-45 P1_SDATA-46 P1_SDATA-47 P1_SDATA-48 P1_SDATA-49 P1_SDATA-50 P1_SDATA-51 P1_SDATA-52 P1_SDATA-53 P1_SDATA-54 P1_SDATA-55 P1_SDATA-56 P1_SDATA-57 P1_SDATA-58 P1_SDATA-59 P1_SDATA-60 P1_SDATA-61 P1_SDATA-62 P1_SDATA-63
P1_DICLK-0 P1_DICLK-1 P1_DICLK-2 P1_DICLK-3
P1_DIVAL­P1_DOCLK-0
P1_DOCLK-1 P1_DOCLK-2 P1_DOCLK-3
P1_DOVAL­P1_AIN-0
P1_AIN-1 P1_AIN-2
P1_AIN-[2..14]<9>
1 1
P1_AINCLK-<9>
P1_CFWDRST<9> P1_CONNECT<9> P1_PROCRDY<9> P1_SFILLVAL-<9>
P1_AIN-3 P1_AIN-4 P1_AIN-5 P1_AIN-6 P1_AIN-7 P1_AIN-8 P1_AIN-9 P1_AIN-10 P1_AIN-11 P1_AIN-12 P1_AIN-13 P1_AIN-14
P1_CFWDRST P1_CONNECT P1_PROCRDY P1_SFILLVAL-
AA35
W37 W35
AA33 AE37 AC33 AC37
AA37 AC35
W33
AN33 AE35
AL31 AJ29
AL29 AG33 AJ37 AL35 AE33 AJ35 AG37 AL33 AN37 AL37 AG35 AN29 AN35 AN31
AJ33 AJ21
AL23 AN23 AJ31
Y35 U35 U33 S37 S33
Y37
S35 Q37 Q35 N37 J33 G33 G37 E37 G35 Q33 N33 L33 N35 L37 J37 A37 E35 E31 E29 A27 A25 E21 C23 C27 A23 A35 C35 C33 C31 A29 C29 E23 C25 E17 E13 E11 C15
E9
A13
C9
A9 C21 A21 E19 C19 C17 A11 A17 A15
J35 E27 E15
C37 A33 C11
SDATA0 SDATA1 SDATA2 SDATA3 SDATA4 SDATA5 SDATA6 SDATA7 SDATA8 SDATA9 SDATA10 SDATA11 SDATA12 SDATA13 SDATA14 SDATA15 SDATA16 SDATA17 SDATA18 SDATA19 SDATA20 SDATA21 SDATA22 SDATA23 SDATA24 SDATA25 SDATA26 SDATA27 SDATA28 SDATA29 SDATA30 SDATA31 SDATA32 SDATA33 SDATA34 SDATA35 SDATA36 SDATA37 SDATA38 SDATA39 SDATA40 SDATA41 SDATA42 SDATA43 SDATA44 SDATA45 SDATA46 SDATA47 SDATA48 SDATA49 SDATA50 SDATA51 SDATA52 SDATA53 SDATA54 SDATA55 SDATA56 SDATA57 SDATA58 SDATA59 SDATA60 SDATA61 SDATA62 SDATA63
SDATAINCLK0 SDATAINCLK1 SDATAINCLK2 SDATAINCLK3
SDATAINVAL SDATAOUTCLK0
SDATAOUTCLK1 SDATAOUTCLK2 SDATAOUTCLK3
SDTATOUTVAL SADDIN0
SADDIN1 SADDIN2 SADDIN3 SADDIN4 SADDIN5 SADDIN6 SADDIN7 SADDIN8 SADDIN9 SADDIN10 SADDIN11 SADDIN12 SADDIN13 SADDIN14
SADDINCLK CLKFWDRST
CONNECT PROCRDY SFILLVAL
A20M FERR
INTR
IGNNE
RESET STPCLK PWROK
PICCLK PICD0/BYPASSCLK PICD1/BYPASSCLK
COREFB-
COREFB+
CLKIN CLKIN
RSTCLK RSTCLK
K7CLKOUT K7CLKOUT
ANALOG
SYSVREFMODE
VREF_SYS
PLLBYPASS PLLBYPASSCLK PLLBYPASSCLK
PLLMON1 PLLMON2
PLLTEST
SCANCLK1
SCANCLK2 SCANINTEVAL SCANSHIFTEN
DBRDY DBREQ
FLUSH
TRST
VID0 VID1 VID2 VID3 VID4
FID0 FID1 FID2 FID3
SCHECK0 SCHECK1 SCHECK2 SCHECK3 SCHECK4 SCHECK5 SCHECK6 SCHECK7
SADDOUT0 SADDOUT1 SADDOUT2 SADDOUT3 SADDOUT4 SADDOUT5 SADDOUT6 SADDOUT7 SADDOUT8
SADDOUT9 SADDOUT10 SADDOUT11 SADDOUT12 SADDOUT13 SADDOUT14
SADDOUTCLK
INIT
NMI SMI
ZN ZP
TCK
TDI TDO TMS
R156 10K
A
B
AE1 AG1 AJ3 AL1 AJ1 AN3 AG3 AN5 AC1
AE3
N1 N3 N5
AG13 AG11
AN17 AL17
AN19 AL19
AL21 AN21
AJ13 AA5
W5 AC5
AE5 AJ25
AN15 AL15
AN13 AL13 AC3
S1 S5 S3 Q5
AA1 AA3 AL3
Q1 U1 U5 Q3 U3
L1 L3 L5 L7 J7
W1 W3 Y1 Y3
U37 Y33 L35 E33 E25 A31 C13 A19
J1 J3 C7 A7 E5 A5 E7 C1 C5 C3 G1 E1 A3 G5 G3
E3
PGA-D462
A20M­FERR_P1 CPUINIT­INTR IGNNE­NMI CPURST­SMI­STPCLK-
R62 100
APICD0­APICD1-
P1_COREFB­P1_COREFB
CPUCLK1_R CPUCLK-1_R
P1_CLKOUT P1_CLKOUT-
P1_VREFMODE P1_VREF_SYS
P1_ZN P1_ZP
P1_PLLBP-
P1_PLLMON1 P1_PLLMON2 P1_PLLTEST-
P1_SCANCLK1 P1_SCANCLK2 P1_SINTVAL P1_SSHIFTEN
P1_CPU_DBRDY P1_DBREQ­P1_FLUSH-
P1_CPU_TCK P1_CPU_TDI
P1_CPU_TDO
P1_CPU_TMS P1_CPU_TRST-
P1_SCHECK-0 P1_SCHECK-1 P1_SCHECK-2 P1_SCHECK-3 P1_SCHECK-4 P1_SCHECK-5 P1_SCHECK-6 P1_SCHECK-7
P1_AOUT-2 P1_AOUT-3 P1_AOUT-4 P1_AOUT-5 P1_AOUT-6 P1_AOUT-7 P1_AOUT-8 P1_AOUT-9 P1_AOUT-10 P1_AOUT-11 P1_AOUT-12 P1_AOUT-13 P1_AOUT-14
A20M- <4,21> FERR_P1 <21> CPUINIT- <4,21>
INTR <4,21>
IGNNE- <4,21> NMI <4,21>
SMI- <4,21> STPCLK- <4,21>
**All CPU interface are 2.5V tolerant**
CPU_PG <4,27>
APICCLK
APICD0- <4,21> APICD1- <4,21>
The farest VCORE and GND
R97 100
VCORE
RN33
R103 100
78 56 34 12
APICCLK <3,4,21>
P1_COREFB- <34> P1_COREFB <34>
VCORE
100
P1_SCHECK-[0..7] <9>
P1_AOUT-[2..14] <9>
P1_AOUTCLK- <9>
CPURST- <4,21>
C
P1_PLLMON1 P1_PLLMON2 P1_FLUSH­P1_PLLBP-
P1_AIN-0 P1_AIN-1
P1_DOVAL­P1_SFILLVAL-
CPUCLK1_R
CPUCLK-1_R
CPUCLK-1<3>
CPUCLK1<3>
R101 56 R95 56 R89 680 R157 680
R172 680 R173 680
R180 270 R406 270
Reserved
680pC154
680pC158
P1_DBREQ-
R75 510
VCC3
RN187 1 2 3 4 5 6 7 8
33
2
3 1
VR8
CSK-2-SOT23-150mA
R486 0 C607
0.01u
0-REV
P1_PLLTEST-
APICCLK
P1_CPU_TCK P1_CPU_TMS P1_CPU_TRST­P1_CPU_TDI
R485
62
R81 510
R483
160
APICD0­APICD1-
VCORE
for internal VREFSYS
R118 1K
R113 270
P1_SCANCLK1 P1_SSHIFTEN P1_SINTVAL P1_SCANCLK2
RN30
7 8 5 6 3 4 1 2
VCORE
P1_VREFMODE
VREFMODE=Low=No voltage scaling
10K
VCORE
R136 60.4
21
R140 301
R143 60.4
21
Near socket-A
D
Title
Size Document Number Rev Custom Date: Sheet of
0.5 * VCORE
P1_VREF_SYS
C142
C143
1000p
39p
P1_ZN
R119 40.2
P1_ZP
R120 40.2
match the transmission line
Push-Pull compensation circuit
P1_CLKOUT P1_CLKOUT-
* Trace lengths of CLKOUT and -CLKOUT are between 2" and 3"
MICRO-STAR
SocketA (Part 1)
MS-6501
E
Page 7
A
B
C
D
E
VCC3
7 8 5 6 3 4 1 2
4 4
C122 39p
2 1
Max 150mA, Design for 100mA
* 25 mils Trace/ 12 mils Space
RN32
33
C133 39p
2 1
3 1
VR5
CSK-2-SOT23-150mA
R102 0
2
R122 0-REV
C134
0.01u
Used when spec. change
2.5V
C144 39p
2 1
NOPOP
VCCA_PLL trace length from the VR1 to the PGA must be 0.75".
C175 39p
2 1
NOPOP
R167 10R114 0
C173 39p
2 1
Place inside CPU socket
P1_VCCA_PLL1P1_VCCA_PLL
C189 39p
2 1
Power Up Strappings :
AD[3:0] => CPU Clock Multiplier
0000 3 0001 3.5 0010 4 0011 4.5 0100 5 0101 5.5 0110 6 0111 6.5
1000 7 1001 7.5 1010 8 1011 8.5 1100 9 1101 9.5 1110 10 1111 Reserved
Place al filters close to the PGA.
Keep all power and signal trce away from the VR1.
Place a cut in the GND plane around the VCCA_PLL regulator circuit.
AJ5
VCC_CORE98
VCC_CORE99
VCC_CORE100
VCC_CORE101
BP0_CUT BP1_CUT BP2_CUT BP3_CUT
VSS100
VSS101
VSS102
VSS103
VSS104
AM4
AK6
AM6
D
P1_VCCA_PLL
0~100 mA,
2.25~2.75V
CPU2B
AC7
AJ23
PGA-D462
VCC_Z
VCC_A
AA31
NC1
AC31
NC2
AE31
NC3
AG23
NC6
AG25
NC7
AG31
NC8
AG5
NC9
AJ11
NC10
AJ15
NC11
AJ17
NC12
AJ19
NC13
AJ27
NC15
AL11
NC16
AN11
NC17
AN9
NC18
G11
NC19
G13
NC20
G27
NC21
G29
NC22
G31
NC23
J31
NC24
J5
NC25
L31
NC27
N31
NC28
Q31
NC29
S31
NC30
S7
NC31
U31
NC32
U7
NC33
W31
NC34
W7
NC35
Y31
NC36
Y5
NC37
AG19
NC42
G21
NC43
AG21
NC44
G19
NC45
AN27 AL27 AN25 AL25
VSS_Z
AE7
P1_THERMADA <22> P1_THERMADC <22>
P1_BP0 <33> P1_BP1 <33> P1_BP2 <33> P1_BP3 <33>
MICRO-STAR
Title
Size Document Number Rev Custom Date: Sheet of
SocketA (Part 2)
MS-6501
E
7 39Wednesday, July 25, 2001
0A
VCORE
3 3
H12
H16
H20
H24M8P30R8T30V8X30Z8AB30
VCC_CORE1
VCC_CORE2
VCC_CORE3
VCC_CORE4
VCC_CORE5
H14
VSS1
H18
VSS2
H22
A
VCC_CORE6
VSS3
VSS4
VSS5
VSS6
H26
M30P8R30T8V30X8Z30
AD30
VCC_SRAM1
AD8
VCC_SRAM2
AF10
VCC_SRAM3
AF28
VCC_SRAM4
AF30
VCC_SRAM5
AF32
VCC_SRAM6
AF6
VCC_SRAM7
AF8
VCC_SRAM8
AH30
VCC_SRAM9
AH8
VCC_SRAM11
AJ9
VCC_SRAM13
AK8
VCC_SRAM14
AL9
VCC_SRAM16
AM8
VCC_SRAM17
2 2
1 1
F30 H10
H28 H30 H32
K30 AJ7
AL7
AN7 G25
G17
AG7 AG15 AG29
AO1
AO2
AO3
AO4
XX1
XX2
F8
H6 H8
K8
G9 N7
Y7
VCC_SRAM19 VCC_SRAM20 VCC_SRAM21 VCC_SRAM22 VCC_SRAM23 VCC_SRAM24 VCC_SRAM25 VCC_SRAM26 VCC_SRAM27 VCC_SRAM28 VCC_SRAM29 VCC_SRAM30 VCC_SRAM31
KEY4 KEY6 KEY8 KEY10 KEY12 KEY14 KEY16 KEY18
EMI EMI EMI EMI EMI EMI
VCC_CORE7
VCC_CORE8
VCC_CORE9
VCC_CORE10
VCC_CORE11
VSS7
VSS8
VSS9
VSS10
VSS11
AF14
AF18
AF22
VCC_CORE12
VCC_CORE13
VCC_CORE14
VCC_CORE15
VSS12
VSS13
VSS14
VSS15
AB8
AF12
AF16
AF20
AF26
AM34
AK36
AK34
AK30
VCC_CORE16
VCC_CORE17
VCC_CORE18
VCC_CORE19
VSS16
VSS17
VSS18
VSS19
AF24
AM36
AK32
AK28
AK24
AK26
AK22
AK18
AK14
VCC_CORE20
VCC_CORE21
VCC_CORE22
VCC_CORE23
VCC_CORE24
VSS20
VSS21
VSS22
VSS23
VSS25
AK20
AK16
AK12
AK4
AK10
AL5
AH26
AM30
VCC_CORE25
VCC_CORE26
VCC_CORE27
VCC_CORE28
VSS26
VSS27
VSS28
VSS29
AK2
AH36
AM32
AH34
AH22
AH18
AH14
AH10
AH4
VCC_CORE29
VCC_CORE30
VCC_CORE31
VCC_CORE32
VSS30
VSS31
VSS32
VSS33
AH32
AH28
AH24
AH20
AH16
AH2
AF36
AF34
AD6
AM26
VCC_CORE33
VCC_CORE34
VCC_CORE35
VCC_CORE36
VCC_CORE37
VSS34
VSS35
VSS37
VSS38
VSS39
AH12
AF4
AF2
AD36
AD34
B
AD4
AD2
AB36
AB34
VCC_CORE38
VCC_CORE39
VCC_CORE40
VCC_CORE41
VCC_CORE42
VSS40
VSS41
VSS42
VSS43
VSS44
AD32
AB6
AB4
AB2
AB32Z6Z4Z2X36
VCC_CORE43
VCC_CORE44
VCC_CORE45
VCC_CORE46
VSS45
VSS46
VSS47
VSS48
Z36
Z34
Z32X6AM28X4X2
X34
AM22
X32V6V4V2T36
VCC_CORE47
VCC_CORE48
VCC_CORE49
VCC_CORE50
VCC_CORE51
VSS49
VSS50
VSS51
VSS52
VSS53
V36
V34
T34
T32R6R4R2AM18
VCC_CORE52
VCC_CORE53
VCC_CORE54
VCC_CORE55
VSS54
VSS55
VSS56
VSS57
V32T6T4T2R36
VCC_CORE56
VCC_CORE57
VCC_CORE58
VCC_CORE59
VCC_CORE60
VSS58
VSS59
VSS60
VSS61
VSS62
R34
AM24
R32P6P4P2M36
P36
P34
P32M4M6M2K36
VCC_CORE61
VCC_CORE62
VCC_CORE63
VCC_CORE64
VSS63
VSS64
VSS65
VSS66
M34
M32K6K4K2AM20
K34
K32H4H2
VCC_CORE65
VCC_CORE66
VCC_CORE67
VCC_CORE68
VCC_CORE69
VSS67
VSS68
VSS69
VSS70
VSS71
C
AM14
F36
F34
VCC_CORE70
VCC_CORE71
VCC_CORE72
VCC_CORE73
VSS72
VSS73
VSS74
VSS75
H36
H34
F26
F22
F18
F32
F28
F24
F20
VCC_CORE74
VCC_CORE75
VCC_CORE76
VCC_CORE77
VCC_CORE78
VSS76
VSS77
VSS78
VSS79
VSS80
F14
F10F6F4F2AM16
F16
F12
D32
D28
AM10
VCC_CORE79
VCC_CORE80
VCC_CORE81
VCC_CORE82
VSS81
VSS82
VSS83
VSS84
D36
D34
D30
D24
D20
D16
D12D8D4D2B36
VCC_CORE83
VCC_CORE84
VCC_CORE85
VCC_CORE86
VCC_CORE87
VSS85
VSS86
VSS87
VSS88
VSS89
D26
D22
D18
D14
VCC_CORE88
VCC_CORE89
VCC_CORE90
VCC_CORE91
VSS90
VSS91
VSS92
VSS93
D10D6B34
AM12
B32
AM2
B28
B24
VCC_CORE92
VCC_CORE93
VCC_CORE94
VCC_CORE95
VSS94
VSS95
VSS96
VSS97
B30
B26
B22
B18
B20
B16
B12B8B4
VCC_CORE96
VCC_CORE97
VSS98
VSS99
B14
B10B6B2
Page 8
5
D D
BELONG TO CLKFWD GROUP[SADDIN] MATCH W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP[SADDOUT] MATCH
C C
W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP;MATCHED TO INDIVIDUAL CLKFWD GROUP
RESPECTIVELY.[SDATA0], [SDATA1], [SDATA2],[SDATA3] W/IN+/-50MILS OF GROUP
B B
P0_AIN-[2..14]<4>
--------------------------------
P0_AOUT-[2..14]<4>
--------------------------------
P0_SCHECK-[0..7]<4>
----------------------
P0_DICLK-[0..3]<4>
P0_DOCLK-[0..3]<4>
4
System Bus 0
P0_CFWDRST<4> P0_CONNECT<4> P0_PROCRDY<4> CPUCLK2<3>
P0_AINCLK-<4>
P0_AOUTCLK-<4>
P0_DIVAL-<4>
P0_SFILLVAL-<4>
P0_CFWDRST P0_CONNECT P0_PROCRDY CPUCLK2
P0_AIN-2 P0_AIN-3 P0_AIN-4 P0_AIN-5 P0_AIN-6 P0_AIN-7 P0_AIN-8 P0_AIN-9 P0_AIN-10 P0_AIN-11 P0_AIN-12 P0_AIN-13 P0_AIN-14
P0_AINCLK-
P0_AOUT-2 P0_AOUT-3 P0_AOUT-4 P0_AOUT-5 P0_AOUT-6 P0_AOUT-7 P0_AOUT-8 P0_AOUT-9 P0_AOUT-10 P0_AOUT-11 P0_AOUT-12 P0_AOUT-13 P0_AOUT-14
P0_AOUTCLK-
P0_SCHECK-0 P0_SCHECK-1 P0_SCHECK-2 P0_SCHECK-3 P0_SCHECK-4 P0_SCHECK-5 P0_SCHECK-6 P0_SCHECK-7
P0_DICLK-0 P0_DICLK-1 P0_DICLK-2 P0_DICLK-3
P0_DIVAL­P0_DOCLK-0
P0_DOCLK-1 P0_DOCLK-2 P0_DOCLK-3
U23A
AC5
P0_CLKFWDRST
AC4
P0_CONNECT
AC6
P0_PROCRDY
AH20
SYSCLK
Y4
P0_SADDIN2#
AA2
P0_SADDIN3#
AA6
P0_SADDIN4#
Y5
P0_SADDIN5#
AA4
P0_SADDIN6#
AA3
P0_SADDIN7#
AA5
P0_SADDIN8#
AB3
P0_SADDIN9#
AB5
P0_SADDIN10#
Y6
P0_SADDIN11#
AD1
P0_SADDIN12#
AC3
P0_SADDIN13#
AC1
P0_SADDIN14#
AA7
P0_SADDINCLK#
G1
P0_SADDOUT2#
H2
P0_SADDOUT3#
G3
P0_SADDOUT4#
F4
P0_SADDOUT5#
H4
P0_SADDOUT6#
E1
P0_SADDOUT7#
F3
P0_SADDOUT8#
F2
P0_SADDOUT9#
F5
P0_SADDOUT10#
G5
P0_SADDOUT11#
F1
P0_SADDOUT12#
E2
P0_SADDOUT13#
D1
P0_SADDOUT14#
E3
P0_SADDOUTCLK#
V7
P0_SCHECK0#
V8
P0_SCHECK1#
P8
P0_SCHECK2#
T1
P0_SCHECK3#
N7
P0_SCHECK4#
N1
P0_SCHECK5#
J3
P0_SCHECK6#
K3
P0_SCHECK7#
U5
P0_SDATAINCLK0#
R1
P0_SDATAINCLK1#
M1
P0_SDATAINCLK2#
H3
P0_SDATAINCLK3#
AB1
P0_SDATAINVALID#
W5
P0_SDATAOUTCLK0#
R8
P0_SDATAOUTCLK1#
N5
P0_SDATAOUTCLK2#
H1
P0_SDATAOUTCLK3#
J8
P0_SYSFILLVALID#
AMD-AMD762
AMD-762
3
P0_SDATA0# P0_SDATA1# P0_SDATA2# P0_SDATA3# P0_SDATA4# P0_SDATA5# P0_SDATA6# P0_SDATA7# P0_SDATA8#
P0_SDATA9# P0_SDATA10# P0_SDATA11# P0_SDATA12# P0_SDATA13# P0_SDATA14# P0_SDATA15# P0_SDATA16# P0_SDATA17# P0_SDATA18# P0_SDATA19# P0_SDATA20# P0_SDATA21# P0_SDATA22# P0_SDATA23# P0_SDATA24# P0_SDATA25# P0_SDATA26# P0_SDATA27# P0_SDATA28# P0_SDATA29# P0_SDATA30# P0_SDATA31# P0_SDATA32# P0_SDATA33# P0_SDATA34# P0_SDATA35# P0_SDATA36# P0_SDATA37# P0_SDATA38# P0_SDATA39# P0_SDATA40# P0_SDATA41# P0_SDATA42# P0_SDATA43# P0_SDATA44# P0_SDATA45# P0_SDATA46# P0_SDATA47# P0_SDATA48# P0_SDATA49# P0_SDATA50# P0_SDATA51# P0_SDATA52# P0_SDATA53# P0_SDATA54# P0_SDATA55# P0_SDATA56# P0_SDATA57# P0_SDATA58# P0_SDATA59# P0_SDATA60# P0_SDATA61# P0_SDATA62# P0_SDATA63#
P0_VREF
W3 V4 V3 V5 V6 U4 U3 U8 Y1 Y3 AA1 Y7 W1 W7 Y2 U6 U7 R7 R6 R5 R3 R4 R2 U2 T7 V1 T5 V2 T3 U1 P6 P1 P2 P4 M8 M6 L3 L7 M4 L6 P7 P5 N3 P3 M5 M7 L5 M3 K7 J6 J7 K5 J4 J2 H6 H5 M2 L4 L2 L1 K1 H7 J5 J1
AC2
P0_SDATA-0 P0_SDATA-1 P0_SDATA-2 P0_SDATA-3 P0_SDATA-4 P0_SDATA-5 P0_SDATA-6 P0_SDATA-7 P0_SDATA-8 P0_SDATA-9 P0_SDATA-10 P0_SDATA-11 P0_SDATA-12 P0_SDATA-13 P0_SDATA-14 P0_SDATA-15 P0_SDATA-16 P0_SDATA-17 P0_SDATA-18 P0_SDATA-19 P0_SDATA-20 P0_SDATA-21 P0_SDATA-22 P0_SDATA-23 P0_SDATA-24 P0_SDATA-25 P0_SDATA-26 P0_SDATA-27 P0_SDATA-28 P0_SDATA-29 P0_SDATA-30 P0_SDATA-31 P0_SDATA-32 P0_SDATA-33 P0_SDATA-34 P0_SDATA-35 P0_SDATA-36 P0_SDATA-37 P0_SDATA-38 P0_SDATA-39 P0_SDATA-40 P0_SDATA-41 P0_SDATA-42 P0_SDATA-43 P0_SDATA-44 P0_SDATA-45 P0_SDATA-46 P0_SDATA-47 P0_SDATA-48 P0_SDATA-49 P0_SDATA-50 P0_SDATA-51 P0_SDATA-52 P0_SDATA-53 P0_SDATA-54 P0_SDATA-55 P0_SDATA-56 P0_SDATA-57 P0_SDATA-58 P0_SDATA-59 P0_SDATA-60 P0_SDATA-61 P0_SDATA-62 P0_SDATA-63
P0_S2K_VREF
2
P0_SDATA-[0..63] <4>
+12V
NBFAN1
2 1
D1x2-WH
1
VCC2_5
R408
U3_X
_
100
R410 150
CPUCLK2
Put these two res. very close to N.B.
Set S2K_VREF to 50% of VCORE
P0_S2K_VREF
C265
C270
0.047u
0.039u
VCORE
R248 100
R251 100
A A
Title
Size Document Number Rev B
5
4
3
2
Date: Sheet of
North Bridge AMD762-CPU0
MICRO-STAR
MS-6501
1
8 39Monday, July 23, 2001
0A
Page 9
5
D D
BELONG TO CLKFWD GROUP[SADDIN] MATCH W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP[SADDOUT] MATCH
C C
W/IN +/-50MILS OF GROUP 5/10, CLK:5/20
BELONG TO CLKFWD GROUP;MATCHED TO INDIVIDUAL CLKFWD GROUP
RESPECTIVELY.[SDATA0], [SDATA1], [SDATA2],[SDATA3] W/IN+/-50MILS OF GROUP
B B
P1_AIN-[2..14]<6>
--------------------------------
P1_AOUT-[2..14]<6>
--------------------------------
P1_SCHECK-[0..7]<6>
----------------------
P1_DICLK-[0..3]<6>
P1_DOCLK-[0..3]<6>
4
P1_CFWDRST<6> P1_CONNECT<6> P1_PROCRDY<6>
P1_AINCLK-<6>
P1_AOUTCLK-<6>
P1_DIVAL-<6>
P1_SFILLVAL-<6>
P1_CFWDRST P1_CONNECT P1_PROCRDY
P1_AIN-2 P1_AIN-3 P1_AIN-4 P1_AIN-5 P1_AIN-6 P1_AIN-7 P1_AIN-8 P1_AIN-9 P1_AIN-10 P1_AIN-11 P1_AIN-12 P1_AIN-13 P1_AIN-14
P1_AINCLK-
P1_AOUT-2 P1_AOUT-3 P1_AOUT-4 P1_AOUT-5 P1_AOUT-6 P1_AOUT-7 P1_AOUT-8 P1_AOUT-9 P1_AOUT-10 P1_AOUT-11 P1_AOUT-12 P1_AOUT-13 P1_AOUT-14
P1_AOUTCLK-
P1_SCHECK-0 P1_SCHECK-1 P1_SCHECK-2 P1_SCHECK-3 P1_SCHECK-4 P1_SCHECK-5 P1_SCHECK-6 P1_SCHECK-7
P1_DICLK-0 P1_DICLK-1 P1_DICLK-2 P1_DICLK-3
P1_DIVAL­P1_DOCLK-0
P1_DOCLK-1 P1_DOCLK-2 P1_DOCLK-3
P1_SFILLVAL-
U23B
AL19
P1_CLKFWDRST
AJ19
P1_CONNECT
AE19
P1_PROCRDY
AG17
P1_SADDIN2#
AH18
P1_SADDIN3#
AL18
P1_SADDIN4#
AL17
P1_SADDIN5#
AF17
P1_SADDIN6#
AG16
P1_SADDIN7#
AG18
P1_SADDIN8#
AD17
P1_SADDIN9#
AK18
P1_SADDIN10#
AK17
P1_SADDIN11#
AG19
P1_SADDIN12#
AE18
P1_SADDIN13#
AF18
P1_SADDIN14#
AJ18
P1_SADDINCLK#
AJ2
P1_SADDOUT2#
AK3
P1_SADDOUT3#
AE3
P1_SADDOUT4#
AG3
P1_SADDOUT5#
AF3
P1_SADDOUT6#
AD7
P1_SADDOUT7#
AJ3
P1_SADDOUT8#
AF2
P1_SADDOUT9#
AD5
P1_SADDOUT10#
AD6
P1_SADDOUT11#
AF1
P1_SADDOUT12#
AH1
P1_SADDOUT13#
AG2
P1_SADDOUT14#
AG1
P1_SADDOUTCLK#
AG14
P1_SCHECK0#
AL15
P1_SCHECK1#
AH12
P1_SCHECK2#
AJ10
P1_SCHECK3#
AL9
P1_SCHECK4#
AG8
P1_SCHECK5#
AF6
P1_SCHECK6#
AL7
P1_SCHECK7#
AE15
P1_SDATAINCLK0#
AD12
P1_SDATAINCLK1#
AJ8
P1_SDATAINCLK2#
AK5
P1_SDATAINCLK3#
AE17
P1_SDATAINVALID#
AH15
P1_SDATAOUTCLK0#
AH11
P1_SDATAOUTCLK1#
AG9
P1_SDATAOUTCLK2#
AJ4
P1_SDATAOUTCLK3#
AL20
P1_SYSFILLVALID#
AMD-AMD762
3
AMD-762
System Bus 1
P1_SDATA0#
P1_SDATA1#
P1_SDATA2#
P1_SDATA3#
P1_SDATA4#
P1_SDATA5#
P1_SDATA6#
P1_SDATA7#
P1_SDATA8#
P1_SDATA9# P1_SDATA10# P1_SDATA11# P1_SDATA12# P1_SDATA13# P1_SDATA14# P1_SDATA15# P1_SDATA16# P1_SDATA17# P1_SDATA18# P1_SDATA19# P1_SDATA20# P1_SDATA21# P1_SDATA22# P1_SDATA23# P1_SDATA24# P1_SDATA25# P1_SDATA26# P1_SDATA27# P1_SDATA28# P1_SDATA29# P1_SDATA30# P1_SDATA31# P1_SDATA32# P1_SDATA33# P1_SDATA34# P1_SDATA35# P1_SDATA36# P1_SDATA37# P1_SDATA38# P1_SDATA39# P1_SDATA40# P1_SDATA41# P1_SDATA42# P1_SDATA43# P1_SDATA44# P1_SDATA45# P1_SDATA46# P1_SDATA47# P1_SDATA48# P1_SDATA49# P1_SDATA50# P1_SDATA51# P1_SDATA52# P1_SDATA53# P1_SDATA54# P1_SDATA55# P1_SDATA56# P1_SDATA57# P1_SDATA58# P1_SDATA59# P1_SDATA60# P1_SDATA61# P1_SDATA62# P1_SDATA63#
P1_VREF
AE14 AJ14 AE16 AD14 AJ15 AL14 AK15 AE13 AL16 AD15 AG15 AF15 AJ16 AH17 AJ17 AH14 AF14 AF12 AE12 AK12 AJ11 AE11 AG11 AF11 AK14 AL13 AL12 AG13 AJ13 AG12 AJ12 AL11 AG7 AF9 AK11 AL10 AK8 AL8 AH8 AK9 AE10 AE9 AD11 AG10 AJ9 AH9 AF8 AJ7 AF4 AG5 AF5 AK6 AH4 AJ5 AL4 AH3 AE8 AE7 AG6 AL6 AJ6 AE5 AH6 AL5
AB7
P1_SDATA-0 P1_SDATA-1 P1_SDATA-2 P1_SDATA-3 P1_SDATA-4 P1_SDATA-5 P1_SDATA-6 P1_SDATA-7 P1_SDATA-8 P1_SDATA-9 P1_SDATA-10 P1_SDATA-11 P1_SDATA-12 P1_SDATA-13 P1_SDATA-14 P1_SDATA-15 P1_SDATA-16 P1_SDATA-17 P1_SDATA-18 P1_SDATA-19 P1_SDATA-20 P1_SDATA-21 P1_SDATA-22 P1_SDATA-23 P1_SDATA-24 P1_SDATA-25 P1_SDATA-26 P1_SDATA-27 P1_SDATA-28 P1_SDATA-29 P1_SDATA-30 P1_SDATA-31 P1_SDATA-32 P1_SDATA-33 P1_SDATA-34 P1_SDATA-35 P1_SDATA-36 P1_SDATA-37 P1_SDATA-38 P1_SDATA-39 P1_SDATA-40 P1_SDATA-41 P1_SDATA-42 P1_SDATA-43 P1_SDATA-44 P1_SDATA-45 P1_SDATA-46 P1_SDATA-47 P1_SDATA-48 P1_SDATA-49 P1_SDATA-50 P1_SDATA-51 P1_SDATA-52 P1_SDATA-53 P1_SDATA-54 P1_SDATA-55 P1_SDATA-56 P1_SDATA-57 P1_SDATA-58 P1_SDATA-59 P1_SDATA-60 P1_SDATA-61 P1_SDATA-62 P1_SDATA-63
P1_S2K_VREF
2
P1_SDATA-[0..63] <6>
1
Set S2K_VREF to 50% of VCORE
P1_S2K_VREF
C261
C250
0.047u
0.039u
VCORE
R242 100
R244 100
A A
Title
Size Document Number Rev B
5
4
3
2
Date: Sheet of
North Bridge AMD762-CPU1
MICRO-STAR
MS-6501
1
9 39Thursday, July 19, 2001
0A
Page 10
5
D D
C C
B B
CLKOUT[0..5]<35>
CLKOUT-[0..5]<35>
A A
DDR_REF
5
C530
0.1u
C532
0.1u
(near the chip)
DDR_VREF
VCC2_5
CLKOUT0 CLKOUT1 CLKOUT2 CLKOUT3 CLKOUT4 CLKOUT5
CLKOUT-0 CLKOUT-1 CLKOUT-2 CLKOUT-3 CLKOUT-4 CLKOUT-5
4
U23E
MAA0
F17
MAA0
MAA1
G15
MAA1
MAA2
E15
MAA2
MAA3
G14
MAA3
MAA4
F14
MAA4
MAA5
E11
MAA5
MAA6
G12
MAA6
MAA7
G9
MAA7
MAA8
G11
MAA8
MAA9
G10
MAA9
MAA10
F18
MAA10
MAA11
H11
MAA11
MAA12
F9
MAA12
MAA13
G19
MAA13
MAA14
MAA[0..14]<35>
MAB[0..14]<35>
DM[0..8]<35>
CS-[0..7]<35>
RASA-<35> RASB-<35>
CASA-<35> CASB-<35>
WEA-<35> WEB-<35>
CKEA<35> CKEB<35>
DDR_REF
4
G18
MAA14
MAB0
H17
MAB0
MAB1
H15
MAB1
MAB2
F15
MAB2
MAB3
H14
MAB3
MAB4
E14
MAB4
MAB5
E12
MAB5
MAB6
G13
MAB6
MAB7
H12
MAB7
MAB8
F12
MAB8
MAB9
F11
MAB9
MAB10
H18
MAB10
MAB11
H9
MAB11
MAB12
E9
MAB12
MAB13
E20
MAB13
MAB14
E18
MAB14
DM0
B5
DM0
DM1
D8
DM1
DM2
A11
DM2
DM3
D14
DM3
DM4
E19
DM4
DM5
A22
DM5
DM6
D24
DM6
DM7
A28
DM7
DM8
C17
DM8
CS-0
H21
CS0#
CS-1
E23
CS1#
CS-2
F21
CS2#
CS-3
F23
CS3#
CS-4
H23
CS4#
CS-5
G23
CS5#
CS-6
G24
CS6#
CS-7
F24
CS7#
RASA-
G20
RASA#
RASB-
F20
RASB#
CASA-
G22
CASA#
CASB-
G21
CASB#
WEA- MDAT57
E21
WEA#
WEB-
H20
WEB#
CKEA
G8
CKEA
CKEB
F8
CLKOUT0 CLKOUT-0 CLKOUT1 CLKOUT-1 CLKOUT2 CLKOUT-2 CLKOUT3 CLKOUT-3 CLKOUT4 CLKOUT-4 CLKOUT5 CLKOUT-5
CKEB
G16
CLKOUT0
G17
CLKOUT#0
E6
CLKOUT1
F6
CLKOUT#1
E24
CLKOUT2
E25
CLKOUT#2
E16
CLKOUT3
E17
CLKOUT#3
E7
CLKOUT4
E8
CLKOUT#4
E26
CLKOUT5
F26
CLKOUT#5
D4
DDR_REF
MECC[0..7]<35>
3
AMD-762
DDR Interface
PDL_OUTPUT_TEST
MECC0
MECC1
MECC2
MECC3
MECC4
MECC5
C15
A16
A17
D17
C14
D15
MECC0
MECC1
MECC5
MECC4
MECC2
MECC3
3
MECC6
B17
A18
MECC7
MECC6
MECC7
MDAT0 MDAT1 MDAT2 MDAT3 MDAT4 MDAT5 MDAT6 MDAT7 MDAT8
MDAT9 MDAT10 MDAT11 MDAT12 MDAT13 MDAT14 MDAT15 MDAT16 MDAT17 MDAT18 MDAT19 MDAT20 MDAT21 MDAT22 MDAT23 MDAT24 MDAT25 MDAT26 MDAT27 MDAT28 MDAT29 MDAT30 MDAT31 MDAT32 MDAT33 MDAT34 MDAT35 MDAT36 MDAT37 MDAT38 MDAT39 MDAT40 MDAT41 MDAT42 MDAT43 MDAT44 MDAT45 MDAT46 MDAT47 MDAT48 MDAT49 MDAT50 MDAT51 MDAT52 MDAT53 MDAT54 MDAT55 MDAT56 MDAT57 MDAT58 MDAT59 MDAT60 MDAT61 MDAT62 MDAT63
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
AMD-AMD762
2
VCC2_5
MDAT0
C4
MDAT1
A4
MDAT2
B6
MDAT3
D6
MDAT4
C3
MDAT5
B3
MDAT6
C5
MDAT7
A6
MDAT8
C6
MDAT9
C7
MDAT10
A9
MDAT11
D9
MDAT12
A7
MDAT13
B8
MDAT14
C8
MDAT15
B9
MDAT16
E10
MDAT17
A10
MDAT18
D11
MDAT19
B12
MDAT20
C9
MDAT21
B11
MDAT22
C11
MDAT23
D12
MDAT24
A12
MDAT25
E13
MDAT26
A14
MDAT27
B15
MDAT28
C12
MDAT29
A13
MDAT30
B14
MDAT31
A15
MDAT32
B18
MDAT33
A19
MDAT34
A20
MDAT35
D20
MDAT36
C18
MDAT37
D18
MDAT38
B20
MDAT39
C20
MDAT40
B21
MDAT41
D21
MDAT42
E22
MDAT43
B23
MDAT44
A21
MDAT45
C21
MDAT46
A23
MDAT47
C23
MDAT48
D23
MDAT49
B24
MDAT50
B26
MDAT51
C26
MDAT52
A24
MDAT53
C24
MDAT54
A25
MDAT55
A26
MDAT56
C27 B27
MDAT58
C29
MDAT59
C30
MDAT60
A27
MDAT61
D26
MDAT62
D28
MDAT63
B29
DQS0
A5
DQS1
A8
DQS2
C10
DQS3
C13
DQS4
C19
DQS5
C22
DQS6
C25
DQS7
C28
DQS8
C16
TP3
D3
Place near IGD4 for VCC2_5 decoupling
MDAT[0..63] <35>
DQS[0..8] <35>
2
C542 0.1u C541 0.1u C540 0.1u C361 0.1u C357 0.1u C539 0.1u C360 0.1u
VCC2_5
C528 100p C513 100p C519 0.1u C524 0.1u C511 0.1u C518 1000p C525 0.1u C527 0.1u
Place under IGD4 (NOPOP)
Title
Size Document Number Rev Custom
Date: Sheet of
North Bridge AMD762-DDR
1
MICRO-STAR
MS-6501
1
10 39Wednesday, July 25, 2001
0A
Page 11
5
4
3
2
1
AMD-762
D D
C C
B B
A A
A_AD[0..31]<16,17,33,36> A_AD[32..63] <16,17>
VCC3
R287
4.7K
A_CBE-[0..3]<16,17,36>
A_CBE-[0..3]
5
A_AD0 A_AD1 A_AD2 A_AD3 A_AD4 A_AD5 A_AD6 A_AD7 A_AD8 A_AD9 A_AD10 A_AD11 A_AD12 A_AD13 A_AD14 A_AD15 A_AD16 A_AD17 A_AD18 A_AD19 A_AD20 A_AD21 A_AD22 A_AD23 A_AD24 A_AD25 A_AD26 A_AD27 A_AD28 A_AD29 A_AD30 A_AD31
A_CBE-0 A_CBE-1 A_CBE-2 A_CBE-3
A_DEVSEL-<16,17>
A_FRAME-<16,17>
A_IRDY-<16,17>
A_PAR<16,17,36>
A_SERR-<16,17>
A_STOP-<16,17>
A_TRDY-<16,17>
A_ISAREQ-<21>
TP29
A_REQ-0<17,21> A_REQ-1<16,17> A_REQ-2<16,17> A_REQ-3<17> A_REQ-4<17> A_REQ-5<17> A_REQ-6<17>
A_GNT-0<21> A_GNT-1<16> A_GNT-2<16>
PCIRST-2<13,23,32,33>
WSC-
P27 R29 P30 T25 P31 U24 R26 U25 T29 R31 V24 T27 R30 T31 U26 U27 V27
W29
V26 Y28
W31
Y29
W27
Y25
Y31 AA28 AA31
Y30 AA30
Y27
Y26 AA27
R27
V25
W25
Y24
V28
V31
H28
V29
U31
U29
U30
V30
E30
F30
H25
H27
F29
G27
E29
D31
E31
G29
H26
F28
F27
D29
AF21
J24 J25
U23C
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
CBE0# CBE1# CBE2# CBE3#
DEVSEL# FRAME# WSC# IRDY# PAR SERR# STOP# TRDY#
SBREQ# SBGNT#
REQ0# REQ1# REQ2# REQ3# REQ4# REQ5# REQ6#
GNT0# GNT1# GNT2# GNT3# GNT4# GNT5# GNT6#
RESET#
AMD-AMD762
PCI Bus
4
AD32 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AD44 AD45 AD46 AD47 AD48 AD49 AD50 AD51 AD52 AD53 AD54 AD55 AD56 AD57 AD58 AD59 AD60 AD61 AD62 AD63
CBE4 CBE5 CBE6 CBE7
PAR64 ACK64# REQ64#
M66
VDD_PCI0 VDD_PCI1 VDD_PCI2 VDD_PCI3 VDD_PCI4 VDD_PCI5 VDD_PCI6 VDD_PCI7 VDD_PCI8
VDD_PCI9 VDD_PCI10 VDD_PCI20 VDD_PCI21 VDD_PCI22 VDD_PCI23 VDD_PCI24
PCI66_CLK0 PCI66_CLK1 PCI66_CLK2
PCICLK
F31 K25 G31 L24 H30 J26 H31 J28 J30 J29 J31 L25 J27 M24 K27 K29 L26 L28 L27 L29 K31 M28 L30 M25 L31 P24 M26 M29 M27 N25 N27 R24
R25 M31 N29 N31
M30 R28 P26 U28
D30 G30 K26 K30 N26 N30 T26 T30 W26 W30 G26 L23 N23 R23 U23 W23
SR_PCI66CLK0
P25
SR_PCI66CLK1
P28
SR_PCI66CLK2
P29 AH21
A_AD32 A_AD33 A_AD34 A_AD35 A_AD36 A_AD37 A_AD38 A_AD39 A_AD40 A_AD41 A_AD42 A_AD43 A_AD44 A_AD45 A_AD46 A_AD47 A_AD48 A_AD49 A_AD50 A_AD51 A_AD52 A_AD53 A_AD54 A_AD55 A_AD56 A_AD57 A_AD58 A_AD59 A_AD60 A_AD61 A_AD62 A_AD63
A_CBE-4 A_CBE-5 A_CBE-6 A_CBE-7
PAR64 ACK64­REQ64-
A_M66EN
VCC3
PLL_PICCLK
PAR64 <16,17> ACK64- <16,17> REQ64- <16,17>WSC-<21>
AGP_CAL-
AGP_CAL
R501 47 R503 47 R504 22 R645 22
A_CBE-[4..7] <16,17>
VCC3
R273
4.7K
R275
4.7K NOPOP
R252 27.4_1%
R268 34.8_1%
PLL_PICCLK
3
VDDQ
PCI_66CLK0 <16> PCI_66CLK1 <16> PCI_66CLK2 <21>
GAD[0..31]<15>
A_M66EN <16,21>
GAD[0..31]
GCLK0<3>
AGP_VREF2X
(near the chip)
R237 100
Reserved
C239 100p Reserved
C259
0.01u
GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31
VDDQ
R249 150
R245 100
2
AB31 AA26 AC31 AA25 AC30 AB29 AD31 AC26
AC27 AG31 AC29
AH31
AB25 AD29 AC28
AE29 AD26
AH28
AJ30
AG29
AK29
AF27
AH29 AG27
AL28
AJ26
AD25
AF24 AG26 AG24
AF23
AE25
AJ21
AA23
AB26
AB30 AC23
AF22
AE26
AE30
AH30
AK22
AK25
AK28
AF25
Y22
AB22 AC21
AB20
U23D
GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31
AGPCLK
VDD_AGP0 VDD_AGP1 VDD_AGP2 VDD_AGP3 VDD_AGP4 VDD_AGP5 VDD_AGP6 VDD_AGP7 VDD_AGP8 VDD_AGP9 VDD_AGP10 VDD_AGP11 VDD_AGP12 VDD_AGP13 VDD_AGP14
VDD_AGP15
AMD-AMD762
AMD-762
VDDQ
AGP Bus
GDEVSEL#
AGP_VREF4X
AGP_VREF
AGP_CAL#VDD_AGP15
AB27
GCBE0#
AD28
GCBE1#
AJ29
GCBE2#
AF26
GCBE3#
AC24 AF29
GFRAME#
AE27
GSERR#
AK27
GSTOP#
AF30
GTRDY#
AF28
GIRDY#
AD27
GPAR
AK26
WBF#
AL25
PIPE#
AL26
RBF#
AL23
GGNT#
AK23
GREQ#
AK24
ST0
AL24
ST1
AJ23
ST2
AE31
ADSTB0
AD30
ADSTB0#
AJ27
ADSTB1
AJ28
ADSTB1#
AG23
SBA0
AE23
SBA1
AJ25
SBA2
AD23
SBA3
AE24
SBA4
AG25
SBA5
AL27
SBA6
AH26
SBA7
AJ24
SBSTB
AH24
SBSTB#
AC25 AG30
AA24
AGP_CAL
AF31AA21
AGP_VREF4X_IN
C257
C262
1u
0.01u
GCBE0- <15> GCBE1- <15> GCBE2- <15> GCBE3- <15>
GDEVSEL- <15> GFRAME- <15> GSERR- <15> GSTOP- <15> GTRDY- <15> GIRDY- <15> GPAR <15> WBF- <15> PIPE- <15> RBF- <15>
GGNT- <15> GREQ- <15>
SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7
SBSTB SBSTB-
AGP_VREF4X_IN AGP_VREF2X
AGP_CAL AGP_CAL-
AGP_VREF4X_IN <15>
C254
0.1u
SBSTB <15> SBSTB- <15>
ST0 <15> ST1 <15> ST2 <15>
ADSTB0 <15> ADSTB0- <15> ADSTB1 <15> ADSTB1- <15>
SBA[0..7]
MICRO-STAR
Title
Size Document Number Rev
B
Date: Sheet of
AMD-762 (PCI & AGP)
MS-6501
1
11 39Wednesday, July 25, 2001
SBA[0..7] <15>
0A
Page 12
5
D D
C C
B B
FB21
VCC2_5
600_0805
A A
Power for clock PLL. MUST close to AMD-762
5
C495
100p
C492
4.7u-0805
C491
4.7u-0805
TP2 TP1
4
AMD-762
U23F
AA11 D2
VDD_CORE P0_K7_VCORE0
AA13
VDD_CORE
AA15
VDD_CORE
AA17
VDD_CORE
AA19
VDD_CORE
B10
VDD_CORE
B13
VDD_CORE
B16
VDD_CORE
B19
VDD_CORE
B22
VDD_CORE
B25
VDD_CORE
B28
VDD_CORE
B4
VDD_CORE
B7
VDD_CORE
F10
VDD_CORE
F13
VDD_CORE
F16
VDD_CORE
F19
VDD_CORE
F22
VDD_CORE
F25
VDD_CORE
J11
VDD_CORE
J13
VDD_CORE
J15
VDD_CORE
J17
VDD_CORE
J19
VDD_CORE
J21
VDD_CORE
J23
VDD_CORE
J9
VDD_CORE
K10
VDD_CORE
K12
VDD_CORE
K14
VDD_CORE
K16
VDD_CORE
K18
VDD_CORE
K20
VDD_CORE
K22
VDD_CORE
L11
VDD_CORE
L13
VDD_CORE
L15
VDD_CORE
L17
VDD_CORE
L19
VDD_CORE
L21
VDD_CORE
M12
VDD_CORE
M14
VDD_CORE
M16
VDD_CORE
M18
VDD_CORE
M20
VDD_CORE
M22
VDD_CORE
N11
VDD_CORE
N13
VDD_CORE
N15
VDD_CORE
N17
VDD_CORE
N19
VDD_CORE
N21
VDD_CORE
P12
VDD_CORE
P14
VDD_CORE
P16
VDD_CORE
P18
VDD_CORE
P20
VDD_CORE
P22
VDD_CORE
R11
VDD_CORE
R13
VDD_CORE
R15
VDD_CORE
R17
VDD_CORE
R19
VDD_CORE
R21
VDD_CORE
T12
VDD_CORE
T14
VDD_CORE
T16
VDD_CORE
T18
VDD_CORE
T20
VDD_CORE
T22
VDD_CORE
U11
VDD_CORE
U13
VDD_CORE
U15
VDD_CORE
U17
VDD_CORE
U19
VDD_CORE
U21
VDD_CORE
V12
VDD_CORE
V14
VDD_CORE
V16
VDD_CORE
V18
VDD_CORE
V20
VDD_CORE
V22
VDD_CORE
W11
VDD_CORE
W13
VDD_CORE
W15
VDD_CORE
W17
VDD_CORE
W19
VDD_CORE
W21
VDD_CORE
Y12
VDD_CORE
Y14
VDD_CORE
Y16
VDD_CORE
Y18
VDD_CORE
Y20
VDD_CORE
F7
VDD_CORE
AG22
AVDD
AE1
SI_VDD
AD2
SI_VSS
4
POWER
P0_K7_VCORE1 P0_K7_VCORE2 P0_K7_VCORE3 P0_K7_VCORE4 P0_K7_VCORE5 P0_K7_VCORE6 P0_K7_VCORE7 P0_K7_VCORE8
P0_K7_VCORE9 P0_K7_VCORE10 P0_K7_VCORE11 P0_K7_VCORE12 P0_K7_VCORE13 P0_K7_VCORE14 P0_K7_VCORE15 P0_K7_VCORE16 P0_K7_VCORE17 P0_K7_VCORE18 P0_K7_VCORE19 P0_K7_VCORE20 P0_K7_VCORE21 P0_K7_VCORE22 P0_K7_VCORE23
P1_K7_VCORE0
P1_K7_VCORE1
P1_K7_VCORE2
P1_K7_VCORE3
P1_K7_VCORE4
P1_K7_VCORE5
P1_K7_VCORE6
P1_K7_VCORE7
P1_K7_VCORE8
P1_K7_VCORE9 P1_K7_VCORE10 P1_K7_VCORE11 P1_K7_VCORE12 P1_K7_VCORE13 P1_K7_VCORE14 P1_K7_VCORE15 P1_K7_VCORE16 P1_K7_VCORE17 P1_K7_VCORE18 P1_K7_VCORE19 P1_K7_VCORE20 P1_K7_VCORE21 P1_K7_VCORE22 P1_K7_VCORE23 P1_K7_VCORE24
NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8
NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC31 NC32
REF_5V
ROM_SDA ROM_SCK
DEBUG0 DEBUG1 DEBUG2
PX_CAL
PX_CAL#
SYSCLKREF
TEST#
DCSTOP#
AMD-AMD762
G2 K2 N2 T2 W2 AB2 G6 K6 N6 T6 W6 AB6 L9 N9 R9 U9 W9 AA9 Y10 V10 T10 P10 M10
AE2 AH2 AK4 AK7 AK10 AK13 AK16 AK19 AF7 AF10 AF13 AF16 AF19 AC9 AC11 AC13 AC15 AC17 AC19 AE6 AB10 AB12 AB14 AB16 AB18
A29 A3 AH23 AA29 AA8 AC8 AD18 AD21 AC7 AD9 AE20 AE22 AJ1 AJ31 AK2 AK30 AL22 AL29 AL3 B2 B30 C1 C2 C31 E27 E5 G25 G7 L8 Y8
H29 AL21
AK21 AK20
AJ22 AF20 AD3 AD4 AG20 AE21 AD20
3
VCOREVCC2_5
REF_5V SIPROM_DATA
SIPROM_CLK
TP4 TP6
TP5 PX_CAL PX_CAL­NBCLK_VREF
TEST-
3
DCSTOP- <21>
D10 D13 D16 D19 D22 D25 D27
E28
G28
H10 H13 H16 H19 H22 H24
K11 K13 K15 K17 K19 K21 K23 K24 K28
M11 M13 M15 M17 M19 M21 M23
N10 N12 N14 N16 N18 N20 N22 N24 N28
P11 P13 P15 P17 P19 P21 P23 R10 R12 R14 R16 R18 R20 R22
T11 T13 T15 T17 T19 T21 T23 T24 T28
D5 D7
E4 G4 H8
J10 J12 J14 J16 J18 J20 J22
K4 K8 K9
L10 L12 L14 L16 L18 L20 L22
M9
N4 N8
P9
T4 T8 T9
U23G
VSS VSS
AMD-762
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AMD-AMD762
GND
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
2
U10 U12 U14 U16 U18 U20 U22 V9 V11 V13 V15 V17 V19 V21 V23 W4 W8 W10 W12 W14 W16 W18 W20 W22 W24 W28 Y9 Y11 Y13 Y15 Y17 Y19 Y21 Y23 AA10 AA12 AA14 AA16 AA18 AA20 AA22 AB4 AB8 AB9 AB11 AB13 AB15 AB17 AB19 AB21 AB23 AB24 AB28 AC10 AC12 AC14 AC16 AC18 AC20 AC22 AD8 AD10 AD13 AD16 AD19 AD22 AD24 AE4 AE28 AG4 AG21 AG28 AH5 AH7 AH10 AH13 AH16 AH19 AH22 AH25 AH27 AJ20
Title
Size Document Number Rev
2
Date: Sheet of
AMD DOC SCH PX_CAL- 32 62 PX_CAL 23 47
PX_CAL PX_CAL-
R246 33 R243 33
REF_5V
Set CLK_VREF to 1.115V
NBCLK_VREF
SIPROM_DATA SIPROM_CLK
{Title}
MS-6501 0A
Custom
R235 470 R234 470
R296 22
C496
1
VCORE
4.7u-0805
TEST-
1
C328
0.1u
5VSB
C497
4.7u-0805
VCC2_5
12 39Tuesday, July 24, 2001
VCC3
R409 10K
R407
5.1K
R231 10K
R230 10K
Reserved
Page 13
5
VCC2_5 VCC2_5
DDR1
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
DDR DIMM-184
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
C858
C859
0.1u
0.1u
C394 1000p
C396 1000p
VCC2_5
C851
0.1u
C397 39p
C395 39p
5
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEA-_SR
C852
0.1u
D D
C C
B B
WEA-_SR<14,35>
VCC2_5
C390
2 1
DDR_VREF
0.1u
C391
2 1
0.1u
A A
DIMM-D184-BK
C853
0.1u
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
VSS0
3111826344250586674818993
Place 104p Cap under DIMMs
C854
C855
C856
0.1u
0.1u
0.1u
VSS1
C857
0.1u
VSS2
VDDQ4
VDDQ5
VSS10
VSS11
C860
0.1u
104
VDDQ6
VSS12
112
VDDQ7
VSS13
100
128
VDDQ8
VSS14
116
C861
0.1u
136
VDDQ9
VSS15
124
4
143
156
VDDQ10
VDDQ11
VSS16
VSS17
132
139
C862
0.1u
4
164
172
VDDQ12
VDDQ13
VSS18
VSS19
145
152
1801582
VDDQ14
VDDQ15
CK1#(CK0#)
NC(RESET#)
VSS20
VSS21
160
176
C863
0.1u
VDDID
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
CK0(DU) CK0#(DU) CK1(CK0)
CK2(DU) CK2#(DU)
CKE0 CKE1 CAS# RAS#
C864
0.1u
184
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12 A13
BA0 BA1 BA2 SCL
SDA
SA0 SA1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NC5
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
C865
0.1u
PCIRST-2<11,23,32,33>
157 158 71 163
5 14 25 36 56 67 78 86 47
167 48
43 41 130 37 32 125 29 122 27 141 118 115 103
59 52 113 92 91 181 182 183
44 45 49 51 134 135 142 144
16 17 137 138 76 75
173 10
21 111 65 154
97 107 119 129 149 159 169 177 140
CS-_SR0 CS-_SR1
DQS_SR0 DQS_SR1 DQS_SR2 DQS_SR3 DQS_SR4 DQS_SR5 DQS_SR6 DQS_SR7 DQS_SR8
MAA_SR0 MAA_SR1 MAA_SR2 MAA_SR3 MAA_SR4 MAA_SR5 MAA_SR6 MAA_SR7 MAA_SR8 MAA_SR9 MAA_SR10 MAA_SR11 MAA_SR12
MAA_SR13 MAA_SR14
SMBCLK SMBDATA
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
CLKOUT_SR1 CLKOUT-_SR1 CLKOUT_SR0 CLKOUT-_SR0 CLKOUT_SR2 CLKOUT-_SR2
CKEA_SR CASA-_SR
RASA-_SR DM_SR0
DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
C866
0.1u
C867
0.1u
R434 62
DDR_VREF
C868
0.1u
3
DDR_RESET-
R433
2.2K
CKEA_SR <14,35> CASA-_SR <14,35>
RASA-_SR <14,35>
WEB-_SR<14,35>
VCC2_5
C401
C409
0.1u
1000p
2 1
C404
C410
0.1u
1000p
2 1
Place 104p Cap. near the DIMM
3
DDR_RESET- <14>
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEB-_SR
C407 39p
DIMM-D184-BK C406 39p
DDR2
94 95 98 99 12 13 19
20 105 106 109 110
23
24
28
31 114 117 121 123
33
35
39
40 126 127 131 133
53
55
57
60 146 147 150 151
61
64
68
69 153 155 161 162
72
73
79
80 165 166 170 171
83
84
87
88 174 175 178 179
90
63
101 102
2 4 6 8
1 9
738467085
VDD0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
WP(NC) WE#
VREF NC2
NC3 NC4
VDD1
108
120
148
168223054627796
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
DDR DIMM-184
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
3111826344250586674818993
MAA_SR[0..14]<14,35> MAB_SR[0..14]<14,35>
MECC_SR[0..7]<14,35>
DM_SR[0..8]<14,35>
VDDQ4
VDDQ5
VSS10
VSS11
104
VDDQ6
VSS12
112
VDDQ7
VSS13
100
128
VDDQ8
VSS14
116
136
VDDQ9
VSS15
124
2
143
156
VDDQ10
VSS16
132
139
2
164
172
VDDQ11
VDDQ12
VSS17
VSS18
145
152
1801582
VDDQ13
VDDQ14
VSS19
VSS20
160
176
VCC2_5VCC2_5
VDDID
VDDQ15
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
SDA
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC5
NC(RESET#)
CKE0 CKE1 CAS# RAS#
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
VSS21
1
184
VDDSPD
CS-_SR2
157
CS-_SR3
158 71 163
DQS_SR0
5
DQS_SR1
14
DQS_SR2
25
DQS_SR3
36
DQS_SR4
56
DQS_SR5
67
DQS_SR6
78
DQS_SR7
86
DQS_SR8
47 167
MAB_SR0
48
A0
MAB_SR1
43
A1
MAB_SR2
41
A2
MAB_SR3
130
A3
MAB_SR4
37
A4
MAB_SR5
32
A5
MAB_SR6
125
A6
MAB_SR7
29
A7
MAB_SR8
122
A8
MAB_SR9
27
A9
MAB_SR10
141
MAB_SR11
118
A11
MAB_SR12
115
A12
103
A13
MAB_SR13
59
BA0
MAB_SR14
52
BA1
113
BA2
SMBCLK
92
SCL
SMBDATA
91 181
SA0
182
SA1
183
SA2
MECC_SR0
44
MECC_SR1
45
MECC_SR2
49
MECC_SR3
51
MECC_SR4
134
MECC_SR5
135
MECC_SR6
142
MECC_SR7
144
CLKOUT_SR4
16
CLKOUT-_SR4
17
CLKOUT_SR3
137
CLKOUT-_SR3
138
CLKOUT_SR5
76
CLKOUT-_SR5
75 173
DDR_RESET-DDR_RESET-
10
CKEB_SR
21 111
CASB-_SR
65
RASB-_SR
154
DM_SR0
97
DM_SR1
107
DM_SR2
119
DM_SR3
129
DM_SR4
149
DM_SR5
159
DM_SR6
169
DM_SR7
177
DM_SR8
140
CLKOUT_SR[0..5]<35>
CLKOUT-_SR[0..5]<35>
CS-_SR[0..7]<14,35>
MDAT_SR[0..63]<14,35>
DQS_SR[0..8]<14,35>
Title
Size Document Number Rev Custom Date: Sheet of
VCC2_5
R366 270
D15
1 2
GNx2-S-GN
SMBCLK <3,14,21,22,33> SMBDATA <3,14,21,22,33>
VCC2_5
CKEB_SR <14,35> CASB-_SR <14,35>
RASB-_SR <14,35>
MICRO-STAR
Rigster DDR DIMMs (1,2)
MS-6501
1
13 39Wednesday, July 25, 2001
0A
Page 14
5
4
3
2
1
VCC2_5 VCC2_5
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEB-_SR
DDR4
2 4 6
8 94 95 98 99 12 13 19 20
105 106 109 110
23 24 28 31
114 117 121 123
33 35 39 40
126 127 131 133
53 55 57 60
146 147 150 151
61 64 68 69
153 155 161 162
72 73 79 80
165 166 170 171
83 84 87 88
174 175 178 179
90 63
1
9
101 102
DIMM-D184-BK
738467085
108
VDD0
VDD1
VDD2
VDD3
VDD4
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
WP(NC) WE#
VREF NC2
NC3 NC4
VSS0
VSS1
3111826344250586674818993
120
148
168223054627796
VDD5
VDD6
VDD7
VDD8
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
104
VDDQ6
112
VDDQ7
DDR DIMM-184
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
100
128
VDDQ8
VSS14
116
136
VDDQ9
VSS15
124
143
VDDQ10
VSS16
132
DDR3
738467085
108
120
148
168223054627796
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
D D
C C
B B
WEA-_SR<13,35>
VCC2_5
C416
0.1u
2 1
DDR_VREF
C412
0.1u
2 1
C414 1000p
C419 1000p
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
WEA-_SR
C420 39p
C424 39p
2
DQ0
4
DQ1
6
DQ2
8
DQ3
94
DQ4
95
DQ5
98
DQ6
99
DQ7
12
DQ8
13
DQ9
19
DQ10
20
DQ11
105
DQ12
106
DQ13
109
DQ14
110
DQ15
23
DQ16
24
DQ17
28
DQ18
31
DQ19
114
DQ20
117
DQ21
121
DQ22
123
DQ23
33
DQ24
35
DQ25
39
DQ26
40
DQ27
126
DQ28
127
DQ29
131
DQ30
133
DQ31
53
DQ32
55
DQ33
57
DQ34
60
DQ35
146
DQ36
147
DQ37
150
DQ38
151
DQ39
61
DQ40
64
DQ41
68
DQ42
69
DQ43
153
DQ44
155
DQ45
161
DQ46
162
DQ47
72
DQ48
73
DQ49
79
DQ50
80
DQ51
165
DQ52
166
DQ53
170
DQ54
171
DQ55
83
DQ56
84
DQ57
87
DQ58
88
DQ59
174
DQ60
175
DQ61
178
DQ62
179
DQ63
90
WP(NC)
63
WE#
1
VREF
9
NC2
101
NC3
102
NC4
DIMM-D184-BK
VDD7
DDR DIMM-184
VSS0
VSS1
VSS2
VSS3
VSS4
3111826344250586674818993
VDD8
VSS5
VDDQ0
VDDQ1
VSS6
VSS7
VDDQ2
VDDQ3
VSS8
VSS9
104
VDDQ4
VDDQ5
VSS10
VSS11
112
VDDQ6
VDDQ7
VSS12
VSS13
100
128
VDDQ8
VSS14
116
136
VDDQ9
VSS15
124
143
156
VDDQ10
VSS16
132
139
164
172
VDDQ11
VDDQ12
VSS17
VSS18
145
152
1801582
VDDQ13
VDDQ14
VSS19
VSS20
160
176
VDDID
VDDQ15
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC(RESET#)
CKE0 CKE1 CAS# RAS#
VSS21
184
VDDSPD
CS-_SR4
157
CS-_SR5
158 71 163
DQS_SR0
5
DQS_SR1
14
DQS_SR2
25
DQS_SR3
36
DQS_SR4
56
DQS_SR5
67
DQS_SR6
78
DQS_SR7
86
DQS_SR8
47 167
MAA_SR0
48
A0
MAA_SR1
43
A1
MAA_SR2
41
A2
MAA_SR3
130
A3
MAA_SR4
37
A4
MAA_SR5
32
A5
MAA_SR6
125
A6
MAA_SR7
29
A7
MAA_SR8
122
A8
MAA_SR9
27
A9
MAA_SR10
141
MAA_SR11
118
A11
MAA_SR12
115
A12
103
A13
MAA_SR13
59
BA0
MAA_SR14
52
BA1
113
BA2
SMBCLK
92
SCL
SMBDATA
91
SDA
181
SA0
182
SA1
183
SA2
MECC_SR0
44
CB0
MECC_SR1
45
CB1
MECC_SR2
49
CB2
MECC_SR3
51
CB3
MECC_SR4
134
CB4
MECC_SR5
135
CB5
MECC_SR6
142
CB6
MECC_SR7
144
CB7
16 17
CLKOUT_SRB2
137
CLKOUT-_SRB2
138 76 75
173
NC5
DDR_RESET- DDR_RESET-
10
CKEA_SR
21 111
CASA-_SR
65
RASA-_SR
154
DM_SR0
97
DM0
DM_SR1
107
DM1
DM_SR2
119
DM2
DM_SR3
129
DM3
DM_SR4
149
DM4
DM_SR5
159
DM5
DM_SR6
169
DM6
DM_SR7
177
DM7
DM_SR8
140
DM8
VCC2_5
DDR_VREF
CKEA_SR <13,35> CASA-_SR <13,35>
RASA-_SR <13,35>
WEB-_SR<13,35>
VCC2_5
C544
C543
0.1u
1000p
2 1
C426
C425
0.1u
1000p
2 1
C429 39p
C428 39p
156
164
VDDQ11
VSS17
139
145
172
1801582
VDDQ12
VDDQ13
VSS18
VSS19
152
160
VDDQ14
VDDQ15
CK0(DU) CK0#(DU) CK1(CK0)
CK1#(CK0#)
CK2(DU) CK2#(DU)
NC(RESET#)
VSS20
VSS21
176
VCC2_5VCC2_5
VDDID
CS0# CS1# CS2# CS3#
DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7 DQS8
FETEN
A10_AP
CKE0 CKE1 CAS# RAS#
184
VDDSPD
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
A11 A12 A13
BA0 BA1
BA2 SCL SDA SA0 SA1 SA2
CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
NC5
DM0 DM1 DM2 DM3 DM4 DM5 DM6 DM7 DM8
157 158 71 163
5 14 25 36 56 67 78 86 47
167 48
43 41 130 37 32 125 29 122 27 141 118 115 103
59 52 113 92 91 181 182 183
44 45 49 51 134 135 142 144
16 17 137 138 76 75
173 10
21 111 65 154
97 107 119 129 149 159 169 177 140
CS-_SR6 CS-_SR7
DQS_SR0 DQS_SR1 DQS_SR2 DQS_SR3 DQS_SR4 DQS_SR5 DQS_SR6 DQS_SR7 DQS_SR8
MAB_SR0 MAB_SR1 MAB_SR2 MAB_SR3 MAB_SR4 MAB_SR5 MAB_SR6 MAB_SR7 MAB_SR8 MAB_SR9 MAB_SR10 MAB_SR11 MAB_SR12
MAB_SR13 MAB_SR14
SMBCLK SMBDATA
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
CLKOUT_SRB5 CLKOUT-_SRB5
CKEB_SR CASB-_SR
RASB-_SR DM_SR0
DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
CLKOUT_SR[0..5]<13,35>
CLKOUT-_SR[0..5]<13,35>
CS-_SR[0..7]<13,35>
MDAT_SR[0..63]<13,35>
DQS_SR[0..8]<13,35> MAA_SR[0..14]<13,35> MAB_SR[0..14]<13,35> MECC_SR[0..7]<13,35>
DM_SR[0..8]<13,35>
SMBCLK <3,13,21,22,33> SMBDATA <3,13,21,22,33>
VCC2_5
CLKOUT_SRB2<35>
CLKOUT-_SRB2<35>
CLKOUT_SRB5<35>
CLKOUT-_SRB5<35>
DDR_RESET- <13> CKEB_SR <13,35> CASB-_SR <13,35>
RASB-_SR <13,35>
CLKOUT_SRB2 CLKOUT-_SRB2
CLKOUT_SRB5 CLKOUT-_SRB5
Place 104p Cap. near the DIMM Place 104p Cap. near the DIMM
A A
Title
Size Document Number Rev Custom
5
4
3
2
Date: Sheet of
MICRO-STAR
Rigster DDR DIMMs (3,4)
MS-6501
14 39Monday, July 23, 2001
1
0A
Page 15
5
WBF­RBF­PIPE­GREQ-
GDEVSEL­GTRDY­GIRDY­GFRAME-
GSERR­GPAR GPERR­GSTOP-
SBA2 SBA0 SBA3 SBA1
SBA6 SBA4 SBA7 SBA5
ADSTB0 ADSTB1
SBSTB ADSTB0­ADSTB1­SBSTB-
C610
0.01u
EC29
1000u/6.3V
C
Q19
E
NPN-3904LT1-S-SOT23
GAD[0..31]
SBA[0..7]
RN35
8.2K RN42
8.2K
RN44
8.2K
RN37
8.2K
RN41
8.2K
R229 8.2K R208 8.2K R170 8.2K
R239 8.2K R196 8.2K R159 8.2K
R164
1K
C178
0.1u
R163
348
3 2
R166 523
VDDQ
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
12 34 56 78
2
+
1
-
U16A NS-LM358MX-SOIC8 8 4
+12V
3VDUAL
3 1
R108 100
GAD[0..31]<11>
SBA[0..7]<11>
D D
C C
B B
VDDQ
VCC
R90
1K
R96
4.7K
EC34 1000u/6.3V
B
5
EC63 1000u/6.3V
A A
TYPEDET-
VR4
CSK-2-SOT23-150mA
N-IPD20N03L-S-TO252
R219 100
4
VCC3
PIRQC-<18,19,21> GCLK1<3> GREQ-<11>
ST0<11> ST2<11> RBF-<11>
SBSTB<11>
3VDUAL
ADSTB1<11>
GCBE2-<11>
GIRDY-<11>
GDEVSEL-<11>
GSERR-<11>
GCBE1-<11>
ADSTB0<11>
Q40
DS
G
C223
0.1u
2 1
NOPOP
4
VCC3
C224
0.1u
GREQ­ST0
ST2 RBF-
SBA0 SBA2
SBA4 SBA6
GAD31 GAD29
GAD27 GAD25
GAD23 GAD21
GAD19 GAD17
GCBE2­GIRDY-
GDEVSEL­GPERR­GSERR-
GCBE1­GAD14
GAD12 GAD10
GAD8
GAD7 GAD5
GAD3 GAD1
VREF4X_OUT
+
EC25
1000u/6.3V
VCC
3
D1 D2 D3 D4 D5 D6 D7 D8 D9
D10
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 B63 B64 B65 B66
F1
F2
F3
F4
F5
F6
F7
F8
F9 F10 F11 F12 F13 F14
3
AGP1
VCC3_3_J VCC3_3_K VCC3_3_L VCC3_3_M VCC3_3_N VCC3_3_O VCC3_3_P VCC3_3_Q PRSNT#2 PRSNT#1
AGP_OVRCNT# 5V_A 5V_B AGP_USB+ GND_Q INTB# AGPCLK_CONN REQ# VCC3_3_R ST0 ST2 RBF# GND_R RESV_L SBA0 VCC3_3_S SBA2 SB_STB GND_S SBA4 SBA6 RESV_M GND_T 3_3AUX_1 VCC3_3_T GAD31 GAD29 VCC3_3_U GAD27 GAD25 GND_U AD_STB1 GAD23 VDDQ_F GAD21 GAD19 GND_V GAD17 C/BE#2 VDDQ_G IRDY# 3_3AUX_2 GND_W RESV_N VCC3_3_V DEVSEL# VDDQ_H PERR# GND_X SERR# C/BE#1 VDDQ_I GAD14 GAD12 GND_Y GAD10 GAD8 VDDQ_J AD_STB0 GAD7 GND_Z GAD5 GAD3 VDDQ_K GAD1 VREFCG
RESV_O RESV_P GND_AA GND_BB GND_CC GND_DD GND_EE GND_FF GND_GG GND_HH GND_II GND_JJ GND_KK GND_LL
CARD-D180
2
VDDQ
C1
VCC3_3_A
C2
GND_A
C3
VCC3_3_B
C4
GND_B
C5
GND_C
C6
GND_D
C7
GND_E
C8
GND_F
C9
RESV_A
C10
RESV_B
KEY
KEY
VCC_12V_A
TYPEDET#
RESV_C
AGP_USB-
GND_G
INTA#
RST# GNT#
VCC3_3_E
RESV_D
PIPE#
GND_H
WBF#
SBA1
VCC3_3_F
SBA3
SB_STB#
GND_I
SBA5 SBA7
RESV_E
GND_J
RESV_F
VCC3_3_G
GAD30 GAD28
VCC3_3_H
GAD26 GAD24
GND_K
AD_STB1#
C/BE#3
VDDQ_A
GAD22 GAD20 GND_L GAD18
GAD16 VDDQ_B FRAME# RESV_G
GND_M
RESV_H
VCC3_3_I
TRDY#
STOP#
PME#
GND_N
GAD15 VDDQ_C
GAD13
GAD11
GND_O
GAD9
C/BE#0
VDDQ_D
AD_STB0#
GAD6
GND_P
GAD4 GAD2
VDDQ_E
GAD0
VREFGC
RESV_I
RESV_J
VCC_12V_B VCC_12V_C VCC_12V_D
VCC_12V_E
VCC_12V_F VCC_12V_G
VCC_12V_H
VCC_12V_I VCC_12V_J VCC_12V_K VCC_12V_L
VCC_12V_M
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
ST1
A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50
PAR
A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 A63 A64 A65 A66
E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14
+12V
+12V
TYPEDET-
GGNT­ST1 PIPE­WBF-
SBA1 SBA3
SBA5 SBA7
GAD30 GAD28
GAD26 GAD24
GCBE3­GAD22
GAD20 GAD18
GAD16 GFRAME-
GTRDY­GSTOP­R704 0-REV
GPAR GAD15
GAD13 GAD11
GAD9 GCBE0-
GAD6 GAD4
GAD2 GAD0
AGP_VREF4X_IN
C299
0.1u
+12V
+ EC37
AGP1-1 AGP LABEL
Near the AGP connector
470u
2
AGP Pro Connector
AGP Pro Imax
VCC3 7.6A VCC12 9.2A
TYPEDET- <36>
PIRQB- <18,19,21,32>
PCIRST-1 <16,18,19,22,23,26>
GGNT- <11> ST1 <11> PIPE- <11> WBF- <11>
SBSTB- <11>
GCBE3- <11>
GFRAME- <11>
GTRDY- <11> GSTOP- <11> PME- <18,19,21,32>
GPAR <11>
GCBE0- <11>
AGP_VREF4X_IN <11>
ADSTB1- <11>
ADSTB0- <11>
Title
Size Document Number Rev Custom Date: Sheet of
VCC3
+ EC18
1000u/6.3V
AGP PRO CONNECTOR
+12V
C591
0.1u
VREF4X_OUT
C587
0.1u NOPOP
TYPEDET#
Low High
MICRO-STAR
MS-6501
1
J4
3
4
21
4.7u-1206
R258 1K
R263 1K
1
GND
12V
2
GND
12V
D2x2
21
C590
C589
4.7u-1206
VDDQ
C280 560p
R255 75
R260 75
C292 560p
Place close to N/B
VDDQ
1.5V
3.3V
15 39Friday, July 20, 2001
1
0A
Page 16
5
4
3
2
1
PCI 64 SLOT
-12V
TCK
A_INTB­A_INTD­PRSNT1_1
PRSNT1_2
PCI_66CLK0 A_REQ-1
A_CBE-3
A_CBE-2
A_IRDY-
A_IRDY-<11,17>
A_DEVSEL­A_PLOCK-
A_PLOCK-<17>
A_PERR-
A_PERR-<17>
A_SERR-
A_SERR-<11,17>
ACK64-
ACK64-<11,17>
A_CBE-6 A_CBE-4
CN22
0.01u
TCK<18,19>
A_INTB-<17,21> A_INTD-<17,21>
PCI_66CLK0<11>
A_REQ-1<11,17>
A_DEVSEL-<11,17>
D D
C C
A_M66EN<11,21>
B B
PRSNT2_1 PRSNT2_2 PRSNT1_1 PRSNT1_2
A_AD[0..63] <11,17,33,36>
A_CBE-[0..7]<11,17,36>
SR_A_CBE-[0..7]<17,21>
SR_A_AD[0..63] <17,21>
IDSEL:A_AD19 INTA#: A_INTA-
A A
INTB#: A_INTB­INTC#: A_INTC­INTD#: A_INTD-
VCC3
Stitch caps
IDSEL:SR_A_AD19 INTA#: SR_A_INTB­INTB#: SR_A_INTC­INTC#: SR_A_INTD­INTD#: SR_A_INTA-
C678
100P
7 8 5 6 3 4 1 2
5
A_AD31 A_AD29
A_AD27 A_AD25
A_AD23 A_AD21
A_AD19 A_AD17
A_CBE-1 A_AD14
A_AD12 A_AD10 A_M66EN
A_AD8 A_AD7
A_AD5 A_AD3
A_AD1
A_AD63 A_AD61
A_AD59 A_AD57
A_AD55 A_AD53
A_AD51 A_AD49
A_AD47 A_AD45
A_AD43 A_AD41
A_AD39 A_AD37
A_AD35 A_AD33
VCC3
VCC
PCI1
B1
-12V
B2
TCK
B3
GND_S
B4
TDO
B5
+5V_E
B6
+5V_F
B7
P64IRQ1
B8
P64IRQ3
B9
PRSNT#1
B10
RESV_E
B11
PRSNT#2
B14
RESV_F
B15
GND_T
B16
CLK
B17
GND_U
B18
REQ#
B19
3_3V_M
B20
AD31
B21
AD29
B22
GND_V
B23
AD27
B24
AD25
B25
3_3V_N
B26
C/BE#3
B27
AD23
B28
GND_W
B29
AD21
B30
AD19
B31
3_3V_O
B32
AD17
B33
C/BE#2
B34
GND_X
B35
IRDY#
B36
3_3V_P
B37
DEVSEL#
B38
GND_Y
B39
LOCK#
B40
PERR#
B41
3_3V_Q
B42
SERR#
B43
3_3V_R
B44
C/BE#1
B45
AD14
B46
GND_Z
B47
AD12
B48
AD10
B49
M66EN
B50
GND_AA
B51
GND_BB
B52
AD8
B53
AD7
B54
3_3V_S
B55
AD5
B56
AD3
B57
GND_CC
B58
AD1
B59
3_3V_T
B60
ACK64#
B61
+5V_G
B62
+5V_H
B63
RESV_G
B64
GND__DD
B65
C/BE#6
B66
C/BE#4
B67
GND_EE
B68
AD63
B69
AD61
B70
3_3V_U
B71
AD59
B72
AD57
B73
GND_FF
B74
AD55
B75
AD53
B76
GND_GG
B77
AD51
B78
AD49
B79
3_3V_V
B80
AD47
B81
AD45
B82
GND_HH
B83
AD43
B84
AD41
B85
GND_II
B86
AD39
B87
AD37
B88
3_3V_W
B89
AD35
B90
AD33
B91
GND_JJ
B92
RESV_H
B93
RESV_I
PCI-64
KEY
KEY
TRST#
+12V TMS
+5V_A P64IRQ0 P64IRQ2
+5V_B
RESV_A
3_3V_A
RESV_B
3_3VAUX_1
RST#
3_3V_B
GNT#
GND_A
PME# AD30
3_3V_C
AD28 AD26
GND_B
AD24
IDSEL
3_3V_D
AD22 AD20
GND_C
AD18 AD16
3_3V_E
FRAME#
GND_D TRDY# GND_E STOP#
3_3V_F
SDONE
SBO#
GND_F
AD15
3_3V_G
AD13 AD11
GND_G
GND_H
GND_I
C/BE#0
3_3V_H
GND_J
3_3V_I
REQ64#
+5V_C
+5V_D
GND_K C/BE#7 C/BE#5 3_3V_J
PAR64
AD62
GND_L
AD60 AD58
GND_M
AD56 AD54
3_3V_K
AD52 AD50
GND_N
AD48 AD46
GND_O
AD44 AD42
3_3V_L
AD40 AD38
GND_P
AD36 AD34
GND_Q
AD32
RESV_C
GND_R
RESV_DGND_KK
4
TDI
PAR
AD9
AD6 AD4
AD2 AD0
VCC
+12V
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94B94
TRST­TMS
TDI A_INTA-
A_INTC-
PCIRST-1
SR_A_GNT-1
A_PCI_PME­A_AD30
A_AD28 A_AD26
A_AD24
A_AD22 A_AD20
A_AD18 A_AD16
A_FRAME­A_TRDY­A_STOP-
A_PAR A_AD15
A_AD13 A_AD11
A_AD9
A_CBE-0 A_AD6
A_AD4 A_AD2
A_AD0 REQ64-
R505 33
R647 100
A_CBE-7 A_CBE-5
PAR64 A_AD62
A_AD60 A_AD58
A_AD56 A_AD54
A_AD52 A_AD50
A_AD48 A_AD46
A_AD44 A_AD42
A_AD40 A_AD38
A_AD36 A_AD34
A_AD32
3VDUAL
REQ64- <11,17>
TRST- <18,19> TMS <18,19>
TDI <18,19> A_INTA- <17,21>
A_INTC- <17,21>
PCIRST-1 <15,18,19,22,23,26>
A_GNT-1 <11>
A_PCI_PME- <21>
A_AD19
IDSEL
A_FRAME- <11,17> A_TRDY- <11,17> A_STOP- <11,17>
A_SDONE1 <17> A_SBO1 <17>
A_PAR <11,17,36>
PAR64 <11,17>
VCC3
Stitch caps
C681
100P
3
TCK<18,19>
SR_A_INTC-<17> SR_A_INTA-<17>
PCI_66CLK1<11>
A_REQ-2<11,17>
SR_A_IRDY-<17,21> SR_A_DEVSEL-<17,21> SR_A_PLOCK-<17>
SR_A_PERR-<17> SR_A_SERR-<17,21>
SR_ACK64-<17>
TCK
SR_A_INTC­SR_A_INTA­PRSNT2_1
PRSNT2_2
PCI_66CLK1 A_REQ-2
SR_A_IRDY­SR_A_DEVSEL­SR_A_PLOCK-
SR_A_PERR­SR_A_SERR-
-12V
SR_A_AD31 SR_A_AD29
SR_A_AD27 SR_A_AD25
SR_A_CBE-3
SR_A_AD23 SR_A_AD21
SR_A_AD19 SR_A_AD17
SR_A_CBE-2
SR_A_CBE-1 SR_A_AD14
SR_A_AD12 SR_A_AD10 A_M66EN
SR_A_AD8 SR_A_AD7
SR_A_AD5 SR_A_AD3
SR_A_AD1
SR_ACK64-
SR_A_CBE-6 SR_A_CBE-4
SR_A_AD63 SR_A_AD61
SR_A_AD59 SR_A_AD57
SR_A_AD55 SR_A_AD53
SR_A_AD51 SR_A_AD49
SR_A_AD47 SR_A_AD45
SR_A_AD43 SR_A_AD41
SR_A_AD39 SR_A_AD37
SR_A_AD35 SR_A_AD33
VCC3
VCC
PCI2
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11
B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 B50 B51 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
B63 B64 B65 B66 B67 B68 B69 B70 B71 B72 B73 B74 B75 B76 B77 B78 B79 B80 B81 B82 B83 B84 B85 B86 B87 B88 B89 B90 B91 B92 B93
-12V TCK GND_S TDO +5V_E +5V_F P64IRQ1 P64IRQ3 PRSNT#1 RESV_E PRSNT#2
RESV_F GND_T CLK GND_U REQ# 3_3V_M AD31 AD29 GND_V AD27 AD25 3_3V_N C/BE#3 AD23 GND_W AD21 AD19 3_3V_O AD17 C/BE#2 GND_X IRDY# 3_3V_P DEVSEL# GND_Y LOCK# PERR# 3_3V_Q SERR# 3_3V_R C/BE#1 AD14 GND_Z AD12 AD10 M66EN GND_AA GND_BB AD8 AD7 3_3V_S AD5 AD3 GND_CC AD1 3_3V_T ACK64# +5V_G +5V_H
RESV_G GND__DD C/BE#6 C/BE#4 GND_EE AD63 AD61 3_3V_U AD59 AD57 GND_FF AD55 AD53 GND_GG AD51 AD49 3_3V_V AD47 AD45 GND_HH AD43 AD41 GND_II AD39 AD37 3_3V_W AD35 AD33 GND_JJ RESV_H RESV_I
CARD-D184
TRST#
+12V
TMS
+5V_A P64IRQ0 P64IRQ2
+5V_B
RESV_A
3_3V_A
RESV_B
KEY
3_3VAUX_1
RST#
3_3V_B
GNT#
GND_A
PME#
AD30
3_3V_C
AD28 AD26
GND_B
AD24
IDSEL
3_3V_D
AD22 AD20
GND_C
AD18 AD16
3_3V_E
FRAME#
GND_D
TRDY# GND_E
STOP# 3_3V_F SDONE
SBO#
GND_F
PAR
AD15
3_3V_G
AD13 AD11
GND_G
AD9
GND_H
GND_I C/BE#0 3_3V_H
AD6 AD4
GND_J
AD2 AD0
3_3V_I
REQ64#
+5V_C +5V_D
KEY
GND_K C/BE#7 C/BE#5
3_3V_J
PAR64
AD62
GND_L
AD60 AD58
GND_M
AD56 AD54
3_3V_K
AD52 AD50
GND_N
AD48 AD46
GND_O
AD44 AD42
3_3V_L
AD40 AD38
GND_P
AD36 AD34
GND_Q
AD32
RESV_C
GND_R
RESV_DGND_KK
2
VCC
+12V
A1 A2 A3 A4
TDI
A5 A6 A7 A8 A9 A10 A11
A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 A50 A51 A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62
A63 A64 A65 A66 A67 A68 A69 A70 A71 A72 A73 A74 A75 A76 A77 A78 A79 A80 A81 A82 A83 A84 A85 A86 A87 A88 A89 A90 A91 A92 A93 A94B94
TRST­TMS
TDI SR_A_INTB-
SR_A_INTD-
PCIRST-1
SR_A_GNT-2
A_PCI_PME­SR_A_AD30
SR_A_AD28 SR_A_AD26
SR_A_AD24
SR_A_AD22 SR_A_AD20
SR_A_AD18 SR_A_AD16
SR_A_FRAME­SR_A_TRDY­SR_A_STOP-
SR_A_PAR SR_A_AD15
SR_A_AD13 SR_A_AD11
SR_A_AD9
SR_A_CBE-0 SR_A_AD6
SR_A_AD4 SR_A_AD2
SR_A_AD0 SR_REQ64-
SR_A_CBE-7 SR_A_CBE-5
SR_PAR64 SR_A_AD62
SR_A_AD60 SR_A_AD58
SR_A_AD56 SR_A_AD54
SR_A_AD52 SR_A_AD50
SR_A_AD48 SR_A_AD46
SR_A_AD44 SR_A_AD42
SR_A_AD40 SR_A_AD38
SR_A_AD36 SR_A_AD34
SR_A_AD32
Title
Size Document Number Rev
Custom
Date: Sheet of
TRST- <18,19> TMS <18,19>
SR_A_INTB- <17> SR_A_INTD- <17>
3VDUAL
PCIRST-1 <15,18,19,22,23,26>
R508 33
A_PCI_PME- <21>
R646 100
SR_A_FRAME- <17,21> SR_A_TRDY- <17,21> SR_A_STOP- <17,21>
A_SDONE2 <17> A_SBO2 <17>
SR_A_PAR <17,21>
SR_REQ64- <17>
SR_PAR64 <17>
A_GNT-2 <11>
SR_A_AD20
MICRO-STAR
PCI 64 SLOT1
MS-6501
1
IDSEL
16 39Wednesday, July 25, 2001
0A
Page 17
SR_A_AD63
1
SR_A_AD62
3
SR_A_AD61
5
SR_A_AD60
7
SR_A_AD59
1
SR_A_AD58
3
SR_A_AD57
5
SR_A_AD56
7
SR_A_AD55
1
SR_A_AD54
3
SR_A_AD53
5
SR_A_AD52
7
SR_A_AD51
1
SR_A_AD50
3
SR_A_AD49
5
SR_A_AD48
7
SR_A_AD47
1
SR_A_AD46
3
SR_A_AD45
5
SR_A_AD44
7
SR_A_AD43
1
SR_A_AD42
3
SR_A_AD41
5
SR_A_AD40
7
SR_A_AD39
1
SR_A_AD38
3
SR_A_AD37
5
SR_A_AD36
7
SR_A_AD35
1
SR_A_AD34
3
SR_A_AD33
5
SR_A_AD32
7
SR_A_AD31
1
SR_A_AD30
3
SR_A_AD29
5
SR_A_AD28
7
SR_A_AD27
1
SR_A_AD26
3
SR_A_AD25
5
SR_A_AD24
7
SR_A_AD23
1
SR_A_AD22
3
SR_A_AD21
5
SR_A_AD20
7
SR_A_AD18
1
SR_A_AD19
3
SR_A_AD16
5
SR_A_AD17
7
SR_A_AD15
1
SR_A_AD14
3
SR_A_AD13
5
SR_A_AD12
7
SR_A_AD11
1
SR_A_AD9
3
SR_A_AD10
5
SR_A_AD8
7
SR_A_AD7
1
SR_A_AD6
3
SR_A_AD5
5
SR_A_AD4
7
SR_A_AD3
1
SR_A_AD1
3
SR_A_AD2
5
SR_A_AD0
7
5
R662 33
A_SERR-<11,16>
R663 33
ACK64-<11,16>
R664 33
REQ64-<11,16>
R665 33
PAR64<11,16>
8
A_INTA-<16,21>
6
A_INTB-<16,21>
4
A_INTC-<16,21>
2
A_INTD-<16,21>
A_CBE-0 A_CBE-1 A_CBE-2 A_CBE-3
33
R666 33 R667 33 R668 33 R669 33
A_CBE-7 SR_A_CBE-7
2
A_CBE-6
4
A_CBE-5
6
A_CBE-4
8
33
2
A_IRDY-<11,16>
A_DEVSEL-<11,16>
4 6
A_PLOCK-<16>
8
A_PERR-<16>
33
SR_A_AD[0..63] SR_A_AD51 A_AD[0..63]
A_AD[0..63]
SR_A_AD[0..63]
A_CBE-[0..7]<11,16,36>
SR_A_CBE-[0..7]<16,21>
SR_A_SERR- <16,21> SR_ACK64- <16> SR_REQ64- <16> SR_PAR64 <16>
RN221
7
SR_A_INTA- <16>
5
SR_A_INTB- <16>
3
SR_A_INTC- <16>
1
SR_A_INTD- <16>
SR_A_CBE-0 SR_A_CBE-1 SR_A_CBE-2 SR_A_CBE-3
RN228
1
SR_A_CBE-6
3
SR_A_CBE-5
5
SR_A_CBE-4
7
RN231
1
SR_A_IRDY- <16,21>
3
SR_A_DEVSEL- <16,21>
5
SR_A_PLOCK- <16>
7
SR_A_PERR- <16>
SR_A_AD[0..63] <16,21> A_AD[0..63] <11,16,33,36>
A_AD[0..63] <11,16,33,36>
SR_A_AD[0..63] <16,21>
A_CBE-[0..7]
SR_A_CBE-[0..7]
RN218
A_AD63
2
A_AD62
4
A_AD61
6
A_AD60
8 33
RN222
A_AD59
2
A_AD58
4
A_AD57
6
A_AD56
8 33
A_AD55 A_AD54 A_AD53 A_AD52
A_AD51 A_AD50 A_AD49 A_AD48
A_AD47 A_AD46 A_AD45 A_AD44
A_AD43 A_AD42 A_AD41 A_AD40
A_AD39 A_AD38 A_AD37 A_AD36
A_AD35 A_AD34 A_AD33 A_AD32
A_AD31 A_AD30 A_AD29 A_AD28
A_AD27 A_AD26 A_AD25 A_AD24
A_AD23 A_AD22 A_AD21 A_AD20
A_AD18 A_AD19 A_AD16 A_AD17
A_AD15 A_AD14 A_AD13 A_AD12
A_AD11 A_AD9 A_AD10 A_AD8
A_AD7 A_AD6 A_AD5 A_AD4
A_AD3 A_AD1 A_AD2 A_AD0
RN226 2 4 6 8
33
RN229 2 4 6 8
33
RN233 2 4 6 8
33
RN236 2 4 6 8
33
RN237 2 4 6 8
33
RN240 2 4 6 8
33
RN243 2 4 6 8
33
RN246 2 4 6 8
33
RN249 2 4 6 8
33
RN253 2 4 6 8
33
RN257 2 4 6 8
33
RN261 2 4 6 8
33
RN264 2 4 6 8
33
RN267 2 4 6 8
D D
C C
B B
A A
33
5
4
3
A_FRAME-<11,16>
A_TRDY-<11,16>
A_STOP-<11,16>
A_PAR<11,16,36>
2
RN232
1
2 4 6 8
33
3 5 7
SR_A_FRAME- <16,21> SR_A_TRDY- <16,21> SR_A_STOP- <16,21> SR_A_PAR <16,21>
1
VCC3
RN40
A_SBO1<16> A_SDONE1<16> A_SBO2<16> A_SDONE2<16>
1 2 3 4 5 6 7 8
8.2K
VCC3 VCC3
RN62
5
10
SR_A_AD32
1
1
SR_A_AD33
2
2
SR_A_AD34
3
3
SR_A_AD35
4
4
SR_A_AD36
6
6
SR_A_AD37
7
7
SR_A_AD38
8
8
SR_A_AD39
9
9510
8.2K
RN60
5
10
SR_A_AD40
1
1
SR_A_AD41
2
2
SR_A_AD42
3
3
SR_A_AD43
4
4
SR_A_AD44
6
6
SR_A_AD45
7
7
SR_A_AD46
8
8
SR_A_AD47
9
9510
8.2K
RN57
5
10
SR_A_AD48
1
1
SR_A_AD49
2
2
SR_A_AD50
3
3
4
4
SR_A_AD52
6
6
SR_A_AD53
7
7
SR_A_AD54
8
8
SR_A_AD55
9
9510
8.2K
RN54
5
10
SR_A_AD56
1
1
SR_A_AD57
2
2
SR_A_AD58
3
3
SR_A_AD59
4
4
SR_A_AD60
6
6
SR_A_AD61
7
7
SR_A_AD62
8
8
SR_A_AD63
9
9510
8.2K
4
3
RN47
5
10
SR_REQ64-
1
1
SR_ACK64-
2
2
SR_PAR64
3
3
4
4
SR_A_CBE-4
6
6
SR_A_CBE-6
7
7
SR_A_CBE-5
8
8
SR_A_CBE-7
9
9510
SR_REQ64- <16> SR_ACK64- <16> SR_PAR64 <16>
SR_A_CBE-[4..7] <16>
SR_A_INTA-<16> SR_A_INTB-<16> SR_A_INTC-<16> SR_A_INTD-<16>
RN244 1 2 3 4 5 6 7 8
8.2K
8.2K
RN288
5
10
1 2 3 4 6 7 8 9510
SR_A_DEVSEL-
1
SR_A_TRDY-
2
SR_A_IRDY-
3
SR_A_FRAME-
4
SR_A_SERR-
6
SR_A_PERR-
7
SR_A_PLOCK-
8
SR_A_STOP-
9
SR_A_DEVSEL- <16,21> SR_A_TRDY- <16,21> SR_A_IRDY- <16,21> SR_A_FRAME- <16,21> SR_A_SERR- <16,21> SR_A_PERR- <16> SR_A_PLOCK- <16> SR_A_STOP- <16,21>
8.2K
RN289
A_REQ-3
1
5
1
A_REQ-4
2
2
A_REQ-5
3
3
A_REQ-6
4
4
A_REQ-0
6
6
A_REQ-1
7
7
A_REQ-2
8
8
9
10
9510
A_REQ-3 <11> A_REQ-4 <11> A_REQ-5 <11> A_REQ-6 <11> A_REQ-0 <11,21> A_REQ-1 <11,16> A_REQ-2 <11,16>
8.2K
Title
PCI64 TERMINATION/BYPASS CAP.
Size Document Number Rev
Custom
2
Date: Sheet of
MICRO-STAR
MS-6501
VCC3
17 39Wednesday, July 25, 2001
1
0A
Page 18
5
4
3
2
1
AD[0..31]<19,21,32,37>
C_BE-[0..3]<19,21,32>
AD[0..31]
C_BE-[0..3]
PCI Connector 3,4
TCK
PIRQD­PRSNT-31
PRSNT-32
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY­DEVSEL­PLOCK-
PERR­SERR­C_BE-1
AD14 AD12
AD10
AD8 AD7
AD5 AD3
AD1 ACK64-3
-12V
VCC3
VCC
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
PCI3
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
PCI-D120-WH-SN
VCC3
+12V
VCC
A1
TRST#
A2
+12V
A3
TMS
A4
TDI
A5
+5V
A6
INTA#
A7
INTC#
A8
+5V
A9
RSVD1
A10
+5V
A11
RSVD3
A12
GND
A13
GND
A14
RSVD4
A15
RST#
A16
+5V
A17
GNT#
A18
GND
A19
RSVD6
A20
AD30
A21
+3.3V
A22
AD28
A23
AD26
A24
GND
A25
AD24
A26
IDSEL#
A27
+3.3V
A28
AD22
A29
AD20
A30
GND
A31
AD18
A32
AD16
A33
+3.3V
A34
FRAME#
A35
GND
A36
TRDY#
A37
GND
A38
STOP#
A39
+3.3V
A40
SDONE
A41
SBO#
A42
GND
A43
PAR
A44
AD15
A45
+3.3V
A46
AD13
A47
AD11
A48
GND
A49
AD9
A52
C/BE0#
A53
+3.3V
A54
AD6
A55
AD4
A56
GND
A57
AD2
A58
AD0
A59
+5V
A60
REQ64#
A61
+5V
A62
+5V
4
TRST­TMS
TDI
PIRQA­PIRQC-PIRQB-
PCIRST-1 GNT1­PME-
AD30 AD28
AD26 AD24
R134 100 AD22
AD20 AD18
AD16 FRAME­TRDY­STOP­SDONE3
SBO3 PAR
AD15 AD13
AD11 AD9
C_BE-0 AD6
AD4 AD2
AD0 REQ64-3
TRST- <16,19> TMS <16,19>
TDI <16,19> PIRQA- <19,21>
PIRQC- <15,19,21>
3VDUAL
PCIRST-1 <15,16,19,22,23,26>
GNT1- <21> PME- <15,19,21,32>
AD20
IDSEL
FRAME- <19,21,32> TRDY- <19,21,32> STOP- <19,21,32>
PAR <19,21,32>
PRSNT-31
PRSNT-32
PRSNT-41
PRSNT-42
3
C98
0.1u C105
0.1u C99
0.1u C108
0.1u
PCLK4<3>
REQ2-<19,21>
SBO3 SDONE3 SBO4 SDONE4
TCK<16,19>
TCK
PIRQC­PIRQA­PRSNT-41
PRSNT-42
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY­DEVSEL­PLOCK-
PERR­SERR­C_BE-1
AD14 AD12
AD10
AD8 AD7
AD5 AD3
AD1 ACK64-4
-12V
VCC3
VCC
RN39 1 2 3 4 5 6 7 8
8.2K
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
2
PCI4
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
PCI-D120-WH-SN
VCC3
VCC3
+12V
VCC
A1
TRST#
A2
+12V
A3
TMS
A4
TDI
A5
+5V
A6
INTA#
A7
INTC#
A8
+5V
A9
RSVD1
A10
+5V
A11
RSVD3
A12
GND
A13
GND
A14
RSVD4
A15
RST#
A16
+5V
A17
GNT#
A18
GND
A19
RSVD6
A20
AD30
A21
+3.3V
A22
AD28
A23
AD26
A24
GND
A25
AD24
A26
IDSEL#
A27
+3.3V
A28
AD22
A29
AD20
A30
GND
A31
AD18
A32
AD16
A33
+3.3V
A34
FRAME#
A35
GND
A36
TRDY#
A37
GND
A38
STOP#
A39
+3.3V
A40
SDONE
A41
SBO#
A42
GND
A43
PAR
A44
AD15
A45
+3.3V
A46
AD13
A47
AD11
A48
GND
A49
AD9
A52
C/BE0#
A53
+3.3V
A54
AD6
A55
AD4
A56
GND
A57
AD2
A58
AD0
A59
+5V
A60
REQ64#
A61
+5V
A62
+5V
Title
Size Document Number Rev Custom Date: Sheet of
TRST­TMS
TDI
PIRQB­PIRQD-
3VDUAL
PCIRST-1 GNT2­PME-
AD30 AD28
AD26 AD24
R135 100 AD22
AD20 AD18
AD16 FRAME­TRDY­STOP­SDONE4
SBO4 PAR
AD15 AD13
AD11 AD9
C_BE-0 AD6
AD4 AD2
AD0 REQ64-4
GNT2- <21>
AD21
IDSEL
MICRO-STAR
PCI CONNECTOR 3,4
MS-6501
1
18 39Thursday, July 19, 2001
0C
D D
TCK<16,19>
PIRQB-<15,19,21,32> PIRQD-<19,21>
PCLK3<3>
REQ1-<19,21>
C C
IRDY-<19,21,32>
DEVSEL-<19,21,32>
PLOCK-<19>
PERR-<19,21,32> SERR-<19,21,32>
B B
VCC3
ACK64-3 ACK64-4 REQ64-3
A A
REQ64-4
1 2 3 4 5 6 7 8
5
RN43
8.2K
Page 19
5
4
3
2
1
VCC3
VCC
AD[0..31]
C_BE-[0..3]
B1 B2 B3 B4 B5 B6 B7 B8
B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49
B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62
PCI5
-12V TCK GND TDO +5V +5V INTB# INTD# PRSNT1# RSVD2 PRSNT2# GND GND RSVD5 GND CLK GND REQ# +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3# AD23 GND AD21 AD19 +3.3V AD17 C/BE2# GND IRDY# +3.3V DEVSEL# GND LOCK# PERR# +3.3V SERR# +3.3V C/BE1# AD14 GND AD12 AD10 GND
AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64# +5V +5V
TRST#
+12V
INTA#
INTC# RSVD1 RSVD3
RSVD4
RST# GNT#
RSVD6
AD30 +3.3V AD28 AD26
AD24
IDSEL#
+3.3V AD22 AD20
AD18 AD16 +3.3V
FRAME#
TRDY# STOP#
+3.3V
SDONE
SBO#
AD15 +3.3V AD13 AD11
C/BE0#
+3.3V
REQ64#
TMS
GND GND
GND
GND
GND
GND GND
GND PAR
GND AD9
AD6 AD4 GND AD2 AD0
PCI Connector 5
TDI TMS TCK TRST-
VCC3
+12V
VCC
A1 A2 A3 A4
TDI
A5
+5V
A6 A7 A8
+5V
A9 A10
+5V
A11 A12 A13 A14 A15 A16
+5V
A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49
A52 A53 A54 A55 A56 A57 A58 A59
+5V
A60 A61
+5V
A62
+5V
TRST­TMS
TDI
PIRQC­PIRQA-
PCIRST-1 GNT3­PME-
AD30 AD28
AD26 AD24
R123 100 AD22
AD20 AD18
AD16 FRAME­TRDY­STOP­SDONE5
SBO5 PAR
AD15 AD13
AD11 AD9
C_BE-0 AD6
AD4 AD2
AD0 REQ64-5
TRST- <16,18> TMS <16,18>
TDI <16,18> PIRQC- <15,18,21>
PIRQA- <18,21>
3VDUAL
PCIRST-1 <15,16,18,22,23,26> GNT3- <21>
PME- <15,18,21,32>
AD22
IDSEL
FRAME- <18,21,32> TRDY- <18,21,32> STOP- <18,21,32>
PAR <18,21,32>
1000u/6.3V
EC32
VCC
SDONE5
-12V+12V
10u
+
C85
EC15
0.1u
3VDUAL
C116
C115
0.1u
0.1u
-
-
+
C228
0.1u
C231
0.1u
C229
0.1u
C117
0.1u
-
C227
0.1u
C80
0.1u
REQ0-<21,32> REQ1-<18,21> REQ2-<18,21> REQ3-<21> REQ4-<21> REQ5-<21> REQ6-<21>
VCC3
C92
0.1u 1000u/6.3V
EC23
+
SBO5 ACK64-5
REQ64-5 PIRQA­PIRQD­PIRQC­PIRQB-
FRAME­IRDY­TRDY­DEVSEL­STOP­PLOCK­SERR­PERR-
REQ0­REQ1­REQ2­REQ3­REQ4­REQ5­REQ6-
10u
+
C222
EC21
0.1u
C193
0.1u
RN28 1 2 3 4 5 6 7 8
8.2K
RN29
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
8.2K
RN38
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
8.2K
RN45
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
8.2K
C190
0.1u
VCC3
VCC3
5
10
VCC3
5
10
VCC3
5
10
AD[0..31]<18,21,32,37>
C_BE-[0..3]<18,21,32>
D D
-12V
TCK
TCK<16,18>
PIRQD-
PIRQD-<18,21>
PIRQB-
PIRQB-<15,18,21,32>
PRSNT-51
C C
PCLK5<3>
DEVSEL-<18,21,32>
PLOCK-<18>
B B
PRSNT-52
PCLK5 REQ3-
REQ3-<21>
AD31 AD29
AD27 AD25
C_BE-3 AD23
AD21 AD19
AD17 C_BE-2
IRDY-
IRDY-<18,21,32>
DEVSEL-
PLOCK­PERR-
PERR-<18,21,32>
SERR-
SERR-<18,21,32>
C_BE-1 AD14
AD12 AD10
AD8 AD7
AD5 AD3
AD1 ACK64-5
PCI-D120-WH-SN
A A
5
4
3
PRSNT-51
PRSNT-52
C102
0.1u C109
0.1u
Title
Size Document Number Rev Custom
2
Date: Sheet of
MICRO-STAR
PCI CONNECTOR 5,6
MS-6501
1
19 39Thursday, July 19, 2001
0C
Page 20
8
BITCLK<29>
SDIN0<29>
PD_D[0..15]<23>
C764
VCC3 VCC
D D
56p
Stitch caps
DDREQ_A<23> DDREQ_B<23> HDRDY_A<23> HDRDY_B<23> -PDCS_1 <23>
BITCLK SDIN0 SDIN1
PD_D15 PD_D14 PD_D13 PD_D12 PD_D11 PD_D10 PD_D9 PD_D8 PD_D7 PD_D6 PD_D5 PD_D4 PD_D3 SD_D3 PD_D2 PD_D1 PD_D0
VCC_LDT
C C
B B
A A
R545 10K
8
LDTCOMP0 LDTCOMP1 LDTCOMP2 LDTCOMP3
LRXCAD_N0 LRXCAD_N1 LRXCAD_N2 LRXCAD_N3 LRXCAD_N4 LRXCAD_N5 LRXCAD_N6 LRXCAD_N7
LRXCAD_P0 LRXCAD_P1 LRXCAD_P2 LRXCAD_P3 LRXCAD_P4 LRXCAD_P5 LRXCAD_P6 LRXCAD_P7
LRXCLK_N LRXCLK_P LRXCTL_N LRXCTL_P
7
U22A
AC25
ACCLK
AB26
ACSDI0
Y25
ACSDI1
C14
DDATA_P15
A16
DDATA_P14
C16
DDATA_P13
B17
DDATA_P12
A18
DDATA_P11
B19
DDATA_P10
A20
DDATA_P9
C20
DDATA_P8
A21
DDATA_P7
B20
DDATA_P6
C19
DDATA_P5
A19
DDATA_P4
C17
DDATA_P3
A17
DDATA_P2
B16
DDATA_P1
A15
DDATA_P0
B14
DDRQP
D14
DDRQS
C18
DRDYP
C12
DRDYS
T1
VLDT0
M4
VLDT1
D2
LDTCOMP0
G5
LDTCOMP1
L3
LDTCOMP2
L4
LDTCOMP3
E5 D3
LDTREQ# LDTSTOP#
E1
LRXCAD_N0
F2
LRXCAD_N1
H2
LRXCAD_N2
J1
LRXCAD_N3
G4
LRXCAD_N4
J5
LRXCAD_N5
J4
LRXCAD_N6
L5
LRXCAD_N7
D1
LRXCAD_P0
F3
LRXCAD_P1
H3
LRXCAD_P2
H1
LRXCAD_P3
G3
LRXCAD_P4
H5
LRXCAD_P5
J3
LRXCAD_P6
K5
LRXCAD_P7
G1
LRXCLK_N
F1
LRXCLK_P
K2
LRXCTL_N
K3
LRXCTL_P
ACRST#
ACSDO
ACSYNC
DDATA_S15 DDATA_S14 DDATA_S13 DDATA_S12 DDATA_S11 DDATA_S10
DDATA_S9 DDATA_S8 DDATA_S7 DDATA_S6 DDATA_S5 DDATA_S4 DDATA_S3 DDATA_S2 DDATA_S1 DDATA_S0
DDACKP# DDACKS#
DCS1P# DCS3P# DCS1S# DCS3S#
DIOWP# DIOWS#
DIORS# DIORP#
DADDR_P2 DADDR_P1 DADDR_P0 DADDR_S2 DADDR_S1 DADDR_S0
DRSTP# DRSTS#
LTXCAD_N0 LTXCAD_N1 LTXCAD_N2 LTXCAD_N3 LTXCAD_N4 LTXCAD_N5 LTXCAD_N6 LTXCAD_N7
LTXCAD_P0 LTXCAD_P1 LTXCAD_P2 LTXCAD_P3 LTXCAD_P4 LTXCAD_P5 LTXCAD_P6 LTXCAD_P7
LTXCLK_N LTXCLK_P LTXCTL_N LTXCTL_P
opus_AMD768
LRXCAD_N7 LRXCAD_P7 LDTCOMP3 LDTCOMP2 LRXCTL_N LRXCAD_P6 LRXCAD_N3 LRXCTL_P
LRXCAD_P4 LRXCLK_N LRXCLK_P LRXCAD_N1 LRXCAD_N0 LDTCOMP0 LRXCAD_P2 LRXCAD_P1
LRXCAD_N4 LRXCAD_P5 LDTCOMP1 LRXCAD_N5 LRXCAD_N2 LRXCAD_P3 LRXCAD_P0 LRXCAD_N6
RN277
1
5
1
2
2
3
3
4
4
6
6
7
7
8
8
9
10
9510
10K RN278
1
5
1
2
2
3
3
4
4
6
6
7
7
8
8
9
10
9510
10K RN279
1
5
1
2
2
3
3
4
4
6
6
7
7
8
8
9
10
9510
10K
7
AC26 AB24 Y22
A7 B8 A9 B10 C11 A11 C13 A13 A14 B13 A12 B11 A10 C10 A8 C8
E17 E12
C15 E14 C9 E9
D19 D13 E13 E18
E15 E16 D16 E10 E11 D10
D8 E8
T3 P1 M1 M3 R5 R4 N5 N4
T2 R1 N1 M2 T5 R3 P5 N3
P3 P2 K1 L1
SD_D15 SD_D14 SD_D13 SD_D12 SD_D11 SD_D10 SD_D9 SD_D8 SD_D7 SD_D6 SD_D5 SD_D4
SD_D2 SD_D1 SD_D0
-DDACK_A
-DDACK_B
-PDCS_1
-PDCS_3
-SDCS_1
-SDCS_3
-DIOW_A
-DIOW_B
-DIOR_B
-DIOR_A
PD_A2 PD_A1 PD_A0 SD_A2 SD_A1 SD_A0
HDRESET1­HDRESET2-
SDIN0 SDIN1
6
RN276
8P4R-22
6
12 56 34 78
SD_D[0..15] <23>
-DDACK_A <23>
-DDACK_B <23>
-PDCS_3 <23>
-SDCS_1 <23>
-SDCS_3 <23>
-DIOW_A <23>
-DIOW_B <23>
-DIOR_B <23>
-DIOR_A <23>
PD_A[2..0] <23>
SD_A[2..0] <23>
HDRESET1- <23> HDRESET2- <23>
RN70 1 2 3 4 5 6 7 8
10K
ACRST- <29> SDOUT <29> SYNC <29>
5
4
3
2
1
U22B
A1
VSS0
AA20 AA21 AA25
AD25 AE12 AE15 AE18 AE21 AE24
AF26
A26
VSS1
AA2
VSS2 VSS3 VSS4 VSS5
AA6
VSS6
AA7
VSS7
AD2
VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14
AE3
VSS15
AE6
VSS16
AE9
VSS17
AF1
VSS18 VSS19
B12
VSS20
B15
VSS21
B18
VSS22
B21
VSS23
B24
VSS24
B3
VSS25
B6
VSS26
B9
VSS27
C2
VSS28
C25
VSS29
D4
VSS30
E2
VSS31
F20
VSS32
F21
VSS33
F25
VSS34
F4
VSS35
F6
VSS36
F7
VSS37
G2
VSS38
G21
VSS39
G6
VSS40
H4
VSS41
J2
VSS42
J25
VSS43
K4
VSS44
L11
VSS45
L12
VSS46
L13
VSS47
L14
VSS48
L15
VSS49
L16
VSS50
L2
VSS51
M11
VSS52
M12
VSS53
M13
VSS54
M14
VSS55
M15
VSS56
M16
VSS57
M25
VSS58
M5
VSS59
N11
VSS60
N12
VSS61
N13
VSS62
N14
VSS63
N15
VSS64
N16
VSS65
N2
VSS66
P11
VSS67
P12
VSS68
P13
VSS69
P14
VSS70
P15
VSS71
P16
VSS72
P4
VSS73
R11
VSS74
R12
VSS75
R13
VSS76
R14
VSS77
R15
VSS78
R16
VSS79
R2
VSS80
R25
VSS81
T11
VSS82
T12
VSS83
T13
VSS84
T14
VSS85
T15
VSS86
T16
VSS87
T4
VSS88
V2
VSS89
V25
VSS90
Y21
VSS91
Y6
VSS92
VDD_AUX2 VDD_AUX3
VDD_REF VDD_RTC
VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3 VDD3
VDD3 VDD_CORE0 VDD_CORE1 VDD_CORE2 VDD_CORE3 VDD_CORE4 VDD_CORE5 VDD_CORE6 VDD_CORE7 VDD_CORE8 VDD_CORE9
VDD_CORE10 VDD_CORE11 VDD_CORE12 VDD_CORE13 VDD_CORE14 VDD_CORE15 VDD_CORE16 VDD_CORE17 VDD_CORE18 VDD_CORE19 VDD_CORE20 VDD_CORE21 VDD_CORE22 VDD_CORE23
NC0 NC1
NC2 SPARE_0 SPARE_1 SPARE_2 SPARE_3 SPARE_4 SPARE_5 SPARE_6 SPARE_7 SPARE_8 SPARE_9
SPARE_10 SPARE_11 SPARE_12 SPARE_13 SPARE_14 SPARE_15 SPARE_16 SPARE_17 SPARE_18
R24 P23
C23 P25
AA23 AA4 AC12 AC15 AC18 AC21 AC23 AC4 AC6 AC9 D12 D15 D18 D21 D23 D6 D9 F23 J23 M23 R23 V23 V4 AA10 AA17 AA18 AA19 AA8 AA9 F10 F17 F18 F19 F8 F9 H21 H6 J21 J6 K21 K6 U21 U6 V21 V6 W21 W6
AE26 F5 U1 V26 Y24 P24 AB25 U26 H25 E22 E19 E20 D20 AD22 AE8 AF8 AF7 V1 C1 AC22 B1 B22
VCC3
2_5VDUAL 3VDUAL
5VSB VBAT
EC86 10u
C822
0.1u
C823
0.1u
C824 1000p
C825 1000p
3VDUAL
C826
0.022u
R617
40.2
R618 127
C827
0.022u
EC88
10u
+
C828
0.022u
C829
0.022u
C816
0.22u
2_5VDUAL 3VDUAL
C818
0.22u
C819
0.01u
C817
0.01u
VCC_OPUS2_5
C831
C830
4.7u-0805
0.022u
C814
0.22u
C820
0.22u
VBAT
C815
0.01u
5VSB
C821
0.01u
opus_AMD768
Title
Size Document Number Rev
5
4
3
Date: Sheet of
2
MICRO-STAR
AMD-768 (Part1)
MS-6501
20 39Wednesday, July 25, 2001
1
0A
Page 21
8
7
6
5
4
3
2
SR_A_AD[31..0] <16,17>
1
VCC3
R547
4.7K
R549 X_0
AD[31..0] <18,19,32,37>
TP23
TP22
21 39Wednesday, July 25, 2001
1
A_REQ-0 <11,17>
A_ISAREQ- <11>
0A
VCC3
C252
0.1u
1 2 3 4 6 7 8 9
1 2 3 4 6 7 8 9
R468
4.7K
RN280
1 2 3 4 6 7 8 9510
10K
RN282
1 2 3 4 6 7 8 9510
10K
FERR-
R555 Should be placed near NB
SR_A_DEVSEL-<16,17>
SR_A_FRAME-<16,17>
A_GNT-0<11>
A_M66EN<11,16>
VCC3
5
10
5
VCC3
R565
10K
10
LOW = NO INTERNAL PULLUPS ENABLED HIGH = INTERNAL PULLUPS ENABLED
USB_VCC
EC35 10u
FB12
0_0805
4
SR_A_CBE-[3..0]<16,17>
VCC3
SPKR<27>
3VDUAL
SR_A_DEVSEL-
SR_A_FRAME­R555 33 SR_A_AD27 SR_A_AD18
A_M66EN
SR_A_PAR<16,17> SR_A_SERR-<16,17>
SR_A_IRDY-<16,17>
SR_A_TRDY-<16,17>
C_BE-[3..0]<18,19,32>
USBOC-1<28>
USBOC-0<28>
USBCLK<3>
C832
4.7u-0805
SR_A_STOP-<16,17>
DEVSEL-<18,19,32>
LFRAME-<22,26>
LAD[3..0]<22,26>
R567 X_200
SPKR
R568 1K
VCC3
SR_A_GNT-0 R648 100 R649 100
PIRQA-<18,19> PIRQB-<15,18,19,32> PIRQC-<15,18,19> PIRQD-<18,19>
FRAME-<18,19,32>
IRDY-<18,19,32>
TRDY-<18,19,32>
STOP-<18,19,32>
PAR<18,19,32>
PERR-<18,19,32>
REQ0-<19,32> REQ1-<18,19> REQ2-<18,19> REQ3-<19> REQ4-<19> REQ5-<19> REQ6-<19>
OSC<3>
LDRQ-0<22>
RN293 1 2 3 4 5 6 7 8
10K
SR_A_CBE-0
SR_A_CBE-1
AB1
A_CBE_L0
AF3
REQ0­REQ1­REQ2­REQ3­REQ4­REQ5­REQ6-
TCK TDI
TMS
AE7 AB4 AE5 AD7 AB6
AB3 AD4 AE4 AF6 AD5 AF5
AF15 AF11 AB11 AB17 AE19 AE25 AD19 AF19 AE11 AD11 AF10 AD24 AE10
AD9 AD10 AE20 AF21 AF22 AF23 AF25 AD21 AA22
AB20
M26
M24
D26
M22
G24
G22
C21
C22
D22
W4
V3
K23 L24 L23 L26 L25 N26
N25 K24
J26 K26 N22
F22 L22 H26
F26
J24
Y23 T22
A22 A24
B25 B23
A_CBE_L1 A_CBE_L2 A_CBE_L3 A_DEVSEL# A_FRAME# A_GNT# A_IDSELA A_IDSELB A_M66EN A_PAR A_SERR# A_IRDY# A_STOP# A_TRDY#
CBE_L3 CBE_L2 CBE_L1 CBE_L0 PIRQA# PIRQB# PIRQC# PIRQD# FRAME# IRDY# TRDY# STOP# DEVSEL# PAR PERR# REQ0# REQ1# REQ2# REQ3# REQ4# REQ5# REQ6#
PREQ#
USBOC1# USBP0 USBN0 USBP1 USBN1 USBP2 USBN2 USBP3 USBN3 USBOC0# USBCLK VSS_USB VDD_USB
OSC LFRAME#
LAD3 LAD2 LAD1 LAD0 LDRQ1# LDRQ0#
PCREQA# PCREQB# SPKR
TEST# STMODE PLLSTOP#
TCK TDI TDO TMS
SR_A_CBE-2 SR_A_CBE-3
SR_A_PAR SR_A_SERR­SR_A_IRDY­SR_A_STOP­SR_A_TRDY-
C_BE-3 C_BE-2 C_BE-1 C_BE-0
PIRQA­PIRQB­PIRQC­PIRQD­FRAME­IRDY­TRDY­STOP­DEVSEL­PAR PERR-
PREQ-
USBOC-1
SR_USBP0 SR_USBN0 SR_USBP1 SR_USBN1 SR_USBP2 SR_USBN2 SR_USBP3 AD6
SR_USBN3 USBOC-0 USBCLK
USB_VCC
OSC
LFRAME-
LAD3
LAD2 LAD1 LAD0
LDRQ-1
LDRQ-0
SB_TEST­STMODE PLLSTOP-
A_REQ#
A_ISAREQ#
A_AD31 A_AD30 A_AD29 A_AD28 A_AD27 A_AD26 A_AD25 A_AD24 A_AD23 A_AD22 A_AD21 A_AD20 A_AD19 A_AD18 A_AD17 A_AD16 A_AD15 A_AD14 A_AD13 A_AD12 A_AD11 A_AD10
A_AD9 A_AD8 A_AD7 A_AD6 A_AD5 A_AD4 A_AD3 A_AD2 A_AD1 A_AD0
GNT0# GNT1# GNT2# GNT3# GNT4# GNT5# GNT6#
PGNT#
PCGNTA# PCGNTB#
FREQ_OUT_N FREQ_OUT_P
opus_AMD768
U22D
C833
0.022u
C834
0.022u
C835
0.022u
C836
0.022u
C837
0.022u
Title
Size Document Number Rev
3
Date: Sheet of
2
AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10
R670 33
SR_A_REQ-0
AF4
SR_A_ISAREQ-
AD8
SR_A_AD31
AC8
SR_A_AD30
AB8
SR_A_AD29
AC7
SR_A_AD28
AB7
SR_A_AD27
AD6
SR_A_AD26
AC5
SR_A_AD25
AB5
SR_A_AD24
AA5
SR_A_AD23
AA3
SR_A_AD22
AD3
SR_A_AD21
Y5
SR_A_AD20
W5
SR_A_AD19
Y4
SR_A_AD18
V5
SR_A_AD17
U5
SR_A_AD16
U4
SR_A_AD15
AF2
SR_A_AD14
AE2
SR_A_AD13
AE1
SR_A_AD12
AD1
SR_A_AD11
AC2
SR_A_AD10
AC3
SR_A_AD9
AC1
SR_A_AD8
AB2
SR_A_AD7
AA1
SR_A_AD6
Y3
SR_A_AD5
Y2
SR_A_AD4
W3
SR_A_AD3
Y1
SR_A_AD2
W2
SR_A_AD1
W1
SR_A_AD0
U3
AD31
AF18 AD17
AD30 AD29
AE17
AD28
AF17
AD27
AD16
AD26
AF16 AE16
AD25 AD24
AD14
AD23
AE14
AD22
AF14
AD21
AC14 AF13
AD20 AD19
AC13
AD18
AE13
AD17
AD13
AD16
AF12 AC10
AD15 AD14
AC11
AD13
AB12
AD12
AB13
AD11
AD12 AB21
AD10 AD9
AB14
AD9
AD8
AB19
AD8
AD7
AC19
AD7
AC16
AD6
AC17
AD5
AD5
AD4
AD15
AD4
AD3
AB18
AD3
AD2
AB15
AD2
AD1
AD18
AD1
AB16
AD0
AD0
GNT0-
AF20 AD20 AE22 AE23 AF24 AD23 AB22
GNT1­GNT2­GNT3-
GNT0- <32> GNT1- <18> GNT2- <18> GNT3- <19>
AC20 AC24
AA24
FREQ_OUT_N
E4
FREQ_OUT_P
E3
MICRO-STAR
AMD-768 (Part2)
MS-6501
U22C
INIT# INTR
SMI#
A20M-
A2 W24 C6 C5 A4 B5 E7
NMI
D5 T26
V22 U22
D24
G23 K22 B4 W25 C7 A25 T24 P22 C24 G26 E25 F24 E21
K25 AB9 AB10 B7 D7 E23 A23 H22 Y26 C4
CPURST­IGNNE­CPUINIT­INTR
NMI SMI-
C32KHZ
RAM_PWR
SB_PWRON-
IRQ8
CPUSTOP­DCSTOP­PCISTP­SUSPEND­SMBCLK SMBDATA
THERM_OVL-
SERIAL_IRQ
SQWAVE
A_INTD­A_INTC­A_INTB­A_INTA­PD_80P SD_80P
GPIO17 GPIO16 GPIO14 GPIO8
A20M- <4,6> CPURST- <4,6> IGNNE- <4,6> CPUINIT- <4,6> INTR <4,6> STPCLK- <4,6> NMI <4,6> SMI- <4,6>
C32KHZ <22>
RAM_PWR <31>
R650 0
CPUSTOP- <3> DCSTOP- <12> PCISTP- <3>
TP17
SMBCLK <3,13,14,22,33> SMBDATA <3,13,14,22,33> THERM_OVL- <22>
SERIAL_IRQ <22>
TP24
A_INTD- <16,17> A_INTC- <16,17> A_INTB- <16,17> A_INTA- <16,17> PD_80P <23> SD_80P <23>
PWRON- <27>
APICD1-<4,6> APICD0-<4,6>
APICCLK<3,4,6>
WSC-<11>
C786 18p
PME-<15,18,19,32>
GA20<22>
KBRST<22>
Y6
YCRY32.768C
RI-<24>
INTRUDER-<22>
SIO_PME-<22>
VBAT
SLPBTN-<27>
R608 0
D D
PCI_66CLK2<11>
SBCLK<3>
1 2 C785 18p
VBAT
R561
A_PCI_PME-<16>
10M
1
1
2
2
JCASE
C C
D1x2-BK
PCIRST-<23>
FERR-
R554X_10M
SLPBTN-
PWRBTN-<22>
PWROK<27,33>
IRQ15<23> IRQ14<23>
SMBALERT-
OPUS_PME-
PCIRST­SERR-
SERR-<18,19,32>
C3
FERR#
A3
PICD1#
A5
PICD0#
E6
PICCLK
U2
IRQ12 IRQ1 IRQ6
AD26
AA26
AB23
W22
N23 N24
T25 U24 U23
D11 D17
J22 H24 H23
E26
G25
U25 V24
P26
W23 W26
R22
E24
R26
C26 D25
B26 T23
AF9
B2
A6
WSC# PRDY
PCLK66 PCLK RTCX_IN RTCX_OUT
SLPBTN# PWRBTN# PWROK
IRQ15 IRQ14 IRQ12 IRQ1 IRQ6
KA20G KBRC#
EXTSMI# RI# PME#
INTRUDER# LID BATLOW# CLKRUN#
SMBALERT# FANRPM ACAV
AGPSTOP# PNPIRQ0
PNPIRQ1 PNPIRQ2
RESET# SERR#
PRDY STPCLK-
RTCX_IN RTCX_OUT
INTRUDER­LID BATLOW­CLKRUN-
FANRPM
A20M#
CPURST#
IGNNE#
STPCLK#
C32KHZ
RPWRON
PWRON#
INTIRQ8#
CACHE_ZZ
CPUSLEEP#
CPUSTOP#
DCSTOP# PCISTOP#
SUSPEND#
SMBUSC SMBUSD
THERM#
SERIRQ FANCON0 FANCON1
SQWAVE
GPIO31 GPIO30 GPIO29 GPIO28 GPIO27 GPIO26 GPIO17 GPIO16 GPIO14
GPIO8
opus_AMD768
VCC3
RN281
1
5
1
2
2
3
3
4
4
6
6
7
7
8
8
9
10
9510
10K
3VDUAL
RN284
1
5
1
2
2
3
3
4
4
6
6
7
7
8
8
9
10
9510
10K
VCORE
R494 680
R469 470
VCORE
NPN-3904LT1-S-SOT23
R495 680
R471 470
NPN-3904LT1-S-SOT23
PWRON DELAY CIRCUIT FOR HOT PLUGGING
6
PLLSTOP­SB_TEST­CLKRUN-
IRQ8
PREQ-
GPIO17 GPIO16
GPIO8
SLPBTN­OPUS_PME­BATLOW-
PME­SMBALERT­A_PCI_PME-
LID
GPIO14
FERR_P0<4>
FERR_P1<6>
SR_USBP2 SR_USBN2 SR_USBP3 SR_USBN3
B B
78
RN51
33
123456
CN13
USBP2
12
USBN2
34
USBP3
56
USBN3
78
RN52
15K
12 34 56 78
47p
R573 X_90.9
C843 56p
RN49
15K
R574 160
78 56 34 12
VCC_OPUS2_5
R575 160
C844 56p
C793
0.01u
SR_USBP0 SR_USBN0 SR_USBP1 SR_USBN1
123456
A A
USBP0 USBP1 USBP2 USBP3
USBN0 USBN1 USBN2 USBN3
USBP[0..3]
USBN[0..3]
8
USBP[0..3] <28>
USBN[0..3] <28>
RN48
33
78
CN12
47p
USBP0
78
USBN0
56
USBP1
34
USBN1
12
APICD[0..1]- 6" longer than APICCLK from SB to CPU1
APICCLK APICD1­APICD0-
7
FANRPM
SERIAL_IRQ IRQ1 IRQ6 IRQ12
THERM_OVL-
PRDY PD_80P SD_80P STMODE
Q62
C
B
E
Q63
C
B
E
5
Page 22
5
Place under CPU1
VREF VAGND
D D
C C
VCC2_5 VCORE
+12V
R592 28KST
-12V
R591 232KST
-5V
R590 120KST
B B
A A
R310
10KST
R311
10KST
R625
10KST
R626 0-REV R627 0
VAGND
VCC
t
VTIN2
Place under CPU2
t
VTIN3
RT3
YT103S-1N
VTIN1
VCOREB
R589 56K
R593 10K
FB25
80-0805
FB26
VACC
80-0805
VAGND
C806
0.1u
RT2 10K
RT1 10K
+12VIN
-12VIN
-5VIN
+ EC87
12
R581 10K
R588 56K
VAGND
VAGND
VREF
10U/16V
VCC3
R582 10K
R583 10K
VREF
VAGND VTIN2
VAGND
VTIN3
R584 10K
4
R472 0 R473 0
R474 0
R475 0
UVID[0..4]<33,34>
3
P0_THERMADC <5>
NOPOP
P0_THERMADA <5>
NOPOP
P1_THERMADC <7>
NOPOP
P1_THERMADA <7>
NOPOP
PCIRST-1<15,16,18,19,23,26>
SIO_PCLK<3>
SERIAL_IRQ<21>
LDRQ-0<21>
LFRAME-<21,26>LAD[3..0]<21,26>
JBX<30>
JAY<30> JAB1<30> JAB2<30>
JAX<30>
JBY<30> JBB1<30> JBB2<30>
TXD<30> RXD<30>
VREF VTIN3 VTIN2 VTIN1 VAGND
-5VIN
-12VIN +12VIN
VCC3
VCORE
FAN_ON2<26>
SYSFAN<26>
FAN_ON<26> CPUFAN2<26> CPUFAN1<26>
THERM_OVL-<21> BEEP<27>
INTRUDER-<21>
SIO_PME-<21> ROMLOCK<26>
SMBDATA<3,13,14,21,33>
PWRBTN-<21>
PSON-<27>
SIO_CLK48<3>
VAVCC
VCOREB
UVID4 UVID3 UVID2 UVID1 UVID0
SMBCLK<3,13,14,21,33>
PWRSW-<27> SUSLED<27>
PWRLED<27>
TP30
Place RT2 under CPU1
Place RT1 under CPU2
VCCVCC3 5VDUAL
1220
30
LRESET#
21
LCLK
23
SERIRQ
22
LDRQ#
29
LFRAME#
LAD0
27
LAD0
LAD1
26
LAD1
LAD2
25
LAD2
LAD3
24
LAD3
125
GPX2/P15/GP14
123
GPY1/GP15
128
GPSA1/P12/GP10
121
GPSA2/GP17
126
GPX1/P14/GP12
124
GPY2/P16/GP14
127
GPSB1/P13/GP11
122
GPSB2/GP16
120
MSO/IRQIN0
119
MSI/GP20
101
VREF
102
VTIN3
103
VTIN2
104
VTIN1
93
AGND
94
-5VIN
95
-12VIN
96
+12VIN
97
AVCC
98
+3.3VIN
99
VCOREB
100
VCOREA
106
VID4
107
VID3
108
VID2
109
VID1
110
VID0
116
FANPWM1
113
FANIO1
115
FANPWM2
112
FANIO2
111
FANIO3
105
OVT#
118
BEEP
76
CASEOPEN#
19
PME#
89
WDTO/GP24
91
SDA/GP22
92
SCL/GP21
67
PSOUT#
68
PSIN
64
SUSLED/GP35
90
PLED/GP23
72
PWRCTL#/GP31
73 70
SUSCIN/GP30 RSMRST#/GP33
18
CLKIN
28
VCC3
48771146174
VTR
VCCVSS
VCC
VCC
VSS
VSS
VSS
5586117
VSB
VBAT
VBAT
HEAD#/HDSEL#
DRVDEN0 DRVDEN1
INDEX#
MOA#/MTRA#
DSB# DSA#
MOB#/MTRB#
DIR#
STEP#
WRDATA#
WE#
TRACK0#
WRTPRT#
RDATA#
DSKCHG#
SLCT BUSY
ACK#
SLCTIN#
INIT#
ERROR#
ALF#
STROBE#
IRRX/GP25
CIRRX/GP34
IRTX/GP26 SUSCLKIN
DCDA# DSRA#
SINA/RXDA
RTSA#
SOUTA/TXDA
CTSA# DTRA#
RIA# DCDB# DSRB#
SINB/RXDB
RTSB#
SOUTB/TXDB
CTSB# DTRB#
RIB#
GA20/A20M
KBRST
KBDATA
KBCLK
MSDATA
MSCLK
KBLOCK#
PWROK/GP32
W83627HF
U33
1 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17
PD0
42
PD0
PD1
41
PD1
PD2
40
PD2
PD3
39
PD3
PD4
38
PD4
PD5
37
PD5
PD6
36
PD6
PD7
35
PD7
31 32
PE
33 34 43 44 45 46 47
88 69 87 75
56 50 53 51 54 49 52 57 84 79 82 80 83 78 81 85
59 60 63 62 66 65 58
71
FDD_WP-
TP31
2
PD6
PD7
VCC3 VCC
C804
C803
0.1u
0.1u
IRRX <27> CIRRX <27> IRTX <27> C32KHZ <21>
RN287 1 2 3 4 5 6 7 8
10K
C805
22u
DRVDEN0 INDEX-
MTR0­DS1­DS0­MTR1­DIR­STEP­WDATA­WGATE­TR0-
RDATA­HDSEL­DSKCHG-
SLCT <24> PE <24> BUSY <24> ACK- <24> SLIN- <24> INIT- <24> ERR- <24> AFD- <24> STB- <24>
DCDA- <24> DSRA- <24> SINA <24> RTSA- <24> SOUTA <24> CTSA- <24> DTRA- <24> RIA- <24> DCDB- <24> DSRB- <24> SINB <24> RTSB- <24> SOUTB <24> CTSB- <24> DTRB- <24> RIB- <24>
GA20 <21> KBRST <21> KDAT <25> KCLK <25> MDAT <25> MCLK <25> KBLOCK- <27>
HM_PWROK <27>
VCC
C801
0.1u
FDD_WP-<33>
PD[7..0] <24>
SOUTA
SOUTB
RTSA-
DTRA-
1
WPORT-
C802
0.1u
SOUTA
SOUTB
RTSA-
DTRA-
FDD_WP-
FDD1
N32-2172021
R579 4.7K
R598 4.7K
R596 4.7K
R597 4.7K
INDEX-
TR0­DSKCHG­RDATA-
A C
12
34
56
78
910
1112 1314 1516 1718 1920 2122 2324 2526 2728 2930 3132 3334
RN117 1K 1 2 3 4 5 6 7 8
R385 1K
D16
1N4148-S-LL34
VCC3
L:Disable KBC H:Enable KBC
H:48MHzL:24MHz
H:CFAD=4EL:CFAD=2E
L:PNP Default H:PNP no Default
VCC
WPORT-
Title
Size Document Number Rev
Custom
5
4
3
2
Date: Sheet of
MICRO-STAR
LPC SIO MS-6501
1
22 39Wednesday, July 25, 2001
0A
Page 23
5
4
3
2
1
D D
PD_D[0..15]<20> SD_D[0..15]<20>
C C
B B
A A
5
PD_D[0..15] SD_D[0..15]
RN84
PDA2PD_A2
7
PD_A2<20>
PD_A0
PD_A0<20>
-PDCS_1
-PDCS_1<20>
-PDCS_3
-PDCS_3<20>
PD_D8 PDD8 PD_D7 PDD7 PD_D9 PDD9 PD_D6 PDD6
PD_D12 PD_D3 PD_D13 PDD13 PD_D2 PDD2
PD_D10 PDD10 PD_D5 PDD5 PD_D11 PDD11 PD_D4 PDD4
PD_D0 PD_D15 PD_D1 PD_D14 -DIORB
PCIRST-<21>
PCIRST-
5 3 1
7 5 3 1
7 5 3 1
7 5 3 1
33 1 3 5 7
33
RN129
33
RN121
33
RN125
33
RN115
8
PDA0
6
-PDCS1
4
-PDCS3
2
8 6 4 2
PDD12
8
PDD3
6 4 2
8 6 4 2
PDD0
2
PDD15
4
PDD1
6
PDD14
8
3VDUAL
U17B
147
3 4
SN74LVC14A-SOIC14
4
U17A
147
1 2
SN74LVC14A-SOIC14
U17C
147
5 6
SN74LVC14A-SOIC14
U17D
147
9 8
SN74LVC14A-SOIC14
-DDACK_A<20> HDRDY_A<20>
DDREQ_A<20>
DDREQ_B<20>
-DDACK_B<20> HDRDY_B<20>
SD_D14 SD_D1 SD_D15 SD_D0
SD_D10 SD_D5 SD_D11 SD_D4
SD_D8 SD_D7 SD_D9 SD_D6
SD_D12 SD_D3 SDD3 SD_D13 SD_D2
PD_A1
PD_A1<20>
-DDACK_A
-DIOR_A
-DIOR_A<20>
HDRDY_A
-SDCS_1
-SDCS_1<20>
-SDCS_3
-SDCS_3<20> SD_A0
SD_A0<20>
SD_A2
SD_A2<20>
DDREQ_A
-DIOW_A
-DIOW_A<20>
-DIOW_B
-DIOW_B<20>
DDREQ_B
SD_A1
SD_A1<20>
-DDACK_B -DDACKB
-DIOR_B
-DIOR_B<20>
HDRDY_B
PCIRST-1
PCIRST-2
RN118
SDD14
1
2
SDD1SDD1
3
4
SDD15
5
6
SDD0
7
8
33
RN127
SDD10
1
2
SDD5
3
4
SDD11
5
6
SDD4
7
8
33
RN131
SDD8
1
2
SDD7
3
4
SDD9
5
6
SDD6
7
8
33
RN122
SDD12
1
2
3
4
SDD13
5
6
SDD2
7
8
33
RN110
PDA1
1
2
-DDACKA
3
4
-DIORA
5
6
HDRDYA
7
8
33
RN83
-SDCS1
1
2
-SDCS3
3
4
SDA0
5
6
SDA2
7
8
33
RN113
DDREQA
1
2
-DIOWA
3
4
-DIOWB
5
6
DDREQB
7
8 33 RN111
SDA1
1
2
3
4
5
6
HDRDYB
7
8
33
PCIRST-1 <15,16,18,19,22,26>
C204 4700p
PCIRST-2 <11,13,32,33>
C203 4700p
All series Res. should be very close SB
VCC
VCC
R367 1K
10K
R369
R277
VCC
R256
1K
R362
R634 33
DDREQA
VCC
R404
4.7K
R635 33
VCC
DDREQB
5.6K
5.6K
R383
10K
R384
10K
SD_D7
2
VCC
R402
4.7K
-DASP0
-DASP1
HDRESET1-<20>
HDRDYA
IRQ14<21>
HDRESET2-<20>
HDRDYB
IRQ15<21>
PD_D7
R401
10K
3
ATA33/66/100
IDERST1­PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD13 PDD1 PDD14 PDD0 PDD15
-DIOWA
-DIORA
-DDACKA PDA1
PDA0
-PDCS1
IDERST2-
SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0
-DIOWB
-DIORB
-DDACKB SDA1
SDA0
-SDCS1
-DASP1
IDE1
1
2 3 4 5 6 7 8 91110
12
13 14
1615
17 18 19 20
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
4039 D2x20-1:21-BL
1N4148-S-LL34
D18 D19
1N4148-S-LL34
IDE2
1
2 3 4 5 6 7 8 91110
12
13 14
1615
17 18 19 20
22
21
24
23
26
25
28
27
30
29
32
31
34
33
36
35
38
37
4039 D2x20-1:21-WH
VCC
C232
C226
0.1u
104P-REV
Title
Size Document Number Rev Custom Date: Sheet of
PDD8 PDD9 PDD10 PDD11 PDD12
R371
470
PD_80P <21>
PDA2
-PDCS3
HD_LED1 <27>
SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15
R373
470
SD_80P <21>
SDA2
-SDCS3
C230
C368
0.1u
0.1u
MICRO-STAR
ATA33/66 Connectors
MS-6501
1
23 39Thursday, July 19, 2001
0A
Page 24
8
7
6
5
4
3
2
1
VCC
PD[0..7]
PD[0..7]<22>
RN18 33
ACK-
ACK-<22>
BUSY<22>
PE<22>
D D
SLCT<22>
ERR-<22>
INIT-<22> SLIN-<22>
AFD-<22>
BUSY PE SLCT
PD3 ERR­INIT-
PD0 PD1 PD2 AFD-
PD4 PD5 PD6 PD7
1 2 3 4 5 6 7 8
RN20 33 1 2 3 4 5 6 7 8
RN21 33 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
PRND3
PRND0 PRND1 PRND2
PRND4 PRND5 PRND6 PRND7
RN19 33
STB-<22>
C C
R23 33
RSTB-
RACK­RBUSY RPE RSLCT
RERR­RINIT­RSLIN-
RAFD-
CN6 180p 1 2 3 4 5 6 7 8
CN8 180p 1 2 3 4 5 6 7 8
CN9 180p 1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
CN7 180p
C43 180p
PRND7 PRND6 PRND5 PRND4
PRND2 PRND1 PRND0
PRND3
RSTB-
RSLCT RPE RBUSY RACK-
RAFD-
RSLIN­RINIT­RERR-
R35 2.2K
1 2 3 4 6 7 8 9
1 2 3 4 6 7 8 9
1N4148-S-LL34
RN26
1 2 3 4 6 7 8 9510
2.2K RN27
1 2 3 4 6 7 8 9510
2.2K
CGNDCGND
D6
NDTRB NSINB NSOUTB NDCDB-
5
CN10 1 2 3 4 5 6 7 8
CGND
180p
NRIB­NCTSB­NDSRB-
10
NRTSB
5
CGND
10
CGNDSTB-
C67
0.1u
CN11 1 2 3 4 5 6 7 8
180p
CN4
7 8 5 6 3 4 1 2
180p
CN5
7 8 5 6 3 4 1 2
180p
NRIA­NCTSA­NDSRA­NRTSA
NDTRA NSINA NSOUTA NDCDA-
CGND
NDCDA­NDSRA­NSINA NRTSA NSOUTA NCTSA­NDTRA NRIA-
LPT1
26 31 27 32 28 33 29 34 30
49
48
C66
0.1u
+12V
B B
-12V
D3 1N4148-S-LL34
RTSA- NRTSA
RTSA-<22>
DTRA- NDTRA
DTRA-<22>
SOUTA NSOUTA
SOUTA<22>
RIA- NRIA-
RIA-<22>
CTSA- NCTSA-
CTSA-<22>
DSRA- NDSRA-
DSRA-<22>
SINA NSINA
SINA<22>
DCDA- NDCDA-
DCDA-<22>
D5
1N4148-S-LL34
C69
0.1u
RTSB-
RTSB-<22>
DTRB-
DTRB-<22>
SOUTB
SOUTB<22>
RIB-
RIB-<22>
CTSB-
CTSB-<22>
DSRB-
DSRB-<22>
SINB
SINB<22>
DCDB-
DCDB-<22>
U9
1
VDD(12V)
16
DA1
15
DA2
13
DA3
19
RA1
18
RA2
17
RA3
14
RA4
12
RA5
10
VSS(-12V)
TI-GD75232-SSOP20
Multiple RS232 Drivers and Receivers
U8
1
VDD(12V)
16
DA1
15
DA2
13
DA3
19
RA1
18
RA2
17
RA3
14
RA4
12
RA5
10
VSS(-12V)
VCC(5V)
GND
VCC(5V)
GND
20
5
DY1
6
DY2
8
DY3
2
RY1
3
RY2
4
RY3
7
RY4
9
RY5
11
VCC
NRIA-
NRIB-
D4 1N4148-S-LL34
D7 1N4148-S-LL34
NDCDB­NDSRB­NSINB NRTSB NSOUTB NCTSB­NDTRB
R49
RI-
10K
R50
4.7K
B
C
Q14
NPN-3904LT1-S-SOT23
E
NRIB-
35 40 36 41 37 42 38 43 39
LPT-D25-BR-BI
CGND
5VSB
50
20
5
DY1
6
DY2
8
DY3
2
RY1
3
RY2
4
RY3
7
RY4
9
RY5
11
NRTSB NDTRB NSOUTB
NRIB­NCTSB­NDSRB­NSINB NDCDB-
VCC
INTERNAL MODEM WAKEUP HEADER
JMDM1
5 4 3 2 1
D1x5-BK
R25 10K
1 2
U10A
7407-SOIC14
LAN WAKEUP HEADER
JWOL1
3 2 1
D1x3-WH-HSNO
5VSB
R59 1K
C73
0.1u
R63 10K
47
51
13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1
52
46
B
LPT1-1
COM-D9-GN
RSLCT RPE RBUSY RACK­PRND7 PRND6 PRND5 PRND4 PRND3
RSLIN­PRND2 RINIT­PRND1 RERR­PRND0 RAFD­RSTB-
CGND <25,28,32,39>
RI-
C
Q16 NPN-3904LT1-S-SOT23
E
LPT1-2
COM-D9-GN
RI- <21>
TI-GD75232-SSOP20
A A
Multiple RS232 Drivers and Receivers
CGND
CGND
CGND
8
7
6
5
4
X2
1 2
X3
1 2
X4
1 2
_
_
_
Title
Size Document Number Rev Custom
3
Date: Sheet of
2
MICRO-STAR
LPT & COM Ports
MS-6501
24 39Thursday, July 19, 2001
1
0A
Page 25
8
7
6
5
4
3
2
1
C31
0.1u
CGND
0805 SIZE
FB7
1 2
0_0805
KBMSVCC
C45
0.1u
CGND
Support Keyboard wake-up
JKBMS1
14
6 4 2 1 3 5
15 17
16 10
12 8 7 11 9
13
3 4
5 6
7 8
FUSE USE POLY SWITCH FUSE
F2
1.1A-MF-MSMD110-S
5VDUAL
D D
VCC
+
EC9 10u
RN23
4.7K 1 2
MINIDINx2-D12-ML
FB11
KDAT<22>
1 2
CGND
0
FB10
C C
KCLK<22>
1 2
0
FB8
MCLK<22>
1 2
0
FB9
MDAT<22>
1 2
0
CN2
B B
VCORE
180p
1 2
3 4
5 6
7 8
PCB1
R169
G
270 NOPOP
K7PWRGD
DS
Q28 NDS7002A-S-SOT23
K7PWRGD <27>
BAT1
BH-D2
6
R19 3K
3 12
5VSB
R29 1K
R24 1K
D1
1N4148-S-LL34
A C
D2
1N5817-S-DO-241AC
5
VBAT
123
JBAT1 D1x3-BK
C306 0.1u
R18 1K
JBAT(1-2) JC-D2-GN
4
VCC
R171 75K
P1_VCCA_PLL1
R177 15K
R174
P0_VCCA_PLL1
10K
R187 15K
R191
VCORE
A A
10K
R205 4.7K
R201 30K C209
8
1u
C198 1u
C202 1u
B
B
B
C
Q33
E
NPN-3904LT1-S-SOT23
C
Q34
E
NPN-3904LT1-S-SOT23
C
Q39
E
NPN-3904LT1-S-SOT23
7
CGND
CGND <24,28,32,39>
3
6501 0A
Title
Size Document Number Rev
Custom
Date: Sheet of
MICRO-STAR
Keyboard & Mouse
MS-6501 0A
2
25 39Tuesday, July 24, 2001
1
Page 26
8
7
+12V
6
5
4
3
2
1
C217 0.1u
R212 1K
D D
VCC3
R390 10K
FAN_ON2<22>
C C
B B
FAN_ON<22>
A A
R61
4.7K
R393
4.7K
C
B
E
C430 0.1u
R400 4.7K SYSFAN1 R399 1K
C
B
Q58
E
NPN-3904LT1-S-SOT23
+12V
C114 0.1u
R67 4.7K
G
R60 1K
+12V
C377 0.1u
R341 4.7K
G
R342 1K
Q18 NPN-3904LT1-S-SOT23
G
+12V
G
Q17
S
SI2303DS-S-SOT23
D
C113
0.1u
Q50
S
SI2303DS-S-SOT23
D
C385
0.1u
Q41
S
SI2303DS-S-SOT23
D
C216
0.1u
Q60
S
SI2303DS-S-SOT23
D
C469
0.1u
CPUFAN2
3 2 1
D1x3-WH-SN
CPUFAN1
3 2 1
D1x3-WH-SN
PSFAN1
3 2 1
D1x3-WH-SN
SYSFAN <22>
3 2 1
D1x3-WH-SN
VCC3
12
R66
4.7K
VCC3
12
R339
4.7K
CPUFAN2
CPUFAN1FAN_ON
ROMLOCK<22>
Fan Driver
CPUFAN2 <22>
CPUFAN1 <22>
VCC3
R290
4.7K
R600 4.7K
JP2(1-2) JC-D2-GN NOPOP
BIOS
PCLK2<3>
R602
R599
4.7K
4.7K
JP2
Bios Protection
1 2
D1x2
PCIRST-1<15,16,18,19,22,23> LFRAME-<21,22>
VCC3
R607 10K
VCC3
C813
0.1u
GPI3 GPI2 GPI1 GPI0
R603 10K R604 10K
R605 10K R606 10K
U26
31
RC#/LCLK
29
MODE
28
RSV/CE#
30
A10/GPI4
3
A9/GPI3
4
A8/GPI2
5
A7/GPI1
6
A6/GPI0
7
A5/WP#
8
A4/TBL#
9
A3/RSV
10
A2/RSV
11
A1/RSV
12
A0/RSV
2
RESET#
23
WE#/LFRAME#
PLCC32-SMT
R619
NOPOP
10K
R601
0
VCC3
252632
VDD
VCC
U26-1
SST49LF020
R620
10K NOPOP
DQ7/RSV DQ6/RSV DQ5/RSV
DQ4/RSV DQ3/LAD3 DQ2/LAD2 DQ1/LAD1 DQ0/LAD0
GND1
GNDOE#/INIT#
R621
10K
NOPOP
R622
10K
21 20 19 18 17 15 14 13
1624
NOPOP
LAD3 LAD2 LAD1 LAD0
LAD[3..0] <21,22>
GPI0 GPI1 GPI2 GPI3
Title
Size Document Number Rev
Custom
8
7
6
5
4
3
JP2(1-2)
Date: Sheet of
2
MICRO-STAR
BIOS & Fans
MS-6501
26 39Wednesday, July 25, 2001
1
0A
Page 27
5
4
3
2
1
VCC2_5
5VSB
U18A
R636 L_0
D D
SN74ALS05ADR-SOIC14
14
PWRSW+PWRSW-
12
5VSB
C840
C841
L_0.1u
PWRSW1
1 2 3
L_D1x3-BK
IRRX<22> IRTX<22>
IR HEADER
VCC
C471
0.1u IRRX IRTX
JIR1
1 2 3 4 5
YJ205
VCC2_5
10
CIRRX
9 8 7 6
CIRRX <22>
5VDUAL
SUSLED<22>
R467 56
R637 1K
R53 56
Q67
C
B
E
2N3904S
MSI_LED1
JGL1
1 2 3
D1x3-BK
MSI_LED2
SLPBTN-<21>
5VSB VCC
R639
VCC
270
5VSB
R643 0
R387 270
R642 1K
C842
0.1u
PWRSW+
R644 10K
RN290 0
L_LED2
1 2
L_LED1
3 4 5 6
C C
MSI_LED2 MSI_LED1
7 8 1 2 3 4 5 6 7 8
RN291 0
PWRSW-
PWRSW-<22>
JP1(2-3) JC-D2-GN NOPOP
JP1
AC97_SPKR<29>
SPKR<21>
B B
-12V
-5V
VCC3
PWRON-
VCC
A A
R109
2.2K
R124
2.2K-REV
11 12 13 14 15 16 17 18 19 20
1 2 3
D1x3-BK NOPOP
C83
0.1u
JWR1
3.3V
-12V GND PS_ON GND GND GND
-5V 5V 5V
ATX-D2x10
B
PW_OK
5V_SB
ALARM
1 2 3 4 5 6 7 8
C E
Q20 NPN-3904LT1-S-SOT23
1
3.3V
2
3.3V
3
GND
4
5V
5
GND
6
5V
7
GND
8 9 10
12V
D10
1N4148-S-LL34
5
A3
150
RN34
JGS1
1 2
D1x2
F_P1
1
GNDK
NC NC
3
HDD+
4
SLED2 PLED1
PWSW-
NC29
M_D2x9-3:1.8.17-BK
D9
1N4148-S-LL34
VCC
5VSB +12V
NOPOP
C112
0.1u
VCC
C411 470p
10
11
12 13 14 15
SPK1
SPK2 16 17 18
A1
AC
D12
1N4148-S-LL34
C157
VCC
0.1u
B
ALARM
C E
Q75 NPN-3904LT1-S-SOT23
R660
2.2K
BEEP<22>
VCC
3VDUAL
SN74LVC14A-SOIC14
R155
2.2K R154
13 12
4.7K
C6130.01u
R158 10K
C172
0.1u
HM_PWROK <22>
4
HD_LED1 <23>
KBLOCK- <22>
R389 0-REV
FP_RST-
FP_RST- <3,33>
BZ1 BUZZER-SAT1205-85dB-D
VCC
U17F
147
R392 100
5VSB
JFP1(10-11 JC-D2-GN
5VSB
R223 1K
U18C
14
5 6
SN74ALS05ADR-SOIC14
VCC3
1110
5VSB
34
PWRGD <31>
R391 1K
C417
0.1u
3VDUAL
147
U17E
SN74LVC14A-SOIC14
14
U18B SN74ALS05ADR-SOIC14
5VSB
U18D
14
9 8
SN74ALS05ADR-SOIC14
3
PWRLED<22>
K7PWRGD <25>
R227 1K
5VSB
5VSB
14 13 12
5VSB
14 11 10
PSON-<22>
R640 L_1K
R641 L_4.7K
5VDUAL
R222 270
U18F
SN74ALS05ADR-SOIC14
U18E
SN74ALS05ADR-SOIC14
R632
4.7K-REV
VCC3
VCORE
R444
4.7K
B
B
PWROK
CPU_PG
C E
5VDUAL
C E
Q68
L_2N3904S
R631
4.7K-REV
Q66
2N3904S-REV
C225 4700p
C565 4700p NOPOP
2
L_LED1 L_LED2
B
2N3904S-REV
PWROK <21,33>
CPU_PG <4,6>
VCC2_5
R638 L_56
JGLED1
1 2 3
L_D1x3-BK
5VDUAL
R630
4.7K
PWRON-
Q65
C E
C839 X_104P
PWRON- <21>
VCC
VCC
C76
C77
0.01u
0.1u
VCC3VCC3
-12V
C91
C75
0.1u
0.01u
+12V -5V-12V
5VSB
C78
0.1u
0.1u
C111
0.01u
C88
0.1u
C81
0.1u
Put near ATX Power Connector
For EMI issue
Title
Size Document Number Rev
Date: Sheet of
MICRO-STAR
Front Panel
MS-6501
1
27 39Wednesday, July 25, 2001
VCCVCC
+12V
C106
0.1u
10u
+
EC13
C110
0.1u
0A
Page 28
E
D
C
B
A
4 4
USBP[0..3] <21>
USBN[0..3] <21>
5VDUAL
F3
R26
470K USB1_5V
1.1A-MF-MSMD110-S C54
1000p
C48 47K
J2A
21
1 2 3 4
22 5
6 7 8
EC10
1000u/6.3V
USBN1_FBUSBN0_FB USBP1_FBUSBP0_FB
R34
+
10K
C56
0.01u
24 23
RJ45+USB+LEDx2-D20-BK
CGND
CGND <24,25,32,39>
3 3
F4
1.1A-MF-MSMD110-S
+
EC52
1000u/6.3V
USBN2_FB
2 2
USBP2_FB USBP3_FB
C403 1000p
C47 0
USBOC-0 <21> USBOC-1 <21>
123456
USBN0_FB USBP0_FB
USBN1_FBUSBN3 USBP1_FB
78
CN1 10p
CGND
USB2_5V
USB1
1 2 3 5 7
D2x5-BK
R378
470K
USBN2
FB4 0
USBP2
FB3 0
C408
R386
0.01u
10K
4 6 8
109
USBN3_FB
USBP3
FB6 0 FB5 0
USBN0
FB20 0
USBP0
USB3V
R347
1.5K
USB3V
EC40
10u
USBPC4NUSBPP4N USBPC4P
USBPP4P
1 1
R34922 R34822
USB3V C386 47p
C388 47p
R441
U25
1
GPIO1
2 3 4 5 6 7 8 9
GL620USB
VCC
GPIO2
GPIO4
LVM
GPIO3
LVP
XTAL2
VCP
XTAL1
RVP
EXTRST_
RVM
OSCSEL
GND GND
16 15 14 13 12 11 10
PC2PCCLK <3>
5VDUAL
EC38
10u
FB19 0
USBPP4N
FB18 0
USBPP4P USBP3_FB
FB17 0
USBP1
FB22 0 NOPOP
USBN1
FB23 0
NOPOP
123456
78
CN17 10p
USBN2_FB USBP2_FB
USBN3_FB
1.5K
USBP1 USBN1
E
D
C
B
Title
Size Document Number Rev
Custom
Date: Sheet of
MICRO-STAR
USB Connector
MS-6501
A
28 39Thursday, July 19, 2001
0A
Page 29
8
D D
C60 22p
NOPOP
C C
SDOUT<20>
BITCLK<20>
SDIN0<20> SYNC<20>
ACRST-<20>
AC97_SPKR<27>
R31 1K-REV
24M-16pf-HC49S-D C53
12
22p
Y1
C64
12
22p
R32 22
7
1 2
R33 0
C58
1u-REV
R466 1M
VCC3
6
1 2
R17 0
1 2 3 4 5 6 7 8
C61
DVDD1 XTL_IN XTL_OUT DVSS1 SDATA_OUT BIT_CLK DVSS2 SDATA_IN DVDD2 SYNC RESET# PC_BEEP
4847464544424140394338
NC
NC
TEST6
TEST5
TEST4
PHONE
AUXL
AUXR
VIDEOL
VIDEOR
1314151617181920212223
0.1u
1 2 3 4 5 6 7 8
9 10 11 12
C59
0.1u
TEST1
AVSS2
CDLNCCDR
TEST3
TEST2
MIC1
NC
MIC2
37
AVDD2
LINL
24
MONO
LINR
5
RN6
8P4R_0-REV
U5
36
LOUTR
35
LOUTL
34
NC
33
NC
32
VRDA
31
VRAD
30
AFILT2
29
AFILT1
28
NC
27
VREF
26
AVSS1
25
AVDD1
CODEC-VIA-VT1611A-VA8
+5VR
4
+12V +5VR
3
VR1 L78L00-TO92-100mA
GND
VIN
VOUT
231
C49
0.1u
2
C50
0.1u
10u
+
EC4
1
AGND
-12V
C63
C8
0.1u
0.1u
VR2 LM79L05-TO92-100mA
2 3
IN OUT
GND
1
-5VR
C62
EC5
+
0.1u 10u
AGND
LINE_OUT_R LINE_OUT_L
LINE_OUT_R <30> LINE_OUT_L <30>
0805 SIZE
C16
C23
0.1u
C9
+
EC1
C10
10u
0.1u
0.1u
C11
+
EC2
C12
10u
270p
270p
C14
C13
1u
1u
0.1u
10u
C17
C15
+
EC3
473P-REV
1u
AGND MIC_IN
R7
2.2K-REV
R28
4.7K-REV
B B
A A
C57 102P-REV
C22 1u
C25 1u
C21 470p
NOPOP
R11 1K
C26 1u
C27 1u C33 1u C44
1u
C46 1u
C51 1u
C52 1u
C18 1u
R5 30K
R8 30K C19 470p
NOPOP
RN7
7 8 5 6 3 4 1 2
4.7K
1000p
LINE_R <30>
C20 1000p
MIC_IN
LINE_L <30>
C5 1000p
MIC_IN <30>
RN13
4.7K
78 56 34 12
JCD1
4 3 2 1
CD-D1x4-BK-SBTJ
JAUX1
4 3
AUX IN
2 1
AUX-D1x4-YL
JPHN1
1 2
MODEM IN
3 4
MON-D1x4-GN
CD IN
C7
AGND
8
7
6
5
4
3
MIC_IN
+5VR
R13 1K
R10
4.7K-REV
EC6
+
10u
R16
R12
2.2K
MIC_PWR <30>
1K
C28
0.1u AGND
Title
Size Document Number Rev
Date: Sheet of
2
MICRO-STAR
AC'97 CODEC
MS-6501
29 39Wednesday, July 25, 2001
0A
1
Page 30
8
7
6
5
4
3
2
1
-5VR
C6
1u
D D
LINE_OUT_R<29>
LINE_OUT_R
R4 33K
C3 4.7u-0805
3
+
2
-
8 4
U4A
TI-TL072CDR-SOIC8
1
R3 47K
AGND
R1 33
FB1
1 2
0_0603
SPEAKER_R
C4 1000p
C2 47p
U4B
5
+
LINE_OUT_L<29>
LINE_OUT_L
R15 33K
C30 4.7u-0805
6
-
TI-TL072CDR-SOIC8
8 4
7
R9 33
R14 47K
C29 47p
C C
AGND
GAME AND CODEDEC BRIDGE
+5VR
C24
1u
AGND
VCC
F1
1.1A-MF-MSMD110-S
FB2
1 2
0_0603
SPEAKER_L
C1 1000p
AGND
AGND
X1
1 2
_
C42
VCCVCC
0.1u
VCC
B B
SPEAKER_R
SPEAKER_L
LINE_R<29>
LINE_L<29>
MIC_PWR<29>
A A
MIC_IN<29>
R
23 22
G
30 21
L
20
R
19 18
G
28 17
L
16
R
27 26
G
29 25
L
24
AUDIO1
32
8 15 7 14 6 13 5 12 4 11 3 10 2 9 1
31
GAME-PHONE-D15-ML-B
RN16
4.7K
1 2
3 4
5 6
7 8
RN11
JBB1 JAB1
C32
0.1u
CN3
1 2
3 4
5 6
7 8
100p
2.2K
AGND
8
7
6
5
R21
R22 22K
4.7K
TXD
TXD <22> RXD <22> JAB2 <22> JBB2 <22>
C38
0.01u
JAY
JAY <22>
JBY
JBY <22>
JBX
JBX <22>
JAX
JAX <22> JBB1 <22> JAB1 <22>
Title
Size Document Number Rev
Custom
3
Date: Sheet of
2
MICRO-STAR
Audio/Game Port
MS-6501
30 39Tuesday, July 24, 2001
0A
1
78 56 34 12
C37
C36 100p
100p
C41
0.01u
C40
C39
0.01u
0.01u
4
Page 31
5
4
3
2
1
DDR Regulator & STR LDO
5VDUAL
D D
3VDUAL
R388 4.7
EC55
+
1000u/6.3V
C415
C418
0.1u
C C
VCC
R476
10K
B B
R477
2.2K
A A
C588
1u
R380 4.7K
B
Q71
NPN-3904LT1-S-SOT23
MOS_SW
NOPOP
C421
0.1u
0.1u
5VDUAL
R609
4.7K
C
E
+12V
B
Q56
NPN-3904LT1-S-SOT23
PWRGD <27>
5
VCC2_5
R379
4.7K
C
E
Q49
SI2303DS-S-SOT23
G
G
R397
15K
R396
10K
VCC
Q54 IPD12N03L-S-TO252
D S
DS
5VSB
1
16
2
15
4
13
5 8 9
12
D13 1N5817-S-DO-241AC
A C
3VDUAL 3VDUAL
R461
VCC1
VCC2
PVDD1 PVDD2
PGND1 PGND2
AGND1 AGND2 AGND3 AGND4
C427
0.1u
NOPOP
402
R463
1K
3VDUAL
C
B
E
2
CSK-2-SOT23-150mA
3 1
U30
VL1
VL2
VIN/2
VCCQ
SD
FB
CM8500
R394
1K
NPN-3904LT1-S-SOT23
Q59
VCC2_5
VR7
3
14
7
10
6
11
R352
82
R350
82
5VDUAL
1 3
10u
C382
0.1u
+
EC16
4
+
1000u/6.3V
EC50
R462 390
REG_OUT
VCC2_5
C392
0.1u
VR3
US1050CD-TO252-5A
VIN VOUT
ADJ
2
R656
10K
Q61
E
PNP-A-31-S-SOT23
B
C
VCC
VCC2_5
R658 10K
R657 10K
C
B
E
Q72
NPN-3904LT1-S-SOT23
C850
R659
1u-REV
2.2K
C
B
E
Q74
NPN-3904LT1-S-SOT23
G
RAM_PWR
DS
Q73 NDS7002A-S-SOT23
VTT_DDR
C359
0.1u
CHOCK1
3.3u
+
EC58 1000u/6.3V
R357
10K
+
EC57 1000u/6.3V
C838
0.1u
5VDUAL
B
R355
1K
C
B
E
C
E
Q53
NPN-3904LT1-S-SOT23
R345
10K Q52 NPN-3904LT1-S-SOT23
R346
24K
4700p
C383
EN
C384
4.7u-0805
12p
+
EC56
1000u/6.3V
R395
100K
C423
1000p
RAM_PWR<21>
R398
1K
5VDUAL
R610
1K
C467
5VDUAL 5VDUAL5VDUAL
R49210R493
10
C380
5
7
COMP
VCC
GND
3
U29
1
BOOT
2
UGATE
8
PHASE
IPD12N03L-S-TO252
46
LGATEFB
IPD12N03L-S-TO252
INTS-ISL6520-SOIC8
R491 1
AC
L10
1.2u
Q55
G
Q51
DS
D14
1N5817-S-DO-241AC
C400
1u
C387
0.1u
L9 3.3u
EC48
1000u/6.3V
EC54
+
1000u/6.3V
EC49
+
1000u/6.3V
EC53
+
1000u/6.3V
EC46
+
+
1000u/6.3V
2.5V/11A
VCC2_5
R343
2.2K-1%
R344
1.02K-1%
1u
DDR_VREF
C398
0.1u
place near DIMM1
5A
50 MILS TRACE
C79
0.1u
3VDUAL
R52 200
R48
332
+
EC14
1000u/6.3V
C94
105P-REV
3
VCC2_5 VCC_OPUS2_5
C71
C86
1u
105P-REV
C72
1u
U34
5
D
6
D
7
D
8
D
CEM4410A-S-SOIC8
1
S
2
S
3
S
4
G
R613
10K
2
VCC3
1N5817-S-DO-241AC-1mA
NPN-3904LT1-S-SOT23
+12V 5VDUAL
D20
R611
A C
10K
Q69
C
B
E
Title
Size Document Number Rev
Custom
Friday, July 20, 2001
Date: Sheet of
R612
10K
Q70
R614 2.2K
C
B
E
NPN-3904LT1-S-SOT23
MICRO-STAR
DDR Regulator & STR LDO
MS-6501
1
VCC3
R615
10K
31 39
0A
Page 32
8
D D
AD[31..0]<18,19,21,37>
3VDUAL
C119
C82
C87
C70
0.1u
0.1u
0.1u
3VDUAL
C93
C65
0.1u
0.1u
C C
D8
AD25
DIS_LAN<33>
3VDUAL
B B
VCC VCC3
R43
C609 0.1u
C606 0.1u
0.1u
+
EC7
10u
C_BE-[3..0]<18,19,21>
1N4148-S-LL34
8.2K
C55
0.1u
3VDUAL
RDN
R36
121
RDP
A A
TDN RDP2
TDP
PLACE THESE RESISTORS AS CLOCE TO 82559 AS POSSIBLE
8
R20
100
C84
0.1u
C_BE-[3..0]
VCC
PCIRST-2<11,13,23,33>
AD[31..0]
FRAME-<18,19,21>
IRDY-<18,19,21>
TRDY-<18,19,21>
DEVSEL-<18,19,21>
STOP-<18,19,21>
PIRQB-<15,18,19,21>
PERR-<18,19,21> SERR-<18,19,21>
REQ0-<19,21> GNT0-<21>
LANCLK<3>
PME-<15,18,19,21>
7
PAR<18,19,21>
3VDUAL
7
R57
C95 0.1u
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C_BE-0 C_BE-1 C_BE-2 C_BE-3
FRAME­IRDY­TRDY­DEVSEL­STOP­PAR PIRQB­PERR­SERR-
REQ0­GNT0-
R47
PCIRST-2 1AOLAUX PME-
R46
R41 R40 R42
5.6K
4.7K
4.7K
4.7K
6
62K
U11
A3A7E1K3N6P2G5G6H5H6H7H8J5J6J7J8J9
VCC1
G2
VIO
VCCPP1
VCCPP2
VCCPP3
N7
AD0
M7
AD1
P6
AD2
P5
AD3
N5
AD4
M5
AD5
P4
AD6
N4
AD7
P3
AD8
N3
AD9
N2
AD10
M1
AD11
M2
AD12
M3
AD13
L1
AD14
L2
AD15
K1
AD16
E3
AD17
D1
AD18
D2
AD19
D3
AD20
C1
AD21
B1
AD22
B2
AD23
B4
AD24
A5
AD25
B5
AD26
B6
AD27
C6
AD28
C7
AD29
A8
AD30
B8
AD31
M4
C/BE#0
L3
C/BE#1
F3
C/BE#2
C4
C/BE#3
F2
FRAME#
F1
IRDY#
G3
TRDY#
H3
DEVSEL#
H1
STOP#
J1
PAR
H2
INTA#
J2
PERR#
A2
SERR#
A4
IDSEL
C3
REQ#
J3
GNT#
62K
C2
RST#
G1
CLK
B9
ISOLATE#
A9
ALRST#
A6
PME#
C5
CSTSCHG/WOL
C8
CLKRUN#
B10
SMBALRT#
A10
SMBCLK
C9
SMBDATA
T1
1
TD+
2
TDC
3
TD-
6
RD+
8
RD-
7
RDC
C34
22p
1:1-TX
C68
22p
6
VCCPP4
VSSPP1
B3E2M6
VCCPP5
VCCPP6
VSSPP2
VSSPP3
CMT
RX+
RXC
VSSPP4
VSSPP5
VSSPP6
N1
B7K2G14
16
TX+
15 14
TX-
11 9
RX-
10
VCC2
VCC3
VCC4
VCC5
VSSPL1
VSSPL2
K12
VCC6
VSSPL3
N12
VCC7
VSSPL4
P8
VCC8
5
VCC9
5
VCC10
VSSPT
C10
123456
J10
J11K4K5K6K7K8K9
VCC11
VCC12
VCC13
VCC14
VSS1
VSS2
D4D5D6D7D8
78
3VDUAL
VCC15
VCC16
VCC17
VSS3
VSS4
VSS5
D11E4E5E6E7E8E9
RN24
75
LGND
VCC18
VSS6
K10
K11L4L5L9L10
VCC19
VCC20
VSS7
VSS8
TDN2
VCC21
VSS9
VCC22
VSS10
VCC23
VSS11
RDN2
TDP2
E12
VCC24
VCC25
VCC26
VSS12
VSS13
VSS14
VSS15
E10
E11F4F5F6F7F8F9
4
A11
VCCPT
VSS16
4
K13N8P12
VCCPL1
VCCPL2
VSS17
VSS18
G13
VCCPL3
VCCPL4
VSS19
VSS20
VSS21
VSS22
VSS23
F10
F11G7G8G9G10
27
10 11 12 13 14 15 16 28
RJ45+USB+LEDx2-D20-BK
9
P14
VSS24
J2B
NC9
VSS25
NC7
NC8
VSS26
VSS27
G11H9H10
NC6
VSS28
NC5
VSS29
H11L6L11
G
Y
CGND
A1
A14D9D10G4H4J4P1
NC1
NC2
NC3
NC4
LINKLED
ACTLED
SPEEDLED
FLA16/CLK25
FLA15/EESK FLA14/EEDO
FLA13/EEDI
FLA12/MCNTSM#
FLA11/MINT
FLA10/MRING#
FLA9/MRST
FLA8/IOCHRDY
FLA7/CLKEN
FLA1/AUXPWR
FLA0/PCIMODE#
FLCS#/AEN
FLWE#
TEXEC
MDMCS/CFCS
NC/CFCLK
RBIAS10
RBIAS100
VSS30
VSS31
VSS32
25 18
17
20
19 26
3
TDP
TDN
RDP
RDN
FLA6 FLA5 FLA4 FLA3 FLA2
FLD7 FLD6 FLD5 FLD4 FLD3 FLD2 FLD1 FLD0
EECS
FLOE#
TEST
TCK
TI
TO
VREF
X1 X2
INT-82559ER
3
LINKLED
A12
ACTLED
C11
SPEEDLED
B11
TDP
C13
TDN
C14
RDP
E13
RDN
E14
P9 M10 N10 P10 M11 M12 N13 P13 N14
R55
M13 M14 L12 L13 L14 K14
R54
J12 J13 J14 H12 H13 H14 G12 F12 F13 F14
P7 N9
M8 M9
A13 D13 D14 D12 B12
C12
L7 L8
B14
B13
LAN1_X1
N11
LAN1_X2
P11
R27
270
R30
270
CGND <24,25,28,39>
3.3K
NOPOP
2
3VDUAL
1
3VDUAL
3VDUAL
3.3K
U13
4 5
DO GND
3
DI
SK
CS
93C46
LAN1_X1 LAN1_X2
ORG
NC
VCC
2
1
R39
150
R76
4.7K NOPOP
6
7
8
3VDUAL
Y2
12
25M-18pf-HC49S-D
C101
R37
R38
549 619
LGND
FB24 80-0805
C100
22p
22p
SPEEDLED
3VDUAL
LINKLED ACTLED
Title
Size Document Number Rev
Monday, July 23, 2001
Date: Sheet of
MICRO-STAR
LAN 82559
2
SPEEDLED
LINKLED
MS-6501
C614 0.01u
NOPOP
C615 0.01u
NOPOP
32 39
1
0A
Page 33
5
P0_FID[0..3] A_AD[16..19] A_AD[0..3] P0_VID[0..4] UVID[0..4]
D D
A_AD3 A_AD2 A_AD1 A_AD0
A_AD19 A_AD18 A_AD17 A_AD16
C C
B B
P0_FID[0..3] <4>
A_AD[16..19] <11,16,17>
A_AD[0..3] <11,16,17>
P0_VID[0..4] <4>
UVID[0..4] <22,34>
VCC3
P0_VCCA_PLL1
RN177
8P4R-10K
1 2
3 4
5 6
7 8
RN180
1 2 3 4 5 6 7 8
8P4R-1K
RN181 7 8 5 6 3 4 1 2
8P4R-1K
100/133-<3,36>
DIS_LAN<32>
RN292
FDD_WP-<22>
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
BPV
470
RN185 470 7 8 5 6 3 4 1 2
VCC3
RN182
5
10
1K
1 2
3 4
5 6
BP0 BP1 BP2 BP3 P0_BP3
7 8
100/133-
DIS_IDE DIS_LAN FDD_WP-
RN178
8P4R-10K
P0_FID0 P0_FID1 P0_FID2 P0_FID3
CPUSTOP-
P0_BP0 P0_BP1 P0_BP2
SMBCLK<3,13,14,21,22>
SMBDATA<3,13,14,21,22> PWROK <21,27>
4
VCC3
R623
40.2
BPV
R624
C35
0.1u
2 1
1 2
3 4
5 6
7 8
BP0 BP1 BP2 BP3
R447 4.7K
P0_BP[0..3] <5>
127
U31
1
VSS
2
P00/FIDI0
3
P01/FIDI1
4
P02/FIDI2
5
P03/FIDI3
6
P04/ICRST#
7
P10/FIDO0
8
P11/FIDO1
9
P12/FIDO2
10
P13/FIDO3
11
P14/FIDO4
12
AVCC
13
A20/BP0
14
A21/BP1
15
A22/BP2
16
A23/BP3
17
A24/BP4
18
P30
19
P31
20
P32
21
P33
22
P34
23
P35
24
P36
25
P37/STPCLK#
26
I/SCLK
27
I/SIO
28 29
VSS IVCC
MS-3
3
PWRGD
P54/VIDI4 P53/VIDI3 P52/VIDI2 P51/VIDI1 P50/VIDI0
P44/VIDO4 P43/VIDO3 P42/VIDO2 P41/VIDO1 P40/VIDO0
I/RST#
OSCO
IVCC
OSCI
2
VCC3
VCC3
RN179 8P4R-10K
1 2
3 4
5 6
R448 4.7K
R449 X_0
R451 X_0
7 8
FP_RST- <3,27>
VCC3
PCIRST-2 <11,13,23,32>
56
55
AD1
54
AD0
53
SEL
52 51
INT
50
P67
49
P66
48
P65
47
P64
46
P63
45
P62
44
P61
43
P60
42 41 40 39 38
37 36 35 34 33
32 31 30
R452 3.9K
DDLED4 DDLED3 DDLED2 DDLED1 D_LED4 D_LED3 D_LED2 D_LED1
P0_VID4
P0_VID3 P0_VID2 P0_VID1
P0_VID0 UVID4
UVID3 UVID2 UVID1 UVID0
pin 29
C585
C586
pin 56
0.1u
0.1u
DDLED[1..4]
D_LED[1..4]
VCC3
EMI solution for MS-3
UVID0 UVID1 UVID2 UVID3 UVID4
P0_VID4 P0_VID3 P0_VID2 P0_VID1 P0_VID0
1
DDLED[1..4]
D_LED[1..4]
DDLED4 DDLED3 DDLED2 DDLED1
D_LED4 D_LED3 D_LED2 D_LED1
RN4
1
1
2
2
3
3
4
4
6
6
7
7
8
8
9
9510
1K
R450 680
1 2 3 4 5 6 7 8
RN183 8P4R-680
CN18 180p
CN19 180p
VCC3
5
10
P0_VCCA_PLL1
78 56 34 12
78 56 34 12
RN186 470 1 2 3 4 5 6 7 8
A A
DDLED1 DDLED2 DDLED3 DDLED4
DDLED1 D_LED1 DDLED2 DDLED3 DDLED4
5
RN184 1 2 3 4 5 6 7 8
8P4R-100
P1_BP0 P1_BP1 P1_BP2 P1_BP3
J1
2 1
4 3
GN_RD-D-5V-CR-A
4
P1_BP[0..3] <7>
56
78
D_LED1
D_LED2
D_LED3
D_LED4
D_LED1
D_LED2
D_LED3
D_LED4
DDLED1 DDLED2 DDLED3 DDLED4
J3
2 4 6 8
10
D2x5-1:2
1
1
2 4 6 8 10
D_LED2
3
3
D_LED3
5
5
D_LED4
7
7
Title
Size Document Number Rev
Custom
3
2
Date: Sheet of
* 25 mils Trace/ 12 mils Space
Wednesday, July 25, 2001
MICRO-STAR
MS-6501
VCORE AJUST
1
33 39
0A
Page 34
5
4
3
2
1
Voltage Regular Module
All N-Channel MOSFET use TO-252
VCC
+12V
D D
C107
1u
U12 INTS-HIP6301-SOIC20
UVID4<22,33> UVID3<22,33> UVID2<22,33> UVID1<22,33> UVID0<22,33>
R87
VCC
C C
+12V 12V_VIN
B B
L1
EC17
1.2u
+
100u
L8
1.2u
Remove EC36 100uF/16V because already has 470uF/16V at AGP PRO (4/23)
1800u/16V
1800u/16V
EC20
EC26
EC24
1800u/16V
EC33
1800u/16V
EC89
EC91
5V_VIN
1800u/16V
1800u/16V
154K
C118
R70
12K
0.01u
C121
47p NOPOP
R71 100K
1
VID4
2
VID3
3
VID2
4
VID1
5
VID0
8
FS/DIS
6
COMP
7
FB
10
VSEN
9
R79 1.5K
R74
C123 NOPOP
NOPOP
VCC+12V
R453 0
R459 0
VCC+12V
R454 0
R460 0
20
VCC
19
PGOOD
15
PWM1
14
PWM2
11
PWM3
18
PWM4
16
ISEN1
13
ISEN2
12
ISEN3
17
ISEN4
GND
NOPOP
C163
NOPOP
1u
Connector to C247(beside NB)
VID4 VID3 VID2 VID1 VID0 VDC(V)
1 0 1 1 0 1.30
1 0 0 0 1 1.425
1 0 0 0 0 1.45
0 1 1 1 1 1.475
0 1 1 1 0 1.500
0 1 1 0 1 1.525
0 1 1 0 0 1.550
A A
0 1 0 1 1 1.575
0 1 0 1 0 1.600
0 1 0 0 1 1.625
0 1 0 0 0 1.650
0 0 1 1 1 1.675
0 0 1 1 0 1.700
5
VID4 VID3 VID2 VID1 VID0 VDC(V)
0 0 1 1 0 1.70
0 0 1 0 1 1.725
0 0 1 0 0 1.75
0 0 0 1 1 1.775
0 0 0 1 0 1.80
0 0 0 0 1 1.825
0 0 0 0 0 1.85
1 1 1 1 1 NO CPU
Design for 45A @+/- 100 mV
4
VCORE
VCORE
C166 106P
C287 106P
Place under CPU0
C149
C177
106P
106P
Place under CPU1
C317
C324
106P
106P
R238 10
C241
1u
+12V
R80 10
C130
1u
+12V 12V_VIN
R254
10
C269
C611
1u
1u
+12V
R142
10
C612
1u
R478 0-REV
R479 0 R88 0
R68 0 R480 0
R481 0-REV
C176
C135
C136
106P
106P
106P
C323
C286
C298
106P
106P
106P
3
C237
1u
U19
2
BOOT
7
PVCC
6
VCC
3
PWM
MOSDVR-INTS-HIP6601A-SOIC8
R72 3.6K
C120
1u
U14
2
BOOT
7
PVCC
6
VCC
3
PWM
MOSDVR-INTS-HIP6601A-SOIC8
R86 3.6K
C268
1u
U21
2
BOOT
7
PVCC
6
VCC
3
PWM
MOSDVR-INTS-HIP6601A-SOIC8
R93 3.6K
C156
1u
U15
2
BOOT
7
PVCC
6
VCC
3
PWM
MOSDVR-INTS-HIP6601A-SOIC8
R69 3K
VCORE
P0_COREFB <4> P1_COREFB <6>
P1_COREFB- <6> P0_COREFB- <4>
C171
C150
106P
106P
C296
C315
106P
106P
UGATE
PHASE
LGATEGND
UGATE
PHASE
LGATEGND
UGATE
PHASE
LGATEGND
UGATE
PHASE
LGATEGND
VCORE
VCORE
1 8
54
1 8
54
1 8
54
1 8
54
R211 0
R228 0
R152 0
R186 0
R226 0
R240 0
N-IPD20N03L-S-TO252
R179 0
R178 0
N-IPD07N03L-S-TO252
C568
C570
150u
150u
C580
C581
150u
150u
IPD12N03L-S-TO252
IPD12N03L-S-TO252
IPD12N03L-S-TO252
IPD12N03L-S-TO252
N-IPD20N03L-S-TO252
N-IPD07N03L-S-TO252
Place under CPU0
Place under CPU1
5V_VIN
DS
UG1
G
Q38
DS
LG1
G Q45
5V_VIN
DS
UG2
G
Q24
DS
LG2
G Q31
DS
UG3
G
Q43
DS
LG3
G Q47
12V_VIN
DS
UG4 UG4
G
Q36
DS
LG4
G
Q35
2
DS
UG1
G
Q37
DS
IPD12N03L-S-TO252
LG1
G Q44 IPD12N03L-S-TO252
C139
DS
UG2
G
Q25
DS
IPD12N03L-S-TO252
LG2
G Q32 IPD12N03L-S-TO252
C214
DS
UG3
G
Q42
DS
N-IPD20N03L-S-TO252
LG3
G Q46 N-IPD07N03L-S-TO252
C208
DS
G Q30
DS
N-IPD20N03L-S-TO252
LG4
G Q29 N-IPD07N03L-S-TO252
C199
C200
1u
1u
L4
0.6u
C138
1u
1u
1u
1u
Title
Size Document Number Rev
Date: Sheet of
C212
1u
C196
1u
Custom
L3
0.6u EC27
EC30
EC28
EC31
2200u/6.3V
2200u/6.3V
2200u/6.3V
2200u/6.3V
L5
0.6u EC19
2200u/6.3V
L2
0.6u
R94 1K
R98
5.1K
EC47
2200u/6.3V
EC22
2200u/6.3V
EC8
2200u/6.3V
MICRO-STAR
MS-6501
VRM
1
DUAL K7
1.1V~1.85V/80A
VCORE
EC90
2200u/6.3V
VCORE
EC92
2200u/6.3V
H1
X_HEATSINK
H2
X_HEATSINK
H3
X_HEATSINK
H4
X_HEATSINK
34 39Wednesday, July 25, 2001
0A
Page 35
5
RN8822 MDAT1 MDAT5 MDAT0 MDAT4
MDAT6 MDAT2 DQS0 DM0
D D
MDAT12 MDAT8 MDAT3 MDAT7
DM1 DQS1 MDAT13 MDAT9
MDAT11 MDAT10 MDAT15 MDAT14
MDAT21 MDAT17 MDAT16 MDAT20
MDAT22 MDAT18 DM2 DQS2
C C
MDAT28 MDAT24 MDAT23 MDAT19
DM3 DQS3 MDAT29 MDAT25
MDAT31 MDAT27 MDAT26 MDAT30
MECC1 MECC0 MECC5 MECC4
MECC2 MECC6 DM8 DQS8
B B
MDAT33 MDAT37 MDAT36 MDAT32
MDAT34 MDAT38 DM4 DQS4
MDAT44 MDAT40 MDAT35 MDAT39
DQS5 DM5 MDAT41 MDAT45
MECC3
MECC7
CS-6 CS-_SR6
A A
7 8 5 6 3 4 1 2
RN8922
7 8 5 6 3 4 1 2
RN9022
7 8 5 6 3 4 1 2
RN9122
7 8 5 6 3 4 1 2
RN9222
7 8 5 6 3 4 1 2
RN9322
7 8 5 6 3 4 1 2
RN9522
7 8 5 6 3 4 1 2
RN9622
7 8 5 6 3 4 1 2
RN9722
7 8 5 6 3 4 1 2
RN9822
7 8 5 6 3 4 1 2
RN9922
7 8 5 6 3 4 1 2
RN10022
7 8 5 6 3 4 1 2
RN10122
7 8 5 6 3 4 1 2
RN10222
7 8 5 6 3 4 1 2
RN10322
7 8 5 6 3 4 1 2
RN10422
7 8 5 6 3 4 1 2
MDAT_SR1 MDAT_SR5 MDAT_SR0 MDAT_SR4
MDAT_SR6 MDAT_SR2 DQS_SR0 DM_SR0
MDAT_SR12 MDAT_SR8 MDAT_SR3 MDAT_SR7
DM_SR1 DQS_SR1 MDAT_SR13 MDAT_SR9
MDAT_SR11 MDAT_SR10 MDAT_SR15 MDAT_SR14
MDAT_SR21 MDAT_SR17 MDAT_SR16 MDAT_SR20
MDAT_SR22 MDAT_SR18 DM_SR2 DQS_SR2
MDAT_SR28 MDAT_SR24 MDAT_SR23 MDAT_SR19
DM_SR3 DQS_SR3 MDAT_SR29 MDAT_SR25
MDAT_SR31 MDAT_SR27 MDAT_SR26 MDAT_SR30
MECC_SR1 MECC_SR0 MECC_SR5 MECC_SR4
MECC_SR2 MECC_SR6 DM_SR8 DQS_SR8
MDAT_SR33 MDAT_SR37 MDAT_SR36 MDAT_SR32
MDAT_SR34 MDAT_SR38 DM_SR4 DQS_SR4
MDAT_SR44 MDAT_SR40 MDAT_SR35 MDAT_SR39
DQS_SR5 DM_SR5 MDAT_SR41 MDAT_SR45
MECC_SR3
R35622
MECC_SR7
R43022
R43122
CS-_SR7CS-7
R43222
CLKOUT-_SRB2CLKOUT_SRB2
R429220 R330220
5
RN15010 CKEA CKEB MAB12 MAA12
MAA9 MAB9 MAA11 MAB11
MAB7 MAA7 MAA8 MAB8
MAB5 MAA5 MAA6 MAB6
MDAT47 MDAT46 MDAT43 MDAT42
MDAT49 MDAT52 MDAT53 MDAT48
MAB3 MAA4 MAB4 MAA3
MAB2 MAA2 MAB1 MAA1
MAA0 MAA10 MAB0 MAB10
MAB14 MAB_SR14 MAA14 MAB13 MAA13
MDAT50 DQS6 MDAT54 DM6
MDAT56 MDAT61 MDAT51 MDAT55
DQS7 DM7 MDAT57 MDAT60
MDAT59 MDAT63 MDAT58 MDAT62
RASB­RASA­WEB­WEA-
CS-4 CS-1CS-_SR4
CASA­CS-0
CLKOUT0 CLKOUT_SR0 CLKOUT1
CLKOUT4
CLKOUT-1 CLKOUT-4 CLKOUT-3
CLKOUT_SR0 CLKOUT_SR1 CLKOUT_SR2 CLKOUT-_SR2 CLKOUT_SR3 CLKOUT_SR4 CLKOUT_SR5 CLKOUT-_SR5
CKEA_SR
7 8
CKEB_SR
5 6
MAB_SR12
3 4
MAA_SR12
1 2
RN9410
MAA_SR9
7 8
MAB_SR9
5 6
MAA_SR11
3 4
MAB_SR11
1 2
RN15110
MAB_SR7
7 8
MAA_SR7
5 6
MAA_SR8
3 4
MAB_SR8
1 2
RN15210
MAB_SR5
7 8
MAA_SR5
5 6
MAA_SR6
3 4
MAB_SR6
1 2
RN10522
MDAT_SR47
7 8
MDAT_SR46
5 6
MDAT_SR43
3 4
MDAT_SR42
1 2
RN8722
MDAT_SR49
7 8
MDAT_SR52
5 6
MDAT_SR53
3 4
MDAT_SR48
1 2
RN15310
MAB_SR3
7 8
MAA_SR4
5 6
MAB_SR4
3 4
MAA_SR3
1 2
RN15410
MAB_SR2
7 8
MAA_SR2
5 6
MAB_SR1
3 4
MAA_SR1
1 2
RN15510
MAA_SR0
7 8
MAA_SR10
5 6
MAB_SR0
3 4
MAB_SR10
1 2
RN15610
7 8
MAA_SR14
5 6
MAB_SR13
3 4
MAA_SR13
1 2
RN10622
MDAT_SR50
7 8
DQS_SR6
5 6
MDAT_SR54
3 4
DM_SR6
1 2
RN10722
MDAT_SR56
7 8
MDAT_SR61
5 6
MDAT_SR51
3 4
MDAT_SR55
1 2
RN10822
DQS_SR7
7 8
DM_SR7
5 6
MDAT_SR57
3 4
MDAT_SR60
1 2
RN10922
MDAT_SR59
7 8
MDAT_SR63
5 6
MDAT_SR58
3 4
MDAT_SR62
1 2
RN15710
RASB-_SR
7 8
RASA-_SR
5 6
WEB-_SR
3 4
WEA-_SR
1 2
RN15822
7 8 5 6
CASA-_SR
3 4
CS-_SR0
1 2
R41833 R41533 R32233
CLKOUT_SR3CLKOUT3
R42033
CLKOUT_SR4
R41733
CLKOUT-_SR0CLKOUT-0
R41933
CLKOUT-_SR1
R41633
CLKOUT-_SR4
R41233
CLKOUT-_SR3
R42133
R427120 R424120 R329220 R428120 R425120 R426220
CLKOUT-_SR0 CLKOUT-_SR1
CLKOUT-_SR3 CLKOUT-_SR4
MDAT_SR1 MDAT_SR5 MDAT_SR0 MDAT_SR4
DQS_SR0 DM_SR0 MDAT_SR2 MDAT_SR6
MDAT_SR12 MDAT_SR8 MDAT_SR3 MDAT_SR7
MDAT_SR9 DQS_SR1 MDAT_SR13 DM_SR1
CKEB_SR MDAT_SR10 MDAT_SR15 MDAT_SR14
CKEA_SR MDAT_SR11 MDAT_SR20 MAB_SR12
MDAT_SR21 MDAT_SR17 MAA_SR12 MDAT_SR16
DQS_SR2 MAA_SR11 MAB_SR11 MAA_SR9
MAB_SR7 MDAT_SR18 DM_SR2 MAB_SR9
MAA_SR7 MDAT_SR22 MAB_SR8 MAA_SR8
MDAT_SR24 MAB_SR5 MDAT_SR23 MDAT_SR19
MAA_SR5 MAB_SR6 MAA_SR6 MDAT_SR28
MAB_SR3 MAB_SR4 DQS_SR3 MDAT_SR25
MDAT_SR29 DM_SR3 MAA_SR4 MAA_SR3
MDAT_SR31 MDAT_SR27 MDAT_SR26 MDAT_SR30
CS-2CASB­CS-3 CS-5
4
4
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
RN15922 7 8 5 6 3 4 1 2
CLKOUT2
CLKOUT-2
CLKOUT5
CLKOUT-5
RN133 27
RN160 27
RN134 27
RN161 27
RN135 27
RN162 27
RN136 27
RN163 27
RN137 27
RN164 27
RN138 27
RN165 27
RN139 27
RN166 27
RN140 27
CS-_SR1
CS-_SR2CASB-_SR
CS-_SR3 CS-_SR5
R42233
R32333 R42333
R41433 R32533
R41333 R32433
MAB_SR2 MAA_SR2 MECC_SR4 MECC_SR5
MECC_SR1 MECC_SR0 MAA_SR1 MAB_SR1
DQS_SR8 DM_SR8 MAB_SR0 MAB_SR10
MAB_SR14 MAA_SR14 MAA_SR10 MAA_SR0
MECC_SR2 MECC_SR6 MECC_SR3 MECC_SR7
MDAT_SR33 MDAT_SR37 MDAT_SR36 MDAT_SR32
DQS_SR4 MDAT_SR34 DM_SR4 MDAT_SR38
RASB-_SR MDAT_SR44 MDAT_SR40 MAB_SR13
MDAT_SR39 MAA_SR13 MDAT_SR35 RASA-_SR
CS-_SR0 MDAT_SR41 WEB-_SR MDAT_SR45
CASA-_SR CS-_SR6 CS-_SR7 CS-_SR3
MDAT_SR46 MDAT_SR43 CS-_SR1 CS-_SR2
DM_SR5 DQS_SR5 MDAT_SR47 MDAT_SR42
MDAT_SR53 MDAT_SR49 MDAT_SR52 MDAT_SR48
MDAT_SR61 MDAT_SR60 DQS_SR6 DM_SR6
MDAT_SR54 MDAT_SR55 MDAT_SR50 MDAT_SR51
MDAT_SR63 MDAT_SR58 MDAT_SR62 MDAT_SR57
MDAT_SR56 DM_SR7 DQS_SR7 MDAT_SR59
WEA-_SR CS-_SR4 CS-_SR5 CASB-_SR
CLKOUT_SR2CLKOUT_SR1 CLKOUT_SRB2
CLKOUT-_SR2 CLKOUT-_SRB2
CLKOUT_SR5 CLKOUT_SRB5
CLKOUT-_SR5 CLKOUT-_SRB5CLKOUT-_SRB5CLKOUT_SRB5
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
7 8 5 6 3 4 1 2
RN167 27
RN141 27
RN168 27
RN142 27
RN169 27
RN143 27
RN170 27
RN144 27
RN171 27
RN145 27
RN173 27
RN146 27
RN174 27
RN147 27
RN148 27
RN175 27
RN149 27
RN176 27
RN172 27
3
3
VCC2_5VTT_DDRVTT_DDR
0.1u
0.1u C558
0.1u C562
0.1u C466
0.1u C464
0.1u C462
0.1u C459
0.1u C457
0.1u C455
0.1u C453
0.1u C554
0.1u C461
0.1u C550
0.1u C451
0.1u C449
0.1u C447
0.1u C444
0.1u C442
0.1u C439
0.1u C441
0.1u C437
0.1u C435
0.1u C433
0.1u C546
0.1u C548
0.1u C556
0.1u C560
VCC2_5
0.01u C512
0.01u C531
0.01u C362
0.01u C356
0.01u C509
C552
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
VTT_DDR
C468
C431
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
21
VTT_DDR
RASA-_SR <13,14> CASA-_SR <13,14> WEA-_SR <13,14> CKEA_SR <13,14>
RASB-_SR <13,14> CASB-_SR <13,14> WEB-_SR <13,14> CKEB_SR <13,14>
RASA- <10> CASA- <10> WEA- <10> CKEA <10>
0.1u C553
0.1u C465
0.1u C463
0.1u C460
0.1u C458
0.1u C456
0.1u C563
0.1u C454
0.1u C445
0.1u C555
0.1u C452
0.1u C549
0.1u C557
0.1u C446
0.1u C559
0.1u C448
0.1u C443
0.1u C440
0.1u C438
0.1u C547
0.1u C436
0.1u C434
0.1u C561
0.1u C551
0.1u C450
0.1u C545
0.1u C432
4.7u-1206
4.7u-1206
Place 475P MLCC cap.on the either end of VTT plane
RASA-_SR CASA-_SR WEA-_SR CKEA_SR
RASB-_SR CASB-_SR WEB-_SR CKEB_SR
RASA­CASA­WEA­CKEA
CLKOUT[0..5]<10>
CLKOUT-[0..5]<10>
MECC[0..7]<10>
MAA[0..14]<10>
MAB[0..14]<10>
DM[0..8]<10>
CS-[0..7]<10>
MDAT[0..63]<10>
DQS[0..8]<10>
RASB-<10>
CASB-<10>
WEB-<10> CKEB<10>
RASB-
CASB-
WEB­CKEB
2
MAA_SR0 MAA_SR1 MAA_SR2 MAA_SR3 MAA_SR4 MAA_SR5 MAA_SR6 MAA_SR7 MAA_SR8 MAA_SR9 MAA_SR10 MAA_SR11 MAA_SR12 MAA_SR13 MAA_SR14
MAB_SR0 MAB_SR1 MAB_SR2 MAB_SR3 MAB_SR4 MAB_SR5 MAB_SR6 MAB_SR7 MAB_SR8 MAB_SR9 MAB_SR10 MAB_SR11 MAB_SR12 MAB_SR13 MAB_SR14
MECC_SR0 MECC_SR1 MECC_SR2 MECC_SR3 MECC_SR4 MECC_SR5 MECC_SR6 MECC_SR7
DM_SR0 DM_SR1 DM_SR2 DM_SR3 DM_SR4 DM_SR5 DM_SR6 DM_SR7 DM_SR8
DQS_SR0 DQS_SR1 DQS_SR2 DQS_SR3 DQS_SR4 DQS_SR5 DQS_SR6 DQS_SR7 DQS_SR8
MAA_SR[0..14] <13,14>
MAB_SR[0..14] <13,14>
MECC_SR[0..7] <13,14>
DM_SR[0..8] <13,14>
DQS_SR[0..8] <13,14>
CS-_SR0 CS-_SR1 CS-_SR2 CS-_SR3 CS-_SR4 CS-_SR5 CS-_SR6 CS-_SR7
CLKOUT_SR0 CLKOUT_SR1 CLKOUT_SR2 CLKOUT_SR3 CLKOUT_SR4 CLKOUT_SR5
CLKOUT-_SR0 CLKOUT-_SR1 CLKOUT-_SR2 CLKOUT-_SR3 CLKOUT-_SR4 CLKOUT-_SR5
CLKOUT_SRB2<14>
CLKOUT-_SRB2<14>
CLKOUT_SRB5<14>
CLKOUT-_SRB5<14>
Title
Size Document Number Rev Custom
2
Date: Sheet of
DDR Termination
MDAT_SR[0..63]<13,14>
CS-_SR[0..7] <13,14>
CLKOUT_SR[0..5] <13>
CLKOUT-_SR[0..5] <13>
CLKOUT_SRB2
CLKOUT-_SRB2
CLKOUT_SRB5
CLKOUT-_SRB5
MICRO-STAR
MS-6501
1
MDAT_SR0 MDAT_SR1 MDAT_SR2 MDAT_SR3 MDAT_SR4 MDAT_SR5 MDAT_SR6 MDAT_SR7 MDAT_SR8 MDAT_SR9 MDAT_SR10 MDAT_SR11 MDAT_SR12 MDAT_SR13 MDAT_SR14 MDAT_SR15 MDAT_SR16 MDAT_SR17 MDAT_SR18 MDAT_SR19 MDAT_SR20 MDAT_SR21 MDAT_SR22 MDAT_SR23 MDAT_SR24 MDAT_SR25 MDAT_SR26 MDAT_SR27 MDAT_SR28 MDAT_SR29 MDAT_SR30 MDAT_SR31 MDAT_SR32 MDAT_SR33 MDAT_SR34 MDAT_SR35 MDAT_SR36 MDAT_SR37 MDAT_SR38 MDAT_SR39 MDAT_SR40 MDAT_SR41 MDAT_SR42 MDAT_SR43 MDAT_SR44 MDAT_SR45 MDAT_SR46 MDAT_SR47 MDAT_SR48 MDAT_SR49 MDAT_SR50 MDAT_SR51 MDAT_SR52 MDAT_SR53 MDAT_SR54 MDAT_SR55 MDAT_SR56 MDAT_SR57 MDAT_SR58 MDAT_SR59 MDAT_SR60 MDAT_SR61 MDAT_SR62 MDAT_SR63
35 39Wednesday, July 25, 2001
1
0A
Page 36
5
4
3
2
1
A_AD[11:10] CPU0 Physical S2K Bus Length
00 - Short non-slotA 01 - Single Slot A or "close" 10 - Far dual Slot A 11 - Farthest possible Slot A
A_AD[27:26] CPU1 Physical S2K Bus Length AD[27:26]
00 - Short non-slotA
A_AD11<11,16,17> A_AD10<11,16,17> A_AD27<11,16,17> A_AD26<11,16,17>
VCC3
10K
01 - Single Slot A or "close" 10 - Far dual Slot A 11 - Farthest possible Slot A
R199
10K-REV
A_AD11 A_AD10 A_AD27 A_AD26
R198
A_AD[25] TRISTATE_ENABLE
R126
R133
Enables board test mode when TEST# is asserted
10K
10K
A_AD[24] INCLK_DELAY_ENABLE
NOPOP
Enables IGD4 INCLK delay
A_AD[23] NAND_TREE_ENABLE
R125
R132
Enables NAND tree test mode when TEST# is asserted
10K
A_AD15<11,16,17>
VCC3
R203
R115
R105 10K
10K-REV
10K
10K
NOPOP
10K
R104 R116 10KR202
10K
A_AD14
A_AD14<11,16,17>
A_AD13
A_AD13<11,16,17>
A_AD12
A_AD12<11,16,17>
R183
10K
D D
VCC3
R210
R182
R149
10K-REV
A_CBE-0
A_CBE-0<11,16,17>
A_CBE-1
A_CBE-1<11,16,17>
A_CBE-2
A_CBE-2<11,16,17>
A_CBE-3
A_CBE-3<11,16,17>
C C
10K
10K
R150
R181
R209
10K
10K
10K
A_AD[31:30] CLK SPEED
L L ---> 100 Mhz (DEFAULT)
L H ---> 66 Mhz
H L ---> RESERVED
H H ---> 133 MHz
R92
A_AD31
A_AD31<11,16,17>
8.2K
A_CBE#3 - K7_PP_Enable
R127 10K
A_CBE#2 - IG_PP_Enable
A_CBE#1 - PLL BYPASS ENABLE
R128
A_CBE#0 - M66ADV
10K
VCC3
R91
1K
C
B
E
Q10 NPN-3904LT1-S-SOT23
Enables/Disables K7 push-pull drivers
Enables/Disables IGD4 push-pull drivers
LOW - Disable
LOW - Diable HIGH - Enable
R45
10K
R111
10K A_AD25 A_AD24 A_AD23
NOPOP
R110
10K
A_AD25<11,16,17> A_AD24<11,16,17> A_AD23<11,16,17>
A_AD15
R184
10K
10K-REV
VCC3
R652
10K
R185
10K-REV
VCC3
R190
10K
R189
A_AD[15] 66MHz PCI
LOW -> Disable 66MHz PCI Mode HIGH -> Enable 66MHz PCI Mode
R195
10K
A_AD[14:12] AGP CLock Mux[2:0]
Selects input APLL clock mux for PLL test mode. Refer to Ch. 11 of IGD4 Differences Document
R194
10K-REV
R218 10K-REV
VCC3
R221
R225 10K-REV
10K-REV
R217
R220
R224
10K
10K
10K
VCC3
R216
R214 R207 10K-REV
A_AD9
A_AD9<11,16,17>
A_AD8
A_AD8<11,16,17>
A_AD7
A_AD7<11,16,17>
R206
10K
10K
R213
10K-REV
10K-REV
R215
10K
A_AD6
A_AD6<11,16,17>
A_AD5
A_AD5<11,16,17>
A_AD4
A_AD4<11,16,17>
A_AD[9] Bypass_PLLs
Enables PLL bypass mode when TEST# is asserted.
A_AD[8] Outclk_Delay_Enable
Enables K7 OUTCLK delay. Default is disabled.
A_AD[7:5] SysClock_Mux[2:0]
Selects input SPLL clock mux for PLL test mode. Refer to Ch. 11 of IGD4 Differences Document
A_AD[4] IGD4 Threshhold Range Select for S2k Cells is
Low - Threshold sense set to between 0.6V and 1.0V. High - S2k Threshold sense set to between 1.0V and 1.4V.
B B
A_AD30
A_AD30<11,16,17>
R99 10K-REV
A A
A_AD29
A_AD29<11,16,17>
A_AD28
A_AD28<11,16,17>
5
VCC3
R82
R83
1K
C
8.2K E
Q11 NPN-3904LT1-S-SOT23
VCC3
A_AD[29] Disable Divider
R106
LOW - disable large skew accomodation mode HIGH - enable large skew accomodation mode
10K-REV
A_AD[28] SysClk Threshold
LOW - Senses input thresholds between 0.6V and 1.0V. HIGH - Senses input thresholds between 1.0V and 1.4V.
R107
R100
10K
10K
R44
B
10K
100/133- <3,33>
A_AD22<11,16,17> A_AD21<11,16,17>
A_AD22 A_AD21
4
VCC3
R144 R138 10K
A_AD[22:21] IGD4 INPUT HYSTERISIS OF OUTCLKS
0b00 - No Hysteresis
0b01 - Low hysteresis
10K
0b10 - Medium Hysteresis
0b11 - Max. Hysteresis
R145
R139
10K
10K
NOPOP
A_PAR<11,16,17>
VCC3
R176
10K
A_PAR
R175
10K
A_AD20<11,16,17>
A pullup on A_PAR will put IGD4 into clock test mode when TEST# is low
3
A_AD20
VCC3
A_AD[20] AGP TYPEDET
5VSB
R147
4.7K
R148
4.7K
U10D
98
7407-SOIC14
2
LOW - AGP Card with VDD_AGP = 1.5V installed HIGH - AGP Card with VDD_AGP = 3.3V installed
TYPEDET- <15>
Title
Size Document Number Rev Custom Date: Sheet of
MICRO-STAR
IGD4 PCI Strappings
MS-6501
1
36 39Wednesday, July 25, 2001
0A
Page 37
5
4
3
2
1
10K-REV
10K-REV
R690
R696
VCC3
R673
R672
10K
10K-REV
R678
R679
10K
10K-REV
AD[9] TBD
R684
R685
10K
10K-REV
AD[8] TBD
R691
10K
AD[15] ECLOCKLC (Zorakonly)
R697
10K-REV
AD[14] TMCMD
R701
R700
10K
10K
AD[3] PCIMODE
LOW - Opus connects to NB through LDT bus HIGH - Opus connects to NB through 66MHz PCI bus
AD[2] LDTFQ
LOW - LDT clock freqency = 200MHz HIGH - LDT clock freqency = 400MHz
LOW - See Opus spec HIGH - See Opus spec
LOW - See Opus spec HIGH - See Opus spec
VCC3
AD[5] NMLRST
R677
R676
10K
AD5<18,19,21,32> AD4<18,19,21,32>
R680
10K-REV
LOW - Fast reset. Approx 1.5us after PWROK HIGH -Normalreset. Greater than 1.5ms after PWROK
10K-REV
AD[4] RPTEST
LOW - GPIO pins are not in test mode HIGH - GPIO pins are in test mode for RNG and PLL
R681
10K
AD[11] CMPOVR
R686
10K
AD11<18,19,21,32> AD10<18,19,21,32>
R692
10K-REV
LOW - Compensation values for LDT phy are specified by register values
R687
HIGH - Compensation values are specified by on-board circuitry
10K
AD[10] NO_REBOOT
LOW - Reboot system with RESET# or PWRON#/RPWRON signals HIGH - Do not reboot system
R693
10K-REV
VCC3
AD[1] Special test mode slave
R675
R702
D D
C C
B B
AD1<18,19,21,32> AD2<18,19,21,32> AD0<18,19,21,32>
AD7<18,19,21,32> AD9<18,19,21,32> AD6<18,19,21,32>
AD13<18,19,21,32> AD12<18,19,21,32> AD14<18,19,21,32>
10K
R703
10K-REV
R682
10K
R688
10K-REV
R694
10K-REV
R698
10K
LOW - Master IOHub HIGH - Slave IOHub
10K-REV
AD[0] PCIBIOS
LOW - BIOS address space located on LPC bus HIGH - BIOS address space located on PCI bus.
R674
10K
VCC3 VCC3 VCC3
AD[7] CPUPINS
R683
LOW - LDT messages are used to transmit interrupt requests HIGH - LDT messages are not used to transmit interrupt requests. Instead ,the
normal signals are used:INTR,NMI,SMI#, INIT#,STPCLK#,IGNNE#,etc.
10K-REV
AD[6] PLLBPM
LOW - The PLL operates normally HIGH - The 400MHz output of VCO is driven on GPIO26
R689
10K
VCC3 VCC3
AD[13] ECMEXT
R695
LOW - See Opus spec HIGH - See Opus spec
10K-REV
AD[12] Currently unused
R699
10K
AD3<18,19,21,32>
AD8<18,19,21,32>
AD15<18,19,21,32>
A A
Title
Size Document Number Rev Custom
5
4
3
2
Date: Sheet of
MICRO-STAR
OPUS PCI Strappings
MS-6501
1
37 39Monday, July 23, 2001
0A
Page 38
8
Place at solder side of CPU0 Place at solder side of CPU1
VCORE VCORE VCORE VCORE
C474 0.1u
NOPOP
C484 0.1u
NOPOP
C473 0.1u
C490 0.1u
C523 0.1u
C535 0.1u
C475 0.1u
C534 0.1u
C515 0.1u
C479 0.1u
C522 0.1u
C489 0.1u
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
D D
C C
B B
C488 0.1u
C516 0.1u
C483 0.1u
C480 0.1u
5VSB
EC45 1000u/6.3V
+
C381 0.1u
NOPOP
NOPOP
NOPOP
NOPOP
VCORE decoupling for IGD4
VCORE
C245
0.1u
C243
0.1u
C353
0.1u
C350
0.1u
Around IGD4
A A
8
VCORE
C499
C526
C355
C247
C244
C503
C498
Under IGD4
7
C502 0.1u
C536 0.1u
C472 0.1u
C508 0.1u
C507 0.1u
C486 0.1u
C476 0.1u
C500 0.1u
C477 0.1u
C482 0.1u
C521 0.1u
C487 0.1u
0.1u
100p
1000p
0.1u
1000p
100p
100p
7
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
NOPOP
VCC3
C485 0.1u
C501 0.1u
C478 0.1u
C481 0.1u
C294 0.1u
C347 0.1u
C345 0.1u
C341 0.1u
Place around the SB
VCC3
6
NOPOP
NOPOP
NOPOP
NOPOP
S.B.
C869 0.1u
C870 0.1u
C871 0.1u
Under IGD4
6
5
AGP Decoupling
VDDQ
(Near the VDDQ Power Pin of AMD762)
C504 0.1u
C493 1u
C592 0.1u
C593 1u
NOPOP
C594 0.1u
C595 1u
NOPOP
C596 0.1u
C597 1u
C598 0.1u
C599 1u
C600 0.1u
C601 1u
NOPOP
Place under IGD4
VDDQ
C288
0.1u
C251
0.1u
C290
0.1u
C255
0.1u
C494
0.1u
C264
0.1u
C602 0.1u
C603 1u
C604 0.1u
C605 1u
Place around IGD4
AGP Slot Decoupling
VDDQ VCC3
C213
0.1u
C233
0.1u
VCC3
VCC2_5
5VDUAL
5VSB
+12V
+
+
3VDUAL
C246
0.1u
10u
EC39
10u
EC43
NOPOP
NOPOP
C249
0.1u
LAN
C616 0.01u
C618 0.01u
C620 0.01u
NOPOP
C621 0.01u
NOPOP
C622 0.01u
NOPOP
N.B.
C197
C151
0.1u
0.1u
Place an additional four spread from A14 - A33
VCC3
near IGD4
VCC3
C211
0.1u
C510 0.1u
C174 0.1u
C520 0.1u
C338 0.1u
C308 0.1u
C340 0.1u
C304 0.1u
C145 1u
C194 1u
C195 1u
C192 1u
5
C207
0.1u
Place 1 at each pair of VDDQ pins
4
C89
0.1u
Place 1 at each pair of VCC3 pins
VCC3 VCC2_5
Place at 2.5v/3.3v plane split near DCSTOP# and PLL signals going into IGD4
VCC3
VCC3
4
VDDQ
C234 0.1u
C256 0.1u
C235 0.1u
C260
0.1u
C205
0.1u
C215
0.1u
C219
0.1u
C148
0.1u
Place near AGP slot
C191
C201
0.1u
1000p
C366 0.1u
C399 0.1u
C221 0.1u
C218 0.1u
C220 0.1u
C617 0.01u
C619 0.01u
EMI
C169
0.1u
C160
0.1u
3
VCORE
C131
C180
C126
C127
C159
C155
C181
C165
C137
C187
C185
C182
VCORE
C282
C334
C325
C305
C322
C331
C329
C277
C275
C273
C327
C309
3
CPU0 VCORE DECOUPLING CAPACITOR
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
CPU1 VCORE DECOUPLING CAPACITOR
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
2
C124
0.22u
C132
0.22u
C129
0.22u
C140
0.22u
C164
0.22u
C168
0.22u
C161
0.22u
C147
0.22u
C188
0.22u
C186
0.22u
C184
0.22u
C170
0.22u
C293
0.22u
C333
0.22u C332
C318
0.22u
C295
0.22u
C316
0.22u
C330
0.22u
C278
0.22u
C276
0.22u
C274
0.22u
C284
0.22u
C283
0.22u
C310
0.22u
Title
Size Document Number Rev
Custom
Date: Sheet of
2
C125
C179
C128
C183
C153
C303
C314
C285
C312
MICRO-STAR
Bypass Capacitors
MS-6501
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
0.22u
1
38 39Wednesday, July 25, 2001
1
0A
Page 39
5
MH2 X_150 Drill / 300 Pad
9 2 3
D D
4
(NPTH)
5 6 7 8
1
MH4 X_150 Drill / 300 Pad
9 2 3 4
(NPTH)
5 6 7 8
4
MH6
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
MH5
X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
3
FIDUCIALSMOUNTING HOLES
5 6 7 8
1
5 6 7 8
FM4
X_FIDUCIAL
FM2
X_FIDUCIAL
FM3
X_FIDUCIAL
2
L1_60ohm
L3_60ohm
L4_60ohm
L6_60ohm
VCC
1
T5
1
1
2
2
3
3
D1x3-BK
T2
1
1
2
2
3
3
D1x3-BK
5 mil Coupon
5 mil Coupon
1
MH3 X_150 Drill / 300 Pad
9 2 3
C C
4
CGND
MH1 X_150 Drill / 300 Pad
9 2 3 4
(NPTH)
(NPTH)
5 6 7 8
1
5 6 7 8
1
MH7
X_150 Drill / 300 Pad
9
B B
2 3 4
(NPTH)
5 6 7 8
1
MH8 X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
1
MH9 X_150 Drill / 300 Pad
9 2 3
(NPTH)
4
1
FM1
X_FIDUCIAL
5 6 7 8
5 6 7 8
FM8
X_FIDUCIAL
FM6
X_FIDUCIAL
FM7
X_FIDUCIAL
FM5
X_FIDUCIAL
1
5VSB
U10E
11 10
7407-SOIC14
5VSB
A A
U10C
5 6
7407-SOIC14
5
4
5VSB
U10B
3 4
7407-SOIC14
5VSB
U10F
13 12
7407-SOIC14
5
+
6
-
NS-LM358MX-SOIC8
8 4
+12V
U16B
7
Title
Size Document Number Rev
B
3
2
Date: Sheet of
MICRO-STAR
Mounting Hole
MS-6501
1
0A
39 39Thursday, July 19, 2001
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