MSI MS-16F3 Schematics rev1.0
A
www.teknisi-indonesia.com
MS-16F3
MS-16F3
MS-16F3MS-16F3
1 1
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BLOCK DIAGRAM
PLATFORM
PROCESSOR (DMI,DP,PEG,FDI)
PROCESSOR (CLK,MISC,JTAG)
PROCESSOR (DDR3)
PROCESSOR POWER
PROCESSOR GRAPHIC POWER
PROCESSOR GND
PROCESSOR RESERVED
DDR3 SODIMM A0
DDR3 SODIMM A1
DDR3 SODIMM B0
DDR3 SODIMM B1
PCH_HDA/JTAG/SATA
PCH_PCIE/SMBUS/CLK
PCH_DMI/FDI/GPIO
PCH_LVDS/DDI
PCH_PCI/USB/NVRAM
PCH_GPIO/NCTF/RSVD
PCH_POWER
PCH_POWER
PCH_GND
MXM 3.0 Slot Part A,C
MXM 3.0 Slot Part B
CRT
LVDS/CAMERA
HDMI
KBC/EC/uP (ENE3930)
EPF021J
LED Driver IC
USB3.0 & IPAD Charger
USB3.0 Port 3 & eSATA
Audio Codec(ALC892)
Audio Amp(APA2051)
GIGA LAN(BFN2200A)
CARD READER(RTS5209)
HDD2/ODD/FAN/3D
WLAN & USB(1762)
TP/BTB
Battery Select
Battery Charger
System Power
DIMM_1.5VRUN
VTT_1.8VRUN_0.85
CPU Core Power
EMI
Screw
Test Pad
HDD1
Launch Board
HDD2
Touch Pad L/R Key
CD_LED_RF
CD_LED_LF
Power on Sequency
Power down Sequence
Power Diagram
MXM Sequence
Clock Distribution
Power Delivery Chart
History
A
Ver. 1.0
Ver. 1.0
Ver. 1.0Ver. 1.0
LED Driver
P2501
B
C
Chief River Platform
Ivy Bridge
rPGA988B
MXM 3.0
Page 23,24
CRT
HDMI
LVDS
GIGA LAN
BFN2200A
Mini PCI-E
WLAN
Card Reader
RTS 5209
Audio ALC892-VL
Page 30
Page 33,34
Audio Out/Input
Launch Board
BIOS ROM
B
Page 25
Page 27
Page 26
Page 35
Page 38
Page 36
Page 14
EPF021J
Page 29
LED KB
TP
PCI-E x16 Gen 3
RGB
HDMI
LVDS*2
PCI-E
PCI-E
PCI-E
Azalia
NB-SPI
SM BUS
Page 39
64 Architecture
IMC
eDP
DDRIII
PEG Gen3
PCI-E x16
Page 3~9
FDI DMI x4
(2.7 GT/s)
Panther Point
HM77
989-Ball BGA
PCI-E 2.0 Ports * 8
USB 3.0 Ports * 4
USB 2.0 Ports * 14
SATA 3.0 Ports * 2
SATA 2.0 Ports * 4
HDMI/DVI/VGA
SDVO/DisplayPort
LVDS *2
Page 14~22
KBC
ENE3930
Page 28
4C/2C
Cache
HD Graphic
GT1/GT2
(4 GB/s)
LPC
C
Dual Channel DDRIII
1066/1333/1600 MHZ
SATA Gen 3
SATA Gen 2
SATA Gen 2
USB3.0 *4
USB2.0 *14
3D glass
Cam LVDS
EPF021J
EC-SPI
DDRIII SO-DIMM
A0 & A1
DDRIII SO-DIMM
B0 & B1
HDD1
Page 49 Page 51
BTB BTB
Port 0 Port 1
BTB
ODD
1762
eSATA
Page 32
USB3.0 Port1,2
Page 31
1,2 3
0,1 2
7 9
Page 27
Page 29
11 12
LPC DEBUG
Page 28
EC ROM
Page 28
Page 10,11
Page 12,13
Page 37
5,84
6
HDD2
USB3.0 Port3
Page 32
LB
USB2.0*1
16F3
BTB
USB2.0*2
1762
Card Reader
RTS 5139
Mini PCI-E
WLAN
Page 38
D
Page 35Page 39
Page 53
Page 36
D
E
2011/12/21
2011/12/21
2011/12/212011/12/21
DC JACK
Page 40
Charger
TI-BQ24707RGRR
Page 41
System Power
+15V & +12V_FAN
Page 42
+1_5VDIMM
TPS51211
Page 43
+VTT_CORE
TPS51211 N-AO4406AL
+1_8VRUN
APL5930KAI
Page 44
+0.85VRUN
APL5912KAC
Page 44
CPU POWER
GPU POWER
ISL95831
Page 48
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
BLOCK DIAGRAM
BLOCK DIAGRAM
BLOCK DIAGRAM
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Custom
Custom
Custom
MS-16F3
MS-16F3
MS-16F3
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
E
+0.75VRUN
APL5337KAC
Page 43
+1.5VRUN
Page 43Page 44
1 61Wednesday, D ecember 21, 2 011
1 61Wednesday, D ecember 21, 2 011
1 61Wednesday, D ecember 21, 2 011
10
10
10
A
B
C
D
E
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
Board Diagram
1 1
2 2
Power StatesVoltage Rails
VOLTAGE DESCRIPTIONACTIVE INPOWER PLANE
3 3
4 4
PWR_SRC
+5VALW
+3VALW
+5VSUS
+3VSUS
+1_5VDIMM
+5VRUN
+3VRUN
+1_5VRUN
+12V_FAN
+15V
+1_8RUN
+0.85VRUN
+0.75VRUN
VTT, VTT_CORE
+VCC_CORE
+VCC_GFXCORE
19 or 12 V
5V
3V
5V
3V
1.5V
5V
3V
1.5V
12V
15V
1.8V
0.9V
0.75V
1.05V
0.8-1.35V
0.65-1.35
A
S0, S3-S5
S0, S3-S5
S0, S3-S5
S0, S3
S0, S3
S0, S3
S0, S3
S0, S3
S0
S0
S0
S0
S0
S0
S0
S0
S0
Power Source
DDR Power
Processor I/O supply voltage for DDR3
Fan Power
LED Keyboard Power
VCCPLL
VCCSA
Processor power for I/O
Processor core power rail
Graphics core power supply
B
S0 (Full on)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft Off)
Net Naming Conventions
Suffix
# = Active Low Signal
Prefix
H = Host
M = DDR Memory
TP = Test Point (does not connect anywhere else)
SLP_S3# SLP_S4# SLP_S5#
High
Low
C
High
High
LowLow Low
High
High
HighLow Low
+V*SUS+V*ALW +V*RUN
On
On
On
On
On
On
Off
Off
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
On
Off
Off
Off
PLATFORM
PLATFORM
PLATFORM
MS-16F3
MS-16F3
MS-16F3
PCB Footprints
SOT-23
1
3
2
As seen from top
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
SOT23-5
1
2
3
2 61Thursday, December 22, 2011
2 61Thursday, December 22, 2011
2 61Thursday, December 22, 2011
E
5
4
10
10
10
A
B
C
D
E
IVYBRIDGE PROCESSOR (DMI,DP,PEG,FDI)
4 4
U50A
U50A
DMI_TXN0<16>
DMI_TXN1<16>
DMI_TXN2<16>
DMI_TXN3<16>
DMI_TXP0<16>
DMI_TXP1<16>
DMI_TXP2<16>
DMI_TXP3<16>
DMI_RXN0<16>
DMI_RXN1<16>
DMI_RXN2<16>
DMI_RXN3<16>
DMI_RXP0<16>
DMI_RXP1<16>
DMI_RXP2<16>
DMI_RXP3<16>
3 3
2 2
If eDP HPD unused, PU 10k.
Intel Comments:
eDP COMP signals are required
if integrated gfx is enabled even
if eDP interface is disabled.
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
+VTT_CORE
+VTT_CORE
FDI_TXN0<16>
FDI_TXN1<16>
FDI_TXN2<16>
FDI_TXN3<16>
FDI_TXN4<16>
FDI_TXN5<16>
FDI_TXN6<16>
FDI_TXN7<16>
FDI_TXP0<16>
FDI_TXP1<16>
FDI_TXP2<16>
FDI_TXP3<16>
FDI_TXP4<16>
FDI_TXP5<16>
FDI_TXP6<16>
FDI_TXP7<16>
FDI_INT<16>
R395 24.9R1%0402R395 24.9R1%0402
R130 X_10KR0402R130 X_10KR0402
B27
DMI_RX#[0]
B25
DMI_RX#[1]
A25
DMI_RX#[2]
B24
DMI_RX#[3]
B28
DMI_RX[0]
B26
DMI_RX[1]
A24
DMI_RX[2]
B23
DMI_RX[3]
G21
DMI_TX#[0]
E22
DMI_TX#[1]
F21
DMI_TX#[2]
D21
DMI_TX#[3]
G22
DMI_TX[0]
D22
DMI_TX[1]
F20
DMI_TX[2]
C21
DMI_TX[3]
A21
FDI0_TX#[0]
H19
FDI0_TX#[1]
E19
FDI0_TX#[2]
F18
FDI0_TX#[3]
B21
FDI1_TX#[0]
C20
FDI1_TX#[1]
D18
FDI1_TX#[2]
E17
FDI1_TX#[3]
A22
FDI0_TX[0]
G19
FDI0_TX[1]
E20
FDI0_TX[2]
G18
FDI0_TX[3]
B20
FDI1_TX[0]
C19
FDI1_TX[1]
D19
FDI1_TX[2]
F17
FDI1_TX[3]
J18
FDI0_FSYNC
J17
FDI1_FSYNC
H20
FDI_INT
J19
FDI0_LSYNC
H17
FDI1_LSYNC
A18
eDP_COMPIO
A17
eDP_ICOMPO
B16
eDP_HPD
C15
eDP_AUX
D15
eDP_AUX#
C17
eDP_TX[0]
F16
eDP_TX[1]
C16
eDP_TX[2]
G15
eDP_TX[3]
C18
eDP_TX#[0]
E16
eDP_TX#[1]
D16
eDP_TX#[2]
F15
eDP_TX#[3]
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
DMI
DMI
Intel(R) FDI
Intel(R) FDI
eDP
eDP
PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO
PEG_RX#[0]
PEG_RX#[1]
PEG_RX#[2]
PEG_RX#[3]
PEG_RX#[4]
PEG_RX#[5]
PEG_RX#[6]
PEG_RX#[7]
PEG_RX#[8]
PEG_RX#[9]
PEG_RX#[10]
PEG_RX#[11]
PEG_RX#[12]
PEG_RX#[13]
PEG_RX#[14]
PEG_RX#[15]
PEG_RX[0]
PEG_RX[1]
PEG_RX[2]
PEG_RX[3]
PEG_RX[4]
PEG_RX[5]
PEG_RX[6]
PEG_RX[7]
PEG_RX[8]
PEG_RX[9]
PEG_RX[10]
PEG_RX[11]
PEG_RX[12]
PEG_RX[13]
PEG_RX[14]
PEG_RX[15]
PEG_TX#[0]
PEG_TX#[1]
PEG_TX#[2]
PEG_TX#[3]
PEG_TX#[4]
PEG_TX#[5]
PEG_TX#[6]
PEG_TX#[7]
PEG_TX#[8]
PEG_TX#[9]
PEG_TX#[10]
PEG_TX#[11]
PCI EXPRESS* - GRAPHICS
PCI EXPRESS* - GRAPHICS
PEG_TX#[12]
PEG_TX#[13]
PEG_TX#[14]
PEG_TX#[15]
PEG_TX[0]
PEG_TX[1]
PEG_TX[2]
PEG_TX[3]
PEG_TX[4]
PEG_TX[5]
PEG_TX[6]
PEG_TX[7]
PEG_TX[8]
PEG_TX[9]
PEG_TX[10]
PEG_TX[11]
PEG_TX[12]
PEG_TX[13]
PEG_TX[14]
PEG_TX[15]
J22
J21
H22
K33
M35
L34
J35
J32
H34
H31
G33
G30
F35
E34
E32
D33
D31
B33
C32
J33
L35
K34
H35
H32
G34
G31
F33
F30
E35
E33
F32
D34
E31
C33
B32
M29
M32
M31
L32
L29
K31
K28
J30
J28
H29
G27
E29
F27
D28
F26
E25
M28
M33
M30
L31
L28
K30
K27
J29
J27
H28
G28
E28
F28
D27
E26
D25
PEG_COMP
PEG_RXN0
PEG_RXN1
PEG_RXN2
PEG_RXN3
PEG_RXN4
PEG_RXN5
PEG_RXN6
PEG_RXN7
PEG_RXN8
PEG_RXN9
PEG_RXN10
PEG_RXN11
PEG_RXN12
PEG_RXN13
PEG_RXN14
PEG_RXN15
PEG_RXP0
PEG_RXP1
PEG_RXP2
PEG_RXP3
PEG_RXP4
PEG_RXP5
PEG_RXP6
PEG_RXP7
PEG_RXP8
PEG_RXP9
PEG_RXP10
PEG_RXP11
PEG_RXP12
PEG_RXP13
PEG_RXP14
PEG_RXP15
PEG_TXN0
PEG_TXN1
PEG_TXN2
PEG_TXN3
PEG_TXN4
PEG_TXN5
PEG_TXN6
PEG_TXN7
PEG_TXN8
PEG_TXN9
PEG_TXN10
PEG_TXN11
PEG_TXN12
PEG_TXN13
PEG_TXN14
PEG_TXN15
PEG_TXP0
PEG_TXP1
PEG_TXP2
PEG_TXP3
PEG_TXP4
PEG_TXP5
PEG_TXP6
PEG_TXP7
PEG_TXP8
PEG_TXP9
PEG_TXP10
PEG_TXP11
PEG_TXP12
PEG_TXP13
PEG_TXP14
PEG_TXP15
PEG_ICOMPO Width:12 mils Spacing:15 mils
PEG_RCOMPO Width:4 mils Spacing:15 mils
PEG_ICOMPI Width:4 mils Spacing:15 mils
R138 24.9R1%0402R138 24.9R1%0402
+VTT_CORE
PEG_RXN[15:0] <24>
PEG_RXP[15:0] <24>
PEG_TXN[15:0] <24>
PEG_TXP[15:0] <24>
1 1
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
PROCESSOR (DMI,DP,PEG,FDI)
PROCESSOR (DMI,DP,PEG,FDI)
PROCESSOR (DMI,DP,PEG,FDI)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
A
B
C
D
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
3 61Thursday, December 15, 2011
3 61Thursday, December 15, 2011
3 61Thursday, December 15, 2011
E
10
10
10
A
B
C
D
E
IVYBRIDGE PROCESSOR (CLK,MISC,JTAG)
4 4
Intel Comments:
CATERR# doesn't not require an external on board pull-up resistor
EC default tri-state active low.
R170 using 330 ohm for EC 4 mA sink current.
+3VRUN
C218
C218
X_C0.1u10X0402
74LVC1G07:
pin 1 is NC
U53
X_SN74LVC1G07DCK_SC70
X_SN74LVC1G07DCK_SC70
EC_PROCHOT#<28>
3 3
IMVP_PROCHOT#<45>
R180 10KR0402R180 10KR0402
BUF_PTL_RST#<18>
2 2
+1_5VRUN
R184
R184
10KR0402
10KR0402
Z0301
1 1
R190
R190
20KR1%0402
20KR1%0402
U53
VCCPWRGOOD_0_R
+3VSUS
B
B
C217
C217
C1u10X0402
C1u10X0402
1
2
R426 0R0402R426 0R0402
X_C0.1u10X0402
53
VCC
VCC
4
A Y
A Y
GND
GND
JNC10 X_0402JNC10 X_0402
1 2
74LVC1G07:
pin 1 is NC
R191
R191
10KR0402
10KR0402
C
C
NC7WZ14P6X_SC70
NC7WZ14P6X_SC70
Q7
Q7
E
E
N-SST3904_SOT23
N-SST3904_SOT23
+VTT_CORE
H_PM_SYNC<16>
H_CPUPW RGD<19>
+3VSUS
53
VCC
VCC
1
A Y
A Y
2
U51
U51
GND
GND
SN74LVC1G07DCK_SC70
SN74LVC1G07DCK_SC70
+3VSUS
C212
C212
C0.1u10X0402
C0.1u10X0402
3
A Y
A Y
R170
R170
680R0402
680R0402
R213 56R0402R213 56R0402
If CPU PROCHOT# not used
Unstuff R170, R213. stuff R194
C216
C216
C0.1u10X0402
C0.1u10X0402
4
5
U28A
U28A
VCC
VCC
4
GND
GND
2
H_SNB_IVB#<19>
+VTT_CORE
+VTT_CORE
JNC9 X_0402JNC9 X_0402
+VTT_CORE
PM_DRAM_PWRGD<16>
R372 X_51R1%0402R372 X_51R1%0402
H_PROCHOT#_R
R194 X_68R0402R194 X_68R0402
1 2
1 2
JNC14 X_0402JNC14 X_0402
R417 X_1.5KR1%0402R417 X_1.5KR1%0402
R420
R420
75R0402
75R0402
R419 43R5%0402R419 43R5%0402
+1_5VRUN_PWGD <43>
TPJNC16TPJNC16
H_PECI<19,28>
H_THRMTRIP#<19>
VCCPWRGOOD_0_R
VDDPWRGOOD_R
1.065V
Change R414 value
to Ivy Bridge
PLT_RST#_R
+3VSUS
R185
R185
200R5%0402
200R5%0402
2
1
SKTOCC#JNC
H_CATERR#
H_PM_SYNC_R
PLT_RST#_R
R414
R414
X_715R1%0402
X_715R1%0402
+3VSUS
53
U57
U57
VCC
VCC
A
A
B
B
GND
GND
74AHC1G09GV_SC74A5
74AHC1G09GV_SC74A5
U50B
U50B
C26
PROC_SELECT#
AN34
SKTOCC#
AL33
CATERR#
AN33
PECI
AL32
PROCHOT#
AN32
THERMTRIP#
AM34
PM_SYNC
AP33
UNCOREPWRGOOD
V8
SM_DRAMPWROK
AR33
RESET#
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
+1_5VRUN
VDDPWRGOOD_BUFF VDDPWRGOOD_R
4
Y
Y
MISCTHERMALPWR MANAGEMENT
MISCTHERMALPWR MANAGEMENT
R187
R187
200R5%0402
200R5%0402
R181 130R1%0402R181 130R1%0402
CLOCKS
CLOCKS
DDR3
DDR3
JTAG & BPM
JTAG & BPM
DPLL_REF_CLK
DPLL_REF_CLK#
SM_DRAMRST#
SM_RCOMP[0]
SM_RCOMP[1]
SM_RCOMP[2]
MISC
MISC
BCLK
BCLK#
PRDY#
PREQ#
TCK
TMS
TRST#
TDO
DBR#
BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]
BPM#[4]
BPM#[5]
BPM#[6]
BPM#[7]
CPU_CLKP
A28
CPU_CLKN
A27
R444 1KR0402R444 1KR0402
A16
R445 1KR0402R445 1KR0402
A15
CPUDRAMRST#
R8
SM_RCOMP0JNC
AK1
SM_RCOMP1JNC
A5
SM_RCOMP2JNC
A4
XDP_PRDY#
AP29
XDP_PREQ#
AP27
XDP_TCLK
AR26
XDP_TMS
AR27
XDP_TRST#
AP30
XDP_TDI
AR28
TDI
AP26
AL35
AT28
AR29
AR30
AT30
AP32
AR31
AT31
AR32
XDP_TDO
XDP_DBRESET#
XDP_CPU_BPM_N0
XDP_CPU_BPM_N1
XDP_CPU_BPM_N2
XDP_CPU_BPM_N3
XDP_CPU_BPM_N4
XDP_CPU_BPM_N5
XDP_CPU_BPM_N6
XDP_CPU_BPM_N7
R326 near the SODIMM
DDR3_DRAMRST#<10,11,12,13>
DRAMRST_CNTRL_PCH<7,15>
JNC35 X_0402JNC35 X_0402
1 2
JNC36 X_0402JNC36 X_0402
1 2
+VTT_CORE
PU, PD
If motherboard only supports external graphics
or integrated graphic but without eDP
R408 140R1%0402R408 140R1%0402
R391 25.5R1%0402R391 25.5R1%0402
R390 200R1%0402R390 200R1%0402
TPJNC64TPJNC64
TPJNC57TPJNC57
TPJNC56TPJNC56
TPJNC58TPJNC58
TPJNC59TPJNC59
TPJNC61TPJNC61
TPJNC60TPJNC60
TPJNC62TPJNC62
TPJNC63TPJNC63
R326 1KR0402R326 1KR0402
JNC34 X_0402JNC34 X_0402
CLK_EXP <15>
CLK_EXP# <15>
+1_5VDIMM
R323
R323
1KR0402
1KR0402
DDR3_DRAMRST#_D
1 2
SM_RCOMP[0] Width:20mil Spacing:20mil
SM_RCOMP[1] Width:20mil Spacing:20mil
SM_RCOMP[2] Width:15mil Spacing:20mil
SM_RCOMP[1][2][3] Length max: 500mil
2
4
6
8
X_1KR1%0402
X_1KR1%0402
+VTT_CORE
+3VRUN
CPUDRAMRST#
R324
R324
4.99KR1%0402
4.99KR1%0402
Close CPU 12/01 Unmount
RN6
XDP_TDI
XDP_TMS
XDP_TDO
XDP_PREQ#
XDP_TCLK
XDP_TRST#
XDP_DBRESET#
RN6
1
3
5
7
X_8P4R-51R1%0402
X_8P4R-51R1%0402
R182 X_51R1%0402R182 X_51R1%0402
R179 X_51R1%0402R179 X_51R1%0402
R176 X_51R1%0402R176 X_51R1%0402
R171
R171
Q24
Q24
N-BSS138_SOT23
N-BSS138_SOT23
D S
G
C359
C359
C0.047u10X0402
C0.047u10X0402
If you use OD output AND Gate,
so follow DG.
A
B
C
D
Title
Title
Title
PROCESSOR (CLK,MISC,JTAG)
PROCESSOR (CLK,MISC,JTAG)
PROCESSOR (CLK,MISC,JTAG)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
4 61Thursday, December 15, 2011
4 61Thursday, December 15, 2011
4 61Thursday, December 15, 2011
E
10
10
10
A
B
C
D
E
IVYBRIDGE PROCESSOR (DDR3)
U50C
U50C
4 4
M_A_DQ[63:0]<10,11> M_B_DQ[63:0]<12,13>
3 3
2 2
M_A_BS0<10,11>
M_A_BS1<10,11>
M_A_BS2<10,11>
M_A_CAS#<10,11>
M_A_RAS#<10,11>
M_A_WE#<10,11>
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
G10
N10
M10
AG6
AG5
AK6
AK5
AH5
AH6
AK8
AK9
AH8
AH9
AL9
AL8
AP11
AN11
AL12
AM12
AM11
AL11
AP12
AN12
AJ14
AH14
AL15
AK15
AL14
AK14
AJ15
AH15
AE10
AF10
AE8
AD9
AF9
F10
G9
G8
G7
M8
M9
M7
AJ5
AJ6
AJ8
AJ9
C5
D5
D3
D2
D6
C6
C2
C3
F8
F9
F7
K4
K5
K1
J1
J5
J4
J2
K2
N8
N7
N9
V6
SA_DQ[0]
SA_DQ[1]
SA_DQ[2]
SA_DQ[3]
SA_DQ[4]
SA_DQ[5]
SA_DQ[6]
SA_DQ[7]
SA_DQ[8]
SA_DQ[9]
SA_DQ[10]
SA_DQ[11]
SA_DQ[12]
SA_DQ[13]
SA_DQ[14]
SA_DQ[15]
SA_DQ[16]
SA_DQ[17]
SA_DQ[18]
SA_DQ[19]
SA_DQ[20]
SA_DQ[21]
SA_DQ[22]
SA_DQ[23]
SA_DQ[24]
SA_DQ[25]
SA_DQ[26]
SA_DQ[27]
SA_DQ[28]
SA_DQ[29]
SA_DQ[30]
SA_DQ[31]
SA_DQ[32]
SA_DQ[33]
SA_DQ[34]
SA_DQ[35]
SA_DQ[36]
SA_DQ[37]
SA_DQ[38]
SA_DQ[39]
SA_DQ[40]
SA_DQ[41]
SA_DQ[42]
SA_DQ[43]
SA_DQ[44]
SA_DQ[45]
SA_DQ[46]
SA_DQ[47]
SA_DQ[48]
SA_DQ[49]
SA_DQ[50]
SA_DQ[51]
SA_DQ[52]
SA_DQ[53]
SA_DQ[54]
SA_DQ[55]
SA_DQ[56]
SA_DQ[57]
SA_DQ[58]
SA_DQ[59]
SA_DQ[60]
SA_DQ[61]
SA_DQ[62]
SA_DQ[63]
SA_BS[0]
SA_BS[1]
SA_BS[2]
SA_CAS#
SA_RAS#
SA_WE#
SA_CLK#[0]
SA_CLK#[1]
SA_CLK#[2]
SA_CLK#[3]
SA_DQS#[0]
SA_DQS#[1]
SA_DQS#[2]
SA_DQS#[3]
SA_DQS#[4]
SA_DQS#[5]
SA_DQS#[6]
SA_DQS#[7]
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY A
SA_CK[0]
SA_CKE[0]
SA_CK[1]
SA_CKE[1]
SA_CK[2]
SA_CKE[2]
SA_CK[3]
SA_CKE[3]
SA_CS#[0]
SA_CS#[1]
SA_CS#[2]
SA_CS#[3]
SA_ODT[0]
SA_ODT[1]
SA_ODT[2]
SA_ODT[3]
SA_DQS[0]
SA_DQS[1]
SA_DQS[2]
SA_DQS[3]
SA_DQS[4]
SA_DQS[5]
SA_DQS[6]
SA_DQS[7]
SA_MA[0]
SA_MA[1]
SA_MA[2]
SA_MA[3]
SA_MA[4]
SA_MA[5]
SA_MA[6]
SA_MA[7]
SA_MA[8]
SA_MA[9]
SA_MA[10]
SA_MA[11]
SA_MA[12]
SA_MA[13]
SA_MA[14]
SA_MA[15]
AB6
AA6
V9
AA5
AB5
V10
AB4
AA4
W9
AB3
AA3
W10
AK3
AL3
AG1
AH1
AH3
AG3
AG2
AH2
C4
G6
J3
M6
AL6
AM8
AR12
AM15
D4
F6
K3
N6
AL5
AM9
AR11
AM14
AD10
W1
W2
W7
V3
V2
W3
W6
V1
W5
AD8
V4
W4
AF8
V5
V7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
M_A_CLK_DDR0 <10>
M_A_CLK_DDR#0 <10>
M_A_CKE0 <10>
M_A_CLK_DDR1 <10>
M_A_CLK_DDR#1 <10>
M_A_CKE1 <10>
M_A_CLK_DDR2 <11>
M_A_CLK_DDR#2 <11>
M_A_CKE2 <11>
M_A_CLK_DDR3 <11>
M_A_CLK_DDR#3 <11>
M_A_CKE3 <11>
M_A_CS#0 <10>
M_A_CS#1 <10>
M_A_CS#2 <11>
M_A_CS#3 <11>
M_A_ODT0 <10>
M_A_ODT1 <10>
M_A_ODT2 <11>
M_A_ODT3 <11>
M_A_DQS#[7:0] <10,11>
M_A_DQS[7:0] <10,11>
M_A_A[15:0] <10,11>
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_BS0<12,13>
M_B_BS1<12,13>
M_B_BS2<12,13>
M_B_CAS#<12,13>
M_B_RAS#<12,13>
M_B_WE#<12,13>
D10
K10
AM5
AM6
AR3
AP3
AN3
AN2
AN1
AP2
AP5
AN9
AT5
AT6
AP6
AN8
AR6
AR5
AR9
AJ11
AT8
AT9
AH11
AR8
AJ12
AH12
AT11
AN14
AR14
AT14
AT12
AN15
AR15
AT15
AA9
AA7
AA10
AB8
AB9
G4
G1
G5
G2
J10
M5
M4
M2
M1
C9
A7
C8
A9
A8
D9
D8
F4
F1
F5
F2
J7
J8
K9
J9
K8
K7
N4
N2
N1
N5
R6
U50D
U50D
SB_DQ[0]
SB_DQ[1]
SB_DQ[2]
SB_DQ[3]
SB_DQ[4]
SB_DQ[5]
SB_DQ[6]
SB_DQ[7]
SB_DQ[8]
SB_DQ[9]
SB_DQ[10]
SB_DQ[11]
SB_DQ[12]
SB_DQ[13]
SB_DQ[14]
SB_DQ[15]
SB_DQ[16]
SB_DQ[17]
SB_DQ[18]
SB_DQ[19]
SB_DQ[20]
SB_DQ[21]
SB_DQ[22]
SB_DQ[23]
SB_DQ[24]
SB_DQ[25]
SB_DQ[26]
SB_DQ[27]
SB_DQ[28]
SB_DQ[29]
SB_DQ[30]
SB_DQ[31]
SB_DQ[32]
SB_DQ[33]
SB_DQ[34]
SB_DQ[35]
SB_DQ[36]
SB_DQ[37]
SB_DQ[38]
SB_DQ[39]
SB_DQ[40]
SB_DQ[41]
SB_DQ[42]
SB_DQ[43]
SB_DQ[44]
SB_DQ[45]
SB_DQ[46]
SB_DQ[47]
SB_DQ[48]
SB_DQ[49]
SB_DQ[50]
SB_DQ[51]
SB_DQ[52]
SB_DQ[53]
SB_DQ[54]
SB_DQ[55]
SB_DQ[56]
SB_DQ[57]
SB_DQ[58]
SB_DQ[59]
SB_DQ[60]
SB_DQ[61]
SB_DQ[62]
SB_DQ[63]
SB_BS[0]
SB_BS[1]
SB_BS[2]
SB_CAS#
SB_RAS#
SB_WE#
AE2
SB_CK[0]
SB_CKE[0]
SB_CK[1]
SB_CKE[1]
SB_CK[2]
SB_CKE[2]
SB_CK[3]
SB_CKE[3]
SB_CS#[0]
SB_CS#[1]
SB_CS#[2]
SB_CS#[3]
SB_ODT[0]
SB_ODT[1]
SB_ODT[2]
SB_ODT[3]
SB_DQS[0]
SB_DQS[1]
SB_DQS[2]
SB_DQS[3]
SB_DQS[4]
SB_DQS[5]
SB_DQS[6]
SB_DQS[7]
SB_MA[0]
SB_MA[1]
SB_MA[2]
SB_MA[3]
SB_MA[4]
SB_MA[5]
SB_MA[6]
SB_MA[7]
SB_MA[8]
SB_MA[9]
SB_MA[10]
SB_MA[11]
SB_MA[12]
SB_MA[13]
SB_MA[14]
SB_MA[15]
AD2
R9
AE1
AD1
R10
AB2
AA2
T9
AA1
AB1
T10
AD3
AE3
AD6
AE6
AE4
AD4
AD5
AE5
D7
F3
K6
N3
AN5
AP9
AK12
AP15
C7
G3
J6
M3
AN6
AP8
AK11
AP14
AA8
T7
R7
T6
T2
T4
T3
R2
T5
R3
AB7
R1
T1
AB10
R5
R4
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
SB_CLK#[0]
SB_CLK#[1]
SB_CLK#[2]
SB_CLK#[3]
SB_DQS#[0]
SB_DQS#[1]
SB_DQS#[2]
SB_DQS#[3]
SB_DQS#[4]
SB_DQS#[5]
SB_DQS#[6]
SB_DQS#[7]
DDR SYSTEM MEMORY B
DDR SYSTEM MEMORY B
M_B_CLK_DDR0 <12>
M_B_CLK_DDR#0 <12>
M_B_CKE0 <12>
M_B_CLK_DDR1 <12>
M_B_CLK_DDR#1 <12>
M_B_CKE1 <12>
M_B_CLK_DDR2 <13>
M_B_CLK_DDR#2 <13>
M_B_CKE2 <13>
M_B_CLK_DDR3 <13>
M_B_CLK_DDR#3 <13>
M_B_CKE3 <13>
M_B_CS#0 <12>
M_B_CS#1 <12>
M_B_CS#2 <13>
M_B_CS#3 <13>
M_B_ODT0 <12>
M_B_ODT1 <12>
M_B_ODT2 <13>
M_B_ODT3 <13>
M_B_DQS#[7:0] <12,13>
M_B_DQS[7:0] <12,13>
M_B_A[15:0] <12,13>
1 1
A
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
PROCESSOR (DDR3)
PROCESSOR (DDR3)
PROCESSOR (DDR3)
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
B
C
D
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
5 61Thursday, December 15, 2011
5 61Thursday, December 15, 2011
5 61Thursday, December 15, 2011
E
10
10
10
A
B
C
D
E
IVYBRIDGE PROCESSOR (POWER)
POWER
U50F
U50F
+VCC_CORE
4 4
3 3
2 2
1 1
94 A
AG35
VCC1
AG34
VCC2
AG33
VCC3
AG32
VCC4
AG31
VCC5
AG30
VCC6
AG29
VCC7
AG28
VCC8
AG27
VCC9
AG26
VCC10
AF35
VCC11
AF34
VCC12
AF33
VCC13
AF32
VCC14
AF31
VCC15
AF30
VCC16
AF29
VCC17
AF28
VCC18
AF27
VCC19
AF26
VCC20
AD35
VCC21
AD34
VCC22
AD33
VCC23
AD32
VCC24
AD31
VCC25
AD30
VCC26
AD29
VCC27
AD28
VCC28
AD27
VCC29
AD26
VCC30
AC35
VCC31
AC34
VCC32
AC33
VCC33
AC32
VCC34
AC31
VCC35
AC30
VCC36
AC29
VCC37
AC28
VCC38
AC27
VCC39
AC26
VCC40
AA35
VCC41
AA34
VCC42
AA33
VCC43
AA32
VCC44
AA31
VCC45
AA30
VCC46
AA29
VCC47
AA28
VCC48
AA27
VCC49
AA26
VCC50
Y35
VCC51
Y34
VCC52
Y33
VCC53
Y32
VCC54
Y31
VCC55
Y30
VCC56
Y29
VCC57
Y28
VCC58
Y27
VCC59
Y26
VCC60
V35
VCC61
V34
VCC62
V33
VCC63
V32
VCC64
V31
VCC65
V30
VCC66
V29
VCC67
V28
VCC68
V27
VCC69
V26
VCC70
U35
VCC71
U34
VCC72
U33
VCC73
U32
VCC74
U31
VCC75
U30
VCC76
U29
VCC77
U28
VCC78
U27
VCC79
U26
VCC80
R35
VCC81
R34
VCC82
R33
VCC83
R32
VCC84
R31
VCC85
R30
VCC86
R29
VCC87
R28
VCC88
R27
VCC89
R26
VCC90
P35
VCC91
P34
VCC92
P33
VCC93
P32
VCC94
P31
VCC95
P30
VCC96
P29
VCC97
P28
VCC98
P27
VCC99
P26
VCC100
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
A
POWER
PEG AND DDR
PEG AND DDR
CORE SUPPLY
CORE SUPPLY
VSS_SENSE_VCCIO
SENSE LINES SVID
SENSE LINES SVID
VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
VCCIO7
VCCIO8
VCCIO9
VCCIO10
VCCIO11
VCCIO12
VCCIO13
VCCIO14
VCCIO15
VCCIO16
VCCIO17
VCCIO18
VCCIO19
VCCIO20
VCCIO21
VCCIO22
VCCIO23
VCCIO24
VCCIO25
VCCIO26
VCCIO27
VCCIO28
VCCIO29
VCCIO30
VCCIO31
VCCIO32
VCCIO33
VCCIO34
VCCIO35
VCCIO36
VCCIO37
VCCIO38
VCCIO39
VCCIO40
VIDALERT#
VIDSCLK
VIDSOUT
VCC_SENSE
VSS_SENSE
VCCIO_SENSE
AH13
AH10
AG10
AC10
Y10
U10
P10
L10
J14
J13
J12
J11
H14
H12
H11
G14
G13
G12
F14
F13
F12
F11
E14
E12
E11
D14
D13
D12
D11
C14
C13
C12
C11
B14
B12
A14
A13
A12
A11
JNC7 X_0603JNC7 X_0603
J23
VR_SVID_ALERT#_R
AJ29
VR_SVID_CLK_R
AJ30
AJ28
VR_SVID_DATA_R
AJ35
AJ34
VTT_SENSE
B10
TP_VSS_SENSE_VTTJNC
A10
B
1 2
C166
C166
X_C10u6.3X50805
X_C10u6.3X50805
C527
C527
C22u6.3X0805
C22u6.3X0805
R162 43R5%0402R162 43R5%0402
TPJNC14TPJNC14
C506
C506
C10u6.3X50805
C10u6.3X50805
C516
C516
C22u6.3X0805
C22u6.3X0805
+VTT_CORE
+VTT_CORE +VTT_CORE
R161
R161
75R0402
75R0402
+VTT_CORE +VTT_CORE
R167
R167
130R1%0402
130R1%0402
Close to CPU Close to IMVP7
VTT_SENSE <44>
C499
C499
C22u6.3X0805
C22u6.3X0805
VR_SVID_ALERT# <45>
JNC16 X_0402JNC16 X_0402
JNC17 X_0402JNC17 X_0402
+VCC_CORE
R411
R411
100R1%0402
100R1%0402
R410
R410
100R1%0402
100R1%0402
C473
C473
X_C10u6.3X50805
X_C10u6.3X50805
1 2
1 2
C520
C520
C10u6.3X50805
C10u6.3X50805
+VTT_CORE
C513
C513
C22u6.3X0805
C22u6.3X0805
VCCSENSE <45>
VSSSENSE <45>
Close to CPU
C
C171
C171
X_C22u6.3X0805
X_C22u6.3X0805
R158
R158
54.9R1%0402
54.9R1%0402
R156
R156
130R1%0402
130R1%0402
8.5 A
C177
C177
X_C10u6.3X50805
X_C10u6.3X50805
VR_SVID_CLK <45>
VR_SVID_DATA <45>
C180
C180
X_C10u6.3X50805
X_C10u6.3X50805
22uF * 16
+VCC_CORE
+VTT_CORE
C526
C526
X_C10u6.3X50805
X_C10u6.3X50805
C192
C192
X_C22u6.3X0805
X_C22u6.3X0805
C511
C511
C22u6.3X0805
C22u6.3X0805
C158
C158
X_C22u6.3X0805
X_C22u6.3X0805
C515
C515
C22u6.3X0805
C22u6.3X0805
C136
C136
C22u6.3X0805
C22u6.3X0805
C528
C528
X_C22u6.3X0805
X_C22u6.3X0805
C194
C194
C22u6.3X0805
C22u6.3X0805
C519
C519
C22u6.3X0805
C22u6.3X0805
C187
C187
C22u6.3X0805
C22u6.3X0805
C137
C137
C22u6.3X0805
C22u6.3X0805
C188
C188
C22u6.3X0805
C22u6.3X0805
C193
C193
X_C22u6.3X0805
X_C22u6.3X0805
C482
C482
C22u6.3X0805
C22u6.3X0805
C191
C191
X_C22u6.3X0805
X_C22u6.3X0805
10uF * 10
+VCC_CORE
C503
C523
C181
C181
X_C10u6.3X50805
X_C10u6.3X50805
C134
C134
X_C10u6.3X50805
X_C10u6.3X50805
+VTT_CORE
R452
R452
X_100R1%0402
X_100R1%0402
VTT_SENSE
Place a 100 ohm catch resistor on VCCIO_SENSE to VCCIO.
PPDG note to include 100ohm catch resistors on all sense lines
D
C523
C10u6.3X50805
C10u6.3X50805
C530
C530
X_C10u6.3X50805
X_C10u6.3X50805
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
C503
C10u6.3X50805
C10u6.3X50805
C172
C172
X_C10u6.3X50805
X_C10u6.3X50805
PROCESSOR POWER
PROCESSOR POWER
PROCESSOR POWER
MS-16F31
MS-16F31
MS-16F31
C505
C505
C10u6.3X50805
C10u6.3X50805
C149
C149
X_C10u6.3X50805
X_C10u6.3X50805
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
E
C481
C481
C22u6.3X0805
C22u6.3X0805
C135
C135
C22u6.3X0805
C22u6.3X0805
C133
C133
X_C10u6.3X50805
X_C10u6.3X50805
C162
C162
X_C10u6.3X50805
X_C10u6.3X50805
6 61Thursday, December 15, 2011
6 61Thursday, December 15, 2011
6 61Thursday, December 15, 2011
10
10
10
A
B
C
D
E
IVYBRIDGE PROCESSOR (GRAPHICS POWER)
1 1
POWER
+VCC_GFXCORE
46 A
C587
C589
C589
X_C22u6.3X0805
X_C22u6.3X0805
C586
C586
C22u6.3X0805
C22u6.3X0805
2 2
PROCESSOR DRIVEN Vref PATH WAS STUFFED BY DEFAULT:
M1 Implementation: 0 ohm stuff, Mos unstuff
DRAMRST_CNTRL_PCH<4,15>
3 3
C223
C223
C22u6.3X0805
C22u6.3X0805
C591
C591
X_C22u6.3X0805
X_C22u6.3X0805
DDR_WR_VREF01
DDR_WR_VREF02
C587
X_C22u6.3X0805
X_C22u6.3X0805
C593
C593
C22u6.3X0805
C22u6.3X0805
R453 X_0R0603R453 X_0R0603
Q29
Q29
DS
X_N-BSS138_SOT23
X_N-BSS138_SOT23
G
G
X_N-BSS138_SOT23
X_N-BSS138_SOT23
DS
Q30
Q30
R454 X_0R0603R454 X_0R0603
C594
C594
X_C22u6.3X0805
X_C22u6.3X0805
C588
C588
C22u6.3X0805
C22u6.3X0805
M_VREF_DQ_DIMMA <10,11>
M_VREF_DQ_DIMMB <12,13>
C453
C453
C22u6.3X0805
C22u6.3X0805
C590
C590
C22u6.3X0805
C22u6.3X0805
C592
C592
C22u6.3X0805
C22u6.3X0805
AT24
AT23
AT21
AT20
AT18
AT17
AR24
AR23
AR21
AR20
AR18
AR17
AP24
AP23
AP21
AP20
AP18
AP17
AN24
AN23
AN21
AN20
AN18
AN17
AM24
AM23
AM21
AM20
AM18
AM17
AL24
AL23
AL21
AL20
AL18
AL17
AK24
AK23
AK21
AK20
AK18
AK17
AJ24
AJ23
AJ21
AJ20
AJ18
AJ17
AH24
AH23
AH21
AH20
AH18
AH17
U50G
U50G
VAXG1
VAXG2
VAXG3
VAXG4
VAXG5
VAXG6
VAXG7
VAXG8
VAXG9
VAXG10
VAXG11
VAXG12
VAXG13
VAXG14
VAXG15
VAXG16
VAXG17
VAXG18
VAXG19
VAXG20
VAXG21
VAXG22
VAXG23
VAXG24
VAXG25
VAXG26
VAXG27
VAXG28
VAXG29
VAXG30
VAXG31
VAXG32
VAXG33
VAXG34
VAXG35
VAXG36
VAXG37
VAXG38
VAXG39
VAXG40
VAXG41
VAXG42
VAXG43
VAXG44
VAXG45
VAXG46
VAXG47
VAXG48
VAXG49
VAXG50
VAXG51
VAXG52
VAXG53
VAXG54
VERF: 20mil trace width & 20mil spacing
+1_8VRUN
4 4
A
12
+
+
C125
C125
C100u6.3pSO
C100u6.3pSO
1.2 A
C124
C124
C22u6.3X0805
C22u6.3X0805
B
C122
C122
C1u10X0603
C1u10X0603
C123
C123
C1u10X0603
C1u10X0603
B6
VCCPLL1
A6
VCCPLL2
A2
VCCPLL3
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
R151 10-K pull-down resistor should be placed on the VCCSA VID lines.
This will ensure the VID is 00 prior to VCCIO stability.
POWER
SENSE
SENSE
GRAPHICS
GRAPHICS
1.8V RAIL
1.8V RAIL
C
VAXG_SENSE
VSSAXG_SENSE
LINES
LINES
SM_VREF
SA_DIMM_VREFDQ
VREFMISC
VREFMISC
SB_DIMM_VREFDQ
DDR3 -1.5V RAILS
DDR3 -1.5V RAILS
SA RAIL
SA RAIL
VCCSA_SENSE
VCCSA_VID[0]
VCCSA_VID[1]
VCCIO_SEL
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VCCSA1
VCCSA2
VCCSA3
VCCSA4
VCCSA5
VCCSA6
VCCSA7
VCCSA8
+VCC_GFXCORE
AK35
AK34
AL1
DDR_WR_VREF01
B4
DDR_WR_VREF02
D1
AF7
AF4
AF1
AC7
AC4
AC1
Y7
Y4
Y1
U7
U4
U1
P7
P4
P1
M27
M26
L26
J26
J25
J24
H26
H25
R451 X_100R1%0402R451 X_100R1%0402
H23
C22
C24
A19
R371
R371
100R1%0402
100R1%0402
VCC_AXG_SENSE <45>
VSS_AXG_SENSE <45>
R376
R376
100R1%0402
100R1%0402
SM_VERF should have 20mil trace width & 20mil spacing
If iGPU noused, can be left connect.
SM_VREF
R413 X_1KR1%0402R413 X_1KR1%0402
R412 X_1KR1%0402R412 X_1KR1%0402
Connect with ChA, ChB.
C189
C183
C183
C0.1u10X0402
C0.1u10X0402
C185
C185
C0.1u10X0402
C0.1u10X0402
C152
C152
C10u6.3X50805
C10u6.3X50805
C189
X_C10u6.3X50805
X_C10u6.3X50805
6 A
C150
C160
C160
X_C0.1u10X0402
X_C0.1u10X0402
+0.85VRUN
H_SNB_IVB#_PWRCTRL <44>
On CRB:
Low-- VTT 1.0V
High--- VTT 1.05V
D
C142
C142
X_C10u6.3X50805
X_C10u6.3X50805
Place a 100 ohm catch resistor on VCCSA_SENSE
to VCCSA rail when CPU is not present.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
Date: Sheet of
Date: Sheet of
Date: Sheet of
C150
C10u6.3X50805
C10u6.3X50805
R151
R151
10KR0402
10KR0402
PROCESSOR GRAPHIC POWER
PROCESSOR GRAPHIC POWER
PROCESSOR GRAPHIC POWER
MS-16F31
MS-16F31
MS-16F31
+1_5VRUN
R409
R409
1KR1%0402
1KR1%0402
R407
+
+
12
C190
C190
C330u2.5KO
C330u2.5KO
7 61Thursday, December 15, 2011
7 61Thursday, December 15, 2011
7 61Thursday, December 15, 2011
R407
1KR1%0402
1KR1%0402
+1_5VRUN
C534
C534
C0.1u10X0402
C0.1u10X0402
5 A
C170
C170
C10u6.3X50805
C10u6.3X50805
+0.85VRUN
C157
C157
C10u6.3X50805
C10u6.3X50805
R394
R394
10KR0402
10KR0402
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
E
10
10
10
A
B
C
D
E
IVYBRIDGE PROCESSOR (GND)
U50I
U50H
U50H
AT35
VSS1
AT32
VSS2
AT29
VSS3
AT27
4 4
3 3
2 2
1 1
A
VSS4
AT25
VSS5
AT22
VSS6
AT19
VSS7
AT16
VSS8
AT13
VSS9
AT10
VSS10
AT7
VSS11
AT4
VSS12
AT3
VSS13
AR25
VSS14
AR22
VSS15
AR19
VSS16
AR16
VSS17
AR13
VSS18
AR10
VSS19
AR7
VSS20
AR4
VSS21
AR2
VSS22
AP34
VSS23
AP31
VSS24
AP28
VSS25
AP25
VSS26
AP22
VSS27
AP19
VSS28
AP16
VSS29
AP13
VSS30
AP10
VSS31
AP7
VSS32
AP4
VSS33
AP1
VSS34
AN30
VSS35
AN27
VSS36
AN25
VSS37
AN22
VSS38
AN19
VSS39
AN16
VSS40
AN13
VSS41
AN10
VSS42
AN7
VSS43
AN4
VSS44
AM29
VSS45
AM25
VSS46
AM22
VSS47
AM19
VSS48
AM16
VSS49
AM13
VSS50
AM10
VSS51
AM7
VSS52
AM4
VSS53
AM3
VSS54
AM2
VSS55
AM1
VSS56
AL34
VSS57
AL31
VSS58
AL28
VSS59
AL25
VSS60
AL22
VSS61
AL19
VSS62
AL16
VSS63
AL13
VSS64
AL10
VSS65
AL7
VSS66
AL4
VSS67
AL2
VSS68
AK33
VSS69
AK30
VSS70
AK27
VSS71
AK25
VSS72
AK22
VSS73
AK19
VSS74
AK16
VSS75
AK13
VSS76
AK10
VSS77
AK7
VSS78
AK4
VSS79
AJ25
VSS80
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
VSS
VSS
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
AJ22
AJ19
AJ16
AJ13
AJ10
AJ7
AJ4
AJ3
AJ2
AJ1
AH35
AH34
AH32
AH30
AH29
AH28
AH25
AH22
AH19
AH16
AH7
AH4
AG9
AG8
AG4
AF6
AF5
AF3
AF2
AE35
AE34
AE33
AE32
AE31
AE30
AE29
AE28
AE27
AE26
AE9
AD7
AC9
AC8
AC6
AC5
AC3
AC2
AB35
AB34
AB33
AB32
AB31
AB30
AB29
AB28
AB27
AB26
Y9
Y8
Y6
Y5
Y3
Y2
W35
W34
W33
W32
W31
W30
W29
W28
W27
W26
U9
U8
U6
U5
U3
U2
B
U50I
T35
VSS161
T34
VSS162
T33
VSS163
T32
VSS164
T31
VSS165
T30
VSS166
T29
VSS167
T28
VSS168
T27
VSS169
T26
VSS170
P9
VSS171
P8
VSS172
P6
VSS173
P5
VSS174
P3
VSS175
P2
VSS176
N35
VSS177
N34
VSS178
N33
VSS179
N32
VSS180
N31
VSS181
N30
VSS182
N29
VSS183
N28
VSS184
N27
VSS185
N26
VSS186
M34
VSS187
L33
VSS188
L30
VSS189
L27
VSS190
L9
VSS191
L8
VSS192
L6
VSS193
L5
VSS194
L4
VSS195
L3
VSS196
L2
VSS197
L1
VSS198
K35
VSS199
K32
VSS200
K29
VSS201
K26
VSS202
J34
VSS203
J31
VSS204
H33
VSS205
H30
VSS206
H27
VSS207
H24
VSS208
H21
VSS209
H18
VSS210
H15
VSS211
H13
VSS212
H10
VSS213
H9
VSS214
H8
VSS215
H7
VSS216
H6
VSS217
H5
VSS218
H4
VSS219
H3
VSS220
H2
VSS221
H1
VSS222
G35
VSS223
G32
VSS224
G29
VSS225
G26
VSS226
G23
VSS227
G20
VSS228
G17
VSS229
G11
VSS230
F34
VSS231
F31
VSS232
F29
VSS233
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
C
VSS
VSS
VSS234
VSS235
VSS236
VSS237
VSS238
VSS239
VSS240
VSS241
VSS242
VSS243
VSS244
VSS245
VSS246
VSS247
VSS248
VSS249
VSS250
VSS251
VSS252
VSS253
VSS254
VSS255
VSS256
VSS257
VSS258
VSS259
VSS260
VSS261
VSS262
VSS263
VSS264
VSS265
VSS266
VSS267
VSS268
VSS269
VSS270
VSS271
VSS272
VSS273
VSS274
VSS275
VSS276
VSS277
VSS278
VSS279
VSS280
VSS281
VSS282
VSS283
VSS284
VSS285
F22
F19
E30
E27
E24
E21
E18
E15
E13
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D35
D32
D29
D26
D20
D17
C34
C31
C28
C27
C25
C23
C10
C1
B22
B19
B17
B15
B13
B11
B9
B8
B7
B5
B3
B2
A35
A32
A29
A26
A23
A20
A3
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
PROCESSOR GND
PROCESSOR GND
PROCESSOR GND
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
Date: Sheet of
D
MICRO-STAR INT'L CO.,LTD.
E
10
10
10
8 61Thursday, December 15, 2011
8 61Thursday, December 15, 2011
8 61Thursday, December 15, 2011
A
B
C
D
E
IVYBRIDGE PROCESSOR (RESERVED)
U50E
U50E
1 1
2 2
3 3
TPJNC65TPJNC65
R174 X_1KR0402R174 X_1KR0402
R163 X_1KR0402R163 X_1KR0402
R168 X_1KR0402R168 X_1KR0402
R175 X_1KR0402R175 X_1KR0402
R173 X_1KR0402R173 X_1KR0402
CFG0
CFG2
CFG4
CFG5
CFG6
CFG7
AK28
CFG[0]
AK29
CFG[1]
AL26
CFG[2]
AL27
CFG[3]
AK26
CFG[4]
AL29
CFG[5]
AL30
CFG[6]
AM31
CFG[7]
AM32
CFG[8]
AM30
CFG[9]
AM28
CFG[10]
AM26
CFG[11]
AN28
CFG[12]
AN31
CFG[13]
AN26
CFG[14]
AM27
CFG[15]
AK31
CFG[16]
AN29
CFG[17]
AJ31
VAXG_VAL_SENSE
AH31
VSSAXG_VAL_SENSE
AJ33
VCC_VAL_SENSE
AH33
VSS_VAL_SENSE
AJ26
RSVD5
F25
RSVD8
F24
RSVD9
F23
RSVD10
D24
RSVD11
G25
RSVD12
G24
RSVD13
E23
RSVD14
D23
RSVD15
C30
RSVD16
A31
RSVD17
B30
RSVD18
B29
RSVD19
D30
RSVD20
B31
RSVD21
A30
RSVD22
C29
RSVD23
J20
RSVD24
B18
RSVD25
CFG
CFG
VCC_DIE_SENSE
VSS_DIE_SENSE
RESERVED
RESERVED
RSVD28
RSVD29
RSVD30
RSVD31
RSVD32
RSVD33
RSVD34
RSVD35
RSVD37
RSVD38
RSVD39
RSVD40
RSVD_NCTF41
RSVD_NCTF42
RSVD_NCTF43
RSVD_NCTF44
RSVD_NCTF45
RSVD_NCTF46
RSVD_NCTF47
RSVD_NCTF48
RSVD_NCTF49
RSVD_NCTF50
RSVD51
RSVD52
BCLK_ITP
BCLK_ITP#
AH27
AH26
L7
AG7
AE7
AK2
W8
AT26
AM33
AJ27
T8
J16
H16
G16
AR35
AT34
AT33
AP35
AR34
B34
A33
A34
B35
C35
AJ32
AK32
AN35
AM35
TPJNC17JNC
TPJNC44JNC
TPJNC17TPJNC17
TPJNC44TPJNC44
PEG Static Lane Reversal
CFG2
Display Port Presence Strap
CFG4
PCIE Port Bifurcation Straps
CFG[5:6]
PEG DEFER TRAINING
CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
1:(Default) Normal Operation
ne Reversed
0:La
1:(Default) Disabled;
No Physical Display Port attached to Embedded Display Port
0:Enabled;
An external Display Port device is connected to the Embedded Display Port
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
0: PEG Wait for BIOS for training
KEY
AT2
AT1
AR1
B1
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
PROCESSOR RESERVED
PROCESSOR RESERVED
PROCESSOR RESERVED
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A4
A4
A4
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
C
Date: Sheet of
D
9 61Thursday, December 15, 2011
9 61Thursday, December 15, 2011
9 61Thursday, December 15, 2011
E
10
10
10
J15
RSVD27
4 4
Ivy Bridge_rPGA_2DPC_Rev0p61
Ivy Bridge_rPGA_2DPC_Rev0p61
A
B
RSVD_NCTF56
RSVD_NCTF57
RSVD_NCTF58
A
B
C
D
E
SODIMM #A0
SOCKET4A
M_A_A[15:0]<5,11>
1 1
M_A_BS0<5,11>
M_A_BS1<5,11>
M_A_BS2<5,11>
M_A_CS#0<5>
M_A_CS#1<5>
M_A_CLK_DDR0<5>
M_A_CLK_DDR#0<5>
M_A_CLK_DDR1<5>
M_A_CLK_DDR#1<5>
M_A_CKE0<5>
M_A_CKE1<5>
2 2
JNC40 X_0402JNC40 X_0402
1 2
JNC32 X_0402JNC32 X_0402
1 2
3 3
M_A_CAS#<5,11>
M_A_RAS#<5,11>
M_A_WE#<5,11>
SMB_CLK_DIMM<11,12,13,15>
SMB_DATA_DIMM<11,12,13,15>
M_A_ODT0<5>
M_A_ODT1<5>
M_A_DQS[7:0]<5,11>
M_A_DQS#[7:0]<5,11>
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
SA0_DIM0_0
SA1_DIM0_0
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
107
119
109
108
114
121
101
103
102
104
115
110
113
197
201
202
200
116
120
136
153
170
187
137
154
171
188
135
152
169
186
98
97
96
95
92
91
90
86
89
85
84
83
80
78
79
73
74
11
28
46
63
12
29
47
64
10
27
45
62
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC#
A13
A14
A15
BA0
BA1
BA2
S0#
S1#
CK0
CK0#
CK1
CK1#
CKE0
CKE1
CAS#
RAS#
WE#
SA0
SA1
SCL
SDA
ODT0
ODT1
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS#0
DQS#1
DQS#2
DQS#3
DQS#4
DQS#5
DQS#6
DQS#7
SOCKET4A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ[63:0] <5,11>
+3VRUN
C540
C540
C0.1u10X0402
C0.1u10X0402
TPJNC45TPJNC45
DDR3_DRAMRST#<4,11,12,13>
C512
C512
X_C10u6.3X0603
X_C10u6.3X0603
TPJNC45JNC
M_VREF_DQ_DIMMA_1
C469
C469
C0.1u10X0402
C0.1u10X0402
M_VREF_CA_DIMMA_1
C517
C517
C0.1u10X0402
C0.1u10X0402
VERF :20mil trace width & 20mil spacing
C514
C514
C1u10X0402
C1u10X0402
C493
C493
C1u10X0402
C1u10X0402
+1_5VDIMM
C535
C535
X_C2.2u6.3X0603
X_C2.2u6.3X0603
C470
C470
C2.2u6.3X0603
C2.2u6.3X0603
C518
C518
C2.2u6.3X0603
C2.2u6.3X0603
C483
C483
C1u10X0402
C1u10X0402
SOCKET4B
SOCKET4B
75
VDD
76
VDD
81
VDD
82
VDD
87
VDD
88
VDD
93
VDD
94
VDD
99
VDD
100
VDD
105
VDD
106
VDD
111
VDD
112
VDD
117
VDD
118
VDD
123
VDD
124
VDD
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204
SODIMM_S204
N13-2040060-L41
N13-2040060-L41
+1_5VDIMM+1_5VDIMM
C498
C498
C1u10X0402
C1u10X0402
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MEC1
MEC2
VTT
VTT
C508
C508
C10u6.3X50805
C10u6.3X50805
205
206
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
MEC1
MEC2
203
204
205
206
C501
C501
X_C10u6.3X50805
X_C10u6.3X50805
+0_75VRUN
C538
C538
C1u10X0603
C1u10X0603
C492
C492
C10u6.3X50805
C10u6.3X50805
C541
C541
C1u10X0603
C1u10X0603
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204
SODIMM_S204
N13-2040060-L41
N13-2040060-L41
Vref DQ & CA
R387
4 4
A
B
R387
1KR1%0402
1KR1%0402
M_VREF_DQ_DIMMA_1
R386
R386
1KR1%0402
1KR1%0402
R455 X_0R0603R455 X_0R0603
C
M_VREF_DQ_DIMMA <7,11>
+1_5VDIMM+1_5VDIMM
R404
R404
1KR1%0402
1KR1%0402
M_VREF_CA_DIMMA_1
R405
R405
1KR1%0402
1KR1%0402
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
DDR3 SODIMM A0
DDR3 SODIMM A0
DDR3 SODIMM A0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
10 61Thursday, December 15, 2011
10 61Thursday, December 15, 2011
10 61Thursday, December 15, 2011
E
10
10
10
A
B
C
D
E
SODIMM #A1
SOCKET1A
M_A_A[15:0]<5,10>
4 4
M_A_BS0<5,10>
M_A_BS1<5,10>
+3VRUN
R434
R434
10KR0402
3 3
2 2
10KR0402
JNC13 X_0402JNC13 X_0402
1 2
M_A_BS2<5,10>
M_A_CS#2<5>
M_A_CS#3<5>
M_A_CLK_DDR2<5>
M_A_CLK_DDR#2<5>
M_A_CLK_DDR3<5>
M_A_CLK_DDR#3<5>
M_A_CKE2<5>
M_A_CKE3<5>
M_A_CAS#<5,10>
M_A_RAS#<5,10>
M_A_WE#<5,10>
SMB_CLK_DIMM<10,12,13,15>
SMB_DATA_DIMM<10,12,13,15>
M_A_ODT2<5>
M_A_ODT3<5>
M_A_DQS[7:0]<5,10>
M_A_DQS#[7:0]<5,10>
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
SA0_DIM0_1
SA1_DIM0_1
M_A_DQS0
M_A_DQS1
M_A_DQS2
M_A_DQS3
M_A_DQS4
M_A_DQS5
M_A_DQS6
M_A_DQS7
M_A_DQS#0
M_A_DQS#1
M_A_DQS#2
M_A_DQS#3
M_A_DQS#4
M_A_DQS#5
M_A_DQS#6
M_A_DQS#7
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204_H5_2_1
SODIMM_S204_H5_2_1
N13-2040120-F02
N13-2040120-F02
SOCKET1A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ35
M_A_DQ36
M_A_DQ37
M_A_DQ38
M_A_DQ39
M_A_DQ40
M_A_DQ41
M_A_DQ42
M_A_DQ43
M_A_DQ44
M_A_DQ45
M_A_DQ46
M_A_DQ47
M_A_DQ48
M_A_DQ49
M_A_DQ50
M_A_DQ51
M_A_DQ52
M_A_DQ53
M_A_DQ54
M_A_DQ55
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
M_A_DQ60
M_A_DQ61
M_A_DQ62
M_A_DQ63
M_A_DQ[63:0] <5,10>
+3VRUN
C205
C205
C0.1u10X0402
C0.1u10X0402
TPJNC19TPJNC19
DDR3_DRAMRST#<4,10,12,13>
C551
C551
X_C10u6.3X0603
X_C10u6.3X0603
TPJNC19JNC
M_VREF_DQ_DIMMA_0
C116
C116
C0.1u10X0402
C0.1u10X0402
M_VREF_CA_DIMMA_0
C174
C174
C0.1u10X0402
C0.1u10X0402
VERF: 20mil width & 20mil spacing
C139
C151
C151
C1u10X0402
C1u10X0402
C139
C1u10X0402
C1u10X0402
+1_5VDIMM
C202
C202
X_C2.2u6.3X0603
X_C2.2u6.3X0603
C114
C114
C2.2u6.3X0603
C2.2u6.3X0603
C182
C182
C2.2u6.3X0603
C2.2u6.3X0603
C131
C131
C1u10X0402
C1u10X0402
SOCKET1B
SOCKET1B
75
VDD
76
VDD
81
VDD
82
VDD
87
VDD
88
VDD
93
VDD
94
VDD
99
VDD
100
VDD
105
VDD
106
VDD
111
VDD
112
VDD
117
VDD
118
VDD
123
VDD
124
VDD
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204_H5_2_1
SODIMM_S204_H5_2_1
N13-2040120-F02
N13-2040120-F02
+1_5VDIMM+1_5VDIMM
C159
C159
C1u10X0402
C1u10X0402
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MEC1
MEC2
VTT
VTT
205
206
C128
C128
C10u6.3X0603
C10u6.3X0603
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
MEC1
MEC2
203
204
205
206
C225
C225
C1u10X0603
C1u10X0603
C165
C165
C10u6.3X0603
C10u6.3X0603
+0_75VRUN
C224
C224
C1u10X0603
C1u10X0603
C169
C169
C10u6.3X0603
C10u6.3X0603
+1_5VDIMM +1_5VDIMM
R121
1 1
A
B
R121
1KR1%0402
1KR1%0402
M_VREF_DQ_DIMMA_0
R122
R122
1KR1%0402
1KR1%0402
Vref DQ & CA
R456 X_0R0603R456 X_0R0603
C
M_VREF_DQ_DIMMA <7,10>
R143
R143
1KR1%0402
1KR1%0402
M_VREF_CA_DIMMA_0
R145
R145
1KR1%0402
1KR1%0402
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
DDR3 SODIMM A1
DDR3 SODIMM A1
DDR3 SODIMM A1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
11 61Thursday, December 15, 2011
11 61Thursday, December 15, 2011
11 61Thursday, December 15, 2011
E
10
10
10
A
B
C
D
E
SODIMM #B0
SOCKET3A
SOCKET3A
M_B_A0
M_B_A1
M_B_A2
M_B_A3
1 1
M_B_BS0<5,13>
M_B_BS1<5,13>
M_B_BS2<5,13>
M_B_CS#0<5>
M_B_CS#1<5>
+3VRUN
R415
R415
2 2
10KR0402
10KR0402
1 2
JNC41 X_0402JNC41 X_0402
3 3
M_B_CLK_DDR0<5>
M_B_CLK_DDR#0<5>
M_B_CLK_DDR1<5>
M_B_CLK_DDR#1<5>
M_B_CKE0<5>
M_B_CKE1<5>
M_B_CAS#<5,13>
M_B_RAS#<5,13>
M_B_WE#<5,13>
SMB_CLK_DIMM<10,11,13,15>
SMB_DATA_DIMM<10,11,13,15>
M_B_ODT0<5>
M_B_ODT1<5>
M_B_DQS[7:0]<5,13>
M_B_DQS#[7:0]<5,13>
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
SA0_DIM1_0
SA1_DMI1_0
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204_1
SODIMM_S204_1
N13-2040080-L41
N13-2040080-L41
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ[63:0] <5,13>M_B_A[15:0]<5,13>
TPJNC46TPJNC46
DDR3_DRAMRST#<4,10,11,13>
C554
C554
X_C10u6.3X0603
X_C10u6.3X0603
TPJNC46JNC
M_VREF_DQ_DIMMB_1
C468
C468
C0.1u10X0402
C0.1u10X0402
M_VREF_CA_DIMMB_1
C522
C522
C0.1u10X0402
C0.1u10X0402
VERF: 20mil trace width & 20mil spacing
+1_5VDIMM
C156
C156
C1u10X0402
C1u10X0402
C480
C480
C1u10X0402
C1u10X0402
C168
C168
C1u10X0402
C1u10X0402
+3VRUN
C537
C537
C0.1u10X0402
C0.1u10X0402
C467
C467
C2.2u6.3X0603
C2.2u6.3X0603
C525
C525
C2.2u6.3X0603
C2.2u6.3X0603
+1_5VDIMM
C488
C488
C1u10X0402
C1u10X0402
SOCKET3B
SOCKET3B
75
VDD
76
VDD
81
VDD
82
VDD
87
VDD
88
VDD
93
VDD
94
VDD
99
VDD
100
VDD
105
VDD
106
VDD
111
VDD
112
VDD
117
VDD
118
VDD
123
VDD
124
VDD
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204_1
SODIMM_S204_1
N13-2040080-L41
N13-2040080-L41
+1_5VDIMM
+
+
12
C155
C155
X_C330u2.5KO
X_C330u2.5KO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MEC1
MEC2
VTT
VTT
205
206
C479
C479
C10u6.3X50805
C10u6.3X50805
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
MEC1
MEC2
203
204
205
206
C545
C545
C1u10X0603
C1u10X0603
C510
C510
C10u6.3X0603
C10u6.3X0603
+0_75VRUN
C542
C542
C1u10X0603
C1u10X0603
C144
C144
C10u6.3X50805
C10u6.3X50805
Vref DQ & CA
R385
4 4
A
B
R385
1KR1%0402
1KR1%0402
M_VREF_DQ_DIMMB_1
R384
R384
1KR1%0402
1KR1%0402
R457 X_0R0603R457 X_0R0603
C
M_VREF_DQ_DIMMB <7,13>
+1_5VDIMM+1_5VDIMM
R403
R403
1KR1%0402
1KR1%0402
R406
R406
1KR1%0402
1KR1%0402
M_VREF_CA_DIMMB_1
D
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
DDR3 SODIMM B0
DDR3 SODIMM B0
DDR3 SODIMM B0
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
12 61Thursday, December 15, 2011
12 61Thursday, December 15, 2011
12 61Thursday, December 15, 2011
E
10
10
10
A
B
C
D
E
SODIMM #B1
SOCKET2A
M_B_A[15:0]<5,12>
1 1
M_B_BS0<5,12>
M_B_BS1<5,12>
M_B_BS2<5,12>
M_B_CS#2<5>
M_B_CS#3<5>
+3VRUN +3VRUN
R210
R186
R186
2 2
10KR0402
10KR0402
3 3
R210
10KR0402
10KR0402
M_B_CLK_DDR2<5>
M_B_CLK_DDR#2<5>
M_B_CLK_DDR3<5>
M_B_CLK_DDR#3<5>
M_B_CKE2<5>
M_B_CKE3<5>
M_B_CAS#<5,12>
M_B_RAS#<5,12>
M_B_WE#<5,12>
SMB_CLK_DIMM<10,11,12,15>
SMB_DATA_DIMM<10,11,12,15>
M_B_ODT2<5>
M_B_ODT3<5>
M_B_DQS[7:0]<5,12>
M_B_DQS#[7:0]<5,12>
M_B_A0
M_B_A1
M_B_A2
M_B_A3
M_B_A4
M_B_A5
M_B_A6
M_B_A7
M_B_A8
M_B_A9
M_B_A10
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
SA0_DIM1_1
SA1_DIM1_1
M_B_DQS0
M_B_DQS1
M_B_DQS2
M_B_DQS3
M_B_DQS4
M_B_DQS5
M_B_DQS6
M_B_DQS7
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
98
A0
97
A1
96
A2
95
A3
92
A4
91
A5
90
A6
86
A7
89
A8
85
A9
107
A10/AP
84
A11
83
A12/BC#
119
A13
80
A14
78
A15
109
BA0
108
BA1
79
BA2
114
S0#
121
S1#
101
CK0
103
CK0#
102
CK1
104
CK1#
73
CKE0
74
CKE1
115
CAS#
110
RAS#
113
WE#
197
SA0
201
SA1
202
SCL
200
SDA
116
ODT0
120
ODT1
11
DM0
28
DM1
46
DM2
63
DM3
136
DM4
153
DM5
170
DM6
187
DM7
12
DQS0
29
DQS1
47
DQS2
64
DQS3
137
DQS4
154
DQS5
171
DQS6
188
DQS7
10
DQS#0
27
DQS#1
45
DQS#2
62
DQS#3
135
DQS#4
152
DQS#5
169
DQS#6
186
DQS#7
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204
SODIMM_S204
N13-2040060-L41
N13-2040060-L41
SOCKET2A
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
M_B_DQ0
M_B_DQ1
M_B_DQ2
M_B_DQ3
M_B_DQ4
M_B_DQ5
M_B_DQ6
M_B_DQ7
M_B_DQ8
M_B_DQ9
M_B_DQ10
M_B_DQ11
M_B_DQ12
M_B_DQ13
M_B_DQ14
M_B_DQ15
M_B_DQ16
M_B_DQ17
M_B_DQ18
M_B_DQ19
M_B_DQ20
M_B_DQ21
M_B_DQ22
M_B_DQ23
M_B_DQ24
M_B_DQ25
M_B_DQ26
M_B_DQ27
M_B_DQ28
M_B_DQ29
M_B_DQ30
M_B_DQ31
M_B_DQ32
M_B_DQ33
M_B_DQ34
M_B_DQ35
M_B_DQ36
M_B_DQ37
M_B_DQ38
M_B_DQ39
M_B_DQ40
M_B_DQ41
M_B_DQ42
M_B_DQ43
M_B_DQ44
M_B_DQ45
M_B_DQ46
M_B_DQ47
M_B_DQ48
M_B_DQ49
M_B_DQ50
M_B_DQ51
M_B_DQ52
M_B_DQ53
M_B_DQ54
M_B_DQ55
M_B_DQ56
M_B_DQ57
M_B_DQ58
M_B_DQ59
M_B_DQ60
M_B_DQ61
M_B_DQ62
M_B_DQ63
M_B_DQ[63:0] <5,12>
+3VRUN
C206
C206
C0.1u10X0402
C0.1u10X0402
TPJNC18TPJNC18
DDR3_DRAMRST#<4,10,11,12>
C556
C556
X_C10u6.3X0603
X_C10u6.3X0603
M_VREF_DQ_DIMMB_0
C112
C112
C0.1u10X0402
C0.1u10X0402
M_VREF_CA_DIMMB_0
C175
C175
C0.1u10X0402
C0.1u10X0402
TPJNC18JNC
VERF: 20mil trace width & 20mil spacing
C154
C143
C143
C1u10X0402
C1u10X0402
C154
C1u10X0402
C1u10X0402
+1_5VDIMM
C211
C211
X_C2.2u6.3X0603
X_C2.2u6.3X0603
C110
C110
C2.2u6.3X0603
C2.2u6.3X0603
C178
C178
C2.2u6.3X0603
C2.2u6.3X0603
C164
C164
C1u10X0402
C1u10X0402
SOCKET2B
SOCKET2B
75
VDD
76
VDD
81
VDD
82
VDD
87
VDD
88
VDD
93
VDD
94
VDD
99
VDD
100
VDD
105
VDD
106
VDD
111
VDD
112
VDD
117
VDD
118
VDD
123
VDD
124
VDD
199
VDDSPD
77
NC1
122
NC2
125
NCTEST
198
EVENT#
30
RESET#
1
VREF_DQ
126
VREF_CA
2
VSS
3
VSS
8
VSS
9
VSS
13
VSS
14
VSS
19
VSS
20
VSS
25
VSS
26
VSS
31
VSS
32
VSS
37
VSS
38
VSS
43
VSS
DDR3SODIMM-204PS_BLACK
DDR3SODIMM-204PS_BLACK
SODIMM_S204
SODIMM_S204
N13-2040060-L41
N13-2040060-L41
+1_5VDIMM+1_5VDIMM
C146
C146
C1u10X0402
C1u10X0402
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
MEC1
MEC2
VTT
VTT
205
206
C476
C476
X_C10u6.3X50805
X_C10u6.3X50805
44
48
49
54
55
60
61
65
66
71
72
127
128
133
134
138
139
144
145
150
151
155
156
161
162
167
168
172
173
178
179
184
185
189
190
195
196
MEC1
MEC2
203
204
205
206
C475
C475
X_C10u6.3X50805
X_C10u6.3X50805
+0_75VRUN
C208
C208
C1u10X0603
C1u10X0603
C474
C474
X_C10u6.3X50805
X_C10u6.3X50805
C204
C204
C1u10X0603
C1u10X0603
Vref DQ & CA
R120
4 4
A
B
R120
1KR1%0402
1KR1%0402
M_VREF_DQ_DIMMB_0
R118
R118
1KR1%0402
1KR1%0402
R458 X_0R0603R458 X_0R0603
C
M_VREF_DQ_DIMMB <7,12>
+1_5VDIMM+1_5VDIMM
R144
R144
1KR1%0402
1KR1%0402
M_VREF_CA_DIMMB_0
R142
R142
1KR1%0402
1KR1%0402
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
DDR3 SODIMM B1
DDR3 SODIMM B1
DDR3 SODIMM B1
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
13 61Thursday, December 15, 2011
13 61Thursday, December 15, 2011
13 61Thursday, December 15, 2011
E
10
10
10
A
+3VALW
D6
D6
S-BAT54C_SOT23
S-BAT54C_SOT23
Y
Z
X
1 1
BH1X2HS-1.25PITCH
BH1X2HS-1.25PITCH
BAT2
BAT2
RTC_BAT
RTC_BAT
2 2
D06-0100300-K26
D06-0100300-K26
CODEC_HDA_RST#<33>
CODEC_HDA_BITCLK<33>
CODEC_HDA_SYNC<33>
CODEC_HDA_SDOUT<33>
SPI_MISO
SPI_MOSI
3 3
SPI_CS0#
SPI_CLK
SPI_HOLD#_B
RTC_P2
R119
R119
1KR0402
1KR0402
RTC_P3
CN2
CN2
1
2
N32-1020790-A81
N32-1020790-A81
+3VRUN
1
2
3
4
5
6
7
8
9
10
34
EC7
EC7
1112
CON6
CON6
X_BH1X10HS-1.25PITCH_WHITE
X_BH1X10HS-1.25PITCH_WHITE
FPC_CONN_12P
FPC_CONN_12P
N32-1100130-H06
N32-1100130-H06
C111
C111
C1u10X0603
C1u10X0603
C10p50N0402
C10p50N0402
EC6
EC6
RTCVCC
C10p50N0402
C10p50N0402
R292 20KR0402R292 20KR0402
RTCVCC
R296
R296
1MR0402
1MR0402
SM_INTRUDER#
RN1 Close PCH
EC5
EC5
C10p50N0402
C10p50N0402
R291 20KR0402R291 20KR0402
RN1
RN1
1
3
5
7
8P4R-33R0402
8P4R-33R0402
EC8
EC8
EMI
C10p50N0402
C10p50N0402
Signal has a weak internal pull-down
Note: The weak internal pull-down is disabled after PLTRST# deasserts.
Change to 8MB
+3VRUN+3VRUN+3VRUN
R44
R44
3.3KR0402
3.3KR0402
SPI_CS0#
4 4
SPI_MISO SPI_HOLD#_B
C58 C0.1u16Y0402C58 C0.1u16Y0402
U14
U14
1
CS
2
DO(IO1)
3
WP(IO2)
4
GND
W25Q64CVSSIG
W25Q64CVSSIG
SIC8_SST_S2A
SIC8_SST_S2A
M31-25Q6423-W03
M31-25Q6423-W03
A
VCC
HOLD(IO3)
CLK
DI(IO0)
R45
R45
3.3KR0402
8
7
SPI_CLK
6
SPI_MOSI
5
3.3KR0402
B
C333
C333
C1u10X0603
C1u10X0603
C332
C332
C1u16Y0603
C1u16Y0603
RTCVCC
2
4
6
8
FLASH_SECURITY<28>
CODEC_HDA_SDIN0<33>
Flash Descriptor Security Protect
HDA_SDO
Low = Enable
High = Disable
SPI_CLK
Reserved for Codec use RUN.
Checklist: Needs to be pulled high for HR
HDA_SYNC
This signal has a weak internal pull-down.
The strap is sampled on the rising edge of RSMRST# signal.
B
Low = On Die PLL VR is supplied by 1.8V
High = On Die PLL VR is supplied by 1.5V
C53 C18p50N0402C53 C18p50N0402
Y1
32.768KHZ12.5p_S
32.768KHZ12.5p_S
C52 C18p50N0402C52 C18p50N0402
R40 330KR0402R40 330KR0402
SPKR<33>
R33 1KR0402R33 1KR0402
R72 22R0402R72 22R0402
EC14
EC14
C10p50N0402
C10p50N0402
EMI
HDA_SYNC_PCH_R
C
CPT & PPT (HDA,JTAG,SATA)
RTCX1JNC
R41
R41
10MR1%0402
Y1
Y1
10MR1%0402
1 2
RTCX2JNC
HDA_BIT_CLK_PCH_R
HDA_SYNC_PCH_R
HDA_RST#_PCH_R
R287 33R0402R287 33R0402
+3VSUS
R287 Close Codec
R32
R32
X_1KR0402
X_1KR0402
HDA_SDOUT_PCH_R
TPJNC8TPJNC8
TPJNC33TPJNC33
TPJNC31TPJNC31
TPJNC34TPJNC34
TPJNC32TPJNC32
TPJNC48TPJNC48
+3VSUS
R30
R30
1KR0402
1KR0402
RTCRST#
SRTCRST#
PCH_INTVRMEN
HDA_SDIN0_R
HDA_DOCK_ENJNC
TPJNC33JNC
TPJNC31JNC
TPJNC34JNC
TPJNC32JNC
SPI_CLKR
SPI_CS0#
TPJNC48JNC
SPI_MOSI
SPI_MISO
U16A
U16A
A20
RTCX1
C20
RTCX2
D20
RTCRST#
G22
SRTCRST#
K22
INTRUDER#
C17
INTVRMEN
N34
HDA_BCLK
L34
HDA_SYNC
T10
SPKR
K34
HDA_RST#
E34
HDA_SDIN0
G34
HDA_SDIN1
C34
HDA_SDIN2
A34
HDA_SDIN3
A36
HDA_SDO
C36
HDA_DOCK_EN# / GPIO33
N32
HDA_DOCK_RST# / GPIO13
J3
JTAG_TCK
H7
JTAG_TMS
K5
JTAG_TDI
H1
JTAG_TDO
T3
SPI_CLK
Y14
SPI_CS0#
T1
SPI_CS1#
V4
SPI_MOSI
U3
SPI_MISO
Panther_Point_QS
Panther_Point_QS
RTCIHDA
RTCIHDA
JTAG
JTAG
SPI
SPI
SPK
C
FWH0 / LAD0
FWH1 / LAD1
FWH2 / LAD2
FWH3 / LAD3
LPC
LPC
FWH4 / LFRAME#
LDRQ1# / GPIO23
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
SATA1RXN
SATA1RXP
SATA 6G
SATA 6G
SATA1TXN
SATA1TXP
SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP
SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP
SATA4RXN
SATA4RXP
SATA4TXN
SATA
SATA
SATA4TXP
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
SATAICOMPO
SATAICOMPI
SATA3RCOMPO
SATA3COMPI
SATA3RBIAS
SATALED#
SATA0GP / GPIO21
SATA1GP / GPIO19
The Signal has a weak internal pull-down
Note: the internal pull-down is disabled after PLTRST# deasserts.
If the signal is sampled high, this indicates that the system is strapped to the "No Reboot" mode
(Panther Point will disable the TCO Timer system reboot feature)
D
+3VRUN
C38
A38
B37
C37
D36
E36
LDRQ0#
K36
V5
SERIRQ
AM3
AM1
AP7
AP5
AM10
AM8
AP11
AP10
AD7
AD5
AH5
AH4
AB8
AB10
AF3
AF1
Y7
Y5
AD3
AD1
Y3
Y1
AB3
SATAICOMP/SATA3COMP
AB1
Width:8mil Spacing:15mil
Y11
SATAICOMP
Y10
AB12
AB13
AH1
Unused SATAxGP pins must be terminated to either VCC3_3 rail or GND using 8.2-kΩ to 10kΩ
P3
V14
P1
close to the PCH
SATA3COMP
R82 750R1%0402R82 750R1%0402
BBS_BIT0
R64
R64
X_1KR0402
X_1KR0402
LAD0 <28>
LAD1 <28>
LAD2 <28>
LAD3 <28>
LPC_FRAME# <28>
L_LDRQ0# <28>
SATA0RXN <37>
SATA0RXP <37>
SATA0TXN <37>
SATA0TXP <37>
SATA1RXN <37>
SATA1RXP <37>
SATA1TXN <37>
SATA1TXP <37>
SATA2RXN <37>
SATA2RXP <37>
SATA2TXN <37>
SATA2TXP <37>
ESATA_RXN <32>
ESATA_RXP <32>
ESATA_TXN <32>
ESATA_TXP <32>
SATA4RXN <39>
SATA4RXP <39>
SATA4TXN <39>
SATA4TXP <39>
R347 37.4R1%0402R347 37.4R1%0402
R351 49.9R1%0402R351 49.9R1%0402
R349 10KR0402R349 10KR0402
R63 10KR0402R63 10KR0402
SATA_ACTIVE# <39>
R344
R344
10KR0402
10KR0402
INT_SERIRQ <28>
mSATA GEN3(6Gb/s)
mSATA GEN3(6Gb/s)
ODD
eSATA
To A board
VTT
+3VRUN
+3VRUN
BBS_BIT0--BIIOS BOOT STRAP BIT0
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
Title
Title
Title
PCH_HDA/JTAG/SATA
PCH_HDA/JTAG/SATA
PCH_HDA/JTAG/SATA
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
MICRO-STAR INT'L CO.,LTD.
E
10
10
10
14 61Thursday, December 15, 2011
14 61Thursday, December 15, 2011
14 61Thursday, December 15, 2011
E
A
B
C
D
E
CPT & PPT (PCI-E,SMBUS,CLK)
U16B
U16B
PCIE_GLAN_RXN<35>
PCIE_GLAN_RXP<35>
PCIE_CARDREADER_RXN<36>
PCIE_CARDREADER_RXP<36>
PCIE_CARDREADER_TXN<36>
PCIE_CARDREADER_TXP<36>
CARDREADER_CLKREQ#<36>
PCIE_GLAN_TXN<35>
PCIE_GLAN_TXP<35>
PCIE_MINI1_RXN<38>
PCIE_MINI1_RXP<38>
PCIE_MINI1_TXN<38>
PCIE_MINI1_TXP<38>
CLK_PCIE_LAN#<35>
CLK_PCIE_LAN<35>
CLK_GLAN_OE#<35>
CLK_CARDREADER_N<36>
CLK_CARDREADER_P<36>
CLK_MINI_PCIE2#<38>
CLK_MINI_PCIE2<38>
RN12
RN12
1
3
5
7
8P4R-10K0402
8P4R-10K0402
2
4
6
8
1 1
2 2
3 3
+3VSUS
4 4
Intel Comments:
If CLKREQ# control is not needed, say for a free running clock, DO NOT pull-down signal to GND. This will increase leakage in Sx states.
PCIe devices or addin cards that do NOT support CLKREQ# functionality should not route this signal to PCH.
Intel recommends terminating PCIECLKRQx# pin on PCH with 10 kΩ ±10% external pull-up resistor instead of No Connect.
C431 C0.1u10X0402C431 C0.1u10X0402
C427 C0.1u10X0402C427 C0.1u10X0402
C420 C0.1u10X0402C420 C0.1u10X0402
C416 C0.1u10X0402C416 C0.1u10X0402
C452 C0.1u10X0402C452 C0.1u10X0402
C451 C0.1u10X0402C451 C0.1u10X0402
+3VRUN
+3VSUS
+3VSUS
+3VSUS
TPJNC55TPJNC55
TPJNC52TPJNC52
PETN1_JNC
PETP1_JNC
PETN3_JNC
PETP3_JNC
PETN5_JNC
PETP5_JNC
R28 10KR0402R28 10KR0402
R346 X_10KR0402R346 X_10KR0402
R140 10KR0402R140 10KR0402
R58 10KR0402R58 10KR0402
R157 10KR0402R157 10KR0402
XDP_CPU_CLK_N_R
XDP_CPU_CLK_P_R
BG34
PERN1
BJ34
PERP1
AV32
PETN1
AU32
PETP1
BE34
PERN2
BF34
PERP2
BB32
PETN2
AY32
PETP2
BG36
PERN3
BJ36
PERP3
AV34
PETN3
AU34
PETP3
BF36
PERN4
BE36
PERP4
AY34
PETN4
BB34
PETP4
BG37
PERN5
BH37
PERP5
AY36
PETN5
BB36
PETP5
BJ38
PERN6
BG38
PERP6
AU36
PETN6
AV36
PETP6
BG40
PERN7
BJ40
PERP7
AY40
PETN7
BB40
PETP7
BE38
PERN8
BC38
PERP8
AW38
PETN8
AY38
PETP8
Y40
CLKOUT_PCIE0N
Y39
CLKOUT_PCIE0P
J2
PCIECLKRQ0# / GPIO73
AB49
CLKOUT_PCIE1N
AB47
CLKOUT_PCIE1P
M1
PCIECLKRQ1# / GPIO18
AA48
CLKOUT_PCIE2N
AA47
CLKOUT_PCIE2P
V10
PCIECLKRQ2# / GPIO20
Y37
CLKOUT_PCIE3N
Y36
CLKOUT_PCIE3P
A8
PCIECLKRQ3# / GPIO25
Y43
CLKOUT_PCIE4N
Y45
CLKOUT_PCIE4P
L12
PCIECLKRQ4# / GPIO26
V45
CLKOUT_PCIE5N
V46
CLKOUT_PCIE5P
L14
PCIECLKRQ5# / GPIO44
AB42
CLKOUT_PEG_B_N
AB40
CLKOUT_PEG_B_P
E6
PEG_B_CLKRQ# / GPIO56
V40
CLKOUT_PCIE6N
V42
CLKOUT_PCIE6P
T13
PCIECLKRQ6# / GPIO45
V38
CLKOUT_PCIE7N
V37
CLKOUT_PCIE7P
K12
PCIECLKRQ7# / GPIO46
AK14
CLKOUT_ITPXDP_N
AK13
CLKOUT_ITPXDP_P
Panther_Point_QS
Panther_Point_QS
SMBUSController
SMBUSController
SML1ALERT# / PCHHOT# / GPIO74
PCI-E*
PCI-E*
CLOCKS
CLOCKS
SMBALERT# / GPIO11
DDR
SML0ALERT# / GPIO60
PHY
SML1CLK / GPIO58
EC...
SML1DATA / GPIO75
Link
Link
PEG_A_CLKRQ# / GPIO47
CLKOUT_PEG_A_N
CLKOUT_PEG_A_P
CLKOUT_DMI_N
CLKOUT_DMI_P
CLKOUT_DP_N
CLKOUT_DP_P
CLKIN_GND1_N
CLKIN_GND1_P
CLKIN_DOT_96N
CLKIN_DOT_96P
CLKIN_SATA_N
CLKIN_SATA_P
CLKIN_PCILOOPBACK
CLKOUTFLEX0 / GPIO64
CLKOUTFLEX1 / GPIO65
CLKOUTFLEX2 / GPIO66
CLKOUTFLEX3 / GPIO67
FLEX CLOCKS
FLEX CLOCKS
SMBCLK
SMBDATA
SML0CLK
SML0DATA
CL_CLK1
CL_DATA1
CL_RST1#
CLKIN_DMI_N
CLKIN_DMI_P
REFCLK14IN
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
PCH_GPIO11
E12
SUS_SMBCLK
H14
SUS_SMBDATA
C9
A12
C8
G12
C13
E14
M16
M7
T11
P10
M10
AB37
AB38
AV22
AU22
AM12
AM13
BF18
BE18
BJ30
BG30
G24
E24
AK7
AK5
K45
H45
V47
V49
Y47
DRAMRST_CNTRL_PCH <4,7>
SML0_CLK
SML0_DATA
PCH_GPIO74
SML1_CLK
SML1_DATA
CLK_EXP#
CLK_EXP
CLOKOUT_DP_N_R
CLOKOUT_DP_P_R
CLK_BUF_EXP#
CLK_BUF_EXP
CLK_BUF_CPYCLKN
CLK_BUF_CPYCLKP
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_SATA#
CLK_BUF_SATA
CLK_BUF_REF14
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
XCLK_RCOMP 4 mils Width
TP_CLK_FLEX0JNC
K43
TP_CLK_FLEX1JNC
F47
TP_CLK_FLEX2JNC
H47
DGPU_PRSNT#
K49
+3VSUS
R284
R284
10KR0402
10KR0402
CLK_PEGA_MXM_N <24>
CLK_PEGA_MXM_P <24>
CLK_EXP# <4>
CLK_EXP <4>
TPJNC54TPJNC54
TPJNC47TPJNC47
CLK_PCI_FB <18>
R342 90.9R1%0402R342 90.9R1%0402
TPJNC35TPJNC35
TPJNC53TPJNC53
TPJNC40TPJNC40
PCH_GPIO74
PCH_GPIO11
DRAMRST_CNTRL_PCH
SUS_SMBDATA
SUS_SMBCLK
SML0_CLK
SML0_DATA
SML1_CLK
SML1_DATA
SUS_SMBCLK
SUS_SMBDATA
SML1_CLK
SML1_DATA
R74
R74
1MR1%0402
1MR1%0402
VTT
R320 X_33R0402R320 X_33R0402
12
R279 10KR0402R279 10KR0402
R280 10KR0402R280 10KR0402
R281 1KR1%0402R281 1KR1%0402
R283 2.2KR0402R283 2.2KR0402
R282 2.2KR0402R282 2.2KR0402
RN10
RN10
1
3
5
7
8P4R-2.2K0402
8P4R-2.2K0402
+3VRUN
Q21
Q21
D1
D2
D1
D2
S1
G1
S2
G2
NN-2N7002DW-7-F_SOT363-6
NN-2N7002DW-7-F_SOT363-6
+3VRUN
Q22
Q22
S1
G1
S2
G2
NN-2N7002DW-7-F_SOT363-6
NN-2N7002DW-7-F_SOT363-6
C74 C18p50N0402C74 C18p50N0402
X1
X1
25MHZ20p_S
25MHZ20p_S
C72 C18p50N0402C72 C18p50N0402
C433
C433
X_C10p25N0402
X_C10p25N0402
Only PCIECLKRQ[2:1]# on PCH are core well powered. All other PCIECLKRQx# are suspend well powered.
A
B
C
D
+3VSUS
2
4
6
8
PEG_CLKREQ# <24>
R315
R315
X_10KR0402
X_10KR0402
CLK_CARD48 <36>
+3VRUN
246
8
RN13
RN13
8P4R-2.2K0402
8P4R-2.2K0402
135
7
SMB_CLK_DIMM <10,11,12,13>
SMB_DATA_DIMM <10,11,12,13>
SWAP
SMB_CPU_CLK <23,28,45>
SMB_CPU_DATA <23,28,45>
CLK_BUF_EXP#
CLK_BUF_EXP
CLK_BUF_CPYCLKN
CLK_BUF_CPYCLKP
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_SATA#
CLK_BUF_SATA
CLK_BUF_REF14
For Intergrated Clock Generation Mode
Title
Title
Title
PCH_PCIE/SMBUS/CLK
PCH_PCIE/SMBUS/CLK
PCH_PCIE/SMBUS/CLK
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
MS-16F31
MS-16F31
MS-16F31
Date: Sheet of
Date: Sheet of
Date: Sheet of
R374 10KR0402R374 10KR0402
R375 10KR0402R375 10KR0402
R106 10KR0402R106 10KR0402
R107 10KR0402R107 10KR0402
R293 10KR0402R293 10KR0402
R294 10KR0402R294 10KR0402
R359 10KR0402R359 10KR0402
R358 10KR0402R358 10KR0402
R306 10KR0402R306 10KR0402
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
MICRO-STAR INT'L CO.,LTD.
15 61Thursday, December 15, 2011
15 61Thursday, December 15, 2011
E
15 61Thursday, December 15, 2011
10
10
10
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