MSI MS-168x Schematic

5

PRELIMINARY

D D

EXTERNAL CLOCK GENERATOR

4

3

GUAM S1G4 SCHEMATIC DESIGN

DDR III, 1333MT/S

HDT

SCAN

16

16

AMD S1G4 CPU

Channel A

Channel B

2

UNBUFFERED DDR3
NEAR SODIMM

18,19

UNBUFFERED DDR3
FAR SODIMM

18,19

Optional CPU
Temperature sensor

16

1

ICS9LPRS478

DISPLAY PORT

37,38

2,3,4

20

HT Debug
Header

21

14,15,16,17

OUT

HyperTransport

IN

LINK0

16x16

SB-TSI

16

MXM 3.0

x2 PCIE
GPP4&5

MINIPCIE

46

Finger Print
Reader

USB1.1-0

GB ETHERNET PHY
(Optional)

LVDS MUX

33

CRT MUX

PCIE x8

50

49

USB#1USB#2

45

X8 PCIE MUX

MINIPCIE

GPP INTERFACE

USB#0

47

46

48

USB1.1

RGMII

USB 2.0

RS880M

HyperTransport LINK0 CPU I/F
DX10 IGP
LVDS/TVOUT/TMDS
DISPLAY PORT X2
Side Port Memory
1 X16 PCIE I/F
1 X4 PCIE I/F WITH SB
6 X1 PCIE I/F

21,22,23,24,25

PCIE

X4

SB800

USB2.0 (14)+1.1(2)
SATA III (6 PORTS)
4 X1 PCIE GEN2 I/F

INT. CLK GEN.
GB MAC
HW MONITOR
PCI/PCI BDGE
INT. RTC

26,27,28,29

EC
HD AUDIO
LPC I/F
SPI I/F
ACPI 1.1

Side port

I2C I/F

HW MONITOR I/F

SPI I/F

I2C I/F

LVDS CON

eDP CON

C C

IEEE 1394

44

VGA CON

LASSO CON

GPP PCIE INTERFACE

MINI PCIE

B B

SIM card
socket

48

PCIE ETHERNET

MINIPCIE

USB12

49

51

SD Reader

Express Card

44

35

37

36

36

USB3.0
Controller

39

50

USB#3

46 46

Bluetooth

USB1.1-1

45

FRAME BUFFER

DRR3 512MBIT

BOOTSTRAPS
ROM(NB)

HD AUDIO I/F

CIR

45

SATA III I/F

SPI ROM

BOOTSTRAPS
ROM (SB)

24

24

AZALIA CODEC

42,43

Mobile 2.5" HDD eSATAMobile ODD

HW MONITOR

41

28

28

30

Ambient Light Sensor

Headphone & SPDIF
Jack

Digital MIC Array
Header x2

43

42

41

CPU FAN

CPU Tempreture Sensor

VOLTAGE MONITOR

52

MIC In Jack

Speaker Headr x2

43

43

41

BATTERY CHAGER

A A

SYSTEM MAIN POWER

VCCNB&VLDT
Power

CPU CORE/NB POWER

7

1V8 &1V1DUAL

13

POWER

DISCHARGE CIRCUIT

12

5

CPU MEMORY POWER

8

59

1V5 &1V5DUAL
POWER

RESET,FAN
& ENABLES

10

9

LPC

11

SCANNED
MATRIX
KEYBOARD

55

4

PS2
TOUCH PAD

53 53

SMSC1100
EC

3

DEBUG
POSTCARD

52

57

LPC ROM
LPC header

TPM1.2

MICRO-STAR INT'L CO.,LTD

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54

54

MSI

MSI

MSI

2

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Wednesday, January 13, 2010

Date:

Wednesday, January 13, 2010

Date:

Wednesday, January 13, 2010

MS-168x

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

1

Sheet of

Sheet of

Sheet of

152

152

152

0A

0A

0A

5

4

3

2

1

D D

P01 : BLOCK DIAGRAM
P02 : TABLE OF CONTENTS
P03 : POWER DELIVERY CHART
P04 : POWER SEQUENCE CHART
P05 : CLOCK DISTRIBUTION
P06 : MISC TABLES
P07 : BATTERY CHARGER
P08 : CPU CORE PWR
P09 : CPU MEM PWR

C C

P10 : 1V1DUAL / 1V1 /18V /3V3 /5V
P11 : 1V5 / 1V5DUAL
P12 : NBCORE / VLDT
P13 : SYSTEM POWER
P14 : S1G4 HT I/F
P15 : S1G4 DDRIII MEMORY I/F
P16 : S1G4 CTRL / DEBUG
P17 : S1G4 PWR / GND
P18 : DDR3 SODIMMS A/B CHANNLE
P19 : DDR3 SODIMMS DECOUPLING
P20 : EXTERNAL CLOCK GEN
P21 : RS880M HT I/F

B B

P22 : RS880M PCIE I/F
P23 : RS880M SYSTEM
P24 : RS880M SPMEM/STRAPS
P25 : RS880M POWER
P26 : SB8X0 PCIE/PCI/CPU/LPC/CLK
P27 : SB8X0 GPIO/USB/AZ/RGMII
P28 : SB8X0 SATA/IDE/HWM/SPI
P29 : SB8X0 POWER / DECOUPLING
P30 : SB8X0 STRAPS
P31 : PCIE SWITCH

TABLE OF CONTENTS

P32 : MXM PWR / MISC
P33 : MXM 3.0 EDGE
P34 : LVDS / CRT SWITCH
P35 : LVDS CON / BACKLIGHT
P36 : CRT / LASSO CONN
P37 : EDP / DPD
P38 : DPB / DPC
P39 : USB3.0 (1)
P40 : USB3.0 (2)
P41 : SATA CONN / DEBUG
P42 : HD AUDIO CODEC
P43 : HD AUDIO CONN
P44 : 1394 / SD READER
P45 : FP / BT / CIR
P46 : USB2.0 PORTS
P47 : LAN PHY (B50610)
P48 : MINI PCIE SLOT 0, 3
P49 : MINI PCIE SLOT 1, 2
P50 : X4 GPP / PCIE EXPRESS CARD
P51 : LOM (57760)
P52 : KBC - SMSC1100L
P53 : KBCBIOS / KBD /MOUSE
P54 : CONFIG ROM / LPC ROM / TPM
P55 : RESET / FAN / LED / PWRGD
P56 : ACPI CONN
P57 : DEBUG - POST LEDS
P58 : DUAL RAIL ENABLE
P59 : DISCHARGE CIRCUIT
P60 : SB800 A11 PU RES
P61 : CHANGE HISTROY
P62 : POWER ON SEQUENCE CHART

A A

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Wednesday, January 13, 2010

Date:

Wednesday, January 13, 2010

Date:

5

4

3

2

Wednesday, January 13, 2010

MS-168x

BLOCK DIAGRAM

BLOCK DIAGRAM

BLOCK DIAGRAM

1

Sheet of

Sheet of

Sheet of

252

252

252

0A

0A

0A

5

BATTERY

11.1V 62WHr

D D

AC ADAPTOR
15-16V 90W

C C

B B

BATTERY
CHARGER
MAX1535

+VIN

CPU_VDDIO_SUS

+5VDUAL

+3.3VDUAL

+1.1V DUAL

A A

+1.1V

+3.3VDUAL

+1.5V

5

4

CPU core
PWM
MAX17009

CPU core
PWM
MAX8792

DDR3 PWM
LDO VTT
MAX8632

+1V~1.2V SW
+1.1V SW
MAX8775

+1.2V SW
MAX8716-1/2

+1.8V SW
MAX8716-2/2

SW
OZ9956

+5V SW
+3V SW
+5V LDO
+3V LDO
MAX1533

SW
MAX1714

SWITCH

SWITCH

SWITCH

2.5V LDO

SWITCH

1.0V LDO

1.5V LDO

SWITCH

4

CPU_VDD_RUN@38A

CPU_VDDNB_RUN@4A

CPU_VDDIO_SUS@9A
MEM_VTT@1.5A

VLDT (1.1V/1.2V)
+VCC_NB_RUN

+1.1VDUAL@10A

+1.8V@3.3A

VDD_LED_BL_RUN

+3.3VALW
+5VALW

+3.3VDUAL@8A
+5VDUAL@8A

+1.5V@5A

+5V

+3.3V

CPU_VDDA_RUN+3.3V

+1.1V

+1.0V

S3,S4,S5

S0

+1.5V

+1.5VDUAL

3

+5V

VLDT
+1.1V

+1.1V
+1.8V

+1.1V

+3.3V
+1.8V
+1.1V
+3.3V
+1.1V
+3.3V
+3.3VDUAL
+1.1VDUAL
+1.1V
+1.1V
VDDIO_GBE_S/2
+3.3VDUAL
+1.1VDUAL
PHY_VDDIO_DUAL
+3.3VDUAL
+1.1VDUAL
+1.1VDUAL
AZ_VDDIO_DUAL
+1.1VDUAL
+3.3V
+1.1V
+3.3VDUAL
+3.3VDUAL
+3.3VDUAL

MXM_EN

+3.3V
+5V
+VIN

3

VLDT

AOZ1024
PWM

+VCC_NB
+3.3V
+1.8V
+1.5V
+1.5V
+3.3V
+1.8V
+3.3V
+1.8V

CPU_VDDA_RUN

CPU_VDD_RUN

CPU_VDDNB_RUN

BEAD

CPU_VDDIO_SUS

VDDR

BEAD
BEAD

BEAD
BEAD

BEAD
BEAD
BEAD
BEAD
BEAD
BEAD
BEAD
BEAD

AMD SB800

BEAD
BEAD
BEAD
BEAD
BEAD
BEAD

BEAD

BEAD

BEAD
BEAD
BEAD
BEAD
BEAD
BEAD

SW
SW

Sensor
Resistor

AMD S1G4

VCCA 2.5V

VDD CORE

1.375-1.500V 36A
VDDNB CORE

0.9V 4A
VLDT 1.2V TPDA

VDD MEM TPDA
VDDR 1.5A

RS880M

VDDHTTX 1.2V 0.68A
VDDHTRX+HT 1.1V 0.68A

VDDPCIE 1.1V 1.1A
VDDA18 1.8V 0.64A
VDDC 1.0V-1.1V 7.6A
VDDG33 3.3V 0.06A
VDDG18 1.8V 0.005A
VDD18_MEM 1.8V 0.005A
VDD_MEM 1.8V 0.23A
AVDD 3.3V 0.125A
VDDLT18 0.22A
VDDLT33 0A
PLLs 1.8V 0.1A
PLLs 1.1/1.2V 0.23A

VDDIO_33_PCIGP 3.3V 0.020A
VDDIO_18_FC 1.8V 0.050A
VDDAN_11_PCIE 1.1V 1A
VDDPL_33_PCIE 3.3V 0.030A
VDDAN_11_SATA 1.1V 0.8A
VDDPL_33_SATA 3.3V 0.020A
VDDAN_33_USB_S 3.3V 0.2A
VDDAN_11_USB_S 1.2V 0.2A
VDDCR_11 1.1V 0.5A
VDDAN_11_CLK 1.1V 0.4A

VDDRF_GBE_S

VDDIO_33_GBE_S 3.3V
VDDCR_11_GBE_S 1.1V

VDDIO_GBE_S 3.3V
VDDIO_33_S 3.3V
VDDCR_11_S 1.1V
VDDCD_11_USB 1.1V
VDDIO_AZ_S 3.3V OR 1.5V
VDDCR_11_USB_S 1.1V
VDDPL_33_SYS 3.3V SYS PLL
VDDPL_11_SYS 1.1 V SYS PLL
VDDPL_33_USB_S 3.3 V USB PLL
VDDAN_33_S 3.3V HWM
VDDXL_33_S 3.3V

MXM HE 3.0

MXM_VDD_3.3V 1A
MXM_VDD_5V 2.5A
MXM_VDD_MAIN upto 10A

2

CPU_VDDIO_SUS
MEM_VTT

BEAD

+1.5V

BEAD

+3.3V
+1.1V

BEAD

+1.5V

BEAD

+3.3V

BEAD

DDRiII SODIMMX2--SYSTEM

VDD MEM 4A
VTT_MEM 0.5A

CLOCK GEN

1.2V 0.2A

3.3V

1.1V 0.5A

HD CODEC

1.5V CORE 0.3A
3V ANALOG 0.1A

1

AUDIO
OP

GBIT ETHERNET

+3.3VDUAL

BEAD

+3.3VDUAL

+3.3V
+5V

SW
BEAD

+5V
VDD_LED_BL_RUN
+VIN

+5VDUAL

+1.5V
+3.3V
+3.3VDUAL

+1.5V

+3.3VDUAL

+3.3V
+5V

+5V

+3.3V
+1.0V

+3.3V
+1.8V

+VIN
+3.3V

+3.3VDUAL

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Date:

2

Date:

3.3V 0.5A

SMSC1100--EC

3.3V 0.5A

LCD PANEL

3.3V 1.5A
5V 0.5A

BACK LIGHT

+5V
LED_BL
+VDD_MAIN

USB X2 FR

5VDual

EXPRESS CARD

1.5V (S0, S1) 0.7A

3.3V (S0, S1) 1.3A

3.3V (S3, S5) 0.3A

MINI PCIE SLOT0,1,2

1.5V (S0, S1) 0.5A
each

3.3V (S3, S5) 2.75A
each

SATA HD0,1

3.3V (S0, S1) TBD

5V (S3, S5) TBD

SATA ODD

5V (S0, S1) TBD

uPD720200

3.3V (S0, S1) TBD

1.0V (S0, S1) TBD

OZ8888

3.3V (S0, S1) 0.5A

1.8V (S0, S1) 0.5A

Desktop x1 PCIE

+12V
+3.3V
+3.3Vaux

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MS-168x

POWER DELIVERT

POWER DELIVERT

Wednesday, January 13, 2010

Wednesday, January 13, 2010

Wednesday, January 13, 2010

POWER DELIVERT

1

Sheet of

Sheet of

Sheet of

0A

0A

352

352

352

0A

5

4

3

2

1

Power on Sequence required:

SB800:
1, +3.3VDUAL ramp before +1.1VDUAL
2, +3.3V ramp before +1.8v
3, +1.8V ramp before +1.1v
4, +3.3v ramp before +1.1v
5, +3.3VALW_R ramping down time > 300us
6, 50uS <= All power rails except +3.3VALW_R <= 40mS
7, 100uS <= +3.3VALW_R <= 40mS

RS880:
1, 0 <(+3.3V) - (+1.8v) < 2.1

D D

2, +1.8V ramp before +1.1v

3. +1.1V ramp before VCC_NB

SB OUTPUT

SB INPUT

C C

CPU MEM CTL &
DDR3 SODIMM PWRS

B B

CPU_THM/SB/SB_SCL1/2
SB_KB/SPI/LPC ROM PWRS

KBC is ready

KBC is powered by
A_VBAT & +3.3VALW

A A

CPU_LDT_RST#
(SB TO CPU)

CPU_PWROK
(SB TO CPU)

CPU_CLKP/N running

NB_PWRGD

NB_PWRGD_IN

+1.2V_PWRGD

VCC_NB

VLDT

+1.1V

VRM_PWRGD

CPU_VDDR

CPU_VDD_RUN

CPU_VDDNB_RUN

VDDA_PWRGD

+2.5V_LDO

(CPU_VDDA_2.5_RUN)

+1.5V

1V8_PWRGD

GROUP A GROUP B

V3V5DUAL_PWRGD
1V1DUAL_PWRGD
SYSTEM_DUAL_PG_DELAY

+5V/+3.3V

RUN_EN_HIGH
RUN_EN_LOW
VDD_BOOST_LOW

SLP_S3#

VDRAM_PWRGD

MEM_VTT
MEM_VREF

CPU_VDDIO_SUS

SLP_S5#

PWR_BTN#_EC

RSMRST#

DUAL RAILS

VDD_DUAL_EN

VDD_DUAL_EN_EC

PWR_BTN#_HW
PWR_BTN#_SB

AC_OK
(ACIN detect)

+5VALW/+3.3VALW

LDO:5.4V
(from DCIN)

+VIN/+12V_HD

A_VBAT

+1.8V

1)+1.5V SWITCH TO +1.5VDUAL 2)LASSO_PWRON 3)LPCPD# for TPM 4) TO SB&KBCSB_PWRGD

VTT only will be shut down in S3 mode, and VTT for DDR3 SODIMM only.

Power button pressed

Power button from EC to SB

20mS
delay

+5VDUAL/+3.3VDUAL/+1.5VDUAL/+1.1VDUAL
When IMC, always on at all time( always PWR)

Battery inserted/AC IN

>1 mS Req.

RC=~22ms

RC=~4.7ms

VRM_PWRGD AND 1V8_PWRGD

RC=0

RC=0

RC=0

RC=0

AC not present scenario = LOW AC present= high

Req.

>1 mS

>1 mS Req.

running

VCC_NB should not ramp before 1.1v

VCC_NB(all NB power) valid before NB_PWRGD.

SLP_S3#

1V1DUAL_PWRGD
1V5_PWRGD/DNI

SYS_RST#

+1.2V_PWRGD

KBC_GPIO77/DNI

to S3

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Wednesday, January 13, 2010

Wednesday, January 13, 2010

5

4

3

2

Wednesday, January 13, 2010

MS-168x

POWER SEQUENCE

POWER SEQUENCE

POWER SEQUENCE

1

Sheet ofDate:

452

Sheet ofDate:

452

Sheet ofDate:

452

0A

0A

0A

5

4

3

2

1

EXTERNAL CLOCK MODE

SPM_CLK

SIDE PORT MEMORY CHIP

NB_OSC

100MHZ

14.318MHZ

xxxMHZ

GFX_CLKP/N

100MHZ

PCIE_DT_CLKP/N

100MHZ

PCIE_1394_CLKP/N

100MHZ

PCIE_PE0_CLKP/N

100MHZ

PCIE_PE1_CLKP/N

100MHZ

PCIE_EXPCARD_CLKP/N

100MHZ

PCIE_PE2_CLKP/N

100MHZ

PCIE_LAN_CLKP/N

100MHZ

PCIE_USB30_CLKP/N

100MHZ

PCIE_PE3_CLKP/N

100MHZ

CLK_REQ in CLK GEN

PCIE GFX SLOT (RS880M, 16 LANES)

EXT_MXM_CLKREQ#

PCIE GPP SLOT (RS880M, 2 LANES)

EXT_PCIE_DT_CLKREQ#

PCIE GPP I/F (RS880M, 1 LANE)

EXT_PCIE_1394_CLKREQ#

MINIPCIE SLOT (RS880M, 1 LANE)

EXT_PCIE_PE0_CLKREQ#

MINIPCIE SLOT (SB800, 1 LANE)

EXT_PCIE_PE1_CLKREQ#

PCIE NEW CARD SLOT (SB800, 1 LANE)

EXT_PCIE_EXPCARD_CLKREQ#

MINIPCIE SLOT (SB800, 1 LANE)

EXT_PCIE_PE2_CLKREQ#

PCIE GPP I/F (RS880M, 1 LANE)

EXT_PCIE_LAN_CLKREQ#

PCIE GPP I/F (RS880M, 1 LANE)

EXT_PCIE_USB30_CLKREQ#

MINIPCIE SLOT (SB800, 1 LANE)

EXT_PCIE_PE3_CLKREQ#

PORT3:WLAN

MXM SLOT

PCIe x4 SLOT

1394:OZ888GS0L3N

PORT0:WLAN

PORT1:WWAN

EXPRESS CARD

PORT2:WUSB

BCM57760A0KMLG

USB3.0:uPD720200F

AMD NORTHBRIDGE

RS880M

A-LINK

GPP_REFCLK

D D

100MHZ

100MHZ

100MHZ

GPP REF_CLK

A_SODIMM

MEM_MB_CLK1_P/N

MEM_MB_CLK2_P/N

MEM_MA_CLK1_P/N

MEM_MA_CLK2_P/N

AMD

SIG4 CPU

B_SODIMM

CPU_CLKP/N
200MHZ

NBLINK_RCLKP/N

EXTERNAL

CLOCK GENERATOR

14.31818MHz

C C

KBC_OSC

SB_OSC

DNI

HT_REFCLKP/N

NB_GFX_REFCLKP/N

NB CLOCK INPUT TABLE

NB CLOCKS

HT_REFCLKP
HT_REFCLKN
REFCLK_P
REFCLK_N

GFX_REFCLK
GPP_REFCLK

GPPSB_REFCLK 100M DIFF

* RS880M can be used as clock buffer to output two PCIE referecence clocks
By deault, chip will configured as input mode, BIOS can program it to output mode.

RS880M

100M DIFF
100M DIFF
14M SE (1.1V)
vref

100M DIFF(IN/OUT)*

NC or 100M DIFF OUTPUT

25M Hz

PCICLK0

25M_X1

25M_X2

PCICLK1

PCICLK2
PCICLK3
PCICLK4

LPCCLK0

LPCCLK1

RTCCLK

AZ_BITCLK

SPI_CLK

14M_25M_48M_OSC

GBE_RXCLK
GBE_TXCLK

FOR SATA

25M Hz

DNI

SBSRC_CLKP/N

100MHZ

CLK_48M_USB

48MHZ

AMD SB800

EXT CLK MODE

SATA_X1

SATA_X2

PCIE_RCLKP/N

USBCLK

PCI_CLK0

33MHZ

SMSC_CLK

33MHZ

PCI_CLK2
PCI_CLK3
PCI_CLK4

33MHZ

LPC_CLK0

33MHZ

LPC_CLK1

33MHZ

AZ_BIT_CLK

24MHZ

SPI_CLK

xxHZ

SB_25MHz_PHY
GBE_TX/RXCLK

IMC_IM_CLK

SPCI MICTOR
PSOT CODE LED

KBC1100L

STRAPS SETTING,
UNUSED CLOCKS

LPC BIOS & HEADER
LPC TPM

HD AUDIO

SPI ROM & HEADER

GBE PHY

MOUSE

TOUCH PAD

IM_CLK

32.768K Hz

25M Hz

KBC1100L

32.768K Hz

INTERNAL CLOCK MODE

MEM_MA_CLK1_P/N
MEM_MA_CLK2_P/N

A_SODIMM

MEM_MB_CLK1_P/N
MEM_MB_CLK2_P/N

B_SODIMM

B B

SPCI MICTOR

OSCILLATOR

14.318MHZ

PSOT CODE LED
KBC1100L

STRAPS
SETTING,
UNUSED
CLOCKS

LPC BIOS & HEADER

LPC TPM

32.768K Hz

SPI ROM & HEADER

25M Hz

HD AUDIO

GBE PHY

A A

KBC1100L

IM_CLK

MOUSE
TOUCH PAD

33MHZ

PCI_CLK0

SMSC_CLK

33MHZ

PCI_CLK2

33MHZ
PCI_CLK3

33MHZ
PCI_CLK4
33MHZ
LPC_CLK0
33MHZ
LPC_CLK1
33MHZ

SPI_CLK

xxHZ

AZ_BIT_CLK

24MHZ

SB_25MHz_PHY

25MHZ

GBE_RXCLK
GBE_TXCLK

IMC_IM_CLK

AMD

SIG4 CPU

CPU_CLKP/N

PCICLK0

PCICLK1

PCICLK2

PCICLK3

PCICLK4

LPCCLK0

LPCCLK1
RTCCLK
SPI_CLK

AZ_BITCLK

14M_25M_48M_OSC
GBE_RXCLK

GBE_TXCLK

PS2M_CLK

FOR MASTER FOR RTC

200MHZ

CPU_HT_CLKP/N

25M Hz

5

4

AMD NORTHBRIDGE

RS880M

REFCLKP/N

A-LINK

100MHZ

100MHZ

100MHZ

NB_REFCLK_P/N

PCIE_RCLKP/N

NB_DISP_CLKP/N

NB_GFX_REFCLKP/N

GPP_CLK6P/N

SB_NBLINK_RCLKP/N

AMD SB800

CLOCK GENERATOR

32.768K Hz

GPP_REFCLK

HT_REFCLKP/N

NB_HT_CLKP/N

FOR SATA

25M Hz

3

100MHZ

DNI

SPM_CLK

xxxMHZ

SLT_GFX_CLKP/N

GPP_CLK5P/N

GPP_CLK8P/N

GPP_CLK1P/N

GPP_CLK4P/N

GPP_CLK0P/N

GPP_CLK2P/N

GPP_CLK3P/N

GPP_CLK7P/N

GPP_CLK6P/N

SIDE PORT MEMORY CHIP

GFX_CLKP/N

100MHZ

PCIE_DT_CLKP/N

100MHZ

PCIE_1394_CLKP/N

100MHZ

PCIE_PE0_CLKP/N

100MHZ

PCIE_PE1_CLKP/N

100MHZ

PCIE_EXPCARD_CLKP/N

100MHZ

PCIE_PE2_CLKP/N

100MHZ

PCIE_LAN_CLKP/N

100MHZ

PCIE_USB30_CLKP/N

100MHZ

PCIE_PE3_CLKP/N

100MHZ

PCIE GFX SLOT (RS880M, 16 LANES)

CLK_REQG# in SB

PCIE GPP SLOT (RS880M, 2 LANES)

CLK_REQ5 in SB

PCIE GPP I/F (RS880M, 1 LANE)

CLK_REQ8 in SB

MINIPCIE SLOT (RS880M, 1 LANE)

CLK_REQ1 in SB

MINIPCIE SLOT (SB800, 1 LANE)

CLK_REQ4 in SB

PCIE NEW CARD SLOT (SB800,1 LANE)

CLK_REQ0 in SB

MINIPCIE SLOT (SB800, 1 LANE)

CLK_REQ2 in SB

PCIE GPP I/F (RS880M, 1 LANE)

CLK_REQ3 in SB

PCIE GPP I/F (RS880M, 1 LANE)

CLK_REQ7 in SB

MINIPCIE SLOT (SB800, 1 LANE)

CLK_REQ6 in SB

2

MXM SLOT

PCIe x4 SLOT

1394:OZ888GS0L3N

PORT0:WLAN

PORT1:WWAN

EXPRESS CARD

PORT2:WUSB

BCM57760A0KMLG

USB3.0:uPD720200F

PORT3:WLAN

MSI

MSI

MSI

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev
Custom

Custom

Custom
Date:

Date:

Date:

MS-168x

CLOCK BLOCK

CLOCK BLOCK

CLOCK BLOCK

Wednesday, January 13, 2010

Wednesday, January 13, 2010

Wednesday, January 13, 2010

552

552

552

Sheet of

Sheet of

Sheet of

1

0A

0A

0A

5

Thermal Systems

(Emergency Shutdown, Throttling, Fan Control)

4

3

2

1

translate1.5V TSI 3.3V TSI

THERMTRIP_L

D D

MEMHOT_L

ALERT_L

THERMDC
THERMDA

SID
SIC

AMD

translate

translate

translate

VRM Power

VRM_HOT#

S1G4

PROCHOT_L

translate

ADM

C C

SO-DIMM
EVENT

MXM

THERM#

SDA
SCL

1032

Thermal disaster prevention is implemented by PROCHOT_L and THERMTRIP_L with hardware

non-system dependant functions. Fan speed control will only be implemented

by SB TSI software based implementation

B B

Global

System

State

A A

G2

G2/G3

Power State / Voltage Rail Activity Summary

Processor

Sleep
State

G0

G0

G0

G0

G0

G0

G1

G1

G2

S5 LOW

G3

Power

State

S0

S0

S0

S0

S0

S0

S1

S3

S4

S5

C0

C0

C1

C2

C3

c4

OFF

OFF

OFF

OFF

OFF

OFF

5

Running

Running

Sleeping

Description

P-state transitions

Powered on suspend

Suspend to diskON

Soft-off

Battery IN

Mechanical off

KBC

SMSC

NON-POP

OVERRIDE#translate

PWM

TACH

4-PIN CPU FAN

NON-POP

under OS control

Halt

Stop grant,

caches snoopable

TBD

TBD

Suspend to RAM

G7

THERMTRIP#

SDA3

(S5-S0)

SCL3

T7

TALERT#

(S0)

Y9

FANOUT2

AMD

W18

SDA0AA18

SB800

SCL0

B6

TEMPIN0

C6

TEMP_COMM

F24

PROCHOT#

M8

FANOUT0

P5

FANIN0
TEMPIN3

J4

GEVENT4#

SCL2

SDA2

Place under DDR

TEMP
SENSOR
(Q600)

ADM
1032

RTC ALW DUAL

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

ON

4

TEMPIN1

TEMP_COMM

TEMPIN2

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

ON

OFF

A6
C6

THERMDC
THERMDA

SUS RUN

ON

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

OFF

OFF

NON-POP

AMD

RS880

ON

ON

ON

ON

ON

ON

ON

OFF

OFF

OFF

OFF

OFF

SMBus Block Diagram

(S5-S0)

DUAL_SMB1

BCM57760

LAN

U1300

mini

PCI Exp x1

J3700

mini

PCI Exp x1

J3703

mini

PCI Exp x1

J3711

mini

PCI Exp x1

J3712

GPP Slot

J3701

Exp Card

J2500

Group Name Description

INT: Stuff when use internal clock generator
EXT: Stuff when use external clock generator
DNI: DO NOT INSTALL
KBC: Stuff when use external KBC
IMC: Stuff when use internal EC
A11:Resistors marked with "A11" is only for SB800A11 ONLY.

3

DDR 2

SO-DIMM

J400

DDR 2

SO-DIMM

J401

CLK. Gen.

ICS9LPRS470

U800

MXM
J3600

CONFIG ROM

U1001

LCP Debug Header

J1000

ADM1032

Diode Reader

U204

POP

NOPOP

NOPOP

SDATA1
SCLK1

SDATA0
SCLK0
SDATA2
SCLK2

NOPOP

CPU Thermal
Sensor
ADM1032

AMD

SB800

(master)

SDA1

(S5-S0)

SCL1

ASF Only

SDA0

(S0)

SCL0
SDA2
SCL2

(S5-S0)

(S5-S0)

1.8V

SDA3
SCL3

AMD

S1G4

MAX17009

(S3-S0)

U2700

SVC
SVD

J106

translate

SDA
SCL

POP

100R

BAT_DAT
BAT_CLK

MSI

MSI

MSI

POP

3.3V SB-TSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Wednesday, January 13, 2010

Date:

Wednesday, January 13, 2010

Date:

Wednesday, January 13, 2010

SIC
SID

TL2560
light sensor
U3201

smart
battery

J2700

MAX1535
battery charger

2

SVC

CPU Core PWR PWM

SVD

U2800

SMSC

I2C1A_DAT
I2C1A_CLK

I2C1B_DAT
I2C1B_CLK

U103
(master)

(S5-S0)

(S5-S0)

(S5-S0)

KBC1100L

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MS-168x

SMBUS BLOCK

SMBUS BLOCK

SMBUS BLOCK

1

Sheet of

Sheet of

Sheet of

652

652

652

0A

0A

0A

5

4

3

2

1

D D

U22A

+VLDT

HT_NB_CPU_CAD_H014
HT_NB_CPU_CAD_L014
HT_NB_CPU_CAD_H114
HT_NB_CPU_CAD_L114
HT_NB_CPU_CAD_H214
HT_NB_CPU_CAD_L214
HT_NB_CPU_CAD_H314
HT_NB_CPU_CAD_L314
HT_NB_CPU_CAD_H414
HT_NB_CPU_CAD_L414

C C

B B

HT_NB_CPU_CAD_H514
HT_NB_CPU_CAD_L514
HT_NB_CPU_CAD_H614
HT_NB_CPU_CAD_L614
HT_NB_CPU_CAD_H714
HT_NB_CPU_CAD_L714
HT_NB_CPU_CAD_H814
HT_NB_CPU_CAD_L814
HT_NB_CPU_CAD_H914
HT_NB_CPU_CAD_L914
HT_NB_CPU_CAD_H1014
HT_NB_CPU_CAD_L1014
HT_NB_CPU_CAD_H1114
HT_NB_CPU_CAD_L1114
HT_NB_CPU_CAD_H1214
HT_NB_CPU_CAD_L1214
HT_NB_CPU_CAD_H1314
HT_NB_CPU_CAD_L1314
HT_NB_CPU_CAD_H1414
HT_NB_CPU_CAD_L1414
HT_NB_CPU_CAD_H1514
HT_NB_CPU_CAD_L1514

HT_NB_CPU_CLK_H014
HT_NB_CPU_CLK_L014
HT_NB_CPU_CLK_H114
HT_NB_CPU_CLK_L114

HT_NB_CPU_CTL_H014
HT_NB_CPU_CTL_L014
HT_NB_CPU_CTL_H114
HT_NB_CPU_CTL_L114

U22A

D1

VLDT_A0

D2

VLDT_A1

D3

VLDT_A2

D4

VLDT_A3

E3

L0_CADIN_H0

E2

L0_CADIN_L0

E1

L0_CADIN_H1

F1

L0_CADIN_L1

G3

L0_CADIN_H2

G2

L0_CADIN_L2

G1

L0_CADIN_H3

H1

L0_CADIN_L3

J1

L0_CADIN_H4

K1

L0_CADIN_L4

L3

L0_CADIN_H5

L2

L0_CADIN_L5

L1

L0_CADIN_H6

M1

L0_CADIN_L6

N3

L0_CADIN_H7

N2

L0_CADIN_L7

E5

L0_CADIN_H8

F5

L0_CADIN_L8

F3

L0_CADIN_H9

F4

L0_CADIN_L9

G5

L0_CADIN_H10

H5

L0_CADIN_L10

H3

L0_CADIN_H11

H4

L0_CADIN_L11

K3

L0_CADIN_H12

K4

L0_CADIN_L12

L5

L0_CADIN_H13

M5

L0_CADIN_L13

M3

L0_CADIN_H14

M4

L0_CADIN_L14

N5

L0_CADIN_H15

P5

L0_CADIN_L15

J3

L0_CLKIN_H0

J2

L0_CLKIN_L0

J5

L0_CLKIN_H1

K5

L0_CLKIN_L1

N1

L0_CTLIN_H0

P1

L0_CTLIN_L0

P3

L0_CTLIN_H1

P4

L0_CTLIN_L1

SOCKET_638_PIN

SOCKET_638_PIN

HT LINK

HT LINK

VLDT_B0
VLDT_B1
VLDT_B2
VLDT_B3

L0_CADOUT_H0

L0_CADOUT_L0

L0_CADOUT_H1

L0_CADOUT_L1

L0_CADOUT_H2

L0_CADOUT_L2

L0_CADOUT_H3

L0_CADOUT_L3

L0_CADOUT_H4

L0_CADOUT_L4

L0_CADOUT_H5

L0_CADOUT_L5

L0_CADOUT_H6

L0_CADOUT_L6

L0_CADOUT_H7

L0_CADOUT_L7

L0_CADOUT_H8

L0_CADOUT_L8

L0_CADOUT_H9

L0_CADOUT_L9

L0_CADOUT_H10

L0_CADOUT_L10

L0_CADOUT_H11

L0_CADOUT_L11

L0_CADOUT_H12

L0_CADOUT_L12

L0_CADOUT_H13

L0_CADOUT_L13

L0_CADOUT_H14

L0_CADOUT_L14

L0_CADOUT_H15

L0_CADOUT_L15

L0_CLKOUT_H0
L0_CLKOUT_L0
L0_CLKOUT_H1
L0_CLKOUT_L1

L0_CTLOUT_H0

L0_CTLOUT_L0

L0_CTLOUT_H1

L0_CTLOUT_L1

AE2
AE3
AE4
AE5

AD1
AC1
AC2
AC3
AB1
AA1
AA2
AA3
W2
W3
V1
U1
U2
U3
T1
R1
AD4
AD3
AD5
AC5
AB4
AB3
AB5
AA5
Y5
W5
V4
V3
V5
U5
T4
T3

Y1
W1
Y4
Y3

R2
R3
T5
R5

+VLDT

HT_CPU_NB_CAD_H0 14
HT_CPU_NB_CAD_L0 14
HT_CPU_NB_CAD_H1 14
HT_CPU_NB_CAD_L1 14
HT_CPU_NB_CAD_H2 14
HT_CPU_NB_CAD_L2 14
HT_CPU_NB_CAD_H3 14
HT_CPU_NB_CAD_L3 14
HT_CPU_NB_CAD_H4 14
HT_CPU_NB_CAD_L4 14
HT_CPU_NB_CAD_H5 14
HT_CPU_NB_CAD_L5 14
HT_CPU_NB_CAD_H6 14
HT_CPU_NB_CAD_L6 14
HT_CPU_NB_CAD_H7 14
HT_CPU_NB_CAD_L7 14
HT_CPU_NB_CAD_H8 14
HT_CPU_NB_CAD_L8 14
HT_CPU_NB_CAD_H9 14

HT_CPU_NB_CAD_L9 14
HT_CPU_NB_CAD_H10 14
HT_CPU_NB_CAD_L10 14
HT_CPU_NB_CAD_H11 14
HT_CPU_NB_CAD_L11 14
HT_CPU_NB_CAD_H12 14
HT_CPU_NB_CAD_L12 14
HT_CPU_NB_CAD_H13 14
HT_CPU_NB_CAD_L13 14
HT_CPU_NB_CAD_H14 14
HT_CPU_NB_CAD_L14 14
HT_CPU_NB_CAD_H15 14
HT_CPU_NB_CAD_L15 14

HT_CPU_NB_CLK_H0 14
HT_CPU_NB_CLK_L0 14
HT_CPU_NB_CLK_H1 14
HT_CPU_NB_CLK_L1 14

HT_CPU_NB_CTL_H0 14
HT_CPU_NB_CTL_L0 14
HT_CPU_NB_CTL_H1 14
HT_CPU_NB_CTL_L1 14

+VLDT

[DG] VLDT total CAP >30uF

*

C379

C379

4.7uF

4.7uF

C153

C153

4.7uF

4.7uF

C159

C159
22uF

22uF

C381

C381

0.22uF

0.22uF

C158

C158

0.22uF

0.22uF

C380

C380
180pF

180pF

Place close to socket

* If VLDT is connected only on one side,
one 4.7uF cap should be added to
the island side

[ChckList] Can change 22u*1/4.7u*2 to 10u*3

E26

T26

P26

W26

L26

R26

U26

K26

M26C26

N26

V26

T25

M25

W25

P25

K25

L25

U25

R25

V25

N25

T24

M24

L24

U24

P24

W24

N24

R24

V24

K24

M23

T23

R23

V23P23

L23

U23

W23

K23

N23

M22

W22

U22

V22

K22

L22

P22

N22

T22

R22

M21

W21

U21

V21

K21

P21

T21

N21

L21

R21

L20

T20

R20

N20

U20

M20

P20

V20

K20

L19

U19N19

P19

V19J19

R19

K19

M19

T18

P18

M18

V18

U18

L18

W18

N18

K18

R18

V17

P17

T17

M17

U17

W17

K17

L17

N17

R17

P16

T16

R16

L16

N16

K16

M16

W16

V16

U16

L15

W15

K15

V15

T15

U15

T14

L14

U14

W14

K14

V14

T13

L13

U13

W13

V13

K13

T12

W12

V12

U12

K12

L12

W11

P11

R11

T11

L11 AE11

K11

U11

V11

M11

N11

V10

R10

T10 AE10

L10

W10

U10

N10

M10

P10 AA10

K10

R9

P9

V9

U9W8W9

L9

T9

M9

N9

K9

K8

R8

U8N8

M8

L8

T8

V8

P8

R7

V7R6AA7

T7

W7

L7

N7

U7

M7

K7

P7

L6

T6

W6

N6

K6

M6

V6

P6

U6

L5

N5K3F5

T5

W5

V5

K5

M5

P5

R5

U5

W4

K4

T4

R4

P4G4

N4

V4

M4

U4

L4

N3

L3

V3D3

R3

P3

T3

M3

U3

N2

L2

U2

R2 V2

T2

P2

K2

W2

M2

U1

R1

M1

T1

V1

L1

P1

K1

W1

N1

BGA638_50_26SQ_S1G3_OEM

Y26

AD26

AB26

AA26

AC26

AE25

AB25

AD25

AA25

Y25

AC25

AA24

AB24

AD24

Y24

AC24

AE24

AF24

AF23

AD23

AA23

Y23

AB23

AC23

AE23

AB22

AD22

AA22

AC22

AE22

Y22

AF22

AB21

AF21

AA21

AC21

AD21

AE21

Y21

AF20

AC20

Y20

AA20

AE20

AD20

AB20

AF19T19

AC19

AB19

AE19

Y19

AD19

AA19

AA18

AC18

AB18

AE18

Y18

AF18

AD18

AE17

AB17

AF17

AA17

AD17

AC17

Y17

Y16

AB16

AA16

AF16

AD16

AE16

AC16

AF15

AA15

AB15J15

Y15

AD15

AE15H15

AC15

AD14

AF14

AB14

Y14

AE14

AC14

AA14

AB13

Y13

AD13

AA13

AF13

AE13

AC13

AC12

AB12

Y12

AA12

AD12

AF12

AE12

Y11

AC11

AA11

AF11

AD10

AB10

AC10

Y10

AF10

Y9

AB9

AE9

AC9

AA9

AD9

AF9

AE8

AA8

AC8

AD8

AF8

AB8

AB7

AD7

AE7

AC7

AF7

Y6

AD6

AB6

AF6

AE6

AC6

AA6

AB5

AF5

AE5

AC5

AA5

Y5

AD5

Y4

AB4

AF4

AA4

AE4

AD4

AC4

AB3

AC3

AA3

Y3

AE3

AD3

Y2

AC2

AD2

AB2

AE2

AA2

AD1

AA1

Y1

AC1

AB1

J26

G26

D26

F26

H26

J25

C25

G25

B25

F25

D25

H25

E25

J24

D24

B24

F24

C24

H24

E24

A24

G24

B23

D23

G23

C23

J23

H23

A23

F23

E23

G22

B22

D22

H22

A22

C22

E22

J22

F22

G21

B21

H21

J21

F21

A21

D21

C21

E21

H20

D20

B20

A20

F20

E20

C20

J20

B19

A19

E19

F19

H19

D19

C19

C18

B18

A18

F18

D18

G18

E18

J18

H18

F17

A17

E17

H17

J17

G17

D17

B17

C17

E16

B16B3H16

F16

A16

J16

G16

D16

C16

G15

B15

F15

A15

E15

C15

D15

B14

C14

G14

A14

J14

F14

D14

E14

H14

C13

B13

E13

J13

A13

H13

F13

G13

D13

B12

F12

C12

A12

H12

G12

E12

D12

J12

A11

B11 AB11

F11

C11

H11

E11

D11

G11 AD11

J11

A10

E10

B10

J10

C10

F10

D10

G10

H10

E9

A9

H9

F9

G9

B9

C9

D9

J9

E8

B8

H8

A8

C8

F8

D8

J8

J7

E7

D7

B7

C7

A7

H7

F7

E6

F6

J6

G6

A6

C6

H6

D6

B6

E5

J5

H5

A5

G5

B5

D5

C5

J4

B4

F4

E4

H4

A4

D4

C4

J3 W3

F3

A3

E3

H3

C3

G3

F2

D2

H2

J2

C2

E2

G2

D1

F1

E1

C1

H1

J1

G1

A1

C156

C156
180pF

180pF

[CheckList] If the I/O device does not support the CTLIN1 pair, pull up 51ohm

A A

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

B

B

B

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

5

4

3

2

Friday, February 05, 2010

MS-168x

SIG4 HT I/F

SIG4 HT I/F

SIG4 HT I/F

Sheet of

Sheet of

Sheet of

1

0A

0A

0A

752

752

752

A

B

C

D

E

Processor Memory Interface

U22C

U22C

MEM:DATA

4 4

U22B

PLACE THEM CLOSE TO
CPU WITHIN 1"

CPU_VDDIO_SUS

R238 0RR238 0R

C391

C391
10uF

10uF

Updated on Rev2.0

[Fuqun] If remove R/C?

3 3

2 2

R235 39.2RR235 39.2R
R237 39.2RR237 39.2R

MEM_MA_RST#11
MEM_MA0_ODT011

MEM_MA0_ODT111

MEM_MA0_CS#011
MEM_MA0_CS#111

MEM_MA_CKE011
MEM_MA_CKE111

MEM_MA_CLK1_P11

MEM_MA_CLK1_N11

MEM_MA_CLK2_P11

MEM_MA_CLK2_N11

MEM_MA_ADD[0..15]11

MEM_MA_BANK011
MEM_MA_BANK111
MEM_MA_BANK211

MEM_MA_RAS#11
MEM_MA_CAS#11
MEM_MA_WE#11

TP51TP51
TP53TP53

TP46TP46
TP47TP47
TP48TP48
TP45TP45

TP54TP54
TP52TP52

MEM_MA1_ODT0
MEM_MA1_ODT1

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

M_ZP
M_ZN

CPU_VDDIO_SUS

AD10

AE10

AA16

AF10

D10
C10
B10

H16
T19

V22
U21
V19

T20
U19
U20
V20

N19
N20
E16
F16
Y16

P19
P20

N21
M20
N22
M19
M22
L20
M24
L21
L19
K22
R21
L22
K20
V24
K24
K19

R20
R23

R19
T22
T24

VDDR1
VDDR2
VDDR3
VDDR4

MEMZP
MEMZN

MA_RESET_L
MA0_ODT0

MA0_ODT1
MA1_ODT0
MA1_ODT1

MA0_CS_L0
MA0_CS_L1
MA1_CS_L0
MA1_CS_L1

J22

MA_CKE0

J20

MA_CKE1
MA_CLK_H5

MA_CLK_L5
MA_CLK_H1
MA_CLK_L1
MA_CLK_H7
MA_CLK_L7
MA_CLK_H4
MA_CLK_L4

MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15

MA_BANK0
MA_BANK1

J21

MA_BANK2
MA_RAS_L

MA_CAS_L
MA_WE_L

SOCKET_638_PIN

SOCKET_638_PIN

R70

R70

1.00K

1.00K

R69

R69

1.00K

1.00K

U22B

MEM:CMD/CTRL/CLK

MEM:CMD/CTRL/CLK

VDDR_SENSE

MB_RESET_L

MB0_ODT0
MB0_ODT1
MB1_ODT0

MB0_CS_L0
MB0_CS_L1
MB1_CS_L0

MB_CLK_H5
MB_CLK_L5
MB_CLK_H1
MB_CLK_L1
MB_CLK_H7
MB_CLK_L7
MB_CLK_H4
MB_CLK_L4

MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15

MB_BANK0
MB_BANK1
MB_BANK2

MB_RAS_L
MB_CAS_L

CPU_M_VREF_SUS

C205

C205

C199

C199

1nF

1nF

10nF

10nF

VDDR5
VDDR6
VDDR7
VDDR8
VDDR9

MEMVREF

MB_CKE0
MB_CKE1

MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9

MB_WE_L

PLACE CLOSE TO CPU

W10
AC10
AB10
AA10
A10

Y10
W17
B18
W26

W23
Y26

V26
W25
U22

J25
H26

P22
R22
A17
A18
AF18
AF17
R26
R25

P24
N24
P26
N23
N26
L23
N25
L24
M26
K26
T26
L26
L25
W24
J23
J24

R24
U26
J26

U25
U24
U23

sensing point for
op-amp feedback
routed near CPU

[Fuqun] VDDR--1.05V

CPU_VDDRCPU_VDDR

[CheckList] VDDR_SENSE NC if not use

MEM_MB1_ODT0

MEM_MB1_CS1

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

TP44TP44

MEM_MB_RST# 11
MEM_MB0_ODT0 11

MEM_MB0_ODT1 11
TP56TP56
MEM_MB0_CS#0 11

MEM_MB0_CS#1 11
TP55TP55

MEM_MB_CKE0 11
MEM_MB_CKE1 11

MEM_MB_CLK1_P 11
MEM_MB_CLK1_N 11

TP49TP49
TP50TP50
TP76TP76
TP75TP75

MEM_MB_CLK2_P 11
MEM_MB_CLK2_N 11

MEM_MB_ADD[0..15] 11

MEM_MB_BANK0 11
MEM_MB_BANK1 11
MEM_MB_BANK2 11

MEM_MB_RAS# 11
MEM_MB_CAS# 11
MEM_MB_WE# 11

CPU_M_VREF_SUS

MEM_MB_DATA[0..63]11

MEM_MB_DM[0..7]11

MEM_MB_DQS0_P11
MEM_MB_DQS0_N11
MEM_MB_DQS1_P11
MEM_MB_DQS1_N11
MEM_MB_DQS2_P11
MEM_MB_DQS2_N11
MEM_MB_DQS3_P11
MEM_MB_DQS3_N11
MEM_MB_DQS4_P11
MEM_MB_DQS4_N11
MEM_MB_DQS5_P11
MEM_MB_DQS5_N11
MEM_MB_DQS6_P11
MEM_MB_DQS6_N11
MEM_MB_DQS7_P11
MEM_MB_DQS7_N11

To reverse SODIMM socket

MEM_MB_DATA0
MEM_MB_DATA1
MEM_MB_DATA2
MEM_MB_DATA3
MEM_MB_DATA4
MEM_MB_DATA5
MEM_MB_DATA6
MEM_MB_DATA7
MEM_MB_DATA8
MEM_MB_DATA9
MEM_MB_DATA10
MEM_MB_DATA11
MEM_MB_DATA12
MEM_MB_DATA13
MEM_MB_DATA14
MEM_MB_DATA15
MEM_MB_DATA16
MEM_MB_DATA17
MEM_MB_DATA18
MEM_MB_DATA19
MEM_MB_DATA20
MEM_MB_DATA21
MEM_MB_DATA22
MEM_MB_DATA23
MEM_MB_DATA24
MEM_MB_DATA25
MEM_MB_DATA26
MEM_MB_DATA27
MEM_MB_DATA28
MEM_MB_DATA29
MEM_MB_DATA30
MEM_MB_DATA31
MEM_MB_DATA32
MEM_MB_DATA33
MEM_MB_DATA34
MEM_MB_DATA35
MEM_MB_DATA36
MEM_MB_DATA37
MEM_MB_DATA38
MEM_MB_DATA39
MEM_MB_DATA40
MEM_MB_DATA41
MEM_MB_DATA42
MEM_MB_DATA43
MEM_MB_DATA44
MEM_MB_DATA45
MEM_MB_DATA46
MEM_MB_DATA47
MEM_MB_DATA48
MEM_MB_DATA49
MEM_MB_DATA50
MEM_MB_DATA51
MEM_MB_DATA52
MEM_MB_DATA53
MEM_MB_DATA54
MEM_MB_DATA55
MEM_MB_DATA56
MEM_MB_DATA57
MEM_MB_DATA58
MEM_MB_DATA59
MEM_MB_DATA60
MEM_MB_DATA61
MEM_MB_DATA62
MEM_MB_DATA63

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

AA24
AA23
AD24
AE24
AA26
AA25
AD26
AE25
AC22
AD22
AE20
AF20
AF24
AF23
AC20
AD20
AD18
AE18
AC14
AD14
AF19
AC18
AF16
AF15
AF13
AC12
AB11

AE14
AF14
AF11
AD11

AB26
AE22
AC16
AD12

AC25
AC26
AF21
AF22
AE16
AD16
AF12
AE12

C11
A11
A14
B14
G11
E11
D12
A13
A15
A16
A19
A20
C14
D14
C18
D18
D20
A21
D24
C25
B20
C20
B24
C24
E23
E24
G25
G26
C26
D26
G23
G24

Y11

A12
B16
A22
E25

C12
B12
D16
C16
A24
A23
F26
E26

MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63

MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7

MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7

SOCKET_638_PIN

SOCKET_638_PIN

MEM:DATA

MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8

MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63

MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7

MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7

G12
F12
H14
G14
H11
H12
C13
E13
H15
E15
E17
H17
E14
F14
C17
G17
G18
C19
D22
E20
E18
F18
B22
C23
F20
F22
H24
J19
E21
E22
H20
H22
Y24
AB24
AB22
AA21
W22
W21
Y22
AA22
Y20
AA20
AA18
AB18
AB21
AD21
AD19
Y18
AD17
W16
W14
Y14
Y17
AB17
AB15
AD15
AB13
AD13
Y12
W11
AB14
AA14
AB12
AA12

E12
C15
E19
F24
AC24
Y19
AB16
Y13

G13
H13
G16
G15
C22
C21
G22
G21
AD23
AC23
AB19
AB20
Y15
W15
W12
W13

MEM_MA_DATA0
MEM_MA_DATA1
MEM_MA_DATA2
MEM_MA_DATA3
MEM_MA_DATA4
MEM_MA_DATA5
MEM_MA_DATA6
MEM_MA_DATA7
MEM_MA_DATA8
MEM_MA_DATA9
MEM_MA_DATA10
MEM_MA_DATA11
MEM_MA_DATA12
MEM_MA_DATA13
MEM_MA_DATA14
MEM_MA_DATA15
MEM_MA_DATA16
MEM_MA_DATA17
MEM_MA_DATA18
MEM_MA_DATA19
MEM_MA_DATA20
MEM_MA_DATA21
MEM_MA_DATA22
MEM_MA_DATA23
MEM_MA_DATA24
MEM_MA_DATA25
MEM_MA_DATA26
MEM_MA_DATA27
MEM_MA_DATA28
MEM_MA_DATA29
MEM_MA_DATA30
MEM_MA_DATA31
MEM_MA_DATA32
MEM_MA_DATA33
MEM_MA_DATA34
MEM_MA_DATA35
MEM_MA_DATA36
MEM_MA_DATA37
MEM_MA_DATA38
MEM_MA_DATA39
MEM_MA_DATA40
MEM_MA_DATA41
MEM_MA_DATA42
MEM_MA_DATA43
MEM_MA_DATA44
MEM_MA_DATA45
MEM_MA_DATA46
MEM_MA_DATA47
MEM_MA_DATA48
MEM_MA_DATA49
MEM_MA_DATA50
MEM_MA_DATA51
MEM_MA_DATA52
MEM_MA_DATA53
MEM_MA_DATA54
MEM_MA_DATA55
MEM_MA_DATA56
MEM_MA_DATA57
MEM_MA_DATA58
MEM_MA_DATA59
MEM_MA_DATA60
MEM_MA_DATA61
MEM_MA_DATA62
MEM_MA_DATA63

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA_DATA[0..63] 11

To normal SODIMM socket

MEM_MA_DM[0..7] 11

MEM_MA_DQS0_P 11
MEM_MA_DQS0_N 11
MEM_MA_DQS1_P 11
MEM_MA_DQS1_N 11
MEM_MA_DQS2_P 11
MEM_MA_DQS2_N 11
MEM_MA_DQS3_P 11
MEM_MA_DQS3_N 11
MEM_MA_DQS4_P 11
MEM_MA_DQS4_N 11
MEM_MA_DQS5_P 11
MEM_MA_DQS5_N 11
MEM_MA_DQS6_P 11
MEM_MA_DQS6_N 11
MEM_MA_DQS7_P 11
MEM_MA_DQS7_N 11

CPU_VDDR

C196

C196

4.7uF

1 1

4.7uF

C195

C195

4.7uF

4.7uF

C191

C191

4.7uF

4.7uF

C188

C188

4.7uF

4.7uF

C192

C192
220nF

220nF

Place close to socket

C177

C177

C180

C180
220nF

220nF

220nF

220nF

C182

C182
220nF

220nF

C187

C187
1nF

1nF

C176

C176
1nF

1nF

C198

C198
1nF

1nF

C181

C181
1nF

1nF

C186

C186
180pF

180pF

C183

C183
180pF

180pF

C189

C189
180pF

180pF

C197

C197
180pF

180pF

[ChckList] VDDR:0.22u*4/1n*4/180p*4/4.7u*4

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

C

C

C

Friday, February 05, 2010

Friday, February 05, 2010

A

B

C

D

Friday, February 05, 2010

MS-168x

SIG4 MEMORY

SIG4 MEMORY

SIG4 MEMORY

E

Sheet ofDate:

852

Sheet ofDate:

852

Sheet ofDate:

852

0A

0A

0A

5

[DG] BEAD: R<40mȍ(about 35), I>500mA

Keep net PWRGD, LDT_STOP#, LDT_RST# no stub

+1.5VRUN

R225

R225
300R

+1.5VRUN

+1.5VRUN

R2031KR203
1K

R2021KR202
1K

R2071KR207
1K

300R

R213

R213
300R

300R

R227

R227
300R

300R

CPU_VDDIO_SUS

CPU_VDDIO_SUS

CPU_VDDIO_SUS

CPU_PWRGD19

D D

CPU_LDT_STOP#16,19

CPU_LDT_RST#19

CPU_VDDIO_SUS

C C

CPU_SID

CPU_VDDIO_SUS

CPU_SIC

CPU_VDDIO_SUS

CPU_ALERT

B B

THERMDA/THERMDC is not used;
CPU thermal control is based on TSI by default.

R224R224

R219R219

R228R228

R204

R204

2.2K

2.2K

Q13

Q13

B

B

N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

C

C

E

E

A C

D10 BAS40WSD10 BAS40WS

R201

R201

2.2K

2.2K

Q12

Q12

B

B

N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

C

C

E

E

A C

D9 BAS40WSD9 BAS40WS

R206

R206
10K

10K

Q14

Q14

B

B

N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

C

C

E

E

PWRGD

LDT_STOP#

LDT_RST#

C388

C388
X_180pF

X_180pF

[ChckList] VDDA:100u*1/4.7u*1/0.22u0603*1/3300p0603*1

+VDDA

C175

C175
22uF

22uF

[CheckList} VDD1_FB_H/L NC if not use

+3.3VSUS

4.7K

4.7K
R194

R194

SMB_THRMCPU_DATA 24,25

+3.3VSUS

4.7K

4.7K
R193

R193

SMB_THRMCPU_CLK 24,25

+3.3VSUS

4.7K

4.7K
R205

R205

SMBALERT# 20

[Fuqun] Connect SB or EC?

4

L12 26R_600mAL12 26R_600mA

200MHz

LAYOUT: ROUTE VDDA TRACE APPROX.
50 mils WIDE (USE 2x25 mil TRACES TO
EXIT BALL FIELD) AND 500 mils LONG.

C167

C167

C169

220nF

220nF

C169

3.3NF

3.3NF

Keep trace from resisor to CPU within 0.6"
keep trace from caps to CPU within 1.2"

C390 3.9NFC390 3.9NF

C389 3.9NFC389 3.9NF

C166

C166

4.7UF

4.7UF

CPU_CLKP24
CPU_CLKN24

CPU_LDT_REQ# is NOT needed by S1G4

[Fuqun] Thermal

place them to CPU within 1.5"

+VLDT

CPU_VDDIO_SUS

R63 44.2RR63 44.2R
R62 44.2RR62 44.2R

R236

R236
510R

510R

R234

R234
510R

510R

R2080RR208
0R

[Fuqun] RSVD/TEST6/7/8/10/28--NC
[Fuqun] TEST14/15/16/17--Test Point
[Fuqun] TEST23/25--Test Point
[Fuqun] TEST12/18~24--Pull down 1Kohn to VSS
[Fuqun] TEST27 pull-up 1Kohm to VDDIO
[Fuqun] TEST25_H pull-up 510ohm to VDDIO
[Fuqun] TEST25_L pull-down 510ohm to VSS
[Fuqun] TEST9 is tied to VSS
[Fuqun] There is a (±1%) differential termination between TEST29_L and TEST29_H
[Fuqun] CPU_DBRDY not need pull down in checklist

CPU_SVC_R
CPU_SVD_R
PWRGD

R232

R232
169R

169R

TP27TP27

CPU_SIC20
CPU_SID20

CPU_VDD0_RUN_FB_H44
CPU_VDD0_RUN_FB_L44

TP29TP29
TP31TP31

TP33TP33
TP37TP37
TP40TP40
TP41TP41

TP32TP32

CPU_VDDA_RUN

CPU_CLKIN_SC_P
CPU_CLKIN_SC_N

LDT_RST#
PWRGD
LDT_STOP#
CPU_LDT_REQ#_CPU

CPU_SIC
CPU_SID
CPU_ALERT

CPU_HTREF0
CPU_HTREF1

CPU_DBRDY
CPU_TMS
CPU_TCK
CPU_TRST#
CPU_TDI

CPU_TEST23_TSTUPD
CPU_TEST18_PLLTEST1

CPU_TEST19_PLLTEST0
CPU_TEST25_H_BYPASSCLK_H

CPU_TEST25_L_BYPASSCLK_L

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST27_SINGLECHAIN

CPU_TEST9_ANALOGIN
CPU_TEST6_DIECRACKMON

R214R214
R211R211
R220R220

3

F8
F9

A9
A8

B7
A7

F10

C6

AF4
AF5
AE6

R6
P6

F6
E6

Y6

AB6
G10

AA9
AC9
AD9

AF9
AD7

H10

G9
E9

E8

AB8

AF7

AE7

AE8
AC8

AF8

C2

AA6

A3
A5
B3
B5
C1

+1.5VRUN

1K
R2121KR212

U22D

U22D

VDDA1
VDDA2

CLKIN_H
CLKIN_L

RESET_L
PWROK
LDTSTOP_L
LDTREQ_L

SIC
SID
ALERT_L

HT_REF0
HT_REF1

VDD0_FB_H
VDD0_FB_L

VDD1_FB_H
VDD1_FB_L

DBRDY
TMS
TCK
TRST_L
TDI

TEST23
TEST18

TEST19
TEST25_H

TEST25_L
TEST21

TEST20
TEST24
TEST22
TEST12
TEST27

TEST9
TEST6

RSVD1
RSVD2
RSVD3
RSVD4
RSVD5

SOCKET_638_PIN

SOCKET_638_PIN

1K
R2091KR209

2

M11

VSS

RSVD11

SVC
SVD

THERMTRIP_L

PROCHOT_L

MEMHOT_L

THERMDC
THERMDA

VDDIO_FB_H
VDDIO_FB_L

VDDNB_FB_H
VDDNB_FB_L

DBREQ_L

TDO

TEST28_H

TEST28_L

TEST17
TEST16
TEST15
TEST14

TEST7

TEST10

TEST8

TEST29_H

TEST29_L

RSVD10

RSVD9
RSVD8
RSVD7
RSVD6

W18

CPU_SVC_R

A6

CPU_SVD_R

A4

CPU_THERMTRIP#_VDDIO

AF6
AC7

CPU_MEMHOT#_VDDIO

AA8

CPU_THERMDC

W7

CPU_THERMDA

W8

W9
Y9

H6
G6

CPU_DBREQ#

E10

CPU_TDO

AE9

CPU_TEST28_H_PLLCHRZ_P

J7

CPU_TEST28_L_PLLCHRZ_N

H8

CPU_TEST17_BP3

D7

CPU_TEST16_BP2

E7

CPU_TEST15_BP1

F7

CPU_TEST14_BP0

C7

CPU_TEST7_ANALOG_T

C3

CPU_TEST10_ANALOGOUT

K8

CPU_TEST8_DIG_T

C4

CPU_TEST29_H_FBCLKOUT_P

C9
C8

CPU_TEST29_L_FBCLKOUT_N

H18
H19
AA7
D5
C5

Route as 80ohm, diff

R184's value is TBD.

CPU_VDDIO_SUS

R2101KR210
1K

TP35TP35

S1G4 does not support MEMHOT_L

TP36TP36
TP39TP39

TP43TP43
TP38TP38

[CheckList] VDDIO_FB_H/L NC if not use

CPU_VDDNB_RUN_FB_H 44

TP28TP28

TP42TP42

TP30TP30
TP34TP34

TP26TP26
TP24TP24

TP23TP23

TP25TP25

R65

R65

80.6R

80.6R

[Fuqun] TEST23--R358 NC in ref schematic?

[Fuqun] PWRGD pull-up in 2 times (R187 and R163)?

R215 X_2.2KR215 X_2.2K

CPU_SVC 44
CPU_SVD 44
CPU_PWRGD_SVID_REG 44

1

CPU_VDDIO_SUS

R216

R216
10K

10K
Q15

R200

R200
300R

300R

Thermdc and Thermda should be routed away to VRM,
crystal, etc. Customer should follow the MBDG.
However, Guam is using TSI so this does not applies to Guam.

route as differential
as short as possible
testpoint under package

Q15

B

B

N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

C

C

E

E

R199 X_0RR199 X_0R

CPU_THERMTRIP# 20
CPU_PROCHOT# 19
VRD_PROCHOT# 44

For debug only

CPU_DBREQ#
CPU_TEST27_SINGLECHAIN

CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST12_SCANSHIFTENB
CPU_TEST15_BP1
CPU_TEST14_BP0

CPU_TEST18_PLLTEST1
CPU_TEST19_PLLTEST0
CPU_TEST23_TSTUPD
CPU_DBRDY

CPU_TEST10_ANALOGOUT

R147, R152 is installed ONLY when SCAN is enabled
R215, R185 internal ONLY
R162 is TBD

[DateSheet] Internal Termination:Systems that do not require use of
these pins can rely on the internal termination to pull the signals
to the proper inactive state. When these pins are used, they must
not be driven with open-drain outputs,otherwise additional
termination is required

[DateSheet] Internal pull_up 870~1250 ohm:
SSA[2;0], TCK, TMS, TRST_L, TDI, DBREQ_L, PLATFORM_TYPE, TEST27

[DateSheet] Internal pull_down 870~1250 ohm:
TEST12, TEST[20:24]

Internal pull_up 870~1250 ohm:
SSA[2;0], TCK, TMS, TRST_L, TDI, DBREQ_L, PLATFORM_TYPE, TEST27

R218 300RR218 300R
R231 1KR231 1K

R226 1KR226 1K
R221 1KR221 1K
R222 1KR222 1K
R233 1KR233 1K
R229 1KR229 1K
R61 X_300RR61 X_300R
R64 X_300RR64 X_300R

R230 1KR230 1K
R223 1KR223 1K
R217 1KR217 1K
R67 X_300RR67 X_300R

R60 X_300RR60 X_300R

CPU_VDDIO_SUS

+VLDT

A A

5

4

BOOT VOLTAGE(VDD)

SVC

SVD

0 0 1.1 1.1
0 1 1.0 1.2
1 0 0.9 1.0
1 1 0.8 0.8

(CPUVRM_PRO#
= VCC/GND)

(CPUVRM_PRO#
= OPEN)

VID OVERIDE TABLE (VDD)

3

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

2

Friday, February 05, 2010

MS-168x

SIG4 CTRL and DEBEG

SIG4 CTRL and DEBEG

SIG4 CTRL and DEBEG

Sheet of

Sheet of

Sheet of

1

0A

0A

0A

952

952

952

5

4

3

2

1

U22F

U22F

AA4

D D

U22E

CPU_VDD_RUN

C C

CPU_VDDNB_RUN

CPU_VDDIO_SUS

B B

A A

G4
H2

J9
J11
J13
J15

K6
K10
K12
K14

L4

L7

L9
L11
L13
L15

M2
M6
M8

M10

N7
N9

N11
K16

M16

P16
T16
V16

H25
J17
K18
K21
K23
K25
L17

M18
M21
M23
M25

N17

U22E

VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23

VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5

VDDIO1
VDDIO2
VDDIO3
VDDIO4
VDDIO5
VDDIO6
VDDIO7
VDDIO8
VDDIO9
VDDIO10
VDDIO11
VDDIO12

SOCKET_638_PIN

SOCKET_638_PIN

VDDIO27
VDDIO26
VDDIO25
VDDIO24
VDDIO23
VDDIO22
VDDIO21
VDDIO20
VDDIO19
VDDIO18
VDDIO17
VDDIO16
VDDIO15
VDDIO14
VDDIO13

VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49

P8
P10
R4
R7
R9
R11
T2
T6
T8
T10
T12
T14
U7
U9
U11
U13
U15
V6
V8
V10
V12
V14
W4
Y2
AC4
AD2

Y25
V25
V23
V21
V18
U17
T25
T23
T21
T18
R17
P25
P23
P21
P18

CPU_VDD_RUN

CPU_VDDIO_SUS

AA11
AA13
AA15
AA17
AA19

AB2
AB7

AB9
AB23
AB25
AC11
AC13
AC15
AC17
AC19
AC21

AD6

AD8
AD25
AE11
AE13
AE15
AE17
AE19
AE21
AE23

B4
B6
B8

B9
B11
B13
B15
B17
B19
B21
B23
B25

D6

D8

D9

D11
D13
D15
D17
D19
D21
D23
D25

E4

F2
F11
F13
F15
F17
F19
F21
F23
F25

H7

H9
H21
H23

J4

VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65

SOCKET_638_PIN

SOCKET_638_PIN

VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98

VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129

J6
J8
J10
J12
J14
J16
J18
K2
K7
K9
K11
K13
K15
K17
L6
L8
L10
L12
L14
L16
L18
M7
M9
AC6
M17
N4
N8
N10
N16
N18
P2
P7
P9
P11
P17
R8
R10
R16
R18
T7
T9
T11
T13
T15
T17
U4
U6
U8
U10
U12
U14
U16
U18
V2
V7
V9
V11
V13
V15
V17
W6
Y21
Y23
N6

CPU_VDD_RUN

CPU_VDD_RUN

CPU_VDDNB_RUN

[ChckList] VDD:22u*8/0.22u*2/0.01u0603*2/180p*2
[ChckList] VDDNB:22u*3

CPU_VDDIO_SUS

[ChckList] VDDIO:22u*2/0.22u*6/0.1u0603*2/0.01u0603*1/180p*1/4.7u*4

PROCESSOR POWER AND GROUND

5

4

3

BOTTOM SIDE DECOUPLING

C184

C203

C203
22uF

22uF

C193

C193
22uF

22uF

C174

C174
22uF

22uF

C202

C202
22uF

22uF

C173

C173

C178

C178

22uF

22uF

22uF

22uF

C179

C179

C185

C185

22uF

22uF

22uF

22uF

CPU_VDDIO_SUS

C204

C204
22uF

22uF

C201

C201
22uF

22uF

C184
22uF

22uF

C194

C194
22uF

22uF

C200

C200
22uF

22uF

C157

C157
220nF

220nF

C161

C161
220nF

220nF

C222

C222
220nF

220nF

C155

C155
10nF

10nF

C154

C154
10nF

10nF

C207

C207
220nF

220nF

C190

C190
180pF

180pF

C160

C160
180pF

180pF

C209

C209
180pF

180pF

DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE

C211

C221

C221

4.7uF

4.7uF

C223

C223

4.7uF

4.7uF

C217

C217

4.7uF

4.7uF

C216

C216

4.7uF

4.7uF

C206

C206
220nF

220nF

C211

C213

220nF

220nF

C213
220nF

220nF

C212

C212
220nF

220nF

2

C210

C210
100nF

100nF

C214

C214
10nF

10nF

MSI

MSI

MSI

C220

C220

C215

C215
180pF

180pF

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

C208

C208

X_180pF

X_180pF

100nF

100nF

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MS-168x

SIG4 POWER and GND

SIG4 POWER and GND

SIG4 POWER and GND

Sheet of

Sheet of

Sheet of

10 52

10 52

1

10 52

0A

0A

0A

5

4

3

2

1

CPU_VDDIO_SUSCPU_VDDIO_SUS

100

105

106

111

112

117

118

123

MEM_MA_ADD[0..15]8 MEM_MB_ADD[0..15]8 MEM_MB_DATA[0..63] 8

D D

MEM_MA_BANK[0..2]8 MEM_MB_BANK[0..2]8

MEM_MA_DM[0..7]8 MEM_MB_DM[0..7]8

MEM_MA_DQS0_P8
MEM_MA_DQS1_P8
MEM_MA_DQS2_P8
MEM_MA_DQS3_P8
MEM_MA_DQS4_P8
MEM_MA_DQS5_P8
MEM_MA_DQS6_P8

C C

B B

MEM_MA_DQS7_P8
MEM_MA_DQS0_N8

MEM_MA_DQS1_N8
MEM_MA_DQS2_N8
MEM_MA_DQS3_N8
MEM_MA_DQS4_N8
MEM_MA_DQS5_N8
MEM_MA_DQS6_N8
MEM_MA_DQS7_N8

MEM_MA_CLK1_P8

MEM_MA_CLK1_N8

MEM_MA_CLK2_P8

MEM_MA_CLK2_N8

MEM_MA_CKE08
MEM_MA_CKE18

MEM_MA_RAS#8
MEM_MA_CAS#8

MEM_MA_WE#8
MEM_MA0_CS#08
MEM_MA0_CS#18

MEM_MA0_ODT08
MEM_MA0_ODT18

SDATA020,24

SCLK020,24

+3.3VRUN

MEM_MA_RST#8 MEM_MB_RST#8

C252

C252
1nF

1nF

Reverse

Connector

2

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

26

27

28

29

30

31

32

33

34
36

35
37

38

39

40

41
43

42
44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

CON_SODIMM200_RVS_V1

74

75

76

77

78

79

80

81

82

83

84

199

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

129

130

131

132

133

134

135

136

137

138

139

140

141

142

143

144

145

146

147

148
149
151

150

152
153

154
155

156
157

158
159

160
161

162
163

164
165

166
167

168
169

170
171

172
173

174
175

176
177

178
179

180
181

182
183

200

184
185
187

186

188
189

190
191

192
193

194
195

196
197

198
199

200

A A

MEM_MA_ADD0
MEM_MA_ADD1
MEM_MA_ADD2
MEM_MA_ADD3
MEM_MA_ADD4
MEM_MA_ADD5
MEM_MA_ADD6
MEM_MA_ADD7
MEM_MA_ADD8
MEM_MA_ADD9
MEM_MA_ADD10
MEM_MA_ADD11
MEM_MA_ADD12
MEM_MA_ADD13
MEM_MA_ADD14
MEM_MA_ADD15

MEM_MA_BANK0
MEM_MA_BANK1
MEM_MA_BANK2

MEM_MA_DM0
MEM_MA_DM1
MEM_MA_DM2
MEM_MA_DM3
MEM_MA_DM4
MEM_MA_DM5
MEM_MA_DM6
MEM_MA_DM7

MEM_MA_EVENT# MEM_MB_EVENT#

TP60TP60

C269

C269
1nF

1nF

+3.3VRUN +3.3VRUN

C238

C238
1uF

1uF

98

A0

97

A1

VDD075VDD176VDD281VDD382VDD487VDD588VDD693VDD899VDD794VDD9

96

A2

95

A3/A4

92

A4/A3

91

A5/A6

90

A6/A5

86

A7/A8

89

A8/A7

85

A9

107

A10/AP

84

A11

83

A12_BC#

119

A13

80

A14

78

A15/BA3

109

BA0/BA1

108

BA1/BA0

79

BA2

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

110

RAS#

115

CAS#

113

WE#

114

S0#

121

S1#

116

ODT0

120

ODT1

197

SA0

201

SA1

200

SDA

202

SCL

199

VDDspd

30

RST#

198

EVENT#

1

VREF

126

VrefCA

203

VTT1

204

VTT2

2

VSS0

3

VSS1

8

VSS2

9

VSS3

13

VSS4

14

VSS5

19

VSS6

20

VSS7

25

VSS8

26

VSS9

31

VSS10

32

VSS11

DDR3 SO-DIMM

DDR3 SO-DIMM

VSS1237VSS1338VSS1443VSS1544VSS16

VSS1854VSS1955VSS20

VSS17

48

60

49

5

124

DIMM1

DIMM1

DQ0
DQ1

VDD10

DQ2

VDD11

VDD12

VDD13

VDD14

VDD15

VDD16

VDD17
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53

(Normal)

(Normal)

DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

NC1
NC2

TEST

205
206

VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27

VSS26

VSS2572VSS2471VSS2366VSS2265VSS21

61

DDR3_SO-DIMM_SOCKET_1.5V

DDR3_SO-DIMM_SOCKET_1.5V

127

4

MEM_MA_DATA0

5

MEM_MA_DATA1

7

MEM_MA_DATA2

15

MEM_MA_DATA3

17

MEM_MA_DATA4

4

MEM_MA_DATA5

6

MEM_MA_DATA6

16

MEM_MA_DATA7

18

MEM_MA_DATA8

21

MEM_MA_DATA9

23

MEM_MA_DATA10

33

MEM_MA_DATA11

35

MEM_MA_DATA12

22

MEM_MA_DATA13

24

MEM_MA_DATA14

34

MEM_MA_DATA15

36

MEM_MA_DATA16

39

MEM_MA_DATA17

41

MEM_MA_DATA18

51

MEM_MA_DATA19

53

MEM_MA_DATA20

40

MEM_MA_DATA21

42

MEM_MA_DATA22

50

MEM_MA_DATA23

52

MEM_MA_DATA24

57

MEM_MA_DATA25

59

MEM_MA_DATA26

67

MEM_MA_DATA27

69

MEM_MA_DATA28

56

MEM_MA_DATA29

58

MEM_MA_DATA30

68

MEM_MA_DATA31

70

MEM_MA_DATA32

129

MEM_MA_DATA33

131

MEM_MA_DATA34

141

MEM_MA_DATA35

143

MEM_MA_DATA36

130

MEM_MA_DATA37

132

MEM_MA_DATA38

140

MEM_MA_DATA39

142

MEM_MA_DATA40

147

MEM_MA_DATA41

149

MEM_MA_DATA42

157

MEM_MA_DATA43

159

MEM_MA_DATA44

146

MEM_MA_DATA45

148

MEM_MA_DATA46

158

MEM_MA_DATA47

160

MEM_MA_DATA48

163

MEM_MA_DATA49

165

MEM_MA_DATA50

175

MEM_MA_DATA51

177

MEM_MA_DATA52

164

MEM_MA_DATA53

166

MEM_MA_DATA54

174

MEM_MA_DATA55

176

MEM_MA_DATA56

181

MEM_MA_DATA57

183

MEM_MA_DATA58

191

MEM_MA_DATA59

193

MEM_MA_DATA60

180

MEM_MA_DATA61

182

MEM_MA_DATA62

192

MEM_MA_DATA63

194
77

122
125

205
206

196
195
190
189
185
184
179
178
173
172
168
167
162
161
156
155
151
150
145
144
139
138
134
133
128

[Fuqun] Update DDR3 coonector LIB [Fuqun] Update DDR3 coonector LIB

MEM_MA_DATA[0..63] 8

TP77TP77

MEM_MB_ADD0
MEM_MB_ADD1
MEM_MB_ADD2
MEM_MB_ADD3
MEM_MB_ADD4
MEM_MB_ADD5
MEM_MB_ADD6
MEM_MB_ADD7
MEM_MB_ADD8
MEM_MB_ADD9
MEM_MB_ADD10
MEM_MB_ADD11
MEM_MB_ADD12
MEM_MB_ADD13
MEM_MB_ADD14
MEM_MB_ADD15

MEM_MB_BANK0
MEM_MB_BANK1
MEM_MB_BANK2

MEM_MB_DM0
MEM_MB_DM1
MEM_MB_DM2
MEM_MB_DM3
MEM_MB_DM4
MEM_MB_DM5
MEM_MB_DM6
MEM_MB_DM7

MEM_MB_DQS0_P8
MEM_MB_DQS1_P8
MEM_MB_DQS2_P8
MEM_MB_DQS3_P8
MEM_MB_DQS4_P8
MEM_MB_DQS5_P8
MEM_MB_DQS6_P8
MEM_MB_DQS7_P8

MEM_MB_DQS0_N8
MEM_MB_DQS1_N8
MEM_MB_DQS2_N8
MEM_MB_DQS3_N8
MEM_MB_DQS4_N8
MEM_MB_DQS5_N8
MEM_MB_DQS6_N8
MEM_MB_DQS7_N8

MEM_MB_CLK1_P8

MEM_MB_CLK1_N8

MEM_MB_CLK2_P8

MEM_MB_CLK2_N8

MEM_MB_CKE08
MEM_MB_CKE18

MEM_MB_RAS#8
MEM_MB_CAS#8

MEM_MB_WE#8
MEM_MB0_CS#08
MEM_MB0_CS#18

MEM_MB0_ODT08
MEM_MB0_ODT18

SDATA020,24

+3.3VRUN

SCLK020,24

R76 4.7KR76 4.7K

+3.3VRUN

TP62TP62

MEM_M_VREF_SUSMEM_M_VREF_SUS
MEM_M_VREFCAMEM_M_VREFCA

MEM_VTTMEM_VTT

C264

C264

C249

C249

1nF

1nF

1nF

1nF

C257

C257
1uF

1uF

3

98

A0

97

A1

VDD075VDD176VDD281VDD382VDD487VDD588VDD693VDD899VDD794VDD9

96

A2

95

A3/A4

92

A4/A3

91

A5/A6

90

A6/A5

86

A7/A8

89

A8/A7

85

A9

107

A10/AP

84

A11

83

A12_BC#

119

A13

80

A14

78

A15/BA3

109

BA0/BA1

108

BA1/BA0

79

BA2

11

DM0

28

DM1

46

DM2

63

DM3

136

DM4

153

DM5

170

DM6

187

DM7

12

DQS0

29

DQS1

47

DQS2

64

DQS3

137

DQS4

154

DQS5

171

DQS6

188

DQS7

10

DQS0#

27

DQS1#

45

DQS2#

62

DQS3#

135

DQS4#

152

DQS5#

169

DQS6#

186

DQS7#

101

CK0

103

CK0#

102

CK1

104

CK1#

73

CKE0

74

CKE1

110

RAS#

115

CAS#

113

WE#

114

S0#

121

S1#

116

ODT0

120

ODT1

197

SA0

201

SA1

200

SDA

202

SCL

199

VDDspd

30

RST#

198

EVENT#

1

VREF

126

VrefCA

203

VTT1

204

VTT2

2

VSS0

3

VSS1

8

VSS2

9

VSS3

13

VSS4

14

VSS5

19

VSS6

20

VSS7

25

VSS8

26

VSS9

31

VSS10

32

VSS11

2

100

105

106

111

112

117

118

VDD10

VDD11

VDD12

VDD13

VDD14

VDD15

DDR3 SO-DIMM

(Reverse)

DDR3 SO-DIMM

(Reverse)

VSS1237VSS1338VSS1443VSS1544VSS16

VSS1854VSS1955VSS20

VSS17

48

49

VSS2572VSS2471VSS2366VSS2265VSS21

60

61

123

124

DIMM2

DIMM2

MEM_MB_DATA0

5

DQ0

MEM_MB_DATA1

7

DQ1

MEM_MB_DATA2

15

DQ2

VDD16

VDD17

MEM_MB_DATA3

17

DQ3

MEM_MB_DATA4

4

DQ4

MEM_MB_DATA5

6

DQ5

MEM_MB_DATA6

16

DQ6

MEM_MB_DATA7

18

DQ7

MEM_MB_DATA8

21

DQ8

MEM_MB_DATA9

23

DQ9

MEM_MB_DATA10

33

DQ10

MEM_MB_DATA11

35

DQ11

MEM_MB_DATA12

22

DQ12

MEM_MB_DATA13

24

DQ13

MEM_MB_DATA14

34

DQ14

MEM_MB_DATA15

36

DQ15

MEM_MB_DATA16

39

DQ16

MEM_MB_DATA17

41

DQ17

MEM_MB_DATA18

51

DQ18

MEM_MB_DATA19

53

DQ19

MEM_MB_DATA20

40

DQ20

MEM_MB_DATA21

42

DQ21

MEM_MB_DATA22

50

DQ22

MEM_MB_DATA23

52

DQ23

MEM_MB_DATA24

57

DQ24

MEM_MB_DATA25

59

DQ25

MEM_MB_DATA26

67

DQ26

MEM_MB_DATA27

69

DQ27

MEM_MB_DATA28

56

DQ28

MEM_MB_DATA29

58

DQ29

MEM_MB_DATA30

68

DQ30

MEM_MB_DATA31

70

DQ31

MEM_MB_DATA32

129

DQ32

MEM_MB_DATA33

131

DQ33

MEM_MB_DATA34

141

DQ34

MEM_MB_DATA35

143

DQ35

MEM_MB_DATA36

130

DQ36

MEM_MB_DATA37

132

DQ37

MEM_MB_DATA38

140

DQ38

MEM_MB_DATA39

142

DQ39

MEM_MB_DATA40

147

DQ40

MEM_MB_DATA41

149

DQ41

MEM_MB_DATA42

157

DQ42

MEM_MB_DATA43

159

DQ43

MEM_MB_DATA44

146

DQ44

MEM_MB_DATA45

148

DQ45

MEM_MB_DATA46

158

DQ46

MEM_MB_DATA47

160

DQ47

MEM_MB_DATA48

163

DQ48

MEM_MB_DATA49

165

DQ49

MEM_MB_DATA50

175

DQ50

MEM_MB_DATA51

177

DQ51

MEM_MB_DATA52

164

DQ52

MEM_MB_DATA53

166

DQ53

MEM_MB_DATA54

174

DQ54

MEM_MB_DATA55

176

DQ55

MEM_MB_DATA56

181

DQ56

MEM_MB_DATA57

183

DQ57

MEM_MB_DATA58

191

DQ58

MEM_MB_DATA59

193

DQ59

MEM_MB_DATA60

180

DQ60

MEM_MB_DATA61

182

DQ61

MEM_MB_DATA62

192

DQ62

MEM_MB_DATA63

194

DQ63

77

NC1

122

NC2

MEM_MB_TESTMEM_MA_TEST

125

TEST

205

205

206

206

196

VSS51

195

VSS50

190

VSS49

189

VSS48

185

VSS47

184

VSS46

179

VSS45

178

VSS44

173

VSS43

172

VSS42

168

VSS41

167

VSS40

162

VSS39

161

VSS38

156

VSS37

155

VSS36

151

VSS35

150

VSS34

145

VSS33

144

VSS32

139

VSS31

138

VSS30

134

VSS29

133

VSS28

128

VSS27

VSS26

127

DDR3_SO-DIMM_SOCKET_1.5V_REVERSE

DDR3_SO-DIMM_SOCKET_1.5V_REVERSE

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Friday, February 05, 2010

Friday, February 05, 2010

Friday, February 05, 2010

TP61TP61

1

199

MS-168x

MS-168x

MS-168x

DDR3 SO-DIMM-A

DDR3 SO-DIMM-A

DDR3 SO-DIMM-A

1

Standard

Connector

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22
24

23
25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

CON_SODIMM200_STD_V1

74

75

76

77

78

79

80

81

82
84

83
85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

120
119
121

122
123

124
125

126
127

128
129

130
131

132
133

134
135

136
137

138

139

140
141

142
143

144
145

146
147

148
149

150
151

152
153

154
155
157

156

158
159

160
161

162
163

164
165

166
167

168
169

170
171

172
173
175

174

176
177

178
179

180
181

182
183

184
185

186
187

188
189

190
191

192

194

193
195

196
197

198
199

200

Sheet ofDate:

11 52

Sheet ofDate:

11 52

Sheet ofDate:

11 52

2

200

0A

0A

0A

5

D D

C C

4

3

2

1

B B

A A

MSI

MSI

MSI

5

4

3

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

A

A

A

Date:

Date:

Date:

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MS-168x

DDR3 SO-DIMM-B

DDR3 SO-DIMM-B

DDR3 SO-DIMM-B

Sheet of

Sheet of

Wednesday, January 13, 2010

Wednesday, January 13, 2010

Wednesday, January 13, 2010

2

Sheet of

12 52

12 52

12 52

1

0A

0A

0A

5

4

3

2

1

MEM_VTT

C240 X_100nFC240 X_100nF

D D

CPU_VDDIO_SUS

C256 100nFC256 100nF

DE-COUPLING FOR CHANNEL A SODIMM

C245

C245

C398

C398

100nF

100nF

100nF

100nF

C265

C265
100nF

100nF

CPU_VDDIO_SUS

C396

C396
100nF

100nF

C261

C261
100nF

100nF

C399

C399
100nF

100nF

C401

C401
X_100nF

X_100nF

C400

C400
X_100nF

X_100nF

C397

C397
X_100nF

X_100nF

C247

C247
X_100nF

X_100nF

C250

C250
X_100nF

X_100nF

C246

C246
X_100nF

X_100nF

DE-COUPLING FOR CHANNEL A SODIMM (ONE CAP PER POWER PIN)

C C

C395

C395
22uF_6.3V

22uF_6.3V

C394

C394
22uF_6.3V

22uF_6.3V

C268

C268

4.7uF

4.7uF

MEM_M_VREFCA

CPU_VDDIO_SUS

LAYOUT: PLACE CLOSE TO DIMMs

R73

R73

1.00K

1.00K
MEM_M_VREFCA

MEM_VTT

C243 X_100nFC243 X_100nF
C270 100nFC270 100nF

CPU_VDDIO_SUS

DE-COUPLING FOR CHANNEL B SODIMM

CPU_VDDIO_SUS

C254

C254

C267

C258

C258
X_100nF

X_100nF

C259

C259
X_100nF

X_100nF

X_100nF

X_100nF

C267
X_100nF

X_100nF

DE-COUPLING FOR CHANNEL B SODIMM (ONE CAP PER POWER PIN)

CPU_VDDIO_SUSCPU_VDDIO_SUS

C393

C392

C392
22uF_6.3V

22uF_6.3V

CPU_VDDIO_SUS

C393
22uF_6.3V

22uF_6.3V

MEM_VREF_SUS

R74

R74

1.00K

1.00K
MEM_M_VREF_SUS

LAYOUT: PLACE CLOSE TO DIMMs

C255

C253

C253

C260

C260
X_100nF

X_100nF

MEM_VTTMEM_VTT

C271

C271

4.7uF

4.7uF

X_100nF

X_100nF

C244

C244
100nF

100nF

C251

C251
100nF

100nF

C248

C248
100nF

100nF

C255
100nF

100nF

C266

C266
100nF

100nF

C262

C262
100nF

100nF

R72

B B

A A

5

R72

1.00K

1.00K

C263

C263
1nF

1nF

[ChckList] 1n*1/0.01u*1

C242

C242

[CRB] 1n*1/0.1u*1

10nF

10nF

4

3

R75

R75

1.00K

1.00K

C239

C239
1nF

1nF

[ChckList] 1n*1/0.01u*1

C241

C241

[CRB] 1n*1/0.1u*1

10nF

10nF

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

2

Friday, February 05, 2010

MS-168x

DDR3 DECOUPLING

DDR3 DECOUPLING

DDR3 DECOUPLING

1

Sheet of

Sheet of

Sheet of

13 52

13 52

13 52

0A

0A

0A

5

HT_CPU_NB_CAD_H07

D D

C C

B B

HT_CPU_NB_CAD_L07
HT_CPU_NB_CAD_H17
HT_CPU_NB_CAD_L17
HT_CPU_NB_CAD_H27
HT_CPU_NB_CAD_L27
HT_CPU_NB_CAD_H37
HT_CPU_NB_CAD_L37
HT_CPU_NB_CAD_H47
HT_CPU_NB_CAD_L47
HT_CPU_NB_CAD_H57
HT_CPU_NB_CAD_L57
HT_CPU_NB_CAD_H67
HT_CPU_NB_CAD_L67
HT_CPU_NB_CAD_H77
HT_CPU_NB_CAD_L77

HT_CPU_NB_CAD_H87
HT_CPU_NB_CAD_L87
HT_CPU_NB_CAD_H97
HT_CPU_NB_CAD_L97
HT_CPU_NB_CAD_H107
HT_CPU_NB_CAD_L107
HT_CPU_NB_CAD_H117
HT_CPU_NB_CAD_L117
HT_CPU_NB_CAD_H127
HT_CPU_NB_CAD_L127
HT_CPU_NB_CAD_H137
HT_CPU_NB_CAD_L137
HT_CPU_NB_CAD_H147
HT_CPU_NB_CAD_L147
HT_CPU_NB_CAD_H157
HT_CPU_NB_CAD_L157

HT_CPU_NB_CLK_H07
HT_CPU_NB_CLK_L07
HT_CPU_NB_CLK_H17
HT_CPU_NB_CLK_L17

HT_CPU_NB_CTL_H07
HT_CPU_NB_CTL_L07
HT_CPU_NB_CTL_H17
HT_CPU_NB_CTL_L17

R190 301RR190 301R

HT_RXCALP HT_TXCALP
HT_RXCALN

4

U21A

U21A

Y25

HT_RXCAD0P

Y24

HT_RXCAD0N

V22

HT_RXCAD1P

V23

HT_RXCAD1N

V25

HT_RXCAD2P

V24

HT_RXCAD2N

U24

HT_RXCAD3P

U25

HT_RXCAD3N

T25

HT_RXCAD4P

T24

HT_RXCAD4N

P22

HT_RXCAD5P

P23

HT_RXCAD5N

P25

HT_RXCAD6P

P24

HT_RXCAD6N

N24

HT_RXCAD7P

N25

HT_RXCAD7N

AC24

HT_RXCAD8P

AC25

HT_RXCAD8N

AB25

HT_RXCAD9P

AB24

HT_RXCAD9N

AA24

HT_RXCAD10P

AA25

HT_RXCAD10N

Y22

HT_RXCAD11P

Y23

HT_RXCAD11N

W21

HT_RXCAD12P

W20

HT_RXCAD12N

V21

HT_RXCAD13P

V20

HT_RXCAD13N

U20

HT_RXCAD14P

U21

HT_RXCAD14N

U19

HT_RXCAD15P

U18

HT_RXCAD15N

T22

HT_RXCLK0P

T23

HT_RXCLK0N

AB23

HT_RXCLK1P

AA22

HT_RXCLK1N

M22

HT_RXCTL0P

M23

HT_RXCTL0N

R21

HT_RXCTL1P

R20

HT_RXCTL1N

C23

HT_RXCALP

A24

HT_RXCALN

RS880M A11 HF MVD

RS880M A11 HF MVD

PART 1 OF 6

PART 1 OF 6

HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N

HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P

HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N

HT_TXCLK0P

HT_TXCLK0N

HT_TXCLK1P

HYPER TRANSPORT CPU I/F

HYPER TRANSPORT CPU I/F

HT_TXCLK1N

HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N

HT_TXCALP
HT_TXCALN

D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22

F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18

H24
H25
L21
L20

M24
M25
P19
R18

B24
B25

HT_TXCALN

3

R192 301RR192 301R

HT_NB_CPU_CAD_H0 7
HT_NB_CPU_CAD_L0 7
HT_NB_CPU_CAD_H1 7
HT_NB_CPU_CAD_L1 7
HT_NB_CPU_CAD_H2 7
HT_NB_CPU_CAD_L2 7
HT_NB_CPU_CAD_H3 7
HT_NB_CPU_CAD_L3 7
HT_NB_CPU_CAD_H4 7
HT_NB_CPU_CAD_L4 7
HT_NB_CPU_CAD_H5 7
HT_NB_CPU_CAD_L5 7
HT_NB_CPU_CAD_H6 7
HT_NB_CPU_CAD_L6 7
HT_NB_CPU_CAD_H7 7
HT_NB_CPU_CAD_L7 7

HT_NB_CPU_CAD_H8 7
HT_NB_CPU_CAD_L8 7
HT_NB_CPU_CAD_H9 7
HT_NB_CPU_CAD_L9 7
HT_NB_CPU_CAD_H10 7
HT_NB_CPU_CAD_L10 7
HT_NB_CPU_CAD_H11 7
HT_NB_CPU_CAD_L11 7
HT_NB_CPU_CAD_H12 7
HT_NB_CPU_CAD_L12 7
HT_NB_CPU_CAD_H13 7
HT_NB_CPU_CAD_L13 7
HT_NB_CPU_CAD_H14 7
HT_NB_CPU_CAD_L14 7
HT_NB_CPU_CAD_H15 7
HT_NB_CPU_CAD_L15 7

HT_NB_CPU_CLK_H0 7
HT_NB_CPU_CLK_L0 7
HT_NB_CPU_CLK_H1 7
HT_NB_CPU_CLK_L1 7

HT_NB_CPU_CTL_H0 7
HT_NB_CPU_CTL_L0 7
HT_NB_CPU_CTL_H1 7
HT_NB_CPU_CTL_L1 7

2

1

A A

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

B

B

B

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

5

4

3

2

Friday, February 05, 2010

MS-168x

RS880M-HT

RS880M-HT

RS880M-HT

Sheet of

Sheet of

Sheet of

1

14 52

14 52

14 52

0A

0A

0A

5

4

3

2

1

MXM3.0 need put the CAP on the motherboard.
Close to the MXM Slot

U21B

U21B

D4

GFX_RX0P

C4

GFX_RX0N

A3

D D

C C

PCIE_WLAN_RX0P35
PCIE_WLAN_RX0N35

PCIE_LAN_RX2P34
PCIE_LAN_RX2N34

PCIE_NEWCARD_RX4P30
PCIE_NEWCARD_RX4N30

PCIE_SB_NB_RX0P19
PCIE_SB_NB_RX0N19
PCIE_SB_NB_RX1P19

B B

PCIE_SB_NB_RX1N19
PCIE_SB_NB_RX2P19
PCIE_SB_NB_RX2N19
PCIE_SB_NB_RX3P19
PCIE_SB_NB_RX3N19

GFX_RX1P

B3

GFX_RX1N

C2

GFX_RX2P

C1

GFX_RX2N

E5

GFX_RX3P

F5

GFX_RX3N

G5

GFX_RX4P

G6

GFX_RX4N

H5

GFX_RX5P

H6

GFX_RX5N

J6

GFX_RX6P

J5

GFX_RX6N

J7

GFX_RX7P

J8

GFX_RX7N

L5

GFX_RX8P

L6

GFX_RX8N

M8

GFX_RX9P

L8

GFX_RX9N

P7

GFX_RX10P

M7

GFX_RX10N

P5

GFX_RX11P

M5

GFX_RX11N

R8

GFX_RX12P

P8

GFX_RX12N

R6

GFX_RX13P

R5

GFX_RX13N

P4

GFX_RX14P

P3

GFX_RX14N

T4

GFX_RX15P

T3

GFX_RX15N

AE3

GPP_RX0P

AD4

GPP_RX0N

AE2

GPP_RX1P

AD3

GPP_RX1N

AD1

GPP_RX2P

AD2

GPP_RX2N

V5

GPP_RX3P

W6

GPP_RX3N

U5

GPP_RX4P

U6

GPP_RX4N

U8

GPP_RX5P

U7

GPP_RX5N

AA8

SB_RX0P

Y8

SB_RX0N

AA7

SB_RX1P

Y7

SB_RX1N

AA5

SB_RX2P

AA6

SB_RX2N

W5

SB_RX3P

Y5

SB_RX3N

RS880M A11 HF MVD

RS880M A11 HF MVD

PART 2 OF 6

PART 2 OF 6

PCIE I/F GFX

PCIE I/F GFX

PCIE I/F GPP

PCIE I/F GPP

PCIE I/F SB

PCIE I/F SB

PCE_CALRP(PCE_BCALRP)

PCE_CALRN(PCE_BCALRN)

GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P

GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N

GPP_TX0P

GPP_TX0N

GPP_TX1P

GPP_TX1N

GPP_TX2P

GPP_TX2N

GPP_TX3P

GPP_TX3N

GPP_TX4P

GPP_TX4N

GPP_TX5P

GPP_TX5N

SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N

MXM3.0 need put the CAP on the motherboard.
Close to the MXM Slot

GFX_TX0P_CGFX_TX0P_C

A5

GFX_TX0N_CGFX_TX0N_C

B5

GFX_TX1P_CGFX_TX1P_C

A4

GFX_TX1N_C

B4

GFX_TX2P_CGFX_TX2P_C

C3

GFX_TX2N_CGFX_TX2N_C

B2

GFX_TX3P_CGFX_TX3P_C

D1

GFX_TX3N_CGFX_TX3N_C

D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2

GPP_TX0P_C

AC1

GPP_TX0N_C

AC2
AB4
AB3

GPP_TX2P_C

AA2

GPP_TX2N_C

AA1
Y1
Y2
Y4
Y3

GPP_TX5P_C

V1

GPP_TX5N_C

V2

A_TX0P_CA_TX0P_C

AD7

A_TX0N_CA_TX0N_C

AE7

A_TX1P_CA_TX1P_C

AE6

A_TX1N_CA_TX1N_C

AD6

A_TX2P_C

AB6

A_TX2N_C

AC6

A_TX3P_C

AD5

A_TX3N_C

AE5
AC8

AB8

R37 1.27KR37 1.27K
R35 2.0KR35 2.0K

+1.1VRUN

C331 C0.1u10X0402C331 C0.1u10X0402
C330 C0.1u10X0402C330 C0.1u10X0402
C329 C0.1u10X0402C329 C0.1u10X0402
C328 C0.1u10X0402C328 C0.1u10X0402
C324 C0.1u10X0402C324 C0.1u10X0402
C327 C0.1u10X0402C327 C0.1u10X0402
C326 C0.1u10X0402C326 C0.1u10X0402
C325 C0.1u10X0402C325 C0.1u10X0402

C333C0.1u10X0402 C333C0.1u10X0402
C334C0.1u10X0402 C334C0.1u10X0402

C335C0.1u10X0402 C335C0.1u10X0402
C336C0.1u10X0402 C336C0.1u10X0402

C339C0.1u10X0402 C339C0.1u10X0402
C338C0.1u10X0402 C338C0.1u10X0402

C362C0.1u10X0402 C362C0.1u10X0402
C356C0.1u10X0402 C356C0.1u10X0402
C352C0.1u10X0402 C352C0.1u10X0402
C355C0.1u10X0402 C355C0.1u10X0402
C348C0.1u10X0402 C348C0.1u10X0402
C351C0.1u10X0402 C351C0.1u10X0402
C345C0.1u10X0402 C345C0.1u10X0402
C347C0.1u10X0402 C347C0.1u10X0402

[CheckList] Use VDD_PCIE power?

HDMI_DATA2P 27
HDMI_DATA2N 27
HDMI_DATA1P 27
HDMI_DATA1N 27
HDMI_DATA0P 27
HDMI_DATA0N 27
HDMI_CLKP 27
HDMI_CLKN 27

PCIE_WLAN_TX0P 35
PCIE_WLAN_TX0N 35

PCIE_LAN_TX2P 34
PCIE_LAN_TX2N 34

PCIE_NEWCARD_TX4P 30
PCIE_NEWCARD_TX4N 30

PCIE_NB_SB_TX0P 19
PCIE_NB_SB_TX0N 19
PCIE_NB_SB_TX1P 19
PCIE_NB_SB_TX1N 19
PCIE_NB_SB_TX2P 19
PCIE_NB_SB_TX2N 19
PCIE_NB_SB_TX3P 19
PCIE_NB_SB_TX3N 19

RS880M Display Port Support (muxed on GFX)

DP0

DP1

A A

GFX_TX0,TX1,TX2 and TX3
AUX0 and HPD0

GFX_TX4,TX5,TX6 and TX7
AUX1 and HPD1

5

Keep the impendance of PCIE lane to 85ohm +/-15%
Including the A-link

4

All PCIe lane shou route 8" max for Gen2 connector and max 12" for Gen2 on board devices
Guam has the Lasso lane over 8" due to the large board, should use shorter lasso calbe for Guam.
Customer need to follow the MBDG.

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

MSI

MSI

MSI

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

B

B

B

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

3

2

Friday, February 05, 2010

MS-168x

RS880M-PCIE

RS880M-PCIE

RS880M-PCIE

Sheet of

Sheet of

Sheet of

1

15 52

15 52

15 52

0A

0A

0A

5

4

3

2

1

DDR3 based CPU and mobile platforms--Level shift to 1.8V
DDR2 based CPU mobile platforms--No need level shift

+1.5VRUN

E

CPU_LDT_STOP#9,19

D D

ALLOW_LDTSTOP19

NB_PWRGD20

A_RST#18,19,24,25

E

+1.8VRUN

+1.8VRUN

[CheckList] Change 1K to 2.2K for DDR3/NoteBook

R168

R1861KR186
1K
Q9

Q9

B

B

C

C

R167

R167
300R

300R

R151 X_NCR151 X_NC

R168

2.2K

2.2K

N-MMBT3904_NL_SOT23

N-MMBT3904_NL_SOT23

+1.8VRUN

R1871KR187
1K

NB_LDT_STOP#

ALLOW_LDTSTOP

NB_PWRGD
NB_RST#_IN

[Fuqun] NBPWRGD:level shifterTto 1.8V if driven from a 3.3-V output?

[CheckList] 200ohm bead?

+1.1VRUN

+1.8VRUN

C C

Change B204/C262 for
black screen issue in

C118

C118
22uF

22uF

L5 220RL5 220R
L7 3.9RL7 3.9R

L9 220RL9 220R
L4 220RL4 220R

C93

C93

2.2uF_4V

2.2uF_4V

20mA

C111

C111

2.2uF_4V

2.2uF_4V

65mA

120mA

AMD 47329 document

GFX_REFCLKP24
GFX_REFCLKN24

+1.1VRUN

[Fuqun] NC or not?

NBLINK_RCLKP24
NBLINK_RCLKN24

B B

PLACE R291, R292 CLOSE TO NB(R291, R292 IS FOR A11 SB800 ONLY)

R39 4.7KR39 4.7K
R40 4.7KR40 4.7K

R36

R36
X_49.9R

X_49.9R
A11

A11

R34

R34
X_49.9R

X_49.9R
A11

A11

+3.3VRUN

L8 220RL8 220R

110mA

+1.8VRUN

20mA

+1.8VRUN

L6 220RL6 220R

4mA

Termination resstors < 1 inch trace

NB_VGA_R26
NB_VGA_G26
NB_VGA_B26

NB_HSYNC#18,26

NB_VSYNC#18,26

DAC_SCL26

DAC_SDAT26

R49 140RR49 140R
R48 150RR48 150R
R50 150RR50 150R

[CheckList] 2.2uf?

C102

C102

4.7uF_4V

4.7uF_4V

C82

C82

2.2uF_4V

2.2uF_4V

HT_REFCLKP24
HT_REFCLKN24

NB_OSC24

TP19TP19
TP71TP71

LCD_I2C_CLK26
LCD_I2C_DATA26

NB_HDMI_CLK27
NB_HDMI_DATA27

STRP_DATA:

1. Strap function

2. Control NB_CORE power
1-0.95V;0-1.1V

C105

C105

2.2uF_4V

2.2uF_4V

C104

C104

0.1uF

0.1uF

C103

C103

2.2uF_4V

2.2uF_4V

1%

**

1%
1%

PLLVDD
PLLVDD18

20mA

VDDA18HTPLL
VDDA18PCIEPLL

NB_RST#_IN
NB_PWRGD
NB_LDT_STOP#
ALLOW_LDTSTOP

NB_REFCLKN

GPP_REFCLKP
GPP_REFCLKN

STRP_DATA18

R155 150RR155 150R

AVDD

AVDDDI

AVDDQ

[Fuqun] TV--NC

R47 715R1%0402R47 715R1%0402

TP20TP20

RS880_AUX_CAL

U21C

U21C

F12

AVDD1(NC)

E12

AVDD2(NC)

F14

AVDDDI(NC)

G15

AVSSDI(NC)

H15

AVDDQ(NC)

H14

AVSSQ(NC)

E17

C_Pr(DFT_GPIO5)

F17

Y(DFT_GPIO2)

F15

COMP_Pb(DFT_GPIO4)

G18

RED(DFT_GPIO0)

G17

REDb(NC)

E18

GREEN(DFT_GPIO1)

F18

GREENb(NC)

E19

BLUE(DFT_GPIO3)

F19

BLUEb(NC)

A11

DAC_HSYNC(PWM_GPIO4)

B11

DAC_VSYNC(PWM_GPIO6)

F8

DAC_SCL(PCE_RCALRN)

E8

DAC_SDA(PCE_TCALRN)

G14

DAC_RSET(PWM_GPIO1)

A12

PLLVDD(NC)

D14

PLLVDD18(NC)

B12

PLLVSS(NC)

H17

VDDA18HTPLL

D7

VDDA18PCIEPLL1

E7

VDDA18PCIEPLL2

D8

SYSRESETb

A10

POWERGOOD

C10

LDTSTOPb

C12

ALLOW_LDTSTOP

C25

HT_REFCLKP

C24

HT_REFCLKN

E11

REFCLK_P/OSCIN(OSCIN)

F11

REFCLK_N(PWM_GPIO3)

T2

GFX_REFCLKP

T1

GFX_REFCLKN

U1

GPP_REFCLKP

U2

GPP_REFCLKN

V4

GPPSB_REFCLKP(SB_REFCLKP)

V3

GPPSB_REFCLKN(SB_REFCLKN)

B9

I2C_CLK

A9

I2C_DATA

A8

DDC_CLK0/AUX0P(NC)

B8

DDC_DATA0/AUX0N(NC)

B7

DDC_CLK1/AUX1P(NC)

A7

DDC_DATA1/AUX1N(NC)

B10

STRP_DATA

G11

RSVD

C8

AUX_CAL(NC)
RS880M A11 HF MVD

RS880M A11 HF MVD

PART 3 OF 6

PART 3 OF 6

TXOUT_L2N(DBG_GPIO0)
TXOUT_L3N(DBG_GPIO2)

TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)

TXOUT_U3P(PCIE_RESET_GPIO5)

CRT/TVOUT

CRT/TVOUT

TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)

LVTM

LVTM

PM

PM

LVDS_DIGON(PCE_TCALRP)

LVDS_BLON(PCE_RCALRP)

LVDS_ENA_BL(PWM_GPIO2)

CLOCKs PLL PWR

CLOCKs PLL PWR

MIS.

MIS.

SUS_STAT#(PWM_GPIO5)

TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)

TXOUT_L3P(NC)

TXOUT_U0P(NC)
TXOUT_U0N(NC)

TXOUT_U2P(NC)
TXOUT_U2N(NC)

TXOUT_U3N(NC)

TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)

VDDLTP18(NC)

VSSLTP18(NC)

VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)

VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)

TMDS_HPD(NC)

HPD(NC)

THERMALDIODE_P

THERMALDIODE_N

TESTMODE

A22
B22
A21
B21
B20
A20
A19
B19

B18
A18
A17
B17
D20
D21
D18
D19

B16
A16
D16
D17

A13
B13

A15
B15
A14
B14

C14
D15
C16
C18
C20
E20
C22

E9
F7
G12

D9
D10

D12
AE8

AD8
D13

TEST_EN

LVDS_TX_L0P 26
LVDS_TX_L0N 26
LVDS_TX_L1P 26
LVDS_TX_L1N 26
LVDS_TX_L2P 26
LVDS_TX_L2N 26

TP22TP22

LVDS_TX_CLKLP 26
LVDS_TX_CLKLN 26

C369

C369

2.2uF_4V

2.2uF_4V

B10 220RB10 220R

B8 220R_2AB8 220R_2A

15mA

300mA

C117

C117

C114

C114

4.7uF

4.7uF

0.1uF

0.1uF

LVDS_VDDEN 26
LVDS_BLON 26

TP21TP21

[Fuqun] BIOS control for BLON or PWM function

HDMI_HPD 27

SUS_STAT# 18,20

R41

R41

1.8K

1.8K

+1.8VRUN

+1.8VRUN

[Fuqun] SUS_STAT#-->Not need connect to SB if Side-Port memory not implemented

RS880M DEBUG PIN MAPPING

1

LVDS_DIGON
LVDS_ENA_BL
LVDS_BLON
TMDS_HPD
AUX1N
AUX1P
HPD
AUX_CAL

Sheet of

Sheet of

Sheet of

16 52

16 52

16 52

0A

0A

0A

DEBUG_OUT0
DEBUG_OUT1
DEBUG_OUT2
DEBUG_OUT3
DEBUG_OUT4
DEBUG_OUT5

A A

MSI

MSI

MSI

5

4

3

2

DEBUG_OUT6
DEBUG_OUT7

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MICRO-STAR INT'L CO.,LTD

MS-168x

MS-168x

Size Document Description Rev

Size Document Description Rev

Size Document Description Rev

Custom

Custom

Custom

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

Date:

Friday, February 05, 2010

MS-168x

RS880M-I/F

RS880M-I/F

RS880M-I/F