motorola W220 Circuit description
W220 GSM/GPRS Level 3 Circuit Descriptions
V1.0
725 Edge
W220 GSM/GPRS
Level 3
Circuit Description
Motorola Proprietary Information/
2006/03/27
W220 GSM/GPRS Level 3 Circuit Descriptions
725 Edge
Index
1 Receive ................................................................................................................................. 4
1.1 Band selection............................................................................................................... 4
1.2 Frontend........................................................................................................................6
1.3 Demodulation................................................................................................................ 6
1.4 Audio............................................................................................................................. 7
1.5 26MHz System Clock..................................................................................................10
2 TRANSMIT....................................................................................................................... 10
2.1 Audio...........................................................................................................................10
2.2 Modulation.................................................................................................................. 12
2.3 TX VCO.......................................................................................................................13
2.4 TX PA.......................................................................................................................... 14
2.5 TX PA Power Control................................................................................................. 14
3 Baseband Processsor ........................................................................................................ 16
3.1 Main Baseband Digital Processor - U201 (CalypsoLite) .......................................... 16
3.2 Baseband Analogue Coprocessor –U202 (IOTA) ...................................................... 17
4 Displays.............................................................................................................................. 18
4.1 Color Display: ............................................................................................................ 18
4.2 Display Backlights......................................................................................................19
4.3 Display Indicators....................................................................................................... 20
5 32KHz RTC.......................................................................................................................20
6 SIM Circuit........................................................................................................................ 20
7 Keypad ............................................................................................................................... 21
7.1 Keypad........................................................................................................................21
7.2 Keypad Backlights ...................................................................................................... 22
8 Memory.............................................................................................................................. 23
8.1 U501 – ST Microelectronics Memory M36W0R6040T1ZAQF ..................................23
9 Charging Circuit and External Power............................................................................ 24
9.1 Battery support ........................................................................................................... 24
9.2 Charger support.......................................................................................................... 25
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W220 GSM/GPRS Level 3 Circuit Descriptions
725 Edge
10 MELODY IC................................................................................................................. 26
10.1 U101 - OKI ML2871................................................................................................... 26
11 FM TUNER ................................................................................................................... 27
11.1 FM IC – Philips TEA5761HN..................................................................................... 27
11.2 Audio Multiplex........................................................................................................... 28
12 HALL SENSOR ............................................................................................................ 29
13 VIBRATOR MOTOR .................................................................................................. 29
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W220 GSM/GPRS Level 3 Circuit Descriptions
725 Edge
1 Receive
1.1 Band selection
Figure 1 Antenna and RF connector
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W220 GSM/GPRS Level 3 Circuit Descriptions
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The received signal is received through the antenna A601, C625, and R606 components
provide antenna matching. The RF signal then enters mechanical 50-ohm RF connector
CON601. This RF connector is used for phasing, testing and HFK.
Figure 2 T/R Switch and Saw filter
From CON601, the RF signal enters U607 (TX/RX antenna switch) on Pin 10 (ANT). By
controlling U607, the RX path is isolated from the TX path. The following VC1 and VC2
control the RF to Switch to RX or TX path:
VC1 on U607 Pin 4 and VC2 on U607 PIN 8 set low to put the phone into RX Mode for the
dual band.
EGSM_RX on U607 Pin 5 is the received GSM900 signal and separated out from U607. The
signal is passed the matching L606 and then is filtered sharply out again by single-ended
differential-output U602 (Saw Filter). U602 (Saw Filter) is used to filter out out-of-band noises
and to isolate the GSM/DCS bands. C610, L601 and C609 are the matching circuits between
U602 and the front-end circuit. The differential RX signal is passed the pi matching circuit
and then enters the front-end circuit.
DCS_RX on U607 Pin 7 is the received DCS1800 signal and separated out from U607. The
signal is passed the matching L607 and then is filtered sharply out again by single-ended
differential-output U603 (Saw Filter). U603 (Saw Filter) is used to filter out-of-band noises and
to isolate the GSM/DCS bands. C608, L602 and C607 are the matching circuits between U602
and the front-end circuit. The differential RX signal is passed the pi matching circuit and then
enters the front-end circuit.
VC1 on U607 Pin 4 set high (2.8V) and VC2 on U607 PIN 8 set low put the phone into TX
Mode of GSM900. The power-amplified GSM signal enters U607 Pin 3 and is routed to
Antenna.
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W220 GSM/GPRS Level 3 Circuit Descriptions
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VC1 on U607 Pin 4 set low and VC2 on U607 PIN 8 set high (2.8V) puts the phone into TX
Mode of DCS1800. The power-amplified DCS signal enters U607 Pin 1 and is routed to
Antenna.
1.2 Frontend
Figure 3 Front-end circuit
The receiver block diagram in the Aero-II SI4210 is shown in Figure 3. The U604 (Aero II
transceiver) uses a digital low-IF receiver architecture that allows for the on-chip integration
of the channel selection filters, eliminating the external RF image reject filters, and the IF
SAW filter required in conventional superheterodyne architectures. Compared with directconversion architectures, the digital low-IF architecture has a much greater degree of
immunity to dc offsets that can arise from RF local oscillator (RFLO) self-mixing, second-order
distortion of blockers (AM suppression), and device 1/f noise.
The RX section integrates four differential input low noise amplifiers (LNAs). Currently, we
just use it for dual-band (GSM 900 & DCS 1800) operation. The LNA inputs are matched to
150 or 200 Ω balanced-output SAW filters through external LC matching networks.
1.3 Demodulation
A quadrature image-reject mixer downconverts the RF signal to a low IF (200KHz). The
mixer output is amplified with an analog programmable gain amplifier (PGA)
The quadrature IF signal is digitized with high resolution analog-to-digital converters
(ADCs). The ADC output is downconverted to baseband with a digital quadrature local
oscillator signal. Digital decimation and FIR filters perform digital filtering, and remove ADC
quantization noise, blockers, and reference interferers.
After filtering, the digital output is scaled with a PGA Digital-to-analog converters (DACs)
drive differential I and Q analog signals onto the RXIP on U604 Pin7, RXIN on U604 Pin6,
RXQP on U604 Pin5 and RXQN on U604 Pin4 to interface to standard analog-input baseband
ICs.
In order to process the analog base-band RXIP, RXIN, RXQP and RXQN generated by the
RF circuits to DSP U201 (Calypso-Lite), the BDL path of U202 (IOTA) includes two identical
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W220 GSM/GPRS Level 3 Circuit Descriptions
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circuits. The first stage of the BDL path is a continuous second-order ant-aliasing filter that
prevents aliasing of out-of-band frequency components due to sampling in the ADC. This filter
serves also as an adaptation stage between external and on-chip circuitry. The anti-aliasing
filter is followed by a fourth-order Σ - ∆ modulator that performs analog-to-digital
conversion at a sampling rate of 6.5 MHz. The ADC provides 2-bit words to a digital filter
that performs the decimation by a ratio of 24 to lower the sampling rate to 270.833 kHz. The
ADC also provides channel separation by providing enough rejection of the adjacent channels
to allow the demodulation performances required by the GSM specification. The BDL path
includes an offset register, in which the value representing the channel dc offset is stored. This
value is subtracted from the output of the digital filter before transmitting the digital samples
to the DSP via the BSP (Base-band Serial Port), i.e. BFSR on U202 Pin K11 and BDR on
U202 Pin L12.
Figure 4 BDL Function Diagram
1.4 Audio
Internal to U202 (IOTA), in the voice downlink (VDL) path, the voice-band coder-decoder
(codec) (VBC) converts the digital samples of speech data received from the DSP via the
voice-band serial port VSP (VDX on Pin H10, VDR on Pin G12, VFSRX on Pin G11,
VCLKRX on Pin K12) into analog audio signals. The VBC includes an output amplifier of
headset and phone speaker. The VBC also performs the programmable gain, volume control,
and side-tone functions. In addition, the Audio Ringer signal will also be generated in the
U101 (Melody IC, ML2871) commanded by U201 (CalypsoLite).
The digital speech coming from the DSP is first fed to a speech digital filter that has two
functions. The first function is to interpolate the input signal and to increase the sampling rate
from 8 kHz up to 40 kHz to allow the digital-to-analog conversion to be performed by an over-
sampling digital modulator. The second function is to band-limit the speech signal with both
low-pass and high-pass transfer functions.
The interpolated and band-limited signal is fed to a second order Σ-∆digital modulator
sampled at 1 MHz to generate a 4-bit (9 levels) over-sampled signal. This signal is then passed
through a dynamic element-matching block and then to a 4-bit digital-to-analog converter
(DAC).
The volume control and the programmable gain are performed in the voice-band digital
filter. Volume control is performed in steps of 6 dB from 0 dB to −24 dB. In mute state,
attenuation is higher than 40 dB. A fine adjustment of gain is possible from −6 dB to +6 dB
in 1-dB steps to calibrate the system depending on the earphone characteristics. In fact, the
user can easily adjust the gain of the audio outputs with the volume control buttons.
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W220 GSM/GPRS Level 3 Circuit Descriptions
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The earphone amplifier provides a full differential signal on the EARP on Pin A12 and
EARN on Pin A11, and a headset output amplifier provides a single-ended signal on the
HSO on Pin A10.
Figure 5. VDL Function Diagram
1.4.1 Handset
VDD_1V8
LED1
VBAT
LED2
LED3
LCD_RESET
/WR
/RD
MAIN_CS
LED4
PWL
A0
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
21
21
23
23
25
25
27
27
29
29
31
31
31 pin connector
C1
33pF
U2
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
22
22
24
24
26
26
28
28
30
30
VIN_2V8
VBAT
D0
D1
D2
D3
D4
D5
D6
D7
EARNEARP
Figure 6. Earphone Path Circuit
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W220 GSM/GPRS Level 3 Circuit Descriptions
725 Edge
U202 (IOTA)’s internal earphone differential amplifier (1dB) drives the handset speaker.
Following the Earphone path from EARP on Pin A12 and EARN on Pin A11, they are passed
trough Pin26 and Pin28 on CON301 to Pin27 and Pin28 on U2 respectively. They are routed
through and filtered by C4, L1 (Noise filter) and C5. Then, both voice signals respectively feed
into the P4 and P5. ESD1 and ESD2 are used to avoid ESD event.
1.4.2 Headset
Figure 7. Audio Switching Path
The headset uses a standard 2.5mm phone jack. The jack contains a mechanical switch that
consists of J102 Pin 3 in serial with J102 Pin 4. As the headset device plug in, the switch path is
open. The voltage of EP_Status is changed from high (2.8V) to low (0V). The phone is
informed the headset device has been plugged in. The headset may contain a momentary
switch, which is normally closed. When the momentary switch is pressed, then U107 (2.2V
Reset IC) is triggered and the output Hook_SW on Pin 1 is set high. The phone will detect the
voltage variation and make an appropriate response to this action, which could be to answer a
call, end a call.
The Headset Speaker is driven by U202 (IOTA)’s internal headset amplifier. Following the
headset speaker path from the U202 (IOTA) Pin A10 HSO in parallel with C218 to filter out
high band noise, in serial with C121 to block DC and in parallel with R125, it is routed and
passed through U104 (Analog Switch), coming out with COM1 and COM2. Then, they are
routed into U105 (Headphone Amplifier). U105’s OUTL and OUTR are fed back into MAX
BASS OP Circuit consisting of internal OP and external resistors to set Max Gain, and then
are coming out with OP_L1 and OP_R1.
OP_L1 is directly connected to J102 Pin 6 in serial with L106 and in parallel with ESD113.
OP_R1 is routed into U104 (Analog Switch) Pin 1 and comes out from HSOOUT on Pin 4.
The signal is connected to J102 Pin 1 in serial with L101 and in parallel with ESD106.
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