MOTOROLA SN74LS221D, SN74LS221DR2, SN74LS221M, SN74LS221ML1, SN74LS221ML2 Datasheet

 Semiconductor Components Industries, LLC, 1999

December, 1999 – Rev. 6

1 Publication Order Number:

SN74LS221/D

SN74LS221

Dual Monostable
Multivibrators with
Schmitt-Trigger Inputs

Each multivibrator of the LS221 features a negative-transition­triggered input and a positive-transition-triggered input either of
which can be used as an inhibit input.

Pulse triggering occurs at a voltage level and is not related to the
transition time of the input pulse. Schmitt-trigger input circuitry for B
input allows jitter-free triggering for inputs as slow as 1 volt /second,
providing the circuit with excellent noise immunity. A high immunity
to V

CC

noise is also provided by internal latching circuitry.

Once triggered, the outputs are independent of further transitions of
the inputs and are a function of the timing components. The output
pulses can be terminated by the overriding clear. Input pulse width
may be of any duration relative to the output pulse width. Output pulse
width may be varied from 35 nanoseconds to a maximum of 70 s by
choosing appropriate timing components. With R

ext

= 2.0 kΩ and C

ext

= 0, a typical output pulse of 30 nanoseconds is achieved. Output rise
and fall times are independent of pulse length.

Pulse width stability is achieved through internal compensation and
is virtually independent of VCC and temperature. In most applications,
pulse stability will only be limited by the accuracy of external timing
components.

Jitter-free operation is maintained over the full temperature and V

CC

ranges for greater than six decades of timing capacitance (10 pF to 10
µF), and greater than one decade of timing resistance (2.0 to 100 kΩ
for the SN74LS221). Pulse width is defined by the relationship:

tw(out) = C

extRext

ln 2.0 ≈ 0.7 C

ext Rext

; where tW is in ns if C

ext

is in

pF and R

ext

is in kΩ. If pulse cutoff is not critical, capacitance up to

1000 µF and resistance as low as 1.4 kΩ may be used. The range of
jitter-free pulse widths is extended if VCC is 5.0 V and 25°C
temperature.

• SN74LS221 is a Dual Highly Stable One-Shot

• Overriding Clear Terminates Output Pulse

• Pin Out is Identical to SN74LS123

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 4.75 5.0 5.25 V

T

A

Operating Ambient

T emperature Range

0 25 70 °C

I

OH

Output Current – High –0.4 mA

I

OL

Output Current – Low 8.0 mA

LOW

POWER

SCHOTTKY

Device Package Shipping

ORDERING INFORMATION

SN74LS221N 16 Pin DIP 2000 Units/Box
SN74LS221D 16 Pin

SOIC

D SUFFIX

CASE 751B

http://onsemi.com

2500/Tape & Reel

PLASTIC
N SUFFIX
CASE 648

16

1

16

1

SN74LS221

http://onsemi.com

2

(TOP VIEW)

Positive logic: Low input to clear resets Q low and

Positive logic: Q

high regardless of dc levels at A

Positive logic: or B inputs.

14 13 12 11 10 9

123456

7

16 15

8

V

CC

1A

1 R

ext/

C

ext

1

C

ext

1Q 2Q 2B

2

CLR

2A

1B 1

CLR

1Q

2Q 2

C

ext

2 R

ext

/

C

ext

GND

Q
Q

CLR

Q

Q

CLR

+

V

CC

R

ext

R/CC

ext

FUNCTION TABLE

(EACH MONOSTABLE)

INPUTS OUTPUTS

CLEAR A B Q Q

L X X L H
X H XL H
X X LL H
H L

°

H

±

H

*

°

L H

*See operational notes — Pulse Trigger Modes

TYPE

TYPICAL

POWER

MAXIMUM

OUTPUT PULSE

DISSIPATION LENGTH

SN74LS221 23 mW 70 s

SN74LS221

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3

OPERATIONAL NOTES

Once in the pulse trigger mode, the output pulse width is

determined by t

W

= R

extCext

In2, as long as R

ext

and C

ext

are
within their minimum and maximum valves and the duty
cycle is less than 50%. This pulse width is essentially
independent of VCC and temperature variations. Output
pulse widths varies typically no more than ±0.5% from
device to device.

If the duty cycle, defined as being 100

@

t

W
T

where T is the

period of the input pulse, rises above 50%, the output pulse
width will become shorter. If the duty cycle varies between
low and high valves, this causes the output pulse width to
vary in length, or jitter. To reduce jitter to a minimum, R

ext

should be as large as possible. (Jitter is independent of C

ext

).

With R

ext

= 100K, jitter is not appreciable until the duty

cycle approaches 90%.

Although the LS221 is pin-for-pin compatible with the
LS123, it should be remembered that they are not
functionally identical. The LS123 is retriggerable so that the
output is dependent upon the input transitions once it is high.
This is not the case for the LS221. Also note that it is
recommended to externally ground the LS123 C

ext

pin.

However, this cannot be done on the LS221.

The SN74LS221 is a dual, monolithic, non-retriggerable,
high-stability one shot. The output pulse width, t

W

can be
varied over 9 decades of timing by proper selection of the
external timing components, R

ext

and C

ext

.

Pulse triggering occurs at a voltage level and is, therefore,
independent of the input slew rate. Although all three inputs
have this Schmitt-trigger effect, only the B input should be
used for very long transition triggers (≥1.0 µV/s). High
immunity to V

CC

noise (typically 1.5 V) is achieved by

internal latching circuitry. However, standard V

CC

bypassing is strongly recommended.

The LS221 has four basic modes of operation.

Clear Mode: If the clear input is held low, irregardless of

the previous output state and other input
states, the Q output is low.

Inhib­it Mode:

If either the A input is high or the B input is
low, once the Q output goes low, it cannot
be retriggered by other inputs.

Pulse Trigger
Mode: A transition of the A or B inputs as indicated

in the functional truth table will trigger the Q
output to go high for a duration determined
by the t

W

equation described above; Q will

go low for a corresponding length of time.
The Clear input may also be used to trigger

an output pulse, but special logic precondi­tioning on the A or B inputs must be done
as follows:

Following any output triggering action
using the A or B inputs, the A input must
be set high OR the B input must be set
low to allow Clear to be used as a trigger.
Inputs should then be set up per the truth
table (without triggering the output) to
allow Clear to be used a trigger for the
output pulse.

If the Clear pin is routinely being used to
trigger the output pulse, the A or B inputs
must be toggled as described above
before and between each Clear trigger
event.

Once triggered, as long as the output
remains high, all input transitions (except
overriding Clear) are ignored.

Overriding
Clear Mode: If the Q output is high, it may be forced low

by bringing the clear input low.