Motorola MCM6341ZP10, MCM6341ZP11, MCM6341ZP12, MCM6341ZP15, SCM6341ZP10A Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MCM6341/D
Advance Information
128K x 24 Bit Static Random
Access Memory
The MCM6341 is a 3,145,728–bit static random access memory organized as
131,072 words of 24 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6341 is equipped with chip enable (E1
) pins, allowing for greater system flexibility and eliminating bus contention
(G
problems.
The MCM6341 is available in a 1 19–bump PBGA package.
• Single 3.3 V ± 10% Power Supply
• Fast Access Time: 10/11/12/15 ns
• Equal Address and Chip Enable Access Time
• All Inputs and Outputs are TTL Compatible
• Three–State Outputs
• Power Operation: 280/275/270/260 mA Maximum, Active AC
• Commercial Temperature (0°C to 70°C) and
Industrial Temperature (– 40°C to + 85°C) Options
BLOCK DIAGRAM
A
A
, E2, E3) and output enable
MCM6341
ZP PACKAGE
CASE 999–02
PIN NAMES
A Address Inputs. . . . . . . . . . . . . . . . . . . . . .
W
G
E1
, E2, E3 Chip Enable. . . . . . . . . . . . . . . .
DQ Data Input/Output. . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . . . .
V
DD
V
SS
+ 3.3 V Power Supply. . . . . . . . . . . . .
PBGA
Write Enable. . . . . . . . . . . . . . . . . . . . . . .
Output Enable. . . . . . . . . . . . . . . . . . . . .
Ground. . . . . . . . . . . . . . . . . . . . . . . . .
DQ
DQ
E1
E2
E3
W
A
A
A
A
A
A
A
G
ROW
DECODER
INPUT
DATA
CONTROL
MEMORY MATRIX
COLUMN I/O
COLUMN DECODER
AAAAAAAA
DQ
DQ
This document contains information on a new product. Specifications and information herein are subject to change without notice.
REV 2
2/18/98
Motorola, Inc. 1998
MOTOROLA FAST SRAM
MCM6341
1
PIN ASSIGNMENT
6543217
A
NC NC
AA AA
B
NC A A E1
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
NC
DQ
DQ VDDVSSV
V
DQ
SS
DQ VDDV
V
DQ
SS
V
DQ
DD
V
V
SS
DD
V
DQ V
DD
DQ
V
SS
V
DQ V
DD
DQ
V
SS
V
DQ V
DD
DQ
NC NC
NC
AA AA
NC NC
A
E2 NC E3
SS
V
V
SS
DD
V
SS
SS
V
V
SS
DD
V
V
SS
SS
V
V
SS
DD
V
SS
SS
V
V
SS
DD
V
SS
SS
V
V
SS
DD
V
SS
SS
NC
W
AA
G
A
A
NC
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
V
V
SS
DD
V
V
DD
SS
V
V
SS
DD
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
NCNC
A
A
V
NC
DQ
DQ
DQ
DQ
DQ
DQ
DD
DQ
DQ
DQ
DQ
DQ
DQ
NC
119–BUMP PBGA
TOP VIEW
MCM6341
2
MOTOROLA FAST SRAM
TRUTH TABLE (X = Don’t Care)
E1 E2 E3 G W Mode I/O Pin Cycle Current
H X X X X Not Selected High–Z — I
X L X X X Not Selected High–Z — I
X X H X X Not Selected High–Z — I
L H L H H Output Disabled High–Z — I
L H L L H Read D
L H L X L Write High–Z Write I
out
Read I
SB1
SB1
SB1
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Power Supply Voltage Relative to V
Voltage Relative to VSS for Any Pin
Except V
Output Current (per I/O) I
Power Dissipation P
Temperature Under Bias Commercial
Storage Temperature — Plastic T
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
DD
exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
SS
Industrial
Symbol Value Unit
V
DD
Vin, V
out
T
bias
stg
out
D
– 0.5 to + 5.0 V
– 0.5 to VDD + 0.5 V
± 20
1.0 W
– 10 to + 85
– 45 to + 90
– 55 to + 150 °C
mA
°C
, I
SB2
, I
SB2
, I
SB2
DDA
DDA
DDA
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields; however, it is advised
that normal precautions be taken to avoid application of any voltage higher than maximum
rated voltages to these high–impedance circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
MOTOROLA FAST SRAM
MCM6341
3
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